2 * AMD 10Gb Ethernet driver
4 * Copyright (c) 2014-2016,2020 Advanced Micro Devices, Inc.
6 * This file is available to you under your choice of the following two
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
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60 * modification, are permitted provided that the following conditions are met:
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73 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
74 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
75 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
76 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
77 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
81 * This file incorporates work covered by the following copyright and
83 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
84 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
85 * Inc. unless otherwise expressly agreed to in writing between Synopsys
88 * The Software IS NOT an item of Licensed Software or Licensed Product
89 * under any End User Software License Agreement or Agreement for Licensed
90 * Product with Synopsys or any supplement thereto. Permission is hereby
91 * granted, free of charge, to any person obtaining a copy of this software
92 * annotated with this license and the Software, to deal in the Software
93 * without restriction, including without limitation the rights to use,
94 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
95 * of the Software, and to permit persons to whom the Software is furnished
96 * to do so, subject to the following conditions:
98 * The above copyright notice and this permission notice shall be included
99 * in all copies or substantial portions of the Software.
101 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
102 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
103 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
104 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
105 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
106 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
107 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
108 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
109 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
110 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
111 * THE POSSIBILITY OF SUCH DAMAGE.
119 #include <sys/param.h>
120 #include <sys/kernel.h>
122 #include <sys/socket.h>
123 #include <sys/bitstring.h>
126 #include <net/if_media.h>
128 #include <dev/mii/mii.h>
129 #include <dev/mii/miivar.h>
131 #include "xgbe_osdep.h"
133 /* From linux/dcbnl.h */
134 #define IEEE_8021QAZ_MAX_TCS 8
136 #define XGBE_DRV_NAME "amd-xgbe"
137 #define XGBE_DRV_VERSION "1.0.3"
138 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver"
140 /* Descriptor related defines */
141 #define XGBE_TX_DESC_CNT 512
142 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3)
143 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1)
144 #define XGBE_RX_DESC_CNT 512
146 #define XGBE_TX_DESC_CNT_MIN 64
147 #define XGBE_TX_DESC_CNT_MAX 4096
148 #define XGBE_RX_DESC_CNT_MIN 64
149 #define XGBE_RX_DESC_CNT_MAX 4096
150 #define XGBE_TX_DESC_CNT_DEFAULT 512
151 #define XGBE_RX_DESC_CNT_DEFAULT 512
153 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
155 /* Descriptors required for maximum contiguous TSO/GSO packet */
156 #define XGBE_TX_MAX_SPLIT ((GSO_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1)
158 /* Maximum possible descriptors needed for an SKB:
159 * - Maximum number of SKB frags
160 * - Maximum descriptors for contiguous TSO/GSO packet
161 * - Possible context descriptor
162 * - Possible TSO header descriptor
164 #define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2)
166 #define XGBE_RX_MIN_BUF_SIZE 1522
167 #define XGBE_RX_BUF_ALIGN 64
168 #define XGBE_SKB_ALLOC_SIZE 256
169 #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZ */
171 #define XGBE_MAX_DMA_CHANNELS 16
172 #define XGBE_MAX_QUEUES 16
173 #define XGBE_PRIORITY_QUEUES 8
174 #define XGBE_DMA_STOP_TIMEOUT 5
176 /* DMA cache settings - Outer sharable, write-back, write-allocate */
177 #define XGBE_DMA_OS_ARCR 0x002b2b2b
178 #define XGBE_DMA_OS_AWCR 0x2f2f2f2f
180 /* DMA cache settings - System, no caches used */
181 #define XGBE_DMA_SYS_ARCR 0x00303030
182 #define XGBE_DMA_SYS_AWCR 0x30303030
184 /* DMA cache settings - PCI device */
185 #define XGBE_DMA_PCI_ARCR 0x00000003
186 #define XGBE_DMA_PCI_AWCR 0x13131313
187 #define XGBE_DMA_PCI_AWARCR 0x00000313
189 /* DMA channel interrupt modes */
190 #define XGBE_IRQ_MODE_EDGE 0
191 #define XGBE_IRQ_MODE_LEVEL 1
193 #define XGMAC_MIN_PACKET 60
194 #define XGMAC_STD_PACKET_MTU 1500
195 #define XGMAC_MAX_STD_PACKET 1518
196 #define XGMAC_JUMBO_PACKET_MTU 9000
197 #define XGMAC_MAX_JUMBO_PACKET 9018
198 #define XGMAC_ETH_PREAMBLE (12 + 8) /* Inter-frame gap + preamble */
200 #define XGMAC_PFC_DATA_LEN 46
201 #define XGMAC_PFC_DELAYS 14000
203 #define XGMAC_PRIO_QUEUES(_cnt) \
204 min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, (_cnt))
206 /* Common property names */
207 #define XGBE_MAC_ADDR_PROPERTY "mac-address"
208 #define XGBE_PHY_MODE_PROPERTY "phy-mode"
209 #define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt"
210 #define XGBE_SPEEDSET_PROPERTY "amd,speed-set"
211 #define XGBE_BLWC_PROPERTY "amd,serdes-blwc"
212 #define XGBE_CDR_RATE_PROPERTY "amd,serdes-cdr-rate"
213 #define XGBE_PQ_SKEW_PROPERTY "amd,serdes-pq-skew"
214 #define XGBE_TX_AMP_PROPERTY "amd,serdes-tx-amp"
215 #define XGBE_DFE_CFG_PROPERTY "amd,serdes-dfe-tap-config"
216 #define XGBE_DFE_ENA_PROPERTY "amd,serdes-dfe-tap-enable"
218 /* Device-tree clock names */
219 #define XGBE_DMA_CLOCK "dma_clk"
220 #define XGBE_PTP_CLOCK "ptp_clk"
222 /* ACPI property names */
223 #define XGBE_ACPI_DMA_FREQ "amd,dma-freq"
224 #define XGBE_ACPI_PTP_FREQ "amd,ptp-freq"
226 /* PCI BAR mapping */
227 #define XGBE_XGMAC_BAR 0
228 #define XGBE_XPCS_BAR 1
229 #define XGBE_MAC_PROP_OFFSET 0x1d000
230 #define XGBE_I2C_CTRL_OFFSET 0x1e000
232 /* PCI MSI/MSIx support */
233 #define XGBE_MSI_BASE_COUNT 4
234 #define XGBE_MSI_MIN_COUNT (XGBE_MSI_BASE_COUNT + 1)
236 /* PCI clock frequencies */
237 #define XGBE_V2_DMA_CLOCK_FREQ 500000000 /* 500 MHz */
238 #define XGBE_V2_PTP_CLOCK_FREQ 125000000 /* 125 MHz */
240 /* Timestamp support - values based on 50MHz PTP clock
243 #define XGBE_TSTAMP_SSINC 20
244 #define XGBE_TSTAMP_SNSINC 0
246 /* Driver PMT macros */
247 #define XGMAC_DRIVER_CONTEXT 1
248 #define XGMAC_IOCTL_CONTEXT 2
250 #define XGMAC_FIFO_MIN_ALLOC 2048
251 #define XGMAC_FIFO_UNIT 256
252 #define XGMAC_FIFO_ALIGN(_x) \
253 (((_x) + XGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1))
254 #define XGMAC_FIFO_FC_OFF 2048
255 #define XGMAC_FIFO_FC_MIN 4096
256 #define XGBE_FIFO_MAX 81920
258 #define XGBE_TC_MIN_QUANTUM 10
260 /* Helper macro for descriptor handling
261 * Always use XGBE_GET_DESC_DATA to access the descriptor data
262 * since the index is free-running and needs to be and-ed
263 * with the descriptor count value of the ring to index to
264 * the proper descriptor data.
266 #define XGBE_GET_DESC_DATA(_ring, _idx) \
268 ((_idx) & ((_ring)->rdesc_count - 1)))
270 /* Default coalescing parameters */
271 #define XGMAC_INIT_DMA_TX_USECS 1000
272 #define XGMAC_INIT_DMA_TX_FRAMES 25
274 #define XGMAC_MAX_DMA_RIWT 0xff
275 #define XGMAC_INIT_DMA_RX_USECS 30
276 #define XGMAC_INIT_DMA_RX_FRAMES 25
278 /* Flow control queue count */
279 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8
281 /* Flow control threshold units */
282 #define XGMAC_FLOW_CONTROL_UNIT 512
283 #define XGMAC_FLOW_CONTROL_ALIGN(_x) \
284 (((_x) + XGMAC_FLOW_CONTROL_UNIT - 1) & ~(XGMAC_FLOW_CONTROL_UNIT - 1))
285 #define XGMAC_FLOW_CONTROL_VALUE(_x) \
286 (((_x) < 1024) ? 0 : ((_x) / XGMAC_FLOW_CONTROL_UNIT) - 2)
287 #define XGMAC_FLOW_CONTROL_MAX 33280
289 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
290 #define XGBE_MAC_HASH_TABLE_SIZE 8
292 /* Receive Side Scaling */
293 #define XGBE_RSS_HASH_KEY_SIZE 40
294 #define XGBE_RSS_MAX_TABLE_SIZE 256
295 #define XGBE_RSS_LOOKUP_TABLE_TYPE 0
296 #define XGBE_RSS_HASH_KEY_TYPE 1
298 /* Auto-negotiation */
299 #define XGBE_AN_MS_TIMEOUT 500
300 #define XGBE_LINK_TIMEOUT 10
302 #define XGBE_SGMII_AN_LINK_STATUS BIT(1)
303 #define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3))
304 #define XGBE_SGMII_AN_LINK_SPEED_100 0x04
305 #define XGBE_SGMII_AN_LINK_SPEED_1000 0x08
306 #define XGBE_SGMII_AN_LINK_DUPLEX BIT(4)
308 /* ECC correctable error notification window (seconds) */
309 #define XGBE_ECC_LIMIT 60
311 #define XGBE_AN_INT_CMPLT 0x01
312 #define XGBE_AN_INC_LINK 0x02
313 #define XGBE_AN_PG_RCV 0x04
314 #define XGBE_AN_INT_MASK 0x07
316 #define XGBE_SGMII_AN_LINK_STATUS BIT(1)
317 #define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3))
318 #define XGBE_SGMII_AN_LINK_SPEED_100 0x04
319 #define XGBE_SGMII_AN_LINK_SPEED_1000 0x08
320 #define XGBE_SGMII_AN_LINK_DUPLEX BIT(4)
322 /* Rate-change complete wait/retry count */
323 #define XGBE_RATECHANGE_COUNT 500
325 /* Default SerDes settings */
326 #define XGBE_SPEED_10000_BLWC 0
327 #define XGBE_SPEED_10000_CDR 0x7
328 #define XGBE_SPEED_10000_PLL 0x1
329 #define XGBE_SPEED_10000_PQ 0x12
330 #define XGBE_SPEED_10000_RATE 0x0
331 #define XGBE_SPEED_10000_TXAMP 0xa
332 #define XGBE_SPEED_10000_WORD 0x7
333 #define XGBE_SPEED_10000_DFE_TAP_CONFIG 0x1
334 #define XGBE_SPEED_10000_DFE_TAP_ENABLE 0x7f
336 #define XGBE_SPEED_2500_BLWC 1
337 #define XGBE_SPEED_2500_CDR 0x2
338 #define XGBE_SPEED_2500_PLL 0x0
339 #define XGBE_SPEED_2500_PQ 0xa
340 #define XGBE_SPEED_2500_RATE 0x1
341 #define XGBE_SPEED_2500_TXAMP 0xf
342 #define XGBE_SPEED_2500_WORD 0x1
343 #define XGBE_SPEED_2500_DFE_TAP_CONFIG 0x3
344 #define XGBE_SPEED_2500_DFE_TAP_ENABLE 0x0
346 #define XGBE_SPEED_1000_BLWC 1
347 #define XGBE_SPEED_1000_CDR 0x2
348 #define XGBE_SPEED_1000_PLL 0x0
349 #define XGBE_SPEED_1000_PQ 0xa
350 #define XGBE_SPEED_1000_RATE 0x3
351 #define XGBE_SPEED_1000_TXAMP 0xf
352 #define XGBE_SPEED_1000_WORD 0x1
353 #define XGBE_SPEED_1000_DFE_TAP_CONFIG 0x3
354 #define XGBE_SPEED_1000_DFE_TAP_ENABLE 0x0
356 /* TSO related macros */
357 #define XGBE_TSO_MAX_SIZE UINT16_MAX
359 /* MDIO port types */
360 #define XGMAC_MAX_C22_PORT 3
362 /* Link mode bit operations */
363 #define XGBE_ZERO_SUP(_phy) \
364 ((_phy)->supported = 0)
366 #define XGBE_SET_SUP(_phy, _mode) \
367 ((_phy)->supported |= SUPPORTED_##_mode)
369 #define XGBE_CLR_SUP(_phy, _mode) \
370 ((_phy)->supported &= ~SUPPORTED_##_mode)
372 #define XGBE_IS_SUP(_phy, _mode) \
373 ((_phy)->supported & SUPPORTED_##_mode)
375 #define XGBE_ZERO_ADV(_phy) \
376 ((_phy)->advertising = 0)
378 #define XGBE_SET_ADV(_phy, _mode) \
379 ((_phy)->advertising |= ADVERTISED_##_mode)
381 #define XGBE_CLR_ADV(_phy, _mode) \
382 ((_phy)->advertising &= ~ADVERTISED_##_mode)
384 #define XGBE_ADV(_phy, _mode) \
385 ((_phy)->advertising & ADVERTISED_##_mode)
387 #define XGBE_ZERO_LP_ADV(_phy) \
388 ((_phy)->lp_advertising = 0)
390 #define XGBE_SET_LP_ADV(_phy, _mode) \
391 ((_phy)->lp_advertising |= ADVERTISED_##_mode)
393 #define XGBE_CLR_LP_ADV(_phy, _mode) \
394 ((_phy)->lp_advertising &= ~ADVERTISED_##_mode)
396 #define XGBE_LP_ADV(_phy, _mode) \
397 ((_phy)->lp_advertising & ADVERTISED_##_mode)
399 #define XGBE_LM_COPY(_dphy, _dname, _sphy, _sname) \
400 ((_dphy)->_dname = (_sphy)->_sname)
402 struct xgbe_prv_data;
404 struct xgbe_packet_data {
407 unsigned int attributes;
411 unsigned int rdesc_count;
414 unsigned int header_len;
415 unsigned int tcp_header_len;
416 unsigned int tcp_payload_len;
419 unsigned short vlan_ctag;
423 unsigned int tx_packets;
424 unsigned int tx_bytes;
427 uint32_t rss_hash_type;
430 /* Common Rx and Tx descriptor mapping */
431 struct xgbe_ring_desc {
438 /* Tx-related ring data */
439 struct xgbe_tx_ring_data {
440 unsigned int packets; /* BQL packet count */
441 unsigned int bytes; /* BQL byte count */
444 /* Rx-related ring data */
445 struct xgbe_rx_ring_data {
446 unsigned short hdr_len; /* Length of received header */
447 unsigned short len; /* Length of received packet */
450 /* Structure used to hold information related to the descriptor
451 * and the packet associated with the descriptor (always use
452 * use the XGBE_GET_DESC_DATA macro to access this data from the ring)
454 struct xgbe_ring_data {
455 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */
456 bus_addr_t rdata_paddr;
458 struct xgbe_tx_ring_data tx; /* Tx-related data */
459 struct xgbe_rx_ring_data rx; /* Rx-related data */
462 /* Incomplete receive save location. If the budget is exhausted
463 * or the last descriptor (last normal descriptor or a following
464 * context descriptor) has not been DMA'd yet the current state
465 * of the receive processing needs to be saved.
467 unsigned int state_saved;
477 /* Ring lock - used just for TX rings at the moment */
480 /* Per packet related information */
481 struct xgbe_packet_data packet_data;
483 /* Virtual/DMA addresses and count of allocated descriptor memory */
484 struct xgbe_ring_desc *rdesc;
485 bus_addr_t rdesc_paddr;
486 unsigned int rdesc_count;
488 /* Array of descriptor data corresponding the descriptor memory
489 * (always use the XGBE_GET_DESC_DATA macro to access this data)
491 struct xgbe_ring_data *rdata;
494 * cur - Tx: index of descriptor to be used for current transfer
495 * Rx: index of descriptor to check for packet availability
496 * dirty - Tx: index of descriptor to check for transfer complete
497 * Rx: index of descriptor to check for buffer reallocation
502 /* Coalesce frame count used for interrupt bit setting */
503 unsigned int coalesce_count;
507 unsigned int queue_stopped;
508 unsigned int xmit_more;
509 unsigned short cur_mss;
510 unsigned short cur_vlan_ctag;
517 } __aligned(CACHE_LINE_SIZE);
519 /* Structure used to describe the descriptor rings associated with
522 struct xgbe_channel {
525 /* Address of private data area for device */
526 struct xgbe_prv_data *pdata;
528 /* Queue index and base address of queue's DMA registers */
529 unsigned int queue_index;
530 bus_space_tag_t dma_tag;
531 bus_space_handle_t dma_handle;
534 /* Per channel interrupt irq number */
535 struct resource *dma_irq_res;
538 /* Per channel interrupt enablement tracker */
539 unsigned int curr_ier;
540 unsigned int saved_ier;
542 struct xgbe_ring *tx_ring;
543 struct xgbe_ring *rx_ring;
544 } __aligned(CACHE_LINE_SIZE);
554 XGMAC_INT_DMA_CH_SR_TI,
555 XGMAC_INT_DMA_CH_SR_TPS,
556 XGMAC_INT_DMA_CH_SR_TBU,
557 XGMAC_INT_DMA_CH_SR_RI,
558 XGMAC_INT_DMA_CH_SR_RBU,
559 XGMAC_INT_DMA_CH_SR_RPS,
560 XGMAC_INT_DMA_CH_SR_TI_RI,
561 XGMAC_INT_DMA_CH_SR_FBE,
565 enum xgbe_int_state {
566 XGMAC_INT_STATE_SAVE,
567 XGMAC_INT_STATE_RESTORE,
583 enum xgbe_xpcs_access {
584 XGBE_XPCS_ACCESS_V1 = 0,
589 XGBE_AN_MODE_CL73 = 0,
590 XGBE_AN_MODE_CL73_REDRV,
592 XGBE_AN_MODE_CL37_SGMII,
598 XGBE_AN_PAGE_RECEIVED,
599 XGBE_AN_INCOMPAT_LINK,
619 XGBE_MODE_SGMII_1000,
625 XGBE_SPEEDSET_1000_10000 = 0,
626 XGBE_SPEEDSET_2500_10000,
629 enum xgbe_mdio_mode {
630 XGBE_MDIO_MODE_NONE = 0,
637 uint32_t advertising;
638 uint32_t lp_advertising;
657 XGBE_I2C_CMD_READ = 0,
662 enum xgbe_i2c_cmd cmd;
670 struct xgbe_i2c_op_state {
671 struct xgbe_i2c_op *op;
674 unsigned char *tx_buf;
677 unsigned char *rx_buf;
679 unsigned int tx_abort_source;
685 unsigned int started;
686 unsigned int max_speed_mode;
687 unsigned int rx_fifo_size;
688 unsigned int tx_fifo_size;
690 struct xgbe_i2c_op_state op_state;
693 struct xgbe_mmc_stats {
695 uint64_t txoctetcount_gb;
696 uint64_t txframecount_gb;
697 uint64_t txbroadcastframes_g;
698 uint64_t txmulticastframes_g;
699 uint64_t tx64octets_gb;
700 uint64_t tx65to127octets_gb;
701 uint64_t tx128to255octets_gb;
702 uint64_t tx256to511octets_gb;
703 uint64_t tx512to1023octets_gb;
704 uint64_t tx1024tomaxoctets_gb;
705 uint64_t txunicastframes_gb;
706 uint64_t txmulticastframes_gb;
707 uint64_t txbroadcastframes_gb;
708 uint64_t txunderflowerror;
709 uint64_t txoctetcount_g;
710 uint64_t txframecount_g;
711 uint64_t txpauseframes;
712 uint64_t txvlanframes_g;
715 uint64_t rxframecount_gb;
716 uint64_t rxoctetcount_gb;
717 uint64_t rxoctetcount_g;
718 uint64_t rxbroadcastframes_g;
719 uint64_t rxmulticastframes_g;
721 uint64_t rxrunterror;
722 uint64_t rxjabbererror;
723 uint64_t rxundersize_g;
724 uint64_t rxoversize_g;
725 uint64_t rx64octets_gb;
726 uint64_t rx65to127octets_gb;
727 uint64_t rx128to255octets_gb;
728 uint64_t rx256to511octets_gb;
729 uint64_t rx512to1023octets_gb;
730 uint64_t rx1024tomaxoctets_gb;
731 uint64_t rxunicastframes_g;
732 uint64_t rxlengtherror;
733 uint64_t rxoutofrangetype;
734 uint64_t rxpauseframes;
735 uint64_t rxfifooverflow;
736 uint64_t rxvlanframes_gb;
737 uint64_t rxwatchdogerror;
740 struct xgbe_ext_stats {
741 uint64_t tx_tso_packets;
742 uint64_t rx_split_header_packets;
743 uint64_t rx_buffer_unavailable;
745 uint64_t txq_packets[XGBE_MAX_DMA_CHANNELS];
746 uint64_t txq_bytes[XGBE_MAX_DMA_CHANNELS];
747 uint64_t rxq_packets[XGBE_MAX_DMA_CHANNELS];
748 uint64_t rxq_bytes[XGBE_MAX_DMA_CHANNELS];
750 uint64_t tx_vxlan_packets;
751 uint64_t rx_vxlan_packets;
752 uint64_t rx_csum_errors;
753 uint64_t rx_vxlan_csum_errors;
757 int (*tx_complete)(struct xgbe_ring_desc *);
759 int (*set_mac_address)(struct xgbe_prv_data *, uint8_t *addr);
760 int (*config_rx_mode)(struct xgbe_prv_data *);
762 int (*enable_rx_csum)(struct xgbe_prv_data *);
763 int (*disable_rx_csum)(struct xgbe_prv_data *);
765 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
766 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
767 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
768 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
769 int (*update_vlan_hash_table)(struct xgbe_prv_data *);
771 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
772 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
773 int (*set_speed)(struct xgbe_prv_data *, int);
775 int (*set_ext_mii_mode)(struct xgbe_prv_data *, unsigned int,
776 enum xgbe_mdio_mode);
777 int (*read_ext_mii_regs)(struct xgbe_prv_data *, int, int);
778 int (*write_ext_mii_regs)(struct xgbe_prv_data *, int, int, uint16_t);
780 int (*set_gpio)(struct xgbe_prv_data *, unsigned int);
781 int (*clr_gpio)(struct xgbe_prv_data *, unsigned int);
783 void (*enable_tx)(struct xgbe_prv_data *);
784 void (*disable_tx)(struct xgbe_prv_data *);
785 void (*enable_rx)(struct xgbe_prv_data *);
786 void (*disable_rx)(struct xgbe_prv_data *);
788 void (*powerup_tx)(struct xgbe_prv_data *);
789 void (*powerdown_tx)(struct xgbe_prv_data *);
790 void (*powerup_rx)(struct xgbe_prv_data *);
791 void (*powerdown_rx)(struct xgbe_prv_data *);
793 int (*init)(struct xgbe_prv_data *);
794 int (*exit)(struct xgbe_prv_data *);
796 int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
797 int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
798 int (*dev_read)(struct xgbe_channel *);
799 void (*tx_desc_init)(struct xgbe_channel *);
800 void (*rx_desc_init)(struct xgbe_channel *);
801 void (*tx_desc_reset)(struct xgbe_ring_data *);
802 int (*is_last_desc)(struct xgbe_ring_desc *);
803 int (*is_context_desc)(struct xgbe_ring_desc *);
806 int (*config_tx_flow_control)(struct xgbe_prv_data *);
807 int (*config_rx_flow_control)(struct xgbe_prv_data *);
809 /* For RX coalescing */
810 int (*config_rx_coalesce)(struct xgbe_prv_data *);
811 int (*config_tx_coalesce)(struct xgbe_prv_data *);
812 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
813 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
815 /* For RX and TX threshold config */
816 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
817 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
819 /* For RX and TX Store and Forward Mode config */
820 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
821 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
823 /* For TX DMA Operate on Second Frame config */
824 int (*config_osp_mode)(struct xgbe_prv_data *);
826 /* For MMC statistics */
827 void (*rx_mmc_int)(struct xgbe_prv_data *);
828 void (*tx_mmc_int)(struct xgbe_prv_data *);
829 void (*read_mmc_stats)(struct xgbe_prv_data *);
831 /* For Receive Side Scaling */
832 int (*enable_rss)(struct xgbe_prv_data *);
833 int (*disable_rss)(struct xgbe_prv_data *);
834 int (*set_rss_hash_key)(struct xgbe_prv_data *, const uint8_t *);
835 int (*set_rss_lookup_table)(struct xgbe_prv_data *, const uint32_t *);
838 /* This structure represents implementation specific routines for an
839 * implementation of a PHY. All routines are required unless noted below.
842 * kr_training_pre, kr_training_post
843 * module_info, module_eeprom
845 struct xgbe_phy_impl_if {
846 /* Perform Setup/teardown actions */
847 int (*init)(struct xgbe_prv_data *);
848 void (*exit)(struct xgbe_prv_data *);
850 /* Perform start/stop specific actions */
851 int (*reset)(struct xgbe_prv_data *);
852 int (*start)(struct xgbe_prv_data *);
853 void (*stop)(struct xgbe_prv_data *);
855 /* Return the link status */
856 int (*link_status)(struct xgbe_prv_data *, int *);
858 /* Indicate if a particular speed is valid */
859 bool (*valid_speed)(struct xgbe_prv_data *, int);
861 /* Check if the specified mode can/should be used */
862 bool (*use_mode)(struct xgbe_prv_data *, enum xgbe_mode);
863 /* Switch the PHY into various modes */
864 void (*set_mode)(struct xgbe_prv_data *, enum xgbe_mode);
865 /* Retrieve mode needed for a specific speed */
866 enum xgbe_mode (*get_mode)(struct xgbe_prv_data *, int);
867 /* Retrieve new/next mode when trying to auto-negotiate */
868 enum xgbe_mode (*switch_mode)(struct xgbe_prv_data *);
869 /* Retrieve current mode */
870 enum xgbe_mode (*cur_mode)(struct xgbe_prv_data *);
871 /* Retrieve interface sub-type */
872 void (*get_type)(struct xgbe_prv_data *, struct ifmediareq *);
874 /* Retrieve current auto-negotiation mode */
875 enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *);
877 /* Configure auto-negotiation settings */
878 int (*an_config)(struct xgbe_prv_data *);
880 /* Set/override auto-negotiation advertisement settings */
881 void (*an_advertising)(struct xgbe_prv_data *,
884 /* Process results of auto-negotiation */
885 enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *);
887 /* Pre/Post auto-negotiation support */
888 void (*an_pre)(struct xgbe_prv_data *);
889 void (*an_post)(struct xgbe_prv_data *);
891 /* Pre/Post KR training enablement support */
892 void (*kr_training_pre)(struct xgbe_prv_data *);
893 void (*kr_training_post)(struct xgbe_prv_data *);
895 /* SFP module related info */
896 int (*module_info)(struct xgbe_prv_data *pdata);
897 int (*module_eeprom)(struct xgbe_prv_data *pdata);
901 /* For PHY setup/teardown */
902 int (*phy_init)(struct xgbe_prv_data *);
903 void (*phy_exit)(struct xgbe_prv_data *);
905 /* For PHY support when setting device up/down */
906 int (*phy_reset)(struct xgbe_prv_data *);
907 int (*phy_start)(struct xgbe_prv_data *);
908 void (*phy_stop)(struct xgbe_prv_data *);
910 /* For PHY support while device is up */
911 void (*phy_status)(struct xgbe_prv_data *);
912 int (*phy_config_aneg)(struct xgbe_prv_data *);
914 /* For PHY settings validation */
915 bool (*phy_valid_speed)(struct xgbe_prv_data *, int);
917 /* For single interrupt support */
918 void (*an_isr)(struct xgbe_prv_data *);
920 /* PHY implementation specific services */
921 struct xgbe_phy_impl_if phy_impl;
925 /* For initial I2C setup */
926 int (*i2c_init)(struct xgbe_prv_data *);
928 /* For I2C support when setting device up/down */
929 int (*i2c_start)(struct xgbe_prv_data *);
930 void (*i2c_stop)(struct xgbe_prv_data *);
932 /* For performing I2C operations */
933 int (*i2c_xfer)(struct xgbe_prv_data *, struct xgbe_i2c_op *);
935 /* For single interrupt support */
936 void (*i2c_isr)(struct xgbe_prv_data *);
939 struct xgbe_desc_if {
940 int (*alloc_ring_resources)(struct xgbe_prv_data *);
941 void (*free_ring_resources)(struct xgbe_prv_data *);
942 int (*map_tx_skb)(struct xgbe_channel *, struct mbuf *);
943 int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *,
944 struct xgbe_ring_data *);
945 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
946 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
947 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
950 /* This structure contains flags that indicate what hardware features
951 * or configurations are present in the device.
953 struct xgbe_hw_features {
955 unsigned int version;
957 /* HW Feature Register0 */
958 unsigned int gmii; /* 1000 Mbps support */
959 unsigned int vlhash; /* VLAN Hash Filter */
960 unsigned int sma; /* SMA(MDIO) Interface */
961 unsigned int rwk; /* PMT remote wake-up packet */
962 unsigned int mgk; /* PMT magic packet */
963 unsigned int mmc; /* RMON module */
964 unsigned int aoe; /* ARP Offload */
965 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */
966 unsigned int eee; /* Energy Efficient Ethernet */
967 unsigned int tx_coe; /* Tx Checksum Offload */
968 unsigned int rx_coe; /* Rx Checksum Offload */
969 unsigned int addn_mac; /* Additional MAC Addresses */
970 unsigned int ts_src; /* Timestamp Source */
971 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
972 unsigned int vxn; /* VXLAN/NVGRE */
974 /* HW Feature Register1 */
975 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
976 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
977 unsigned int adv_ts_hi; /* Advance Timestamping High Word */
978 unsigned int dma_width; /* DMA width */
979 unsigned int dcb; /* DCB Feature */
980 unsigned int sph; /* Split Header Feature */
981 unsigned int tso; /* TCP Segmentation Offload */
982 unsigned int dma_debug; /* DMA Debug Registers */
983 unsigned int rss; /* Receive Side Scaling */
984 unsigned int tc_cnt; /* Number of Traffic Classes */
985 unsigned int hash_table_size; /* Hash Table Size */
986 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
988 /* HW Feature Register2 */
989 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
990 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
991 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
992 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
993 unsigned int pps_out_num; /* Number of PPS outputs */
994 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
997 struct xgbe_version_data {
998 void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *);
999 enum xgbe_xpcs_access xpcs_access;
1000 unsigned int mmc_64bit;
1001 unsigned int tx_max_fifo_size;
1002 unsigned int rx_max_fifo_size;
1003 unsigned int tx_tstamp_workaround;
1004 unsigned int ecc_support;
1005 unsigned int i2c_support;
1006 unsigned int irq_reissue_support;
1007 unsigned int tx_desc_prefetch;
1008 unsigned int rx_desc_prefetch;
1009 unsigned int an_cdr_workaround;
1012 struct xgbe_prv_data {
1013 struct ifnet *netdev;
1015 struct platform_device *pdev;
1016 struct acpi_device *adev;
1019 /* Version related data */
1020 struct xgbe_version_data *vdata;
1022 /* ACPI or DT flag */
1023 unsigned int use_acpi;
1025 /* XGMAC/XPCS related mmio registers */
1026 struct resource *xgmac_res; /* XGMAC CSRs */
1027 struct resource *xpcs_res; /* XPCS MMD registers */
1028 struct resource *rxtx_res; /* SerDes Rx/Tx CSRs */
1029 struct resource *sir0_res; /* SerDes integration registers (1/2) */
1030 struct resource *sir1_res; /* SerDes integration registers (2/2) */
1032 /* Port property registers */
1042 /* XPCS indirect addressing lock */
1043 spinlock_t xpcs_lock;
1044 unsigned int xpcs_window_def_reg;
1045 unsigned int xpcs_window_sel_reg;
1046 unsigned int xpcs_window;
1047 unsigned int xpcs_window_size;
1048 unsigned int xpcs_window_mask;
1050 /* RSS addressing mutex */
1051 struct mtx rss_mutex;
1053 /* Flags representing xgbe_state */
1054 unsigned long dev_state;
1057 unsigned long tx_sec_period;
1058 unsigned long tx_ded_period;
1059 unsigned long rx_sec_period;
1060 unsigned long rx_ded_period;
1061 unsigned long desc_sec_period;
1062 unsigned long desc_ded_period;
1064 unsigned int tx_sec_count;
1065 unsigned int tx_ded_count;
1066 unsigned int rx_sec_count;
1067 unsigned int rx_ded_count;
1068 unsigned int desc_ded_count;
1069 unsigned int desc_sec_count;
1071 struct if_irq dev_irq;
1073 struct resource *dev_irq_res;
1074 struct resource *ecc_irq_res;
1075 struct resource *i2c_irq_res;
1076 struct resource *an_irq_res;
1087 struct resource *chan_irq_res[XGBE_MAX_DMA_CHANNELS];
1089 unsigned int per_channel_irq;
1090 unsigned int irq_count;
1091 unsigned int channel_irq_count;
1092 unsigned int channel_irq_mode;
1094 char ecc_name[IFNAMSIZ + 32];
1096 unsigned int isr_as_tasklet;
1097 struct xgbe_hw_if hw_if;
1098 struct xgbe_phy_if phy_if;
1099 struct xgbe_desc_if desc_if;
1100 struct xgbe_i2c_if i2c_if;
1102 /* AXI DMA settings */
1103 unsigned int coherent;
1106 unsigned int awarcr;
1108 /* Service routine support */
1109 struct taskqueue *dev_workqueue;
1110 struct task service_work;
1111 struct callout service_timer;
1112 struct mtx timer_mutex;
1114 /* Rings for Tx/Rx on a DMA channel */
1115 struct xgbe_channel *channel[XGBE_MAX_DMA_CHANNELS];
1116 unsigned int tx_max_channel_count;
1117 unsigned int rx_max_channel_count;
1118 unsigned int total_channel_count;
1119 unsigned int channel_count;
1120 unsigned int tx_ring_count;
1121 unsigned int tx_desc_count;
1122 unsigned int rx_ring_count;
1123 unsigned int rx_desc_count;
1125 unsigned int new_tx_ring_count;
1126 unsigned int new_rx_ring_count;
1128 unsigned int tx_max_q_count;
1129 unsigned int rx_max_q_count;
1130 unsigned int tx_q_count;
1131 unsigned int rx_q_count;
1133 /* Tx/Rx common settings */
1137 unsigned int rd_osr_limit;
1138 unsigned int wr_osr_limit;
1141 unsigned int tx_sf_mode;
1142 unsigned int tx_threshold;
1143 unsigned int tx_osp_mode;
1144 unsigned int tx_max_fifo_size;
1147 unsigned int rx_sf_mode;
1148 unsigned int rx_threshold;
1149 unsigned int rx_max_fifo_size;
1151 /* Tx coalescing settings */
1152 unsigned int tx_usecs;
1153 unsigned int tx_frames;
1155 /* Rx coalescing settings */
1156 unsigned int rx_riwt;
1157 unsigned int rx_usecs;
1158 unsigned int rx_frames;
1160 /* Current Rx buffer size */
1161 unsigned int rx_buf_size;
1163 /* Flow control settings */
1164 unsigned int pause_autoneg;
1165 unsigned int tx_pause;
1166 unsigned int rx_pause;
1167 unsigned int rx_rfa[XGBE_MAX_QUEUES];
1168 unsigned int rx_rfd[XGBE_MAX_QUEUES];
1170 /* Receive Side Scaling settings */
1171 uint8_t rss_key[XGBE_RSS_HASH_KEY_SIZE];
1172 uint32_t rss_table[XGBE_RSS_MAX_TABLE_SIZE];
1173 uint32_t rss_options;
1174 unsigned int enable_rss;
1176 /* VXLAN settings */
1177 unsigned int vxlan_port_set;
1178 unsigned int vxlan_offloads_set;
1179 unsigned int vxlan_force_disable;
1180 unsigned int vxlan_port_count;
1181 uint16_t vxlan_port;
1182 uint64_t vxlan_features;
1184 /* Netdev related settings */
1185 unsigned char mac_addr[ETH_ALEN];
1186 uint64_t netdev_features;
1187 struct xgbe_mmc_stats mmc_stats;
1188 struct xgbe_ext_stats ext_stats;
1190 /* Filtering support */
1191 bitstr_t *active_vlans;
1192 unsigned int num_active_vlans;
1196 unsigned long sysclk_rate;
1198 unsigned long ptpclk_rate;
1201 unsigned int q2tc_map[XGBE_MAX_QUEUES];
1202 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
1204 /* Hardware features of the device */
1205 struct xgbe_hw_features hw_feat;
1207 /* Device work structure */
1208 struct task restart_work;
1209 struct task stopdev_work;
1211 /* Keeps track of power mode */
1212 unsigned int power_down;
1214 /* Network interface message level setting */
1215 uint32_t msg_enable;
1217 /* Current PHY settings */
1221 /* MDIO/PHY related settings */
1222 unsigned int phy_started;
1224 struct xgbe_phy phy;
1226 unsigned long link_check;
1227 struct mtx mdio_mutex;
1228 unsigned int mdio_addr;
1230 unsigned int kr_redrv;
1232 char an_name[IFNAMSIZ + 32];
1233 struct taskqueue *an_workqueue;
1235 struct task an_irq_work;
1237 unsigned int speed_set;
1239 /* SerDes UEFI configurable settings.
1240 * Switching between modes/speeds requires new values for some
1241 * SerDes settings. The values can be supplied as device
1242 * properties in array format. The first array entry is for
1243 * 1GbE, second for 2.5GbE and third for 10GbE
1245 uint32_t serdes_blwc[XGBE_SPEEDS];
1246 uint32_t serdes_cdr_rate[XGBE_SPEEDS];
1247 uint32_t serdes_pq_skew[XGBE_SPEEDS];
1248 uint32_t serdes_tx_amp[XGBE_SPEEDS];
1249 uint32_t serdes_dfe_tap_cfg[XGBE_SPEEDS];
1250 uint32_t serdes_dfe_tap_ena[XGBE_SPEEDS];
1252 /* Auto-negotiation state machine support */
1253 unsigned int an_int;
1254 unsigned int an_status;
1256 enum xgbe_an an_result;
1257 enum xgbe_an an_state;
1258 enum xgbe_rx kr_state;
1259 enum xgbe_rx kx_state;
1260 struct task an_work;
1261 unsigned int an_again;
1262 unsigned int an_supported;
1263 unsigned int parallel_detect;
1264 unsigned int fec_ability;
1265 unsigned long an_start;
1266 enum xgbe_an_mode an_mode;
1269 struct xgbe_i2c i2c;
1270 struct mtx i2c_mutex;
1273 unsigned int lpm_ctrl; /* CTRL1 for resume */
1274 unsigned int an_cdr_track_early;
1278 device_t axgbe_miibus;
1279 unsigned int sysctl_xgmac_reg;
1280 unsigned int sysctl_xpcs_mmd;
1281 unsigned int sysctl_xpcs_reg;
1283 unsigned int sysctl_xprop_reg;
1284 unsigned int sysctl_xi2c_reg;
1286 bool sysctl_an_cdr_workaround;
1287 bool sysctl_an_cdr_track_early;
1289 int pcie_bus; /* PCIe bus number */
1290 int pcie_device; /* PCIe device/slot number */
1291 int pcie_func; /* PCIe function number */
1294 uint64_t use_adaptive_rx_coalesce;
1295 uint64_t use_adaptive_tx_coalesce;
1296 uint64_t rx_coalesce_usecs;
1298 unsigned int debug_level;
1301 * Toggles the split header feature.
1302 * This requires a complete restart.
1304 unsigned int sph_enable;
1305 unsigned int link_workaround;
1308 struct axgbe_if_softc {
1309 struct xgbe_prv_data pdata;
1310 if_softc_ctx_t scctx;
1311 if_shared_ctx_t sctx;
1314 struct ifmedia *media;
1315 unsigned int link_status;
1318 /* Function prototypes*/
1319 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
1320 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *);
1321 void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *);
1322 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *);
1323 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
1324 void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *);
1325 void xgbe_get_all_hw_features(struct xgbe_prv_data *);
1326 void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
1327 void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
1329 int xgbe_calc_rx_buf_size(struct ifnet *netdev, unsigned int mtu);
1331 void axgbe_sysctl_init(struct xgbe_prv_data *pdata);
1332 void axgbe_sysctl_exit(struct xgbe_prv_data *pdata);
1334 int xgbe_phy_mii_write(struct xgbe_prv_data *pdata, int addr, int reg,
1336 int xgbe_phy_mii_read(struct xgbe_prv_data *pdata, int addr, int reg);
1338 void xgbe_dump_i2c_registers(struct xgbe_prv_data *);
1340 uint32_t bitrev32(uint32_t);
1342 /* For debug prints */
1344 #define DBGPR(x...) device_printf(pdata->dev, x)
1346 #define DBGPR(x...) do { } while (0)
1350 #define DBGPR_MDIO(x...) device_printf(pdata->dev, x)
1352 #define DBGPR_MDIO(x...) do { } while (0)
1355 #define axgbe_printf(lvl, ...) do { \
1356 if (lvl <= pdata->debug_level) \
1357 device_printf(pdata->dev, __VA_ARGS__); \
1360 #define axgbe_error(...) do { \
1361 device_printf(pdata->dev, __VA_ARGS__); \
1364 #endif /* __XGBE_H__ */