2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
122 #include "xgbe_osdep.h"
124 /* From linux/dcbnl.h */
125 #define IEEE_8021QAZ_MAX_TCS 8
127 #define XGBE_DRV_NAME "amd-xgbe"
128 #define XGBE_DRV_VERSION "1.0.2"
129 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver"
131 /* Descriptor related defines */
132 #define XGBE_TX_DESC_CNT 512
133 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3)
134 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1)
135 #define XGBE_RX_DESC_CNT 512
137 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
139 /* Descriptors required for maximum contiguous TSO/GSO packet */
140 #define XGBE_TX_MAX_SPLIT ((GSO_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1)
142 /* Maximum possible descriptors needed for an SKB:
143 * - Maximum number of SKB frags
144 * - Maximum descriptors for contiguous TSO/GSO packet
145 * - Possible context descriptor
146 * - Possible TSO header descriptor
148 #define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2)
150 #define XGBE_RX_MIN_BUF_SIZE 1522
151 #define XGBE_RX_BUF_ALIGN 64
152 #define XGBE_SKB_ALLOC_SIZE 256
153 #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */
155 #define XGBE_MAX_DMA_CHANNELS 16
156 #define XGBE_MAX_QUEUES 16
157 #define XGBE_DMA_STOP_TIMEOUT 5
159 /* DMA cache settings - Outer sharable, write-back, write-allocate */
160 #define XGBE_DMA_OS_AXDOMAIN 0x2
161 #define XGBE_DMA_OS_ARCACHE 0xb
162 #define XGBE_DMA_OS_AWCACHE 0xf
164 /* DMA cache settings - System, no caches used */
165 #define XGBE_DMA_SYS_AXDOMAIN 0x3
166 #define XGBE_DMA_SYS_ARCACHE 0x0
167 #define XGBE_DMA_SYS_AWCACHE 0x0
169 #define XGBE_DMA_INTERRUPT_MASK 0x31c7
171 #define XGMAC_MIN_PACKET 60
172 #define XGMAC_STD_PACKET_MTU 1500
173 #define XGMAC_MAX_STD_PACKET 1518
174 #define XGMAC_JUMBO_PACKET_MTU 9000
175 #define XGMAC_MAX_JUMBO_PACKET 9018
177 /* Common property names */
178 #define XGBE_MAC_ADDR_PROPERTY "mac-address"
179 #define XGBE_PHY_MODE_PROPERTY "phy-mode"
180 #define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt"
181 #define XGBE_SPEEDSET_PROPERTY "amd,speed-set"
182 #define XGBE_BLWC_PROPERTY "amd,serdes-blwc"
183 #define XGBE_CDR_RATE_PROPERTY "amd,serdes-cdr-rate"
184 #define XGBE_PQ_SKEW_PROPERTY "amd,serdes-pq-skew"
185 #define XGBE_TX_AMP_PROPERTY "amd,serdes-tx-amp"
186 #define XGBE_DFE_CFG_PROPERTY "amd,serdes-dfe-tap-config"
187 #define XGBE_DFE_ENA_PROPERTY "amd,serdes-dfe-tap-enable"
189 /* Device-tree clock names */
190 #define XGBE_DMA_CLOCK "dma_clk"
191 #define XGBE_PTP_CLOCK "ptp_clk"
193 /* ACPI property names */
194 #define XGBE_ACPI_DMA_FREQ "amd,dma-freq"
195 #define XGBE_ACPI_PTP_FREQ "amd,ptp-freq"
197 /* Timestamp support - values based on 50MHz PTP clock
200 #define XGBE_TSTAMP_SSINC 20
201 #define XGBE_TSTAMP_SNSINC 0
203 /* Driver PMT macros */
204 #define XGMAC_DRIVER_CONTEXT 1
205 #define XGMAC_IOCTL_CONTEXT 2
207 #define XGBE_FIFO_MAX 81920
209 #define XGBE_TC_MIN_QUANTUM 10
211 /* Helper macro for descriptor handling
212 * Always use XGBE_GET_DESC_DATA to access the descriptor data
213 * since the index is free-running and needs to be and-ed
214 * with the descriptor count value of the ring to index to
215 * the proper descriptor data.
217 #define XGBE_GET_DESC_DATA(_ring, _idx) \
219 ((_idx) & ((_ring)->rdesc_count - 1)))
221 /* Default coalescing parameters */
222 #define XGMAC_INIT_DMA_TX_USECS 1000
223 #define XGMAC_INIT_DMA_TX_FRAMES 25
225 #define XGMAC_MAX_DMA_RIWT 0xff
226 #define XGMAC_INIT_DMA_RX_USECS 30
227 #define XGMAC_INIT_DMA_RX_FRAMES 25
229 /* Flow control queue count */
230 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8
232 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
233 #define XGBE_MAC_HASH_TABLE_SIZE 8
235 /* Receive Side Scaling */
236 #define XGBE_RSS_HASH_KEY_SIZE 40
237 #define XGBE_RSS_MAX_TABLE_SIZE 256
238 #define XGBE_RSS_LOOKUP_TABLE_TYPE 0
239 #define XGBE_RSS_HASH_KEY_TYPE 1
241 /* Auto-negotiation */
242 #define XGBE_AN_MS_TIMEOUT 500
243 #define XGBE_LINK_TIMEOUT 10
245 #define XGBE_AN_INT_CMPLT 0x01
246 #define XGBE_AN_INC_LINK 0x02
247 #define XGBE_AN_PG_RCV 0x04
248 #define XGBE_AN_INT_MASK 0x07
250 /* Rate-change complete wait/retry count */
251 #define XGBE_RATECHANGE_COUNT 500
253 /* Default SerDes settings */
254 #define XGBE_SPEED_10000_BLWC 0
255 #define XGBE_SPEED_10000_CDR 0x7
256 #define XGBE_SPEED_10000_PLL 0x1
257 #define XGBE_SPEED_10000_PQ 0x12
258 #define XGBE_SPEED_10000_RATE 0x0
259 #define XGBE_SPEED_10000_TXAMP 0xa
260 #define XGBE_SPEED_10000_WORD 0x7
261 #define XGBE_SPEED_10000_DFE_TAP_CONFIG 0x1
262 #define XGBE_SPEED_10000_DFE_TAP_ENABLE 0x7f
264 #define XGBE_SPEED_2500_BLWC 1
265 #define XGBE_SPEED_2500_CDR 0x2
266 #define XGBE_SPEED_2500_PLL 0x0
267 #define XGBE_SPEED_2500_PQ 0xa
268 #define XGBE_SPEED_2500_RATE 0x1
269 #define XGBE_SPEED_2500_TXAMP 0xf
270 #define XGBE_SPEED_2500_WORD 0x1
271 #define XGBE_SPEED_2500_DFE_TAP_CONFIG 0x3
272 #define XGBE_SPEED_2500_DFE_TAP_ENABLE 0x0
274 #define XGBE_SPEED_1000_BLWC 1
275 #define XGBE_SPEED_1000_CDR 0x2
276 #define XGBE_SPEED_1000_PLL 0x0
277 #define XGBE_SPEED_1000_PQ 0xa
278 #define XGBE_SPEED_1000_RATE 0x3
279 #define XGBE_SPEED_1000_TXAMP 0xf
280 #define XGBE_SPEED_1000_WORD 0x1
281 #define XGBE_SPEED_1000_DFE_TAP_CONFIG 0x3
282 #define XGBE_SPEED_1000_DFE_TAP_ENABLE 0x0
284 struct xgbe_prv_data;
286 struct xgbe_packet_data {
289 unsigned int attributes;
293 unsigned int rdesc_count;
298 unsigned int tx_packets;
299 unsigned int tx_bytes;
302 /* Common Rx and Tx descriptor mapping */
303 struct xgbe_ring_desc {
310 /* Tx-related ring data */
311 struct xgbe_tx_ring_data {
312 unsigned int packets; /* BQL packet count */
313 unsigned int bytes; /* BQL byte count */
316 /* Rx-related ring data */
317 struct xgbe_rx_ring_data {
318 unsigned short hdr_len; /* Length of received header */
319 unsigned short len; /* Length of received packet */
322 /* Structure used to hold information related to the descriptor
323 * and the packet associated with the descriptor (always use
324 * use the XGBE_GET_DESC_DATA macro to access this data from the ring)
326 struct xgbe_ring_data {
327 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */
328 bus_addr_t rdata_paddr;
330 bus_dma_tag_t mbuf_dmat;
331 bus_dmamap_t mbuf_map;
332 bus_addr_t mbuf_hdr_paddr;
333 bus_addr_t mbuf_data_paddr;
339 struct xgbe_tx_ring_data tx; /* Tx-related data */
340 struct xgbe_rx_ring_data rx; /* Rx-related data */
344 /* Ring lock - used just for TX rings at the moment */
347 /* Per packet related information */
348 struct xgbe_packet_data packet_data;
350 /* Virtual/DMA addresses and count of allocated descriptor memory */
351 struct xgbe_ring_desc *rdesc;
352 bus_dmamap_t rdesc_map;
353 bus_dma_tag_t rdesc_dmat;
354 bus_addr_t rdesc_paddr;
355 unsigned int rdesc_count;
357 bus_dma_tag_t mbuf_dmat;
358 bus_dmamap_t mbuf_map;
360 /* Array of descriptor data corresponding the descriptor memory
361 * (always use the XGBE_GET_DESC_DATA macro to access this data)
363 struct xgbe_ring_data *rdata;
366 * cur - Tx: index of descriptor to be used for current transfer
367 * Rx: index of descriptor to check for packet availability
368 * dirty - Tx: index of descriptor to check for transfer complete
369 * Rx: index of descriptor to check for buffer reallocation
374 /* Coalesce frame count used for interrupt bit setting */
375 unsigned int coalesce_count;
379 unsigned int queue_stopped;
380 unsigned int xmit_more;
381 unsigned short cur_mss;
382 unsigned short cur_vlan_ctag;
385 } __aligned(CACHE_LINE_SIZE);
387 /* Structure used to describe the descriptor rings associated with
390 struct xgbe_channel {
393 /* Address of private data area for device */
394 struct xgbe_prv_data *pdata;
396 /* Queue index and base address of queue's DMA registers */
397 unsigned int queue_index;
398 bus_space_tag_t dma_tag;
399 bus_space_handle_t dma_handle;
401 /* Per channel interrupt irq number */
402 struct resource *dma_irq_res;
405 unsigned int saved_ier;
407 struct xgbe_ring *tx_ring;
408 struct xgbe_ring *rx_ring;
409 } __aligned(CACHE_LINE_SIZE);
418 XGMAC_INT_DMA_CH_SR_TI,
419 XGMAC_INT_DMA_CH_SR_TPS,
420 XGMAC_INT_DMA_CH_SR_TBU,
421 XGMAC_INT_DMA_CH_SR_RI,
422 XGMAC_INT_DMA_CH_SR_RBU,
423 XGMAC_INT_DMA_CH_SR_RPS,
424 XGMAC_INT_DMA_CH_SR_TI_RI,
425 XGMAC_INT_DMA_CH_SR_FBE,
429 enum xgbe_int_state {
430 XGMAC_INT_STATE_SAVE,
431 XGMAC_INT_STATE_RESTORE,
443 XGBE_AN_PAGE_RECEIVED,
444 XGBE_AN_INCOMPAT_LINK,
463 XGBE_SPEEDSET_1000_10000 = 0,
464 XGBE_SPEEDSET_2500_10000,
485 struct xgbe_mmc_stats {
489 u64 txbroadcastframes_g;
490 u64 txmulticastframes_g;
492 u64 tx65to127octets_gb;
493 u64 tx128to255octets_gb;
494 u64 tx256to511octets_gb;
495 u64 tx512to1023octets_gb;
496 u64 tx1024tomaxoctets_gb;
497 u64 txunicastframes_gb;
498 u64 txmulticastframes_gb;
499 u64 txbroadcastframes_gb;
500 u64 txunderflowerror;
510 u64 rxbroadcastframes_g;
511 u64 rxmulticastframes_g;
518 u64 rx65to127octets_gb;
519 u64 rx128to255octets_gb;
520 u64 rx256to511octets_gb;
521 u64 rx512to1023octets_gb;
522 u64 rx1024tomaxoctets_gb;
523 u64 rxunicastframes_g;
525 u64 rxoutofrangetype;
532 struct xgbe_ext_stats {
534 u64 rx_split_header_packets;
535 u64 rx_buffer_unavailable;
539 int (*tx_complete)(struct xgbe_ring_desc *);
541 int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr);
542 int (*config_rx_mode)(struct xgbe_prv_data *);
544 int (*enable_rx_csum)(struct xgbe_prv_data *);
545 int (*disable_rx_csum)(struct xgbe_prv_data *);
547 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
548 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
549 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
550 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
551 int (*update_vlan_hash_table)(struct xgbe_prv_data *);
553 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
554 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
555 int (*set_gmii_speed)(struct xgbe_prv_data *);
556 int (*set_gmii_2500_speed)(struct xgbe_prv_data *);
557 int (*set_xgmii_speed)(struct xgbe_prv_data *);
559 void (*enable_tx)(struct xgbe_prv_data *);
560 void (*disable_tx)(struct xgbe_prv_data *);
561 void (*enable_rx)(struct xgbe_prv_data *);
562 void (*disable_rx)(struct xgbe_prv_data *);
564 void (*powerup_tx)(struct xgbe_prv_data *);
565 void (*powerdown_tx)(struct xgbe_prv_data *);
566 void (*powerup_rx)(struct xgbe_prv_data *);
567 void (*powerdown_rx)(struct xgbe_prv_data *);
569 int (*init)(struct xgbe_prv_data *);
570 int (*exit)(struct xgbe_prv_data *);
572 int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
573 int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
574 void (*dev_xmit)(struct xgbe_channel *);
575 int (*dev_read)(struct xgbe_channel *);
576 void (*tx_desc_init)(struct xgbe_channel *);
577 void (*rx_desc_init)(struct xgbe_channel *);
578 void (*tx_desc_reset)(struct xgbe_ring_data *);
579 void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *,
581 int (*is_last_desc)(struct xgbe_ring_desc *);
582 int (*is_context_desc)(struct xgbe_ring_desc *);
583 void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *);
586 int (*config_tx_flow_control)(struct xgbe_prv_data *);
587 int (*config_rx_flow_control)(struct xgbe_prv_data *);
589 /* For RX coalescing */
590 int (*config_rx_coalesce)(struct xgbe_prv_data *);
591 int (*config_tx_coalesce)(struct xgbe_prv_data *);
592 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
593 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
595 /* For RX and TX threshold config */
596 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
597 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
599 /* For RX and TX Store and Forward Mode config */
600 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
601 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
603 /* For TX DMA Operate on Second Frame config */
604 int (*config_osp_mode)(struct xgbe_prv_data *);
606 /* For RX and TX PBL config */
607 int (*config_rx_pbl_val)(struct xgbe_prv_data *);
608 int (*get_rx_pbl_val)(struct xgbe_prv_data *);
609 int (*config_tx_pbl_val)(struct xgbe_prv_data *);
610 int (*get_tx_pbl_val)(struct xgbe_prv_data *);
611 int (*config_pblx8)(struct xgbe_prv_data *);
613 /* For MMC statistics */
614 void (*rx_mmc_int)(struct xgbe_prv_data *);
615 void (*tx_mmc_int)(struct xgbe_prv_data *);
616 void (*read_mmc_stats)(struct xgbe_prv_data *);
618 /* For Receive Side Scaling */
619 int (*disable_rss)(struct xgbe_prv_data *);
623 /* For initial PHY setup */
624 void (*phy_init)(struct xgbe_prv_data *);
626 /* For PHY support when setting device up/down */
627 int (*phy_reset)(struct xgbe_prv_data *);
628 int (*phy_start)(struct xgbe_prv_data *);
629 void (*phy_stop)(struct xgbe_prv_data *);
631 /* For PHY support while device is up */
632 void (*phy_status)(struct xgbe_prv_data *);
633 int (*phy_config_aneg)(struct xgbe_prv_data *);
636 struct xgbe_desc_if {
637 int (*alloc_ring_resources)(struct xgbe_prv_data *);
638 void (*free_ring_resources)(struct xgbe_prv_data *);
639 int (*map_tx_skb)(struct xgbe_channel *, struct mbuf *);
640 int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *,
641 struct xgbe_ring_data *);
642 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
643 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
644 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
647 /* This structure contains flags that indicate what hardware features
648 * or configurations are present in the device.
650 struct xgbe_hw_features {
652 unsigned int version;
654 /* HW Feature Register0 */
655 unsigned int gmii; /* 1000 Mbps support */
656 unsigned int vlhash; /* VLAN Hash Filter */
657 unsigned int sma; /* SMA(MDIO) Interface */
658 unsigned int rwk; /* PMT remote wake-up packet */
659 unsigned int mgk; /* PMT magic packet */
660 unsigned int mmc; /* RMON module */
661 unsigned int aoe; /* ARP Offload */
662 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */
663 unsigned int eee; /* Energy Efficient Ethernet */
664 unsigned int tx_coe; /* Tx Checksum Offload */
665 unsigned int rx_coe; /* Rx Checksum Offload */
666 unsigned int addn_mac; /* Additional MAC Addresses */
667 unsigned int ts_src; /* Timestamp Source */
668 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
670 /* HW Feature Register1 */
671 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
672 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
673 unsigned int adv_ts_hi; /* Advance Timestamping High Word */
674 unsigned int dma_width; /* DMA width */
675 unsigned int dcb; /* DCB Feature */
676 unsigned int sph; /* Split Header Feature */
677 unsigned int tso; /* TCP Segmentation Offload */
678 unsigned int dma_debug; /* DMA Debug Registers */
679 unsigned int rss; /* Receive Side Scaling */
680 unsigned int tc_cnt; /* Number of Traffic Classes */
681 unsigned int hash_table_size; /* Hash Table Size */
682 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
684 /* HW Feature Register2 */
685 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
686 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
687 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
688 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
689 unsigned int pps_out_num; /* Number of PPS outputs */
690 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
693 struct xgbe_prv_data {
694 struct ifnet *netdev;
695 struct platform_device *pdev;
696 struct acpi_device *adev;
699 /* ACPI or DT flag */
700 unsigned int use_acpi;
702 /* XGMAC/XPCS related mmio registers */
703 struct resource *xgmac_res; /* XGMAC CSRs */
704 struct resource *xpcs_res; /* XPCS MMD registers */
705 struct resource *rxtx_res; /* SerDes Rx/Tx CSRs */
706 struct resource *sir0_res; /* SerDes integration registers (1/2) */
707 struct resource *sir1_res; /* SerDes integration registers (2/2) */
712 /* XPCS indirect addressing lock */
713 spinlock_t xpcs_lock;
715 /* Flags representing xgbe_state */
716 unsigned long dev_state;
718 struct resource *dev_irq_res;
719 struct resource *chan_irq_res[4];
721 unsigned int per_channel_irq;
723 struct xgbe_hw_if hw_if;
724 struct xgbe_phy_if phy_if;
725 struct xgbe_desc_if desc_if;
727 /* AXI DMA settings */
728 unsigned int coherent;
729 unsigned int axdomain;
730 unsigned int arcache;
731 unsigned int awcache;
733 /* Service routine support */
734 struct taskqueue *dev_workqueue;
735 struct task service_work;
736 struct callout service_timer;
738 /* Rings for Tx/Rx on a DMA channel */
739 struct xgbe_channel *channel;
740 unsigned int channel_count;
741 unsigned int tx_ring_count;
742 unsigned int tx_desc_count;
743 unsigned int rx_ring_count;
744 unsigned int rx_desc_count;
746 unsigned int tx_q_count;
747 unsigned int rx_q_count;
749 /* Tx/Rx common settings */
753 unsigned int tx_sf_mode;
754 unsigned int tx_threshold;
756 unsigned int tx_osp_mode;
759 unsigned int rx_sf_mode;
760 unsigned int rx_threshold;
763 /* Tx coalescing settings */
764 unsigned int tx_usecs;
765 unsigned int tx_frames;
767 /* Rx coalescing settings */
768 unsigned int rx_riwt;
769 unsigned int rx_usecs;
770 unsigned int rx_frames;
772 /* Current Rx buffer size */
773 unsigned int rx_buf_size;
775 /* Flow control settings */
776 unsigned int pause_autoneg;
777 unsigned int tx_pause;
778 unsigned int rx_pause;
780 /* Receive Side Scaling settings */
781 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE];
782 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE];
785 /* Netdev related settings */
786 unsigned char mac_addr[ETH_ALEN];
787 struct xgbe_mmc_stats mmc_stats;
788 struct xgbe_ext_stats ext_stats;
792 unsigned long sysclk_rate;
794 unsigned long ptpclk_rate;
797 unsigned int q2tc_map[XGBE_MAX_QUEUES];
798 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
801 /* Hardware features of the device */
802 struct xgbe_hw_features hw_feat;
804 /* Device restart work structure */
805 struct task restart_work;
807 /* Keeps track of power mode */
808 unsigned int power_down;
810 /* Network interface message level setting */
813 /* Current PHY settings */
817 /* MDIO/PHY related settings */
820 unsigned long link_check;
822 char an_name[IFNAMSIZ + 32];
824 struct resource *an_irq_res;
827 unsigned int speed_set;
829 /* SerDes UEFI configurable settings.
830 * Switching between modes/speeds requires new values for some
831 * SerDes settings. The values can be supplied as device
832 * properties in array format. The first array entry is for
833 * 1GbE, second for 2.5GbE and third for 10GbE
835 u32 serdes_blwc[XGBE_SPEEDS];
836 u32 serdes_cdr_rate[XGBE_SPEEDS];
837 u32 serdes_pq_skew[XGBE_SPEEDS];
838 u32 serdes_tx_amp[XGBE_SPEEDS];
839 u32 serdes_dfe_tap_cfg[XGBE_SPEEDS];
840 u32 serdes_dfe_tap_ena[XGBE_SPEEDS];
842 /* Auto-negotiation state machine support */
845 enum xgbe_an an_result;
846 enum xgbe_an an_state;
847 enum xgbe_rx kr_state;
848 enum xgbe_rx kx_state;
849 unsigned int an_supported;
850 unsigned int parallel_detect;
851 unsigned int fec_ability;
852 unsigned long an_start;
854 unsigned int lpm_ctrl; /* CTRL1 for resume */
857 /* Function prototypes*/
859 int xgbe_open(struct ifnet *);
860 int xgbe_close(struct ifnet *);
861 int xgbe_xmit(struct ifnet *, struct mbuf *);
862 int xgbe_change_mtu(struct ifnet *, int);
863 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
864 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *);
865 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
866 void xgbe_get_all_hw_features(struct xgbe_prv_data *);
867 void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
868 void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
870 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */
876 /* For debug prints */
878 #define DBGPR(x...) printf(x)
880 #define DBGPR(x...) do { } while (0)
884 #define DBGPR_MDIO(x...) printf(x)
886 #define DBGPR_MDIO(x...) do { } while (0)