2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2016,2017 SoftIron Inc.
5 * Copyright (c) 2020 Advanced Micro Devices, Inc.
7 * This software was developed by Andrew Turner under
8 * the sponsorship of SoftIron Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 #ifndef _XGBE_OSDEP_H_
35 #define _XGBE_OSDEP_H_
37 #include <sys/endian.h>
38 #include <sys/socket.h>
40 #include <net/ethernet.h>
42 #include <net/if_var.h>
43 #include <net/iflib.h>
45 MALLOC_DECLARE(M_AXGBE);
47 typedef uint16_t __le16;
48 typedef uint16_t __be16;
49 typedef uint32_t __le32;
51 #define BIT(pos) (1ul << pos)
53 #define cpu_to_be16(x) be16toh(x)
54 #define be16_to_cpu(x) htobe16(x)
55 #define lower_32_bits(x) ((x) & 0xffffffffu)
56 #define upper_32_bits(x) (((x) >> 32) & 0xffffffffu)
57 #define cpu_to_le32(x) le32toh(x)
58 #define le32_to_cpu(x) htole32(x)
59 #define cpu_to_le16(x) htole16(x)
61 #define for_each_set_bit(bit, addr, size) \
62 for ((bit) = find_first_bit((addr), (size)); \
64 (bit) = find_next_bit((addr), (size), (bit) + 1))
66 typedef struct mtx spinlock_t;
69 spin_lock_init(spinlock_t *spinlock)
71 mtx_init(spinlock, "axgbe_spin", NULL, MTX_SPIN);
74 #define spin_lock_irqsave(spinlock, flags) \
76 (flags) = intr_disable(); \
77 mtx_lock_spin(spinlock); \
80 #define spin_unlock_irqrestore(spinlock, flags) \
82 mtx_unlock_spin(spinlock); \
83 intr_restore(flags); \
86 #define ADVERTISED_Pause (1 << 0)
87 #define ADVERTISED_Asym_Pause (1 << 1)
88 #define ADVERTISED_Autoneg (1 << 2)
89 #define ADVERTISED_Backplane (1 << 3)
90 #define ADVERTISED_10000baseKR_Full (1 << 4)
91 #define ADVERTISED_2500baseX_Full (1 << 5)
92 #define ADVERTISED_1000baseKX_Full (1 << 6)
93 #define ADVERTISED_100baseT_Full (1 << 7)
94 #define ADVERTISED_10000baseR_FEC (1 << 8)
95 #define ADVERTISED_10000baseT_Full (1 << 9)
96 #define ADVERTISED_2500baseT_Full (1 << 10)
97 #define ADVERTISED_1000baseT_Full (1 << 11)
98 #define ADVERTISED_TP (1 << 12)
99 #define ADVERTISED_FIBRE (1 << 13)
100 #define ADVERTISED_1000baseX_Full (1 << 14)
101 #define ADVERTISED_10000baseSR_Full (1 << 15)
102 #define ADVERTISED_10000baseLR_Full (1 << 16)
103 #define ADVERTISED_10000baseLRM_Full (1 << 17)
104 #define ADVERTISED_10000baseER_Full (1 << 18)
105 #define ADVERTISED_10000baseCR_Full (1 << 19)
106 #define ADVERTISED_100baseT_Half (1 << 20)
107 #define ADVERTISED_1000baseT_Half (1 << 21)
109 #define SUPPORTED_Pause (1 << 0)
110 #define SUPPORTED_Asym_Pause (1 << 1)
111 #define SUPPORTED_Autoneg (1 << 2)
112 #define SUPPORTED_Backplane (1 << 3)
113 #define SUPPORTED_10000baseKR_Full (1 << 4)
114 #define SUPPORTED_2500baseX_Full (1 << 5)
115 #define SUPPORTED_1000baseKX_Full (1 << 6)
116 #define SUPPORTED_100baseT_Full (1 << 7)
117 #define SUPPORTED_10000baseR_FEC (1 << 8)
118 #define SUPPORTED_10000baseT_Full (1 << 9)
119 #define SUPPORTED_2500baseT_Full (1 << 10)
120 #define SUPPORTED_1000baseT_Full (1 << 11)
121 #define SUPPORTED_TP (1 << 12)
122 #define SUPPORTED_FIBRE (1 << 13)
123 #define SUPPORTED_1000baseX_Full (1 << 14)
124 #define SUPPORTED_10000baseSR_Full (1 << 15)
125 #define SUPPORTED_10000baseLR_Full (1 << 16)
126 #define SUPPORTED_10000baseLRM_Full (1 << 17)
127 #define SUPPORTED_10000baseER_Full (1 << 18)
128 #define SUPPORTED_10000baseCR_Full (1 << 19)
129 #define SUPPORTED_100baseT_Half (1 << 20)
130 #define SUPPORTED_1000baseT_Half (1 << 21)
132 #define LPA_PAUSE_ASYM 0x0800
134 #define AUTONEG_DISABLE 0
135 #define AUTONEG_ENABLE 1
137 #define DUPLEX_UNKNOWN 1
138 #define DUPLEX_FULL 2
139 #define DUPLEX_HALF 3
141 #define SPEED_UNKNOWN 1
142 #define SPEED_10000 2
148 #define BMCR_SPEED100 0x2000
150 #define MDIO_MMD_PMAPMD 1
151 #define MDIO_MMD_PCS 3
152 #define MDIO_MMD_AN 7
153 #define MDIO_MMD_VEND1 30 /* Vendor specific 1 */
154 #define MDIO_MMD_VEND2 31 /* Vendor specific 2 */
156 #define MDIO_PMA_10GBR_FECABLE 170
157 #define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001
158 #define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002
159 #define MII_ADDR_C45 (1<<30)
161 #define MDIO_CTRL1 0x00 /* MII_BMCR */
162 #define MDIO_CTRL1_RESET 0x8000 /* BMCR_RESET */
163 #define MDIO_CTRL1_SPEEDSELEXT 0x2040 /* BMCR_SPEED1000|BMCR_SPEED100*/
164 #define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x3c)
165 #define MDIO_AN_CTRL1_ENABLE 0x1000 /* BMCR_AUTOEN */
166 #define MDIO_CTRL1_LPOWER 0x0800 /* BMCR_PDOWN */
167 #define MDIO_AN_CTRL1_RESTART 0x0200 /* BMCR_STARTNEG */
169 #define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00)
171 #define MDIO_STAT1 1 /* MII_BMSR */
172 #define MDIO_STAT1_LSTATUS 0x0004 /* BMSR_LINK */
174 #define MDIO_DEVID1 2 /* MII_PHYSID1 */
175 #define MDIO_DEVID2 3 /* MII_PHYSID2 */
179 #define MDIO_CTRL2 0x07
180 #define MDIO_PCS_CTRL2_10GBR 0x0000
181 #define MDIO_PCS_CTRL2_10GBX 0x0001
182 #define MDIO_PCS_CTRL2_TYPE 0x0003
184 #define MDIO_AN_ADVERTISE 16
186 #define MDIO_AN_LPA 19
188 #define ETH_ALEN ETHER_ADDR_LEN
189 #define ETH_HLEN ETHER_HDR_LEN
190 #define ETH_FCS_LEN 4
191 #define VLAN_HLEN ETHER_VLAN_ENCAP_LEN
192 #define VLAN_NVID 4096
193 #define VLAN_VID_MASK 0x0FFF
195 #define CRC32_POLY_LE 0xedb88320
197 #define ARRAY_SIZE(x) nitems(x)
199 #define BITS_PER_LONG (sizeof(long) * CHAR_BIT)
200 #define BITS_TO_LONGS(n) howmany((n), BITS_PER_LONG)
202 #define BITMAP_LAST_WORD_MASK(n) (~0UL >> (BITS_PER_LONG - (n)))
204 #define min_t(t, a, b) MIN((t)(a), (t)(b))
205 #define max_t(t, a, b) MAX((t)(a), (t)(b))
208 clear_bit(int pos, unsigned long *p)
211 atomic_clear_long(p, 1ul << pos);
215 test_bit(int pos, unsigned long *p)
220 return ((val & 1ul << pos) != 0);
224 set_bit(int pos, unsigned long *p)
227 atomic_set_long(p, 1ul << pos);
234 return (ffsl(mask) - 1);
241 return (flsll(mask));
245 get_bitmask_order(unsigned int count)
250 return (order); /* We could be slightly more clever with -1 here... */
253 static inline unsigned long
254 find_next_bit(const unsigned long *addr, unsigned long size, unsigned long offset)
263 pos = offset / BITS_PER_LONG;
264 offs = offset % BITS_PER_LONG;
265 bit = BITS_PER_LONG * pos;
268 mask = (*addr) & ~BITMAP_LAST_WORD_MASK(offs);
270 return (bit + __ffsl(mask));
271 if (size - bit <= BITS_PER_LONG)
273 bit += BITS_PER_LONG;
276 for (size -= bit; size >= BITS_PER_LONG;
277 size -= BITS_PER_LONG, bit += BITS_PER_LONG, addr++) {
280 return (bit + __ffsl(*addr));
283 mask = (*addr) & BITMAP_LAST_WORD_MASK(size);
292 static inline unsigned long
293 find_first_bit(const unsigned long *addr, unsigned long size)
298 for (bit = 0; size >= BITS_PER_LONG;
299 size -= BITS_PER_LONG, bit += BITS_PER_LONG, addr++) {
302 return (bit + __ffsl(*addr));
305 mask = (*addr) & BITMAP_LAST_WORD_MASK(size);
314 #endif /* _XGBE_OSDEP_H_ */