sys/dev/bce/if_bce.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright (c) 2006-2014 QLogic Corporation
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  20  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  26  * THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 /*
  33  * The following controllers are supported by this driver:
  34  *   BCM5706C A2, A3
  35  *   BCM5706S A2, A3
  36  *   BCM5708C B1, B2
  37  *   BCM5708S B1, B2
  38  *   BCM5709C A1, C0
  39  *   BCM5709S A1, C0
  40  *   BCM5716C C0
  41  *   BCM5716S C0
  42  *
  43  * The following controllers are not supported by this driver:
  44  *   BCM5706C A0, A1 (pre-production)
  45  *   BCM5706S A0, A1 (pre-production)
  46  *   BCM5708C A0, B0 (pre-production)
  47  *   BCM5708S A0, B0 (pre-production)
  48  *   BCM5709C A0  B0, B1, B2 (pre-production)
  49  *   BCM5709S A0, B0, B1, B2 (pre-production)
  50  */
  51
  52 #include "opt_bce.h"
  53
  54 #include <sys/param.h>
  55 #include <sys/endian.h>
  56 #include <sys/systm.h>
  57 #include <sys/sockio.h>
  58 #include <sys/lock.h>
  59 #include <sys/mbuf.h>
  60 #include <sys/malloc.h>
  61 #include <sys/mutex.h>
  62 #include <sys/kernel.h>
  63 #include <sys/module.h>
  64 #include <sys/socket.h>
  65 #include <sys/sysctl.h>
  66 #include <sys/queue.h>
  67
  68 #include <net/bpf.h>
  69 #include <net/ethernet.h>
  70 #include <net/if.h>
  71 #include <net/if_var.h>
  72 #include <net/if_arp.h>
  73 #include <net/if_dl.h>
  74 #include <net/if_media.h>
  75
  76 #include <net/if_types.h>
  77 #include <net/if_vlan_var.h>
  78
  79 #include <netinet/in_systm.h>
  80 #include <netinet/in.h>
  81 #include <netinet/if_ether.h>
  82 #include <netinet/ip.h>
  83 #include <netinet/ip6.h>
  84 #include <netinet/tcp.h>
  85 #include <netinet/udp.h>
  86
  87 #include <machine/bus.h>
  88 #include <machine/resource.h>
  89 #include <sys/bus.h>
  90 #include <sys/rman.h>
  91
  92 #include <dev/mii/mii.h>
  93 #include <dev/mii/miivar.h>
  94 #include "miidevs.h"
  95 #include <dev/mii/brgphyreg.h>
  96
  97 #include <dev/pci/pcireg.h>
  98 #include <dev/pci/pcivar.h>
  99
 100 #include "miibus_if.h"
 101
 102 #include <dev/bce/if_bcereg.h>
 103 #include <dev/bce/if_bcefw.h>
 104
 105 /****************************************************************************/
 106 /* BCE Debug Options                                                        */
 107 /****************************************************************************/
 108 #ifdef BCE_DEBUG
 109         u32 bce_debug = BCE_WARN;
 110
 111         /*          0 = Never              */
 112         /*          1 = 1 in 2,147,483,648 */
 113         /*        256 = 1 in     8,388,608 */
 114         /*       2048 = 1 in     1,048,576 */
 115         /*      65536 = 1 in        32,768 */
 116         /*    1048576 = 1 in         2,048 */
 117         /*  268435456 = 1 in             8 */
 118         /*  536870912 = 1 in             4 */
 119         /* 1073741824 = 1 in             2 */
 120
 121         /* Controls how often the l2_fhdr frame error check will fail. */
 122         int l2fhdr_error_sim_control = 0;
 123
 124         /* Controls how often the unexpected attention check will fail. */
 125         int unexpected_attention_sim_control = 0;
 126
 127         /* Controls how often to simulate an mbuf allocation failure. */
 128         int mbuf_alloc_failed_sim_control = 0;
 129
 130         /* Controls how often to simulate a DMA mapping failure. */
 131         int dma_map_addr_failed_sim_control = 0;
 132
 133         /* Controls how often to simulate a bootcode failure. */
 134         int bootcode_running_failure_sim_control = 0;
 135 #endif
 136
 137 /****************************************************************************/
 138 /* PCI Device ID Table                                                      */
 139 /*                                                                          */
 140 /* Used by bce_probe() to identify the devices supported by this driver.    */
 141 /****************************************************************************/
 142 #define BCE_DEVDESC_MAX         64
 143
 144 static const struct bce_type bce_devs[] = {
 145         /* BCM5706C Controllers and OEM boards. */
 146         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
 147                 "HP NC370T Multifunction Gigabit Server Adapter" },
 148         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
 149                 "HP NC370i Multifunction Gigabit Server Adapter" },
 150         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
 151                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
 152         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
 153                 "HP NC371i Multifunction Gigabit Server Adapter" },
 154         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 155                 "QLogic NetXtreme II BCM5706 1000Base-T" },
 156
 157         /* BCM5706S controllers and OEM boards. */
 158         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 159                 "HP NC370F Multifunction Gigabit Server Adapter" },
 160         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 161                 "QLogic NetXtreme II BCM5706 1000Base-SX" },
 162
 163         /* BCM5708C controllers and OEM boards. */
 164         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
 165                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
 166         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
 167                 "HP NC373i Multifunction Gigabit Server Adapter" },
 168         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
 169                 "HP NC374m PCIe Multifunction Adapter" },
 170         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 171                 "QLogic NetXtreme II BCM5708 1000Base-T" },
 172
 173         /* BCM5708S controllers and OEM boards. */
 174         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
 175                 "HP NC373m Multifunction Gigabit Server Adapter" },
 176         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
 177                 "HP NC373i Multifunction Gigabit Server Adapter" },
 178         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
 179                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
 180         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 181                 "QLogic NetXtreme II BCM5708 1000Base-SX" },
 182
 183         /* BCM5709C controllers and OEM boards. */
 184         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
 185                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 186         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
 187                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
 188         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
 189                 "QLogic NetXtreme II BCM5709 1000Base-T" },
 190
 191         /* BCM5709S controllers and OEM boards. */
 192         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
 193                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
 194         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
 195                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 196         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
 197                 "QLogic NetXtreme II BCM5709 1000Base-SX" },
 198
 199         /* BCM5716 controllers and OEM boards. */
 200         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,  PCI_ANY_ID,  PCI_ANY_ID,
 201                 "QLogic NetXtreme II BCM5716 1000Base-T" },
 202
 203         { 0, 0, 0, 0, NULL }
 204 };
 205
 206
 207 /****************************************************************************/
 208 /* Supported Flash NVRAM device data.                                       */
 209 /****************************************************************************/
 210 static const struct flash_spec flash_table[] =
 211 {
 212 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
 213 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
 214
 215         /* Slow EEPROM */
 216         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 217          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 218          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 219          "EEPROM - slow"},
 220         /* Expansion entry 0001 */
 221         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 222          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 223          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 224          "Entry 0001"},
 225         /* Saifun SA25F010 (non-buffered flash) */
 226         /* strap, cfg1, & write1 need updates */
 227         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 228          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 229          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 230          "Non-buffered flash (128kB)"},
 231         /* Saifun SA25F020 (non-buffered flash) */
 232         /* strap, cfg1, & write1 need updates */
 233         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 234          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 235          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 236          "Non-buffered flash (256kB)"},
 237         /* Expansion entry 0100 */
 238         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 239          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 240          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 241          "Entry 0100"},
 242         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 243         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 244          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 245          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 246          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 247         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 248         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 249          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 250          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 251          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 252         /* Saifun SA25F005 (non-buffered flash) */
 253         /* strap, cfg1, & write1 need updates */
 254         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 255          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 256          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 257          "Non-buffered flash (64kB)"},
 258         /* Fast EEPROM */
 259         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 260          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 261          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 262          "EEPROM - fast"},
 263         /* Expansion entry 1001 */
 264         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 265          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 266          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 267          "Entry 1001"},
 268         /* Expansion entry 1010 */
 269         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 270          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 271          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 272          "Entry 1010"},
 273         /* ATMEL AT45DB011B (buffered flash) */
 274         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 275          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 276          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 277          "Buffered flash (128kB)"},
 278         /* Expansion entry 1100 */
 279         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 280          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 281          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 282          "Entry 1100"},
 283         /* Expansion entry 1101 */
 284         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 285          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 286          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 287          "Entry 1101"},
 288         /* Ateml Expansion entry 1110 */
 289         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 290          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 291          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 292          "Entry 1110 (Atmel)"},
 293         /* ATMEL AT45DB021B (buffered flash) */
 294         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 295          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 296          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 297          "Buffered flash (256kB)"},
 298 };
 299
 300 /*
 301  * The BCM5709 controllers transparently handle the
 302  * differences between Atmel 264 byte pages and all
 303  * flash devices which use 256 byte pages, so no
 304  * logical-to-physical mapping is required in the
 305  * driver.
 306  */
 307 static const struct flash_spec flash_5709 = {
 308         .flags          = BCE_NV_BUFFERED,
 309         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 310         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 311         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 312         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
 313         .name           = "5709/5716 buffered flash (256kB)",
 314 };
 315
 316
 317 /****************************************************************************/
 318 /* FreeBSD device entry points.                                             */
 319 /****************************************************************************/
 320 static int  bce_probe                   (device_t);
 321 static int  bce_attach                  (device_t);
 322 static int  bce_detach                  (device_t);
 323 static int  bce_shutdown                (device_t);
 324
 325
 326 /****************************************************************************/
 327 /* BCE Debug Data Structure Dump Routines                                   */
 328 /****************************************************************************/
 329 #ifdef BCE_DEBUG
 330 static u32  bce_reg_rd                          (struct bce_softc *, u32);
 331 static void bce_reg_wr                          (struct bce_softc *, u32, u32);
 332 static void bce_reg_wr16                        (struct bce_softc *, u32, u16);
 333 static u32  bce_ctx_rd                          (struct bce_softc *, u32, u32);
 334 static void bce_dump_enet                       (struct bce_softc *, struct mbuf *);
 335 static void bce_dump_mbuf                       (struct bce_softc *, struct mbuf *);
 336 static void bce_dump_tx_mbuf_chain      (struct bce_softc *, u16, int);
 337 static void bce_dump_rx_mbuf_chain      (struct bce_softc *, u16, int);
 338 static void bce_dump_pg_mbuf_chain      (struct bce_softc *, u16, int);
 339 static void bce_dump_txbd                       (struct bce_softc *,
 340     int, struct tx_bd *);
 341 static void bce_dump_rxbd                       (struct bce_softc *,
 342     int, struct rx_bd *);
 343 static void bce_dump_pgbd                       (struct bce_softc *,
 344     int, struct rx_bd *);
 345 static void bce_dump_l2fhdr             (struct bce_softc *,
 346     int, struct l2_fhdr *);
 347 static void bce_dump_ctx                        (struct bce_softc *, u16);
 348 static void bce_dump_ftqs                       (struct bce_softc *);
 349 static void bce_dump_tx_chain           (struct bce_softc *, u16, int);
 350 static void bce_dump_rx_bd_chain        (struct bce_softc *, u16, int);
 351 static void bce_dump_pg_chain           (struct bce_softc *, u16, int);
 352 static void bce_dump_status_block       (struct bce_softc *);
 353 static void bce_dump_stats_block        (struct bce_softc *);
 354 static void bce_dump_driver_state       (struct bce_softc *);
 355 static void bce_dump_hw_state           (struct bce_softc *);
 356 static void bce_dump_shmem_state        (struct bce_softc *);
 357 static void bce_dump_mq_regs            (struct bce_softc *);
 358 static void bce_dump_bc_state           (struct bce_softc *);
 359 static void bce_dump_txp_state          (struct bce_softc *, int);
 360 static void bce_dump_rxp_state          (struct bce_softc *, int);
 361 static void bce_dump_tpat_state (struct bce_softc *, int);
 362 static void bce_dump_cp_state           (struct bce_softc *, int);
 363 static void bce_dump_com_state          (struct bce_softc *, int);
 364 static void bce_dump_rv2p_state (struct bce_softc *);
 365 static void bce_breakpoint                      (struct bce_softc *);
 366 #endif /*BCE_DEBUG */
 367
 368
 369 /****************************************************************************/
 370 /* BCE Register/Memory Access Routines                                      */
 371 /****************************************************************************/
 372 static u32  bce_reg_rd_ind              (struct bce_softc *, u32);
 373 static void bce_reg_wr_ind              (struct bce_softc *, u32, u32);
 374 static void bce_shmem_wr                (struct bce_softc *, u32, u32);
 375 static u32  bce_shmem_rd                (struct bce_softc *, u32);
 376 static void bce_ctx_wr                  (struct bce_softc *, u32, u32, u32);
 377 static int  bce_miibus_read_reg         (device_t, int, int);
 378 static int  bce_miibus_write_reg        (device_t, int, int, int);
 379 static void bce_miibus_statchg          (device_t);
 380
 381 #ifdef BCE_DEBUG
 382 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS);
 383 #ifdef BCE_NVRAM_WRITE_SUPPORT
 384 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS);
 385 #endif
 386 #endif
 387
 388 /****************************************************************************/
 389 /* BCE NVRAM Access Routines                                                */
 390 /****************************************************************************/
 391 static int  bce_acquire_nvram_lock      (struct bce_softc *);
 392 static int  bce_release_nvram_lock      (struct bce_softc *);
 393 static void bce_enable_nvram_access(struct bce_softc *);
 394 static void bce_disable_nvram_access(struct bce_softc *);
 395 static int  bce_nvram_read_dword        (struct bce_softc *, u32, u8 *, u32);
 396 static int  bce_init_nvram                      (struct bce_softc *);
 397 static int  bce_nvram_read                      (struct bce_softc *, u32, u8 *, int);
 398 static int  bce_nvram_test                      (struct bce_softc *);
 399 #ifdef BCE_NVRAM_WRITE_SUPPORT
 400 static int  bce_enable_nvram_write      (struct bce_softc *);
 401 static void bce_disable_nvram_write(struct bce_softc *);
 402 static int  bce_nvram_erase_page        (struct bce_softc *, u32);
 403 static int  bce_nvram_write_dword       (struct bce_softc *, u32, u8 *, u32);
 404 static int  bce_nvram_write             (struct bce_softc *, u32, u8 *, int);
 405 #endif
 406
 407 /****************************************************************************/
 408 /*                                                                          */
 409 /****************************************************************************/
 410 static void bce_get_rx_buffer_sizes(struct bce_softc *, int);
 411 static void bce_get_media                       (struct bce_softc *);
 412 static void bce_init_media                      (struct bce_softc *);
 413 static u32 bce_get_rphy_link            (struct bce_softc *);
 414 static void bce_dma_map_addr            (void *, bus_dma_segment_t *, int, int);
 415 static int  bce_dma_alloc                       (device_t);
 416 static void bce_dma_free                        (struct bce_softc *);
 417 static void bce_release_resources       (struct bce_softc *);
 418
 419 /****************************************************************************/
 420 /* BCE Firmware Synchronization and Load                                    */
 421 /****************************************************************************/
 422 static void bce_fw_cap_init                     (struct bce_softc *);
 423 static int  bce_fw_sync                 (struct bce_softc *, u32);
 424 static void bce_load_rv2p_fw            (struct bce_softc *, const u32 *, u32,
 425     u32);
 426 static void bce_load_cpu_fw             (struct bce_softc *,
 427     struct cpu_reg *, struct fw_info *);
 428 static void bce_start_cpu                       (struct bce_softc *, struct cpu_reg *);
 429 static void bce_halt_cpu                        (struct bce_softc *, struct cpu_reg *);
 430 static void bce_start_rxp_cpu           (struct bce_softc *);
 431 static void bce_init_rxp_cpu            (struct bce_softc *);
 432 static void bce_init_txp_cpu            (struct bce_softc *);
 433 static void bce_init_tpat_cpu           (struct bce_softc *);
 434 static void bce_init_cp_cpu             (struct bce_softc *);
 435 static void bce_init_com_cpu            (struct bce_softc *);
 436 static void bce_init_cpus                       (struct bce_softc *);
 437
 438 static void bce_print_adapter_info      (struct bce_softc *);
 439 static void bce_probe_pci_caps          (device_t, struct bce_softc *);
 440 static void bce_stop                            (struct bce_softc *);
 441 static int  bce_reset                           (struct bce_softc *, u32);
 442 static int  bce_chipinit                        (struct bce_softc *);
 443 static int  bce_blockinit                       (struct bce_softc *);
 444
 445 static int  bce_init_tx_chain           (struct bce_softc *);
 446 static void bce_free_tx_chain           (struct bce_softc *);
 447
 448 static int  bce_get_rx_buf              (struct bce_softc *, u16, u16, u32 *);
 449 static int  bce_init_rx_chain           (struct bce_softc *);
 450 static void bce_fill_rx_chain           (struct bce_softc *);
 451 static void bce_free_rx_chain           (struct bce_softc *);
 452
 453 static int  bce_get_pg_buf              (struct bce_softc *, u16, u16);
 454 static int  bce_init_pg_chain           (struct bce_softc *);
 455 static void bce_fill_pg_chain           (struct bce_softc *);
 456 static void bce_free_pg_chain           (struct bce_softc *);
 457
 458 static struct mbuf *bce_tso_setup       (struct bce_softc *,
 459     struct mbuf **, u16 *);
 460 static int  bce_tx_encap                        (struct bce_softc *, struct mbuf **);
 461 static void bce_start_locked            (struct ifnet *);
 462 static void bce_start                   (struct ifnet *);
 463 static int  bce_ioctl                   (struct ifnet *, u_long, caddr_t);
 464 static uint64_t bce_get_counter         (struct ifnet *, ift_counter);
 465 static void bce_watchdog                (struct bce_softc *);
 466 static int  bce_ifmedia_upd             (struct ifnet *);
 467 static int  bce_ifmedia_upd_locked      (struct ifnet *);
 468 static void bce_ifmedia_sts             (struct ifnet *, struct ifmediareq *);
 469 static void bce_ifmedia_sts_rphy        (struct bce_softc *, struct ifmediareq *);
 470 static void bce_init_locked             (struct bce_softc *);
 471 static void bce_init                            (void *);
 472 static void bce_mgmt_init_locked        (struct bce_softc *sc);
 473
 474 static int  bce_init_ctx                        (struct bce_softc *);
 475 static void bce_get_mac_addr            (struct bce_softc *);
 476 static void bce_set_mac_addr            (struct bce_softc *);
 477 static void bce_phy_intr                        (struct bce_softc *);
 478 static inline u16 bce_get_hw_rx_cons    (struct bce_softc *);
 479 static void bce_rx_intr                 (struct bce_softc *);
 480 static void bce_tx_intr                 (struct bce_softc *);
 481 static void bce_disable_intr            (struct bce_softc *);
 482 static void bce_enable_intr             (struct bce_softc *, int);
 483
 484 static void bce_intr                            (void *);
 485 static void bce_set_rx_mode             (struct bce_softc *);
 486 static void bce_stats_update            (struct bce_softc *);
 487 static void bce_tick                            (void *);
 488 static void bce_pulse                           (void *);
 489 static void bce_add_sysctls             (struct bce_softc *);
 490
 491
 492 /****************************************************************************/
 493 /* FreeBSD device dispatch table.                                           */
 494 /****************************************************************************/
 495 static device_method_t bce_methods[] = {
 496         /* Device interface (device_if.h) */
 497         DEVMETHOD(device_probe,         bce_probe),
 498         DEVMETHOD(device_attach,        bce_attach),
 499         DEVMETHOD(device_detach,        bce_detach),
 500         DEVMETHOD(device_shutdown,      bce_shutdown),
 501 /* Supported by device interface but not used here. */
 502 /*      DEVMETHOD(device_identify,      bce_identify),      */
 503 /*      DEVMETHOD(device_suspend,       bce_suspend),       */
 504 /*      DEVMETHOD(device_resume,        bce_resume),        */
 505 /*      DEVMETHOD(device_quiesce,       bce_quiesce),       */
 506
 507         /* MII interface (miibus_if.h) */
 508         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 509         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 510         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 511 /* Supported by MII interface but not used here.       */
 512 /*      DEVMETHOD(miibus_linkchg,       bce_miibus_linkchg),   */
 513 /*      DEVMETHOD(miibus_mediainit,     bce_miibus_mediainit), */
 514
 515         DEVMETHOD_END
 516 };
 517
 518 static driver_t bce_driver = {
 519         "bce",
 520         bce_methods,
 521         sizeof(struct bce_softc)
 522 };
 523
 524 static devclass_t bce_devclass;
 525
 526 MODULE_DEPEND(bce, pci, 1, 1, 1);
 527 MODULE_DEPEND(bce, ether, 1, 1, 1);
 528 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 529
 530 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, NULL, NULL);
 531 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
 532 MODULE_PNP_INFO("U16:vendor;U16:device;U16:#;U16:#;D:#", pci, bce,
 533     bce_devs, nitems(bce_devs) - 1);
 534
 535 /****************************************************************************/
 536 /* Tunable device values                                                    */
 537 /****************************************************************************/
 538 static SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters");
 539
 540 /* Allowable values are TRUE or FALSE */
 541 static int bce_verbose = TRUE;
 542 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0,
 543     "Verbose output enable/disable");
 544
 545 /* Allowable values are TRUE or FALSE */
 546 static int bce_tso_enable = TRUE;
 547 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0,
 548     "TSO Enable/Disable");
 549
 550 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
 551 /* ToDo: Add MSI-X support. */
 552 static int bce_msi_enable = 1;
 553 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0,
 554     "MSI-X|MSI|INTx selector");
 555
 556 /* Allowable values are 1, 2, 4, 8. */
 557 static int bce_rx_pages = DEFAULT_RX_PAGES;
 558 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0,
 559     "Receive buffer descriptor pages (1 page = 255 buffer descriptors)");
 560
 561 /* Allowable values are 1, 2, 4, 8. */
 562 static int bce_tx_pages = DEFAULT_TX_PAGES;
 563 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0,
 564     "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)");
 565
 566 /* Allowable values are TRUE or FALSE. */
 567 static int bce_hdr_split = TRUE;
 568 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0,
 569     "Frame header/payload splitting Enable/Disable");
 570
 571 /* Allowable values are TRUE or FALSE. */
 572 static int bce_strict_rx_mtu = FALSE;
 573 SYSCTL_UINT(_hw_bce, OID_AUTO, strict_rx_mtu, CTLFLAG_RDTUN,
 574     &bce_strict_rx_mtu, 0,
 575     "Enable/Disable strict RX frame size checking");
 576
 577 /* Allowable values are 0 ... 100 */
 578 #ifdef BCE_DEBUG
 579 /* Generate 1 interrupt for every transmit completion. */
 580 static int bce_tx_quick_cons_trip_int = 1;
 581 #else
 582 /* Generate 1 interrupt for every 20 transmit completions. */
 583 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT;
 584 #endif
 585 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN,
 586     &bce_tx_quick_cons_trip_int, 0,
 587     "Transmit BD trip point during interrupts");
 588
 589 /* Allowable values are 0 ... 100 */
 590 /* Generate 1 interrupt for every transmit completion. */
 591 #ifdef BCE_DEBUG
 592 static int bce_tx_quick_cons_trip = 1;
 593 #else
 594 /* Generate 1 interrupt for every 20 transmit completions. */
 595 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
 596 #endif
 597 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN,
 598     &bce_tx_quick_cons_trip, 0,
 599     "Transmit BD trip point");
 600
 601 /* Allowable values are 0 ... 100 */
 602 #ifdef BCE_DEBUG
 603 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
 604 static int bce_tx_ticks_int = 0;
 605 #else
 606 /* Generate an interrupt if 80us have elapsed since the last TX completion. */
 607 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT;
 608 #endif
 609 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN,
 610     &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt");
 611
 612 /* Allowable values are 0 ... 100 */
 613 #ifdef BCE_DEBUG
 614 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
 615 static int bce_tx_ticks = 0;
 616 #else
 617 /* Generate an interrupt if 80us have elapsed since the last TX completion. */
 618 static int bce_tx_ticks = DEFAULT_TX_TICKS;
 619 #endif
 620 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN,
 621     &bce_tx_ticks, 0, "Transmit ticks count");
 622
 623 /* Allowable values are 1 ... 100 */
 624 #ifdef BCE_DEBUG
 625 /* Generate 1 interrupt for every received frame. */
 626 static int bce_rx_quick_cons_trip_int = 1;
 627 #else
 628 /* Generate 1 interrupt for every 6 received frames. */
 629 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT;
 630 #endif
 631 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN,
 632     &bce_rx_quick_cons_trip_int, 0,
 633     "Receive BD trip point duirng interrupts");
 634
 635 /* Allowable values are 1 ... 100 */
 636 #ifdef BCE_DEBUG
 637 /* Generate 1 interrupt for every received frame. */
 638 static int bce_rx_quick_cons_trip = 1;
 639 #else
 640 /* Generate 1 interrupt for every 6 received frames. */
 641 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP;
 642 #endif
 643 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN,
 644     &bce_rx_quick_cons_trip, 0,
 645     "Receive BD trip point");
 646
 647 /* Allowable values are 0 ... 100 */
 648 #ifdef BCE_DEBUG
 649 /* Generate an int. if 0us have elapsed since the last received frame. */
 650 static int bce_rx_ticks_int = 0;
 651 #else
 652 /* Generate an int. if 18us have elapsed since the last received frame. */
 653 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT;
 654 #endif
 655 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN,
 656     &bce_rx_ticks_int, 0, "Receive ticks count during interrupt");
 657
 658 /* Allowable values are 0 ... 100 */
 659 #ifdef BCE_DEBUG
 660 /* Generate an int. if 0us have elapsed since the last received frame. */
 661 static int bce_rx_ticks = 0;
 662 #else
 663 /* Generate an int. if 18us have elapsed since the last received frame. */
 664 static int bce_rx_ticks = DEFAULT_RX_TICKS;
 665 #endif
 666 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN,
 667     &bce_rx_ticks, 0, "Receive ticks count");
 668
 669
 670 /****************************************************************************/
 671 /* Device probe function.                                                   */
 672 /*                                                                          */
 673 /* Compares the device to the driver's list of supported devices and        */
 674 /* reports back to the OS whether this is the right driver for the device.  */
 675 /*                                                                          */
 676 /* Returns:                                                                 */
 677 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 678 /****************************************************************************/
 679 static int
 680 bce_probe(device_t dev)
 681 {
 682         const struct bce_type *t;
 683         struct bce_softc *sc;
 684         char *descbuf;
 685         u16 vid = 0, did = 0, svid = 0, sdid = 0;
 686
 687         t = bce_devs;
 688
 689         sc = device_get_softc(dev);
 690         sc->bce_unit = device_get_unit(dev);
 691         sc->bce_dev = dev;
 692
 693         /* Get the data for the device to be probed. */
 694         vid  = pci_get_vendor(dev);
 695         did  = pci_get_device(dev);
 696         svid = pci_get_subvendor(dev);
 697         sdid = pci_get_subdevice(dev);
 698
 699         DBPRINT(sc, BCE_EXTREME_LOAD,
 700             "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
 701             "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
 702
 703         /* Look through the list of known devices for a match. */
 704         while(t->bce_name != NULL) {
 705
 706                 if ((vid == t->bce_vid) && (did == t->bce_did) &&
 707                     ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) &&
 708                     ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) {
 709
 710                         descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
 711
 712                         if (descbuf == NULL)
 713                                 return(ENOMEM);
 714
 715                         /* Print out the device identity. */
 716                         snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 717                             t->bce_name, (((pci_read_config(dev,
 718                             PCIR_REVID, 4) & 0xf0) >> 4) + 'A'),
 719                             (pci_read_config(dev, PCIR_REVID, 4) & 0xf));
 720
 721                         device_set_desc_copy(dev, descbuf);
 722                         free(descbuf, M_TEMP);
 723                         return(BUS_PROBE_DEFAULT);
 724                 }
 725                 t++;
 726         }
 727
 728         return(ENXIO);
 729 }
 730
 731
 732 /****************************************************************************/
 733 /* PCI Capabilities Probe Function.                                         */
 734 /*                                                                          */
 735 /* Walks the PCI capabiites list for the device to find what features are   */
 736 /* supported.                                                               */
 737 /*                                                                          */
 738 /* Returns:                                                                 */
 739 /*   None.                                                                  */
 740 /****************************************************************************/
 741 static void
 742 bce_print_adapter_info(struct bce_softc *sc)
 743 {
 744         int i = 0;
 745
 746         DBENTER(BCE_VERBOSE_LOAD);
 747
 748         if (bce_verbose || bootverbose) {
 749                 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid);
 750                 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >>
 751                     12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
 752
 753
 754                 /* Bus info. */
 755                 if (sc->bce_flags & BCE_PCIE_FLAG) {
 756                         printf("Bus (PCIe x%d, ", sc->link_width);
 757                         switch (sc->link_speed) {
 758                         case 1: printf("2.5Gbps); "); break;
 759                         case 2: printf("5Gbps); "); break;
 760                         default: printf("Unknown link speed); ");
 761                         }
 762                 } else {
 763                         printf("Bus (PCI%s, %s, %dMHz); ",
 764                             ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
 765                             ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ?
 766                             "32-bit" : "64-bit"), sc->bus_speed_mhz);
 767                 }
 768
 769                 /* Firmware version and device features. */
 770                 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (",
 771                     sc->bce_bc_ver,     sc->rx_pages, sc->tx_pages,
 772                     (bce_hdr_split == TRUE ? sc->pg_pages: 0));
 773
 774                 if (bce_hdr_split == TRUE) {
 775                         printf("SPLT");
 776                         i++;
 777                 }
 778
 779                 if (sc->bce_flags & BCE_USING_MSI_FLAG) {
 780                         if (i > 0) printf("|");
 781                         printf("MSI"); i++;
 782                 }
 783
 784                 if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
 785                         if (i > 0) printf("|");
 786                         printf("MSI-X"); i++;
 787                 }
 788
 789                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
 790                         if (i > 0) printf("|");
 791                         printf("2.5G"); i++;
 792                 }
 793
 794                 if (sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) {
 795                         if (i > 0) printf("|");
 796                         printf("Remote PHY(%s)",
 797                             sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG ?
 798                             "FIBER" : "TP"); i++;
 799                 }
 800
 801                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
 802                         if (i > 0) printf("|");
 803                         printf("MFW); MFW (%s)\n", sc->bce_mfw_ver);
 804                 } else {
 805                         printf(")\n");
 806                 }
 807
 808                 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n",
 809                     sc->bce_rx_quick_cons_trip_int,
 810                     sc->bce_rx_quick_cons_trip,
 811                     sc->bce_rx_ticks_int,
 812                     sc->bce_rx_ticks,
 813                     sc->bce_tx_quick_cons_trip_int,
 814                     sc->bce_tx_quick_cons_trip,
 815                     sc->bce_tx_ticks_int,
 816                     sc->bce_tx_ticks);
 817
 818         }
 819
 820         DBEXIT(BCE_VERBOSE_LOAD);
 821 }
 822
 823
 824 /****************************************************************************/
 825 /* PCI Capabilities Probe Function.                                         */
 826 /*                                                                          */
 827 /* Walks the PCI capabiites list for the device to find what features are   */
 828 /* supported.                                                               */
 829 /*                                                                          */
 830 /* Returns:                                                                 */
 831 /*   None.                                                                  */
 832 /****************************************************************************/
 833 static void
 834 bce_probe_pci_caps(device_t dev, struct bce_softc *sc)
 835 {
 836         u32 reg;
 837
 838         DBENTER(BCE_VERBOSE_LOAD);
 839
 840         /* Check if PCI-X capability is enabled. */
 841         if (pci_find_cap(dev, PCIY_PCIX, &reg) == 0) {
 842                 if (reg != 0)
 843                         sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
 844         }
 845
 846         /* Check if PCIe capability is enabled. */
 847         if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
 848                 if (reg != 0) {
 849                         u16 link_status = pci_read_config(dev, reg + 0x12, 2);
 850                         DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = "
 851                             "0x%08X\n", link_status);
 852                         sc->link_speed = link_status & 0xf;
 853                         sc->link_width = (link_status >> 4) & 0x3f;
 854                         sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
 855                         sc->bce_flags |= BCE_PCIE_FLAG;
 856                 }
 857         }
 858
 859         /* Check if MSI capability is enabled. */
 860         if (pci_find_cap(dev, PCIY_MSI, &reg) == 0) {
 861                 if (reg != 0)
 862                         sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG;
 863         }
 864
 865         /* Check if MSI-X capability is enabled. */
 866         if (pci_find_cap(dev, PCIY_MSIX, &reg) == 0) {
 867                 if (reg != 0)
 868                         sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG;
 869         }
 870
 871         DBEXIT(BCE_VERBOSE_LOAD);
 872 }
 873
 874
 875 /****************************************************************************/
 876 /* Load and validate user tunable settings.                                 */
 877 /*                                                                          */
 878 /* Returns:                                                                 */
 879 /*   Nothing.                                                               */
 880 /****************************************************************************/
 881 static void
 882 bce_set_tunables(struct bce_softc *sc)
 883 {
 884         /* Set sysctl values for RX page count. */
 885         switch (bce_rx_pages) {
 886         case 1:
 887                 /* fall-through */
 888         case 2:
 889                 /* fall-through */
 890         case 4:
 891                 /* fall-through */
 892         case 8:
 893                 sc->rx_pages = bce_rx_pages;
 894                 break;
 895         default:
 896                 sc->rx_pages = DEFAULT_RX_PAGES;
 897                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 898                     "hw.bce.rx_pages!  Setting default of %d.\n",
 899                     __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES);
 900         }
 901
 902         /* ToDo: Consider allowing user setting for pg_pages. */
 903         sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES);
 904
 905         /* Set sysctl values for TX page count. */
 906         switch (bce_tx_pages) {
 907         case 1:
 908                 /* fall-through */
 909         case 2:
 910                 /* fall-through */
 911         case 4:
 912                 /* fall-through */
 913         case 8:
 914                 sc->tx_pages = bce_tx_pages;
 915                 break;
 916         default:
 917                 sc->tx_pages = DEFAULT_TX_PAGES;
 918                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 919                     "hw.bce.tx_pages!  Setting default of %d.\n",
 920                     __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES);
 921         }
 922
 923         /*
 924          * Validate the TX trip point (i.e. the number of
 925          * TX completions before a status block update is
 926          * generated and an interrupt is asserted.
 927          */
 928         if (bce_tx_quick_cons_trip_int <= 100) {
 929                 sc->bce_tx_quick_cons_trip_int =
 930                     bce_tx_quick_cons_trip_int;
 931         } else {
 932                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 933                     "hw.bce.tx_quick_cons_trip_int!  Setting default of %d.\n",
 934                     __FILE__, __LINE__, bce_tx_quick_cons_trip_int,
 935                     DEFAULT_TX_QUICK_CONS_TRIP_INT);
 936                 sc->bce_tx_quick_cons_trip_int =
 937                     DEFAULT_TX_QUICK_CONS_TRIP_INT;
 938         }
 939
 940         if (bce_tx_quick_cons_trip <= 100) {
 941                 sc->bce_tx_quick_cons_trip =
 942                     bce_tx_quick_cons_trip;
 943         } else {
 944                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 945                     "hw.bce.tx_quick_cons_trip!  Setting default of %d.\n",
 946                     __FILE__, __LINE__, bce_tx_quick_cons_trip,
 947                     DEFAULT_TX_QUICK_CONS_TRIP);
 948                 sc->bce_tx_quick_cons_trip =
 949                     DEFAULT_TX_QUICK_CONS_TRIP;
 950         }
 951
 952         /*
 953          * Validate the TX ticks count (i.e. the maximum amount
 954          * of time to wait after the last TX completion has
 955          * occurred before a status block update is generated
 956          * and an interrupt is asserted.
 957          */
 958         if (bce_tx_ticks_int <= 100) {
 959                 sc->bce_tx_ticks_int =
 960                     bce_tx_ticks_int;
 961         } else {
 962                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 963                     "hw.bce.tx_ticks_int!  Setting default of %d.\n",
 964                     __FILE__, __LINE__, bce_tx_ticks_int,
 965                     DEFAULT_TX_TICKS_INT);
 966                 sc->bce_tx_ticks_int =
 967                     DEFAULT_TX_TICKS_INT;
 968            }
 969
 970         if (bce_tx_ticks <= 100) {
 971                 sc->bce_tx_ticks =
 972                     bce_tx_ticks;
 973         } else {
 974                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 975                     "hw.bce.tx_ticks!  Setting default of %d.\n",
 976                     __FILE__, __LINE__, bce_tx_ticks,
 977                     DEFAULT_TX_TICKS);
 978                 sc->bce_tx_ticks =
 979                     DEFAULT_TX_TICKS;
 980         }
 981
 982         /*
 983          * Validate the RX trip point (i.e. the number of
 984          * RX frames received before a status block update is
 985          * generated and an interrupt is asserted.
 986          */
 987         if (bce_rx_quick_cons_trip_int <= 100) {
 988                 sc->bce_rx_quick_cons_trip_int =
 989                     bce_rx_quick_cons_trip_int;
 990         } else {
 991                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 992                     "hw.bce.rx_quick_cons_trip_int!  Setting default of %d.\n",
 993                     __FILE__, __LINE__, bce_rx_quick_cons_trip_int,
 994                     DEFAULT_RX_QUICK_CONS_TRIP_INT);
 995                 sc->bce_rx_quick_cons_trip_int =
 996                     DEFAULT_RX_QUICK_CONS_TRIP_INT;
 997         }
 998
 999         if (bce_rx_quick_cons_trip <= 100) {
1000                 sc->bce_rx_quick_cons_trip =
1001                     bce_rx_quick_cons_trip;
1002         } else {
1003                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
1004                     "hw.bce.rx_quick_cons_trip!  Setting default of %d.\n",
1005                     __FILE__, __LINE__, bce_rx_quick_cons_trip,
1006                     DEFAULT_RX_QUICK_CONS_TRIP);
1007                 sc->bce_rx_quick_cons_trip =
1008                     DEFAULT_RX_QUICK_CONS_TRIP;
1009         }
1010
1011         /*
1012          * Validate the RX ticks count (i.e. the maximum amount
1013          * of time to wait after the last RX frame has been
1014          * received before a status block update is generated
1015          * and an interrupt is asserted.
1016          */
1017         if (bce_rx_ticks_int <= 100) {
1018                 sc->bce_rx_ticks_int = bce_rx_ticks_int;
1019         } else {
1020                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
1021                     "hw.bce.rx_ticks_int!  Setting default of %d.\n",
1022                     __FILE__, __LINE__, bce_rx_ticks_int,
1023                     DEFAULT_RX_TICKS_INT);
1024                 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT;
1025         }
1026
1027         if (bce_rx_ticks <= 100) {
1028                 sc->bce_rx_ticks = bce_rx_ticks;
1029         } else {
1030                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
1031                     "hw.bce.rx_ticks!  Setting default of %d.\n",
1032                     __FILE__, __LINE__, bce_rx_ticks,
1033                     DEFAULT_RX_TICKS);
1034                 sc->bce_rx_ticks = DEFAULT_RX_TICKS;
1035         }
1036
1037         /* Disabling both RX ticks and RX trips will prevent interrupts. */
1038         if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) {
1039                 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and "
1040                     "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n",
1041                    __FILE__, __LINE__);
1042                 sc->bce_rx_ticks = DEFAULT_RX_TICKS;
1043                 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP;
1044         }
1045
1046         /* Disabling both TX ticks and TX trips will prevent interrupts. */
1047         if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) {
1048                 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and "
1049                     "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n",
1050                    __FILE__, __LINE__);
1051                 sc->bce_tx_ticks = DEFAULT_TX_TICKS;
1052                 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
1053         }
1054 }
1055
1056
1057 /****************************************************************************/
1058 /* Device attach function.                                                  */
1059 /*                                                                          */
1060 /* Allocates device resources, performs secondary chip identification,      */
1061 /* resets and initializes the hardware, and initializes driver instance     */
1062 /* variables.                                                               */
1063 /*                                                                          */
1064 /* Returns:                                                                 */
1065 /*   0 on success, positive value on failure.                               */
1066 /****************************************************************************/
1067 static int
1068 bce_attach(device_t dev)
1069 {
1070         struct bce_softc *sc;
1071         struct ifnet *ifp;
1072         u32 val;
1073         int count, error, rc = 0, rid;
1074
1075         sc = device_get_softc(dev);
1076         sc->bce_dev = dev;
1077
1078         DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1079
1080         sc->bce_unit = device_get_unit(dev);
1081
1082         /* Set initial device and PHY flags */
1083         sc->bce_flags = 0;
1084         sc->bce_phy_flags = 0;
1085
1086         bce_set_tunables(sc);
1087
1088         pci_enable_busmaster(dev);
1089
1090         /* Allocate PCI memory resources. */
1091         rid = PCIR_BAR(0);
1092         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1093                 &rid, RF_ACTIVE);
1094
1095         if (sc->bce_res_mem == NULL) {
1096                 BCE_PRINTF("%s(%d): PCI memory allocation failed\n",
1097                     __FILE__, __LINE__);
1098                 rc = ENXIO;
1099                 goto bce_attach_fail;
1100         }
1101
1102         /* Get various resource handles. */
1103         sc->bce_btag    = rman_get_bustag(sc->bce_res_mem);
1104         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
1105         sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem);
1106
1107         bce_probe_pci_caps(dev, sc);
1108
1109         rid = 1;
1110         count = 0;
1111 #if 0
1112         /* Try allocating MSI-X interrupts. */
1113         if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) &&
1114                 (bce_msi_enable >= 2) &&
1115                 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1116                 &rid, RF_ACTIVE)) != NULL)) {
1117
1118                 msi_needed = count = 1;
1119
1120                 if (((error = pci_alloc_msix(dev, &count)) != 0) ||
1121                         (count != msi_needed)) {
1122                         BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d,"
1123                                 "Received = %d, error = %d\n", __FILE__, __LINE__,
1124                                 msi_needed, count, error);
1125                         count = 0;
1126                         pci_release_msi(dev);
1127                         bus_release_resource(dev, SYS_RES_MEMORY, rid,
1128                                 sc->bce_res_irq);
1129                         sc->bce_res_irq = NULL;
1130                 } else {
1131                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n",
1132                                 __FUNCTION__);
1133                         sc->bce_flags |= BCE_USING_MSIX_FLAG;
1134                 }
1135         }
1136 #endif
1137
1138         /* Try allocating a MSI interrupt. */
1139         if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) &&
1140                 (bce_msi_enable >= 1) && (count == 0)) {
1141                 count = 1;
1142                 if ((error = pci_alloc_msi(dev, &count)) != 0) {
1143                         BCE_PRINTF("%s(%d): MSI allocation failed! "
1144                             "error = %d\n", __FILE__, __LINE__, error);
1145                         count = 0;
1146                         pci_release_msi(dev);
1147                 } else {
1148                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI "
1149                             "interrupt.\n", __FUNCTION__);
1150                         sc->bce_flags |= BCE_USING_MSI_FLAG;
1151                         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
1152                                 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG;
1153                         rid = 1;
1154                 }
1155         }
1156
1157         /* Try allocating a legacy interrupt. */
1158         if (count == 0) {
1159                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n",
1160                         __FUNCTION__);
1161                 rid = 0;
1162         }
1163
1164         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1165             &rid, RF_ACTIVE | (count != 0 ? 0 : RF_SHAREABLE));
1166
1167         /* Report any IRQ allocation errors. */
1168         if (sc->bce_res_irq == NULL) {
1169                 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n",
1170                     __FILE__, __LINE__);
1171                 rc = ENXIO;
1172                 goto bce_attach_fail;
1173         }
1174
1175         /* Initialize mutex for the current device instance. */
1176         BCE_LOCK_INIT(sc, device_get_nameunit(dev));
1177
1178         /*
1179          * Configure byte swap and enable indirect register access.
1180          * Rely on CPU to do target byte swapping on big endian systems.
1181          * Access to registers outside of PCI configurtion space are not
1182          * valid until this is done.
1183          */
1184         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
1185             BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
1186             BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
1187
1188         /* Save ASIC revsion info. */
1189         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
1190
1191         /* Weed out any non-production controller revisions. */
1192         switch(BCE_CHIP_ID(sc)) {
1193         case BCE_CHIP_ID_5706_A0:
1194         case BCE_CHIP_ID_5706_A1:
1195         case BCE_CHIP_ID_5708_A0:
1196         case BCE_CHIP_ID_5708_B0:
1197         case BCE_CHIP_ID_5709_A0:
1198         case BCE_CHIP_ID_5709_B0:
1199         case BCE_CHIP_ID_5709_B1:
1200         case BCE_CHIP_ID_5709_B2:
1201                 BCE_PRINTF("%s(%d): Unsupported controller "
1202                     "revision (%c%d)!\n", __FILE__, __LINE__,
1203                     (((pci_read_config(dev, PCIR_REVID, 4) &
1204                     0xf0) >> 4) + 'A'), (pci_read_config(dev,
1205                     PCIR_REVID, 4) & 0xf));
1206                 rc = ENODEV;
1207                 goto bce_attach_fail;
1208         }
1209
1210         /*
1211          * The embedded PCIe to PCI-X bridge (EPB)
1212          * in the 5708 cannot address memory above
1213          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
1214          */
1215         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
1216                 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR;
1217         else
1218                 sc->max_bus_addr = BUS_SPACE_MAXADDR;
1219
1220         /*
1221          * Find the base address for shared memory access.
1222          * Newer versions of bootcode use a signature and offset
1223          * while older versions use a fixed address.
1224          */
1225         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
1226         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG)
1227                 /* Multi-port devices use different offsets in shared memory. */
1228                 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 +
1229                     (pci_get_function(sc->bce_dev) << 2));
1230         else
1231                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
1232
1233         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n",
1234             __FUNCTION__, sc->bce_shmem_base);
1235
1236         /* Fetch the bootcode revision. */
1237         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
1238         for (int i = 0, j = 0; i < 3; i++) {
1239                 u8 num;
1240
1241                 num = (u8) (val >> (24 - (i * 8)));
1242                 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
1243                         if (num >= k || !skip0 || k == 1) {
1244                                 sc->bce_bc_ver[j++] = (num / k) + '0';
1245                                 skip0 = 0;
1246                         }
1247                 }
1248
1249                 if (i != 2)
1250                         sc->bce_bc_ver[j++] = '.';
1251         }
1252
1253         /* Check if any management firwmare is enabled. */
1254         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
1255         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
1256                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
1257
1258                 /* Allow time for firmware to enter the running state. */
1259                 for (int i = 0; i < 30; i++) {
1260                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
1261                         if (val & BCE_CONDITION_MFW_RUN_MASK)
1262                                 break;
1263                         DELAY(10000);
1264                 }
1265
1266                 /* Check if management firmware is running. */
1267                 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
1268                 val &= BCE_CONDITION_MFW_RUN_MASK;
1269                 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) &&
1270                     (val != BCE_CONDITION_MFW_RUN_NONE)) {
1271                         u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
1272                         int i = 0;
1273
1274                         /* Read the management firmware version string. */
1275                         for (int j = 0; j < 3; j++) {
1276                                 val = bce_reg_rd_ind(sc, addr + j * 4);
1277                                 val = bswap32(val);
1278                                 memcpy(&sc->bce_mfw_ver[i], &val, 4);
1279                                 i += 4;
1280                         }
1281                 } else {
1282                         /* May cause firmware synchronization timeouts. */
1283                         BCE_PRINTF("%s(%d): Management firmware enabled "
1284                             "but not running!\n", __FILE__, __LINE__);
1285                         strcpy(sc->bce_mfw_ver, "NOT RUNNING!");
1286
1287                         /* ToDo: Any action the driver should take? */
1288                 }
1289         }
1290
1291         /* Get PCI bus information (speed and type). */
1292         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
1293         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
1294                 u32 clkreg;
1295
1296                 sc->bce_flags |= BCE_PCIX_FLAG;
1297
1298                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS);
1299
1300                 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
1301                 switch (clkreg) {
1302                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
1303                         sc->bus_speed_mhz = 133;
1304                         break;
1305
1306                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
1307                         sc->bus_speed_mhz = 100;
1308                         break;
1309
1310                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
1311                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
1312                         sc->bus_speed_mhz = 66;
1313                         break;
1314
1315                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
1316                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
1317                         sc->bus_speed_mhz = 50;
1318                         break;
1319
1320                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
1321                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
1322                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
1323                         sc->bus_speed_mhz = 33;
1324                         break;
1325                 }
1326         } else {
1327                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
1328                         sc->bus_speed_mhz = 66;
1329                 else
1330                         sc->bus_speed_mhz = 33;
1331         }
1332
1333         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
1334                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
1335
1336         /* Find the media type for the adapter. */
1337         bce_get_media(sc);
1338
1339         /* Reset controller and announce to bootcode that driver is present. */
1340         if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
1341                 BCE_PRINTF("%s(%d): Controller reset failed!\n",
1342                     __FILE__, __LINE__);
1343                 rc = ENXIO;
1344                 goto bce_attach_fail;
1345         }
1346
1347         /* Initialize the controller. */
1348         if (bce_chipinit(sc)) {
1349                 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
1350                     __FILE__, __LINE__);
1351                 rc = ENXIO;
1352                 goto bce_attach_fail;
1353         }
1354
1355         /* Perform NVRAM test. */
1356         if (bce_nvram_test(sc)) {
1357                 BCE_PRINTF("%s(%d): NVRAM test failed!\n",
1358                     __FILE__, __LINE__);
1359                 rc = ENXIO;
1360                 goto bce_attach_fail;
1361         }
1362
1363         /* Fetch the permanent Ethernet MAC address. */
1364         bce_get_mac_addr(sc);
1365
1366         /* Update statistics once every second. */
1367         sc->bce_stats_ticks = 1000000 & 0xffff00;
1368
1369         /* Store data needed by PHY driver for backplane applications */
1370         sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
1371         sc->bce_port_hw_cfg   = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG);
1372
1373         /* Allocate DMA memory resources. */
1374         if (bce_dma_alloc(dev)) {
1375                 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n",
1376                     __FILE__, __LINE__);
1377                 rc = ENXIO;
1378                 goto bce_attach_fail;
1379         }
1380
1381         /* Allocate an ifnet structure. */
1382         ifp = sc->bce_ifp = if_alloc(IFT_ETHER);
1383         if (ifp == NULL) {
1384                 BCE_PRINTF("%s(%d): Interface allocation failed!\n",
1385                     __FILE__, __LINE__);
1386                 rc = ENXIO;
1387                 goto bce_attach_fail;
1388         }
1389
1390         /* Initialize the ifnet interface. */
1391         ifp->if_softc   = sc;
1392         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1393         ifp->if_flags   = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1394         ifp->if_ioctl   = bce_ioctl;
1395         ifp->if_start   = bce_start;
1396         ifp->if_get_counter = bce_get_counter;
1397         ifp->if_init    = bce_init;
1398         ifp->if_mtu     = ETHERMTU;
1399
1400         if (bce_tso_enable) {
1401                 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO;
1402                 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 |
1403                     IFCAP_VLAN_HWTSO;
1404         } else {
1405                 ifp->if_hwassist = BCE_IF_HWASSIST;
1406                 ifp->if_capabilities = BCE_IF_CAPABILITIES;
1407         }
1408
1409 #if __FreeBSD_version >= 800505
1410         /*
1411          * Introducing IFCAP_LINKSTATE didn't bump __FreeBSD_version
1412          * so it's approximate value.
1413          */
1414         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1415                 ifp->if_capabilities |= IFCAP_LINKSTATE;
1416 #endif
1417
1418         ifp->if_capenable = ifp->if_capabilities;
1419
1420         /*
1421          * Assume standard mbuf sizes for buffer allocation.
1422          * This may change later if the MTU size is set to
1423          * something other than 1500.
1424          */
1425         bce_get_rx_buffer_sizes(sc,
1426             (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN));
1427
1428         /* Recalculate our buffer allocation sizes. */
1429         ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC;
1430         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
1431         IFQ_SET_READY(&ifp->if_snd);
1432
1433         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1434                 ifp->if_baudrate = IF_Mbps(2500ULL);
1435         else
1436                 ifp->if_baudrate = IF_Mbps(1000);
1437
1438         /* Handle any special PHY initialization for SerDes PHYs. */
1439         bce_init_media(sc);
1440
1441         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
1442                 ifmedia_init(&sc->bce_ifmedia, IFM_IMASK, bce_ifmedia_upd,
1443                     bce_ifmedia_sts);
1444                 /*
1445                  * We can't manually override remote PHY's link and assume
1446                  * PHY port configuration(Fiber or TP) is not changed after
1447                  * device attach.  This may not be correct though.
1448                  */
1449                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) {
1450                         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
1451                                 ifmedia_add(&sc->bce_ifmedia,
1452                                     IFM_ETHER | IFM_2500_SX, 0, NULL);
1453                                 ifmedia_add(&sc->bce_ifmedia,
1454                                     IFM_ETHER | IFM_2500_SX | IFM_FDX, 0, NULL);
1455                         }
1456                         ifmedia_add(&sc->bce_ifmedia,
1457                             IFM_ETHER | IFM_1000_SX, 0, NULL);
1458                         ifmedia_add(&sc->bce_ifmedia,
1459                             IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL);
1460                 } else {
1461                         ifmedia_add(&sc->bce_ifmedia,
1462                             IFM_ETHER | IFM_10_T, 0, NULL);
1463                         ifmedia_add(&sc->bce_ifmedia,
1464                             IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
1465                         ifmedia_add(&sc->bce_ifmedia,
1466                             IFM_ETHER | IFM_100_TX, 0, NULL);
1467                         ifmedia_add(&sc->bce_ifmedia,
1468                             IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
1469                         ifmedia_add(&sc->bce_ifmedia,
1470                             IFM_ETHER | IFM_1000_T, 0, NULL);
1471                         ifmedia_add(&sc->bce_ifmedia,
1472                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1473                 }
1474                 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
1475                 ifmedia_set(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO);
1476                 sc->bce_ifmedia.ifm_media = sc->bce_ifmedia.ifm_cur->ifm_media;
1477         } else {
1478                 /* MII child bus by attaching the PHY. */
1479                 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd,
1480                     bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr,
1481                     MII_OFFSET_ANY, MIIF_DOPAUSE);
1482                 if (rc != 0) {
1483                         BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__,
1484                             __LINE__);
1485                         goto bce_attach_fail;
1486                 }
1487         }
1488
1489         /* Attach to the Ethernet interface list. */
1490         ether_ifattach(ifp, sc->eaddr);
1491
1492 #if __FreeBSD_version < 500000
1493         callout_init(&sc->bce_tick_callout);
1494         callout_init(&sc->bce_pulse_callout);
1495 #else
1496         callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0);
1497         callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0);
1498 #endif
1499
1500         /* Hookup IRQ last. */
1501         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE,
1502                 NULL, bce_intr, sc, &sc->bce_intrhand);
1503
1504         if (rc) {
1505                 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n",
1506                     __FILE__, __LINE__);
1507                 bce_detach(dev);
1508                 goto bce_attach_exit;
1509         }
1510
1511         /*
1512          * At this point we've acquired all the resources
1513          * we need to run so there's no turning back, we're
1514          * cleared for launch.
1515          */
1516
1517         /* Print some important debugging info. */
1518         DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc));
1519
1520         /* Add the supported sysctls to the kernel. */
1521         bce_add_sysctls(sc);
1522
1523         BCE_LOCK(sc);
1524
1525         /*
1526          * The chip reset earlier notified the bootcode that
1527          * a driver is present.  We now need to start our pulse
1528          * routine so that the bootcode is reminded that we're
1529          * still running.
1530          */
1531         bce_pulse(sc);
1532
1533         bce_mgmt_init_locked(sc);
1534         BCE_UNLOCK(sc);
1535
1536         /* Finally, print some useful adapter info */
1537         bce_print_adapter_info(sc);
1538         DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n",
1539                 __FUNCTION__, sc);
1540
1541         goto bce_attach_exit;
1542
1543 bce_attach_fail:
1544         bce_release_resources(sc);
1545
1546 bce_attach_exit:
1547
1548         DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1549
1550         return(rc);
1551 }
1552
1553
1554 /****************************************************************************/
1555 /* Device detach function.                                                  */
1556 /*                                                                          */
1557 /* Stops the controller, resets the controller, and releases resources.     */
1558 /*                                                                          */
1559 /* Returns:                                                                 */
1560 /*   0 on success, positive value on failure.                               */
1561 /****************************************************************************/
1562 static int
1563 bce_detach(device_t dev)
1564 {
1565         struct bce_softc *sc = device_get_softc(dev);
1566         struct ifnet *ifp;
1567         u32 msg;
1568
1569         DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1570
1571         ifp = sc->bce_ifp;
1572
1573         /* Stop and reset the controller. */
1574         BCE_LOCK(sc);
1575
1576         /* Stop the pulse so the bootcode can go to driver absent state. */
1577         callout_stop(&sc->bce_pulse_callout);
1578
1579         bce_stop(sc);
1580         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1581                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1582         else
1583                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1584         bce_reset(sc, msg);
1585
1586         BCE_UNLOCK(sc);
1587
1588         ether_ifdetach(ifp);
1589
1590         /* If we have a child device on the MII bus remove it too. */
1591         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1592                 ifmedia_removeall(&sc->bce_ifmedia);
1593         else {
1594                 bus_generic_detach(dev);
1595                 device_delete_child(dev, sc->bce_miibus);
1596         }
1597
1598         /* Release all remaining resources. */
1599         bce_release_resources(sc);
1600
1601         DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1602
1603         return(0);
1604 }
1605
1606
1607 /****************************************************************************/
1608 /* Device shutdown function.                                                */
1609 /*                                                                          */
1610 /* Stops and resets the controller.                                         */
1611 /*                                                                          */
1612 /* Returns:                                                                 */
1613 /*   0 on success, positive value on failure.                               */
1614 /****************************************************************************/
1615 static int
1616 bce_shutdown(device_t dev)
1617 {
1618         struct bce_softc *sc = device_get_softc(dev);
1619         u32 msg;
1620
1621         DBENTER(BCE_VERBOSE);
1622
1623         BCE_LOCK(sc);
1624         bce_stop(sc);
1625         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1626                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1627         else
1628                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1629         bce_reset(sc, msg);
1630         BCE_UNLOCK(sc);
1631
1632         DBEXIT(BCE_VERBOSE);
1633
1634         return (0);
1635 }
1636
1637
1638 #ifdef BCE_DEBUG
1639 /****************************************************************************/
1640 /* Register read.                                                           */
1641 /*                                                                          */
1642 /* Returns:                                                                 */
1643 /*   The value of the register.                                             */
1644 /****************************************************************************/
1645 static u32
1646 bce_reg_rd(struct bce_softc *sc, u32 offset)
1647 {
1648         u32 val = REG_RD(sc, offset);
1649         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1650                 __FUNCTION__, offset, val);
1651         return val;
1652 }
1653
1654
1655 /****************************************************************************/
1656 /* Register write (16 bit).                                                 */
1657 /*                                                                          */
1658 /* Returns:                                                                 */
1659 /*   Nothing.                                                               */
1660 /****************************************************************************/
1661 static void
1662 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val)
1663 {
1664         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n",
1665                 __FUNCTION__, offset, val);
1666         REG_WR16(sc, offset, val);
1667 }
1668
1669
1670 /****************************************************************************/
1671 /* Register write.                                                          */
1672 /*                                                                          */
1673 /* Returns:                                                                 */
1674 /*   Nothing.                                                               */
1675 /****************************************************************************/
1676 static void
1677 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val)
1678 {
1679         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1680                 __FUNCTION__, offset, val);
1681         REG_WR(sc, offset, val);
1682 }
1683 #endif
1684
1685 /****************************************************************************/
1686 /* Indirect register read.                                                  */
1687 /*                                                                          */
1688 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1689 /* configuration space.  Using this mechanism avoids issues with posted     */
1690 /* reads but is much slower than memory-mapped I/O.                         */
1691 /*                                                                          */
1692 /* Returns:                                                                 */
1693 /*   The value of the register.                                             */
1694 /****************************************************************************/
1695 static u32
1696 bce_reg_rd_ind(struct bce_softc *sc, u32 offset)
1697 {
1698         device_t dev;
1699         dev = sc->bce_dev;
1700
1701         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1702 #ifdef BCE_DEBUG
1703         {
1704                 u32 val;
1705                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1706                 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1707                         __FUNCTION__, offset, val);
1708                 return val;
1709         }
1710 #else
1711         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1712 #endif
1713 }
1714
1715
1716 /****************************************************************************/
1717 /* Indirect register write.                                                 */
1718 /*                                                                          */
1719 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1720 /* configuration space.  Using this mechanism avoids issues with posted     */
1721 /* writes but is muchh slower than memory-mapped I/O.                       */
1722 /*                                                                          */
1723 /* Returns:                                                                 */
1724 /*   Nothing.                                                               */
1725 /****************************************************************************/
1726 static void
1727 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val)
1728 {
1729         device_t dev;
1730         dev = sc->bce_dev;
1731
1732         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1733                 __FUNCTION__, offset, val);
1734
1735         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1736         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1737 }
1738
1739
1740 /****************************************************************************/
1741 /* Shared memory write.                                                     */
1742 /*                                                                          */
1743 /* Writes NetXtreme II shared memory region.                                */
1744 /*                                                                          */
1745 /* Returns:                                                                 */
1746 /*   Nothing.                                                               */
1747 /****************************************************************************/
1748 static void
1749 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val)
1750 {
1751         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X  to  "
1752             "0x%08X\n", __FUNCTION__, val, offset);
1753
1754         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1755 }
1756
1757
1758 /****************************************************************************/
1759 /* Shared memory read.                                                      */
1760 /*                                                                          */
1761 /* Reads NetXtreme II shared memory region.                                 */
1762 /*                                                                          */
1763 /* Returns:                                                                 */
1764 /*   The 32 bit value read.                                                 */
1765 /****************************************************************************/
1766 static u32
1767 bce_shmem_rd(struct bce_softc *sc, u32 offset)
1768 {
1769         u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1770
1771         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from "
1772             "0x%08X\n", __FUNCTION__, val, offset);
1773
1774         return val;
1775 }
1776
1777
1778 #ifdef BCE_DEBUG
1779 /****************************************************************************/
1780 /* Context memory read.                                                     */
1781 /*                                                                          */
1782 /* The NetXtreme II controller uses context memory to track connection      */
1783 /* information for L2 and higher network protocols.                         */
1784 /*                                                                          */
1785 /* Returns:                                                                 */
1786 /*   The requested 32 bit value of context memory.                          */
1787 /****************************************************************************/
1788 static u32
1789 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset)
1790 {
1791         u32 idx, offset, retry_cnt = 5, val;
1792
1793         DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 ||
1794             cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID "
1795             "address: 0x%08X.\n", __FUNCTION__, cid_addr));
1796
1797         offset = ctx_offset + cid_addr;
1798
1799         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1800
1801                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ));
1802
1803                 for (idx = 0; idx < retry_cnt; idx++) {
1804                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1805                         if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0)
1806                                 break;
1807                         DELAY(5);
1808                 }
1809
1810                 if (val & BCE_CTX_CTX_CTRL_READ_REQ)
1811                         BCE_PRINTF("%s(%d); Unable to read CTX memory: "
1812                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1813                             __FILE__, __LINE__, cid_addr, ctx_offset);
1814
1815                 val = REG_RD(sc, BCE_CTX_CTX_DATA);
1816         } else {
1817                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1818                 val = REG_RD(sc, BCE_CTX_DATA);
1819         }
1820
1821         DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1822                 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val);
1823
1824         return(val);
1825 }
1826 #endif
1827
1828
1829 /****************************************************************************/
1830 /* Context memory write.                                                    */
1831 /*                                                                          */
1832 /* The NetXtreme II controller uses context memory to track connection      */
1833 /* information for L2 and higher network protocols.                         */
1834 /*                                                                          */
1835 /* Returns:                                                                 */
1836 /*   Nothing.                                                               */
1837 /****************************************************************************/
1838 static void
1839 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val)
1840 {
1841         u32 idx, offset = ctx_offset + cid_addr;
1842         u32 val, retry_cnt = 5;
1843
1844         DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1845                 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val);
1846
1847         DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK),
1848                 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n",
1849                     __FUNCTION__, cid_addr));
1850
1851         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1852
1853                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1854                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1855
1856                 for (idx = 0; idx < retry_cnt; idx++) {
1857                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1858                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1859                                 break;
1860                         DELAY(5);
1861                 }
1862
1863                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ)
1864                         BCE_PRINTF("%s(%d); Unable to write CTX memory: "
1865                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1866                             __FILE__, __LINE__, cid_addr, ctx_offset);
1867
1868         } else {
1869                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1870                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1871         }
1872 }
1873
1874
1875 /****************************************************************************/
1876 /* PHY register read.                                                       */
1877 /*                                                                          */
1878 /* Implements register reads on the MII bus.                                */
1879 /*                                                                          */
1880 /* Returns:                                                                 */
1881 /*   The value of the register.                                             */
1882 /****************************************************************************/
1883 static int
1884 bce_miibus_read_reg(device_t dev, int phy, int reg)
1885 {
1886         struct bce_softc *sc;
1887         u32 val;
1888         int i;
1889
1890         sc = device_get_softc(dev);
1891
1892     /*
1893      * The 5709S PHY is an IEEE Clause 45 PHY
1894      * with special mappings to work with IEEE
1895      * Clause 22 register accesses.
1896      */
1897         if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1898                 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1899                         reg += 0x10;
1900         }
1901
1902     if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1903                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1904                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1905
1906                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1907                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1908
1909                 DELAY(40);
1910         }
1911
1912
1913         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1914             BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1915             BCE_EMAC_MDIO_COMM_START_BUSY;
1916         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1917
1918         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1919                 DELAY(10);
1920
1921                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1922                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1923                         DELAY(5);
1924
1925                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1926                         val &= BCE_EMAC_MDIO_COMM_DATA;
1927
1928                         break;
1929                 }
1930         }
1931
1932         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1933                 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, "
1934                     "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg);
1935                 val = 0x0;
1936         } else {
1937                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1938         }
1939
1940
1941         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1942                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1943                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1944
1945                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1946                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1947
1948                 DELAY(40);
1949         }
1950
1951         DB_PRINT_PHY_REG(reg, val);
1952         return (val & 0xffff);
1953 }
1954
1955
1956 /****************************************************************************/
1957 /* PHY register write.                                                      */
1958 /*                                                                          */
1959 /* Implements register writes on the MII bus.                               */
1960 /*                                                                          */
1961 /* Returns:                                                                 */
1962 /*   The value of the register.                                             */
1963 /****************************************************************************/
1964 static int
1965 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1966 {
1967         struct bce_softc *sc;
1968         u32 val1;
1969         int i;
1970
1971         sc = device_get_softc(dev);
1972
1973         DB_PRINT_PHY_REG(reg, val);
1974
1975         /*
1976          * The 5709S PHY is an IEEE Clause 45 PHY
1977          * with special mappings to work with IEEE
1978          * Clause 22 register accesses.
1979          */
1980         if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1981                 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1982                         reg += 0x10;
1983         }
1984
1985         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1986                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1987                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1988
1989                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1990                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1991
1992                 DELAY(40);
1993         }
1994
1995         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1996             BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1997             BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1998         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1999
2000         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
2001                 DELAY(10);
2002
2003                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
2004                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
2005                         DELAY(5);
2006                         break;
2007                 }
2008         }
2009
2010         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
2011                 BCE_PRINTF("%s(%d): PHY write timeout!\n",
2012                     __FILE__, __LINE__);
2013
2014         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
2015                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
2016                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
2017
2018                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
2019                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
2020
2021                 DELAY(40);
2022         }
2023
2024         return 0;
2025 }
2026
2027
2028 /****************************************************************************/
2029 /* MII bus status change.                                                   */
2030 /*                                                                          */
2031 /* Called by the MII bus driver when the PHY establishes link to set the    */
2032 /* MAC interface registers.                                                 */
2033 /*                                                                          */
2034 /* Returns:                                                                 */
2035 /*   Nothing.                                                               */
2036 /****************************************************************************/
2037 static void
2038 bce_miibus_statchg(device_t dev)
2039 {
2040         struct bce_softc *sc;
2041         struct mii_data *mii;
2042         struct ifmediareq ifmr;
2043         int media_active, media_status, val;
2044
2045         sc = device_get_softc(dev);
2046
2047         DBENTER(BCE_VERBOSE_PHY);
2048
2049         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
2050                 bzero(&ifmr, sizeof(ifmr));
2051                 bce_ifmedia_sts_rphy(sc, &ifmr);
2052                 media_active = ifmr.ifm_active;
2053                 media_status = ifmr.ifm_status;
2054         } else {
2055                 mii = device_get_softc(sc->bce_miibus);
2056                 media_active = mii->mii_media_active;
2057                 media_status = mii->mii_media_status;
2058         }
2059
2060         /* Ignore invalid media status. */
2061         if ((media_status & (IFM_ACTIVE | IFM_AVALID)) !=
2062             (IFM_ACTIVE | IFM_AVALID))
2063                 goto bce_miibus_statchg_exit;
2064
2065         val = REG_RD(sc, BCE_EMAC_MODE);
2066         val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX |
2067             BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK |
2068             BCE_EMAC_MODE_25G);
2069
2070         /* Set MII or GMII interface based on the PHY speed. */
2071         switch (IFM_SUBTYPE(media_active)) {
2072         case IFM_10_T:
2073                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2074                         DBPRINT(sc, BCE_INFO_PHY,
2075                             "Enabling 10Mb interface.\n");
2076                         val |= BCE_EMAC_MODE_PORT_MII_10;
2077                         break;
2078                 }
2079                 /* fall-through */
2080         case IFM_100_TX:
2081                 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n");
2082                 val |= BCE_EMAC_MODE_PORT_MII;
2083                 break;
2084         case IFM_2500_SX:
2085                 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n");
2086                 val |= BCE_EMAC_MODE_25G;
2087                 /* fall-through */
2088         case IFM_1000_T:
2089         case IFM_1000_SX:
2090                 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n");
2091                 val |= BCE_EMAC_MODE_PORT_GMII;
2092                 break;
2093         default:
2094                 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling "
2095                     "default GMII interface.\n");
2096                 val |= BCE_EMAC_MODE_PORT_GMII;
2097         }
2098
2099         /* Set half or full duplex based on PHY settings. */
2100         if ((IFM_OPTIONS(media_active) & IFM_FDX) == 0) {
2101                 DBPRINT(sc, BCE_INFO_PHY,
2102                     "Setting Half-Duplex interface.\n");
2103                 val |= BCE_EMAC_MODE_HALF_DUPLEX;
2104         } else
2105                 DBPRINT(sc, BCE_INFO_PHY,
2106                     "Setting Full-Duplex interface.\n");
2107
2108         REG_WR(sc, BCE_EMAC_MODE, val);
2109
2110         if ((IFM_OPTIONS(media_active) & IFM_ETH_RXPAUSE) != 0) {
2111                 DBPRINT(sc, BCE_INFO_PHY,
2112                     "%s(): Enabling RX flow control.\n", __FUNCTION__);
2113                 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
2114                 sc->bce_flags |= BCE_USING_RX_FLOW_CONTROL;
2115         } else {
2116                 DBPRINT(sc, BCE_INFO_PHY,
2117                     "%s(): Disabling RX flow control.\n", __FUNCTION__);
2118                 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
2119                 sc->bce_flags &= ~BCE_USING_RX_FLOW_CONTROL;
2120         }
2121
2122         if ((IFM_OPTIONS(media_active) & IFM_ETH_TXPAUSE) != 0) {
2123                 DBPRINT(sc, BCE_INFO_PHY,
2124                     "%s(): Enabling TX flow control.\n", __FUNCTION__);
2125                 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
2126                 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL;
2127         } else {
2128                 DBPRINT(sc, BCE_INFO_PHY,
2129                     "%s(): Disabling TX flow control.\n", __FUNCTION__);
2130                 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
2131                 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL;
2132         }
2133
2134         /* ToDo: Update watermarks in bce_init_rx_context(). */
2135
2136 bce_miibus_statchg_exit:
2137         DBEXIT(BCE_VERBOSE_PHY);
2138 }
2139
2140
2141 /****************************************************************************/
2142 /* Acquire NVRAM lock.                                                      */
2143 /*                                                                          */
2144 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
2145 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
2146 /* for use by the driver.                                                   */
2147 /*                                                                          */
2148 /* Returns:                                                                 */
2149 /*   0 on success, positive value on failure.                               */
2150 /****************************************************************************/
2151 static int
2152 bce_acquire_nvram_lock(struct bce_softc *sc)
2153 {
2154         u32 val;
2155         int j, rc = 0;
2156
2157         DBENTER(BCE_VERBOSE_NVRAM);
2158
2159         /* Request access to the flash interface. */
2160         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
2161         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2162                 val = REG_RD(sc, BCE_NVM_SW_ARB);
2163                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
2164                         break;
2165
2166                 DELAY(5);
2167         }
2168
2169         if (j >= NVRAM_TIMEOUT_COUNT) {
2170                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
2171                 rc = EBUSY;
2172         }
2173
2174         DBEXIT(BCE_VERBOSE_NVRAM);
2175         return (rc);
2176 }
2177
2178
2179 /****************************************************************************/
2180 /* Release NVRAM lock.                                                      */
2181 /*                                                                          */
2182 /* When the caller is finished accessing NVRAM the lock must be released.   */
2183 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
2184 /* for use by the driver.                                                   */
2185 /*                                                                          */
2186 /* Returns:                                                                 */
2187 /*   0 on success, positive value on failure.                               */
2188 /****************************************************************************/
2189 static int
2190 bce_release_nvram_lock(struct bce_softc *sc)
2191 {
2192         u32 val;
2193         int j, rc = 0;
2194
2195         DBENTER(BCE_VERBOSE_NVRAM);
2196
2197         /*
2198          * Relinquish nvram interface.
2199          */
2200         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
2201
2202         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2203                 val = REG_RD(sc, BCE_NVM_SW_ARB);
2204                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
2205                         break;
2206
2207                 DELAY(5);
2208         }
2209
2210         if (j >= NVRAM_TIMEOUT_COUNT) {
2211                 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n");
2212                 rc = EBUSY;
2213         }
2214
2215         DBEXIT(BCE_VERBOSE_NVRAM);
2216         return (rc);
2217 }
2218
2219
2220 #ifdef BCE_NVRAM_WRITE_SUPPORT
2221 /****************************************************************************/
2222 /* Enable NVRAM write access.                                               */
2223 /*                                                                          */
2224 /* Before writing to NVRAM the caller must enable NVRAM writes.             */
2225 /*                                                                          */
2226 /* Returns:                                                                 */
2227 /*   0 on success, positive value on failure.                               */
2228 /****************************************************************************/
2229 static int
2230 bce_enable_nvram_write(struct bce_softc *sc)
2231 {
2232         u32 val;
2233         int rc = 0;
2234
2235         DBENTER(BCE_VERBOSE_NVRAM);
2236
2237         val = REG_RD(sc, BCE_MISC_CFG);
2238         REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);
2239
2240         if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2241                 int j;
2242
2243                 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2244                 REG_WR(sc, BCE_NVM_COMMAND,     BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT);
2245
2246                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2247                         DELAY(5);
2248
2249                         val = REG_RD(sc, BCE_NVM_COMMAND);
2250                         if (val & BCE_NVM_COMMAND_DONE)
2251                                 break;
2252                 }
2253
2254                 if (j >= NVRAM_TIMEOUT_COUNT) {
2255                         DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n");
2256                         rc = EBUSY;
2257                 }
2258         }
2259
2260         DBENTER(BCE_VERBOSE_NVRAM);
2261         return (rc);
2262 }
2263
2264
2265 /****************************************************************************/
2266 /* Disable NVRAM write access.                                              */
2267 /*                                                                          */
2268 /* When the caller is finished writing to NVRAM write access must be        */
2269 /* disabled.                                                                */
2270 /*                                                                          */
2271 /* Returns:                                                                 */
2272 /*   Nothing.                                                               */
2273 /****************************************************************************/
2274 static void
2275 bce_disable_nvram_write(struct bce_softc *sc)
2276 {
2277         u32 val;
2278
2279         DBENTER(BCE_VERBOSE_NVRAM);
2280
2281         val = REG_RD(sc, BCE_MISC_CFG);
2282         REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);
2283
2284         DBEXIT(BCE_VERBOSE_NVRAM);
2285
2286 }
2287 #endif
2288
2289
2290 /****************************************************************************/
2291 /* Enable NVRAM access.                                                     */
2292 /*                                                                          */
2293 /* Before accessing NVRAM for read or write operations the caller must      */
2294 /* enabled NVRAM access.                                                    */
2295 /*                                                                          */
2296 /* Returns:                                                                 */
2297 /*   Nothing.                                                               */
2298 /****************************************************************************/
2299 static void
2300 bce_enable_nvram_access(struct bce_softc *sc)
2301 {
2302         u32 val;
2303
2304         DBENTER(BCE_VERBOSE_NVRAM);
2305
2306         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
2307         /* Enable both bits, even on read. */
2308         REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val |
2309             BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
2310
2311         DBEXIT(BCE_VERBOSE_NVRAM);
2312 }
2313
2314
2315 /****************************************************************************/
2316 /* Disable NVRAM access.                                                    */
2317 /*                                                                          */
2318 /* When the caller is finished accessing NVRAM access must be disabled.     */
2319 /*                                                                          */
2320 /* Returns:                                                                 */
2321 /*   Nothing.                                                               */
2322 /****************************************************************************/
2323 static void
2324 bce_disable_nvram_access(struct bce_softc *sc)
2325 {
2326         u32 val;
2327
2328         DBENTER(BCE_VERBOSE_NVRAM);
2329
2330         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
2331
2332         /* Disable both bits, even after read. */
2333         REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val &
2334             ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
2335
2336         DBEXIT(BCE_VERBOSE_NVRAM);
2337 }
2338
2339
2340 #ifdef BCE_NVRAM_WRITE_SUPPORT
2341 /****************************************************************************/
2342 /* Erase NVRAM page before writing.                                         */
2343 /*                                                                          */
2344 /* Non-buffered flash parts require that a page be erased before it is      */
2345 /* written.                                                                 */
2346 /*                                                                          */
2347 /* Returns:                                                                 */
2348 /*   0 on success, positive value on failure.                               */
2349 /****************************************************************************/
2350 static int
2351 bce_nvram_erase_page(struct bce_softc *sc, u32 offset)
2352 {
2353         u32 cmd;
2354         int j, rc = 0;
2355
2356         DBENTER(BCE_VERBOSE_NVRAM);
2357
2358         /* Buffered flash doesn't require an erase. */
2359         if (sc->bce_flash_info->flags & BCE_NV_BUFFERED)
2360                 goto bce_nvram_erase_page_exit;
2361
2362         /* Build an erase command. */
2363         cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR |
2364             BCE_NVM_COMMAND_DOIT;
2365
2366         /*
2367          * Clear the DONE bit separately, set the NVRAM address to erase,
2368          * and issue the erase command.
2369          */
2370         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2371         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2372         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2373
2374         /* Wait for completion. */
2375         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2376                 u32 val;
2377
2378                 DELAY(5);
2379
2380                 val = REG_RD(sc, BCE_NVM_COMMAND);
2381                 if (val & BCE_NVM_COMMAND_DONE)
2382                         break;
2383         }
2384
2385         if (j >= NVRAM_TIMEOUT_COUNT) {
2386                 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n");
2387                 rc = EBUSY;
2388         }
2389
2390 bce_nvram_erase_page_exit:
2391         DBEXIT(BCE_VERBOSE_NVRAM);
2392         return (rc);
2393 }
2394 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2395
2396
2397 /****************************************************************************/
2398 /* Read a dword (32 bits) from NVRAM.                                       */
2399 /*                                                                          */
2400 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
2401 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
2402 /*                                                                          */
2403 /* Returns:                                                                 */
2404 /*   0 on success and the 32 bit value read, positive value on failure.     */
2405 /****************************************************************************/
2406 static int
2407 bce_nvram_read_dword(struct bce_softc *sc,
2408     u32 offset, u8 *ret_val, u32 cmd_flags)
2409 {
2410         u32 cmd;
2411         int i, rc = 0;
2412
2413         DBENTER(BCE_EXTREME_NVRAM);
2414
2415         /* Build the command word. */
2416         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
2417
2418         /* Calculate the offset for buffered flash if translation is used. */
2419         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2420                 offset = ((offset / sc->bce_flash_info->page_size) <<
2421                     sc->bce_flash_info->page_bits) +
2422                     (offset % sc->bce_flash_info->page_size);
2423         }
2424
2425         /*
2426          * Clear the DONE bit separately, set the address to read,
2427          * and issue the read.
2428          */
2429         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2430         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2431         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2432
2433         /* Wait for completion. */
2434         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
2435                 u32 val;
2436
2437                 DELAY(5);
2438
2439                 val = REG_RD(sc, BCE_NVM_COMMAND);
2440                 if (val & BCE_NVM_COMMAND_DONE) {
2441                         val = REG_RD(sc, BCE_NVM_READ);
2442
2443                         val = bce_be32toh(val);
2444                         memcpy(ret_val, &val, 4);
2445                         break;
2446                 }
2447         }
2448
2449         /* Check for errors. */
2450         if (i >= NVRAM_TIMEOUT_COUNT) {
2451                 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at "
2452                     "offset 0x%08X!\n", __FILE__, __LINE__, offset);
2453                 rc = EBUSY;
2454         }
2455
2456         DBEXIT(BCE_EXTREME_NVRAM);
2457         return(rc);
2458 }
2459
2460
2461 #ifdef BCE_NVRAM_WRITE_SUPPORT
2462 /****************************************************************************/
2463 /* Write a dword (32 bits) to NVRAM.                                        */
2464 /*                                                                          */
2465 /* Write a 32 bit word to NVRAM.  The caller is assumed to have already     */
2466 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and    */
2467 /* enabled NVRAM write access.                                              */
2468 /*                                                                          */
2469 /* Returns:                                                                 */
2470 /*   0 on success, positive value on failure.                               */
2471 /****************************************************************************/
2472 static int
2473 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val,
2474         u32 cmd_flags)
2475 {
2476         u32 cmd, val32;
2477         int j, rc = 0;
2478
2479         DBENTER(BCE_VERBOSE_NVRAM);
2480
2481         /* Build the command word. */
2482         cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags;
2483
2484         /* Calculate the offset for buffered flash if translation is used. */
2485         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2486                 offset = ((offset / sc->bce_flash_info->page_size) <<
2487                     sc->bce_flash_info->page_bits) +
2488                     (offset % sc->bce_flash_info->page_size);
2489         }
2490
2491         /*
2492          * Clear the DONE bit separately, convert NVRAM data to big-endian,
2493          * set the NVRAM address to write, and issue the write command
2494          */
2495         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2496         memcpy(&val32, val, 4);
2497         val32 = htobe32(val32);
2498         REG_WR(sc, BCE_NVM_WRITE, val32);
2499         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2500         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2501
2502         /* Wait for completion. */
2503         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2504                 DELAY(5);
2505
2506                 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE)
2507                         break;
2508         }
2509         if (j >= NVRAM_TIMEOUT_COUNT) {
2510                 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at "
2511                     "offset 0x%08X\n", __FILE__, __LINE__, offset);
2512                 rc = EBUSY;
2513         }
2514
2515         DBEXIT(BCE_VERBOSE_NVRAM);
2516         return (rc);
2517 }
2518 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2519
2520
2521 /****************************************************************************/
2522 /* Initialize NVRAM access.                                                 */
2523 /*                                                                          */
2524 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
2525 /* access that device.                                                      */
2526 /*                                                                          */
2527 /* Returns:                                                                 */
2528 /*   0 on success, positive value on failure.                               */
2529 /****************************************************************************/
2530 static int
2531 bce_init_nvram(struct bce_softc *sc)
2532 {
2533         u32 val;
2534         int j, entry_count, rc = 0;
2535         const struct flash_spec *flash;
2536
2537         DBENTER(BCE_VERBOSE_NVRAM);
2538
2539         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
2540                 sc->bce_flash_info = &flash_5709;
2541                 goto bce_init_nvram_get_flash_size;
2542         }
2543
2544         /* Determine the selected interface. */
2545         val = REG_RD(sc, BCE_NVM_CFG1);
2546
2547         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2548
2549         /*
2550          * Flash reconfiguration is required to support additional
2551          * NVRAM devices not directly supported in hardware.
2552          * Check if the flash interface was reconfigured
2553          * by the bootcode.
2554          */
2555
2556         if (val & 0x40000000) {
2557                 /* Flash interface reconfigured by bootcode. */
2558
2559                 DBPRINT(sc,BCE_INFO_LOAD,
2560                         "bce_init_nvram(): Flash WAS reconfigured.\n");
2561
2562                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2563                      j++, flash++) {
2564                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
2565                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2566                                 sc->bce_flash_info = flash;
2567                                 break;
2568                         }
2569                 }
2570         } else {
2571                 /* Flash interface not yet reconfigured. */
2572                 u32 mask;
2573
2574                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n",
2575                         __FUNCTION__);
2576
2577                 if (val & (1 << 23))
2578                         mask = FLASH_BACKUP_STRAP_MASK;
2579                 else
2580                         mask = FLASH_STRAP_MASK;
2581
2582                 /* Look for the matching NVRAM device configuration data. */
2583                 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) {
2584
2585                         /* Check if the device matches any of the known devices. */
2586                         if ((val & mask) == (flash->strapping & mask)) {
2587                                 /* Found a device match. */
2588                                 sc->bce_flash_info = flash;
2589
2590                                 /* Request access to the flash interface. */
2591                                 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2592                                         return rc;
2593
2594                                 /* Reconfigure the flash interface. */
2595                                 bce_enable_nvram_access(sc);
2596                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
2597                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
2598                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
2599                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
2600                                 bce_disable_nvram_access(sc);
2601                                 bce_release_nvram_lock(sc);
2602
2603                                 break;
2604                         }
2605                 }
2606         }
2607
2608         /* Check if a matching device was found. */
2609         if (j == entry_count) {
2610                 sc->bce_flash_info = NULL;
2611                 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n",
2612                     __FILE__, __LINE__);
2613                 DBEXIT(BCE_VERBOSE_NVRAM);
2614                 return (ENODEV);
2615         }
2616
2617 bce_init_nvram_get_flash_size:
2618         /* Write the flash config data to the shared memory interface. */
2619         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2);
2620         val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
2621         if (val)
2622                 sc->bce_flash_size = val;
2623         else
2624                 sc->bce_flash_size = sc->bce_flash_info->total_size;
2625
2626         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n",
2627             __FUNCTION__, sc->bce_flash_info->name,
2628             sc->bce_flash_info->total_size);
2629
2630         DBEXIT(BCE_VERBOSE_NVRAM);
2631         return rc;
2632 }
2633
2634
2635 /****************************************************************************/
2636 /* Read an arbitrary range of data from NVRAM.                              */
2637 /*                                                                          */
2638 /* Prepares the NVRAM interface for access and reads the requested data     */
2639 /* into the supplied buffer.                                                */
2640 /*                                                                          */
2641 /* Returns:                                                                 */
2642 /*   0 on success and the data read, positive value on failure.             */
2643 /****************************************************************************/
2644 static int
2645 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf,
2646         int buf_size)
2647 {
2648         int rc = 0;
2649         u32 cmd_flags, offset32, len32, extra;
2650
2651         DBENTER(BCE_VERBOSE_NVRAM);
2652
2653         if (buf_size == 0)
2654                 goto bce_nvram_read_exit;
2655
2656         /* Request access to the flash interface. */
2657         if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2658                 goto bce_nvram_read_exit;
2659
2660         /* Enable access to flash interface */
2661         bce_enable_nvram_access(sc);
2662
2663         len32 = buf_size;
2664         offset32 = offset;
2665         extra = 0;
2666
2667         cmd_flags = 0;
2668
2669         if (offset32 & 3) {
2670                 u8 buf[4];
2671                 u32 pre_len;
2672
2673                 offset32 &= ~3;
2674                 pre_len = 4 - (offset & 3);
2675
2676                 if (pre_len >= len32) {
2677                         pre_len = len32;
2678                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
2679                 }
2680                 else {
2681                         cmd_flags = BCE_NVM_COMMAND_FIRST;
2682                 }
2683
2684                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2685
2686                 if (rc)
2687                         return rc;
2688
2689                 memcpy(ret_buf, buf + (offset & 3), pre_len);
2690
2691                 offset32 += 4;
2692                 ret_buf += pre_len;
2693                 len32 -= pre_len;
2694         }
2695
2696         if (len32 & 3) {
2697                 extra = 4 - (len32 & 3);
2698                 len32 = (len32 + 4) & ~3;
2699         }
2700
2701         if (len32 == 4) {
2702                 u8 buf[4];
2703
2704                 if (cmd_flags)
2705                         cmd_flags = BCE_NVM_COMMAND_LAST;
2706                 else
2707                         cmd_flags = BCE_NVM_COMMAND_FIRST |
2708                                     BCE_NVM_COMMAND_LAST;
2709
2710                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2711
2712                 memcpy(ret_buf, buf, 4 - extra);
2713         }
2714         else if (len32 > 0) {
2715                 u8 buf[4];
2716
2717                 /* Read the first word. */
2718                 if (cmd_flags)
2719                         cmd_flags = 0;
2720                 else
2721                         cmd_flags = BCE_NVM_COMMAND_FIRST;
2722
2723                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
2724
2725                 /* Advance to the next dword. */
2726                 offset32 += 4;
2727                 ret_buf += 4;
2728                 len32 -= 4;
2729
2730                 while (len32 > 4 && rc == 0) {
2731                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
2732
2733                         /* Advance to the next dword. */
2734                         offset32 += 4;
2735                         ret_buf += 4;
2736                         len32 -= 4;
2737                 }
2738
2739                 if (rc)
2740                         goto bce_nvram_read_locked_exit;
2741
2742                 cmd_flags = BCE_NVM_COMMAND_LAST;
2743                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2744
2745                 memcpy(ret_buf, buf, 4 - extra);
2746         }
2747
2748 bce_nvram_read_locked_exit:
2749         /* Disable access to flash interface and release the lock. */
2750         bce_disable_nvram_access(sc);
2751         bce_release_nvram_lock(sc);
2752
2753 bce_nvram_read_exit:
2754         DBEXIT(BCE_VERBOSE_NVRAM);
2755         return rc;
2756 }
2757
2758
2759 #ifdef BCE_NVRAM_WRITE_SUPPORT
2760 /****************************************************************************/
2761 /* Write an arbitrary range of data from NVRAM.                             */
2762 /*                                                                          */
2763 /* Prepares the NVRAM interface for write access and writes the requested   */
2764 /* data from the supplied buffer.  The caller is responsible for            */
2765 /* calculating any appropriate CRCs.                                        */
2766 /*                                                                          */
2767 /* Returns:                                                                 */
2768 /*   0 on success, positive value on failure.                               */
2769 /****************************************************************************/
2770 static int
2771 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf,
2772         int buf_size)
2773 {
2774         u32 written, offset32, len32;
2775         u8 *buf, start[4], end[4];
2776         int rc = 0;
2777         int align_start, align_end;
2778
2779         DBENTER(BCE_VERBOSE_NVRAM);
2780
2781         buf = data_buf;
2782         offset32 = offset;
2783         len32 = buf_size;
2784         align_start = align_end = 0;
2785
2786         if ((align_start = (offset32 & 3))) {
2787                 offset32 &= ~3;
2788                 len32 += align_start;
2789                 if ((rc = bce_nvram_read(sc, offset32, start, 4)))
2790                         goto bce_nvram_write_exit;
2791         }
2792
2793         if (len32 & 3) {
2794                 if ((len32 > 4) || !align_start) {
2795                         align_end = 4 - (len32 & 3);
2796                         len32 += align_end;
2797                         if ((rc = bce_nvram_read(sc, offset32 + len32 - 4,
2798                                 end, 4))) {
2799                                 goto bce_nvram_write_exit;
2800                         }
2801                 }
2802         }
2803
2804         if (align_start || align_end) {
2805                 buf = malloc(len32, M_DEVBUF, M_NOWAIT);
2806                 if (buf == NULL) {
2807                         rc = ENOMEM;
2808                         goto bce_nvram_write_exit;
2809                 }
2810
2811                 if (align_start) {
2812                         memcpy(buf, start, 4);
2813                 }
2814
2815                 if (align_end) {
2816                         memcpy(buf + len32 - 4, end, 4);
2817                 }
2818                 memcpy(buf + align_start, data_buf, buf_size);
2819         }
2820
2821         written = 0;
2822         while ((written < len32) && (rc == 0)) {
2823                 u32 page_start, page_end, data_start, data_end;
2824                 u32 addr, cmd_flags;
2825                 int i;
2826                 u8 flash_buffer[264];
2827
2828             /* Find the page_start addr */
2829                 page_start = offset32 + written;
2830                 page_start -= (page_start % sc->bce_flash_info->page_size);
2831                 /* Find the page_end addr */
2832                 page_end = page_start + sc->bce_flash_info->page_size;
2833                 /* Find the data_start addr */
2834                 data_start = (written == 0) ? offset32 : page_start;
2835                 /* Find the data_end addr */
2836                 data_end = (page_end > offset32 + len32) ?
2837                         (offset32 + len32) : page_end;
2838
2839                 /* Request access to the flash interface. */
2840                 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2841                         goto bce_nvram_write_exit;
2842
2843                 /* Enable access to flash interface */
2844                 bce_enable_nvram_access(sc);
2845
2846                 cmd_flags = BCE_NVM_COMMAND_FIRST;
2847                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2848                         int j;
2849
2850                         /* Read the whole page into the buffer
2851                          * (non-buffer flash only) */
2852                         for (j = 0; j < sc->bce_flash_info->page_size; j += 4) {
2853                                 if (j == (sc->bce_flash_info->page_size - 4)) {
2854                                         cmd_flags |= BCE_NVM_COMMAND_LAST;
2855                                 }
2856                                 rc = bce_nvram_read_dword(sc,
2857                                         page_start + j,
2858                                         &flash_buffer[j],
2859                                         cmd_flags);
2860
2861                                 if (rc)
2862                                         goto bce_nvram_write_locked_exit;
2863
2864                                 cmd_flags = 0;
2865                         }
2866                 }
2867
2868                 /* Enable writes to flash interface (unlock write-protect) */
2869                 if ((rc = bce_enable_nvram_write(sc)) != 0)
2870                         goto bce_nvram_write_locked_exit;
2871
2872                 /* Erase the page */
2873                 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0)
2874                         goto bce_nvram_write_locked_exit;
2875
2876                 /* Re-enable the write again for the actual write */
2877                 bce_enable_nvram_write(sc);
2878
2879                 /* Loop to write back the buffer data from page_start to
2880                  * data_start */
2881                 i = 0;
2882                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2883                         for (addr = page_start; addr < data_start;
2884                                 addr += 4, i += 4) {
2885
2886                                 rc = bce_nvram_write_dword(sc, addr,
2887                                         &flash_buffer[i], cmd_flags);
2888
2889                                 if (rc != 0)
2890                                         goto bce_nvram_write_locked_exit;
2891
2892                                 cmd_flags = 0;
2893                         }
2894                 }
2895
2896                 /* Loop to write the new data from data_start to data_end */
2897                 for (addr = data_start; addr < data_end; addr += 4, i++) {
2898                         if ((addr == page_end - 4) ||
2899                                 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) &&
2900                                 (addr == data_end - 4))) {
2901
2902                                 cmd_flags |= BCE_NVM_COMMAND_LAST;
2903                         }
2904                         rc = bce_nvram_write_dword(sc, addr, buf,
2905                                 cmd_flags);
2906
2907                         if (rc != 0)
2908                                 goto bce_nvram_write_locked_exit;
2909
2910                         cmd_flags = 0;
2911                         buf += 4;
2912                 }
2913
2914                 /* Loop to write back the buffer data from data_end
2915                  * to page_end */
2916                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2917                         for (addr = data_end; addr < page_end;
2918                                 addr += 4, i += 4) {
2919
2920                                 if (addr == page_end-4) {
2921                                         cmd_flags = BCE_NVM_COMMAND_LAST;
2922                                 }
2923                                 rc = bce_nvram_write_dword(sc, addr,
2924                                         &flash_buffer[i], cmd_flags);
2925
2926                                 if (rc != 0)
2927                                         goto bce_nvram_write_locked_exit;
2928
2929                                 cmd_flags = 0;
2930                         }
2931                 }
2932
2933                 /* Disable writes to flash interface (lock write-protect) */
2934                 bce_disable_nvram_write(sc);
2935
2936                 /* Disable access to flash interface */
2937                 bce_disable_nvram_access(sc);
2938                 bce_release_nvram_lock(sc);
2939
2940                 /* Increment written */
2941                 written += data_end - data_start;
2942         }
2943
2944         goto bce_nvram_write_exit;
2945
2946 bce_nvram_write_locked_exit:
2947         bce_disable_nvram_write(sc);
2948         bce_disable_nvram_access(sc);
2949         bce_release_nvram_lock(sc);
2950
2951 bce_nvram_write_exit:
2952         if (align_start || align_end)
2953                 free(buf, M_DEVBUF);
2954
2955         DBEXIT(BCE_VERBOSE_NVRAM);
2956         return (rc);
2957 }
2958 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2959
2960
2961 /****************************************************************************/
2962 /* Verifies that NVRAM is accessible and contains valid data.               */
2963 /*                                                                          */
2964 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
2965 /* correct.                                                                 */
2966 /*                                                                          */
2967 /* Returns:                                                                 */
2968 /*   0 on success, positive value on failure.                               */
2969 /****************************************************************************/
2970 static int
2971 bce_nvram_test(struct bce_softc *sc)
2972 {
2973         u32 buf[BCE_NVRAM_SIZE / 4];
2974         u8 *data = (u8 *) buf;
2975         int rc = 0;
2976         u32 magic, csum;
2977
2978         DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
2979
2980         /*
2981          * Check that the device NVRAM is valid by reading
2982          * the magic value at offset 0.
2983          */
2984         if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) {
2985                 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n",
2986                     __FILE__, __LINE__);
2987                 goto bce_nvram_test_exit;
2988         }
2989
2990         /*
2991          * Verify that offset 0 of the NVRAM contains
2992          * a valid magic number.
2993          */
2994         magic = bce_be32toh(buf[0]);
2995         if (magic != BCE_NVRAM_MAGIC) {
2996                 rc = ENODEV;
2997                 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! "
2998                     "Expected: 0x%08X, Found: 0x%08X\n",
2999                     __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic);
3000                 goto bce_nvram_test_exit;
3001         }
3002
3003         /*
3004          * Verify that the device NVRAM includes valid
3005          * configuration data.
3006          */
3007         if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) {
3008                 BCE_PRINTF("%s(%d): Unable to read manufacturing "
3009                     "Information from  NVRAM!\n", __FILE__, __LINE__);
3010                 goto bce_nvram_test_exit;
3011         }
3012
3013         csum = ether_crc32_le(data, 0x100);
3014         if (csum != BCE_CRC32_RESIDUAL) {
3015                 rc = ENODEV;
3016                 BCE_PRINTF("%s(%d): Invalid manufacturing information "
3017                     "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n",
3018                     __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum);
3019                 goto bce_nvram_test_exit;
3020         }
3021
3022         csum = ether_crc32_le(data + 0x100, 0x100);
3023         if (csum != BCE_CRC32_RESIDUAL) {
3024                 rc = ENODEV;
3025                 BCE_PRINTF("%s(%d): Invalid feature configuration "
3026                     "information NVRAM CRC! Expected: 0x%08X, "
3027                     "Found: 08%08X\n", __FILE__, __LINE__,
3028                     BCE_CRC32_RESIDUAL, csum);
3029         }
3030
3031 bce_nvram_test_exit:
3032         DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
3033         return rc;
3034 }
3035
3036
3037 /****************************************************************************/
3038 /* Calculates the size of the buffers to allocate based on the MTU.         */
3039 /*                                                                          */
3040 /* Returns:                                                                 */
3041 /*   Nothing.                                                               */
3042 /****************************************************************************/
3043 static void
3044 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu)
3045 {
3046         DBENTER(BCE_VERBOSE_LOAD);
3047
3048         /* Use a single allocation type when header splitting enabled. */
3049         if (bce_hdr_split == TRUE) {
3050                 sc->rx_bd_mbuf_alloc_size = MHLEN;
3051                 /* Make sure offset is 16 byte aligned for hardware. */
3052                 sc->rx_bd_mbuf_align_pad =
3053                         roundup2(MSIZE - MHLEN, 16) - (MSIZE - MHLEN);
3054                 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
3055                         sc->rx_bd_mbuf_align_pad;
3056         } else {
3057                 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
3058                     ETHER_CRC_LEN) > MCLBYTES) {
3059                         /* Setup for jumbo RX buffer allocations. */
3060                         sc->rx_bd_mbuf_alloc_size = MJUM9BYTES;
3061                         sc->rx_bd_mbuf_align_pad  =
3062                                 roundup2(MJUM9BYTES, 16) - MJUM9BYTES;
3063                         sc->rx_bd_mbuf_data_len =
3064                             sc->rx_bd_mbuf_alloc_size -
3065                             sc->rx_bd_mbuf_align_pad;
3066                 } else {
3067                         /* Setup for standard RX buffer allocations. */
3068                         sc->rx_bd_mbuf_alloc_size = MCLBYTES;
3069                         sc->rx_bd_mbuf_align_pad  =
3070                             roundup2(MCLBYTES, 16) - MCLBYTES;
3071                         sc->rx_bd_mbuf_data_len =
3072                             sc->rx_bd_mbuf_alloc_size -
3073                             sc->rx_bd_mbuf_align_pad;
3074                 }
3075         }
3076
3077 //      DBPRINT(sc, BCE_INFO_LOAD,
3078         DBPRINT(sc, BCE_WARN,
3079            "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, "
3080            "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__,
3081            sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len,
3082            sc->rx_bd_mbuf_align_pad);
3083
3084         DBEXIT(BCE_VERBOSE_LOAD);
3085 }
3086
3087 /****************************************************************************/
3088 /* Identifies the current media type of the controller and sets the PHY     */
3089 /* address.                                                                 */
3090 /*                                                                          */
3091 /* Returns:                                                                 */
3092 /*   Nothing.                                                               */
3093 /****************************************************************************/
3094 static void
3095 bce_get_media(struct bce_softc *sc)
3096 {
3097         u32 val;
3098
3099         DBENTER(BCE_VERBOSE_PHY);
3100
3101         /* Assume PHY address for copper controllers. */
3102         sc->bce_phy_addr = 1;
3103
3104         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3105                 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
3106                 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
3107                 u32 strap;
3108
3109                 /*
3110                  * The BCM5709S is software configurable
3111                  * for Copper or SerDes operation.
3112                  */
3113                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
3114                         DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
3115                             "for copper.\n");
3116                         goto bce_get_media_exit;
3117                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
3118                         DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
3119                             "for dual media.\n");
3120                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3121                         goto bce_get_media_exit;
3122                 }
3123
3124                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
3125                         strap = (val &
3126                             BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
3127                 else
3128                         strap = (val &
3129                             BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
3130
3131                 if (pci_get_function(sc->bce_dev) == 0) {
3132                         switch (strap) {
3133                         case 0x4:
3134                         case 0x5:
3135                         case 0x6:
3136                                 DBPRINT(sc, BCE_INFO_LOAD,
3137                                     "BCM5709 s/w configured for SerDes.\n");
3138                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3139                                 break;
3140                         default:
3141                                 DBPRINT(sc, BCE_INFO_LOAD,
3142                                     "BCM5709 s/w configured for Copper.\n");
3143                                 break;
3144                         }
3145                 } else {
3146                         switch (strap) {
3147                         case 0x1:
3148                         case 0x2:
3149                         case 0x4:
3150                                 DBPRINT(sc, BCE_INFO_LOAD,
3151                                     "BCM5709 s/w configured for SerDes.\n");
3152                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3153                                 break;
3154                         default:
3155                                 DBPRINT(sc, BCE_INFO_LOAD,
3156                                     "BCM5709 s/w configured for Copper.\n");
3157                                 break;
3158                         }
3159                 }
3160
3161         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT)
3162                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3163
3164         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
3165
3166                 sc->bce_flags |= BCE_NO_WOL_FLAG;
3167
3168                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
3169                         sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG;
3170
3171                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
3172                         /* 5708S/09S/16S use a separate PHY for SerDes. */
3173                         sc->bce_phy_addr = 2;
3174
3175                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
3176                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G) {
3177                                 sc->bce_phy_flags |=
3178                                     BCE_PHY_2_5G_CAPABLE_FLAG;
3179                                 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb "
3180                                     "capable adapter\n");
3181                         }
3182                 }
3183         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
3184             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708))
3185                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
3186
3187 bce_get_media_exit:
3188         DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY),
3189                 "Using PHY address %d.\n", sc->bce_phy_addr);
3190
3191         DBEXIT(BCE_VERBOSE_PHY);
3192 }
3193
3194
3195 /****************************************************************************/
3196 /* Performs PHY initialization required before MII drivers access the       */
3197 /* device.                                                                  */
3198 /*                                                                          */
3199 /* Returns:                                                                 */
3200 /*   Nothing.                                                               */
3201 /****************************************************************************/
3202 static void
3203 bce_init_media(struct bce_softc *sc)
3204 {
3205         if ((sc->bce_phy_flags & (BCE_PHY_IEEE_CLAUSE_45_FLAG |
3206             BCE_PHY_REMOTE_CAP_FLAG)) == BCE_PHY_IEEE_CLAUSE_45_FLAG) {
3207                 /*
3208                  * Configure 5709S/5716S PHYs to use traditional IEEE
3209                  * Clause 22 method. Otherwise we have no way to attach
3210                  * the PHY in mii(4) layer. PHY specific configuration
3211                  * is done in mii layer.
3212                  */
3213
3214                 /* Select auto-negotiation MMD of the PHY. */
3215                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3216                     BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT);
3217                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3218                     BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD);
3219
3220                 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */
3221                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3222                     BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
3223         }
3224 }
3225
3226
3227 /****************************************************************************/
3228 /* Free any DMA memory owned by the driver.                                 */
3229 /*                                                                          */
3230 /* Scans through each data structre that requires DMA memory and frees      */
3231 /* the memory if allocated.                                                 */
3232 /*                                                                          */
3233 /* Returns:                                                                 */
3234 /*   Nothing.                                                               */
3235 /****************************************************************************/
3236 static void
3237 bce_dma_free(struct bce_softc *sc)
3238 {
3239         int i;
3240
3241         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
3242
3243         /* Free, unmap, and destroy the status block. */
3244         if (sc->status_block_paddr != 0) {
3245                 bus_dmamap_unload(
3246                     sc->status_tag,
3247                     sc->status_map);
3248                 sc->status_block_paddr = 0;
3249         }
3250
3251         if (sc->status_block != NULL) {
3252                 bus_dmamem_free(
3253                    sc->status_tag,
3254                     sc->status_block,
3255                     sc->status_map);
3256                 sc->status_block = NULL;
3257         }
3258
3259         if (sc->status_tag != NULL) {
3260                 bus_dma_tag_destroy(sc->status_tag);
3261                 sc->status_tag = NULL;
3262         }
3263
3264
3265         /* Free, unmap, and destroy the statistics block. */
3266         if (sc->stats_block_paddr != 0) {
3267                 bus_dmamap_unload(
3268                     sc->stats_tag,
3269                     sc->stats_map);
3270                 sc->stats_block_paddr = 0;
3271         }
3272
3273         if (sc->stats_block != NULL) {
3274                 bus_dmamem_free(
3275                     sc->stats_tag,
3276                     sc->stats_block,
3277                     sc->stats_map);
3278                 sc->stats_block = NULL;
3279         }
3280
3281         if (sc->stats_tag != NULL) {
3282                 bus_dma_tag_destroy(sc->stats_tag);
3283                 sc->stats_tag = NULL;
3284         }
3285
3286
3287         /* Free, unmap and destroy all context memory pages. */
3288         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3289                 for (i = 0; i < sc->ctx_pages; i++ ) {
3290                         if (sc->ctx_paddr[i] != 0) {
3291                                 bus_dmamap_unload(
3292                                     sc->ctx_tag,
3293                                     sc->ctx_map[i]);
3294                                 sc->ctx_paddr[i] = 0;
3295                         }
3296
3297                         if (sc->ctx_block[i] != NULL) {
3298                                 bus_dmamem_free(
3299                                     sc->ctx_tag,
3300                                     sc->ctx_block[i],
3301                                     sc->ctx_map[i]);
3302                                 sc->ctx_block[i] = NULL;
3303                         }
3304                 }
3305
3306                 /* Destroy the context memory tag. */
3307                 if (sc->ctx_tag != NULL) {
3308                         bus_dma_tag_destroy(sc->ctx_tag);
3309                         sc->ctx_tag = NULL;
3310                 }
3311         }
3312
3313
3314         /* Free, unmap and destroy all TX buffer descriptor chain pages. */
3315         for (i = 0; i < sc->tx_pages; i++ ) {
3316                 if (sc->tx_bd_chain_paddr[i] != 0) {
3317                         bus_dmamap_unload(
3318                             sc->tx_bd_chain_tag,
3319                             sc->tx_bd_chain_map[i]);
3320                         sc->tx_bd_chain_paddr[i] = 0;
3321                 }
3322
3323                 if (sc->tx_bd_chain[i] != NULL) {
3324                         bus_dmamem_free(
3325                             sc->tx_bd_chain_tag,
3326                             sc->tx_bd_chain[i],
3327                             sc->tx_bd_chain_map[i]);
3328                         sc->tx_bd_chain[i] = NULL;
3329                 }
3330         }
3331
3332         /* Destroy the TX buffer descriptor tag. */
3333         if (sc->tx_bd_chain_tag != NULL) {
3334                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
3335                 sc->tx_bd_chain_tag = NULL;
3336         }
3337
3338
3339         /* Free, unmap and destroy all RX buffer descriptor chain pages. */
3340         for (i = 0; i < sc->rx_pages; i++ ) {
3341                 if (sc->rx_bd_chain_paddr[i] != 0) {
3342                         bus_dmamap_unload(
3343                             sc->rx_bd_chain_tag,
3344                             sc->rx_bd_chain_map[i]);
3345                         sc->rx_bd_chain_paddr[i] = 0;
3346                 }
3347
3348                 if (sc->rx_bd_chain[i] != NULL) {
3349                         bus_dmamem_free(
3350                             sc->rx_bd_chain_tag,
3351                             sc->rx_bd_chain[i],
3352                             sc->rx_bd_chain_map[i]);
3353                         sc->rx_bd_chain[i] = NULL;
3354                 }
3355         }
3356
3357         /* Destroy the RX buffer descriptor tag. */
3358         if (sc->rx_bd_chain_tag != NULL) {
3359                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
3360                 sc->rx_bd_chain_tag = NULL;
3361         }
3362
3363
3364         /* Free, unmap and destroy all page buffer descriptor chain pages. */
3365         if (bce_hdr_split == TRUE) {
3366                 for (i = 0; i < sc->pg_pages; i++ ) {
3367                         if (sc->pg_bd_chain_paddr[i] != 0) {
3368                                 bus_dmamap_unload(
3369                                     sc->pg_bd_chain_tag,
3370                                     sc->pg_bd_chain_map[i]);
3371                                 sc->pg_bd_chain_paddr[i] = 0;
3372                         }
3373
3374                         if (sc->pg_bd_chain[i] != NULL) {
3375                                 bus_dmamem_free(
3376                                     sc->pg_bd_chain_tag,
3377                                     sc->pg_bd_chain[i],
3378                                     sc->pg_bd_chain_map[i]);
3379                                 sc->pg_bd_chain[i] = NULL;
3380                         }
3381                 }
3382
3383                 /* Destroy the page buffer descriptor tag. */
3384                 if (sc->pg_bd_chain_tag != NULL) {
3385                         bus_dma_tag_destroy(sc->pg_bd_chain_tag);
3386                         sc->pg_bd_chain_tag = NULL;
3387                 }
3388         }
3389
3390
3391         /* Unload and destroy the TX mbuf maps. */
3392         for (i = 0; i < MAX_TX_BD_AVAIL; i++) {
3393                 if (sc->tx_mbuf_map[i] != NULL) {
3394                         bus_dmamap_unload(sc->tx_mbuf_tag,
3395                             sc->tx_mbuf_map[i]);
3396                         bus_dmamap_destroy(sc->tx_mbuf_tag,
3397                             sc->tx_mbuf_map[i]);
3398                         sc->tx_mbuf_map[i] = NULL;
3399                 }
3400         }
3401
3402         /* Destroy the TX mbuf tag. */
3403         if (sc->tx_mbuf_tag != NULL) {
3404                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
3405                 sc->tx_mbuf_tag = NULL;
3406         }
3407
3408         /* Unload and destroy the RX mbuf maps. */
3409         for (i = 0; i < MAX_RX_BD_AVAIL; i++) {
3410                 if (sc->rx_mbuf_map[i] != NULL) {
3411                         bus_dmamap_unload(sc->rx_mbuf_tag,
3412                             sc->rx_mbuf_map[i]);
3413                         bus_dmamap_destroy(sc->rx_mbuf_tag,
3414                             sc->rx_mbuf_map[i]);
3415                         sc->rx_mbuf_map[i] = NULL;
3416                 }
3417         }
3418
3419         /* Destroy the RX mbuf tag. */
3420         if (sc->rx_mbuf_tag != NULL) {
3421                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
3422                 sc->rx_mbuf_tag = NULL;
3423         }
3424
3425         /* Unload and destroy the page mbuf maps. */
3426         if (bce_hdr_split == TRUE) {
3427                 for (i = 0; i < MAX_PG_BD_AVAIL; i++) {
3428                         if (sc->pg_mbuf_map[i] != NULL) {
3429                                 bus_dmamap_unload(sc->pg_mbuf_tag,
3430                                     sc->pg_mbuf_map[i]);
3431                                 bus_dmamap_destroy(sc->pg_mbuf_tag,
3432                                     sc->pg_mbuf_map[i]);
3433                                 sc->pg_mbuf_map[i] = NULL;
3434                         }
3435                 }
3436
3437                 /* Destroy the page mbuf tag. */
3438                 if (sc->pg_mbuf_tag != NULL) {
3439                         bus_dma_tag_destroy(sc->pg_mbuf_tag);
3440                         sc->pg_mbuf_tag = NULL;
3441                 }
3442         }
3443
3444         /* Destroy the parent tag */
3445         if (sc->parent_tag != NULL) {
3446                 bus_dma_tag_destroy(sc->parent_tag);
3447                 sc->parent_tag = NULL;
3448         }
3449
3450         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
3451 }
3452
3453
3454 /****************************************************************************/
3455 /* Get DMA memory from the OS.                                              */
3456 /*                                                                          */
3457 /* Validates that the OS has provided DMA buffers in response to a          */
3458 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
3459 /* When the callback is used the OS will return 0 for the mapping function  */
3460 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
3461 /* failures back to the caller.                                             */
3462 /*                                                                          */
3463 /* Returns:                                                                 */
3464 /*   Nothing.                                                               */
3465 /****************************************************************************/
3466 static void
3467 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3468 {
3469         bus_addr_t *busaddr = arg;
3470
3471         KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!",
3472             __FUNCTION__, nseg));
3473         /* Simulate a mapping failure. */
3474         DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control),
3475             error = ENOMEM);
3476
3477         /* ToDo: How to increment debug sim_count variable here? */
3478
3479         /* Check for an error and signal the caller that an error occurred. */
3480         if (error) {
3481                 *busaddr = 0;
3482         } else {
3483                 *busaddr = segs->ds_addr;
3484         }
3485 }
3486
3487
3488 /****************************************************************************/
3489 /* Allocate any DMA memory needed by the driver.                            */
3490 /*                                                                          */
3491 /* Allocates DMA memory needed for the various global structures needed by  */
3492 /* hardware.                                                                */
3493 /*                                                                          */
3494 /* Memory alignment requirements:                                           */
3495 /* +-----------------+----------+----------+----------+----------+          */
3496 /* |                 |   5706   |   5708   |   5709   |   5716   |          */
3497 /* +-----------------+----------+----------+----------+----------+          */
3498 /* |Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |          */
3499 /* |Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |          */
3500 /* |RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |          */
3501 /* |PG Buffers       |   none   |   none   |   none   |   none   |          */
3502 /* |TX Buffers       |   none   |   none   |   none   |   none   |          */
3503 /* |Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |          */
3504 /* |Context Memory   |          |          |          |          |          */
3505 /* +-----------------+----------+----------+----------+----------+          */
3506 /*                                                                          */
3507 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
3508 /*                                                                          */
3509 /* Returns:                                                                 */
3510 /*   0 for success, positive value for failure.                             */
3511 /****************************************************************************/
3512 static int
3513 bce_dma_alloc(device_t dev)
3514 {
3515         struct bce_softc *sc;
3516         int i, error, rc = 0;
3517         bus_size_t max_size, max_seg_size;
3518         int max_segments;
3519
3520         sc = device_get_softc(dev);
3521
3522         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3523
3524         /*
3525          * Allocate the parent bus DMA tag appropriate for PCI.
3526          */
3527         if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY,
3528             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3529             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
3530             &sc->parent_tag)) {
3531                 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n",
3532                     __FILE__, __LINE__);
3533                 rc = ENOMEM;
3534                 goto bce_dma_alloc_exit;
3535         }
3536
3537         /*
3538          * Create a DMA tag for the status block, allocate and clear the
3539          * memory, map the memory into DMA space, and fetch the physical
3540          * address of the block.
3541          */
3542         if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3543             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3544             NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ,
3545             0, NULL, NULL, &sc->status_tag)) {
3546                 BCE_PRINTF("%s(%d): Could not allocate status block "
3547                     "DMA tag!\n", __FILE__, __LINE__);
3548                 rc = ENOMEM;
3549                 goto bce_dma_alloc_exit;
3550         }
3551
3552         if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block,
3553             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3554             &sc->status_map)) {
3555                 BCE_PRINTF("%s(%d): Could not allocate status block "
3556                     "DMA memory!\n", __FILE__, __LINE__);
3557                 rc = ENOMEM;
3558                 goto bce_dma_alloc_exit;
3559         }
3560
3561         error = bus_dmamap_load(sc->status_tag, sc->status_map,
3562             sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr,
3563             &sc->status_block_paddr, BUS_DMA_NOWAIT);
3564
3565         if (error || sc->status_block_paddr == 0) {
3566                 BCE_PRINTF("%s(%d): Could not map status block "
3567                     "DMA memory!\n", __FILE__, __LINE__);
3568                 rc = ENOMEM;
3569                 goto bce_dma_alloc_exit;
3570         }
3571
3572         DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n",
3573             __FUNCTION__, (uintmax_t) sc->status_block_paddr);
3574
3575         /*
3576          * Create a DMA tag for the statistics block, allocate and clear the
3577          * memory, map the memory into DMA space, and fetch the physical
3578          * address of the block.
3579          */
3580         if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3581             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3582             NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ,
3583             0, NULL, NULL, &sc->stats_tag)) {
3584                 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3585                     "DMA tag!\n", __FILE__, __LINE__);
3586                 rc = ENOMEM;
3587                 goto bce_dma_alloc_exit;
3588         }
3589
3590         if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block,
3591             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) {
3592                 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3593                     "DMA memory!\n", __FILE__, __LINE__);
3594                 rc = ENOMEM;
3595                 goto bce_dma_alloc_exit;
3596         }
3597
3598         error = bus_dmamap_load(sc->stats_tag, sc->stats_map,
3599             sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr,
3600             &sc->stats_block_paddr, BUS_DMA_NOWAIT);
3601
3602         if (error || sc->stats_block_paddr == 0) {
3603                 BCE_PRINTF("%s(%d): Could not map statistics block "
3604                     "DMA memory!\n", __FILE__, __LINE__);
3605                 rc = ENOMEM;
3606                 goto bce_dma_alloc_exit;
3607         }
3608
3609         DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n",
3610             __FUNCTION__, (uintmax_t) sc->stats_block_paddr);
3611
3612         /* BCM5709 uses host memory as cache for context memory. */
3613         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3614                 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
3615                 if (sc->ctx_pages == 0)
3616                         sc->ctx_pages = 1;
3617
3618                 DBRUNIF((sc->ctx_pages > 512),
3619                     BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n",
3620                     __FILE__, __LINE__, sc->ctx_pages));
3621
3622                 /*
3623                  * Create a DMA tag for the context pages,
3624                  * allocate and clear the memory, map the
3625                  * memory into DMA space, and fetch the
3626                  * physical address of the block.
3627                  */
3628                 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3629                     BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3630                     NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
3631                     0, NULL, NULL, &sc->ctx_tag)) {
3632                         BCE_PRINTF("%s(%d): Could not allocate CTX "
3633                             "DMA tag!\n", __FILE__, __LINE__);
3634                         rc = ENOMEM;
3635                         goto bce_dma_alloc_exit;
3636                 }
3637
3638                 for (i = 0; i < sc->ctx_pages; i++) {
3639
3640                         if(bus_dmamem_alloc(sc->ctx_tag,
3641                             (void **)&sc->ctx_block[i],
3642                             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3643                             &sc->ctx_map[i])) {
3644                                 BCE_PRINTF("%s(%d): Could not allocate CTX "
3645                                     "DMA memory!\n", __FILE__, __LINE__);
3646                                 rc = ENOMEM;
3647                                 goto bce_dma_alloc_exit;
3648                         }
3649
3650                         error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
3651                             sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr,
3652                             &sc->ctx_paddr[i], BUS_DMA_NOWAIT);
3653
3654                         if (error || sc->ctx_paddr[i] == 0) {
3655                                 BCE_PRINTF("%s(%d): Could not map CTX "
3656                                     "DMA memory!\n", __FILE__, __LINE__);
3657                                 rc = ENOMEM;
3658                                 goto bce_dma_alloc_exit;
3659                         }
3660
3661                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] "
3662                             "= 0x%jX\n", __FUNCTION__, i,
3663                             (uintmax_t) sc->ctx_paddr[i]);
3664                 }
3665         }
3666
3667         /*
3668          * Create a DMA tag for the TX buffer descriptor chain,
3669          * allocate and clear the  memory, and fetch the
3670          * physical address of the block.
3671          */
3672         if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY,
3673             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3674             BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0,
3675             NULL, NULL, &sc->tx_bd_chain_tag)) {
3676                 BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3677                     "chain DMA tag!\n", __FILE__, __LINE__);
3678                 rc = ENOMEM;
3679                 goto bce_dma_alloc_exit;
3680         }
3681
3682         for (i = 0; i < sc->tx_pages; i++) {
3683
3684                 if(bus_dmamem_alloc(sc->tx_bd_chain_tag,
3685                     (void **)&sc->tx_bd_chain[i],
3686                     BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3687                     &sc->tx_bd_chain_map[i])) {
3688                         BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3689                             "chain DMA memory!\n", __FILE__, __LINE__);
3690                         rc = ENOMEM;
3691                         goto bce_dma_alloc_exit;
3692                 }
3693
3694                 error = bus_dmamap_load(sc->tx_bd_chain_tag,
3695                     sc->tx_bd_chain_map[i], sc->tx_bd_chain[i],
3696                     BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3697                     &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3698
3699                 if (error || sc->tx_bd_chain_paddr[i] == 0) {
3700                         BCE_PRINTF("%s(%d): Could not map TX descriptor "
3701                             "chain DMA memory!\n", __FILE__, __LINE__);
3702                         rc = ENOMEM;
3703                         goto bce_dma_alloc_exit;
3704                 }
3705
3706                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = "
3707                     "0x%jX\n", __FUNCTION__, i,
3708                     (uintmax_t) sc->tx_bd_chain_paddr[i]);
3709         }
3710
3711         /* Check the required size before mapping to conserve resources. */
3712         if (bce_tso_enable) {
3713                 max_size     = BCE_TSO_MAX_SIZE;
3714                 max_segments = BCE_MAX_SEGMENTS;
3715                 max_seg_size = BCE_TSO_MAX_SEG_SIZE;
3716         } else {
3717                 max_size     = MCLBYTES * BCE_MAX_SEGMENTS;
3718                 max_segments = BCE_MAX_SEGMENTS;
3719                 max_seg_size = MCLBYTES;
3720         }
3721
3722         /* Create a DMA tag for TX mbufs. */
3723         if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3724             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size,
3725             max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) {
3726                 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n",
3727                     __FILE__, __LINE__);
3728                 rc = ENOMEM;
3729                 goto bce_dma_alloc_exit;
3730         }
3731
3732         /* Create DMA maps for the TX mbufs clusters. */
3733         for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) {
3734                 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT,
3735                         &sc->tx_mbuf_map[i])) {
3736                         BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA "
3737                             "map!\n", __FILE__, __LINE__);
3738                         rc = ENOMEM;
3739                         goto bce_dma_alloc_exit;
3740                 }
3741         }
3742
3743         /*
3744          * Create a DMA tag for the RX buffer descriptor chain,
3745          * allocate and clear the memory, and fetch the physical
3746          * address of the blocks.
3747          */
3748         if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3749                         BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR,
3750                         sc->max_bus_addr, NULL, NULL,
3751                         BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
3752                         0, NULL, NULL, &sc->rx_bd_chain_tag)) {
3753                 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain "
3754                     "DMA tag!\n", __FILE__, __LINE__);
3755                 rc = ENOMEM;
3756                 goto bce_dma_alloc_exit;
3757         }
3758
3759         for (i = 0; i < sc->rx_pages; i++) {
3760
3761                 if (bus_dmamem_alloc(sc->rx_bd_chain_tag,
3762                     (void **)&sc->rx_bd_chain[i],
3763                     BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3764                     &sc->rx_bd_chain_map[i])) {
3765                         BCE_PRINTF("%s(%d): Could not allocate RX descriptor "
3766                             "chain DMA memory!\n", __FILE__, __LINE__);
3767                         rc = ENOMEM;
3768                         goto bce_dma_alloc_exit;
3769                 }
3770
3771                 error = bus_dmamap_load(sc->rx_bd_chain_tag,
3772                     sc->rx_bd_chain_map[i], sc->rx_bd_chain[i],
3773                     BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3774                     &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3775
3776                 if (error || sc->rx_bd_chain_paddr[i] == 0) {
3777                         BCE_PRINTF("%s(%d): Could not map RX descriptor "
3778                             "chain DMA memory!\n", __FILE__, __LINE__);
3779                         rc = ENOMEM;
3780                         goto bce_dma_alloc_exit;
3781                 }
3782
3783                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = "
3784                     "0x%jX\n", __FUNCTION__, i,
3785                     (uintmax_t) sc->rx_bd_chain_paddr[i]);
3786         }
3787
3788         /*
3789          * Create a DMA tag for RX mbufs.
3790          */
3791         if (bce_hdr_split == TRUE)
3792                 max_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ?
3793                     MCLBYTES : sc->rx_bd_mbuf_alloc_size);
3794         else
3795                 max_size = MJUM9BYTES;
3796
3797         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag "
3798             "(max size = 0x%jX)\n", __FUNCTION__, (uintmax_t)max_size);
3799
3800         if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN,
3801             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3802             max_size, 1, max_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) {
3803                 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n",
3804                     __FILE__, __LINE__);
3805                 rc = ENOMEM;
3806                 goto bce_dma_alloc_exit;
3807         }
3808
3809         /* Create DMA maps for the RX mbuf clusters. */
3810         for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) {
3811                 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT,
3812                     &sc->rx_mbuf_map[i])) {
3813                         BCE_PRINTF("%s(%d): Unable to create RX mbuf "
3814                             "DMA map!\n", __FILE__, __LINE__);
3815                         rc = ENOMEM;
3816                         goto bce_dma_alloc_exit;
3817                 }
3818         }
3819
3820         if (bce_hdr_split == TRUE) {
3821                 /*
3822                  * Create a DMA tag for the page buffer descriptor chain,
3823                  * allocate and clear the memory, and fetch the physical
3824                  * address of the blocks.
3825                  */
3826                 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3827                             BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr,
3828                             NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ,
3829                             0, NULL, NULL, &sc->pg_bd_chain_tag)) {
3830                         BCE_PRINTF("%s(%d): Could not allocate page descriptor "
3831                             "chain DMA tag!\n", __FILE__, __LINE__);
3832                         rc = ENOMEM;
3833                         goto bce_dma_alloc_exit;
3834                 }
3835
3836                 for (i = 0; i < sc->pg_pages; i++) {
3837                         if (bus_dmamem_alloc(sc->pg_bd_chain_tag,
3838                             (void **)&sc->pg_bd_chain[i],
3839                             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3840                             &sc->pg_bd_chain_map[i])) {
3841                                 BCE_PRINTF("%s(%d): Could not allocate page "
3842                                     "descriptor chain DMA memory!\n",
3843                                     __FILE__, __LINE__);
3844                                 rc = ENOMEM;
3845                                 goto bce_dma_alloc_exit;
3846                         }
3847
3848                         error = bus_dmamap_load(sc->pg_bd_chain_tag,
3849                             sc->pg_bd_chain_map[i], sc->pg_bd_chain[i],
3850                             BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr,
3851                             &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3852
3853                         if (error || sc->pg_bd_chain_paddr[i] == 0) {
3854                                 BCE_PRINTF("%s(%d): Could not map page descriptor "
3855                                         "chain DMA memory!\n", __FILE__, __LINE__);
3856                                 rc = ENOMEM;
3857                                 goto bce_dma_alloc_exit;
3858                         }
3859
3860                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = "
3861                                 "0x%jX\n", __FUNCTION__, i,
3862                                 (uintmax_t) sc->pg_bd_chain_paddr[i]);
3863                 }
3864
3865                 /*
3866                  * Create a DMA tag for page mbufs.
3867                  */
3868                 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3869                     sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
3870                     1, MCLBYTES, 0, NULL, NULL, &sc->pg_mbuf_tag)) {
3871                         BCE_PRINTF("%s(%d): Could not allocate page mbuf "
3872                                 "DMA tag!\n", __FILE__, __LINE__);
3873                         rc = ENOMEM;
3874                         goto bce_dma_alloc_exit;
3875                 }
3876
3877                 /* Create DMA maps for the page mbuf clusters. */
3878                 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) {
3879                         if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT,
3880                                 &sc->pg_mbuf_map[i])) {
3881                                 BCE_PRINTF("%s(%d): Unable to create page mbuf "
3882                                         "DMA map!\n", __FILE__, __LINE__);
3883                                 rc = ENOMEM;
3884                                 goto bce_dma_alloc_exit;
3885                         }
3886                 }
3887         }
3888
3889 bce_dma_alloc_exit:
3890         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3891         return(rc);
3892 }
3893
3894
3895 /****************************************************************************/
3896 /* Release all resources used by the driver.                                */
3897 /*                                                                          */
3898 /* Releases all resources acquired by the driver including interrupts,      */
3899 /* interrupt handler, interfaces, mutexes, and DMA memory.                  */
3900 /*                                                                          */
3901 /* Returns:                                                                 */
3902 /*   Nothing.                                                               */
3903 /****************************************************************************/
3904 static void
3905 bce_release_resources(struct bce_softc *sc)
3906 {
3907         device_t dev;
3908
3909         DBENTER(BCE_VERBOSE_RESET);
3910
3911         dev = sc->bce_dev;
3912
3913         bce_dma_free(sc);
3914
3915         if (sc->bce_intrhand != NULL) {
3916                 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n");
3917                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
3918         }
3919
3920         if (sc->bce_res_irq != NULL) {
3921                 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n");
3922                 bus_release_resource(dev, SYS_RES_IRQ,
3923                     rman_get_rid(sc->bce_res_irq), sc->bce_res_irq);
3924         }
3925
3926         if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) {
3927                 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n");
3928                 pci_release_msi(dev);
3929         }
3930
3931         if (sc->bce_res_mem != NULL) {
3932                 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n");
3933                     bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
3934                     sc->bce_res_mem);
3935         }
3936
3937         if (sc->bce_ifp != NULL) {
3938                 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n");
3939                 if_free(sc->bce_ifp);
3940         }
3941
3942         if (mtx_initialized(&sc->bce_mtx))
3943                 BCE_LOCK_DESTROY(sc);
3944
3945         DBEXIT(BCE_VERBOSE_RESET);
3946 }
3947
3948
3949 /****************************************************************************/
3950 /* Firmware synchronization.                                                */
3951 /*                                                                          */
3952 /* Before performing certain events such as a chip reset, synchronize with  */
3953 /* the firmware first.                                                      */
3954 /*                                                                          */
3955 /* Returns:                                                                 */
3956 /*   0 for success, positive value for failure.                             */
3957 /****************************************************************************/
3958 static int
3959 bce_fw_sync(struct bce_softc *sc, u32 msg_data)
3960 {
3961         int i, rc = 0;
3962         u32 val;
3963
3964         DBENTER(BCE_VERBOSE_RESET);
3965
3966         /* Don't waste any time if we've timed out before. */
3967         if (sc->bce_fw_timed_out == TRUE) {
3968                 rc = EBUSY;
3969                 goto bce_fw_sync_exit;
3970         }
3971
3972         /* Increment the message sequence number. */
3973         sc->bce_fw_wr_seq++;
3974         msg_data |= sc->bce_fw_wr_seq;
3975
3976         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = "
3977             "0x%08X\n", msg_data);
3978
3979         /* Send the message to the bootcode driver mailbox. */
3980         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
3981
3982         /* Wait for the bootcode to acknowledge the message. */
3983         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
3984                 /* Check for a response in the bootcode firmware mailbox. */
3985                 val = bce_shmem_rd(sc, BCE_FW_MB);
3986                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
3987                         break;
3988                 DELAY(1000);
3989         }
3990
3991         /* If we've timed out, tell bootcode that we've stopped waiting. */
3992         if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) &&
3993             ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) {
3994
3995                 BCE_PRINTF("%s(%d): Firmware synchronization timeout! "
3996                     "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data);
3997
3998                 msg_data &= ~BCE_DRV_MSG_CODE;
3999                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
4000
4001                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
4002
4003                 sc->bce_fw_timed_out = TRUE;
4004                 rc = EBUSY;
4005         }
4006
4007 bce_fw_sync_exit:
4008         DBEXIT(BCE_VERBOSE_RESET);
4009         return (rc);
4010 }
4011
4012
4013 /****************************************************************************/
4014 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
4015 /*                                                                          */
4016 /* Returns:                                                                 */
4017 /*   Nothing.                                                               */
4018 /****************************************************************************/
4019 static void
4020 bce_load_rv2p_fw(struct bce_softc *sc, const u32 *rv2p_code,
4021         u32 rv2p_code_len, u32 rv2p_proc)
4022 {
4023         int i;
4024         u32 val;
4025
4026         DBENTER(BCE_VERBOSE_RESET);
4027
4028         /* Set the page size used by RV2P. */
4029         if (rv2p_proc == RV2P_PROC2) {
4030                 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE);
4031         }
4032
4033         for (i = 0; i < rv2p_code_len; i += 8) {
4034                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
4035                 rv2p_code++;
4036                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
4037                 rv2p_code++;
4038
4039                 if (rv2p_proc == RV2P_PROC1) {
4040                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
4041                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
4042                 }
4043                 else {
4044                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
4045                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
4046                 }
4047         }
4048
4049         /* Reset the processor, un-stall is done later. */
4050         if (rv2p_proc == RV2P_PROC1) {
4051                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
4052         }
4053         else {
4054                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
4055         }
4056
4057         DBEXIT(BCE_VERBOSE_RESET);
4058 }
4059
4060
4061 /****************************************************************************/
4062 /* Load RISC processor firmware.                                            */
4063 /*                                                                          */
4064 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
4065 /* associated with a particular processor.                                  */
4066 /*                                                                          */
4067 /* Returns:                                                                 */
4068 /*   Nothing.                                                               */
4069 /****************************************************************************/
4070 static void
4071 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
4072         struct fw_info *fw)
4073 {
4074         u32 offset;
4075
4076         DBENTER(BCE_VERBOSE_RESET);
4077
4078     bce_halt_cpu(sc, cpu_reg);
4079
4080         /* Load the Text area. */
4081         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
4082         if (fw->text) {
4083                 int j;
4084
4085                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
4086                         REG_WR_IND(sc, offset, fw->text[j]);
4087                 }
4088         }
4089
4090         /* Load the Data area. */
4091         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
4092         if (fw->data) {
4093                 int j;
4094
4095                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
4096                         REG_WR_IND(sc, offset, fw->data[j]);
4097                 }
4098         }
4099
4100         /* Load the SBSS area. */
4101         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
4102         if (fw->sbss) {
4103                 int j;
4104
4105                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
4106                         REG_WR_IND(sc, offset, fw->sbss[j]);
4107                 }
4108         }
4109
4110         /* Load the BSS area. */
4111         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
4112         if (fw->bss) {
4113                 int j;
4114
4115                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
4116                         REG_WR_IND(sc, offset, fw->bss[j]);
4117                 }
4118         }
4119
4120         /* Load the Read-Only area. */
4121         offset = cpu_reg->spad_base +
4122                 (fw->rodata_addr - cpu_reg->mips_view_base);
4123         if (fw->rodata) {
4124                 int j;
4125
4126                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
4127                         REG_WR_IND(sc, offset, fw->rodata[j]);
4128                 }
4129         }
4130
4131         /* Clear the pre-fetch instruction and set the FW start address. */
4132         REG_WR_IND(sc, cpu_reg->inst, 0);
4133         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
4134
4135         DBEXIT(BCE_VERBOSE_RESET);
4136 }
4137
4138
4139 /****************************************************************************/
4140 /* Starts the RISC processor.                                               */
4141 /*                                                                          */
4142 /* Assumes the CPU starting address has already been set.                   */
4143 /*                                                                          */
4144 /* Returns:                                                                 */
4145 /*   Nothing.                                                               */
4146 /****************************************************************************/
4147 static void
4148 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4149 {
4150         u32 val;
4151
4152         DBENTER(BCE_VERBOSE_RESET);
4153
4154         /* Start the CPU. */
4155         val = REG_RD_IND(sc, cpu_reg->mode);
4156         val &= ~cpu_reg->mode_value_halt;
4157         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4158         REG_WR_IND(sc, cpu_reg->mode, val);
4159
4160         DBEXIT(BCE_VERBOSE_RESET);
4161 }
4162
4163
4164 /****************************************************************************/
4165 /* Halts the RISC processor.                                                */
4166 /*                                                                          */
4167 /* Returns:                                                                 */
4168 /*   Nothing.                                                               */
4169 /****************************************************************************/
4170 static void
4171 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4172 {
4173         u32 val;
4174
4175         DBENTER(BCE_VERBOSE_RESET);
4176
4177         /* Halt the CPU. */
4178         val = REG_RD_IND(sc, cpu_reg->mode);
4179         val |= cpu_reg->mode_value_halt;
4180         REG_WR_IND(sc, cpu_reg->mode, val);
4181         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4182
4183         DBEXIT(BCE_VERBOSE_RESET);
4184 }
4185
4186
4187 /****************************************************************************/
4188 /* Initialize the RX CPU.                                                   */
4189 /*                                                                          */
4190 /* Returns:                                                                 */
4191 /*   Nothing.                                                               */
4192 /****************************************************************************/
4193 static void
4194 bce_start_rxp_cpu(struct bce_softc *sc)
4195 {
4196         struct cpu_reg cpu_reg;
4197
4198         DBENTER(BCE_VERBOSE_RESET);
4199
4200         cpu_reg.mode = BCE_RXP_CPU_MODE;
4201         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4202         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4203         cpu_reg.state = BCE_RXP_CPU_STATE;
4204         cpu_reg.state_value_clear = 0xffffff;
4205         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4206         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4207         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4208         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4209         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4210         cpu_reg.spad_base = BCE_RXP_SCRATCH;
4211         cpu_reg.mips_view_base = 0x8000000;
4212
4213         DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n");
4214         bce_start_cpu(sc, &cpu_reg);
4215
4216         DBEXIT(BCE_VERBOSE_RESET);
4217 }
4218
4219
4220 /****************************************************************************/
4221 /* Initialize the RX CPU.                                                   */
4222 /*                                                                          */
4223 /* Returns:                                                                 */
4224 /*   Nothing.                                                               */
4225 /****************************************************************************/
4226 static void
4227 bce_init_rxp_cpu(struct bce_softc *sc)
4228 {
4229         struct cpu_reg cpu_reg;
4230         struct fw_info fw;
4231
4232         DBENTER(BCE_VERBOSE_RESET);
4233
4234         cpu_reg.mode = BCE_RXP_CPU_MODE;
4235         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4236         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4237         cpu_reg.state = BCE_RXP_CPU_STATE;
4238         cpu_reg.state_value_clear = 0xffffff;
4239         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4240         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4241         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4242         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4243         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4244         cpu_reg.spad_base = BCE_RXP_SCRATCH;
4245         cpu_reg.mips_view_base = 0x8000000;
4246
4247         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4248                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
4249                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
4250                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
4251                 fw.start_addr = bce_RXP_b09FwStartAddr;
4252
4253                 fw.text_addr = bce_RXP_b09FwTextAddr;
4254                 fw.text_len = bce_RXP_b09FwTextLen;
4255                 fw.text_index = 0;
4256                 fw.text = bce_RXP_b09FwText;
4257
4258                 fw.data_addr = bce_RXP_b09FwDataAddr;
4259                 fw.data_len = bce_RXP_b09FwDataLen;
4260                 fw.data_index = 0;
4261                 fw.data = bce_RXP_b09FwData;
4262
4263                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
4264                 fw.sbss_len = bce_RXP_b09FwSbssLen;
4265                 fw.sbss_index = 0;
4266                 fw.sbss = bce_RXP_b09FwSbss;
4267
4268                 fw.bss_addr = bce_RXP_b09FwBssAddr;
4269                 fw.bss_len = bce_RXP_b09FwBssLen;
4270                 fw.bss_index = 0;
4271                 fw.bss = bce_RXP_b09FwBss;
4272
4273                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
4274                 fw.rodata_len = bce_RXP_b09FwRodataLen;
4275                 fw.rodata_index = 0;
4276                 fw.rodata = bce_RXP_b09FwRodata;
4277         } else {
4278                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
4279                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
4280                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
4281                 fw.start_addr = bce_RXP_b06FwStartAddr;
4282
4283                 fw.text_addr = bce_RXP_b06FwTextAddr;
4284                 fw.text_len = bce_RXP_b06FwTextLen;
4285                 fw.text_index = 0;
4286                 fw.text = bce_RXP_b06FwText;
4287
4288                 fw.data_addr = bce_RXP_b06FwDataAddr;
4289                 fw.data_len = bce_RXP_b06FwDataLen;
4290                 fw.data_index = 0;
4291                 fw.data = bce_RXP_b06FwData;
4292
4293                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
4294                 fw.sbss_len = bce_RXP_b06FwSbssLen;
4295                 fw.sbss_index = 0;
4296                 fw.sbss = bce_RXP_b06FwSbss;
4297
4298                 fw.bss_addr = bce_RXP_b06FwBssAddr;
4299                 fw.bss_len = bce_RXP_b06FwBssLen;
4300                 fw.bss_index = 0;
4301                 fw.bss = bce_RXP_b06FwBss;
4302
4303                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
4304                 fw.rodata_len = bce_RXP_b06FwRodataLen;
4305                 fw.rodata_index = 0;
4306                 fw.rodata = bce_RXP_b06FwRodata;
4307         }
4308
4309         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
4310         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4311
4312     /* Delay RXP start until initialization is complete. */
4313
4314         DBEXIT(BCE_VERBOSE_RESET);
4315 }
4316
4317
4318 /****************************************************************************/
4319 /* Initialize the TX CPU.                                                   */
4320 /*                                                                          */
4321 /* Returns:                                                                 */
4322 /*   Nothing.                                                               */
4323 /****************************************************************************/
4324 static void
4325 bce_init_txp_cpu(struct bce_softc *sc)
4326 {
4327         struct cpu_reg cpu_reg;
4328         struct fw_info fw;
4329
4330         DBENTER(BCE_VERBOSE_RESET);
4331
4332         cpu_reg.mode = BCE_TXP_CPU_MODE;
4333         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
4334         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
4335         cpu_reg.state = BCE_TXP_CPU_STATE;
4336         cpu_reg.state_value_clear = 0xffffff;
4337         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
4338         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
4339         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
4340         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
4341         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
4342         cpu_reg.spad_base = BCE_TXP_SCRATCH;
4343         cpu_reg.mips_view_base = 0x8000000;
4344
4345         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4346                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
4347                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
4348                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
4349                 fw.start_addr = bce_TXP_b09FwStartAddr;
4350
4351                 fw.text_addr = bce_TXP_b09FwTextAddr;
4352                 fw.text_len = bce_TXP_b09FwTextLen;
4353                 fw.text_index = 0;
4354                 fw.text = bce_TXP_b09FwText;
4355
4356                 fw.data_addr = bce_TXP_b09FwDataAddr;
4357                 fw.data_len = bce_TXP_b09FwDataLen;
4358                 fw.data_index = 0;
4359                 fw.data = bce_TXP_b09FwData;
4360
4361                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
4362                 fw.sbss_len = bce_TXP_b09FwSbssLen;
4363                 fw.sbss_index = 0;
4364                 fw.sbss = bce_TXP_b09FwSbss;
4365
4366                 fw.bss_addr = bce_TXP_b09FwBssAddr;
4367                 fw.bss_len = bce_TXP_b09FwBssLen;
4368                 fw.bss_index = 0;
4369                 fw.bss = bce_TXP_b09FwBss;
4370
4371                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
4372                 fw.rodata_len = bce_TXP_b09FwRodataLen;
4373                 fw.rodata_index = 0;
4374                 fw.rodata = bce_TXP_b09FwRodata;
4375         } else {
4376                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
4377                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
4378                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
4379                 fw.start_addr = bce_TXP_b06FwStartAddr;
4380
4381                 fw.text_addr = bce_TXP_b06FwTextAddr;
4382                 fw.text_len = bce_TXP_b06FwTextLen;
4383                 fw.text_index = 0;
4384                 fw.text = bce_TXP_b06FwText;
4385
4386                 fw.data_addr = bce_TXP_b06FwDataAddr;
4387                 fw.data_len = bce_TXP_b06FwDataLen;
4388                 fw.data_index = 0;
4389                 fw.data = bce_TXP_b06FwData;
4390
4391                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
4392                 fw.sbss_len = bce_TXP_b06FwSbssLen;
4393                 fw.sbss_index = 0;
4394                 fw.sbss = bce_TXP_b06FwSbss;
4395
4396                 fw.bss_addr = bce_TXP_b06FwBssAddr;
4397                 fw.bss_len = bce_TXP_b06FwBssLen;
4398                 fw.bss_index = 0;
4399                 fw.bss = bce_TXP_b06FwBss;
4400
4401                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
4402                 fw.rodata_len = bce_TXP_b06FwRodataLen;
4403                 fw.rodata_index = 0;
4404                 fw.rodata = bce_TXP_b06FwRodata;
4405         }
4406
4407         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
4408         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4409     bce_start_cpu(sc, &cpu_reg);
4410
4411         DBEXIT(BCE_VERBOSE_RESET);
4412 }
4413
4414
4415 /****************************************************************************/
4416 /* Initialize the TPAT CPU.                                                 */
4417 /*                                                                          */
4418 /* Returns:                                                                 */
4419 /*   Nothing.                                                               */
4420 /****************************************************************************/
4421 static void
4422 bce_init_tpat_cpu(struct bce_softc *sc)
4423 {
4424         struct cpu_reg cpu_reg;
4425         struct fw_info fw;
4426
4427         DBENTER(BCE_VERBOSE_RESET);
4428
4429         cpu_reg.mode = BCE_TPAT_CPU_MODE;
4430         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
4431         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
4432         cpu_reg.state = BCE_TPAT_CPU_STATE;
4433         cpu_reg.state_value_clear = 0xffffff;
4434         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
4435         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
4436         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
4437         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
4438         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
4439         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
4440         cpu_reg.mips_view_base = 0x8000000;
4441
4442         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4443                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
4444                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
4445                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
4446                 fw.start_addr = bce_TPAT_b09FwStartAddr;
4447
4448                 fw.text_addr = bce_TPAT_b09FwTextAddr;
4449                 fw.text_len = bce_TPAT_b09FwTextLen;
4450                 fw.text_index = 0;
4451                 fw.text = bce_TPAT_b09FwText;
4452
4453                 fw.data_addr = bce_TPAT_b09FwDataAddr;
4454                 fw.data_len = bce_TPAT_b09FwDataLen;
4455                 fw.data_index = 0;
4456                 fw.data = bce_TPAT_b09FwData;
4457
4458                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
4459                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
4460                 fw.sbss_index = 0;
4461                 fw.sbss = bce_TPAT_b09FwSbss;
4462
4463                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
4464                 fw.bss_len = bce_TPAT_b09FwBssLen;
4465                 fw.bss_index = 0;
4466                 fw.bss = bce_TPAT_b09FwBss;
4467
4468                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
4469                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
4470                 fw.rodata_index = 0;
4471                 fw.rodata = bce_TPAT_b09FwRodata;
4472         } else {
4473                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
4474                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
4475                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
4476                 fw.start_addr = bce_TPAT_b06FwStartAddr;
4477
4478                 fw.text_addr = bce_TPAT_b06FwTextAddr;
4479                 fw.text_len = bce_TPAT_b06FwTextLen;
4480                 fw.text_index = 0;
4481                 fw.text = bce_TPAT_b06FwText;
4482
4483                 fw.data_addr = bce_TPAT_b06FwDataAddr;
4484                 fw.data_len = bce_TPAT_b06FwDataLen;
4485                 fw.data_index = 0;
4486                 fw.data = bce_TPAT_b06FwData;
4487
4488                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
4489                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
4490                 fw.sbss_index = 0;
4491                 fw.sbss = bce_TPAT_b06FwSbss;
4492
4493                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
4494                 fw.bss_len = bce_TPAT_b06FwBssLen;
4495                 fw.bss_index = 0;
4496                 fw.bss = bce_TPAT_b06FwBss;
4497
4498                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
4499                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
4500                 fw.rodata_index = 0;
4501                 fw.rodata = bce_TPAT_b06FwRodata;
4502         }
4503
4504         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
4505         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4506         bce_start_cpu(sc, &cpu_reg);
4507
4508         DBEXIT(BCE_VERBOSE_RESET);
4509 }
4510
4511
4512 /****************************************************************************/
4513 /* Initialize the CP CPU.                                                   */
4514 /*                                                                          */
4515 /* Returns:                                                                 */
4516 /*   Nothing.                                                               */
4517 /****************************************************************************/
4518 static void
4519 bce_init_cp_cpu(struct bce_softc *sc)
4520 {
4521         struct cpu_reg cpu_reg;
4522         struct fw_info fw;
4523
4524         DBENTER(BCE_VERBOSE_RESET);
4525
4526         cpu_reg.mode = BCE_CP_CPU_MODE;
4527         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
4528         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
4529         cpu_reg.state = BCE_CP_CPU_STATE;
4530         cpu_reg.state_value_clear = 0xffffff;
4531         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
4532         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
4533         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
4534         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
4535         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
4536         cpu_reg.spad_base = BCE_CP_SCRATCH;
4537         cpu_reg.mips_view_base = 0x8000000;
4538
4539         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4540                 fw.ver_major = bce_CP_b09FwReleaseMajor;
4541                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
4542                 fw.ver_fix = bce_CP_b09FwReleaseFix;
4543                 fw.start_addr = bce_CP_b09FwStartAddr;
4544
4545                 fw.text_addr = bce_CP_b09FwTextAddr;
4546                 fw.text_len = bce_CP_b09FwTextLen;
4547                 fw.text_index = 0;
4548                 fw.text = bce_CP_b09FwText;
4549
4550                 fw.data_addr = bce_CP_b09FwDataAddr;
4551                 fw.data_len = bce_CP_b09FwDataLen;
4552                 fw.data_index = 0;
4553                 fw.data = bce_CP_b09FwData;
4554
4555                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
4556                 fw.sbss_len = bce_CP_b09FwSbssLen;
4557                 fw.sbss_index = 0;
4558                 fw.sbss = bce_CP_b09FwSbss;
4559
4560                 fw.bss_addr = bce_CP_b09FwBssAddr;
4561                 fw.bss_len = bce_CP_b09FwBssLen;
4562                 fw.bss_index = 0;
4563                 fw.bss = bce_CP_b09FwBss;
4564
4565                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
4566                 fw.rodata_len = bce_CP_b09FwRodataLen;
4567                 fw.rodata_index = 0;
4568                 fw.rodata = bce_CP_b09FwRodata;
4569         } else {
4570                 fw.ver_major = bce_CP_b06FwReleaseMajor;
4571                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
4572                 fw.ver_fix = bce_CP_b06FwReleaseFix;
4573                 fw.start_addr = bce_CP_b06FwStartAddr;
4574
4575                 fw.text_addr = bce_CP_b06FwTextAddr;
4576                 fw.text_len = bce_CP_b06FwTextLen;
4577                 fw.text_index = 0;
4578                 fw.text = bce_CP_b06FwText;
4579
4580                 fw.data_addr = bce_CP_b06FwDataAddr;
4581                 fw.data_len = bce_CP_b06FwDataLen;
4582                 fw.data_index = 0;
4583                 fw.data = bce_CP_b06FwData;
4584
4585                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
4586                 fw.sbss_len = bce_CP_b06FwSbssLen;
4587                 fw.sbss_index = 0;
4588                 fw.sbss = bce_CP_b06FwSbss;
4589
4590                 fw.bss_addr = bce_CP_b06FwBssAddr;
4591                 fw.bss_len = bce_CP_b06FwBssLen;
4592                 fw.bss_index = 0;
4593                 fw.bss = bce_CP_b06FwBss;
4594
4595                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
4596                 fw.rodata_len = bce_CP_b06FwRodataLen;
4597                 fw.rodata_index = 0;
4598                 fw.rodata = bce_CP_b06FwRodata;
4599         }
4600
4601         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
4602         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4603         bce_start_cpu(sc, &cpu_reg);
4604
4605         DBEXIT(BCE_VERBOSE_RESET);
4606 }
4607
4608
4609 /****************************************************************************/
4610 /* Initialize the COM CPU.                                                 */
4611 /*                                                                          */
4612 /* Returns:                                                                 */
4613 /*   Nothing.                                                               */
4614 /****************************************************************************/
4615 static void
4616 bce_init_com_cpu(struct bce_softc *sc)
4617 {
4618         struct cpu_reg cpu_reg;
4619         struct fw_info fw;
4620
4621         DBENTER(BCE_VERBOSE_RESET);
4622
4623         cpu_reg.mode = BCE_COM_CPU_MODE;
4624         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
4625         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
4626         cpu_reg.state = BCE_COM_CPU_STATE;
4627         cpu_reg.state_value_clear = 0xffffff;
4628         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
4629         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
4630         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
4631         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
4632         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
4633         cpu_reg.spad_base = BCE_COM_SCRATCH;
4634         cpu_reg.mips_view_base = 0x8000000;
4635
4636         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4637                 fw.ver_major = bce_COM_b09FwReleaseMajor;
4638                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
4639                 fw.ver_fix = bce_COM_b09FwReleaseFix;
4640                 fw.start_addr = bce_COM_b09FwStartAddr;
4641
4642                 fw.text_addr = bce_COM_b09FwTextAddr;
4643                 fw.text_len = bce_COM_b09FwTextLen;
4644                 fw.text_index = 0;
4645                 fw.text = bce_COM_b09FwText;
4646
4647                 fw.data_addr = bce_COM_b09FwDataAddr;
4648                 fw.data_len = bce_COM_b09FwDataLen;
4649                 fw.data_index = 0;
4650                 fw.data = bce_COM_b09FwData;
4651
4652                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
4653                 fw.sbss_len = bce_COM_b09FwSbssLen;
4654                 fw.sbss_index = 0;
4655                 fw.sbss = bce_COM_b09FwSbss;
4656
4657                 fw.bss_addr = bce_COM_b09FwBssAddr;
4658                 fw.bss_len = bce_COM_b09FwBssLen;
4659                 fw.bss_index = 0;
4660                 fw.bss = bce_COM_b09FwBss;
4661
4662                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
4663                 fw.rodata_len = bce_COM_b09FwRodataLen;
4664                 fw.rodata_index = 0;
4665                 fw.rodata = bce_COM_b09FwRodata;
4666         } else {
4667                 fw.ver_major = bce_COM_b06FwReleaseMajor;
4668                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
4669                 fw.ver_fix = bce_COM_b06FwReleaseFix;
4670                 fw.start_addr = bce_COM_b06FwStartAddr;
4671
4672                 fw.text_addr = bce_COM_b06FwTextAddr;
4673                 fw.text_len = bce_COM_b06FwTextLen;
4674                 fw.text_index = 0;
4675                 fw.text = bce_COM_b06FwText;
4676
4677                 fw.data_addr = bce_COM_b06FwDataAddr;
4678                 fw.data_len = bce_COM_b06FwDataLen;
4679                 fw.data_index = 0;
4680                 fw.data = bce_COM_b06FwData;
4681
4682                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
4683                 fw.sbss_len = bce_COM_b06FwSbssLen;
4684                 fw.sbss_index = 0;
4685                 fw.sbss = bce_COM_b06FwSbss;
4686
4687                 fw.bss_addr = bce_COM_b06FwBssAddr;
4688                 fw.bss_len = bce_COM_b06FwBssLen;
4689                 fw.bss_index = 0;
4690                 fw.bss = bce_COM_b06FwBss;
4691
4692                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
4693                 fw.rodata_len = bce_COM_b06FwRodataLen;
4694                 fw.rodata_index = 0;
4695                 fw.rodata = bce_COM_b06FwRodata;
4696         }
4697
4698         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
4699         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4700         bce_start_cpu(sc, &cpu_reg);
4701
4702         DBEXIT(BCE_VERBOSE_RESET);
4703 }
4704
4705
4706 /****************************************************************************/
4707 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
4708 /*                                                                          */
4709 /* Loads the firmware for each CPU and starts the CPU.                      */
4710 /*                                                                          */
4711 /* Returns:                                                                 */
4712 /*   Nothing.                                                               */
4713 /****************************************************************************/
4714 static void
4715 bce_init_cpus(struct bce_softc *sc)
4716 {
4717         DBENTER(BCE_VERBOSE_RESET);
4718
4719         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4720
4721                 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) {
4722                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
4723                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
4724                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
4725                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
4726                 } else {
4727                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
4728                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
4729                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
4730                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
4731                 }
4732
4733         } else {
4734                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
4735                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
4736                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
4737                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
4738         }
4739
4740         bce_init_rxp_cpu(sc);
4741         bce_init_txp_cpu(sc);
4742         bce_init_tpat_cpu(sc);
4743         bce_init_com_cpu(sc);
4744         bce_init_cp_cpu(sc);
4745
4746         DBEXIT(BCE_VERBOSE_RESET);
4747 }
4748
4749
4750 /****************************************************************************/
4751 /* Initialize context memory.                                               */
4752 /*                                                                          */
4753 /* Clears the memory associated with each Context ID (CID).                 */
4754 /*                                                                          */
4755 /* Returns:                                                                 */
4756 /*   Nothing.                                                               */
4757 /****************************************************************************/
4758 static int
4759 bce_init_ctx(struct bce_softc *sc)
4760 {
4761         u32 offset, val, vcid_addr;
4762         int i, j, rc, retry_cnt;
4763
4764         rc = 0;
4765         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4766
4767         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4768                 retry_cnt = CTX_INIT_RETRY_COUNT;
4769
4770                 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n");
4771
4772                 /*
4773                  * BCM5709 context memory may be cached
4774                  * in host memory so prepare the host memory
4775                  * for access.
4776                  */
4777                 val = BCE_CTX_COMMAND_ENABLED |
4778                     BCE_CTX_COMMAND_MEM_INIT | (1 << 12);
4779                 val |= (BCM_PAGE_BITS - 8) << 16;
4780                 REG_WR(sc, BCE_CTX_COMMAND, val);
4781
4782                 /* Wait for mem init command to complete. */
4783                 for (i = 0; i < retry_cnt; i++) {
4784                         val = REG_RD(sc, BCE_CTX_COMMAND);
4785                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
4786                                 break;
4787                         DELAY(2);
4788                 }
4789                 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) {
4790                         BCE_PRINTF("%s(): Context memory initialization failed!\n",
4791                             __FUNCTION__);
4792                         rc = EBUSY;
4793                         goto init_ctx_fail;
4794                 }
4795
4796                 for (i = 0; i < sc->ctx_pages; i++) {
4797                         /* Set the physical address of the context memory. */
4798                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
4799                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
4800                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
4801                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
4802                             BCE_ADDR_HI(sc->ctx_paddr[i]));
4803                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i |
4804                             BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
4805
4806                         /* Verify the context memory write was successful. */
4807                         for (j = 0; j < retry_cnt; j++) {
4808                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
4809                                 if ((val &
4810                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
4811                                         break;
4812                                 DELAY(5);
4813                         }
4814                         if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) {
4815                                 BCE_PRINTF("%s(): Failed to initialize "
4816                                     "context page %d!\n", __FUNCTION__, i);
4817                                 rc = EBUSY;
4818                                 goto init_ctx_fail;
4819                         }
4820                 }
4821         } else {
4822
4823                 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n");
4824
4825                 /*
4826                  * For the 5706/5708, context memory is local to
4827                  * the controller, so initialize the controller
4828                  * context memory.
4829                  */
4830
4831                 vcid_addr = GET_CID_ADDR(96);
4832                 while (vcid_addr) {
4833
4834                         vcid_addr -= PHY_CTX_SIZE;
4835
4836                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
4837                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4838
4839                         for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
4840                                 CTX_WR(sc, 0x00, offset, 0);
4841                         }
4842
4843                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
4844                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4845                 }
4846
4847         }
4848 init_ctx_fail:
4849         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4850         return (rc);
4851 }
4852
4853
4854 /****************************************************************************/
4855 /* Fetch the permanent MAC address of the controller.                       */
4856 /*                                                                          */
4857 /* Returns:                                                                 */
4858 /*   Nothing.                                                               */
4859 /****************************************************************************/
4860 static void
4861 bce_get_mac_addr(struct bce_softc *sc)
4862 {
4863         u32 mac_lo = 0, mac_hi = 0;
4864
4865         DBENTER(BCE_VERBOSE_RESET);
4866
4867         /*
4868          * The NetXtreme II bootcode populates various NIC
4869          * power-on and runtime configuration items in a
4870          * shared memory area.  The factory configured MAC
4871          * address is available from both NVRAM and the
4872          * shared memory area so we'll read the value from
4873          * shared memory for speed.
4874          */
4875
4876         mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER);
4877         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
4878
4879         if ((mac_lo == 0) && (mac_hi == 0)) {
4880                 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n",
4881                     __FILE__, __LINE__);
4882         } else {
4883                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
4884                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
4885                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
4886                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
4887                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
4888                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
4889         }
4890
4891         DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet "
4892             "address = %6D\n", sc->eaddr, ":");
4893         DBEXIT(BCE_VERBOSE_RESET);
4894 }
4895
4896
4897 /****************************************************************************/
4898 /* Program the MAC address.                                                 */
4899 /*                                                                          */
4900 /* Returns:                                                                 */
4901 /*   Nothing.                                                               */
4902 /****************************************************************************/
4903 static void
4904 bce_set_mac_addr(struct bce_softc *sc)
4905 {
4906         u32 val;
4907         u8 *mac_addr = sc->eaddr;
4908
4909         /* ToDo: Add support for setting multiple MAC addresses. */
4910
4911         DBENTER(BCE_VERBOSE_RESET);
4912         DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = "
4913             "%6D\n", sc->eaddr, ":");
4914
4915         val = (mac_addr[0] << 8) | mac_addr[1];
4916
4917         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
4918
4919         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
4920             (mac_addr[4] << 8) | mac_addr[5];
4921
4922         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
4923
4924         DBEXIT(BCE_VERBOSE_RESET);
4925 }
4926
4927
4928 /****************************************************************************/
4929 /* Stop the controller.                                                     */
4930 /*                                                                          */
4931 /* Returns:                                                                 */
4932 /*   Nothing.                                                               */
4933 /****************************************************************************/
4934 static void
4935 bce_stop(struct bce_softc *sc)
4936 {
4937         struct ifnet *ifp;
4938
4939         DBENTER(BCE_VERBOSE_RESET);
4940
4941         BCE_LOCK_ASSERT(sc);
4942
4943         ifp = sc->bce_ifp;
4944
4945         callout_stop(&sc->bce_tick_callout);
4946
4947         /* Disable the transmit/receive blocks. */
4948         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
4949         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
4950         DELAY(20);
4951
4952         bce_disable_intr(sc);
4953
4954         /* Free RX buffers. */
4955         if (bce_hdr_split == TRUE) {
4956                 bce_free_pg_chain(sc);
4957         }
4958         bce_free_rx_chain(sc);
4959
4960         /* Free TX buffers. */
4961         bce_free_tx_chain(sc);
4962
4963         sc->watchdog_timer = 0;
4964
4965         sc->bce_link_up = FALSE;
4966
4967         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4968
4969         DBEXIT(BCE_VERBOSE_RESET);
4970 }
4971
4972
4973 static int
4974 bce_reset(struct bce_softc *sc, u32 reset_code)
4975 {
4976         u32 emac_mode_save, val;
4977         int i, rc = 0;
4978         static const u32 emac_mode_mask = BCE_EMAC_MODE_PORT |
4979             BCE_EMAC_MODE_HALF_DUPLEX | BCE_EMAC_MODE_25G;
4980
4981         DBENTER(BCE_VERBOSE_RESET);
4982
4983         DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n",
4984             __FUNCTION__, reset_code);
4985
4986         /*
4987          * If ASF/IPMI is operational, then the EMAC Mode register already
4988          * contains appropriate values for the link settings that have
4989          * been auto-negotiated.  Resetting the chip will clobber those
4990          * values.  Save the important bits so we can restore them after
4991          * the reset.
4992          */
4993         emac_mode_save = REG_RD(sc, BCE_EMAC_MODE) & emac_mode_mask;
4994
4995         /* Wait for pending PCI transactions to complete. */
4996         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
4997             BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4998             BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4999             BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
5000             BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
5001         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
5002         DELAY(5);
5003
5004         /* Disable DMA */
5005         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5006                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
5007                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
5008                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
5009         }
5010
5011         /* Assume bootcode is running. */
5012         sc->bce_fw_timed_out = FALSE;
5013         sc->bce_drv_cardiac_arrest = FALSE;
5014
5015         /* Give the firmware a chance to prepare for the reset. */
5016         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
5017         if (rc)
5018                 goto bce_reset_exit;
5019
5020         /* Set a firmware reminder that this is a soft reset. */
5021         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC);
5022
5023         /* Dummy read to force the chip to complete all current transactions. */
5024         val = REG_RD(sc, BCE_MISC_ID);
5025
5026         /* Chip reset. */
5027         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5028                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
5029                 REG_RD(sc, BCE_MISC_COMMAND);
5030                 DELAY(5);
5031
5032                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5033                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
5034
5035                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
5036         } else {
5037                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5038                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5039                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
5040                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
5041
5042                 /* Allow up to 30us for reset to complete. */
5043                 for (i = 0; i < 10; i++) {
5044                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
5045                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5046                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
5047                                 break;
5048                         }
5049                         DELAY(10);
5050                 }
5051
5052                 /* Check that reset completed successfully. */
5053                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5054                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
5055                         BCE_PRINTF("%s(%d): Reset failed!\n",
5056                             __FILE__, __LINE__);
5057                         rc = EBUSY;
5058                         goto bce_reset_exit;
5059                 }
5060         }
5061
5062         /* Make sure byte swapping is properly configured. */
5063         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
5064         if (val != 0x01020304) {
5065                 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n",
5066                     __FILE__, __LINE__);
5067                 rc = ENODEV;
5068                 goto bce_reset_exit;
5069         }
5070
5071         /* Just completed a reset, assume that firmware is running again. */
5072         sc->bce_fw_timed_out = FALSE;
5073         sc->bce_drv_cardiac_arrest = FALSE;
5074
5075         /* Wait for the firmware to finish its initialization. */
5076         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
5077         if (rc)
5078                 BCE_PRINTF("%s(%d): Firmware did not complete "
5079                     "initialization!\n", __FILE__, __LINE__);
5080         /* Get firmware capabilities. */
5081         bce_fw_cap_init(sc);
5082
5083 bce_reset_exit:
5084         /* Restore EMAC Mode bits needed to keep ASF/IPMI running. */
5085         if (reset_code == BCE_DRV_MSG_CODE_RESET) {
5086                 val = REG_RD(sc, BCE_EMAC_MODE);
5087                 val = (val & ~emac_mode_mask) | emac_mode_save;
5088                 REG_WR(sc, BCE_EMAC_MODE, val);
5089         }
5090
5091         DBEXIT(BCE_VERBOSE_RESET);
5092         return (rc);
5093 }
5094
5095
5096 static int
5097 bce_chipinit(struct bce_softc *sc)
5098 {
5099         u32 val;
5100         int rc = 0;
5101
5102         DBENTER(BCE_VERBOSE_RESET);
5103
5104         bce_disable_intr(sc);
5105
5106         /*
5107          * Initialize DMA byte/word swapping, configure the number of DMA
5108          * channels and PCI clock compensation delay.
5109          */
5110         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
5111             BCE_DMA_CONFIG_DATA_WORD_SWAP |
5112 #if BYTE_ORDER == BIG_ENDIAN
5113             BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
5114 #endif
5115             BCE_DMA_CONFIG_CNTL_WORD_SWAP |
5116             DMA_READ_CHANS << 12 |
5117             DMA_WRITE_CHANS << 16;
5118
5119         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
5120
5121         if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133))
5122                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
5123
5124         /*
5125          * This setting resolves a problem observed on certain Intel PCI
5126          * chipsets that cannot handle multiple outstanding DMA operations.
5127          * See errata E9_5706A1_65.
5128          */
5129         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5130             (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) &&
5131             !(sc->bce_flags & BCE_PCIX_FLAG))
5132                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
5133
5134         REG_WR(sc, BCE_DMA_CONFIG, val);
5135
5136         /* Enable the RX_V2P and Context state machines before access. */
5137         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5138             BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
5139             BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
5140             BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
5141
5142         /* Initialize context mapping and zero out the quick contexts. */
5143         if ((rc = bce_init_ctx(sc)) != 0)
5144                 goto bce_chipinit_exit;
5145
5146         /* Initialize the on-boards CPUs */
5147         bce_init_cpus(sc);
5148
5149         /* Enable management frames (NC-SI) to flow to the MCP. */
5150         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5151                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
5152                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5153         }
5154
5155         /* Prepare NVRAM for access. */
5156         if ((rc = bce_init_nvram(sc)) != 0)
5157                 goto bce_chipinit_exit;
5158
5159         /* Set the kernel bypass block size */
5160         val = REG_RD(sc, BCE_MQ_CONFIG);
5161         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
5162         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
5163
5164         /* Enable bins used on the 5709. */
5165         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5166                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
5167                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
5168                         val |= BCE_MQ_CONFIG_HALT_DIS;
5169         }
5170
5171         REG_WR(sc, BCE_MQ_CONFIG, val);
5172
5173         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
5174         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
5175         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
5176
5177         /* Set the page size and clear the RV2P processor stall bits. */
5178         val = (BCM_PAGE_BITS - 8) << 24;
5179         REG_WR(sc, BCE_RV2P_CONFIG, val);
5180
5181         /* Configure page size. */
5182         val = REG_RD(sc, BCE_TBDR_CONFIG);
5183         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
5184         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
5185         REG_WR(sc, BCE_TBDR_CONFIG, val);
5186
5187         /* Set the perfect match control register to default. */
5188         REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
5189
5190 bce_chipinit_exit:
5191         DBEXIT(BCE_VERBOSE_RESET);
5192
5193         return(rc);
5194 }
5195
5196
5197 /****************************************************************************/
5198 /* Initialize the controller in preparation to send/receive traffic.        */
5199 /*                                                                          */
5200 /* Returns:                                                                 */
5201 /*   0 for success, positive value for failure.                             */
5202 /****************************************************************************/
5203 static int
5204 bce_blockinit(struct bce_softc *sc)
5205 {
5206         u32 reg, val;
5207         int rc = 0;
5208
5209         DBENTER(BCE_VERBOSE_RESET);
5210
5211         /* Load the hardware default MAC address. */
5212         bce_set_mac_addr(sc);
5213
5214         /* Set the Ethernet backoff seed value */
5215         val = sc->eaddr[0]         + (sc->eaddr[1] << 8) +
5216               (sc->eaddr[2] << 16) + (sc->eaddr[3]     ) +
5217               (sc->eaddr[4] << 8)  + (sc->eaddr[5] << 16);
5218         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
5219
5220         sc->last_status_idx = 0;
5221         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
5222
5223         /* Set up link change interrupt generation. */
5224         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
5225
5226         /* Program the physical address of the status block. */
5227         REG_WR(sc, BCE_HC_STATUS_ADDR_L,
5228             BCE_ADDR_LO(sc->status_block_paddr));
5229         REG_WR(sc, BCE_HC_STATUS_ADDR_H,
5230             BCE_ADDR_HI(sc->status_block_paddr));
5231
5232         /* Program the physical address of the statistics block. */
5233         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
5234             BCE_ADDR_LO(sc->stats_block_paddr));
5235         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
5236             BCE_ADDR_HI(sc->stats_block_paddr));
5237
5238         /*
5239          * Program various host coalescing parameters.
5240          * Trip points control how many BDs should be ready before generating
5241          * an interrupt while ticks control how long a BD can sit in the chain
5242          * before generating an interrupt.
5243          */
5244         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5245             (sc->bce_tx_quick_cons_trip_int << 16) |
5246             sc->bce_tx_quick_cons_trip);
5247         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5248             (sc->bce_rx_quick_cons_trip_int << 16) |
5249             sc->bce_rx_quick_cons_trip);
5250         REG_WR(sc, BCE_HC_TX_TICKS,
5251             (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
5252         REG_WR(sc, BCE_HC_RX_TICKS,
5253             (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
5254         REG_WR(sc, BCE_HC_STATS_TICKS, sc->bce_stats_ticks & 0xffff00);
5255         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
5256         /* Not used for L2. */
5257         REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 0);
5258         REG_WR(sc, BCE_HC_COM_TICKS, 0);
5259         REG_WR(sc, BCE_HC_CMD_TICKS, 0);
5260
5261         /* Configure the Host Coalescing block. */
5262         val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE |
5263             BCE_HC_CONFIG_COLLECT_STATS;
5264
5265 #if 0
5266         /* ToDo: Add MSI-X support. */
5267         if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
5268                 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) +
5269                     BCE_HC_SB_CONFIG_1;
5270
5271                 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL);
5272
5273                 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE |
5274                     BCE_HC_SB_CONFIG_1_ONE_SHOT);
5275
5276                 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF,
5277                     (sc->tx_quick_cons_trip_int << 16) |
5278                      sc->tx_quick_cons_trip);
5279
5280                 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF,
5281                     (sc->tx_ticks_int << 16) | sc->tx_ticks);
5282
5283                 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
5284         }
5285
5286         /*
5287          * Tell the HC block to automatically set the
5288          * INT_MASK bit after an MSI/MSI-X interrupt
5289          * is generated so the driver doesn't have to.
5290          */
5291         if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG)
5292                 val |= BCE_HC_CONFIG_ONE_SHOT;
5293
5294         /* Set the MSI-X status blocks to 128 byte boundaries. */
5295         if (sc->bce_flags & BCE_USING_MSIX_FLAG)
5296                 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
5297 #endif
5298
5299         REG_WR(sc, BCE_HC_CONFIG, val);
5300
5301         /* Clear the internal statistics counters. */
5302         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
5303
5304         /* Verify that bootcode is running. */
5305         reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
5306
5307         DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control),
5308             BCE_PRINTF("%s(%d): Simulating bootcode failure.\n",
5309             __FILE__, __LINE__);
5310             reg = 0);
5311
5312         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5313             BCE_DEV_INFO_SIGNATURE_MAGIC) {
5314                 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, "
5315                     "Expected: 08%08X\n", __FILE__, __LINE__,
5316                     (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK),
5317                     BCE_DEV_INFO_SIGNATURE_MAGIC);
5318                 rc = ENODEV;
5319                 goto bce_blockinit_exit;
5320         }
5321
5322         /* Enable DMA */
5323         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5324                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
5325                 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
5326                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
5327         }
5328
5329         /* Allow bootcode to apply additional fixes before enabling MAC. */
5330         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 |
5331             BCE_DRV_MSG_CODE_RESET);
5332
5333         /* Enable link state change interrupt generation. */
5334         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
5335
5336         /* Enable the RXP. */
5337         bce_start_rxp_cpu(sc);
5338
5339         /* Disable management frames (NC-SI) from flowing to the MCP. */
5340         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5341                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
5342                     ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
5343                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5344         }
5345
5346         /* Enable all remaining blocks in the MAC. */
5347         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
5348                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5349                     BCE_MISC_ENABLE_DEFAULT_XI);
5350         else
5351                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5352                     BCE_MISC_ENABLE_DEFAULT);
5353
5354         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
5355         DELAY(20);
5356
5357         /* Save the current host coalescing block settings. */
5358         sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
5359
5360 bce_blockinit_exit:
5361         DBEXIT(BCE_VERBOSE_RESET);
5362
5363         return (rc);
5364 }
5365
5366
5367 /****************************************************************************/
5368 /* Encapsulate an mbuf into the rx_bd chain.                                */
5369 /*                                                                          */
5370 /* Returns:                                                                 */
5371 /*   0 for success, positive value for failure.                             */
5372 /****************************************************************************/
5373 static int
5374 bce_get_rx_buf(struct bce_softc *sc, u16 prod, u16 chain_prod, u32 *prod_bseq)
5375 {
5376         bus_dma_segment_t segs[1];
5377         struct mbuf *m_new = NULL;
5378         struct rx_bd *rxbd;
5379         int nsegs, error, rc = 0;
5380 #ifdef BCE_DEBUG
5381         u16 debug_chain_prod = chain_prod;
5382 #endif
5383
5384         DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5385
5386         /* Make sure the inputs are valid. */
5387         DBRUNIF((chain_prod > MAX_RX_BD_ALLOC),
5388             BCE_PRINTF("%s(%d): RX producer out of range: "
5389             "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5390             chain_prod, (u16)MAX_RX_BD_ALLOC));
5391
5392         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5393             "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__,
5394             prod, chain_prod, *prod_bseq);
5395
5396         /* Update some debug statistic counters */
5397         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
5398             sc->rx_low_watermark = sc->free_rx_bd);
5399         DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
5400             sc->rx_empty_count++);
5401
5402         /* Simulate an mbuf allocation failure. */
5403         DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5404             sc->mbuf_alloc_failed_count++;
5405             sc->mbuf_alloc_failed_sim_count++;
5406             rc = ENOBUFS;
5407             goto bce_get_rx_buf_exit);
5408
5409         /* This is a new mbuf allocation. */
5410         if (bce_hdr_split == TRUE)
5411                 MGETHDR(m_new, M_NOWAIT, MT_DATA);
5412         else
5413                 m_new = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
5414                     sc->rx_bd_mbuf_alloc_size);
5415
5416         if (m_new == NULL) {
5417                 sc->mbuf_alloc_failed_count++;
5418                 rc = ENOBUFS;
5419                 goto bce_get_rx_buf_exit;
5420         }
5421
5422         DBRUN(sc->debug_rx_mbuf_alloc++);
5423
5424         /* Make sure we have a valid packet header. */
5425         M_ASSERTPKTHDR(m_new);
5426
5427         /* Initialize the mbuf size and pad if necessary for alignment. */
5428         m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size;
5429         m_adj(m_new, sc->rx_bd_mbuf_align_pad);
5430
5431         /* ToDo: Consider calling m_fragment() to test error handling. */
5432
5433         /* Map the mbuf cluster into device memory. */
5434         error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag,
5435             sc->rx_mbuf_map[chain_prod], m_new, segs, &nsegs, BUS_DMA_NOWAIT);
5436
5437         /* Handle any mapping errors. */
5438         if (error) {
5439                 BCE_PRINTF("%s(%d): Error mapping mbuf into RX "
5440                     "chain (%d)!\n", __FILE__, __LINE__, error);
5441
5442                 sc->dma_map_addr_rx_failed_count++;
5443                 m_freem(m_new);
5444
5445                 DBRUN(sc->debug_rx_mbuf_alloc--);
5446
5447                 rc = ENOBUFS;
5448                 goto bce_get_rx_buf_exit;
5449         }
5450
5451         /* All mbufs must map to a single segment. */
5452         KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",
5453             __FUNCTION__, nsegs));
5454
5455         /* Setup the rx_bd for the segment. */
5456         rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
5457
5458         rxbd->rx_bd_haddr_lo  = htole32(BCE_ADDR_LO(segs[0].ds_addr));
5459         rxbd->rx_bd_haddr_hi  = htole32(BCE_ADDR_HI(segs[0].ds_addr));
5460         rxbd->rx_bd_len       = htole32(segs[0].ds_len);
5461         rxbd->rx_bd_flags     = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5462         *prod_bseq += segs[0].ds_len;
5463
5464         /* Save the mbuf and update our counter. */
5465         sc->rx_mbuf_ptr[chain_prod] = m_new;
5466         sc->free_rx_bd -= nsegs;
5467
5468         DBRUNMSG(BCE_INSANE_RECV,
5469             bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs));
5470
5471         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5472             "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, prod,
5473             chain_prod, *prod_bseq);
5474
5475 bce_get_rx_buf_exit:
5476         DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5477
5478         return(rc);
5479 }
5480
5481
5482 /****************************************************************************/
5483 /* Encapsulate an mbuf cluster into the page chain.                         */
5484 /*                                                                          */
5485 /* Returns:                                                                 */
5486 /*   0 for success, positive value for failure.                             */
5487 /****************************************************************************/
5488 static int
5489 bce_get_pg_buf(struct bce_softc *sc, u16 prod, u16 prod_idx)
5490 {
5491         bus_dma_segment_t segs[1];
5492         struct mbuf *m_new = NULL;
5493         struct rx_bd *pgbd;
5494         int error, nsegs, rc = 0;
5495 #ifdef BCE_DEBUG
5496         u16 debug_prod_idx = prod_idx;
5497 #endif
5498
5499         DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5500
5501         /* Make sure the inputs are valid. */
5502         DBRUNIF((prod_idx > MAX_PG_BD_ALLOC),
5503             BCE_PRINTF("%s(%d): page producer out of range: "
5504             "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5505             prod_idx, (u16)MAX_PG_BD_ALLOC));
5506
5507         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5508             "chain_prod = 0x%04X\n", __FUNCTION__, prod, prod_idx);
5509
5510         /* Update counters if we've hit a new low or run out of pages. */
5511         DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark),
5512             sc->pg_low_watermark = sc->free_pg_bd);
5513         DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++);
5514
5515         /* Simulate an mbuf allocation failure. */
5516         DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5517             sc->mbuf_alloc_failed_count++;
5518             sc->mbuf_alloc_failed_sim_count++;
5519             rc = ENOBUFS;
5520             goto bce_get_pg_buf_exit);
5521
5522         /* This is a new mbuf allocation. */
5523         m_new = m_getcl(M_NOWAIT, MT_DATA, 0);
5524         if (m_new == NULL) {
5525                 sc->mbuf_alloc_failed_count++;
5526                 rc = ENOBUFS;
5527                 goto bce_get_pg_buf_exit;
5528         }
5529
5530         DBRUN(sc->debug_pg_mbuf_alloc++);
5531
5532         m_new->m_len = MCLBYTES;
5533
5534         /* ToDo: Consider calling m_fragment() to test error handling. */
5535
5536         /* Map the mbuf cluster into device memory. */
5537         error = bus_dmamap_load_mbuf_sg(sc->pg_mbuf_tag,
5538             sc->pg_mbuf_map[prod_idx], m_new, segs, &nsegs, BUS_DMA_NOWAIT);
5539
5540         /* Handle any mapping errors. */
5541         if (error) {
5542                 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n",
5543                     __FILE__, __LINE__);
5544
5545                 m_freem(m_new);
5546                 DBRUN(sc->debug_pg_mbuf_alloc--);
5547
5548                 rc = ENOBUFS;
5549                 goto bce_get_pg_buf_exit;
5550         }
5551
5552         /* All mbufs must map to a single segment. */
5553         KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",
5554             __FUNCTION__, nsegs));
5555
5556         /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */
5557
5558         /*
5559          * The page chain uses the same rx_bd data structure
5560          * as the receive chain but doesn't require a byte sequence (bseq).
5561          */
5562         pgbd = &sc->pg_bd_chain[PG_PAGE(prod_idx)][PG_IDX(prod_idx)];
5563
5564         pgbd->rx_bd_haddr_lo  = htole32(BCE_ADDR_LO(segs[0].ds_addr));
5565         pgbd->rx_bd_haddr_hi  = htole32(BCE_ADDR_HI(segs[0].ds_addr));
5566         pgbd->rx_bd_len       = htole32(MCLBYTES);
5567         pgbd->rx_bd_flags     = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5568
5569         /* Save the mbuf and update our counter. */
5570         sc->pg_mbuf_ptr[prod_idx] = m_new;
5571         sc->free_pg_bd--;
5572
5573         DBRUNMSG(BCE_INSANE_RECV,
5574             bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1));
5575
5576         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5577             "prod_idx = 0x%04X\n", __FUNCTION__, prod, prod_idx);
5578
5579 bce_get_pg_buf_exit:
5580         DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5581
5582         return(rc);
5583 }
5584
5585
5586 /****************************************************************************/
5587 /* Initialize the TX context memory.                                        */
5588 /*                                                                          */
5589 /* Returns:                                                                 */
5590 /*   Nothing                                                                */
5591 /****************************************************************************/
5592 static void
5593 bce_init_tx_context(struct bce_softc *sc)
5594 {
5595         u32 val;
5596
5597         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5598
5599         /* Initialize the context ID for an L2 TX chain. */
5600         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5601                 /* Set the CID type to support an L2 connection. */
5602                 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI |
5603                     BCE_L2CTX_TX_TYPE_SIZE_L2_XI;
5604                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
5605                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16);
5606                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5607                     BCE_L2CTX_TX_CMD_TYPE_XI, val);
5608
5609                 /* Point the hardware to the first page in the chain. */
5610                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5611                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5612                     BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
5613                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5614                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5615                     BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
5616         } else {
5617                 /* Set the CID type to support an L2 connection. */
5618                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
5619                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
5620                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
5621                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
5622
5623                 /* Point the hardware to the first page in the chain. */
5624                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5625                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5626                     BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
5627                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5628                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5629                     BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
5630         }
5631
5632         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5633 }
5634
5635
5636 /****************************************************************************/
5637 /* Allocate memory and initialize the TX data structures.                   */
5638 /*                                                                          */
5639 /* Returns:                                                                 */
5640 /*   0 for success, positive value for failure.                             */
5641 /****************************************************************************/
5642 static int
5643 bce_init_tx_chain(struct bce_softc *sc)
5644 {
5645         struct tx_bd *txbd;
5646         int i, rc = 0;
5647
5648         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5649
5650         /* Set the initial TX producer/consumer indices. */
5651         sc->tx_prod        = 0;
5652         sc->tx_cons        = 0;
5653         sc->tx_prod_bseq   = 0;
5654         sc->used_tx_bd     = 0;
5655         sc->max_tx_bd      = USABLE_TX_BD_ALLOC;
5656         DBRUN(sc->tx_hi_watermark = 0);
5657         DBRUN(sc->tx_full_count = 0);
5658
5659         /*
5660          * The NetXtreme II supports a linked-list structre called
5661          * a Buffer Descriptor Chain (or BD chain).  A BD chain
5662          * consists of a series of 1 or more chain pages, each of which
5663          * consists of a fixed number of BD entries.
5664          * The last BD entry on each page is a pointer to the next page
5665          * in the chain, and the last pointer in the BD chain
5666          * points back to the beginning of the chain.
5667          */
5668
5669         /* Set the TX next pointer chain entries. */
5670         for (i = 0; i < sc->tx_pages; i++) {
5671                 int j;
5672
5673                 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
5674
5675                 /* Check if we've reached the last page. */
5676                 if (i == (sc->tx_pages - 1))
5677                         j = 0;
5678                 else
5679                         j = i + 1;
5680
5681                 txbd->tx_bd_haddr_hi =
5682                     htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
5683                 txbd->tx_bd_haddr_lo =
5684                     htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
5685         }
5686
5687         bce_init_tx_context(sc);
5688
5689         DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC));
5690         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5691
5692         return(rc);
5693 }
5694
5695
5696 /****************************************************************************/
5697 /* Free memory and clear the TX data structures.                            */
5698 /*                                                                          */
5699 /* Returns:                                                                 */
5700 /*   Nothing.                                                               */
5701 /****************************************************************************/
5702 static void
5703 bce_free_tx_chain(struct bce_softc *sc)
5704 {
5705         int i;
5706
5707         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5708
5709         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
5710         for (i = 0; i < MAX_TX_BD_AVAIL; i++) {
5711                 if (sc->tx_mbuf_ptr[i] != NULL) {
5712                         if (sc->tx_mbuf_map[i] != NULL)
5713                                 bus_dmamap_sync(sc->tx_mbuf_tag,
5714                                     sc->tx_mbuf_map[i],
5715                                     BUS_DMASYNC_POSTWRITE);
5716                         m_freem(sc->tx_mbuf_ptr[i]);
5717                         sc->tx_mbuf_ptr[i] = NULL;
5718                         DBRUN(sc->debug_tx_mbuf_alloc--);
5719                 }
5720         }
5721
5722         /* Clear each TX chain page. */
5723         for (i = 0; i < sc->tx_pages; i++)
5724                 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
5725
5726         sc->used_tx_bd = 0;
5727
5728         /* Check if we lost any mbufs in the process. */
5729         DBRUNIF((sc->debug_tx_mbuf_alloc),
5730             BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs "
5731             "from tx chain!\n", __FILE__, __LINE__,
5732             sc->debug_tx_mbuf_alloc));
5733
5734         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5735 }
5736
5737
5738 /****************************************************************************/
5739 /* Initialize the RX context memory.                                        */
5740 /*                                                                          */
5741 /* Returns:                                                                 */
5742 /*   Nothing                                                                */
5743 /****************************************************************************/
5744 static void
5745 bce_init_rx_context(struct bce_softc *sc)
5746 {
5747         u32 val;
5748
5749         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5750
5751         /* Init the type, size, and BD cache levels for the RX context. */
5752         val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
5753             BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 |
5754             (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT);
5755
5756         /*
5757          * Set the level for generating pause frames
5758          * when the number of available rx_bd's gets
5759          * too low (the low watermark) and the level
5760          * when pause frames can be stopped (the high
5761          * watermark).
5762          */
5763         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5764                 u32 lo_water, hi_water;
5765
5766                 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) {
5767                         lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
5768                 } else {
5769                         lo_water = 0;
5770                 }
5771
5772                 if (lo_water >= USABLE_RX_BD_ALLOC) {
5773                         lo_water = 0;
5774                 }
5775
5776                 hi_water = USABLE_RX_BD_ALLOC / 4;
5777
5778                 if (hi_water <= lo_water) {
5779                         lo_water = 0;
5780                 }
5781
5782                 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
5783                 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
5784
5785                 if (hi_water > 0xf)
5786                         hi_water = 0xf;
5787                 else if (hi_water == 0)
5788                         lo_water = 0;
5789
5790                 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) |
5791                     (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
5792         }
5793
5794         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
5795
5796         /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
5797         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5798                 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
5799                 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
5800         }
5801
5802         /* Point the hardware to the first page in the chain. */
5803         val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
5804         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
5805         val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
5806         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
5807
5808         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5809 }
5810
5811
5812 /****************************************************************************/
5813 /* Allocate memory and initialize the RX data structures.                   */
5814 /*                                                                          */
5815 /* Returns:                                                                 */
5816 /*   0 for success, positive value for failure.                             */
5817 /****************************************************************************/
5818 static int
5819 bce_init_rx_chain(struct bce_softc *sc)
5820 {
5821         struct rx_bd *rxbd;
5822         int i, rc = 0;
5823
5824         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5825             BCE_VERBOSE_CTX);
5826
5827         /* Initialize the RX producer and consumer indices. */
5828         sc->rx_prod        = 0;
5829         sc->rx_cons        = 0;
5830         sc->rx_prod_bseq   = 0;
5831         sc->free_rx_bd     = USABLE_RX_BD_ALLOC;
5832         sc->max_rx_bd      = USABLE_RX_BD_ALLOC;
5833
5834         /* Initialize the RX next pointer chain entries. */
5835         for (i = 0; i < sc->rx_pages; i++) {
5836                 int j;
5837
5838                 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
5839
5840                 /* Check if we've reached the last page. */
5841                 if (i == (sc->rx_pages - 1))
5842                         j = 0;
5843                 else
5844                         j = i + 1;
5845
5846                 /* Setup the chain page pointers. */
5847                 rxbd->rx_bd_haddr_hi =
5848                     htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
5849                 rxbd->rx_bd_haddr_lo =
5850                     htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
5851         }
5852
5853         /* Fill up the RX chain. */
5854         bce_fill_rx_chain(sc);
5855
5856         DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC);
5857         DBRUN(sc->rx_empty_count = 0);
5858         for (i = 0; i < sc->rx_pages; i++) {
5859                 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i],
5860                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
5861         }
5862
5863         bce_init_rx_context(sc);
5864
5865         DBRUNMSG(BCE_EXTREME_RECV,
5866             bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC));
5867         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5868             BCE_VERBOSE_CTX);
5869
5870         /* ToDo: Are there possible failure modes here? */
5871
5872         return(rc);
5873 }
5874
5875
5876 /****************************************************************************/
5877 /* Add mbufs to the RX chain until its full or an mbuf allocation error     */
5878 /* occurs.                                                                  */
5879 /*                                                                          */
5880 /* Returns:                                                                 */
5881 /*   Nothing                                                                */
5882 /****************************************************************************/
5883 static void
5884 bce_fill_rx_chain(struct bce_softc *sc)
5885 {
5886         u16 prod, prod_idx;
5887         u32 prod_bseq;
5888
5889         DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5890             BCE_VERBOSE_CTX);
5891
5892         /* Get the RX chain producer indices. */
5893         prod      = sc->rx_prod;
5894         prod_bseq = sc->rx_prod_bseq;
5895
5896         /* Keep filling the RX chain until it's full. */
5897         while (sc->free_rx_bd > 0) {
5898                 prod_idx = RX_CHAIN_IDX(prod);
5899                 if (bce_get_rx_buf(sc, prod, prod_idx, &prod_bseq)) {
5900                         /* Bail out if we can't add an mbuf to the chain. */
5901                         break;
5902                 }
5903                 prod = NEXT_RX_BD(prod);
5904         }
5905
5906         /* Save the RX chain producer indices. */
5907         sc->rx_prod      = prod;
5908         sc->rx_prod_bseq = prod_bseq;
5909
5910         /* We should never end up pointing to a next page pointer. */
5911         DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
5912             BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n",
5913             __FUNCTION__, rx_prod));
5914
5915         /* Write the mailbox and tell the chip about the waiting rx_bd's. */
5916         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX, prod);
5917         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ, prod_bseq);
5918
5919         DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5920             BCE_VERBOSE_CTX);
5921 }
5922
5923
5924 /****************************************************************************/
5925 /* Free memory and clear the RX data structures.                            */
5926 /*                                                                          */
5927 /* Returns:                                                                 */
5928 /*   Nothing.                                                               */
5929 /****************************************************************************/
5930 static void
5931 bce_free_rx_chain(struct bce_softc *sc)
5932 {
5933         int i;
5934
5935         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5936
5937         /* Free any mbufs still in the RX mbuf chain. */
5938         for (i = 0; i < MAX_RX_BD_AVAIL; i++) {
5939                 if (sc->rx_mbuf_ptr[i] != NULL) {
5940                         if (sc->rx_mbuf_map[i] != NULL)
5941                                 bus_dmamap_sync(sc->rx_mbuf_tag,
5942                                     sc->rx_mbuf_map[i],
5943                                     BUS_DMASYNC_POSTREAD);
5944                         m_freem(sc->rx_mbuf_ptr[i]);
5945                         sc->rx_mbuf_ptr[i] = NULL;
5946                         DBRUN(sc->debug_rx_mbuf_alloc--);
5947                 }
5948         }
5949
5950         /* Clear each RX chain page. */
5951         for (i = 0; i < sc->rx_pages; i++)
5952                 if (sc->rx_bd_chain[i] != NULL)
5953                         bzero((char *)sc->rx_bd_chain[i],
5954                             BCE_RX_CHAIN_PAGE_SZ);
5955
5956         sc->free_rx_bd = sc->max_rx_bd;
5957
5958         /* Check if we lost any mbufs in the process. */
5959         DBRUNIF((sc->debug_rx_mbuf_alloc),
5960             BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n",
5961             __FUNCTION__, sc->debug_rx_mbuf_alloc));
5962
5963         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5964 }
5965
5966
5967 /****************************************************************************/
5968 /* Allocate memory and initialize the page data structures.                 */
5969 /* Assumes that bce_init_rx_chain() has not already been called.            */
5970 /*                                                                          */
5971 /* Returns:                                                                 */
5972 /*   0 for success, positive value for failure.                             */
5973 /****************************************************************************/
5974 static int
5975 bce_init_pg_chain(struct bce_softc *sc)
5976 {
5977         struct rx_bd *pgbd;
5978         int i, rc = 0;
5979         u32 val;
5980
5981         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5982                 BCE_VERBOSE_CTX);
5983
5984         /* Initialize the page producer and consumer indices. */
5985         sc->pg_prod        = 0;
5986         sc->pg_cons        = 0;
5987         sc->free_pg_bd     = USABLE_PG_BD_ALLOC;
5988         sc->max_pg_bd      = USABLE_PG_BD_ALLOC;
5989         DBRUN(sc->pg_low_watermark = sc->max_pg_bd);
5990         DBRUN(sc->pg_empty_count = 0);
5991
5992         /* Initialize the page next pointer chain entries. */
5993         for (i = 0; i < sc->pg_pages; i++) {
5994                 int j;
5995
5996                 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE];
5997
5998                 /* Check if we've reached the last page. */
5999                 if (i == (sc->pg_pages - 1))
6000                         j = 0;
6001                 else
6002                         j = i + 1;
6003
6004                 /* Setup the chain page pointers. */
6005                 pgbd->rx_bd_haddr_hi =
6006                     htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j]));
6007                 pgbd->rx_bd_haddr_lo =
6008                     htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j]));
6009         }
6010
6011         /* Setup the MQ BIN mapping for host_pg_bidx. */
6012         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
6013                 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT);
6014
6015         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0);
6016
6017         /* Configure the rx_bd and page chain mbuf cluster size. */
6018         val = (sc->rx_bd_mbuf_data_len << 16) | MCLBYTES;
6019         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val);
6020
6021         /* Configure the context reserved for jumbo support. */
6022         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY,
6023                 BCE_L2CTX_RX_RBDC_JUMBO_KEY);
6024
6025         /* Point the hardware to the first page in the page chain. */
6026         val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]);
6027         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val);
6028         val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]);
6029         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val);
6030
6031         /* Fill up the page chain. */
6032         bce_fill_pg_chain(sc);
6033
6034         for (i = 0; i < sc->pg_pages; i++) {
6035                 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i],
6036                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
6037         }
6038
6039         DBRUNMSG(BCE_EXTREME_RECV,
6040             bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC));
6041         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
6042                 BCE_VERBOSE_CTX);
6043         return(rc);
6044 }
6045
6046
6047 /****************************************************************************/
6048 /* Add mbufs to the page chain until its full or an mbuf allocation error   */
6049 /* occurs.                                                                  */
6050 /*                                                                          */
6051 /* Returns:                                                                 */
6052 /*   Nothing                                                                */
6053 /****************************************************************************/
6054 static void
6055 bce_fill_pg_chain(struct bce_softc *sc)
6056 {
6057         u16 prod, prod_idx;
6058
6059         DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
6060             BCE_VERBOSE_CTX);
6061
6062         /* Get the page chain prodcuer index. */
6063         prod = sc->pg_prod;
6064
6065         /* Keep filling the page chain until it's full. */
6066         while (sc->free_pg_bd > 0) {
6067                 prod_idx = PG_CHAIN_IDX(prod);
6068                 if (bce_get_pg_buf(sc, prod, prod_idx)) {
6069                         /* Bail out if we can't add an mbuf to the chain. */
6070                         break;
6071                 }
6072                 prod = NEXT_PG_BD(prod);
6073         }
6074
6075         /* Save the page chain producer index. */
6076         sc->pg_prod = prod;
6077
6078         DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
6079             BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n",
6080             __FUNCTION__, pg_prod));
6081
6082         /*
6083          * Write the mailbox and tell the chip about
6084          * the new rx_bd's in the page chain.
6085          */
6086         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_PG_BDIDX,
6087             prod);
6088
6089         DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
6090             BCE_VERBOSE_CTX);
6091 }
6092
6093
6094 /****************************************************************************/
6095 /* Free memory and clear the RX data structures.                            */
6096 /*                                                                          */
6097 /* Returns:                                                                 */
6098 /*   Nothing.                                                               */
6099 /****************************************************************************/
6100 static void
6101 bce_free_pg_chain(struct bce_softc *sc)
6102 {
6103         int i;
6104
6105         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
6106
6107         /* Free any mbufs still in the mbuf page chain. */
6108         for (i = 0; i < MAX_PG_BD_AVAIL; i++) {
6109                 if (sc->pg_mbuf_ptr[i] != NULL) {
6110                         if (sc->pg_mbuf_map[i] != NULL)
6111                                 bus_dmamap_sync(sc->pg_mbuf_tag,
6112                                     sc->pg_mbuf_map[i],
6113                                     BUS_DMASYNC_POSTREAD);
6114                         m_freem(sc->pg_mbuf_ptr[i]);
6115                         sc->pg_mbuf_ptr[i] = NULL;
6116                         DBRUN(sc->debug_pg_mbuf_alloc--);
6117                 }
6118         }
6119
6120         /* Clear each page chain pages. */
6121         for (i = 0; i < sc->pg_pages; i++)
6122                 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ);
6123
6124         sc->free_pg_bd = sc->max_pg_bd;
6125
6126         /* Check if we lost any mbufs in the process. */
6127         DBRUNIF((sc->debug_pg_mbuf_alloc),
6128             BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n",
6129             __FUNCTION__, sc->debug_pg_mbuf_alloc));
6130
6131         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
6132 }
6133
6134
6135 static u32
6136 bce_get_rphy_link(struct bce_softc *sc)
6137 {
6138         u32 advertise, link;
6139         int fdpx;
6140
6141         advertise = 0;
6142         fdpx = 0;
6143         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0)
6144                 link = bce_shmem_rd(sc, BCE_RPHY_SERDES_LINK);
6145         else
6146                 link = bce_shmem_rd(sc, BCE_RPHY_COPPER_LINK);
6147         if (link & BCE_NETLINK_ANEG_ENB)
6148                 advertise |= BCE_NETLINK_ANEG_ENB;
6149         if (link & BCE_NETLINK_SPEED_10HALF)
6150                 advertise |= BCE_NETLINK_SPEED_10HALF;
6151         if (link & BCE_NETLINK_SPEED_10FULL) {
6152                 advertise |= BCE_NETLINK_SPEED_10FULL;
6153                 fdpx++;
6154         }
6155         if (link & BCE_NETLINK_SPEED_100HALF)
6156                 advertise |= BCE_NETLINK_SPEED_100HALF;
6157         if (link & BCE_NETLINK_SPEED_100FULL) {
6158                 advertise |= BCE_NETLINK_SPEED_100FULL;
6159                 fdpx++;
6160         }
6161         if (link & BCE_NETLINK_SPEED_1000HALF)
6162                 advertise |= BCE_NETLINK_SPEED_1000HALF;
6163         if (link & BCE_NETLINK_SPEED_1000FULL) {
6164                 advertise |= BCE_NETLINK_SPEED_1000FULL;
6165                 fdpx++;
6166         }
6167         if (link & BCE_NETLINK_SPEED_2500HALF)
6168                 advertise |= BCE_NETLINK_SPEED_2500HALF;
6169         if (link & BCE_NETLINK_SPEED_2500FULL) {
6170                 advertise |= BCE_NETLINK_SPEED_2500FULL;
6171                 fdpx++;
6172         }
6173         if (fdpx)
6174                 advertise |= BCE_NETLINK_FC_PAUSE_SYM |
6175                     BCE_NETLINK_FC_PAUSE_ASYM;
6176         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6177                 advertise |= BCE_NETLINK_PHY_APP_REMOTE |
6178                     BCE_NETLINK_ETH_AT_WIRESPEED;
6179
6180         return (advertise);
6181 }
6182
6183
6184 /****************************************************************************/
6185 /* Set media options.                                                       */
6186 /*                                                                          */
6187 /* Returns:                                                                 */
6188 /*   0 for success, positive value for failure.                             */
6189 /****************************************************************************/
6190 static int
6191 bce_ifmedia_upd(struct ifnet *ifp)
6192 {
6193         struct bce_softc *sc = ifp->if_softc;
6194         int error;
6195
6196         DBENTER(BCE_VERBOSE);
6197
6198         BCE_LOCK(sc);
6199         error = bce_ifmedia_upd_locked(ifp);
6200         BCE_UNLOCK(sc);
6201
6202         DBEXIT(BCE_VERBOSE);
6203         return (error);
6204 }
6205
6206
6207 /****************************************************************************/
6208 /* Set media options.                                                       */
6209 /*                                                                          */
6210 /* Returns:                                                                 */
6211 /*   Nothing.                                                               */
6212 /****************************************************************************/
6213 static int
6214 bce_ifmedia_upd_locked(struct ifnet *ifp)
6215 {
6216         struct bce_softc *sc = ifp->if_softc;
6217         struct mii_data *mii;
6218         struct mii_softc *miisc;
6219         struct ifmedia *ifm;
6220         u32 link;
6221         int error, fdx;
6222
6223         DBENTER(BCE_VERBOSE_PHY);
6224
6225         error = 0;
6226         BCE_LOCK_ASSERT(sc);
6227
6228         sc->bce_link_up = FALSE;
6229         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6230                 ifm = &sc->bce_ifmedia;
6231                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
6232                         return (EINVAL);
6233                 link = 0;
6234                 fdx = IFM_OPTIONS(ifm->ifm_media) & IFM_FDX;
6235                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
6236                 case IFM_AUTO:
6237                         /*
6238                          * Check advertised link of remote PHY by reading
6239                          * BCE_RPHY_SERDES_LINK or BCE_RPHY_COPPER_LINK.
6240                          * Always use the same link type of remote PHY.
6241                          */
6242                         link = bce_get_rphy_link(sc);
6243                         break;
6244                 case IFM_2500_SX:
6245                         if ((sc->bce_phy_flags &
6246                             (BCE_PHY_REMOTE_PORT_FIBER_FLAG |
6247                             BCE_PHY_2_5G_CAPABLE_FLAG)) == 0)
6248                                 return (EINVAL);
6249                         /*
6250                          * XXX
6251                          * Have to enable forced 2.5Gbps configuration.
6252                          */
6253                         if (fdx != 0)
6254                                 link |= BCE_NETLINK_SPEED_2500FULL;
6255                         else
6256                                 link |= BCE_NETLINK_SPEED_2500HALF;
6257                         break;
6258                 case IFM_1000_SX:
6259                         if ((sc->bce_phy_flags &
6260                             BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6261                                 return (EINVAL);
6262                         /*
6263                          * XXX
6264                          * Have to disable 2.5Gbps configuration.
6265                          */
6266                         if (fdx != 0)
6267                                 link = BCE_NETLINK_SPEED_1000FULL;
6268                         else
6269                                 link = BCE_NETLINK_SPEED_1000HALF;
6270                         break;
6271                 case IFM_1000_T:
6272                         if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6273                                 return (EINVAL);
6274                         if (fdx != 0)
6275                                 link = BCE_NETLINK_SPEED_1000FULL;
6276                         else
6277                                 link = BCE_NETLINK_SPEED_1000HALF;
6278                         break;
6279                 case IFM_100_TX:
6280                         if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6281                                 return (EINVAL);
6282                         if (fdx != 0)
6283                                 link = BCE_NETLINK_SPEED_100FULL;
6284                         else
6285                                 link = BCE_NETLINK_SPEED_100HALF;
6286                         break;
6287                 case IFM_10_T:
6288                         if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6289                                 return (EINVAL);
6290                         if (fdx != 0)
6291                                 link = BCE_NETLINK_SPEED_10FULL;
6292                         else
6293                                 link = BCE_NETLINK_SPEED_10HALF;
6294                         break;
6295                 default:
6296                         return (EINVAL);
6297                 }
6298                 if (IFM_SUBTYPE(ifm->ifm_media) != IFM_AUTO) {
6299                         /*
6300                          * XXX
6301                          * Advertise pause capability for full-duplex media.
6302                          */
6303                         if (fdx != 0)
6304                                 link |= BCE_NETLINK_FC_PAUSE_SYM |
6305                                     BCE_NETLINK_FC_PAUSE_ASYM;
6306                         if ((sc->bce_phy_flags &
6307                             BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6308                                 link |= BCE_NETLINK_PHY_APP_REMOTE |
6309                                     BCE_NETLINK_ETH_AT_WIRESPEED;
6310                 }
6311
6312                 bce_shmem_wr(sc, BCE_MB_ARGS_0, link);
6313                 error = bce_fw_sync(sc, BCE_DRV_MSG_CODE_CMD_SET_LINK);
6314         } else {
6315                 mii = device_get_softc(sc->bce_miibus);
6316
6317                 /* Make sure the MII bus has been enumerated. */
6318                 if (mii) {
6319                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
6320                                 PHY_RESET(miisc);
6321                         error = mii_mediachg(mii);
6322                 }
6323         }
6324
6325         DBEXIT(BCE_VERBOSE_PHY);
6326         return (error);
6327 }
6328
6329
6330 static void
6331 bce_ifmedia_sts_rphy(struct bce_softc *sc, struct ifmediareq *ifmr)
6332 {
6333         struct ifnet *ifp;
6334         u32 link;
6335
6336         ifp = sc->bce_ifp;
6337         BCE_LOCK_ASSERT(sc);
6338
6339         ifmr->ifm_status = IFM_AVALID;
6340         ifmr->ifm_active = IFM_ETHER;
6341         link = bce_shmem_rd(sc, BCE_LINK_STATUS);
6342         /* XXX Handle heart beat status? */
6343         if ((link & BCE_LINK_STATUS_LINK_UP) != 0)
6344                 ifmr->ifm_status |= IFM_ACTIVE;
6345         else {
6346                 ifmr->ifm_active |= IFM_NONE;
6347                 ifp->if_baudrate = 0;
6348                 return;
6349         }
6350         switch (link & BCE_LINK_STATUS_SPEED_MASK) {
6351         case BCE_LINK_STATUS_10HALF:
6352                 ifmr->ifm_active |= IFM_10_T | IFM_HDX;
6353                 ifp->if_baudrate = IF_Mbps(10UL);
6354                 break;
6355         case BCE_LINK_STATUS_10FULL:
6356                 ifmr->ifm_active |= IFM_10_T | IFM_FDX;
6357                 ifp->if_baudrate = IF_Mbps(10UL);
6358                 break;
6359         case BCE_LINK_STATUS_100HALF:
6360                 ifmr->ifm_active |= IFM_100_TX | IFM_HDX;
6361                 ifp->if_baudrate = IF_Mbps(100UL);
6362                 break;
6363         case BCE_LINK_STATUS_100FULL:
6364                 ifmr->ifm_active |= IFM_100_TX | IFM_FDX;
6365                 ifp->if_baudrate = IF_Mbps(100UL);
6366                 break;
6367         case BCE_LINK_STATUS_1000HALF:
6368                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6369                         ifmr->ifm_active |= IFM_1000_T | IFM_HDX;
6370                 else
6371                         ifmr->ifm_active |= IFM_1000_SX | IFM_HDX;
6372                 ifp->if_baudrate = IF_Mbps(1000UL);
6373                 break;
6374         case BCE_LINK_STATUS_1000FULL:
6375                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6376                         ifmr->ifm_active |= IFM_1000_T | IFM_FDX;
6377                 else
6378                         ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
6379                 ifp->if_baudrate = IF_Mbps(1000UL);
6380                 break;
6381         case BCE_LINK_STATUS_2500HALF:
6382                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6383                         ifmr->ifm_active |= IFM_NONE;
6384                         return;
6385                 } else
6386                         ifmr->ifm_active |= IFM_2500_SX | IFM_HDX;
6387                 ifp->if_baudrate = IF_Mbps(2500UL);
6388                 break;
6389         case BCE_LINK_STATUS_2500FULL:
6390                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6391                         ifmr->ifm_active |= IFM_NONE;
6392                         return;
6393                 } else
6394                         ifmr->ifm_active |= IFM_2500_SX | IFM_FDX;
6395                 ifp->if_baudrate = IF_Mbps(2500UL);
6396                 break;
6397         default:
6398                 ifmr->ifm_active |= IFM_NONE;
6399                 return;
6400         }
6401
6402         if ((link & BCE_LINK_STATUS_RX_FC_ENABLED) != 0)
6403                 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
6404         if ((link & BCE_LINK_STATUS_TX_FC_ENABLED) != 0)
6405                 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
6406 }
6407
6408
6409 /****************************************************************************/
6410 /* Reports current media status.                                            */
6411 /*                                                                          */
6412 /* Returns:                                                                 */
6413 /*   Nothing.                                                               */
6414 /****************************************************************************/
6415 static void
6416 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
6417 {
6418         struct bce_softc *sc = ifp->if_softc;
6419         struct mii_data *mii;
6420
6421         DBENTER(BCE_VERBOSE_PHY);
6422
6423         BCE_LOCK(sc);
6424
6425         if ((ifp->if_flags & IFF_UP) == 0) {
6426                 BCE_UNLOCK(sc);
6427                 return;
6428         }
6429
6430         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
6431                 bce_ifmedia_sts_rphy(sc, ifmr);
6432         else {
6433                 mii = device_get_softc(sc->bce_miibus);
6434                 mii_pollstat(mii);
6435                 ifmr->ifm_active = mii->mii_media_active;
6436                 ifmr->ifm_status = mii->mii_media_status;
6437         }
6438
6439         BCE_UNLOCK(sc);
6440
6441         DBEXIT(BCE_VERBOSE_PHY);
6442 }
6443
6444
6445 /****************************************************************************/
6446 /* Handles PHY generated interrupt events.                                  */
6447 /*                                                                          */
6448 /* Returns:                                                                 */
6449 /*   Nothing.                                                               */
6450 /****************************************************************************/
6451 static void
6452 bce_phy_intr(struct bce_softc *sc)
6453 {
6454         u32 new_link_state, old_link_state;
6455
6456         DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
6457
6458         DBRUN(sc->phy_interrupts++);
6459
6460         new_link_state = sc->status_block->status_attn_bits &
6461             STATUS_ATTN_BITS_LINK_STATE;
6462         old_link_state = sc->status_block->status_attn_bits_ack &
6463             STATUS_ATTN_BITS_LINK_STATE;
6464
6465         /* Handle any changes if the link state has changed. */
6466         if (new_link_state != old_link_state) {
6467
6468                 /* Update the status_attn_bits_ack field. */
6469                 if (new_link_state) {
6470                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
6471                             STATUS_ATTN_BITS_LINK_STATE);
6472                         DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n",
6473                             __FUNCTION__);
6474                 } else {
6475                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
6476                             STATUS_ATTN_BITS_LINK_STATE);
6477                         DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n",
6478                             __FUNCTION__);
6479                 }
6480
6481                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6482                         if (new_link_state) {
6483                                 if (bootverbose)
6484                                         if_printf(sc->bce_ifp, "link UP\n");
6485                                 if_link_state_change(sc->bce_ifp,
6486                                     LINK_STATE_UP);
6487                         } else {
6488                                 if (bootverbose)
6489                                         if_printf(sc->bce_ifp, "link DOWN\n");
6490                                 if_link_state_change(sc->bce_ifp,
6491                                     LINK_STATE_DOWN);
6492                         }
6493                 }
6494                 /*
6495                  * Assume link is down and allow
6496                  * tick routine to update the state
6497                  * based on the actual media state.
6498                  */
6499                 sc->bce_link_up = FALSE;
6500                 callout_stop(&sc->bce_tick_callout);
6501                 bce_tick(sc);
6502         }
6503
6504         /* Acknowledge the link change interrupt. */
6505         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
6506
6507         DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
6508 }
6509
6510
6511 /****************************************************************************/
6512 /* Reads the receive consumer value from the status block (skipping over    */
6513 /* chain page pointer if necessary).                                        */
6514 /*                                                                          */
6515 /* Returns:                                                                 */
6516 /*   hw_cons                                                                */
6517 /****************************************************************************/
6518 static inline u16
6519 bce_get_hw_rx_cons(struct bce_softc *sc)
6520 {
6521         u16 hw_cons;
6522
6523         rmb();
6524         hw_cons = sc->status_block->status_rx_quick_consumer_index0;
6525         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
6526                 hw_cons++;
6527
6528         return hw_cons;
6529 }
6530
6531 /****************************************************************************/
6532 /* Handles received frame interrupt events.                                 */
6533 /*                                                                          */
6534 /* Returns:                                                                 */
6535 /*   Nothing.                                                               */
6536 /****************************************************************************/
6537 static void
6538 bce_rx_intr(struct bce_softc *sc)
6539 {
6540         struct ifnet *ifp = sc->bce_ifp;
6541         struct l2_fhdr *l2fhdr;
6542         struct ether_vlan_header *vh;
6543         unsigned int pkt_len;
6544         u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons;
6545         u32 status;
6546         unsigned int rem_len;
6547         u16 sw_pg_cons, sw_pg_cons_idx;
6548
6549         DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6550         DBRUN(sc->interrupts_rx++);
6551         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, "
6552             "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6553             __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6554
6555         /* Prepare the RX chain pages to be accessed by the host CPU. */
6556         for (int i = 0; i < sc->rx_pages; i++)
6557                 bus_dmamap_sync(sc->rx_bd_chain_tag,
6558                     sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
6559
6560         /* Prepare the page chain pages to be accessed by the host CPU. */
6561         if (bce_hdr_split == TRUE) {
6562                 for (int i = 0; i < sc->pg_pages; i++)
6563                         bus_dmamap_sync(sc->pg_bd_chain_tag,
6564                             sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
6565         }
6566
6567         /* Get the hardware's view of the RX consumer index. */
6568         hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6569
6570         /* Get working copies of the driver's view of the consumer indices. */
6571         sw_rx_cons = sc->rx_cons;
6572         sw_pg_cons = sc->pg_cons;
6573
6574         /* Update some debug statistics counters */
6575         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
6576             sc->rx_low_watermark = sc->free_rx_bd);
6577         DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
6578             sc->rx_empty_count++);
6579
6580         /* Scan through the receive chain as long as there is work to do */
6581         /* ToDo: Consider setting a limit on the number of packets processed. */
6582         rmb();
6583         while (sw_rx_cons != hw_rx_cons) {
6584                 struct mbuf *m0;
6585
6586                 /* Convert the producer/consumer indices to an actual rx_bd index. */
6587                 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons);
6588
6589                 /* Unmap the mbuf from DMA space. */
6590                 bus_dmamap_sync(sc->rx_mbuf_tag,
6591                     sc->rx_mbuf_map[sw_rx_cons_idx],
6592                     BUS_DMASYNC_POSTREAD);
6593                 bus_dmamap_unload(sc->rx_mbuf_tag,
6594                     sc->rx_mbuf_map[sw_rx_cons_idx]);
6595
6596                 /* Remove the mbuf from the RX chain. */
6597                 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx];
6598                 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL;
6599                 DBRUN(sc->debug_rx_mbuf_alloc--);
6600                 sc->free_rx_bd++;
6601
6602                 /*
6603                  * Frames received on the NetXteme II are prepended
6604                  * with an l2_fhdr structure which provides status
6605                  * information about the received frame (including
6606                  * VLAN tags and checksum info).  The frames are
6607                  * also automatically adjusted to word align the IP
6608                  * header (i.e. two null bytes are inserted before
6609                  * the Ethernet header).  As a result the data
6610                  * DMA'd by the controller into the mbuf looks
6611                  * like this:
6612                  *
6613                  * +---------+-----+---------------------+-----+
6614                  * | l2_fhdr | pad | packet data         | FCS |
6615                  * +---------+-----+---------------------+-----+
6616                  *
6617                  * The l2_fhdr needs to be checked and skipped and
6618                  * the FCS needs to be stripped before sending the
6619                  * packet up the stack.
6620                  */
6621                 l2fhdr  = mtod(m0, struct l2_fhdr *);
6622
6623                 /* Get the packet data + FCS length and the status. */
6624                 pkt_len = l2fhdr->l2_fhdr_pkt_len;
6625                 status  = l2fhdr->l2_fhdr_status;
6626
6627                 /*
6628                  * Skip over the l2_fhdr and pad, resulting in the
6629                  * following data in the mbuf:
6630                  * +---------------------+-----+
6631                  * | packet data         | FCS |
6632                  * +---------------------+-----+
6633                  */
6634                 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN);
6635
6636                 /*
6637                  * When split header mode is used, an ethernet frame
6638                  * may be split across the receive chain and the
6639                  * page chain. If that occurs an mbuf cluster must be
6640                  * reassembled from the individual mbuf pieces.
6641                  */
6642                 if (bce_hdr_split == TRUE) {
6643                         /*
6644                          * Check whether the received frame fits in a single
6645                          * mbuf or not (i.e. packet data + FCS <=
6646                          * sc->rx_bd_mbuf_data_len bytes).
6647                          */
6648                         if (pkt_len > m0->m_len) {
6649                                 /*
6650                                  * The received frame is larger than a single mbuf.
6651                                  * If the frame was a TCP frame then only the TCP
6652                                  * header is placed in the mbuf, the remaining
6653                                  * payload (including FCS) is placed in the page
6654                                  * chain, the SPLIT flag is set, and the header
6655                                  * length is placed in the IP checksum field.
6656                                  * If the frame is not a TCP frame then the mbuf
6657                                  * is filled and the remaining bytes are placed
6658                                  * in the page chain.
6659                                  */
6660
6661                                 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large "
6662                                         "packet.\n", __FUNCTION__);
6663                                 DBRUN(sc->split_header_frames_rcvd++);
6664
6665                                 /*
6666                                  * When the page chain is enabled and the TCP
6667                                  * header has been split from the TCP payload,
6668                                  * the ip_xsum structure will reflect the length
6669                                  * of the TCP header, not the IP checksum.  Set
6670                                  * the packet length of the mbuf accordingly.
6671                                  */
6672                                 if (status & L2_FHDR_STATUS_SPLIT) {
6673                                         m0->m_len = l2fhdr->l2_fhdr_ip_xsum;
6674                                         DBRUN(sc->split_header_tcp_frames_rcvd++);
6675                                 }
6676
6677                                 rem_len = pkt_len - m0->m_len;
6678
6679                                 /* Pull mbufs off the page chain for any remaining data. */
6680                                 while (rem_len > 0) {
6681                                         struct mbuf *m_pg;
6682
6683                                         sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons);
6684
6685                                         /* Remove the mbuf from the page chain. */
6686                                         m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx];
6687                                         sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL;
6688                                         DBRUN(sc->debug_pg_mbuf_alloc--);
6689                                         sc->free_pg_bd++;
6690
6691                                         /* Unmap the page chain mbuf from DMA space. */
6692                                         bus_dmamap_sync(sc->pg_mbuf_tag,
6693                                                 sc->pg_mbuf_map[sw_pg_cons_idx],
6694                                                 BUS_DMASYNC_POSTREAD);
6695                                         bus_dmamap_unload(sc->pg_mbuf_tag,
6696                                                 sc->pg_mbuf_map[sw_pg_cons_idx]);
6697
6698                                         /* Adjust the mbuf length. */
6699                                         if (rem_len < m_pg->m_len) {
6700                                                 /* The mbuf chain is complete. */
6701                                                 m_pg->m_len = rem_len;
6702                                                 rem_len = 0;
6703                                         } else {
6704                                                 /* More packet data is waiting. */
6705                                                 rem_len -= m_pg->m_len;
6706                                         }
6707
6708                                         /* Concatenate the mbuf cluster to the mbuf. */
6709                                         m_cat(m0, m_pg);
6710
6711                                         sw_pg_cons = NEXT_PG_BD(sw_pg_cons);
6712                                 }
6713
6714                                 /* Set the total packet length. */
6715                                 m0->m_pkthdr.len = pkt_len;
6716
6717                         } else {
6718                                 /*
6719                                  * The received packet is small and fits in a
6720                                  * single mbuf (i.e. the l2_fhdr + pad + packet +
6721                                  * FCS <= MHLEN).  In other words, the packet is
6722                                  * 154 bytes or less in size.
6723                                  */
6724
6725                                 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small "
6726                                         "packet.\n", __FUNCTION__);
6727
6728                                 /* Set the total packet length. */
6729                                 m0->m_pkthdr.len = m0->m_len = pkt_len;
6730                         }
6731                 } else
6732                         /* Set the total packet length. */
6733                         m0->m_pkthdr.len = m0->m_len = pkt_len;
6734
6735                 /* Remove the trailing Ethernet FCS. */
6736                 m_adj(m0, -ETHER_CRC_LEN);
6737
6738                 /* Check that the resulting mbuf chain is valid. */
6739                 DBRUN(m_sanity(m0, FALSE));
6740                 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) |
6741                     (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)),
6742                     BCE_PRINTF("Invalid Ethernet frame size!\n");
6743                     m_print(m0, 128));
6744
6745                 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control),
6746                     sc->l2fhdr_error_sim_count++;
6747                     status = status | L2_FHDR_ERRORS_PHY_DECODE);
6748
6749                 /* Check the received frame for errors. */
6750                 if (status & (L2_FHDR_ERRORS_BAD_CRC |
6751                     L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT |
6752                     L2_FHDR_ERRORS_TOO_SHORT  | L2_FHDR_ERRORS_GIANT_FRAME)) {
6753
6754                         /* Log the error and release the mbuf. */
6755                         sc->l2fhdr_error_count++;
6756                         m_freem(m0);
6757                         m0 = NULL;
6758                         goto bce_rx_intr_next_rx;
6759                 }
6760
6761                 /* Send the packet to the appropriate interface. */
6762                 m0->m_pkthdr.rcvif = ifp;
6763
6764                 /* Assume no hardware checksum. */
6765                 m0->m_pkthdr.csum_flags = 0;
6766
6767                 /* Validate the checksum if offload enabled. */
6768                 if (ifp->if_capenable & IFCAP_RXCSUM) {
6769                         /* Check for an IP datagram. */
6770                         if (!(status & L2_FHDR_STATUS_SPLIT) &&
6771                             (status & L2_FHDR_STATUS_IP_DATAGRAM)) {
6772                                 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
6773                                 DBRUN(sc->csum_offload_ip++);
6774                                 /* Check if the IP checksum is valid. */
6775                                 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0)
6776                                         m0->m_pkthdr.csum_flags |=
6777                                             CSUM_IP_VALID;
6778                         }
6779
6780                         /* Check for a valid TCP/UDP frame. */
6781                         if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
6782                             L2_FHDR_STATUS_UDP_DATAGRAM)) {
6783
6784                                 /* Check for a good TCP/UDP checksum. */
6785                                 if ((status & (L2_FHDR_ERRORS_TCP_XSUM |
6786                                     L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
6787                                         DBRUN(sc->csum_offload_tcp_udp++);
6788                                         m0->m_pkthdr.csum_data =
6789                                             l2fhdr->l2_fhdr_tcp_udp_xsum;
6790                                         m0->m_pkthdr.csum_flags |=
6791                                             (CSUM_DATA_VALID
6792                                             | CSUM_PSEUDO_HDR);
6793                                 }
6794                         }
6795                 }
6796
6797                 /* Attach the VLAN tag. */
6798                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
6799                     !(sc->rx_mode & BCE_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
6800                         DBRUN(sc->vlan_tagged_frames_rcvd++);
6801                         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
6802                                 DBRUN(sc->vlan_tagged_frames_stripped++);
6803 #if __FreeBSD_version < 700000
6804                                 VLAN_INPUT_TAG(ifp, m0,
6805                                     l2fhdr->l2_fhdr_vlan_tag, continue);
6806 #else
6807                                 m0->m_pkthdr.ether_vtag =
6808                                     l2fhdr->l2_fhdr_vlan_tag;
6809                                 m0->m_flags |= M_VLANTAG;
6810 #endif
6811                         } else {
6812                                 /*
6813                                  * bce(4) controllers can't disable VLAN
6814                                  * tag stripping if management firmware
6815                                  * (ASF/IPMI/UMP) is running. So we always
6816                                  * strip VLAN tag and manually reconstruct
6817                                  * the VLAN frame by appending stripped
6818                                  * VLAN tag in driver if VLAN tag stripping
6819                                  * was disabled.
6820                                  *
6821                                  * TODO: LLC SNAP handling.
6822                                  */
6823                                 bcopy(mtod(m0, uint8_t *),
6824                                     mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN,
6825                                     ETHER_ADDR_LEN * 2);
6826                                 m0->m_data -= ETHER_VLAN_ENCAP_LEN;
6827                                 vh = mtod(m0, struct ether_vlan_header *);
6828                                 vh->evl_encap_proto = htons(ETHERTYPE_VLAN);
6829                                 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag);
6830                                 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN;
6831                                 m0->m_len += ETHER_VLAN_ENCAP_LEN;
6832                         }
6833                 }
6834
6835                 /* Increment received packet statistics. */
6836                 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
6837
6838 bce_rx_intr_next_rx:
6839                 sw_rx_cons = NEXT_RX_BD(sw_rx_cons);
6840
6841                 /* If we have a packet, pass it up the stack */
6842                 if (m0) {
6843                         /* Make sure we don't lose our place when we release the lock. */
6844                         sc->rx_cons = sw_rx_cons;
6845                         sc->pg_cons = sw_pg_cons;
6846
6847                         BCE_UNLOCK(sc);
6848                         (*ifp->if_input)(ifp, m0);
6849                         BCE_LOCK(sc);
6850
6851                         /* Recover our place. */
6852                         sw_rx_cons = sc->rx_cons;
6853                         sw_pg_cons = sc->pg_cons;
6854                 }
6855
6856                 /* Refresh hw_cons to see if there's new work */
6857                 if (sw_rx_cons == hw_rx_cons)
6858                         hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6859         }
6860
6861         /* No new packets.  Refill the page chain. */
6862         if (bce_hdr_split == TRUE) {
6863                 sc->pg_cons = sw_pg_cons;
6864                 bce_fill_pg_chain(sc);
6865         }
6866
6867         /* No new packets.  Refill the RX chain. */
6868         sc->rx_cons = sw_rx_cons;
6869         bce_fill_rx_chain(sc);
6870
6871         /* Prepare the page chain pages to be accessed by the NIC. */
6872         for (int i = 0; i < sc->rx_pages; i++)
6873                 bus_dmamap_sync(sc->rx_bd_chain_tag,
6874                     sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6875
6876         if (bce_hdr_split == TRUE) {
6877                 for (int i = 0; i < sc->pg_pages; i++)
6878                         bus_dmamap_sync(sc->pg_bd_chain_tag,
6879                             sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6880         }
6881
6882         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, "
6883             "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6884             __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6885         DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6886 }
6887
6888
6889 /****************************************************************************/
6890 /* Reads the transmit consumer value from the status block (skipping over   */
6891 /* chain page pointer if necessary).                                        */
6892 /*                                                                          */
6893 /* Returns:                                                                 */
6894 /*   hw_cons                                                                */
6895 /****************************************************************************/
6896 static inline u16
6897 bce_get_hw_tx_cons(struct bce_softc *sc)
6898 {
6899         u16 hw_cons;
6900
6901         mb();
6902         hw_cons = sc->status_block->status_tx_quick_consumer_index0;
6903         if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
6904                 hw_cons++;
6905
6906         return hw_cons;
6907 }
6908
6909
6910 /****************************************************************************/
6911 /* Handles transmit completion interrupt events.                            */
6912 /*                                                                          */
6913 /* Returns:                                                                 */
6914 /*   Nothing.                                                               */
6915 /****************************************************************************/
6916 static void
6917 bce_tx_intr(struct bce_softc *sc)
6918 {
6919         struct ifnet *ifp = sc->bce_ifp;
6920         u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
6921
6922         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
6923         DBRUN(sc->interrupts_tx++);
6924         DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, "
6925             "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
6926             __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
6927
6928         BCE_LOCK_ASSERT(sc);
6929
6930         /* Get the hardware's view of the TX consumer index. */
6931         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6932         sw_tx_cons = sc->tx_cons;
6933
6934         /* Prevent speculative reads of the status block. */
6935         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6936             BUS_SPACE_BARRIER_READ);
6937
6938         /* Cycle through any completed TX chain page entries. */
6939         while (sw_tx_cons != hw_tx_cons) {
6940 #ifdef BCE_DEBUG
6941                 struct tx_bd *txbd = NULL;
6942 #endif
6943                 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
6944
6945                 DBPRINT(sc, BCE_INFO_SEND,
6946                     "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
6947                     "sw_tx_chain_cons = 0x%04X\n",
6948                     __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
6949
6950                 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC),
6951                     BCE_PRINTF("%s(%d): TX chain consumer out of range! "
6952                     " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons,
6953                     (int) MAX_TX_BD_ALLOC);
6954                     bce_breakpoint(sc));
6955
6956                 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
6957                     [TX_IDX(sw_tx_chain_cons)]);
6958
6959                 DBRUNIF((txbd == NULL),
6960                     BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n",
6961                     __FILE__, __LINE__, sw_tx_chain_cons);
6962                     bce_breakpoint(sc));
6963
6964                 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__);
6965                     bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
6966
6967                 /*
6968                  * Free the associated mbuf. Remember
6969                  * that only the last tx_bd of a packet
6970                  * has an mbuf pointer and DMA map.
6971                  */
6972                 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
6973
6974                         /* Validate that this is the last tx_bd. */
6975                         DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
6976                             BCE_PRINTF("%s(%d): tx_bd END flag not set but "
6977                             "txmbuf == NULL!\n", __FILE__, __LINE__);
6978                             bce_breakpoint(sc));
6979
6980                         DBRUNMSG(BCE_INFO_SEND,
6981                             BCE_PRINTF("%s(): Unloading map/freeing mbuf "
6982                             "from tx_bd[0x%04X]\n", __FUNCTION__,
6983                             sw_tx_chain_cons));
6984
6985                         /* Unmap the mbuf. */
6986                         bus_dmamap_unload(sc->tx_mbuf_tag,
6987                             sc->tx_mbuf_map[sw_tx_chain_cons]);
6988
6989                         /* Free the mbuf. */
6990                         m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
6991                         sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
6992                         DBRUN(sc->debug_tx_mbuf_alloc--);
6993
6994                         if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
6995                 }
6996
6997                 sc->used_tx_bd--;
6998                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
6999
7000                 /* Refresh hw_cons to see if there's new work. */
7001                 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
7002
7003                 /* Prevent speculative reads of the status block. */
7004                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
7005                     BUS_SPACE_BARRIER_READ);
7006         }
7007
7008         /* Clear the TX timeout timer. */
7009         sc->watchdog_timer = 0;
7010
7011         /* Clear the tx hardware queue full flag. */
7012         if (sc->used_tx_bd < sc->max_tx_bd) {
7013                 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE),
7014                     DBPRINT(sc, BCE_INFO_SEND,
7015                     "%s(): Open TX chain! %d/%d (used/total)\n",
7016                     __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd));
7017                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
7018         }
7019
7020         sc->tx_cons = sw_tx_cons;
7021
7022         DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, "
7023             "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
7024             __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
7025         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
7026 }
7027
7028
7029 /****************************************************************************/
7030 /* Disables interrupt generation.                                           */
7031 /*                                                                          */
7032 /* Returns:                                                                 */
7033 /*   Nothing.                                                               */
7034 /****************************************************************************/
7035 static void
7036 bce_disable_intr(struct bce_softc *sc)
7037 {
7038         DBENTER(BCE_VERBOSE_INTR);
7039
7040         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
7041         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
7042
7043         DBEXIT(BCE_VERBOSE_INTR);
7044 }
7045
7046
7047 /****************************************************************************/
7048 /* Enables interrupt generation.                                            */
7049 /*                                                                          */
7050 /* Returns:                                                                 */
7051 /*   Nothing.                                                               */
7052 /****************************************************************************/
7053 static void
7054 bce_enable_intr(struct bce_softc *sc, int coal_now)
7055 {
7056         DBENTER(BCE_VERBOSE_INTR);
7057
7058         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7059             BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
7060             BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
7061
7062         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7063             BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
7064
7065         /* Force an immediate interrupt (whether there is new data or not). */
7066         if (coal_now)
7067                 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
7068
7069         DBEXIT(BCE_VERBOSE_INTR);
7070 }
7071
7072
7073 /****************************************************************************/
7074 /* Handles controller initialization.                                       */
7075 /*                                                                          */
7076 /* Returns:                                                                 */
7077 /*   Nothing.                                                               */
7078 /****************************************************************************/
7079 static void
7080 bce_init_locked(struct bce_softc *sc)
7081 {
7082         struct ifnet *ifp;
7083         u32 ether_mtu = 0;
7084
7085         DBENTER(BCE_VERBOSE_RESET);
7086
7087         BCE_LOCK_ASSERT(sc);
7088
7089         ifp = sc->bce_ifp;
7090
7091         /* Check if the driver is still running and bail out if it is. */
7092         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
7093                 goto bce_init_locked_exit;
7094
7095         bce_stop(sc);
7096
7097         if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
7098                 BCE_PRINTF("%s(%d): Controller reset failed!\n",
7099                     __FILE__, __LINE__);
7100                 goto bce_init_locked_exit;
7101         }
7102
7103         if (bce_chipinit(sc)) {
7104                 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
7105                     __FILE__, __LINE__);
7106                 goto bce_init_locked_exit;
7107         }
7108
7109         if (bce_blockinit(sc)) {
7110                 BCE_PRINTF("%s(%d): Block initialization failed!\n",
7111                     __FILE__, __LINE__);
7112                 goto bce_init_locked_exit;
7113         }
7114
7115         /* Load our MAC address. */
7116         bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN);
7117         bce_set_mac_addr(sc);
7118
7119         if (bce_hdr_split == FALSE)
7120                 bce_get_rx_buffer_sizes(sc, ifp->if_mtu);
7121         /*
7122          * Calculate and program the hardware Ethernet MTU
7123          * size. Be generous on the receive if we have room
7124          * and allowed by the user.
7125          */
7126         if (bce_strict_rx_mtu == TRUE)
7127                 ether_mtu = ifp->if_mtu;
7128         else {
7129                 if (bce_hdr_split == TRUE) {
7130                         if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len + MCLBYTES)
7131                                 ether_mtu = sc->rx_bd_mbuf_data_len +
7132                                     MCLBYTES;
7133                         else
7134                                 ether_mtu = ifp->if_mtu;
7135                 } else {
7136                         if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len)
7137                                 ether_mtu = sc->rx_bd_mbuf_data_len;
7138                         else
7139                                 ether_mtu = ifp->if_mtu;
7140                 }
7141         }
7142
7143         ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
7144
7145         DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n",
7146             __FUNCTION__, ether_mtu);
7147
7148         /* Program the mtu, enabling jumbo frame support if necessary. */
7149         if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN))
7150                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
7151                     min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
7152                     BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
7153         else
7154                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
7155
7156         /* Program appropriate promiscuous/multicast filtering. */
7157         bce_set_rx_mode(sc);
7158
7159         if (bce_hdr_split == TRUE) {
7160                 /* Init page buffer descriptor chain. */
7161                 bce_init_pg_chain(sc);
7162         }
7163
7164         /* Init RX buffer descriptor chain. */
7165         bce_init_rx_chain(sc);
7166
7167         /* Init TX buffer descriptor chain. */
7168         bce_init_tx_chain(sc);
7169
7170         /* Enable host interrupts. */
7171         bce_enable_intr(sc, 1);
7172
7173         bce_ifmedia_upd_locked(ifp);
7174
7175         /* Let the OS know the driver is up and running. */
7176         ifp->if_drv_flags |= IFF_DRV_RUNNING;
7177         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
7178
7179         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
7180
7181 bce_init_locked_exit:
7182         DBEXIT(BCE_VERBOSE_RESET);
7183 }
7184
7185
7186 /****************************************************************************/
7187 /* Initialize the controller just enough so that any management firmware    */
7188 /* running on the device will continue to operate correctly.                */
7189 /*                                                                          */
7190 /* Returns:                                                                 */
7191 /*   Nothing.                                                               */
7192 /****************************************************************************/
7193 static void
7194 bce_mgmt_init_locked(struct bce_softc *sc)
7195 {
7196         struct ifnet *ifp;
7197
7198         DBENTER(BCE_VERBOSE_RESET);
7199
7200         BCE_LOCK_ASSERT(sc);
7201
7202         /* Bail out if management firmware is not running. */
7203         if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) {
7204                 DBPRINT(sc, BCE_VERBOSE_SPECIAL,
7205                     "No management firmware running...\n");
7206                 goto bce_mgmt_init_locked_exit;
7207         }
7208
7209         ifp = sc->bce_ifp;
7210
7211         /* Enable all critical blocks in the MAC. */
7212         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
7213         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
7214         DELAY(20);
7215
7216         bce_ifmedia_upd_locked(ifp);
7217
7218 bce_mgmt_init_locked_exit:
7219         DBEXIT(BCE_VERBOSE_RESET);
7220 }
7221
7222
7223 /****************************************************************************/
7224 /* Handles controller initialization when called from an unlocked routine.  */
7225 /*                                                                          */
7226 /* Returns:                                                                 */
7227 /*   Nothing.                                                               */
7228 /****************************************************************************/
7229 static void
7230 bce_init(void *xsc)
7231 {
7232         struct bce_softc *sc = xsc;
7233
7234         DBENTER(BCE_VERBOSE_RESET);
7235
7236         BCE_LOCK(sc);
7237         bce_init_locked(sc);
7238         BCE_UNLOCK(sc);
7239
7240         DBEXIT(BCE_VERBOSE_RESET);
7241 }
7242
7243
7244 /****************************************************************************/
7245 /* Modifies an mbuf for TSO on the hardware.                                */
7246 /*                                                                          */
7247 /* Returns:                                                                 */
7248 /*   Pointer to a modified mbuf.                                            */
7249 /****************************************************************************/
7250 static struct mbuf *
7251 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags)
7252 {
7253         struct mbuf *m;
7254         struct ether_header *eh;
7255         struct ip *ip;
7256         struct tcphdr *th;
7257         u16 etype;
7258         int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0;
7259
7260         DBRUN(sc->tso_frames_requested++);
7261
7262         /* Controller may modify mbuf chains. */
7263         if (M_WRITABLE(*m_head) == 0) {
7264                 m = m_dup(*m_head, M_NOWAIT);
7265                 m_freem(*m_head);
7266                 if (m == NULL) {
7267                         sc->mbuf_alloc_failed_count++;
7268                         *m_head = NULL;
7269                         return (NULL);
7270                 }
7271                 *m_head = m;
7272         }
7273
7274         /*
7275          * For TSO the controller needs two pieces of info,
7276          * the MSS and the IP+TCP options length.
7277          */
7278         m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip));
7279         if (m == NULL) {
7280                 *m_head = NULL;
7281                 return (NULL);
7282         }
7283         eh = mtod(m, struct ether_header *);
7284         etype = ntohs(eh->ether_type);
7285
7286         /* Check for supported TSO Ethernet types (only IPv4 for now) */
7287         switch (etype) {
7288         case ETHERTYPE_IP:
7289                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7290                 /* TSO only supported for TCP protocol. */
7291                 if (ip->ip_p != IPPROTO_TCP) {
7292                         BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n",
7293                             __FILE__, __LINE__);
7294                         m_freem(*m_head);
7295                         *m_head = NULL;
7296                         return (NULL);
7297                 }
7298
7299                 /* Get IP header length in bytes (min 20) */
7300                 ip_hlen = ip->ip_hl << 2;
7301                 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen +
7302                     sizeof(struct tcphdr));
7303                 if (m == NULL) {
7304                         *m_head = NULL;
7305                         return (NULL);
7306                 }
7307
7308                 /* Get the TCP header length in bytes (min 20) */
7309                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7310                 th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
7311                 tcp_hlen = (th->th_off << 2);
7312
7313                 /* Make sure all IP/TCP options live in the same buffer. */
7314                 m = m_pullup(*m_head,  sizeof(struct ether_header)+ ip_hlen +
7315                     tcp_hlen);
7316                 if (m == NULL) {
7317                         *m_head = NULL;
7318                         return (NULL);
7319                 }
7320
7321                 /* Clear IP header length and checksum, will be calc'd by h/w. */
7322                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7323                 ip_len = ip->ip_len;
7324                 ip->ip_len = 0;
7325                 ip->ip_sum = 0;
7326                 break;
7327         case ETHERTYPE_IPV6:
7328                 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n",
7329                     __FILE__, __LINE__);
7330                 m_freem(*m_head);
7331                 *m_head = NULL;
7332                 return (NULL);
7333                 /* NOT REACHED */
7334         default:
7335                 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n",
7336                     __FILE__, __LINE__);
7337                 m_freem(*m_head);
7338                 *m_head = NULL;
7339                 return (NULL);
7340         }
7341
7342         hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen;
7343
7344         DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, "
7345             "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n",
7346             __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen,
7347             tcp_hlen, ip_len);
7348
7349         /* Set the LSO flag in the TX BD */
7350         *flags |= TX_BD_FLAGS_SW_LSO;
7351
7352         /* Set the length of IP + TCP options (in 32 bit words) */
7353         *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) -
7354             sizeof(struct tcphdr)) >> 2) << 8);
7355
7356         DBRUN(sc->tso_frames_completed++);
7357         return (*m_head);
7358 }
7359
7360
7361 /****************************************************************************/
7362 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
7363 /* memory visible to the controller.                                        */
7364 /*                                                                          */
7365 /* Returns:                                                                 */
7366 /*   0 for success, positive value for failure.                             */
7367 /* Modified:                                                                */
7368 /*   m_head: May be set to NULL if MBUF is excessively fragmented.          */
7369 /****************************************************************************/
7370 static int
7371 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head)
7372 {
7373         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
7374         bus_dmamap_t map;
7375         struct tx_bd *txbd = NULL;
7376         struct mbuf *m0;
7377         u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0;
7378         u32 prod_bseq;
7379
7380 #ifdef BCE_DEBUG
7381         u16 debug_prod;
7382 #endif
7383
7384         int i, error, nsegs, rc = 0;
7385
7386         DBENTER(BCE_VERBOSE_SEND);
7387
7388         /* Make sure we have room in the TX chain. */
7389         if (sc->used_tx_bd >= sc->max_tx_bd)
7390                 goto bce_tx_encap_exit;
7391
7392         /* Transfer any checksum offload flags to the bd. */
7393         m0 = *m_head;
7394         if (m0->m_pkthdr.csum_flags) {
7395                 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
7396                         m0 = bce_tso_setup(sc, m_head, &flags);
7397                         if (m0 == NULL) {
7398                                 DBRUN(sc->tso_frames_failed++);
7399                                 goto bce_tx_encap_exit;
7400                         }
7401                         mss = htole16(m0->m_pkthdr.tso_segsz);
7402                 } else {
7403                         if (m0->m_pkthdr.csum_flags & CSUM_IP)
7404                                 flags |= TX_BD_FLAGS_IP_CKSUM;
7405                         if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
7406                                 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
7407                 }
7408         }
7409
7410         /* Transfer any VLAN tags to the bd. */
7411         if (m0->m_flags & M_VLANTAG) {
7412                 flags |= TX_BD_FLAGS_VLAN_TAG;
7413                 vlan_tag = m0->m_pkthdr.ether_vtag;
7414         }
7415
7416         /* Map the mbuf into DMAable memory. */
7417         prod = sc->tx_prod;
7418         chain_prod = TX_CHAIN_IDX(prod);
7419         map = sc->tx_mbuf_map[chain_prod];
7420
7421         /* Map the mbuf into our DMA address space. */
7422         error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
7423             segs, &nsegs, BUS_DMA_NOWAIT);
7424
7425         /* Check if the DMA mapping was successful */
7426         if (error == EFBIG) {
7427                 sc->mbuf_frag_count++;
7428
7429                 /* Try to defrag the mbuf. */
7430                 m0 = m_collapse(*m_head, M_NOWAIT, BCE_MAX_SEGMENTS);
7431                 if (m0 == NULL) {
7432                         /* Defrag was unsuccessful */
7433                         m_freem(*m_head);
7434                         *m_head = NULL;
7435                         sc->mbuf_alloc_failed_count++;
7436                         rc = ENOBUFS;
7437                         goto bce_tx_encap_exit;
7438                 }
7439
7440                 /* Defrag was successful, try mapping again */
7441                 *m_head = m0;
7442                 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag,
7443                     map, m0, segs, &nsegs, BUS_DMA_NOWAIT);
7444
7445                 /* Still getting an error after a defrag. */
7446                 if (error == ENOMEM) {
7447                         /* Insufficient DMA buffers available. */
7448                         sc->dma_map_addr_tx_failed_count++;
7449                         rc = error;
7450                         goto bce_tx_encap_exit;
7451                 } else if (error != 0) {
7452                         /* Release it and return an error. */
7453                         BCE_PRINTF("%s(%d): Unknown error mapping mbuf into "
7454                             "TX chain!\n", __FILE__, __LINE__);
7455                         m_freem(m0);
7456                         *m_head = NULL;
7457                         sc->dma_map_addr_tx_failed_count++;
7458                         rc = ENOBUFS;
7459                         goto bce_tx_encap_exit;
7460                 }
7461         } else if (error == ENOMEM) {
7462                 /* Insufficient DMA buffers available. */
7463                 sc->dma_map_addr_tx_failed_count++;
7464                 rc = error;
7465                 goto bce_tx_encap_exit;
7466         } else if (error != 0) {
7467                 m_freem(m0);
7468                 *m_head = NULL;
7469                 sc->dma_map_addr_tx_failed_count++;
7470                 rc = error;
7471                 goto bce_tx_encap_exit;
7472         }
7473
7474         /* Make sure there's room in the chain */
7475         if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) {
7476                 bus_dmamap_unload(sc->tx_mbuf_tag, map);
7477                 rc = ENOBUFS;
7478                 goto bce_tx_encap_exit;
7479         }
7480
7481         /* prod points to an empty tx_bd at this point. */
7482         prod_bseq  = sc->tx_prod_bseq;
7483
7484 #ifdef BCE_DEBUG
7485         debug_prod = chain_prod;
7486 #endif
7487
7488         DBPRINT(sc, BCE_INFO_SEND,
7489             "%s(start): prod = 0x%04X, chain_prod = 0x%04X, "
7490             "prod_bseq = 0x%08X\n",
7491             __FUNCTION__, prod, chain_prod, prod_bseq);
7492
7493         /*
7494          * Cycle through each mbuf segment that makes up
7495          * the outgoing frame, gathering the mapping info
7496          * for that segment and creating a tx_bd for
7497          * the mbuf.
7498          */
7499         for (i = 0; i < nsegs ; i++) {
7500
7501                 chain_prod = TX_CHAIN_IDX(prod);
7502                 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)]
7503                     [TX_IDX(chain_prod)];
7504
7505                 txbd->tx_bd_haddr_lo =
7506                     htole32(BCE_ADDR_LO(segs[i].ds_addr));
7507                 txbd->tx_bd_haddr_hi =
7508                     htole32(BCE_ADDR_HI(segs[i].ds_addr));
7509                 txbd->tx_bd_mss_nbytes = htole32(mss << 16) |
7510                     htole16(segs[i].ds_len);
7511                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
7512                 txbd->tx_bd_flags = htole16(flags);
7513                 prod_bseq += segs[i].ds_len;
7514                 if (i == 0)
7515                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
7516                 prod = NEXT_TX_BD(prod);
7517         }
7518
7519         /* Set the END flag on the last TX buffer descriptor. */
7520         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
7521
7522         DBRUNMSG(BCE_EXTREME_SEND,
7523             bce_dump_tx_chain(sc, debug_prod, nsegs));
7524
7525         /*
7526          * Ensure that the mbuf pointer for this transmission
7527          * is placed at the array index of the last
7528          * descriptor in this chain.  This is done
7529          * because a single map is used for all
7530          * segments of the mbuf and we don't want to
7531          * unload the map before all of the segments
7532          * have been freed.
7533          */
7534         sc->tx_mbuf_ptr[chain_prod] = m0;
7535         sc->used_tx_bd += nsegs;
7536
7537         /* Update some debug statistic counters */
7538         DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
7539             sc->tx_hi_watermark = sc->used_tx_bd);
7540         DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
7541         DBRUNIF(sc->debug_tx_mbuf_alloc++);
7542
7543         DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1));
7544
7545         /* prod points to the next free tx_bd at this point. */
7546         sc->tx_prod = prod;
7547         sc->tx_prod_bseq = prod_bseq;
7548
7549         /* Tell the chip about the waiting TX frames. */
7550         REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) +
7551             BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod);
7552         REG_WR(sc, MB_GET_CID_ADDR(TX_CID) +
7553             BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq);
7554
7555 bce_tx_encap_exit:
7556         DBEXIT(BCE_VERBOSE_SEND);
7557         return(rc);
7558 }
7559
7560
7561 /****************************************************************************/
7562 /* Main transmit routine when called from another routine with a lock.      */
7563 /*                                                                          */
7564 /* Returns:                                                                 */
7565 /*   Nothing.                                                               */
7566 /****************************************************************************/
7567 static void
7568 bce_start_locked(struct ifnet *ifp)
7569 {
7570         struct bce_softc *sc = ifp->if_softc;
7571         struct mbuf *m_head = NULL;
7572         int count = 0;
7573         u16 tx_prod, tx_chain_prod;
7574
7575         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7576
7577         BCE_LOCK_ASSERT(sc);
7578
7579         /* prod points to the next free tx_bd. */
7580         tx_prod = sc->tx_prod;
7581         tx_chain_prod = TX_CHAIN_IDX(tx_prod);
7582
7583         DBPRINT(sc, BCE_INFO_SEND,
7584             "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
7585             "tx_prod_bseq = 0x%08X\n",
7586             __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq);
7587
7588         /* If there's no link or the transmit queue is empty then just exit. */
7589         if (sc->bce_link_up == FALSE) {
7590                 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n",
7591                     __FUNCTION__);
7592                 goto bce_start_locked_exit;
7593         }
7594
7595         if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
7596                 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n",
7597                     __FUNCTION__);
7598                 goto bce_start_locked_exit;
7599         }
7600
7601         /*
7602          * Keep adding entries while there is space in the ring.
7603          */
7604         while (sc->used_tx_bd < sc->max_tx_bd) {
7605
7606                 /* Check for any frames to send. */
7607                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
7608
7609                 /* Stop when the transmit queue is empty. */
7610                 if (m_head == NULL)
7611                         break;
7612
7613                 /*
7614                  * Pack the data into the transmit ring. If we
7615                  * don't have room, place the mbuf back at the
7616                  * head of the queue and set the OACTIVE flag
7617                  * to wait for the NIC to drain the chain.
7618                  */
7619                 if (bce_tx_encap(sc, &m_head)) {
7620                         if (m_head != NULL)
7621                                 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
7622                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
7623                         DBPRINT(sc, BCE_INFO_SEND,
7624                             "TX chain is closed for business! Total "
7625                             "tx_bd used = %d\n", sc->used_tx_bd);
7626                         break;
7627                 }
7628
7629                 count++;
7630
7631                 /* Send a copy of the frame to any BPF listeners. */
7632                 ETHER_BPF_MTAP(ifp, m_head);
7633         }
7634
7635         /* Exit if no packets were dequeued. */
7636         if (count == 0) {
7637                 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were "
7638                     "dequeued\n", __FUNCTION__);
7639                 goto bce_start_locked_exit;
7640         }
7641
7642         DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into "
7643             "send queue.\n", __FUNCTION__, count);
7644
7645         /* Set the tx timeout. */
7646         sc->watchdog_timer = BCE_TX_TIMEOUT;
7647
7648         DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID));
7649         DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc));
7650
7651 bce_start_locked_exit:
7652         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7653 }
7654
7655
7656 /****************************************************************************/
7657 /* Main transmit routine when called from another routine without a lock.   */
7658 /*                                                                          */
7659 /* Returns:                                                                 */
7660 /*   Nothing.                                                               */
7661 /****************************************************************************/
7662 static void
7663 bce_start(struct ifnet *ifp)
7664 {
7665         struct bce_softc *sc = ifp->if_softc;
7666
7667         DBENTER(BCE_VERBOSE_SEND);
7668
7669         BCE_LOCK(sc);
7670         bce_start_locked(ifp);
7671         BCE_UNLOCK(sc);
7672
7673         DBEXIT(BCE_VERBOSE_SEND);
7674 }
7675
7676
7677 /****************************************************************************/
7678 /* Handles any IOCTL calls from the operating system.                       */
7679 /*                                                                          */
7680 /* Returns:                                                                 */
7681 /*   0 for success, positive value for failure.                             */
7682 /****************************************************************************/
7683 static int
7684 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
7685 {
7686         struct bce_softc *sc = ifp->if_softc;
7687         struct ifreq *ifr = (struct ifreq *) data;
7688         struct mii_data *mii;
7689         int mask, error = 0;
7690
7691         DBENTER(BCE_VERBOSE_MISC);
7692
7693         switch(command) {
7694
7695         /* Set the interface MTU. */
7696         case SIOCSIFMTU:
7697                 /* Check that the MTU setting is supported. */
7698                 if ((ifr->ifr_mtu < BCE_MIN_MTU) ||
7699                         (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) {
7700                         error = EINVAL;
7701                         break;
7702                 }
7703
7704                 DBPRINT(sc, BCE_INFO_MISC,
7705                     "SIOCSIFMTU: Changing MTU from %d to %d\n",
7706                     (int) ifp->if_mtu, (int) ifr->ifr_mtu);
7707
7708                 BCE_LOCK(sc);
7709                 ifp->if_mtu = ifr->ifr_mtu;
7710                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7711                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
7712                         bce_init_locked(sc);
7713                 }
7714                 BCE_UNLOCK(sc);
7715                 break;
7716
7717         /* Set interface flags. */
7718         case SIOCSIFFLAGS:
7719                 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n");
7720
7721                 BCE_LOCK(sc);
7722
7723                 /* Check if the interface is up. */
7724                 if (ifp->if_flags & IFF_UP) {
7725                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7726                                 /* Change promiscuous/multicast flags as necessary. */
7727                                 bce_set_rx_mode(sc);
7728                         } else {
7729                                 /* Start the HW */
7730                                 bce_init_locked(sc);
7731                         }
7732                 } else {
7733                         /* The interface is down, check if driver is running. */
7734                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7735                                 bce_stop(sc);
7736
7737                                 /* If MFW is running, restart the controller a bit. */
7738                                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
7739                                         bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
7740                                         bce_chipinit(sc);
7741                                         bce_mgmt_init_locked(sc);
7742                                 }
7743                         }
7744                 }
7745
7746                 BCE_UNLOCK(sc);
7747                 break;
7748
7749         /* Add/Delete multicast address */
7750         case SIOCADDMULTI:
7751         case SIOCDELMULTI:
7752                 DBPRINT(sc, BCE_VERBOSE_MISC,
7753                     "Received SIOCADDMULTI/SIOCDELMULTI\n");
7754
7755                 BCE_LOCK(sc);
7756                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
7757                         bce_set_rx_mode(sc);
7758                 BCE_UNLOCK(sc);
7759
7760                 break;
7761
7762         /* Set/Get Interface media */
7763         case SIOCSIFMEDIA:
7764         case SIOCGIFMEDIA:
7765                 DBPRINT(sc, BCE_VERBOSE_MISC,
7766                     "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n");
7767                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
7768                         error = ifmedia_ioctl(ifp, ifr, &sc->bce_ifmedia,
7769                             command);
7770                 else {
7771                         mii = device_get_softc(sc->bce_miibus);
7772                         error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
7773                             command);
7774                 }
7775                 break;
7776
7777         /* Set interface capability */
7778         case SIOCSIFCAP:
7779                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
7780                 DBPRINT(sc, BCE_INFO_MISC,
7781                     "Received SIOCSIFCAP = 0x%08X\n", (u32) mask);
7782
7783                 /* Toggle the TX checksum capabilities enable flag. */
7784                 if (mask & IFCAP_TXCSUM &&
7785                     ifp->if_capabilities & IFCAP_TXCSUM) {
7786                         ifp->if_capenable ^= IFCAP_TXCSUM;
7787                         if (IFCAP_TXCSUM & ifp->if_capenable)
7788                                 ifp->if_hwassist |= BCE_IF_HWASSIST;
7789                         else
7790                                 ifp->if_hwassist &= ~BCE_IF_HWASSIST;
7791                 }
7792
7793                 /* Toggle the RX checksum capabilities enable flag. */
7794                 if (mask & IFCAP_RXCSUM &&
7795                     ifp->if_capabilities & IFCAP_RXCSUM)
7796                         ifp->if_capenable ^= IFCAP_RXCSUM;
7797
7798                 /* Toggle the TSO capabilities enable flag. */
7799                 if (bce_tso_enable && (mask & IFCAP_TSO4) &&
7800                     ifp->if_capabilities & IFCAP_TSO4) {
7801                         ifp->if_capenable ^= IFCAP_TSO4;
7802                         if (IFCAP_TSO4 & ifp->if_capenable)
7803                                 ifp->if_hwassist |= CSUM_TSO;
7804                         else
7805                                 ifp->if_hwassist &= ~CSUM_TSO;
7806                 }
7807
7808                 if (mask & IFCAP_VLAN_HWCSUM &&
7809                     ifp->if_capabilities & IFCAP_VLAN_HWCSUM)
7810                         ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
7811
7812                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
7813                     (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
7814                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
7815                 /*
7816                  * Don't actually disable VLAN tag stripping as
7817                  * management firmware (ASF/IPMI/UMP) requires the
7818                  * feature. If VLAN tag stripping is disabled driver
7819                  * will manually reconstruct the VLAN frame by
7820                  * appending stripped VLAN tag.
7821                  */
7822                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
7823                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) {
7824                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
7825                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
7826                             == 0)
7827                                 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
7828                 }
7829                 VLAN_CAPABILITIES(ifp);
7830                 break;
7831         default:
7832                 /* We don't know how to handle the IOCTL, pass it on. */
7833                 error = ether_ioctl(ifp, command, data);
7834                 break;
7835         }
7836
7837         DBEXIT(BCE_VERBOSE_MISC);
7838         return(error);
7839 }
7840
7841
7842 /****************************************************************************/
7843 /* Transmit timeout handler.                                                */
7844 /*                                                                          */
7845 /* Returns:                                                                 */
7846 /*   Nothing.                                                               */
7847 /****************************************************************************/
7848 static void
7849 bce_watchdog(struct bce_softc *sc)
7850 {
7851         uint32_t status;
7852
7853         DBENTER(BCE_EXTREME_SEND);
7854
7855         BCE_LOCK_ASSERT(sc);
7856
7857         status = 0;
7858         /* If the watchdog timer hasn't expired then just exit. */
7859         if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
7860                 goto bce_watchdog_exit;
7861
7862         status = REG_RD(sc, BCE_EMAC_RX_STATUS);
7863         /* If pause frames are active then don't reset the hardware. */
7864         if ((sc->bce_flags & BCE_USING_RX_FLOW_CONTROL) != 0) {
7865                 if ((status & BCE_EMAC_RX_STATUS_FFED) != 0) {
7866                         /*
7867                          * If link partner has us in XOFF state then wait for
7868                          * the condition to clear.
7869                          */
7870                         sc->watchdog_timer = BCE_TX_TIMEOUT;
7871                         goto bce_watchdog_exit;
7872                 } else if ((status & BCE_EMAC_RX_STATUS_FF_RECEIVED) != 0 &&
7873                         (status & BCE_EMAC_RX_STATUS_N_RECEIVED) != 0) {
7874                         /*
7875                          * If we're not currently XOFF'ed but have recently
7876                          * been XOFF'd/XON'd then assume that's delaying TX
7877                          * this time around.
7878                          */
7879                         sc->watchdog_timer = BCE_TX_TIMEOUT;
7880                         goto bce_watchdog_exit;
7881                 }
7882                 /*
7883                  * Any other condition is unexpected and the controller
7884                  * should be reset.
7885                  */
7886         }
7887
7888         BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n",
7889             __FILE__, __LINE__);
7890
7891         DBRUNMSG(BCE_INFO,
7892             bce_dump_driver_state(sc);
7893             bce_dump_status_block(sc);
7894             bce_dump_stats_block(sc);
7895             bce_dump_ftqs(sc);
7896             bce_dump_txp_state(sc, 0);
7897             bce_dump_rxp_state(sc, 0);
7898             bce_dump_tpat_state(sc, 0);
7899             bce_dump_cp_state(sc, 0);
7900             bce_dump_com_state(sc, 0));
7901
7902         DBRUN(bce_breakpoint(sc));
7903
7904         sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
7905
7906         bce_init_locked(sc);
7907         sc->watchdog_timeouts++;
7908
7909 bce_watchdog_exit:
7910         REG_WR(sc, BCE_EMAC_RX_STATUS, status);
7911         DBEXIT(BCE_EXTREME_SEND);
7912 }
7913
7914
7915 /*
7916  * Interrupt handler.
7917  */
7918 /****************************************************************************/
7919 /* Main interrupt entry point.  Verifies that the controller generated the  */
7920 /* interrupt and then calls a separate routine for handle the various       */
7921 /* interrupt causes (PHY, TX, RX).                                          */
7922 /*                                                                          */
7923 /* Returns:                                                                 */
7924 /*   Nothing.                                                               */
7925 /****************************************************************************/
7926 static void
7927 bce_intr(void *xsc)
7928 {
7929         struct bce_softc *sc;
7930         struct ifnet *ifp;
7931         u32 status_attn_bits;
7932         u16 hw_rx_cons, hw_tx_cons;
7933
7934         sc = xsc;
7935         ifp = sc->bce_ifp;
7936
7937         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
7938         DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
7939         DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc));
7940
7941         BCE_LOCK(sc);
7942
7943         DBRUN(sc->interrupts_generated++);
7944
7945         /* Synchnorize before we read from interface's status block */
7946         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
7947
7948         /*
7949          * If the hardware status block index matches the last value read
7950          * by the driver and we haven't asserted our interrupt then there's
7951          * nothing to do.  This may only happen in case of INTx due to the
7952          * interrupt arriving at the CPU before the status block is updated.
7953          */
7954         if ((sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) == 0 &&
7955             sc->status_block->status_idx == sc->last_status_idx &&
7956             (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
7957              BCE_PCICFG_MISC_STATUS_INTA_VALUE)) {
7958                 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n",
7959                     __FUNCTION__);
7960                 goto bce_intr_exit;
7961         }
7962
7963         /* Ack the interrupt and stop others from occurring. */
7964         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7965             BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
7966             BCE_PCICFG_INT_ACK_CMD_MASK_INT);
7967
7968         /* Check if the hardware has finished any work. */
7969         hw_rx_cons = bce_get_hw_rx_cons(sc);
7970         hw_tx_cons = bce_get_hw_tx_cons(sc);
7971
7972         /* Keep processing data as long as there is work to do. */
7973         for (;;) {
7974
7975                 status_attn_bits = sc->status_block->status_attn_bits;
7976
7977                 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control),
7978                     BCE_PRINTF("Simulating unexpected status attention "
7979                     "bit set.");
7980                     sc->unexpected_attention_sim_count++;
7981                     status_attn_bits = status_attn_bits |
7982                     STATUS_ATTN_BITS_PARITY_ERROR);
7983
7984                 /* Was it a link change interrupt? */
7985                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
7986                     (sc->status_block->status_attn_bits_ack &
7987                      STATUS_ATTN_BITS_LINK_STATE)) {
7988                         bce_phy_intr(sc);
7989
7990                         /* Clear transient updates during link state change. */
7991                         REG_WR(sc, BCE_HC_COMMAND, sc->hc_command |
7992                             BCE_HC_COMMAND_COAL_NOW_WO_INT);
7993                         REG_RD(sc, BCE_HC_COMMAND);
7994                 }
7995
7996                 /* If any other attention is asserted, the chip is toast. */
7997                 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
7998                     (sc->status_block->status_attn_bits_ack &
7999                     ~STATUS_ATTN_BITS_LINK_STATE))) {
8000
8001                         sc->unexpected_attention_count++;
8002
8003                         BCE_PRINTF("%s(%d): Fatal attention detected: "
8004                             "0x%08X\n", __FILE__, __LINE__,
8005                             sc->status_block->status_attn_bits);
8006
8007                         DBRUNMSG(BCE_FATAL,
8008                             if (unexpected_attention_sim_control == 0)
8009                                 bce_breakpoint(sc));
8010
8011                         bce_init_locked(sc);
8012                         goto bce_intr_exit;
8013                 }
8014
8015                 /* Check for any completed RX frames. */
8016                 if (hw_rx_cons != sc->hw_rx_cons)
8017                         bce_rx_intr(sc);
8018
8019                 /* Check for any completed TX frames. */
8020                 if (hw_tx_cons != sc->hw_tx_cons)
8021                         bce_tx_intr(sc);
8022
8023                 /* Save status block index value for the next interrupt. */
8024                 sc->last_status_idx = sc->status_block->status_idx;
8025
8026                 /*
8027                  * Prevent speculative reads from getting
8028                  * ahead of the status block.
8029                  */
8030                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
8031                     BUS_SPACE_BARRIER_READ);
8032
8033                 /*
8034                  * If there's no work left then exit the
8035                  * interrupt service routine.
8036                  */
8037                 hw_rx_cons = bce_get_hw_rx_cons(sc);
8038                 hw_tx_cons = bce_get_hw_tx_cons(sc);
8039
8040                 if ((hw_rx_cons == sc->hw_rx_cons) &&
8041                     (hw_tx_cons == sc->hw_tx_cons))
8042                         break;
8043         }
8044
8045         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREREAD);
8046
8047         /* Re-enable interrupts. */
8048         bce_enable_intr(sc, 0);
8049
8050         /* Handle any frames that arrived while handling the interrupt. */
8051         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
8052             !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
8053                 bce_start_locked(ifp);
8054
8055 bce_intr_exit:
8056         BCE_UNLOCK(sc);
8057
8058         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
8059 }
8060
8061
8062 /****************************************************************************/
8063 /* Programs the various packet receive modes (broadcast and multicast).     */
8064 /*                                                                          */
8065 /* Returns:                                                                 */
8066 /*   Nothing.                                                               */
8067 /****************************************************************************/
8068 static void
8069 bce_set_rx_mode(struct bce_softc *sc)
8070 {
8071         struct ifnet *ifp;
8072         struct ifmultiaddr *ifma;
8073         u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
8074         u32 rx_mode, sort_mode;
8075         int h, i;
8076
8077         DBENTER(BCE_VERBOSE_MISC);
8078
8079         BCE_LOCK_ASSERT(sc);
8080
8081         ifp = sc->bce_ifp;
8082
8083         /* Initialize receive mode default settings. */
8084         rx_mode   = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
8085             BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
8086         sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
8087
8088         /*
8089          * ASF/IPMI/UMP firmware requires that VLAN tag stripping
8090          * be enbled.
8091          */
8092         if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
8093             (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)))
8094                 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
8095
8096         /*
8097          * Check for promiscuous, all multicast, or selected
8098          * multicast address filtering.
8099          */
8100         if (ifp->if_flags & IFF_PROMISC) {
8101                 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n");
8102
8103                 /* Enable promiscuous mode. */
8104                 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
8105                 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
8106         } else if (ifp->if_flags & IFF_ALLMULTI) {
8107                 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n");
8108
8109                 /* Enable all multicast addresses. */
8110                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
8111                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
8112                             0xffffffff);
8113                 }
8114                 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
8115         } else {
8116                 /* Accept one or more multicast(s). */
8117                 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n");
8118
8119                 if_maddr_rlock(ifp);
8120                 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
8121                         if (ifma->ifma_addr->sa_family != AF_LINK)
8122                                 continue;
8123                         h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
8124                             ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF;
8125                             hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
8126                 }
8127                 if_maddr_runlock(ifp);
8128
8129                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++)
8130                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]);
8131
8132                 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
8133         }
8134
8135         /* Only make changes if the recive mode has actually changed. */
8136         if (rx_mode != sc->rx_mode) {
8137                 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: "
8138                     "0x%08X\n", rx_mode);
8139
8140                 sc->rx_mode = rx_mode;
8141                 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
8142         }
8143
8144         /* Disable and clear the exisitng sort before enabling a new sort. */
8145         REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
8146         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
8147         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
8148
8149         DBEXIT(BCE_VERBOSE_MISC);
8150 }
8151
8152
8153 /****************************************************************************/
8154 /* Called periodically to updates statistics from the controllers           */
8155 /* statistics block.                                                        */
8156 /*                                                                          */
8157 /* Returns:                                                                 */
8158 /*   Nothing.                                                               */
8159 /****************************************************************************/
8160 static void
8161 bce_stats_update(struct bce_softc *sc)
8162 {
8163         struct statistics_block *stats;
8164
8165         DBENTER(BCE_EXTREME_MISC);
8166
8167         bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD);
8168
8169         stats = (struct statistics_block *) sc->stats_block;
8170
8171         /*
8172          * Update the sysctl statistics from the
8173          * hardware statistics.
8174          */
8175         sc->stat_IfHCInOctets =
8176             ((u64) stats->stat_IfHCInOctets_hi << 32) +
8177              (u64) stats->stat_IfHCInOctets_lo;
8178
8179         sc->stat_IfHCInBadOctets =
8180             ((u64) stats->stat_IfHCInBadOctets_hi << 32) +
8181              (u64) stats->stat_IfHCInBadOctets_lo;
8182
8183         sc->stat_IfHCOutOctets =
8184             ((u64) stats->stat_IfHCOutOctets_hi << 32) +
8185              (u64) stats->stat_IfHCOutOctets_lo;
8186
8187         sc->stat_IfHCOutBadOctets =
8188             ((u64) stats->stat_IfHCOutBadOctets_hi << 32) +
8189              (u64) stats->stat_IfHCOutBadOctets_lo;
8190
8191         sc->stat_IfHCInUcastPkts =
8192             ((u64) stats->stat_IfHCInUcastPkts_hi << 32) +
8193              (u64) stats->stat_IfHCInUcastPkts_lo;
8194
8195         sc->stat_IfHCInMulticastPkts =
8196             ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) +
8197              (u64) stats->stat_IfHCInMulticastPkts_lo;
8198
8199         sc->stat_IfHCInBroadcastPkts =
8200             ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) +
8201              (u64) stats->stat_IfHCInBroadcastPkts_lo;
8202
8203         sc->stat_IfHCOutUcastPkts =
8204             ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) +
8205              (u64) stats->stat_IfHCOutUcastPkts_lo;
8206
8207         sc->stat_IfHCOutMulticastPkts =
8208             ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) +
8209              (u64) stats->stat_IfHCOutMulticastPkts_lo;
8210
8211         sc->stat_IfHCOutBroadcastPkts =
8212             ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) +
8213              (u64) stats->stat_IfHCOutBroadcastPkts_lo;
8214
8215         /* ToDo: Preserve counters beyond 32 bits? */
8216         /* ToDo: Read the statistics from auto-clear regs? */
8217
8218         sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
8219             stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
8220
8221         sc->stat_Dot3StatsCarrierSenseErrors =
8222             stats->stat_Dot3StatsCarrierSenseErrors;
8223
8224         sc->stat_Dot3StatsFCSErrors =
8225             stats->stat_Dot3StatsFCSErrors;
8226
8227         sc->stat_Dot3StatsAlignmentErrors =
8228             stats->stat_Dot3StatsAlignmentErrors;
8229
8230         sc->stat_Dot3StatsSingleCollisionFrames =
8231             stats->stat_Dot3StatsSingleCollisionFrames;
8232
8233         sc->stat_Dot3StatsMultipleCollisionFrames =
8234             stats->stat_Dot3StatsMultipleCollisionFrames;
8235
8236         sc->stat_Dot3StatsDeferredTransmissions =
8237             stats->stat_Dot3StatsDeferredTransmissions;
8238
8239         sc->stat_Dot3StatsExcessiveCollisions =
8240             stats->stat_Dot3StatsExcessiveCollisions;
8241
8242         sc->stat_Dot3StatsLateCollisions =
8243             stats->stat_Dot3StatsLateCollisions;
8244
8245         sc->stat_EtherStatsCollisions =
8246             stats->stat_EtherStatsCollisions;
8247
8248         sc->stat_EtherStatsFragments =
8249             stats->stat_EtherStatsFragments;
8250
8251         sc->stat_EtherStatsJabbers =
8252             stats->stat_EtherStatsJabbers;
8253
8254         sc->stat_EtherStatsUndersizePkts =
8255             stats->stat_EtherStatsUndersizePkts;
8256
8257         sc->stat_EtherStatsOversizePkts =
8258              stats->stat_EtherStatsOversizePkts;
8259
8260         sc->stat_EtherStatsPktsRx64Octets =
8261             stats->stat_EtherStatsPktsRx64Octets;
8262
8263         sc->stat_EtherStatsPktsRx65Octetsto127Octets =
8264             stats->stat_EtherStatsPktsRx65Octetsto127Octets;
8265
8266         sc->stat_EtherStatsPktsRx128Octetsto255Octets =
8267             stats->stat_EtherStatsPktsRx128Octetsto255Octets;
8268
8269         sc->stat_EtherStatsPktsRx256Octetsto511Octets =
8270             stats->stat_EtherStatsPktsRx256Octetsto511Octets;
8271
8272         sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
8273             stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
8274
8275         sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
8276             stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
8277
8278         sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
8279             stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
8280
8281         sc->stat_EtherStatsPktsTx64Octets =
8282             stats->stat_EtherStatsPktsTx64Octets;
8283
8284         sc->stat_EtherStatsPktsTx65Octetsto127Octets =
8285             stats->stat_EtherStatsPktsTx65Octetsto127Octets;
8286
8287         sc->stat_EtherStatsPktsTx128Octetsto255Octets =
8288             stats->stat_EtherStatsPktsTx128Octetsto255Octets;
8289
8290         sc->stat_EtherStatsPktsTx256Octetsto511Octets =
8291             stats->stat_EtherStatsPktsTx256Octetsto511Octets;
8292
8293         sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
8294             stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
8295
8296         sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
8297             stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
8298
8299         sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
8300             stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
8301
8302         sc->stat_XonPauseFramesReceived =
8303             stats->stat_XonPauseFramesReceived;
8304
8305         sc->stat_XoffPauseFramesReceived =
8306             stats->stat_XoffPauseFramesReceived;
8307
8308         sc->stat_OutXonSent =
8309             stats->stat_OutXonSent;
8310
8311         sc->stat_OutXoffSent =
8312             stats->stat_OutXoffSent;
8313
8314         sc->stat_FlowControlDone =
8315             stats->stat_FlowControlDone;
8316
8317         sc->stat_MacControlFramesReceived =
8318             stats->stat_MacControlFramesReceived;
8319
8320         sc->stat_XoffStateEntered =
8321             stats->stat_XoffStateEntered;
8322
8323         sc->stat_IfInFramesL2FilterDiscards =
8324             stats->stat_IfInFramesL2FilterDiscards;
8325
8326         sc->stat_IfInRuleCheckerDiscards =
8327             stats->stat_IfInRuleCheckerDiscards;
8328
8329         sc->stat_IfInFTQDiscards =
8330             stats->stat_IfInFTQDiscards;
8331
8332         sc->stat_IfInMBUFDiscards =
8333             stats->stat_IfInMBUFDiscards;
8334
8335         sc->stat_IfInRuleCheckerP4Hit =
8336             stats->stat_IfInRuleCheckerP4Hit;
8337
8338         sc->stat_CatchupInRuleCheckerDiscards =
8339             stats->stat_CatchupInRuleCheckerDiscards;
8340
8341         sc->stat_CatchupInFTQDiscards =
8342             stats->stat_CatchupInFTQDiscards;
8343
8344         sc->stat_CatchupInMBUFDiscards =
8345             stats->stat_CatchupInMBUFDiscards;
8346
8347         sc->stat_CatchupInRuleCheckerP4Hit =
8348             stats->stat_CatchupInRuleCheckerP4Hit;
8349
8350         sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
8351
8352         /* ToDo: Add additional statistics? */
8353
8354         DBEXIT(BCE_EXTREME_MISC);
8355 }
8356
8357 static uint64_t
8358 bce_get_counter(struct ifnet *ifp, ift_counter cnt)
8359 {
8360         struct bce_softc *sc;
8361         uint64_t rv;
8362
8363         sc = if_getsoftc(ifp);
8364
8365         switch (cnt) {
8366         case IFCOUNTER_COLLISIONS:
8367                 return (sc->stat_EtherStatsCollisions);
8368         case IFCOUNTER_IERRORS:
8369                 return (sc->stat_EtherStatsUndersizePkts +
8370                     sc->stat_EtherStatsOversizePkts +
8371                     sc->stat_IfInMBUFDiscards +
8372                     sc->stat_Dot3StatsAlignmentErrors +
8373                     sc->stat_Dot3StatsFCSErrors +
8374                     sc->stat_IfInRuleCheckerDiscards +
8375                     sc->stat_IfInFTQDiscards +
8376                     sc->l2fhdr_error_count +
8377                     sc->com_no_buffers);
8378         case IFCOUNTER_OERRORS:
8379                 rv = sc->stat_Dot3StatsExcessiveCollisions +
8380                     sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
8381                     sc->stat_Dot3StatsLateCollisions +
8382                     sc->watchdog_timeouts;
8383                 /*
8384                  * Certain controllers don't report
8385                  * carrier sense errors correctly.
8386                  * See errata E11_5708CA0_1165.
8387                  */
8388                 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
8389                     !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0))
8390                         rv += sc->stat_Dot3StatsCarrierSenseErrors;
8391                 return (rv);
8392         default:
8393                 return (if_get_counter_default(ifp, cnt));
8394         }
8395 }
8396
8397
8398 /****************************************************************************/
8399 /* Periodic function to notify the bootcode that the driver is still        */
8400 /* present.                                                                 */
8401 /*                                                                          */
8402 /* Returns:                                                                 */
8403 /*   Nothing.                                                               */
8404 /****************************************************************************/
8405 static void
8406 bce_pulse(void *xsc)
8407 {
8408         struct bce_softc *sc = xsc;
8409         u32 msg;
8410
8411         DBENTER(BCE_EXTREME_MISC);
8412
8413         BCE_LOCK_ASSERT(sc);
8414
8415         /* Tell the firmware that the driver is still running. */
8416         msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq;
8417         bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
8418
8419         /* Update the bootcode condition. */
8420         sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
8421
8422         /* Report whether the bootcode still knows the driver is running. */
8423         if (bce_verbose || bootverbose) {
8424                 if (sc->bce_drv_cardiac_arrest == FALSE) {
8425                         if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
8426                                 sc->bce_drv_cardiac_arrest = TRUE;
8427                                 BCE_PRINTF("%s(): Warning: bootcode "
8428                                     "thinks driver is absent! "
8429                                     "(bc_state = 0x%08X)\n",
8430                                     __FUNCTION__, sc->bc_state);
8431                         }
8432                 } else {
8433                         /*
8434                          * Not supported by all bootcode versions.
8435                          * (v5.0.11+ and v5.2.1+)  Older bootcode
8436                          * will require the driver to reset the
8437                          * controller to clear this condition.
8438                          */
8439                         if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
8440                                 sc->bce_drv_cardiac_arrest = FALSE;
8441                                 BCE_PRINTF("%s(): Bootcode found the "
8442                                     "driver pulse! (bc_state = 0x%08X)\n",
8443                                     __FUNCTION__, sc->bc_state);
8444                         }
8445                 }
8446         }
8447
8448
8449         /* Schedule the next pulse. */
8450         callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
8451
8452         DBEXIT(BCE_EXTREME_MISC);
8453 }
8454
8455
8456 /****************************************************************************/
8457 /* Periodic function to perform maintenance tasks.                          */
8458 /*                                                                          */
8459 /* Returns:                                                                 */
8460 /*   Nothing.                                                               */
8461 /****************************************************************************/
8462 static void
8463 bce_tick(void *xsc)
8464 {
8465         struct bce_softc *sc = xsc;
8466         struct mii_data *mii;
8467         struct ifnet *ifp;
8468         struct ifmediareq ifmr;
8469
8470         ifp = sc->bce_ifp;
8471
8472         DBENTER(BCE_EXTREME_MISC);
8473
8474         BCE_LOCK_ASSERT(sc);
8475
8476         /* Schedule the next tick. */
8477         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
8478
8479         /* Update the statistics from the hardware statistics block. */
8480         bce_stats_update(sc);
8481
8482         /* Ensure page and RX chains get refilled in low-memory situations. */
8483         if (bce_hdr_split == TRUE)
8484                 bce_fill_pg_chain(sc);
8485         bce_fill_rx_chain(sc);
8486
8487         /* Check that chip hasn't hung. */
8488         bce_watchdog(sc);
8489
8490         /* If link is up already up then we're done. */
8491         if (sc->bce_link_up == TRUE)
8492                 goto bce_tick_exit;
8493
8494         /* Link is down.  Check what the PHY's doing. */
8495         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
8496                 bzero(&ifmr, sizeof(ifmr));
8497                 bce_ifmedia_sts_rphy(sc, &ifmr);
8498                 if ((ifmr.ifm_status & (IFM_ACTIVE | IFM_AVALID)) ==
8499                     (IFM_ACTIVE | IFM_AVALID)) {
8500                         sc->bce_link_up = TRUE;
8501                         bce_miibus_statchg(sc->bce_dev);
8502                 }
8503         } else {
8504                 mii = device_get_softc(sc->bce_miibus);
8505                 mii_tick(mii);
8506                 /* Check if the link has come up. */
8507                 if ((mii->mii_media_status & IFM_ACTIVE) &&
8508                     (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) {
8509                         DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n",
8510                             __FUNCTION__);
8511                         sc->bce_link_up = TRUE;
8512                         if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
8513                             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX ||
8514                             IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) &&
8515                             (bce_verbose || bootverbose))
8516                                 BCE_PRINTF("Gigabit link up!\n");
8517                 }
8518
8519         }
8520         if (sc->bce_link_up == TRUE) {
8521                 /* Now that link is up, handle any outstanding TX traffic. */
8522                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
8523                         DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found "
8524                             "pending TX traffic.\n", __FUNCTION__);
8525                         bce_start_locked(ifp);
8526                 }
8527         }
8528
8529 bce_tick_exit:
8530         DBEXIT(BCE_EXTREME_MISC);
8531 }
8532
8533 static void
8534 bce_fw_cap_init(struct bce_softc *sc)
8535 {
8536         u32 ack, cap, link;
8537
8538         ack = 0;
8539         cap = bce_shmem_rd(sc, BCE_FW_CAP_MB);
8540         if ((cap & BCE_FW_CAP_SIGNATURE_MAGIC_MASK) !=
8541             BCE_FW_CAP_SIGNATURE_MAGIC)
8542                 return;
8543         if ((cap & (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) ==
8544             (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN))
8545                 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC |
8546                     BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN;
8547         if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 &&
8548             (cap & BCE_FW_CAP_REMOTE_PHY_CAP) != 0) {
8549                 sc->bce_phy_flags &= ~BCE_PHY_REMOTE_PORT_FIBER_FLAG;
8550                 sc->bce_phy_flags |= BCE_PHY_REMOTE_CAP_FLAG;
8551                 link = bce_shmem_rd(sc, BCE_LINK_STATUS);
8552                 if ((link & BCE_LINK_STATUS_SERDES_LINK) != 0)
8553                         sc->bce_phy_flags |= BCE_PHY_REMOTE_PORT_FIBER_FLAG;
8554                 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC |
8555                     BCE_FW_CAP_REMOTE_PHY_CAP;
8556         }
8557
8558         if (ack != 0)
8559                 bce_shmem_wr(sc, BCE_DRV_ACK_CAP_MB, ack);
8560 }
8561
8562
8563 #ifdef BCE_DEBUG
8564 /****************************************************************************/
8565 /* Allows the driver state to be dumped through the sysctl interface.       */
8566 /*                                                                          */
8567 /* Returns:                                                                 */
8568 /*   0 for success, positive value for failure.                             */
8569 /****************************************************************************/
8570 static int
8571 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
8572 {
8573         int error;
8574         int result;
8575         struct bce_softc *sc;
8576
8577         result = -1;
8578         error = sysctl_handle_int(oidp, &result, 0, req);
8579
8580         if (error || !req->newptr)
8581                 return (error);
8582
8583         if (result == 1) {
8584                 sc = (struct bce_softc *)arg1;
8585                 bce_dump_driver_state(sc);
8586         }
8587
8588         return error;
8589 }
8590
8591
8592 /****************************************************************************/
8593 /* Allows the hardware state to be dumped through the sysctl interface.     */
8594 /*                                                                          */
8595 /* Returns:                                                                 */
8596 /*   0 for success, positive value for failure.                             */
8597 /****************************************************************************/
8598 static int
8599 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
8600 {
8601         int error;
8602         int result;
8603         struct bce_softc *sc;
8604
8605         result = -1;
8606         error = sysctl_handle_int(oidp, &result, 0, req);
8607
8608         if (error || !req->newptr)
8609                 return (error);
8610
8611         if (result == 1) {
8612                 sc = (struct bce_softc *)arg1;
8613                 bce_dump_hw_state(sc);
8614         }
8615
8616         return error;
8617 }
8618
8619
8620 /****************************************************************************/
8621 /* Allows the status block to be dumped through the sysctl interface.       */
8622 /*                                                                          */
8623 /* Returns:                                                                 */
8624 /*   0 for success, positive value for failure.                             */
8625 /****************************************************************************/
8626 static int
8627 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS)
8628 {
8629         int error;
8630         int result;
8631         struct bce_softc *sc;
8632
8633         result = -1;
8634         error = sysctl_handle_int(oidp, &result, 0, req);
8635
8636         if (error || !req->newptr)
8637                 return (error);
8638
8639         if (result == 1) {
8640                 sc = (struct bce_softc *)arg1;
8641                 bce_dump_status_block(sc);
8642         }
8643
8644         return error;
8645 }
8646
8647
8648 /****************************************************************************/
8649 /* Allows the stats block to be dumped through the sysctl interface.        */
8650 /*                                                                          */
8651 /* Returns:                                                                 */
8652 /*   0 for success, positive value for failure.                             */
8653 /****************************************************************************/
8654 static int
8655 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS)
8656 {
8657         int error;
8658         int result;
8659         struct bce_softc *sc;
8660
8661         result = -1;
8662         error = sysctl_handle_int(oidp, &result, 0, req);
8663
8664         if (error || !req->newptr)
8665                 return (error);
8666
8667         if (result == 1) {
8668                 sc = (struct bce_softc *)arg1;
8669                 bce_dump_stats_block(sc);
8670         }
8671
8672         return error;
8673 }
8674
8675
8676 /****************************************************************************/
8677 /* Allows the stat counters to be cleared without unloading/reloading the   */
8678 /* driver.                                                                  */
8679 /*                                                                          */
8680 /* Returns:                                                                 */
8681 /*   0 for success, positive value for failure.                             */
8682 /****************************************************************************/
8683 static int
8684 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS)
8685 {
8686         int error;
8687         int result;
8688         struct bce_softc *sc;
8689
8690         result = -1;
8691         error = sysctl_handle_int(oidp, &result, 0, req);
8692
8693         if (error || !req->newptr)
8694                 return (error);
8695
8696         if (result == 1) {
8697                 sc = (struct bce_softc *)arg1;
8698                 struct statistics_block *stats;
8699
8700                 stats = (struct statistics_block *) sc->stats_block;
8701                 bzero(stats, sizeof(struct statistics_block));
8702                 bus_dmamap_sync(sc->stats_tag, sc->stats_map,
8703                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
8704
8705                 /* Clear the internal H/W statistics counters. */
8706                 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
8707
8708                 /* Reset the driver maintained statistics. */
8709                 sc->interrupts_rx =
8710                     sc->interrupts_tx = 0;
8711                 sc->tso_frames_requested =
8712                     sc->tso_frames_completed =
8713                     sc->tso_frames_failed = 0;
8714                 sc->rx_empty_count =
8715                     sc->tx_full_count = 0;
8716                 sc->rx_low_watermark = USABLE_RX_BD_ALLOC;
8717                 sc->tx_hi_watermark = 0;
8718                 sc->l2fhdr_error_count =
8719                     sc->l2fhdr_error_sim_count = 0;
8720                 sc->mbuf_alloc_failed_count =
8721                     sc->mbuf_alloc_failed_sim_count = 0;
8722                 sc->dma_map_addr_rx_failed_count =
8723                     sc->dma_map_addr_tx_failed_count = 0;
8724                 sc->mbuf_frag_count = 0;
8725                 sc->csum_offload_tcp_udp =
8726                     sc->csum_offload_ip = 0;
8727                 sc->vlan_tagged_frames_rcvd =
8728                     sc->vlan_tagged_frames_stripped = 0;
8729                 sc->split_header_frames_rcvd =
8730                     sc->split_header_tcp_frames_rcvd = 0;
8731
8732                 /* Clear firmware maintained statistics. */
8733                 REG_WR_IND(sc, 0x120084, 0);
8734         }
8735
8736         return error;
8737 }
8738
8739
8740 /****************************************************************************/
8741 /* Allows the shared memory contents to be dumped through the sysctl  .     */
8742 /* interface.                                                               */
8743 /*                                                                          */
8744 /* Returns:                                                                 */
8745 /*   0 for success, positive value for failure.                             */
8746 /****************************************************************************/
8747 static int
8748 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS)
8749 {
8750         int error;
8751         int result;
8752         struct bce_softc *sc;
8753
8754         result = -1;
8755         error = sysctl_handle_int(oidp, &result, 0, req);
8756
8757         if (error || !req->newptr)
8758                 return (error);
8759
8760         if (result == 1) {
8761                 sc = (struct bce_softc *)arg1;
8762                 bce_dump_shmem_state(sc);
8763         }
8764
8765         return error;
8766 }
8767
8768
8769 /****************************************************************************/
8770 /* Allows the bootcode state to be dumped through the sysctl interface.     */
8771 /*                                                                          */
8772 /* Returns:                                                                 */
8773 /*   0 for success, positive value for failure.                             */
8774 /****************************************************************************/
8775 static int
8776 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS)
8777 {
8778         int error;
8779         int result;
8780         struct bce_softc *sc;
8781
8782         result = -1;
8783         error = sysctl_handle_int(oidp, &result, 0, req);
8784
8785         if (error || !req->newptr)
8786                 return (error);
8787
8788         if (result == 1) {
8789                 sc = (struct bce_softc *)arg1;
8790                 bce_dump_bc_state(sc);
8791         }
8792
8793         return error;
8794 }
8795
8796
8797 /****************************************************************************/
8798 /* Provides a sysctl interface to allow dumping the RX BD chain.            */
8799 /*                                                                          */
8800 /* Returns:                                                                 */
8801 /*   0 for success, positive value for failure.                             */
8802 /****************************************************************************/
8803 static int
8804 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS)
8805 {
8806         int error;
8807         int result;
8808         struct bce_softc *sc;
8809
8810         result = -1;
8811         error = sysctl_handle_int(oidp, &result, 0, req);
8812
8813         if (error || !req->newptr)
8814                 return (error);
8815
8816         if (result == 1) {
8817                 sc = (struct bce_softc *)arg1;
8818                 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC);
8819         }
8820
8821         return error;
8822 }
8823
8824
8825 /****************************************************************************/
8826 /* Provides a sysctl interface to allow dumping the RX MBUF chain.          */
8827 /*                                                                          */
8828 /* Returns:                                                                 */
8829 /*   0 for success, positive value for failure.                             */
8830 /****************************************************************************/
8831 static int
8832 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS)
8833 {
8834         int error;
8835         int result;
8836         struct bce_softc *sc;
8837
8838         result = -1;
8839         error = sysctl_handle_int(oidp, &result, 0, req);
8840
8841         if (error || !req->newptr)
8842                 return (error);
8843
8844         if (result == 1) {
8845                 sc = (struct bce_softc *)arg1;
8846                 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC);
8847         }
8848
8849         return error;
8850 }
8851
8852
8853 /****************************************************************************/
8854 /* Provides a sysctl interface to allow dumping the TX chain.               */
8855 /*                                                                          */
8856 /* Returns:                                                                 */
8857 /*   0 for success, positive value for failure.                             */
8858 /****************************************************************************/
8859 static int
8860 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
8861 {
8862         int error;
8863         int result;
8864         struct bce_softc *sc;
8865
8866         result = -1;
8867         error = sysctl_handle_int(oidp, &result, 0, req);
8868
8869         if (error || !req->newptr)
8870                 return (error);
8871
8872         if (result == 1) {
8873                 sc = (struct bce_softc *)arg1;
8874                 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC);
8875         }
8876
8877         return error;
8878 }
8879
8880
8881 /****************************************************************************/
8882 /* Provides a sysctl interface to allow dumping the page chain.             */
8883 /*                                                                          */
8884 /* Returns:                                                                 */
8885 /*   0 for success, positive value for failure.                             */
8886 /****************************************************************************/
8887 static int
8888 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS)
8889 {
8890         int error;
8891         int result;
8892         struct bce_softc *sc;
8893
8894         result = -1;
8895         error = sysctl_handle_int(oidp, &result, 0, req);
8896
8897         if (error || !req->newptr)
8898                 return (error);
8899
8900         if (result == 1) {
8901                 sc = (struct bce_softc *)arg1;
8902                 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC);
8903         }
8904
8905         return error;
8906 }
8907
8908 /****************************************************************************/
8909 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in  */
8910 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
8911 /*                                                                          */
8912 /* Returns:                                                                 */
8913 /*   0 for success, positive value for failure.                             */
8914 /****************************************************************************/
8915 static int
8916 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS)
8917 {
8918         struct bce_softc *sc = (struct bce_softc *)arg1;
8919         int error;
8920         u32 result;
8921         u32 val[1];
8922         u8 *data = (u8 *) val;
8923
8924         result = -1;
8925         error = sysctl_handle_int(oidp, &result, 0, req);
8926         if (error || (req->newptr == NULL))
8927                 return (error);
8928
8929         error = bce_nvram_read(sc, result, data, 4);
8930
8931         BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0]));
8932
8933         return (error);
8934 }
8935
8936
8937 /****************************************************************************/
8938 /* Provides a sysctl interface to allow reading arbitrary registers in the  */
8939 /* device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                            */
8940 /*                                                                          */
8941 /* Returns:                                                                 */
8942 /*   0 for success, positive value for failure.                             */
8943 /****************************************************************************/
8944 static int
8945 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
8946 {
8947         struct bce_softc *sc = (struct bce_softc *)arg1;
8948         int error;
8949         u32 val, result;
8950
8951         result = -1;
8952         error = sysctl_handle_int(oidp, &result, 0, req);
8953         if (error || (req->newptr == NULL))
8954                 return (error);
8955
8956         /* Make sure the register is accessible. */
8957         if (result < 0x8000) {
8958                 val = REG_RD(sc, result);
8959                 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8960         } else if (result < 0x0280000) {
8961                 val = REG_RD_IND(sc, result);
8962                 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8963         }
8964
8965         return (error);
8966 }
8967
8968
8969 /****************************************************************************/
8970 /* Provides a sysctl interface to allow reading arbitrary PHY registers in  */
8971 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
8972 /*                                                                          */
8973 /* Returns:                                                                 */
8974 /*   0 for success, positive value for failure.                             */
8975 /****************************************************************************/
8976 static int
8977 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
8978 {
8979         struct bce_softc *sc;
8980         device_t dev;
8981         int error, result;
8982         u16 val;
8983
8984         result = -1;
8985         error = sysctl_handle_int(oidp, &result, 0, req);
8986         if (error || (req->newptr == NULL))
8987                 return (error);
8988
8989         /* Make sure the register is accessible. */
8990         if (result < 0x20) {
8991                 sc = (struct bce_softc *)arg1;
8992                 dev = sc->bce_dev;
8993                 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
8994                 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val);
8995         }
8996         return (error);
8997 }
8998
8999
9000 /****************************************************************************/
9001 /* Provides a sysctl interface for dumping the nvram contents.              */
9002 /* DO NOT ENABLE ON PRODUCTION SYSTEMS!                                     */
9003 /*                                                                          */
9004 /* Returns:                                                                 */
9005 /*   0 for success, positive errno for failure.                             */
9006 /****************************************************************************/
9007 static int
9008 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS)
9009 {
9010         struct bce_softc *sc = (struct bce_softc *)arg1;
9011         int error, i;
9012
9013         if (sc->nvram_buf == NULL)
9014                 sc->nvram_buf = malloc(sc->bce_flash_size,
9015                                     M_TEMP, M_ZERO | M_WAITOK);
9016
9017         error = 0;
9018         if (req->oldlen == sc->bce_flash_size) {
9019                 for (i = 0; i < sc->bce_flash_size && error == 0; i++)
9020                         error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1);
9021         }
9022
9023         if (error == 0)
9024                 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size);
9025
9026         return error;
9027 }
9028
9029 #ifdef BCE_NVRAM_WRITE_SUPPORT
9030 /****************************************************************************/
9031 /* Provides a sysctl interface for writing to nvram.                        */
9032 /* DO NOT ENABLE ON PRODUCTION SYSTEMS!                                     */
9033 /*                                                                          */
9034 /* Returns:                                                                 */
9035 /*   0 for success, positive errno for failure.                             */
9036 /****************************************************************************/
9037 static int
9038 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS)
9039 {
9040         struct bce_softc *sc = (struct bce_softc *)arg1;
9041         int error;
9042
9043         if (sc->nvram_buf == NULL)
9044                 sc->nvram_buf = malloc(sc->bce_flash_size,
9045                                     M_TEMP, M_ZERO | M_WAITOK);
9046         else
9047                 bzero(sc->nvram_buf, sc->bce_flash_size);
9048
9049         error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size);
9050         if (error == 0)
9051                 return (error);
9052
9053         if (req->newlen == sc->bce_flash_size)
9054                 error = bce_nvram_write(sc, 0, sc->nvram_buf,
9055                             sc->bce_flash_size);
9056
9057
9058         return error;
9059 }
9060 #endif
9061
9062
9063 /****************************************************************************/
9064 /* Provides a sysctl interface to allow reading a CID.                      */
9065 /*                                                                          */
9066 /* Returns:                                                                 */
9067 /*   0 for success, positive value for failure.                             */
9068 /****************************************************************************/
9069 static int
9070 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS)
9071 {
9072         struct bce_softc *sc;
9073         int error, result;
9074
9075         result = -1;
9076         error = sysctl_handle_int(oidp, &result, 0, req);
9077         if (error || (req->newptr == NULL))
9078                 return (error);
9079
9080         /* Make sure the register is accessible. */
9081         if (result <= TX_CID) {
9082                 sc = (struct bce_softc *)arg1;
9083                 bce_dump_ctx(sc, result);
9084         }
9085
9086         return (error);
9087 }
9088
9089
9090 /****************************************************************************/
9091 /* Provides a sysctl interface to forcing the driver to dump state and      */
9092 /* enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                */
9093 /*                                                                          */
9094 /* Returns:                                                                 */
9095 /*   0 for success, positive value for failure.                             */
9096 /****************************************************************************/
9097 static int
9098 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
9099 {
9100         int error;
9101         int result;
9102         struct bce_softc *sc;
9103
9104         result = -1;
9105         error = sysctl_handle_int(oidp, &result, 0, req);
9106
9107         if (error || !req->newptr)
9108                 return (error);
9109
9110         if (result == 1) {
9111                 sc = (struct bce_softc *)arg1;
9112                 bce_breakpoint(sc);
9113         }
9114
9115         return error;
9116 }
9117 #endif
9118
9119 /****************************************************************************/
9120 /* Adds any sysctl parameters for tuning or debugging purposes.             */
9121 /*                                                                          */
9122 /* Returns:                                                                 */
9123 /*   0 for success, positive value for failure.                             */
9124 /****************************************************************************/
9125 static void
9126 bce_add_sysctls(struct bce_softc *sc)
9127 {
9128         struct sysctl_ctx_list *ctx;
9129         struct sysctl_oid_list *children;
9130
9131         DBENTER(BCE_VERBOSE_MISC);
9132
9133         ctx = device_get_sysctl_ctx(sc->bce_dev);
9134         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev));
9135
9136 #ifdef BCE_DEBUG
9137         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9138             "l2fhdr_error_sim_control",
9139             CTLFLAG_RW, &l2fhdr_error_sim_control,
9140             0, "Debug control to force l2fhdr errors");
9141
9142         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9143             "l2fhdr_error_sim_count",
9144             CTLFLAG_RD, &sc->l2fhdr_error_sim_count,
9145             0, "Number of simulated l2_fhdr errors");
9146 #endif
9147
9148         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9149             "l2fhdr_error_count",
9150             CTLFLAG_RD, &sc->l2fhdr_error_count,
9151             0, "Number of l2_fhdr errors");
9152
9153 #ifdef BCE_DEBUG
9154         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9155             "mbuf_alloc_failed_sim_control",
9156             CTLFLAG_RW, &mbuf_alloc_failed_sim_control,
9157             0, "Debug control to force mbuf allocation failures");
9158
9159         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9160             "mbuf_alloc_failed_sim_count",
9161             CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count,
9162             0, "Number of simulated mbuf cluster allocation failures");
9163 #endif
9164
9165         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9166             "mbuf_alloc_failed_count",
9167             CTLFLAG_RD, &sc->mbuf_alloc_failed_count,
9168             0, "Number of mbuf allocation failures");
9169
9170         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9171             "mbuf_frag_count",
9172             CTLFLAG_RD, &sc->mbuf_frag_count,
9173             0, "Number of fragmented mbufs");
9174
9175 #ifdef BCE_DEBUG
9176         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9177             "dma_map_addr_failed_sim_control",
9178             CTLFLAG_RW, &dma_map_addr_failed_sim_control,
9179             0, "Debug control to force DMA mapping failures");
9180
9181         /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */
9182         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9183             "dma_map_addr_failed_sim_count",
9184             CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count,
9185             0, "Number of simulated DMA mapping failures");
9186
9187 #endif
9188
9189         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9190             "dma_map_addr_rx_failed_count",
9191             CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count,
9192             0, "Number of RX DMA mapping failures");
9193
9194         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9195             "dma_map_addr_tx_failed_count",
9196             CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count,
9197             0, "Number of TX DMA mapping failures");
9198
9199 #ifdef BCE_DEBUG
9200         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9201             "unexpected_attention_sim_control",
9202             CTLFLAG_RW, &unexpected_attention_sim_control,
9203             0, "Debug control to simulate unexpected attentions");
9204
9205         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9206             "unexpected_attention_sim_count",
9207             CTLFLAG_RW, &sc->unexpected_attention_sim_count,
9208             0, "Number of simulated unexpected attentions");
9209 #endif
9210
9211         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9212             "unexpected_attention_count",
9213             CTLFLAG_RW, &sc->unexpected_attention_count,
9214             0, "Number of unexpected attentions");
9215
9216 #ifdef BCE_DEBUG
9217         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9218             "debug_bootcode_running_failure",
9219             CTLFLAG_RW, &bootcode_running_failure_sim_control,
9220             0, "Debug control to force bootcode running failures");
9221
9222         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9223             "rx_low_watermark",
9224             CTLFLAG_RD, &sc->rx_low_watermark,
9225             0, "Lowest level of free rx_bd's");
9226
9227         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9228             "rx_empty_count",
9229             CTLFLAG_RD, &sc->rx_empty_count,
9230             "Number of times the RX chain was empty");
9231
9232         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9233             "tx_hi_watermark",
9234             CTLFLAG_RD, &sc->tx_hi_watermark,
9235             0, "Highest level of used tx_bd's");
9236
9237         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9238             "tx_full_count",
9239             CTLFLAG_RD, &sc->tx_full_count,
9240             "Number of times the TX chain was full");
9241
9242         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9243             "tso_frames_requested",
9244             CTLFLAG_RD, &sc->tso_frames_requested,
9245             "Number of TSO frames requested");
9246
9247         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9248             "tso_frames_completed",
9249             CTLFLAG_RD, &sc->tso_frames_completed,
9250             "Number of TSO frames completed");
9251
9252         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9253             "tso_frames_failed",
9254             CTLFLAG_RD, &sc->tso_frames_failed,
9255             "Number of TSO frames failed");
9256
9257         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9258             "csum_offload_ip",
9259             CTLFLAG_RD, &sc->csum_offload_ip,
9260             "Number of IP checksum offload frames");
9261
9262         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9263             "csum_offload_tcp_udp",
9264             CTLFLAG_RD, &sc->csum_offload_tcp_udp,
9265             "Number of TCP/UDP checksum offload frames");
9266
9267         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9268             "vlan_tagged_frames_rcvd",
9269             CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd,
9270             "Number of VLAN tagged frames received");
9271
9272         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9273             "vlan_tagged_frames_stripped",
9274             CTLFLAG_RD, &sc->vlan_tagged_frames_stripped,
9275             "Number of VLAN tagged frames stripped");
9276
9277         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9278             "interrupts_rx",
9279             CTLFLAG_RD, &sc->interrupts_rx,
9280             "Number of RX interrupts");
9281
9282         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9283             "interrupts_tx",
9284             CTLFLAG_RD, &sc->interrupts_tx,
9285             "Number of TX interrupts");
9286
9287         if (bce_hdr_split == TRUE) {
9288                 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9289                     "split_header_frames_rcvd",
9290                     CTLFLAG_RD, &sc->split_header_frames_rcvd,
9291                     "Number of split header frames received");
9292
9293                 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9294                     "split_header_tcp_frames_rcvd",
9295                     CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd,
9296                     "Number of split header TCP frames received");
9297         }
9298
9299         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9300             "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD,
9301             (void *)sc, 0,
9302             bce_sysctl_nvram_dump, "S", "");
9303
9304 #ifdef BCE_NVRAM_WRITE_SUPPORT
9305         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9306             "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR,
9307             (void *)sc, 0,
9308             bce_sysctl_nvram_write, "S", "");
9309 #endif
9310 #endif /* BCE_DEBUG */
9311
9312         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9313             "stat_IfHcInOctets",
9314             CTLFLAG_RD, &sc->stat_IfHCInOctets,
9315             "Bytes received");
9316
9317         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9318             "stat_IfHCInBadOctets",
9319             CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
9320             "Bad bytes received");
9321
9322         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9323             "stat_IfHCOutOctets",
9324             CTLFLAG_RD, &sc->stat_IfHCOutOctets,
9325             "Bytes sent");
9326
9327         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9328             "stat_IfHCOutBadOctets",
9329             CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
9330             "Bad bytes sent");
9331
9332         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9333             "stat_IfHCInUcastPkts",
9334             CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
9335             "Unicast packets received");
9336
9337         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9338             "stat_IfHCInMulticastPkts",
9339             CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
9340             "Multicast packets received");
9341
9342         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9343             "stat_IfHCInBroadcastPkts",
9344             CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
9345             "Broadcast packets received");
9346
9347         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9348             "stat_IfHCOutUcastPkts",
9349             CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
9350             "Unicast packets sent");
9351
9352         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9353             "stat_IfHCOutMulticastPkts",
9354             CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
9355             "Multicast packets sent");
9356
9357         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9358             "stat_IfHCOutBroadcastPkts",
9359             CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
9360             "Broadcast packets sent");
9361
9362         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9363             "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
9364             CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
9365             0, "Internal MAC transmit errors");
9366
9367         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9368             "stat_Dot3StatsCarrierSenseErrors",
9369             CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
9370             0, "Carrier sense errors");
9371
9372         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9373             "stat_Dot3StatsFCSErrors",
9374             CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
9375             0, "Frame check sequence errors");
9376
9377         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9378             "stat_Dot3StatsAlignmentErrors",
9379             CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
9380             0, "Alignment errors");
9381
9382         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9383             "stat_Dot3StatsSingleCollisionFrames",
9384             CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
9385             0, "Single Collision Frames");
9386
9387         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9388             "stat_Dot3StatsMultipleCollisionFrames",
9389             CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
9390             0, "Multiple Collision Frames");
9391
9392         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9393             "stat_Dot3StatsDeferredTransmissions",
9394             CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
9395             0, "Deferred Transmissions");
9396
9397         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9398             "stat_Dot3StatsExcessiveCollisions",
9399             CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
9400             0, "Excessive Collisions");
9401
9402         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9403             "stat_Dot3StatsLateCollisions",
9404             CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
9405             0, "Late Collisions");
9406
9407         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9408             "stat_EtherStatsCollisions",
9409             CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
9410             0, "Collisions");
9411
9412         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9413             "stat_EtherStatsFragments",
9414             CTLFLAG_RD, &sc->stat_EtherStatsFragments,
9415             0, "Fragments");
9416
9417         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9418             "stat_EtherStatsJabbers",
9419             CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
9420             0, "Jabbers");
9421
9422         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9423             "stat_EtherStatsUndersizePkts",
9424             CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
9425             0, "Undersize packets");
9426
9427         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9428             "stat_EtherStatsOversizePkts",
9429             CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts,
9430             0, "stat_EtherStatsOversizePkts");
9431
9432         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9433             "stat_EtherStatsPktsRx64Octets",
9434             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
9435             0, "Bytes received in 64 byte packets");
9436
9437         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9438             "stat_EtherStatsPktsRx65Octetsto127Octets",
9439             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
9440             0, "Bytes received in 65 to 127 byte packets");
9441
9442         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9443             "stat_EtherStatsPktsRx128Octetsto255Octets",
9444             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
9445             0, "Bytes received in 128 to 255 byte packets");
9446
9447         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9448             "stat_EtherStatsPktsRx256Octetsto511Octets",
9449             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
9450             0, "Bytes received in 256 to 511 byte packets");
9451
9452         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9453             "stat_EtherStatsPktsRx512Octetsto1023Octets",
9454             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
9455             0, "Bytes received in 512 to 1023 byte packets");
9456
9457         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9458             "stat_EtherStatsPktsRx1024Octetsto1522Octets",
9459             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
9460             0, "Bytes received in 1024 t0 1522 byte packets");
9461
9462         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9463             "stat_EtherStatsPktsRx1523Octetsto9022Octets",
9464             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
9465             0, "Bytes received in 1523 to 9022 byte packets");
9466
9467         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9468             "stat_EtherStatsPktsTx64Octets",
9469             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
9470             0, "Bytes sent in 64 byte packets");
9471
9472         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9473             "stat_EtherStatsPktsTx65Octetsto127Octets",
9474             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
9475             0, "Bytes sent in 65 to 127 byte packets");
9476
9477         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9478             "stat_EtherStatsPktsTx128Octetsto255Octets",
9479             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
9480             0, "Bytes sent in 128 to 255 byte packets");
9481
9482         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9483             "stat_EtherStatsPktsTx256Octetsto511Octets",
9484             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
9485             0, "Bytes sent in 256 to 511 byte packets");
9486
9487         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9488             "stat_EtherStatsPktsTx512Octetsto1023Octets",
9489             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
9490             0, "Bytes sent in 512 to 1023 byte packets");
9491
9492         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9493             "stat_EtherStatsPktsTx1024Octetsto1522Octets",
9494             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
9495             0, "Bytes sent in 1024 to 1522 byte packets");
9496
9497         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9498             "stat_EtherStatsPktsTx1523Octetsto9022Octets",
9499             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
9500             0, "Bytes sent in 1523 to 9022 byte packets");
9501
9502         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9503             "stat_XonPauseFramesReceived",
9504             CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
9505             0, "XON pause frames receved");
9506
9507         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9508             "stat_XoffPauseFramesReceived",
9509             CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
9510             0, "XOFF pause frames received");
9511
9512         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9513             "stat_OutXonSent",
9514             CTLFLAG_RD, &sc->stat_OutXonSent,
9515             0, "XON pause frames sent");
9516
9517         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9518             "stat_OutXoffSent",
9519             CTLFLAG_RD, &sc->stat_OutXoffSent,
9520             0, "XOFF pause frames sent");
9521
9522         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9523             "stat_FlowControlDone",
9524             CTLFLAG_RD, &sc->stat_FlowControlDone,
9525             0, "Flow control done");
9526
9527         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9528             "stat_MacControlFramesReceived",
9529             CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
9530             0, "MAC control frames received");
9531
9532         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9533             "stat_XoffStateEntered",
9534             CTLFLAG_RD, &sc->stat_XoffStateEntered,
9535             0, "XOFF state entered");
9536
9537         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9538             "stat_IfInFramesL2FilterDiscards",
9539             CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
9540             0, "Received L2 packets discarded");
9541
9542         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9543             "stat_IfInRuleCheckerDiscards",
9544             CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
9545             0, "Received packets discarded by rule");
9546
9547         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9548             "stat_IfInFTQDiscards",
9549             CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
9550             0, "Received packet FTQ discards");
9551
9552         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9553             "stat_IfInMBUFDiscards",
9554             CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
9555             0, "Received packets discarded due to lack "
9556             "of controller buffer memory");
9557
9558         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9559             "stat_IfInRuleCheckerP4Hit",
9560             CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
9561             0, "Received packets rule checker hits");
9562
9563         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9564             "stat_CatchupInRuleCheckerDiscards",
9565             CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
9566             0, "Received packets discarded in Catchup path");
9567
9568         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9569             "stat_CatchupInFTQDiscards",
9570             CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
9571             0, "Received packets discarded in FTQ in Catchup path");
9572
9573         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9574             "stat_CatchupInMBUFDiscards",
9575             CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
9576             0, "Received packets discarded in controller "
9577             "buffer memory in Catchup path");
9578
9579         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9580             "stat_CatchupInRuleCheckerP4Hit",
9581             CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
9582             0, "Received packets rule checker hits in Catchup path");
9583
9584         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9585             "com_no_buffers",
9586             CTLFLAG_RD, &sc->com_no_buffers,
9587             0, "Valid packets received but no RX buffers available");
9588
9589 #ifdef BCE_DEBUG
9590         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9591             "driver_state", CTLTYPE_INT | CTLFLAG_RW,
9592             (void *)sc, 0,
9593             bce_sysctl_driver_state, "I", "Drive state information");
9594
9595         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9596             "hw_state", CTLTYPE_INT | CTLFLAG_RW,
9597             (void *)sc, 0,
9598             bce_sysctl_hw_state, "I", "Hardware state information");
9599
9600         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9601             "status_block", CTLTYPE_INT | CTLFLAG_RW,
9602             (void *)sc, 0,
9603             bce_sysctl_status_block, "I", "Dump status block");
9604
9605         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9606             "stats_block", CTLTYPE_INT | CTLFLAG_RW,
9607             (void *)sc, 0,
9608             bce_sysctl_stats_block, "I", "Dump statistics block");
9609
9610         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9611             "stats_clear", CTLTYPE_INT | CTLFLAG_RW,
9612             (void *)sc, 0,
9613             bce_sysctl_stats_clear, "I", "Clear statistics block");
9614
9615         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9616             "shmem_state", CTLTYPE_INT | CTLFLAG_RW,
9617             (void *)sc, 0,
9618             bce_sysctl_shmem_state, "I", "Shared memory state information");
9619
9620         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9621             "bc_state", CTLTYPE_INT | CTLFLAG_RW,
9622             (void *)sc, 0,
9623             bce_sysctl_bc_state, "I", "Bootcode state information");
9624
9625         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9626             "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW,
9627             (void *)sc, 0,
9628             bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain");
9629
9630         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9631             "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW,
9632             (void *)sc, 0,
9633             bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain");
9634
9635         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9636             "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
9637             (void *)sc, 0,
9638             bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
9639
9640         if (bce_hdr_split == TRUE) {
9641                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9642                     "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW,
9643                     (void *)sc, 0,
9644                     bce_sysctl_dump_pg_chain, "I", "Dump page chain");
9645         }
9646
9647         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9648             "dump_ctx", CTLTYPE_INT | CTLFLAG_RW,
9649             (void *)sc, 0,
9650             bce_sysctl_dump_ctx, "I", "Dump context memory");
9651
9652         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9653             "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
9654             (void *)sc, 0,
9655             bce_sysctl_breakpoint, "I", "Driver breakpoint");
9656
9657         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9658             "reg_read", CTLTYPE_INT | CTLFLAG_RW,
9659             (void *)sc, 0,
9660             bce_sysctl_reg_read, "I", "Register read");
9661
9662         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9663             "nvram_read", CTLTYPE_INT | CTLFLAG_RW,
9664             (void *)sc, 0,
9665             bce_sysctl_nvram_read, "I", "NVRAM read");
9666
9667         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9668             "phy_read", CTLTYPE_INT | CTLFLAG_RW,
9669             (void *)sc, 0,
9670             bce_sysctl_phy_read, "I", "PHY register read");
9671
9672 #endif
9673
9674         DBEXIT(BCE_VERBOSE_MISC);
9675 }
9676
9677
9678 /****************************************************************************/
9679 /* BCE Debug Routines                                                       */
9680 /****************************************************************************/
9681 #ifdef BCE_DEBUG
9682
9683 /****************************************************************************/
9684 /* Freezes the controller to allow for a cohesive state dump.               */
9685 /*                                                                          */
9686 /* Returns:                                                                 */
9687 /*   Nothing.                                                               */
9688 /****************************************************************************/
9689 static __attribute__ ((noinline)) void
9690 bce_freeze_controller(struct bce_softc *sc)
9691 {
9692         u32 val;
9693         val = REG_RD(sc, BCE_MISC_COMMAND);
9694         val |= BCE_MISC_COMMAND_DISABLE_ALL;
9695         REG_WR(sc, BCE_MISC_COMMAND, val);
9696 }
9697
9698
9699 /****************************************************************************/
9700 /* Unfreezes the controller after a freeze operation.  This may not always  */
9701 /* work and the controller will require a reset!                            */
9702 /*                                                                          */
9703 /* Returns:                                                                 */
9704 /*   Nothing.                                                               */
9705 /****************************************************************************/
9706 static __attribute__ ((noinline)) void
9707 bce_unfreeze_controller(struct bce_softc *sc)
9708 {
9709         u32 val;
9710         val = REG_RD(sc, BCE_MISC_COMMAND);
9711         val |= BCE_MISC_COMMAND_ENABLE_ALL;
9712         REG_WR(sc, BCE_MISC_COMMAND, val);
9713 }
9714
9715
9716 /****************************************************************************/
9717 /* Prints out Ethernet frame information from an mbuf.                      */
9718 /*                                                                          */
9719 /* Partially decode an Ethernet frame to look at some important headers.    */
9720 /*                                                                          */
9721 /* Returns:                                                                 */
9722 /*   Nothing.                                                               */
9723 /****************************************************************************/
9724 static __attribute__ ((noinline)) void
9725 bce_dump_enet(struct bce_softc *sc, struct mbuf *m)
9726 {
9727         struct ether_vlan_header *eh;
9728         u16 etype;
9729         int ehlen;
9730         struct ip *ip;
9731         struct tcphdr *th;
9732         struct udphdr *uh;
9733         struct arphdr *ah;
9734
9735         BCE_PRINTF(
9736             "-----------------------------"
9737             " Frame Decode "
9738             "-----------------------------\n");
9739
9740         eh = mtod(m, struct ether_vlan_header *);
9741
9742         /* Handle VLAN encapsulation if present. */
9743         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
9744                 etype = ntohs(eh->evl_proto);
9745                 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
9746         } else {
9747                 etype = ntohs(eh->evl_encap_proto);
9748                 ehlen = ETHER_HDR_LEN;
9749         }
9750
9751         /* ToDo: Add VLAN output. */
9752         BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n",
9753             eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen);
9754
9755         switch (etype) {
9756         case ETHERTYPE_IP:
9757                 ip = (struct ip *)(m->m_data + ehlen);
9758                 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, "
9759                     "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n",
9760                     ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr),
9761                     ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum));
9762
9763                 switch (ip->ip_p) {
9764                 case IPPROTO_TCP:
9765                         th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9766                         BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = "
9767                             "%d bytes, flags = 0x%b, csum = 0x%04X\n",
9768                             ntohs(th->th_dport), ntohs(th->th_sport),
9769                             (th->th_off << 2), th->th_flags,
9770                             "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST"
9771                             "\02SYN\01FIN", ntohs(th->th_sum));
9772                         break;
9773                 case IPPROTO_UDP:
9774                         uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9775                         BCE_PRINTF("-udp: dest = %d, src = %d, len = %d "
9776                             "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport),
9777                             ntohs(uh->uh_sport), ntohs(uh->uh_ulen),
9778                             ntohs(uh->uh_sum));
9779                         break;
9780                 case IPPROTO_ICMP:
9781                         BCE_PRINTF("icmp:\n");
9782                         break;
9783                 default:
9784                         BCE_PRINTF("----: Other IP protocol.\n");
9785                         }
9786                 break;
9787         case ETHERTYPE_IPV6:
9788                 BCE_PRINTF("ipv6: No decode supported.\n");
9789                 break;
9790         case ETHERTYPE_ARP:
9791                 BCE_PRINTF("-arp: ");
9792                 ah = (struct arphdr *) (m->m_data + ehlen);
9793                 switch (ntohs(ah->ar_op)) {
9794                 case ARPOP_REVREQUEST:
9795                         printf("reverse ARP request\n");
9796                         break;
9797                 case ARPOP_REVREPLY:
9798                         printf("reverse ARP reply\n");
9799                         break;
9800                 case ARPOP_REQUEST:
9801                         printf("ARP request\n");
9802                         break;
9803                 case ARPOP_REPLY:
9804                         printf("ARP reply\n");
9805                         break;
9806                 default:
9807                         printf("other ARP operation\n");
9808                 }
9809                 break;
9810         default:
9811                 BCE_PRINTF("----: Other protocol.\n");
9812         }
9813
9814         BCE_PRINTF(
9815                 "-----------------------------"
9816                 "--------------"
9817                 "-----------------------------\n");
9818 }
9819
9820
9821 /****************************************************************************/
9822 /* Prints out information about an mbuf.                                    */
9823 /*                                                                          */
9824 /* Returns:                                                                 */
9825 /*   Nothing.                                                               */
9826 /****************************************************************************/
9827 static __attribute__ ((noinline)) void
9828 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
9829 {
9830         struct mbuf *mp = m;
9831
9832         if (m == NULL) {
9833                 BCE_PRINTF("mbuf: null pointer\n");
9834                 return;
9835         }
9836
9837         while (mp) {
9838                 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, "
9839                     "m_data = %p\n", mp, mp->m_len, mp->m_flags,
9840                     "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data);
9841
9842                 if (mp->m_flags & M_PKTHDR) {
9843                         BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, "
9844                             "csum_flags = %b\n", mp->m_pkthdr.len,
9845                             mp->m_flags, M_FLAG_PRINTF,
9846                             mp->m_pkthdr.csum_flags, CSUM_BITS);
9847                 }
9848
9849                 if (mp->m_flags & M_EXT) {
9850                         BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ",
9851                             mp->m_ext.ext_buf, mp->m_ext.ext_size);
9852                         switch (mp->m_ext.ext_type) {
9853                         case EXT_CLUSTER:
9854                                 printf("EXT_CLUSTER\n"); break;
9855                         case EXT_SFBUF:
9856                                 printf("EXT_SFBUF\n"); break;
9857                         case EXT_JUMBO9:
9858                                 printf("EXT_JUMBO9\n"); break;
9859                         case EXT_JUMBO16:
9860                                 printf("EXT_JUMBO16\n"); break;
9861                         case EXT_PACKET:
9862                                 printf("EXT_PACKET\n"); break;
9863                         case EXT_MBUF:
9864                                 printf("EXT_MBUF\n"); break;
9865                         case EXT_NET_DRV:
9866                                 printf("EXT_NET_DRV\n"); break;
9867                         case EXT_MOD_TYPE:
9868                                 printf("EXT_MDD_TYPE\n"); break;
9869                         case EXT_DISPOSABLE:
9870                                 printf("EXT_DISPOSABLE\n"); break;
9871                         case EXT_EXTREF:
9872                                 printf("EXT_EXTREF\n"); break;
9873                         default:
9874                                 printf("UNKNOWN\n");
9875                         }
9876                 }
9877
9878                 mp = mp->m_next;
9879         }
9880 }
9881
9882
9883 /****************************************************************************/
9884 /* Prints out the mbufs in the TX mbuf chain.                               */
9885 /*                                                                          */
9886 /* Returns:                                                                 */
9887 /*   Nothing.                                                               */
9888 /****************************************************************************/
9889 static __attribute__ ((noinline)) void
9890 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9891 {
9892         struct mbuf *m;
9893
9894         BCE_PRINTF(
9895                 "----------------------------"
9896                 "  tx mbuf data  "
9897                 "----------------------------\n");
9898
9899         for (int i = 0; i < count; i++) {
9900                 m = sc->tx_mbuf_ptr[chain_prod];
9901                 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod);
9902                 bce_dump_mbuf(sc, m);
9903                 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
9904         }
9905
9906         BCE_PRINTF(
9907                 "----------------------------"
9908                 "----------------"
9909                 "----------------------------\n");
9910 }
9911
9912
9913 /****************************************************************************/
9914 /* Prints out the mbufs in the RX mbuf chain.                               */
9915 /*                                                                          */
9916 /* Returns:                                                                 */
9917 /*   Nothing.                                                               */
9918 /****************************************************************************/
9919 static __attribute__ ((noinline)) void
9920 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9921 {
9922         struct mbuf *m;
9923
9924         BCE_PRINTF(
9925                 "----------------------------"
9926                 "  rx mbuf data  "
9927                 "----------------------------\n");
9928
9929         for (int i = 0; i < count; i++) {
9930                 m = sc->rx_mbuf_ptr[chain_prod];
9931                 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod);
9932                 bce_dump_mbuf(sc, m);
9933                 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
9934         }
9935
9936
9937         BCE_PRINTF(
9938                 "----------------------------"
9939                 "----------------"
9940                 "----------------------------\n");
9941 }
9942
9943
9944 /****************************************************************************/
9945 /* Prints out the mbufs in the mbuf page chain.                             */
9946 /*                                                                          */
9947 /* Returns:                                                                 */
9948 /*   Nothing.                                                               */
9949 /****************************************************************************/
9950 static __attribute__ ((noinline)) void
9951 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9952 {
9953         struct mbuf *m;
9954
9955         BCE_PRINTF(
9956                 "----------------------------"
9957                 "  pg mbuf data  "
9958                 "----------------------------\n");
9959
9960         for (int i = 0; i < count; i++) {
9961                 m = sc->pg_mbuf_ptr[chain_prod];
9962                 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod);
9963                 bce_dump_mbuf(sc, m);
9964                 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod));
9965         }
9966
9967
9968         BCE_PRINTF(
9969                 "----------------------------"
9970                 "----------------"
9971                 "----------------------------\n");
9972 }
9973
9974
9975 /****************************************************************************/
9976 /* Prints out a tx_bd structure.                                            */
9977 /*                                                                          */
9978 /* Returns:                                                                 */
9979 /*   Nothing.                                                               */
9980 /****************************************************************************/
9981 static __attribute__ ((noinline)) void
9982 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
9983 {
9984         int i = 0;
9985
9986         if (idx > MAX_TX_BD_ALLOC)
9987                 /* Index out of range. */
9988                 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
9989         else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
9990                 /* TX Chain page pointer. */
9991                 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
9992                     "pointer\n", idx, txbd->tx_bd_haddr_hi,
9993                     txbd->tx_bd_haddr_lo);
9994         else {
9995                 /* Normal tx_bd entry. */
9996                 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
9997                     "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = "
9998                     "0x%04X (", idx, txbd->tx_bd_haddr_hi,
9999                     txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes,
10000                     txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
10001
10002                 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) {
10003                         if (i>0)
10004                                 printf("|");
10005                         printf("CONN_FAULT");
10006                         i++;
10007                 }
10008
10009                 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) {
10010                         if (i>0)
10011                                 printf("|");
10012                         printf("TCP_UDP_CKSUM");
10013                         i++;
10014                 }
10015
10016                 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) {
10017                         if (i>0)
10018                                 printf("|");
10019                         printf("IP_CKSUM");
10020                         i++;
10021                 }
10022
10023                 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) {
10024                         if (i>0)
10025                                 printf("|");
10026                         printf("VLAN");
10027                         i++;
10028                 }
10029
10030                 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) {
10031                         if (i>0)
10032                                 printf("|");
10033                         printf("COAL_NOW");
10034                         i++;
10035                 }
10036
10037                 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) {
10038                         if (i>0)
10039                                 printf("|");
10040                         printf("DONT_GEN_CRC");
10041                         i++;
10042                 }
10043
10044                 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) {
10045                         if (i>0)
10046                                 printf("|");
10047                         printf("START");
10048                         i++;
10049                 }
10050
10051                 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) {
10052                         if (i>0)
10053                                 printf("|");
10054                         printf("END");
10055                         i++;
10056                 }
10057
10058                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) {
10059                         if (i>0)
10060                                 printf("|");
10061                         printf("LSO");
10062                         i++;
10063                 }
10064
10065                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) {
10066                         if (i>0)
10067                                 printf("|");
10068                         printf("SW_OPTION=%d", ((txbd->tx_bd_flags &
10069                             TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++;
10070                 }
10071
10072                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) {
10073                         if (i>0)
10074                                 printf("|");
10075                         printf("SW_FLAGS");
10076                         i++;
10077                 }
10078
10079                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) {
10080                         if (i>0)
10081                                 printf("|");
10082                         printf("SNAP)");
10083                 } else {
10084                         printf(")\n");
10085                 }
10086         }
10087 }
10088
10089
10090 /****************************************************************************/
10091 /* Prints out a rx_bd structure.                                            */
10092 /*                                                                          */
10093 /* Returns:                                                                 */
10094 /*   Nothing.                                                               */
10095 /****************************************************************************/
10096 static __attribute__ ((noinline)) void
10097 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
10098 {
10099         if (idx > MAX_RX_BD_ALLOC)
10100                 /* Index out of range. */
10101                 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
10102         else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
10103                 /* RX Chain page pointer. */
10104                 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
10105                     "pointer\n", idx, rxbd->rx_bd_haddr_hi,
10106                     rxbd->rx_bd_haddr_lo);
10107         else
10108                 /* Normal rx_bd entry. */
10109                 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = "
10110                     "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi,
10111                     rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len,
10112                     rxbd->rx_bd_flags);
10113 }
10114
10115
10116 /****************************************************************************/
10117 /* Prints out a rx_bd structure in the page chain.                          */
10118 /*                                                                          */
10119 /* Returns:                                                                 */
10120 /*   Nothing.                                                               */
10121 /****************************************************************************/
10122 static __attribute__ ((noinline)) void
10123 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd)
10124 {
10125         if (idx > MAX_PG_BD_ALLOC)
10126                 /* Index out of range. */
10127                 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx);
10128         else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE)
10129                 /* Page Chain page pointer. */
10130                 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n",
10131                         idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo);
10132         else
10133                 /* Normal rx_bd entry. */
10134                 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, "
10135                         "flags = 0x%08X\n", idx,
10136                         pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo,
10137                         pgbd->rx_bd_len, pgbd->rx_bd_flags);
10138 }
10139
10140
10141 /****************************************************************************/
10142 /* Prints out a l2_fhdr structure.                                          */
10143 /*                                                                          */
10144 /* Returns:                                                                 */
10145 /*   Nothing.                                                               */
10146 /****************************************************************************/
10147 static __attribute__ ((noinline)) void
10148 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
10149 {
10150         BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, "
10151                 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, "
10152                 "tcp_udp_xsum = 0x%04X\n", idx,
10153                 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB,
10154                 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
10155                 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
10156 }
10157
10158
10159 /****************************************************************************/
10160 /* Prints out context memory info.  (Only useful for CID 0 to 16.)          */
10161 /*                                                                          */
10162 /* Returns:                                                                 */
10163 /*   Nothing.                                                               */
10164 /****************************************************************************/
10165 static __attribute__ ((noinline)) void
10166 bce_dump_ctx(struct bce_softc *sc, u16 cid)
10167 {
10168         if (cid > TX_CID) {
10169                 BCE_PRINTF(" Unknown CID\n");
10170                 return;
10171         }
10172
10173         BCE_PRINTF(
10174             "----------------------------"
10175             "    CTX Data    "
10176             "----------------------------\n");
10177
10178         BCE_PRINTF("     0x%04X - (CID) Context ID\n", cid);
10179
10180         if (cid == RX_CID) {
10181                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx "
10182                    "producer index\n",
10183                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX));
10184                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host "
10185                     "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
10186                     BCE_L2CTX_RX_HOST_BSEQ));
10187                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n",
10188                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ));
10189                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer "
10190                     "descriptor address\n",
10191                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI));
10192                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer "
10193                     "descriptor address\n",
10194                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO));
10195                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer "
10196                     "index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10197                     BCE_L2CTX_RX_NX_BDIDX));
10198                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page "
10199                     "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10200                     BCE_L2CTX_RX_HOST_PG_BDIDX));
10201                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page "
10202                     "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid),
10203                     BCE_L2CTX_RX_PG_BUF_SIZE));
10204                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page "
10205                     "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
10206                     BCE_L2CTX_RX_NX_PG_BDHADDR_HI));
10207                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page "
10208                     "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
10209                     BCE_L2CTX_RX_NX_PG_BDHADDR_LO));
10210                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page "
10211                     "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10212                     BCE_L2CTX_RX_NX_PG_BDIDX));
10213         } else if (cid == TX_CID) {
10214                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
10215                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n",
10216                             CTX_RD(sc, GET_CID_ADDR(cid),
10217                             BCE_L2CTX_TX_TYPE_XI));
10218                         BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx "
10219                             "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid),
10220                             BCE_L2CTX_TX_CMD_TYPE_XI));
10221                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) "
10222                             "h/w buffer descriptor address\n",
10223                             CTX_RD(sc, GET_CID_ADDR(cid),
10224                             BCE_L2CTX_TX_TBDR_BHADDR_HI_XI));
10225                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) "
10226                             "h/w buffer descriptor address\n",
10227                             CTX_RD(sc, GET_CID_ADDR(cid),
10228                             BCE_L2CTX_TX_TBDR_BHADDR_LO_XI));
10229                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) "
10230                             "host producer index\n",
10231                             CTX_RD(sc, GET_CID_ADDR(cid),
10232                             BCE_L2CTX_TX_HOST_BIDX_XI));
10233                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) "
10234                             "host byte sequence\n",
10235                             CTX_RD(sc, GET_CID_ADDR(cid),
10236                             BCE_L2CTX_TX_HOST_BSEQ_XI));
10237                 } else {
10238                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n",
10239                             CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE));
10240                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n",
10241                             CTX_RD(sc, GET_CID_ADDR(cid),
10242                             BCE_L2CTX_TX_CMD_TYPE));
10243                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) "
10244                             "h/w buffer descriptor address\n",
10245                             CTX_RD(sc, GET_CID_ADDR(cid),
10246                             BCE_L2CTX_TX_TBDR_BHADDR_HI));
10247                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) "
10248                             "h/w buffer descriptor address\n",
10249                             CTX_RD(sc, GET_CID_ADDR(cid),
10250                             BCE_L2CTX_TX_TBDR_BHADDR_LO));
10251                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host "
10252                             "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10253                             BCE_L2CTX_TX_HOST_BIDX));
10254                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte "
10255                             "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
10256                             BCE_L2CTX_TX_HOST_BSEQ));
10257                 }
10258         }
10259
10260         BCE_PRINTF(
10261            "----------------------------"
10262            "    Raw CTX     "
10263            "----------------------------\n");
10264
10265         for (int i = 0x0; i < 0x300; i += 0x10) {
10266                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
10267                    CTX_RD(sc, GET_CID_ADDR(cid), i),
10268                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4),
10269                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8),
10270                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc));
10271         }
10272
10273
10274         BCE_PRINTF(
10275            "----------------------------"
10276            "----------------"
10277            "----------------------------\n");
10278 }
10279
10280
10281 /****************************************************************************/
10282 /* Prints out the FTQ data.                                                 */
10283 /*                                                                          */
10284 /* Returns:                                                                */
10285 /*   Nothing.                                                               */
10286 /****************************************************************************/
10287 static __attribute__ ((noinline)) void
10288 bce_dump_ftqs(struct bce_softc *sc)
10289 {
10290         u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val;
10291
10292         BCE_PRINTF(
10293             "----------------------------"
10294             "    FTQ Data    "
10295             "----------------------------\n");
10296
10297         BCE_PRINTF("   FTQ    Command    Control   Depth_Now  "
10298             "Max_Depth  Valid_Cnt \n");
10299         BCE_PRINTF(" ------- ---------- ---------- ---------- "
10300             "---------- ----------\n");
10301
10302         /* Setup the generic statistic counters for the FTQ valid count. */
10303         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) |
10304             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT  << 16) |
10305             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT   <<  8) |
10306             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT);
10307         REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10308
10309         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT  << 24) |
10310             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT  << 16) |
10311             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT <<  8) |
10312             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT);
10313         REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val);
10314
10315         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT  << 24) |
10316             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT  << 16) |
10317             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT   <<  8) |
10318             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT);
10319         REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val);
10320
10321         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT   << 24) |
10322             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT  << 16) |
10323             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT  <<  8) |
10324             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT);
10325         REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val);
10326
10327         /* Input queue to the Receive Lookup state machine */
10328         cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD);
10329         ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL);
10330         cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22;
10331         max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12;
10332         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
10333         BCE_PRINTF(" RLUP    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10334             cmd, ctl, cur_depth, max_depth, valid_cnt);
10335
10336         /* Input queue to the Receive Processor */
10337         cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD);
10338         ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL);
10339         cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22;
10340         max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12;
10341         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
10342         BCE_PRINTF(" RXP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10343             cmd, ctl, cur_depth, max_depth, valid_cnt);
10344
10345         /* Input queue to the Recevie Processor */
10346         cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD);
10347         ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL);
10348         cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22;
10349         max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12;
10350         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
10351         BCE_PRINTF(" RXPC    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10352             cmd, ctl, cur_depth, max_depth, valid_cnt);
10353
10354         /* Input queue to the Receive Virtual to Physical state machine */
10355         cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD);
10356         ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL);
10357         cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22;
10358         max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12;
10359         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
10360         BCE_PRINTF(" RV2PP   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10361             cmd, ctl, cur_depth, max_depth, valid_cnt);
10362
10363         /* Input queue to the Recevie Virtual to Physical state machine */
10364         cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD);
10365         ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL);
10366         cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22;
10367         max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12;
10368         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4);
10369         BCE_PRINTF(" RV2PM   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10370             cmd, ctl, cur_depth, max_depth, valid_cnt);
10371
10372         /* Input queue to the Receive Virtual to Physical state machine */
10373         cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD);
10374         ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL);
10375         cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22;
10376         max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12;
10377         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5);
10378         BCE_PRINTF(" RV2PT   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10379             cmd, ctl, cur_depth, max_depth, valid_cnt);
10380
10381         /* Input queue to the Receive DMA state machine */
10382         cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD);
10383         ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL);
10384         cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22;
10385         max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12;
10386         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6);
10387         BCE_PRINTF(" RDMA    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10388             cmd, ctl, cur_depth, max_depth, valid_cnt);
10389
10390         /* Input queue to the Transmit Scheduler state machine */
10391         cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD);
10392         ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL);
10393         cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22;
10394         max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12;
10395         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7);
10396         BCE_PRINTF(" TSCH    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10397             cmd, ctl, cur_depth, max_depth, valid_cnt);
10398
10399         /* Input queue to the Transmit Buffer Descriptor state machine */
10400         cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD);
10401         ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL);
10402         cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22;
10403         max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12;
10404         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8);
10405         BCE_PRINTF(" TBDR    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10406             cmd, ctl, cur_depth, max_depth, valid_cnt);
10407
10408         /* Input queue to the Transmit Processor */
10409         cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD);
10410         ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL);
10411         cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22;
10412         max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12;
10413         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9);
10414         BCE_PRINTF(" TXP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10415             cmd, ctl, cur_depth, max_depth, valid_cnt);
10416
10417         /* Input queue to the Transmit DMA state machine */
10418         cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD);
10419         ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL);
10420         cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22;
10421         max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12;
10422         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10);
10423         BCE_PRINTF(" TDMA    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10424             cmd, ctl, cur_depth, max_depth, valid_cnt);
10425
10426         /* Input queue to the Transmit Patch-Up Processor */
10427         cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD);
10428         ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL);
10429         cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22;
10430         max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12;
10431         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11);
10432         BCE_PRINTF(" TPAT    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10433             cmd, ctl, cur_depth, max_depth, valid_cnt);
10434
10435         /* Input queue to the Transmit Assembler state machine */
10436         cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD);
10437         ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL);
10438         cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22;
10439         max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12;
10440         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12);
10441         BCE_PRINTF(" TAS     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10442             cmd, ctl, cur_depth, max_depth, valid_cnt);
10443
10444         /* Input queue to the Completion Processor */
10445         cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD);
10446         ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL);
10447         cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22;
10448         max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12;
10449         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13);
10450         BCE_PRINTF(" COMX    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10451             cmd, ctl, cur_depth, max_depth, valid_cnt);
10452
10453         /* Input queue to the Completion Processor */
10454         cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD);
10455         ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL);
10456         cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22;
10457         max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12;
10458         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14);
10459         BCE_PRINTF(" COMT    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10460             cmd, ctl, cur_depth, max_depth, valid_cnt);
10461
10462         /* Input queue to the Completion Processor */
10463         cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD);
10464         ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL);
10465         cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22;
10466         max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12;
10467         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15);
10468         BCE_PRINTF(" COMX    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10469             cmd, ctl, cur_depth, max_depth, valid_cnt);
10470
10471         /* Setup the generic statistic counters for the FTQ valid count. */
10472         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT  << 16) |
10473             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT  <<  8) |
10474             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT);
10475
10476         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
10477                 val = val |
10478                     (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI <<
10479                      24);
10480         REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10481
10482         /* Input queue to the Management Control Processor */
10483         cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD);
10484         ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL);
10485         cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22;
10486         max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12;
10487         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
10488         BCE_PRINTF(" MCP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10489             cmd, ctl, cur_depth, max_depth, valid_cnt);
10490
10491         /* Input queue to the Command Processor */
10492         cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD);
10493         ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL);
10494         cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22;
10495         max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12;
10496         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
10497         BCE_PRINTF(" CP      0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10498             cmd, ctl, cur_depth, max_depth, valid_cnt);
10499
10500         /* Input queue to the Completion Scheduler state machine */
10501         cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD);
10502         ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL);
10503         cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22;
10504         max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12;
10505         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
10506         BCE_PRINTF(" CS      0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10507             cmd, ctl, cur_depth, max_depth, valid_cnt);
10508
10509         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
10510                 /* Input queue to the RV2P Command Scheduler */
10511                 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD);
10512                 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL);
10513                 cur_depth = (ctl & 0xFFC00000) >> 22;
10514                 max_depth = (ctl & 0x003FF000) >> 12;
10515                 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
10516                 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10517                     cmd, ctl, cur_depth, max_depth, valid_cnt);
10518         }
10519
10520         BCE_PRINTF(
10521             "----------------------------"
10522             "----------------"
10523             "----------------------------\n");
10524 }
10525
10526
10527 /****************************************************************************/
10528 /* Prints out the TX chain.                                                 */
10529 /*                                                                          */
10530 /* Returns:                                                                 */
10531 /*   Nothing.                                                               */
10532 /****************************************************************************/
10533 static __attribute__ ((noinline)) void
10534 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count)
10535 {
10536         struct tx_bd *txbd;
10537
10538         /* First some info about the tx_bd chain structure. */
10539         BCE_PRINTF(
10540             "----------------------------"
10541             "  tx_bd  chain  "
10542             "----------------------------\n");
10543
10544         BCE_PRINTF("page size      = 0x%08X, tx chain pages        = 0x%08X\n",
10545             (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages);
10546         BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n",
10547             (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE);
10548         BCE_PRINTF("total tx_bd    = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC);
10549
10550         BCE_PRINTF(
10551             "----------------------------"
10552             "   tx_bd data   "
10553             "----------------------------\n");
10554
10555         /* Now print out a decoded list of TX buffer descriptors. */
10556         for (int i = 0; i < count; i++) {
10557                 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
10558                 bce_dump_txbd(sc, tx_prod, txbd);
10559                 tx_prod++;
10560         }
10561
10562         BCE_PRINTF(
10563             "----------------------------"
10564             "----------------"
10565             "----------------------------\n");
10566 }
10567
10568
10569 /****************************************************************************/
10570 /* Prints out the RX chain.                                                 */
10571 /*                                                                          */
10572 /* Returns:                                                                 */
10573 /*   Nothing.                                                               */
10574 /****************************************************************************/
10575 static __attribute__ ((noinline)) void
10576 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count)
10577 {
10578         struct rx_bd *rxbd;
10579
10580         /* First some info about the rx_bd chain structure. */
10581         BCE_PRINTF(
10582             "----------------------------"
10583             "  rx_bd  chain  "
10584             "----------------------------\n");
10585
10586         BCE_PRINTF("page size      = 0x%08X, rx chain pages        = 0x%08X\n",
10587             (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages);
10588
10589         BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
10590             (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE);
10591
10592         BCE_PRINTF("total rx_bd    = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC);
10593
10594         BCE_PRINTF(
10595             "----------------------------"
10596             "   rx_bd data   "
10597             "----------------------------\n");
10598
10599         /* Now print out the rx_bd's themselves. */
10600         for (int i = 0; i < count; i++) {
10601                 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
10602                 bce_dump_rxbd(sc, rx_prod, rxbd);
10603                 rx_prod = RX_CHAIN_IDX(rx_prod + 1);
10604         }
10605
10606         BCE_PRINTF(
10607             "----------------------------"
10608             "----------------"
10609             "----------------------------\n");
10610 }
10611
10612
10613 /****************************************************************************/
10614 /* Prints out the page chain.                                               */
10615 /*                                                                          */
10616 /* Returns:                                                                 */
10617 /*   Nothing.                                                               */
10618 /****************************************************************************/
10619 static __attribute__ ((noinline)) void
10620 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count)
10621 {
10622         struct rx_bd *pgbd;
10623
10624         /* First some info about the page chain structure. */
10625         BCE_PRINTF(
10626             "----------------------------"
10627             "   page chain   "
10628             "----------------------------\n");
10629
10630         BCE_PRINTF("page size      = 0x%08X, pg chain pages        = 0x%08X\n",
10631             (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages);
10632
10633         BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
10634             (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE);
10635
10636         BCE_PRINTF("total pg_bd             = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC);
10637
10638         BCE_PRINTF(
10639             "----------------------------"
10640             "   page data    "
10641             "----------------------------\n");
10642
10643         /* Now print out the rx_bd's themselves. */
10644         for (int i = 0; i < count; i++) {
10645                 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)];
10646                 bce_dump_pgbd(sc, pg_prod, pgbd);
10647                 pg_prod = PG_CHAIN_IDX(pg_prod + 1);
10648         }
10649
10650         BCE_PRINTF(
10651             "----------------------------"
10652             "----------------"
10653             "----------------------------\n");
10654 }
10655
10656
10657 #define BCE_PRINT_RX_CONS(arg)                                          \
10658 if (sblk->status_rx_quick_consumer_index##arg)                          \
10659         BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n",      \
10660             sblk->status_rx_quick_consumer_index##arg, (u16)            \
10661             RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg),    \
10662             arg);
10663
10664
10665 #define BCE_PRINT_TX_CONS(arg)                                          \
10666 if (sblk->status_tx_quick_consumer_index##arg)                          \
10667         BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n",      \
10668             sblk->status_tx_quick_consumer_index##arg, (u16)            \
10669             TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg),    \
10670             arg);
10671
10672 /****************************************************************************/
10673 /* Prints out the status block from host memory.                            */
10674 /*                                                                          */
10675 /* Returns:                                                                 */
10676 /*   Nothing.                                                               */
10677 /****************************************************************************/
10678 static __attribute__ ((noinline)) void
10679 bce_dump_status_block(struct bce_softc *sc)
10680 {
10681         struct status_block *sblk;
10682
10683         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
10684
10685         sblk = sc->status_block;
10686
10687         BCE_PRINTF(
10688             "----------------------------"
10689             "  Status Block  "
10690             "----------------------------\n");
10691
10692         /* Theses indices are used for normal L2 drivers. */
10693         BCE_PRINTF("    0x%08X - attn_bits\n",
10694             sblk->status_attn_bits);
10695
10696         BCE_PRINTF("    0x%08X - attn_bits_ack\n",
10697             sblk->status_attn_bits_ack);
10698
10699         BCE_PRINT_RX_CONS(0);
10700         BCE_PRINT_TX_CONS(0)
10701
10702         BCE_PRINTF("        0x%04X - status_idx\n", sblk->status_idx);
10703
10704         /* Theses indices are not used for normal L2 drivers. */
10705         BCE_PRINT_RX_CONS(1);   BCE_PRINT_RX_CONS(2);   BCE_PRINT_RX_CONS(3);
10706         BCE_PRINT_RX_CONS(4);   BCE_PRINT_RX_CONS(5);   BCE_PRINT_RX_CONS(6);
10707         BCE_PRINT_RX_CONS(7);   BCE_PRINT_RX_CONS(8);   BCE_PRINT_RX_CONS(9);
10708         BCE_PRINT_RX_CONS(10);  BCE_PRINT_RX_CONS(11);  BCE_PRINT_RX_CONS(12);
10709         BCE_PRINT_RX_CONS(13);  BCE_PRINT_RX_CONS(14);  BCE_PRINT_RX_CONS(15);
10710
10711         BCE_PRINT_TX_CONS(1);   BCE_PRINT_TX_CONS(2);   BCE_PRINT_TX_CONS(3);
10712
10713         if (sblk->status_completion_producer_index ||
10714             sblk->status_cmd_consumer_index)
10715                 BCE_PRINTF("com_prod  = 0x%08X, cmd_cons      = 0x%08X\n",
10716                     sblk->status_completion_producer_index,
10717                     sblk->status_cmd_consumer_index);
10718
10719         BCE_PRINTF(
10720             "----------------------------"
10721             "----------------"
10722             "----------------------------\n");
10723 }
10724
10725
10726 #define BCE_PRINT_64BIT_STAT(arg)                               \
10727 if (sblk->arg##_lo || sblk->arg##_hi)                           \
10728         BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi,        \
10729             sblk->arg##_lo, #arg);
10730
10731 #define BCE_PRINT_32BIT_STAT(arg)                               \
10732 if (sblk->arg)                                                  \
10733         BCE_PRINTF("         0x%08X : %s\n",                    \
10734             sblk->arg, #arg);
10735
10736 /****************************************************************************/
10737 /* Prints out the statistics block from host memory.                        */
10738 /*                                                                          */
10739 /* Returns:                                                                 */
10740 /*   Nothing.                                                               */
10741 /****************************************************************************/
10742 static __attribute__ ((noinline)) void
10743 bce_dump_stats_block(struct bce_softc *sc)
10744 {
10745         struct statistics_block *sblk;
10746
10747         bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD);
10748
10749         sblk = sc->stats_block;
10750
10751         BCE_PRINTF(
10752             "---------------"
10753             " Stats Block  (All Stats Not Shown Are 0) "
10754             "---------------\n");
10755
10756         BCE_PRINT_64BIT_STAT(stat_IfHCInOctets);
10757         BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets);
10758         BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets);
10759         BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets);
10760         BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts);
10761         BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts);
10762         BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts);
10763         BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts);
10764         BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts);
10765         BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts);
10766         BCE_PRINT_32BIT_STAT(
10767             stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
10768         BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors);
10769         BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors);
10770         BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors);
10771         BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames);
10772         BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames);
10773         BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions);
10774         BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions);
10775         BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions);
10776         BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions);
10777         BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments);
10778         BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers);
10779         BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts);
10780         BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts);
10781         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets);
10782         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets);
10783         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets);
10784         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets);
10785         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets);
10786         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets);
10787         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets);
10788         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets);
10789         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets);
10790         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets);
10791         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets);
10792         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets);
10793         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets);
10794         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets);
10795         BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived);
10796         BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived);
10797         BCE_PRINT_32BIT_STAT(stat_OutXonSent);
10798         BCE_PRINT_32BIT_STAT(stat_OutXoffSent);
10799         BCE_PRINT_32BIT_STAT(stat_FlowControlDone);
10800         BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived);
10801         BCE_PRINT_32BIT_STAT(stat_XoffStateEntered);
10802         BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards);
10803         BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards);
10804         BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards);
10805         BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards);
10806         BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit);
10807         BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards);
10808         BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards);
10809         BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards);
10810         BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit);
10811
10812         BCE_PRINTF(
10813             "----------------------------"
10814             "----------------"
10815             "----------------------------\n");
10816 }
10817
10818
10819 /****************************************************************************/
10820 /* Prints out a summary of the driver state.                                */
10821 /*                                                                          */
10822 /* Returns:                                                                 */
10823 /*   Nothing.                                                               */
10824 /****************************************************************************/
10825 static __attribute__ ((noinline)) void
10826 bce_dump_driver_state(struct bce_softc *sc)
10827 {
10828         u32 val_hi, val_lo;
10829
10830         BCE_PRINTF(
10831             "-----------------------------"
10832             " Driver State "
10833             "-----------------------------\n");
10834
10835         val_hi = BCE_ADDR_HI(sc);
10836         val_lo = BCE_ADDR_LO(sc);
10837         BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual "
10838             "address\n", val_hi, val_lo);
10839
10840         val_hi = BCE_ADDR_HI(sc->bce_vhandle);
10841         val_lo = BCE_ADDR_LO(sc->bce_vhandle);
10842         BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual "
10843             "address\n", val_hi, val_lo);
10844
10845         val_hi = BCE_ADDR_HI(sc->status_block);
10846         val_lo = BCE_ADDR_LO(sc->status_block);
10847         BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block "
10848             "virtual address\n",        val_hi, val_lo);
10849
10850         val_hi = BCE_ADDR_HI(sc->stats_block);
10851         val_lo = BCE_ADDR_LO(sc->stats_block);
10852         BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block "
10853             "virtual address\n", val_hi, val_lo);
10854
10855         val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
10856         val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
10857         BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
10858             "virtual adddress\n", val_hi, val_lo);
10859
10860         val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
10861         val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
10862         BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
10863             "virtual address\n", val_hi, val_lo);
10864
10865         if (bce_hdr_split == TRUE) {
10866                 val_hi = BCE_ADDR_HI(sc->pg_bd_chain);
10867                 val_lo = BCE_ADDR_LO(sc->pg_bd_chain);
10868                 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain "
10869                     "virtual address\n", val_hi, val_lo);
10870         }
10871
10872         val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
10873         val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
10874         BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
10875             "virtual address\n",        val_hi, val_lo);
10876
10877         val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
10878         val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
10879         BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
10880             "virtual address\n", val_hi, val_lo);
10881
10882         if (bce_hdr_split == TRUE) {
10883                 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr);
10884                 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr);
10885                 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain "
10886                     "virtual address\n", val_hi, val_lo);
10887         }
10888
10889         BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) "
10890             "h/w intrs\n",
10891             (long long unsigned int) sc->interrupts_generated);
10892
10893         BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) "
10894             "rx interrupts handled\n",
10895             (long long unsigned int) sc->interrupts_rx);
10896
10897         BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) "
10898             "tx interrupts handled\n",
10899             (long long unsigned int) sc->interrupts_tx);
10900
10901         BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) "
10902             "phy interrupts handled\n",
10903             (long long unsigned int) sc->phy_interrupts);
10904
10905         BCE_PRINTF("         0x%08X - (sc->last_status_idx) "
10906             "status block index\n", sc->last_status_idx);
10907
10908         BCE_PRINTF("     0x%04X(0x%04X) - (sc->tx_prod) tx producer "
10909             "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod));
10910
10911         BCE_PRINTF("     0x%04X(0x%04X) - (sc->tx_cons) tx consumer "
10912             "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons));
10913
10914         BCE_PRINTF("         0x%08X - (sc->tx_prod_bseq) tx producer "
10915             "byte seq index\n", sc->tx_prod_bseq);
10916
10917         BCE_PRINTF("         0x%08X - (sc->debug_tx_mbuf_alloc) tx "
10918             "mbufs allocated\n", sc->debug_tx_mbuf_alloc);
10919
10920         BCE_PRINTF("         0x%08X - (sc->used_tx_bd) used "
10921             "tx_bd's\n", sc->used_tx_bd);
10922
10923         BCE_PRINTF("      0x%04X/0x%04X - (sc->tx_hi_watermark)/"
10924             "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd);
10925
10926         BCE_PRINTF("     0x%04X(0x%04X) - (sc->rx_prod) rx producer "
10927             "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod));
10928
10929         BCE_PRINTF("     0x%04X(0x%04X) - (sc->rx_cons) rx consumer "
10930             "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons));
10931
10932         BCE_PRINTF("         0x%08X - (sc->rx_prod_bseq) rx producer "
10933             "byte seq index\n", sc->rx_prod_bseq);
10934
10935         BCE_PRINTF("      0x%04X/0x%04X - (sc->rx_low_watermark)/"
10936                    "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd);
10937
10938         BCE_PRINTF("         0x%08X - (sc->debug_rx_mbuf_alloc) rx "
10939             "mbufs allocated\n", sc->debug_rx_mbuf_alloc);
10940
10941         BCE_PRINTF("         0x%08X - (sc->free_rx_bd) free "
10942             "rx_bd's\n", sc->free_rx_bd);
10943
10944         if (bce_hdr_split == TRUE) {
10945                 BCE_PRINTF("     0x%04X(0x%04X) - (sc->pg_prod) page producer "
10946                     "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod));
10947
10948                 BCE_PRINTF("     0x%04X(0x%04X) - (sc->pg_cons) page consumer "
10949                     "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons));
10950
10951                 BCE_PRINTF("         0x%08X - (sc->debug_pg_mbuf_alloc) page "
10952                     "mbufs allocated\n", sc->debug_pg_mbuf_alloc);
10953         }
10954
10955         BCE_PRINTF("         0x%08X - (sc->free_pg_bd) free page "
10956             "rx_bd's\n", sc->free_pg_bd);
10957
10958         BCE_PRINTF("      0x%04X/0x%04X - (sc->pg_low_watermark)/"
10959             "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd);
10960
10961         BCE_PRINTF("         0x%08X - (sc->mbuf_alloc_failed_count) "
10962             "mbuf alloc failures\n", sc->mbuf_alloc_failed_count);
10963
10964         BCE_PRINTF("         0x%08X - (sc->bce_flags) "
10965             "bce mac flags\n", sc->bce_flags);
10966
10967         BCE_PRINTF("         0x%08X - (sc->bce_phy_flags) "
10968             "bce phy flags\n", sc->bce_phy_flags);
10969
10970         BCE_PRINTF(
10971             "----------------------------"
10972             "----------------"
10973             "----------------------------\n");
10974 }
10975
10976
10977 /****************************************************************************/
10978 /* Prints out the hardware state through a summary of important register,   */
10979 /* followed by a complete register dump.                                    */
10980 /*                                                                          */
10981 /* Returns:                                                                 */
10982 /*   Nothing.                                                               */
10983 /****************************************************************************/
10984 static __attribute__ ((noinline)) void
10985 bce_dump_hw_state(struct bce_softc *sc)
10986 {
10987         u32 val;
10988
10989         BCE_PRINTF(
10990             "----------------------------"
10991             " Hardware State "
10992             "----------------------------\n");
10993
10994         BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
10995
10996         val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
10997         BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n",
10998             val, BCE_MISC_ENABLE_STATUS_BITS);
10999
11000         val = REG_RD(sc, BCE_DMA_STATUS);
11001         BCE_PRINTF("0x%08X - (0x%06X) dma_status\n",
11002             val, BCE_DMA_STATUS);
11003
11004         val = REG_RD(sc, BCE_CTX_STATUS);
11005         BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n",
11006             val, BCE_CTX_STATUS);
11007
11008         val = REG_RD(sc, BCE_EMAC_STATUS);
11009         BCE_PRINTF("0x%08X - (0x%06X) emac_status\n",
11010             val, BCE_EMAC_STATUS);
11011
11012         val = REG_RD(sc, BCE_RPM_STATUS);
11013         BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n",
11014             val, BCE_RPM_STATUS);
11015
11016         /* ToDo: Create a #define for this constant. */
11017         val = REG_RD(sc, 0x2004);
11018         BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n",
11019             val, 0x2004);
11020
11021         val = REG_RD(sc, BCE_RV2P_STATUS);
11022         BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n",
11023             val, BCE_RV2P_STATUS);
11024
11025         /* ToDo: Create a #define for this constant. */
11026         val = REG_RD(sc, 0x2c04);
11027         BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n",
11028             val, 0x2c04);
11029
11030         val = REG_RD(sc, BCE_TBDR_STATUS);
11031         BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n",
11032             val, BCE_TBDR_STATUS);
11033
11034         val = REG_RD(sc, BCE_TDMA_STATUS);
11035         BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n",
11036             val, BCE_TDMA_STATUS);
11037
11038         val = REG_RD(sc, BCE_HC_STATUS);
11039         BCE_PRINTF("0x%08X - (0x%06X) hc_status\n",
11040             val, BCE_HC_STATUS);
11041
11042         val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
11043         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
11044             val, BCE_TXP_CPU_STATE);
11045
11046         val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11047         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
11048             val, BCE_TPAT_CPU_STATE);
11049
11050         val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11051         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
11052             val, BCE_RXP_CPU_STATE);
11053
11054         val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11055         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
11056             val, BCE_COM_CPU_STATE);
11057
11058         val = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
11059         BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n",
11060             val, BCE_MCP_CPU_STATE);
11061
11062         val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11063         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
11064             val, BCE_CP_CPU_STATE);
11065
11066         BCE_PRINTF(
11067             "----------------------------"
11068             "----------------"
11069             "----------------------------\n");
11070
11071         BCE_PRINTF(
11072             "----------------------------"
11073             " Register  Dump "
11074             "----------------------------\n");
11075
11076         for (int i = 0x400; i < 0x8000; i += 0x10) {
11077                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11078                     i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
11079                     REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
11080         }
11081
11082         BCE_PRINTF(
11083             "----------------------------"
11084             "----------------"
11085             "----------------------------\n");
11086 }
11087
11088
11089 /****************************************************************************/
11090 /* Prints out the contentst of shared memory which is used for host driver  */
11091 /* to bootcode firmware communication.                                      */
11092 /*                                                                          */
11093 /* Returns:                                                                 */
11094 /*   Nothing.                                                               */
11095 /****************************************************************************/
11096 static __attribute__ ((noinline)) void
11097 bce_dump_shmem_state(struct bce_softc *sc)
11098 {
11099         BCE_PRINTF(
11100             "----------------------------"
11101             " Hardware State "
11102             "----------------------------\n");
11103
11104         BCE_PRINTF("0x%08X - Shared memory base address\n",
11105             sc->bce_shmem_base);
11106         BCE_PRINTF("%s - bootcode version\n",
11107             sc->bce_bc_ver);
11108
11109         BCE_PRINTF(
11110             "----------------------------"
11111             "   Shared Mem   "
11112             "----------------------------\n");
11113
11114         for (int i = 0x0; i < 0x200; i += 0x10) {
11115                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11116                     i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4),
11117                     bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC));
11118         }
11119
11120         BCE_PRINTF(
11121             "----------------------------"
11122             "----------------"
11123             "----------------------------\n");
11124 }
11125
11126
11127 /****************************************************************************/
11128 /* Prints out the mailbox queue registers.                                  */
11129 /*                                                                          */
11130 /* Returns:                                                                 */
11131 /*   Nothing.                                                               */
11132 /****************************************************************************/
11133 static __attribute__ ((noinline)) void
11134 bce_dump_mq_regs(struct bce_softc *sc)
11135 {
11136         BCE_PRINTF(
11137             "----------------------------"
11138             "    MQ Regs     "
11139             "----------------------------\n");
11140
11141         BCE_PRINTF(
11142             "----------------------------"
11143             "----------------"
11144             "----------------------------\n");
11145
11146         for (int i = 0x3c00; i < 0x4000; i += 0x10) {
11147                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11148                     i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
11149                     REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
11150         }
11151
11152         BCE_PRINTF(
11153             "----------------------------"
11154             "----------------"
11155             "----------------------------\n");
11156 }
11157
11158
11159 /****************************************************************************/
11160 /* Prints out the bootcode state.                                           */
11161 /*                                                                          */
11162 /* Returns:                                                                 */
11163 /*   Nothing.                                                               */
11164 /****************************************************************************/
11165 static __attribute__ ((noinline)) void
11166 bce_dump_bc_state(struct bce_softc *sc)
11167 {
11168         u32 val;
11169
11170         BCE_PRINTF(
11171             "----------------------------"
11172             " Bootcode State "
11173             "----------------------------\n");
11174
11175         BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
11176
11177         val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE);
11178         BCE_PRINTF("0x%08X - (0x%06X) reset_type\n",
11179             val, BCE_BC_RESET_TYPE);
11180
11181         val = bce_shmem_rd(sc, BCE_BC_STATE);
11182         BCE_PRINTF("0x%08X - (0x%06X) state\n",
11183             val, BCE_BC_STATE);
11184
11185         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
11186         BCE_PRINTF("0x%08X - (0x%06X) condition\n",
11187             val, BCE_BC_STATE_CONDITION);
11188
11189         val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD);
11190         BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n",
11191             val, BCE_BC_STATE_DEBUG_CMD);
11192
11193         BCE_PRINTF(
11194             "----------------------------"
11195             "----------------"
11196             "----------------------------\n");
11197 }
11198
11199
11200 /****************************************************************************/
11201 /* Prints out the TXP processor state.                                      */
11202 /*                                                                          */
11203 /* Returns:                                                                 */
11204 /*   Nothing.                                                               */
11205 /****************************************************************************/
11206 static __attribute__ ((noinline)) void
11207 bce_dump_txp_state(struct bce_softc *sc, int regs)
11208 {
11209         u32 val;
11210         u32 fw_version[3];
11211
11212         BCE_PRINTF(
11213             "----------------------------"
11214             "   TXP  State   "
11215             "----------------------------\n");
11216
11217         for (int i = 0; i < 3; i++)
11218                 fw_version[i] = htonl(REG_RD_IND(sc,
11219                     (BCE_TXP_SCRATCH + 0x10 + i * 4)));
11220         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11221
11222         val = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
11223         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n",
11224             val, BCE_TXP_CPU_MODE);
11225
11226         val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
11227         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
11228             val, BCE_TXP_CPU_STATE);
11229
11230         val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
11231         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n",
11232             val, BCE_TXP_CPU_EVENT_MASK);
11233
11234         if (regs) {
11235                 BCE_PRINTF(
11236                     "----------------------------"
11237                     " Register  Dump "
11238                     "----------------------------\n");
11239
11240                 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
11241                         /* Skip the big blank spaces */
11242                         if (i < 0x454000 && i > 0x5ffff)
11243                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11244                                     "0x%08X 0x%08X\n", i,
11245                                     REG_RD_IND(sc, i),
11246                                     REG_RD_IND(sc, i + 0x4),
11247                                     REG_RD_IND(sc, i + 0x8),
11248                                     REG_RD_IND(sc, i + 0xC));
11249                 }
11250         }
11251
11252         BCE_PRINTF(
11253             "----------------------------"
11254             "----------------"
11255             "----------------------------\n");
11256 }
11257
11258
11259 /****************************************************************************/
11260 /* Prints out the RXP processor state.                                      */
11261 /*                                                                          */
11262 /* Returns:                                                                 */
11263 /*   Nothing.                                                               */
11264 /****************************************************************************/
11265 static __attribute__ ((noinline)) void
11266 bce_dump_rxp_state(struct bce_softc *sc, int regs)
11267 {
11268         u32 val;
11269         u32 fw_version[3];
11270
11271         BCE_PRINTF(
11272             "----------------------------"
11273             "   RXP  State   "
11274             "----------------------------\n");
11275
11276         for (int i = 0; i < 3; i++)
11277                 fw_version[i] = htonl(REG_RD_IND(sc,
11278                     (BCE_RXP_SCRATCH + 0x10 + i * 4)));
11279
11280         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11281
11282         val = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
11283         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n",
11284             val, BCE_RXP_CPU_MODE);
11285
11286         val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11287         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
11288             val, BCE_RXP_CPU_STATE);
11289
11290         val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
11291         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n",
11292             val, BCE_RXP_CPU_EVENT_MASK);
11293
11294         if (regs) {
11295                 BCE_PRINTF(
11296                     "----------------------------"
11297                     " Register  Dump "
11298                     "----------------------------\n");
11299
11300                 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
11301                         /* Skip the big blank sapces */
11302                         if (i < 0xc5400 && i > 0xdffff)
11303                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11304                                     "0x%08X 0x%08X\n", i,
11305                                     REG_RD_IND(sc, i),
11306                                     REG_RD_IND(sc, i + 0x4),
11307                                     REG_RD_IND(sc, i + 0x8),
11308                                     REG_RD_IND(sc, i + 0xC));
11309                 }
11310         }
11311
11312         BCE_PRINTF(
11313             "----------------------------"
11314             "----------------"
11315             "----------------------------\n");
11316 }
11317
11318
11319 /****************************************************************************/
11320 /* Prints out the TPAT processor state.                                     */
11321 /*                                                                          */
11322 /* Returns:                                                                 */
11323 /*   Nothing.                                                               */
11324 /****************************************************************************/
11325 static __attribute__ ((noinline)) void
11326 bce_dump_tpat_state(struct bce_softc *sc, int regs)
11327 {
11328         u32 val;
11329         u32 fw_version[3];
11330
11331         BCE_PRINTF(
11332             "----------------------------"
11333             "   TPAT State   "
11334             "----------------------------\n");
11335
11336         for (int i = 0; i < 3; i++)
11337                 fw_version[i] = htonl(REG_RD_IND(sc,
11338                     (BCE_TPAT_SCRATCH + 0x410 + i * 4)));
11339
11340         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11341
11342         val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
11343         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n",
11344             val, BCE_TPAT_CPU_MODE);
11345
11346         val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11347         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
11348             val, BCE_TPAT_CPU_STATE);
11349
11350         val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
11351         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n",
11352             val, BCE_TPAT_CPU_EVENT_MASK);
11353
11354         if (regs) {
11355                 BCE_PRINTF(
11356                     "----------------------------"
11357                     " Register  Dump "
11358                     "----------------------------\n");
11359
11360                 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
11361                         /* Skip the big blank spaces */
11362                         if (i < 0x854000 && i > 0x9ffff)
11363                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11364                                     "0x%08X 0x%08X\n", i,
11365                                     REG_RD_IND(sc, i),
11366                                     REG_RD_IND(sc, i + 0x4),
11367                                     REG_RD_IND(sc, i + 0x8),
11368                                     REG_RD_IND(sc, i + 0xC));
11369                 }
11370         }
11371
11372         BCE_PRINTF(
11373                 "----------------------------"
11374                 "----------------"
11375                 "----------------------------\n");
11376 }
11377
11378
11379 /****************************************************************************/
11380 /* Prints out the Command Procesor (CP) state.                              */
11381 /*                                                                          */
11382 /* Returns:                                                                 */
11383 /*   Nothing.                                                               */
11384 /****************************************************************************/
11385 static __attribute__ ((noinline)) void
11386 bce_dump_cp_state(struct bce_softc *sc, int regs)
11387 {
11388         u32 val;
11389         u32 fw_version[3];
11390
11391         BCE_PRINTF(
11392             "----------------------------"
11393             "    CP State    "
11394             "----------------------------\n");
11395
11396         for (int i = 0; i < 3; i++)
11397                 fw_version[i] = htonl(REG_RD_IND(sc,
11398                     (BCE_CP_SCRATCH + 0x10 + i * 4)));
11399
11400         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11401
11402         val = REG_RD_IND(sc, BCE_CP_CPU_MODE);
11403         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n",
11404             val, BCE_CP_CPU_MODE);
11405
11406         val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11407         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
11408             val, BCE_CP_CPU_STATE);
11409
11410         val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK);
11411         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val,
11412             BCE_CP_CPU_EVENT_MASK);
11413
11414         if (regs) {
11415                 BCE_PRINTF(
11416                     "----------------------------"
11417                     " Register  Dump "
11418                     "----------------------------\n");
11419
11420                 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) {
11421                         /* Skip the big blank spaces */
11422                         if (i < 0x185400 && i > 0x19ffff)
11423                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11424                                     "0x%08X 0x%08X\n", i,
11425                                     REG_RD_IND(sc, i),
11426                                     REG_RD_IND(sc, i + 0x4),
11427                                     REG_RD_IND(sc, i + 0x8),
11428                                     REG_RD_IND(sc, i + 0xC));
11429                 }
11430         }
11431
11432         BCE_PRINTF(
11433             "----------------------------"
11434             "----------------"
11435             "----------------------------\n");
11436 }
11437
11438
11439 /****************************************************************************/
11440 /* Prints out the Completion Procesor (COM) state.                          */
11441 /*                                                                          */
11442 /* Returns:                                                                 */
11443 /*   Nothing.                                                               */
11444 /****************************************************************************/
11445 static __attribute__ ((noinline)) void
11446 bce_dump_com_state(struct bce_softc *sc, int regs)
11447 {
11448         u32 val;
11449         u32 fw_version[4];
11450
11451         BCE_PRINTF(
11452             "----------------------------"
11453             "   COM State    "
11454             "----------------------------\n");
11455
11456         for (int i = 0; i < 3; i++)
11457                 fw_version[i] = htonl(REG_RD_IND(sc,
11458                     (BCE_COM_SCRATCH + 0x10 + i * 4)));
11459
11460         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11461
11462         val = REG_RD_IND(sc, BCE_COM_CPU_MODE);
11463         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n",
11464             val, BCE_COM_CPU_MODE);
11465
11466         val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11467         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
11468             val, BCE_COM_CPU_STATE);
11469
11470         val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK);
11471         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val,
11472             BCE_COM_CPU_EVENT_MASK);
11473
11474         if (regs) {
11475                 BCE_PRINTF(
11476                     "----------------------------"
11477                     " Register  Dump "
11478                     "----------------------------\n");
11479
11480                 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) {
11481                         BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11482                             "0x%08X 0x%08X\n", i,
11483                             REG_RD_IND(sc, i),
11484                             REG_RD_IND(sc, i + 0x4),
11485                             REG_RD_IND(sc, i + 0x8),
11486                             REG_RD_IND(sc, i + 0xC));
11487                 }
11488         }
11489
11490         BCE_PRINTF(
11491                 "----------------------------"
11492                 "----------------"
11493                 "----------------------------\n");
11494 }
11495
11496
11497 /****************************************************************************/
11498 /* Prints out the Receive Virtual 2 Physical (RV2P) state.                  */
11499 /*                                                                          */
11500 /* Returns:                                                                 */
11501 /*   Nothing.                                                               */
11502 /****************************************************************************/
11503 static __attribute__ ((noinline)) void
11504 bce_dump_rv2p_state(struct bce_softc *sc)
11505 {
11506         u32 val, pc1, pc2, fw_ver_high, fw_ver_low;
11507
11508         BCE_PRINTF(
11509             "----------------------------"
11510             "   RV2P State   "
11511             "----------------------------\n");
11512
11513         /* Stall the RV2P processors. */
11514         val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11515         val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2;
11516         REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
11517
11518         /* Read the firmware version. */
11519         val = 0x00000001;
11520         REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
11521         fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
11522         fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
11523             BCE_RV2P_INSTR_HIGH_HIGH;
11524         BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n",
11525             fw_ver_high, fw_ver_low);
11526
11527         val = 0x00000001;
11528         REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
11529         fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
11530         fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
11531             BCE_RV2P_INSTR_HIGH_HIGH;
11532         BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n",
11533             fw_ver_high, fw_ver_low);
11534
11535         /* Resume the RV2P processors. */
11536         val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11537         val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2);
11538         REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
11539
11540         /* Fetch the program counter value. */
11541         val = 0x68007800;
11542         REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
11543         val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11544         pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
11545         pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
11546         BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1);
11547         BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2);
11548
11549         /* Fetch the program counter value again to see if it is advancing. */
11550         val = 0x68007800;
11551         REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
11552         val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11553         pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
11554         pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
11555         BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1);
11556         BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2);
11557
11558         BCE_PRINTF(
11559             "----------------------------"
11560             "----------------"
11561             "----------------------------\n");
11562 }
11563
11564
11565 /****************************************************************************/
11566 /* Prints out the driver state and then enters the debugger.                */
11567 /*                                                                          */
11568 /* Returns:                                                                 */
11569 /*   Nothing.                                                               */
11570 /****************************************************************************/
11571 static __attribute__ ((noinline)) void
11572 bce_breakpoint(struct bce_softc *sc)
11573 {
11574
11575         /*
11576          * Unreachable code to silence compiler warnings
11577          * about unused functions.
11578          */
11579         if (0) {
11580                 bce_freeze_controller(sc);
11581                 bce_unfreeze_controller(sc);
11582                 bce_dump_enet(sc, NULL);
11583                 bce_dump_txbd(sc, 0, NULL);
11584                 bce_dump_rxbd(sc, 0, NULL);
11585                 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC);
11586                 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC);
11587                 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC);
11588                 bce_dump_l2fhdr(sc, 0, NULL);
11589                 bce_dump_ctx(sc, RX_CID);
11590                 bce_dump_ftqs(sc);
11591                 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC);
11592                 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC);
11593                 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC);
11594                 bce_dump_status_block(sc);
11595                 bce_dump_stats_block(sc);
11596                 bce_dump_driver_state(sc);
11597                 bce_dump_hw_state(sc);
11598                 bce_dump_bc_state(sc);
11599                 bce_dump_txp_state(sc, 0);
11600                 bce_dump_rxp_state(sc, 0);
11601                 bce_dump_tpat_state(sc, 0);
11602                 bce_dump_cp_state(sc, 0);
11603                 bce_dump_com_state(sc, 0);
11604                 bce_dump_rv2p_state(sc);
11605                 bce_dump_pgbd(sc, 0, NULL);
11606         }
11607
11608         bce_dump_status_block(sc);
11609         bce_dump_driver_state(sc);
11610
11611         /* Call the debugger. */
11612         breakpoint();
11613 }
11614 #endif