sys/dev/bce/if_bce.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause
   3  *
   4  * Copyright (c) 2006-2014 QLogic Corporation
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  20  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  26  * THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 /*
  33  * The following controllers are supported by this driver:
  34  *   BCM5706C A2, A3
  35  *   BCM5706S A2, A3
  36  *   BCM5708C B1, B2
  37  *   BCM5708S B1, B2
  38  *   BCM5709C A1, C0
  39  *   BCM5709S A1, C0
  40  *   BCM5716C C0
  41  *   BCM5716S C0
  42  *
  43  * The following controllers are not supported by this driver:
  44  *   BCM5706C A0, A1 (pre-production)
  45  *   BCM5706S A0, A1 (pre-production)
  46  *   BCM5708C A0, B0 (pre-production)
  47  *   BCM5708S A0, B0 (pre-production)
  48  *   BCM5709C A0  B0, B1, B2 (pre-production)
  49  *   BCM5709S A0, B0, B1, B2 (pre-production)
  50  */
  51
  52 #include "opt_bce.h"
  53
  54 #include <sys/param.h>
  55 #include <sys/endian.h>
  56 #include <sys/systm.h>
  57 #include <sys/sockio.h>
  58 #include <sys/lock.h>
  59 #include <sys/mbuf.h>
  60 #include <sys/malloc.h>
  61 #include <sys/mutex.h>
  62 #include <sys/kernel.h>
  63 #include <sys/module.h>
  64 #include <sys/socket.h>
  65 #include <sys/sysctl.h>
  66 #include <sys/queue.h>
  67
  68 #include <net/bpf.h>
  69 #include <net/ethernet.h>
  70 #include <net/if.h>
  71 #include <net/if_var.h>
  72 #include <net/if_arp.h>
  73 #include <net/if_dl.h>
  74 #include <net/if_media.h>
  75
  76 #include <net/if_types.h>
  77 #include <net/if_vlan_var.h>
  78
  79 #include <netinet/in_systm.h>
  80 #include <netinet/in.h>
  81 #include <netinet/if_ether.h>
  82 #include <netinet/ip.h>
  83 #include <netinet/ip6.h>
  84 #include <netinet/tcp.h>
  85 #include <netinet/udp.h>
  86
  87 #include <machine/bus.h>
  88 #include <machine/resource.h>
  89 #include <sys/bus.h>
  90 #include <sys/rman.h>
  91
  92 #include <dev/mii/mii.h>
  93 #include <dev/mii/miivar.h>
  94 #include "miidevs.h"
  95 #include <dev/mii/brgphyreg.h>
  96
  97 #include <dev/pci/pcireg.h>
  98 #include <dev/pci/pcivar.h>
  99
 100 #include "miibus_if.h"
 101
 102 #include <dev/bce/if_bcereg.h>
 103 #include <dev/bce/if_bcefw.h>
 104
 105 /****************************************************************************/
 106 /* BCE Debug Options                                                        */
 107 /****************************************************************************/
 108 #ifdef BCE_DEBUG
 109         u32 bce_debug = BCE_WARN;
 110
 111         /*          0 = Never              */
 112         /*          1 = 1 in 2,147,483,648 */
 113         /*        256 = 1 in     8,388,608 */
 114         /*       2048 = 1 in     1,048,576 */
 115         /*      65536 = 1 in        32,768 */
 116         /*    1048576 = 1 in         2,048 */
 117         /*  268435456 = 1 in             8 */
 118         /*  536870912 = 1 in             4 */
 119         /* 1073741824 = 1 in             2 */
 120
 121         /* Controls how often the l2_fhdr frame error check will fail. */
 122         int l2fhdr_error_sim_control = 0;
 123
 124         /* Controls how often the unexpected attention check will fail. */
 125         int unexpected_attention_sim_control = 0;
 126
 127         /* Controls how often to simulate an mbuf allocation failure. */
 128         int mbuf_alloc_failed_sim_control = 0;
 129
 130         /* Controls how often to simulate a DMA mapping failure. */
 131         int dma_map_addr_failed_sim_control = 0;
 132
 133         /* Controls how often to simulate a bootcode failure. */
 134         int bootcode_running_failure_sim_control = 0;
 135 #endif
 136
 137 /****************************************************************************/
 138 /* PCI Device ID Table                                                      */
 139 /*                                                                          */
 140 /* Used by bce_probe() to identify the devices supported by this driver.    */
 141 /****************************************************************************/
 142 #define BCE_DEVDESC_MAX         64
 143
 144 static const struct bce_type bce_devs[] = {
 145         /* BCM5706C Controllers and OEM boards. */
 146         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
 147                 "HP NC370T Multifunction Gigabit Server Adapter" },
 148         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
 149                 "HP NC370i Multifunction Gigabit Server Adapter" },
 150         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
 151                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
 152         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
 153                 "HP NC371i Multifunction Gigabit Server Adapter" },
 154         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 155                 "QLogic NetXtreme II BCM5706 1000Base-T" },
 156
 157         /* BCM5706S controllers and OEM boards. */
 158         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 159                 "HP NC370F Multifunction Gigabit Server Adapter" },
 160         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 161                 "QLogic NetXtreme II BCM5706 1000Base-SX" },
 162
 163         /* BCM5708C controllers and OEM boards. */
 164         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
 165                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
 166         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
 167                 "HP NC373i Multifunction Gigabit Server Adapter" },
 168         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
 169                 "HP NC374m PCIe Multifunction Adapter" },
 170         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 171                 "QLogic NetXtreme II BCM5708 1000Base-T" },
 172
 173         /* BCM5708S controllers and OEM boards. */
 174         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
 175                 "HP NC373m Multifunction Gigabit Server Adapter" },
 176         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
 177                 "HP NC373i Multifunction Gigabit Server Adapter" },
 178         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
 179                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
 180         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 181                 "QLogic NetXtreme II BCM5708 1000Base-SX" },
 182
 183         /* BCM5709C controllers and OEM boards. */
 184         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
 185                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 186         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
 187                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
 188         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
 189                 "QLogic NetXtreme II BCM5709 1000Base-T" },
 190
 191         /* BCM5709S controllers and OEM boards. */
 192         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
 193                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
 194         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
 195                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 196         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
 197                 "QLogic NetXtreme II BCM5709 1000Base-SX" },
 198
 199         /* BCM5716 controllers and OEM boards. */
 200         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,  PCI_ANY_ID,  PCI_ANY_ID,
 201                 "QLogic NetXtreme II BCM5716 1000Base-T" },
 202
 203         { 0, 0, 0, 0, NULL }
 204 };
 205
 206
 207 /****************************************************************************/
 208 /* Supported Flash NVRAM device data.                                       */
 209 /****************************************************************************/
 210 static const struct flash_spec flash_table[] =
 211 {
 212 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
 213 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
 214
 215         /* Slow EEPROM */
 216         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 217          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 218          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 219          "EEPROM - slow"},
 220         /* Expansion entry 0001 */
 221         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 222          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 223          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 224          "Entry 0001"},
 225         /* Saifun SA25F010 (non-buffered flash) */
 226         /* strap, cfg1, & write1 need updates */
 227         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 228          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 229          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 230          "Non-buffered flash (128kB)"},
 231         /* Saifun SA25F020 (non-buffered flash) */
 232         /* strap, cfg1, & write1 need updates */
 233         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 234          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 235          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 236          "Non-buffered flash (256kB)"},
 237         /* Expansion entry 0100 */
 238         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 239          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 240          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 241          "Entry 0100"},
 242         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 243         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 244          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 245          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 246          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 247         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 248         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 249          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 250          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 251          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 252         /* Saifun SA25F005 (non-buffered flash) */
 253         /* strap, cfg1, & write1 need updates */
 254         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 255          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 256          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 257          "Non-buffered flash (64kB)"},
 258         /* Fast EEPROM */
 259         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 260          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 261          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 262          "EEPROM - fast"},
 263         /* Expansion entry 1001 */
 264         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 265          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 266          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 267          "Entry 1001"},
 268         /* Expansion entry 1010 */
 269         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 270          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 271          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 272          "Entry 1010"},
 273         /* ATMEL AT45DB011B (buffered flash) */
 274         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 275          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 276          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 277          "Buffered flash (128kB)"},
 278         /* Expansion entry 1100 */
 279         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 280          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 281          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 282          "Entry 1100"},
 283         /* Expansion entry 1101 */
 284         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 285          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 286          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 287          "Entry 1101"},
 288         /* Ateml Expansion entry 1110 */
 289         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 290          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 291          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 292          "Entry 1110 (Atmel)"},
 293         /* ATMEL AT45DB021B (buffered flash) */
 294         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 295          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 296          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 297          "Buffered flash (256kB)"},
 298 };
 299
 300 /*
 301  * The BCM5709 controllers transparently handle the
 302  * differences between Atmel 264 byte pages and all
 303  * flash devices which use 256 byte pages, so no
 304  * logical-to-physical mapping is required in the
 305  * driver.
 306  */
 307 static const struct flash_spec flash_5709 = {
 308         .flags          = BCE_NV_BUFFERED,
 309         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 310         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 311         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 312         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
 313         .name           = "5709/5716 buffered flash (256kB)",
 314 };
 315
 316
 317 /****************************************************************************/
 318 /* FreeBSD device entry points.                                             */
 319 /****************************************************************************/
 320 static int  bce_probe                   (device_t);
 321 static int  bce_attach                  (device_t);
 322 static int  bce_detach                  (device_t);
 323 static int  bce_shutdown                (device_t);
 324
 325
 326 /****************************************************************************/
 327 /* BCE Debug Data Structure Dump Routines                                   */
 328 /****************************************************************************/
 329 #ifdef BCE_DEBUG
 330 static u32  bce_reg_rd                          (struct bce_softc *, u32);
 331 static void bce_reg_wr                          (struct bce_softc *, u32, u32);
 332 static void bce_reg_wr16                        (struct bce_softc *, u32, u16);
 333 static u32  bce_ctx_rd                          (struct bce_softc *, u32, u32);
 334 static void bce_dump_enet                       (struct bce_softc *, struct mbuf *);
 335 static void bce_dump_mbuf                       (struct bce_softc *, struct mbuf *);
 336 static void bce_dump_tx_mbuf_chain      (struct bce_softc *, u16, int);
 337 static void bce_dump_rx_mbuf_chain      (struct bce_softc *, u16, int);
 338 static void bce_dump_pg_mbuf_chain      (struct bce_softc *, u16, int);
 339 static void bce_dump_txbd                       (struct bce_softc *,
 340     int, struct tx_bd *);
 341 static void bce_dump_rxbd                       (struct bce_softc *,
 342     int, struct rx_bd *);
 343 static void bce_dump_pgbd                       (struct bce_softc *,
 344     int, struct rx_bd *);
 345 static void bce_dump_l2fhdr             (struct bce_softc *,
 346     int, struct l2_fhdr *);
 347 static void bce_dump_ctx                        (struct bce_softc *, u16);
 348 static void bce_dump_ftqs                       (struct bce_softc *);
 349 static void bce_dump_tx_chain           (struct bce_softc *, u16, int);
 350 static void bce_dump_rx_bd_chain        (struct bce_softc *, u16, int);
 351 static void bce_dump_pg_chain           (struct bce_softc *, u16, int);
 352 static void bce_dump_status_block       (struct bce_softc *);
 353 static void bce_dump_stats_block        (struct bce_softc *);
 354 static void bce_dump_driver_state       (struct bce_softc *);
 355 static void bce_dump_hw_state           (struct bce_softc *);
 356 static void bce_dump_shmem_state        (struct bce_softc *);
 357 static void bce_dump_mq_regs            (struct bce_softc *);
 358 static void bce_dump_bc_state           (struct bce_softc *);
 359 static void bce_dump_txp_state          (struct bce_softc *, int);
 360 static void bce_dump_rxp_state          (struct bce_softc *, int);
 361 static void bce_dump_tpat_state (struct bce_softc *, int);
 362 static void bce_dump_cp_state           (struct bce_softc *, int);
 363 static void bce_dump_com_state          (struct bce_softc *, int);
 364 static void bce_dump_rv2p_state (struct bce_softc *);
 365 static void bce_breakpoint                      (struct bce_softc *);
 366 #endif /*BCE_DEBUG */
 367
 368
 369 /****************************************************************************/
 370 /* BCE Register/Memory Access Routines                                      */
 371 /****************************************************************************/
 372 static u32  bce_reg_rd_ind              (struct bce_softc *, u32);
 373 static void bce_reg_wr_ind              (struct bce_softc *, u32, u32);
 374 static void bce_shmem_wr                (struct bce_softc *, u32, u32);
 375 static u32  bce_shmem_rd                (struct bce_softc *, u32);
 376 static void bce_ctx_wr                  (struct bce_softc *, u32, u32, u32);
 377 static int  bce_miibus_read_reg         (device_t, int, int);
 378 static int  bce_miibus_write_reg        (device_t, int, int, int);
 379 static void bce_miibus_statchg          (device_t);
 380
 381 #ifdef BCE_DEBUG
 382 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS);
 383 #ifdef BCE_NVRAM_WRITE_SUPPORT
 384 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS);
 385 #endif
 386 #endif
 387
 388 /****************************************************************************/
 389 /* BCE NVRAM Access Routines                                                */
 390 /****************************************************************************/
 391 static int  bce_acquire_nvram_lock      (struct bce_softc *);
 392 static int  bce_release_nvram_lock      (struct bce_softc *);
 393 static void bce_enable_nvram_access(struct bce_softc *);
 394 static void bce_disable_nvram_access(struct bce_softc *);
 395 static int  bce_nvram_read_dword        (struct bce_softc *, u32, u8 *, u32);
 396 static int  bce_init_nvram                      (struct bce_softc *);
 397 static int  bce_nvram_read                      (struct bce_softc *, u32, u8 *, int);
 398 static int  bce_nvram_test                      (struct bce_softc *);
 399 #ifdef BCE_NVRAM_WRITE_SUPPORT
 400 static int  bce_enable_nvram_write      (struct bce_softc *);
 401 static void bce_disable_nvram_write(struct bce_softc *);
 402 static int  bce_nvram_erase_page        (struct bce_softc *, u32);
 403 static int  bce_nvram_write_dword       (struct bce_softc *, u32, u8 *, u32);
 404 static int  bce_nvram_write             (struct bce_softc *, u32, u8 *, int);
 405 #endif
 406
 407 /****************************************************************************/
 408 /*                                                                          */
 409 /****************************************************************************/
 410 static void bce_get_rx_buffer_sizes(struct bce_softc *, int);
 411 static void bce_get_media                       (struct bce_softc *);
 412 static void bce_init_media                      (struct bce_softc *);
 413 static u32 bce_get_rphy_link            (struct bce_softc *);
 414 static void bce_dma_map_addr            (void *, bus_dma_segment_t *, int, int);
 415 static int  bce_dma_alloc                       (device_t);
 416 static void bce_dma_free                        (struct bce_softc *);
 417 static void bce_release_resources       (struct bce_softc *);
 418
 419 /****************************************************************************/
 420 /* BCE Firmware Synchronization and Load                                    */
 421 /****************************************************************************/
 422 static void bce_fw_cap_init                     (struct bce_softc *);
 423 static int  bce_fw_sync                 (struct bce_softc *, u32);
 424 static void bce_load_rv2p_fw            (struct bce_softc *, const u32 *, u32,
 425     u32);
 426 static void bce_load_cpu_fw             (struct bce_softc *,
 427     struct cpu_reg *, struct fw_info *);
 428 static void bce_start_cpu                       (struct bce_softc *, struct cpu_reg *);
 429 static void bce_halt_cpu                        (struct bce_softc *, struct cpu_reg *);
 430 static void bce_start_rxp_cpu           (struct bce_softc *);
 431 static void bce_init_rxp_cpu            (struct bce_softc *);
 432 static void bce_init_txp_cpu            (struct bce_softc *);
 433 static void bce_init_tpat_cpu           (struct bce_softc *);
 434 static void bce_init_cp_cpu             (struct bce_softc *);
 435 static void bce_init_com_cpu            (struct bce_softc *);
 436 static void bce_init_cpus                       (struct bce_softc *);
 437
 438 static void bce_print_adapter_info      (struct bce_softc *);
 439 static void bce_probe_pci_caps          (device_t, struct bce_softc *);
 440 static void bce_stop                            (struct bce_softc *);
 441 static int  bce_reset                           (struct bce_softc *, u32);
 442 static int  bce_chipinit                        (struct bce_softc *);
 443 static int  bce_blockinit                       (struct bce_softc *);
 444
 445 static int  bce_init_tx_chain           (struct bce_softc *);
 446 static void bce_free_tx_chain           (struct bce_softc *);
 447
 448 static int  bce_get_rx_buf              (struct bce_softc *, u16, u16, u32 *);
 449 static int  bce_init_rx_chain           (struct bce_softc *);
 450 static void bce_fill_rx_chain           (struct bce_softc *);
 451 static void bce_free_rx_chain           (struct bce_softc *);
 452
 453 static int  bce_get_pg_buf              (struct bce_softc *, u16, u16);
 454 static int  bce_init_pg_chain           (struct bce_softc *);
 455 static void bce_fill_pg_chain           (struct bce_softc *);
 456 static void bce_free_pg_chain           (struct bce_softc *);
 457
 458 static struct mbuf *bce_tso_setup       (struct bce_softc *,
 459     struct mbuf **, u16 *);
 460 static int  bce_tx_encap                        (struct bce_softc *, struct mbuf **);
 461 static void bce_start_locked            (struct ifnet *);
 462 static void bce_start                   (struct ifnet *);
 463 static int  bce_ioctl                   (struct ifnet *, u_long, caddr_t);
 464 static uint64_t bce_get_counter         (struct ifnet *, ift_counter);
 465 static void bce_watchdog                (struct bce_softc *);
 466 static int  bce_ifmedia_upd             (struct ifnet *);
 467 static int  bce_ifmedia_upd_locked      (struct ifnet *);
 468 static void bce_ifmedia_sts             (struct ifnet *, struct ifmediareq *);
 469 static void bce_ifmedia_sts_rphy        (struct bce_softc *, struct ifmediareq *);
 470 static void bce_init_locked             (struct bce_softc *);
 471 static void bce_init                            (void *);
 472 static void bce_mgmt_init_locked        (struct bce_softc *sc);
 473
 474 static int  bce_init_ctx                        (struct bce_softc *);
 475 static void bce_get_mac_addr            (struct bce_softc *);
 476 static void bce_set_mac_addr            (struct bce_softc *);
 477 static void bce_phy_intr                        (struct bce_softc *);
 478 static inline u16 bce_get_hw_rx_cons    (struct bce_softc *);
 479 static void bce_rx_intr                 (struct bce_softc *);
 480 static void bce_tx_intr                 (struct bce_softc *);
 481 static void bce_disable_intr            (struct bce_softc *);
 482 static void bce_enable_intr             (struct bce_softc *, int);
 483
 484 static void bce_intr                            (void *);
 485 static void bce_set_rx_mode             (struct bce_softc *);
 486 static void bce_stats_update            (struct bce_softc *);
 487 static void bce_tick                            (void *);
 488 static void bce_pulse                           (void *);
 489 static void bce_add_sysctls             (struct bce_softc *);
 490
 491
 492 /****************************************************************************/
 493 /* FreeBSD device dispatch table.                                           */
 494 /****************************************************************************/
 495 static device_method_t bce_methods[] = {
 496         /* Device interface (device_if.h) */
 497         DEVMETHOD(device_probe,         bce_probe),
 498         DEVMETHOD(device_attach,        bce_attach),
 499         DEVMETHOD(device_detach,        bce_detach),
 500         DEVMETHOD(device_shutdown,      bce_shutdown),
 501 /* Supported by device interface but not used here. */
 502 /*      DEVMETHOD(device_identify,      bce_identify),      */
 503 /*      DEVMETHOD(device_suspend,       bce_suspend),       */
 504 /*      DEVMETHOD(device_resume,        bce_resume),        */
 505 /*      DEVMETHOD(device_quiesce,       bce_quiesce),       */
 506
 507         /* MII interface (miibus_if.h) */
 508         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 509         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 510         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 511 /* Supported by MII interface but not used here.       */
 512 /*      DEVMETHOD(miibus_linkchg,       bce_miibus_linkchg),   */
 513 /*      DEVMETHOD(miibus_mediainit,     bce_miibus_mediainit), */
 514
 515         DEVMETHOD_END
 516 };
 517
 518 static driver_t bce_driver = {
 519         "bce",
 520         bce_methods,
 521         sizeof(struct bce_softc)
 522 };
 523
 524 static devclass_t bce_devclass;
 525
 526 MODULE_DEPEND(bce, pci, 1, 1, 1);
 527 MODULE_DEPEND(bce, ether, 1, 1, 1);
 528 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 529
 530 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, NULL, NULL);
 531 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
 532 MODULE_PNP_INFO("U16:vendor;U16:device;U16:#;U16:#;D:#", pci, bce,
 533     bce_devs, nitems(bce_devs) - 1);
 534
 535 /****************************************************************************/
 536 /* Tunable device values                                                    */
 537 /****************************************************************************/
 538 static SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
 539     "bce driver parameters");
 540
 541 /* Allowable values are TRUE or FALSE */
 542 static int bce_verbose = TRUE;
 543 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0,
 544     "Verbose output enable/disable");
 545
 546 /* Allowable values are TRUE or FALSE */
 547 static int bce_tso_enable = TRUE;
 548 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0,
 549     "TSO Enable/Disable");
 550
 551 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
 552 /* ToDo: Add MSI-X support. */
 553 static int bce_msi_enable = 1;
 554 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0,
 555     "MSI-X|MSI|INTx selector");
 556
 557 /* Allowable values are 1, 2, 4, 8. */
 558 static int bce_rx_pages = DEFAULT_RX_PAGES;
 559 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0,
 560     "Receive buffer descriptor pages (1 page = 255 buffer descriptors)");
 561
 562 /* Allowable values are 1, 2, 4, 8. */
 563 static int bce_tx_pages = DEFAULT_TX_PAGES;
 564 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0,
 565     "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)");
 566
 567 /* Allowable values are TRUE or FALSE. */
 568 static int bce_hdr_split = TRUE;
 569 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0,
 570     "Frame header/payload splitting Enable/Disable");
 571
 572 /* Allowable values are TRUE or FALSE. */
 573 static int bce_strict_rx_mtu = FALSE;
 574 SYSCTL_UINT(_hw_bce, OID_AUTO, strict_rx_mtu, CTLFLAG_RDTUN,
 575     &bce_strict_rx_mtu, 0,
 576     "Enable/Disable strict RX frame size checking");
 577
 578 /* Allowable values are 0 ... 100 */
 579 #ifdef BCE_DEBUG
 580 /* Generate 1 interrupt for every transmit completion. */
 581 static int bce_tx_quick_cons_trip_int = 1;
 582 #else
 583 /* Generate 1 interrupt for every 20 transmit completions. */
 584 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT;
 585 #endif
 586 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN,
 587     &bce_tx_quick_cons_trip_int, 0,
 588     "Transmit BD trip point during interrupts");
 589
 590 /* Allowable values are 0 ... 100 */
 591 /* Generate 1 interrupt for every transmit completion. */
 592 #ifdef BCE_DEBUG
 593 static int bce_tx_quick_cons_trip = 1;
 594 #else
 595 /* Generate 1 interrupt for every 20 transmit completions. */
 596 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
 597 #endif
 598 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN,
 599     &bce_tx_quick_cons_trip, 0,
 600     "Transmit BD trip point");
 601
 602 /* Allowable values are 0 ... 100 */
 603 #ifdef BCE_DEBUG
 604 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
 605 static int bce_tx_ticks_int = 0;
 606 #else
 607 /* Generate an interrupt if 80us have elapsed since the last TX completion. */
 608 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT;
 609 #endif
 610 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN,
 611     &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt");
 612
 613 /* Allowable values are 0 ... 100 */
 614 #ifdef BCE_DEBUG
 615 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
 616 static int bce_tx_ticks = 0;
 617 #else
 618 /* Generate an interrupt if 80us have elapsed since the last TX completion. */
 619 static int bce_tx_ticks = DEFAULT_TX_TICKS;
 620 #endif
 621 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN,
 622     &bce_tx_ticks, 0, "Transmit ticks count");
 623
 624 /* Allowable values are 1 ... 100 */
 625 #ifdef BCE_DEBUG
 626 /* Generate 1 interrupt for every received frame. */
 627 static int bce_rx_quick_cons_trip_int = 1;
 628 #else
 629 /* Generate 1 interrupt for every 6 received frames. */
 630 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT;
 631 #endif
 632 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN,
 633     &bce_rx_quick_cons_trip_int, 0,
 634     "Receive BD trip point duirng interrupts");
 635
 636 /* Allowable values are 1 ... 100 */
 637 #ifdef BCE_DEBUG
 638 /* Generate 1 interrupt for every received frame. */
 639 static int bce_rx_quick_cons_trip = 1;
 640 #else
 641 /* Generate 1 interrupt for every 6 received frames. */
 642 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP;
 643 #endif
 644 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN,
 645     &bce_rx_quick_cons_trip, 0,
 646     "Receive BD trip point");
 647
 648 /* Allowable values are 0 ... 100 */
 649 #ifdef BCE_DEBUG
 650 /* Generate an int. if 0us have elapsed since the last received frame. */
 651 static int bce_rx_ticks_int = 0;
 652 #else
 653 /* Generate an int. if 18us have elapsed since the last received frame. */
 654 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT;
 655 #endif
 656 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN,
 657     &bce_rx_ticks_int, 0, "Receive ticks count during interrupt");
 658
 659 /* Allowable values are 0 ... 100 */
 660 #ifdef BCE_DEBUG
 661 /* Generate an int. if 0us have elapsed since the last received frame. */
 662 static int bce_rx_ticks = 0;
 663 #else
 664 /* Generate an int. if 18us have elapsed since the last received frame. */
 665 static int bce_rx_ticks = DEFAULT_RX_TICKS;
 666 #endif
 667 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN,
 668     &bce_rx_ticks, 0, "Receive ticks count");
 669
 670
 671 /****************************************************************************/
 672 /* Device probe function.                                                   */
 673 /*                                                                          */
 674 /* Compares the device to the driver's list of supported devices and        */
 675 /* reports back to the OS whether this is the right driver for the device.  */
 676 /*                                                                          */
 677 /* Returns:                                                                 */
 678 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 679 /****************************************************************************/
 680 static int
 681 bce_probe(device_t dev)
 682 {
 683         const struct bce_type *t;
 684         struct bce_softc *sc;
 685         char *descbuf;
 686         u16 vid = 0, did = 0, svid = 0, sdid = 0;
 687
 688         t = bce_devs;
 689
 690         sc = device_get_softc(dev);
 691         sc->bce_unit = device_get_unit(dev);
 692         sc->bce_dev = dev;
 693
 694         /* Get the data for the device to be probed. */
 695         vid  = pci_get_vendor(dev);
 696         did  = pci_get_device(dev);
 697         svid = pci_get_subvendor(dev);
 698         sdid = pci_get_subdevice(dev);
 699
 700         DBPRINT(sc, BCE_EXTREME_LOAD,
 701             "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
 702             "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
 703
 704         /* Look through the list of known devices for a match. */
 705         while(t->bce_name != NULL) {
 706
 707                 if ((vid == t->bce_vid) && (did == t->bce_did) &&
 708                     ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) &&
 709                     ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) {
 710
 711                         descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
 712
 713                         if (descbuf == NULL)
 714                                 return(ENOMEM);
 715
 716                         /* Print out the device identity. */
 717                         snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 718                             t->bce_name, (((pci_read_config(dev,
 719                             PCIR_REVID, 4) & 0xf0) >> 4) + 'A'),
 720                             (pci_read_config(dev, PCIR_REVID, 4) & 0xf));
 721
 722                         device_set_desc_copy(dev, descbuf);
 723                         free(descbuf, M_TEMP);
 724                         return(BUS_PROBE_DEFAULT);
 725                 }
 726                 t++;
 727         }
 728
 729         return(ENXIO);
 730 }
 731
 732
 733 /****************************************************************************/
 734 /* PCI Capabilities Probe Function.                                         */
 735 /*                                                                          */
 736 /* Walks the PCI capabiites list for the device to find what features are   */
 737 /* supported.                                                               */
 738 /*                                                                          */
 739 /* Returns:                                                                 */
 740 /*   None.                                                                  */
 741 /****************************************************************************/
 742 static void
 743 bce_print_adapter_info(struct bce_softc *sc)
 744 {
 745         int i = 0;
 746
 747         DBENTER(BCE_VERBOSE_LOAD);
 748
 749         if (bce_verbose || bootverbose) {
 750                 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid);
 751                 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >>
 752                     12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
 753
 754
 755                 /* Bus info. */
 756                 if (sc->bce_flags & BCE_PCIE_FLAG) {
 757                         printf("Bus (PCIe x%d, ", sc->link_width);
 758                         switch (sc->link_speed) {
 759                         case 1: printf("2.5Gbps); "); break;
 760                         case 2: printf("5Gbps); "); break;
 761                         default: printf("Unknown link speed); ");
 762                         }
 763                 } else {
 764                         printf("Bus (PCI%s, %s, %dMHz); ",
 765                             ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
 766                             ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ?
 767                             "32-bit" : "64-bit"), sc->bus_speed_mhz);
 768                 }
 769
 770                 /* Firmware version and device features. */
 771                 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (",
 772                     sc->bce_bc_ver,     sc->rx_pages, sc->tx_pages,
 773                     (bce_hdr_split == TRUE ? sc->pg_pages: 0));
 774
 775                 if (bce_hdr_split == TRUE) {
 776                         printf("SPLT");
 777                         i++;
 778                 }
 779
 780                 if (sc->bce_flags & BCE_USING_MSI_FLAG) {
 781                         if (i > 0) printf("|");
 782                         printf("MSI"); i++;
 783                 }
 784
 785                 if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
 786                         if (i > 0) printf("|");
 787                         printf("MSI-X"); i++;
 788                 }
 789
 790                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
 791                         if (i > 0) printf("|");
 792                         printf("2.5G"); i++;
 793                 }
 794
 795                 if (sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) {
 796                         if (i > 0) printf("|");
 797                         printf("Remote PHY(%s)",
 798                             sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG ?
 799                             "FIBER" : "TP"); i++;
 800                 }
 801
 802                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
 803                         if (i > 0) printf("|");
 804                         printf("MFW); MFW (%s)\n", sc->bce_mfw_ver);
 805                 } else {
 806                         printf(")\n");
 807                 }
 808
 809                 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n",
 810                     sc->bce_rx_quick_cons_trip_int,
 811                     sc->bce_rx_quick_cons_trip,
 812                     sc->bce_rx_ticks_int,
 813                     sc->bce_rx_ticks,
 814                     sc->bce_tx_quick_cons_trip_int,
 815                     sc->bce_tx_quick_cons_trip,
 816                     sc->bce_tx_ticks_int,
 817                     sc->bce_tx_ticks);
 818
 819         }
 820
 821         DBEXIT(BCE_VERBOSE_LOAD);
 822 }
 823
 824
 825 /****************************************************************************/
 826 /* PCI Capabilities Probe Function.                                         */
 827 /*                                                                          */
 828 /* Walks the PCI capabiites list for the device to find what features are   */
 829 /* supported.                                                               */
 830 /*                                                                          */
 831 /* Returns:                                                                 */
 832 /*   None.                                                                  */
 833 /****************************************************************************/
 834 static void
 835 bce_probe_pci_caps(device_t dev, struct bce_softc *sc)
 836 {
 837         u32 reg;
 838
 839         DBENTER(BCE_VERBOSE_LOAD);
 840
 841         /* Check if PCI-X capability is enabled. */
 842         if (pci_find_cap(dev, PCIY_PCIX, &reg) == 0) {
 843                 if (reg != 0)
 844                         sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
 845         }
 846
 847         /* Check if PCIe capability is enabled. */
 848         if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
 849                 if (reg != 0) {
 850                         u16 link_status = pci_read_config(dev, reg + 0x12, 2);
 851                         DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = "
 852                             "0x%08X\n", link_status);
 853                         sc->link_speed = link_status & 0xf;
 854                         sc->link_width = (link_status >> 4) & 0x3f;
 855                         sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
 856                         sc->bce_flags |= BCE_PCIE_FLAG;
 857                 }
 858         }
 859
 860         /* Check if MSI capability is enabled. */
 861         if (pci_find_cap(dev, PCIY_MSI, &reg) == 0) {
 862                 if (reg != 0)
 863                         sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG;
 864         }
 865
 866         /* Check if MSI-X capability is enabled. */
 867         if (pci_find_cap(dev, PCIY_MSIX, &reg) == 0) {
 868                 if (reg != 0)
 869                         sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG;
 870         }
 871
 872         DBEXIT(BCE_VERBOSE_LOAD);
 873 }
 874
 875
 876 /****************************************************************************/
 877 /* Load and validate user tunable settings.                                 */
 878 /*                                                                          */
 879 /* Returns:                                                                 */
 880 /*   Nothing.                                                               */
 881 /****************************************************************************/
 882 static void
 883 bce_set_tunables(struct bce_softc *sc)
 884 {
 885         /* Set sysctl values for RX page count. */
 886         switch (bce_rx_pages) {
 887         case 1:
 888                 /* fall-through */
 889         case 2:
 890                 /* fall-through */
 891         case 4:
 892                 /* fall-through */
 893         case 8:
 894                 sc->rx_pages = bce_rx_pages;
 895                 break;
 896         default:
 897                 sc->rx_pages = DEFAULT_RX_PAGES;
 898                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 899                     "hw.bce.rx_pages!  Setting default of %d.\n",
 900                     __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES);
 901         }
 902
 903         /* ToDo: Consider allowing user setting for pg_pages. */
 904         sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES);
 905
 906         /* Set sysctl values for TX page count. */
 907         switch (bce_tx_pages) {
 908         case 1:
 909                 /* fall-through */
 910         case 2:
 911                 /* fall-through */
 912         case 4:
 913                 /* fall-through */
 914         case 8:
 915                 sc->tx_pages = bce_tx_pages;
 916                 break;
 917         default:
 918                 sc->tx_pages = DEFAULT_TX_PAGES;
 919                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 920                     "hw.bce.tx_pages!  Setting default of %d.\n",
 921                     __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES);
 922         }
 923
 924         /*
 925          * Validate the TX trip point (i.e. the number of
 926          * TX completions before a status block update is
 927          * generated and an interrupt is asserted.
 928          */
 929         if (bce_tx_quick_cons_trip_int <= 100) {
 930                 sc->bce_tx_quick_cons_trip_int =
 931                     bce_tx_quick_cons_trip_int;
 932         } else {
 933                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 934                     "hw.bce.tx_quick_cons_trip_int!  Setting default of %d.\n",
 935                     __FILE__, __LINE__, bce_tx_quick_cons_trip_int,
 936                     DEFAULT_TX_QUICK_CONS_TRIP_INT);
 937                 sc->bce_tx_quick_cons_trip_int =
 938                     DEFAULT_TX_QUICK_CONS_TRIP_INT;
 939         }
 940
 941         if (bce_tx_quick_cons_trip <= 100) {
 942                 sc->bce_tx_quick_cons_trip =
 943                     bce_tx_quick_cons_trip;
 944         } else {
 945                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 946                     "hw.bce.tx_quick_cons_trip!  Setting default of %d.\n",
 947                     __FILE__, __LINE__, bce_tx_quick_cons_trip,
 948                     DEFAULT_TX_QUICK_CONS_TRIP);
 949                 sc->bce_tx_quick_cons_trip =
 950                     DEFAULT_TX_QUICK_CONS_TRIP;
 951         }
 952
 953         /*
 954          * Validate the TX ticks count (i.e. the maximum amount
 955          * of time to wait after the last TX completion has
 956          * occurred before a status block update is generated
 957          * and an interrupt is asserted.
 958          */
 959         if (bce_tx_ticks_int <= 100) {
 960                 sc->bce_tx_ticks_int =
 961                     bce_tx_ticks_int;
 962         } else {
 963                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 964                     "hw.bce.tx_ticks_int!  Setting default of %d.\n",
 965                     __FILE__, __LINE__, bce_tx_ticks_int,
 966                     DEFAULT_TX_TICKS_INT);
 967                 sc->bce_tx_ticks_int =
 968                     DEFAULT_TX_TICKS_INT;
 969            }
 970
 971         if (bce_tx_ticks <= 100) {
 972                 sc->bce_tx_ticks =
 973                     bce_tx_ticks;
 974         } else {
 975                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 976                     "hw.bce.tx_ticks!  Setting default of %d.\n",
 977                     __FILE__, __LINE__, bce_tx_ticks,
 978                     DEFAULT_TX_TICKS);
 979                 sc->bce_tx_ticks =
 980                     DEFAULT_TX_TICKS;
 981         }
 982
 983         /*
 984          * Validate the RX trip point (i.e. the number of
 985          * RX frames received before a status block update is
 986          * generated and an interrupt is asserted.
 987          */
 988         if (bce_rx_quick_cons_trip_int <= 100) {
 989                 sc->bce_rx_quick_cons_trip_int =
 990                     bce_rx_quick_cons_trip_int;
 991         } else {
 992                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 993                     "hw.bce.rx_quick_cons_trip_int!  Setting default of %d.\n",
 994                     __FILE__, __LINE__, bce_rx_quick_cons_trip_int,
 995                     DEFAULT_RX_QUICK_CONS_TRIP_INT);
 996                 sc->bce_rx_quick_cons_trip_int =
 997                     DEFAULT_RX_QUICK_CONS_TRIP_INT;
 998         }
 999
1000         if (bce_rx_quick_cons_trip <= 100) {
1001                 sc->bce_rx_quick_cons_trip =
1002                     bce_rx_quick_cons_trip;
1003         } else {
1004                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
1005                     "hw.bce.rx_quick_cons_trip!  Setting default of %d.\n",
1006                     __FILE__, __LINE__, bce_rx_quick_cons_trip,
1007                     DEFAULT_RX_QUICK_CONS_TRIP);
1008                 sc->bce_rx_quick_cons_trip =
1009                     DEFAULT_RX_QUICK_CONS_TRIP;
1010         }
1011
1012         /*
1013          * Validate the RX ticks count (i.e. the maximum amount
1014          * of time to wait after the last RX frame has been
1015          * received before a status block update is generated
1016          * and an interrupt is asserted.
1017          */
1018         if (bce_rx_ticks_int <= 100) {
1019                 sc->bce_rx_ticks_int = bce_rx_ticks_int;
1020         } else {
1021                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
1022                     "hw.bce.rx_ticks_int!  Setting default of %d.\n",
1023                     __FILE__, __LINE__, bce_rx_ticks_int,
1024                     DEFAULT_RX_TICKS_INT);
1025                 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT;
1026         }
1027
1028         if (bce_rx_ticks <= 100) {
1029                 sc->bce_rx_ticks = bce_rx_ticks;
1030         } else {
1031                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
1032                     "hw.bce.rx_ticks!  Setting default of %d.\n",
1033                     __FILE__, __LINE__, bce_rx_ticks,
1034                     DEFAULT_RX_TICKS);
1035                 sc->bce_rx_ticks = DEFAULT_RX_TICKS;
1036         }
1037
1038         /* Disabling both RX ticks and RX trips will prevent interrupts. */
1039         if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) {
1040                 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and "
1041                     "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n",
1042                    __FILE__, __LINE__);
1043                 sc->bce_rx_ticks = DEFAULT_RX_TICKS;
1044                 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP;
1045         }
1046
1047         /* Disabling both TX ticks and TX trips will prevent interrupts. */
1048         if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) {
1049                 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and "
1050                     "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n",
1051                    __FILE__, __LINE__);
1052                 sc->bce_tx_ticks = DEFAULT_TX_TICKS;
1053                 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
1054         }
1055 }
1056
1057
1058 /****************************************************************************/
1059 /* Device attach function.                                                  */
1060 /*                                                                          */
1061 /* Allocates device resources, performs secondary chip identification,      */
1062 /* resets and initializes the hardware, and initializes driver instance     */
1063 /* variables.                                                               */
1064 /*                                                                          */
1065 /* Returns:                                                                 */
1066 /*   0 on success, positive value on failure.                               */
1067 /****************************************************************************/
1068 static int
1069 bce_attach(device_t dev)
1070 {
1071         struct bce_softc *sc;
1072         struct ifnet *ifp;
1073         u32 val;
1074         int count, error, rc = 0, rid;
1075
1076         sc = device_get_softc(dev);
1077         sc->bce_dev = dev;
1078
1079         DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1080
1081         sc->bce_unit = device_get_unit(dev);
1082
1083         /* Set initial device and PHY flags */
1084         sc->bce_flags = 0;
1085         sc->bce_phy_flags = 0;
1086
1087         bce_set_tunables(sc);
1088
1089         pci_enable_busmaster(dev);
1090
1091         /* Allocate PCI memory resources. */
1092         rid = PCIR_BAR(0);
1093         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1094                 &rid, RF_ACTIVE);
1095
1096         if (sc->bce_res_mem == NULL) {
1097                 BCE_PRINTF("%s(%d): PCI memory allocation failed\n",
1098                     __FILE__, __LINE__);
1099                 rc = ENXIO;
1100                 goto bce_attach_fail;
1101         }
1102
1103         /* Get various resource handles. */
1104         sc->bce_btag    = rman_get_bustag(sc->bce_res_mem);
1105         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
1106         sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem);
1107
1108         bce_probe_pci_caps(dev, sc);
1109
1110         rid = 1;
1111         count = 0;
1112 #if 0
1113         /* Try allocating MSI-X interrupts. */
1114         if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) &&
1115                 (bce_msi_enable >= 2) &&
1116                 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1117                 &rid, RF_ACTIVE)) != NULL)) {
1118
1119                 msi_needed = count = 1;
1120
1121                 if (((error = pci_alloc_msix(dev, &count)) != 0) ||
1122                         (count != msi_needed)) {
1123                         BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d,"
1124                                 "Received = %d, error = %d\n", __FILE__, __LINE__,
1125                                 msi_needed, count, error);
1126                         count = 0;
1127                         pci_release_msi(dev);
1128                         bus_release_resource(dev, SYS_RES_MEMORY, rid,
1129                                 sc->bce_res_irq);
1130                         sc->bce_res_irq = NULL;
1131                 } else {
1132                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n",
1133                                 __FUNCTION__);
1134                         sc->bce_flags |= BCE_USING_MSIX_FLAG;
1135                 }
1136         }
1137 #endif
1138
1139         /* Try allocating a MSI interrupt. */
1140         if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) &&
1141                 (bce_msi_enable >= 1) && (count == 0)) {
1142                 count = 1;
1143                 if ((error = pci_alloc_msi(dev, &count)) != 0) {
1144                         BCE_PRINTF("%s(%d): MSI allocation failed! "
1145                             "error = %d\n", __FILE__, __LINE__, error);
1146                         count = 0;
1147                         pci_release_msi(dev);
1148                 } else {
1149                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI "
1150                             "interrupt.\n", __FUNCTION__);
1151                         sc->bce_flags |= BCE_USING_MSI_FLAG;
1152                         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
1153                                 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG;
1154                         rid = 1;
1155                 }
1156         }
1157
1158         /* Try allocating a legacy interrupt. */
1159         if (count == 0) {
1160                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n",
1161                         __FUNCTION__);
1162                 rid = 0;
1163         }
1164
1165         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1166             &rid, RF_ACTIVE | (count != 0 ? 0 : RF_SHAREABLE));
1167
1168         /* Report any IRQ allocation errors. */
1169         if (sc->bce_res_irq == NULL) {
1170                 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n",
1171                     __FILE__, __LINE__);
1172                 rc = ENXIO;
1173                 goto bce_attach_fail;
1174         }
1175
1176         /* Initialize mutex for the current device instance. */
1177         BCE_LOCK_INIT(sc, device_get_nameunit(dev));
1178
1179         /*
1180          * Configure byte swap and enable indirect register access.
1181          * Rely on CPU to do target byte swapping on big endian systems.
1182          * Access to registers outside of PCI configurtion space are not
1183          * valid until this is done.
1184          */
1185         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
1186             BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
1187             BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
1188
1189         /* Save ASIC revsion info. */
1190         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
1191
1192         /* Weed out any non-production controller revisions. */
1193         switch(BCE_CHIP_ID(sc)) {
1194         case BCE_CHIP_ID_5706_A0:
1195         case BCE_CHIP_ID_5706_A1:
1196         case BCE_CHIP_ID_5708_A0:
1197         case BCE_CHIP_ID_5708_B0:
1198         case BCE_CHIP_ID_5709_A0:
1199         case BCE_CHIP_ID_5709_B0:
1200         case BCE_CHIP_ID_5709_B1:
1201         case BCE_CHIP_ID_5709_B2:
1202                 BCE_PRINTF("%s(%d): Unsupported controller "
1203                     "revision (%c%d)!\n", __FILE__, __LINE__,
1204                     (((pci_read_config(dev, PCIR_REVID, 4) &
1205                     0xf0) >> 4) + 'A'), (pci_read_config(dev,
1206                     PCIR_REVID, 4) & 0xf));
1207                 rc = ENODEV;
1208                 goto bce_attach_fail;
1209         }
1210
1211         /*
1212          * The embedded PCIe to PCI-X bridge (EPB)
1213          * in the 5708 cannot address memory above
1214          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
1215          */
1216         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
1217                 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR;
1218         else
1219                 sc->max_bus_addr = BUS_SPACE_MAXADDR;
1220
1221         /*
1222          * Find the base address for shared memory access.
1223          * Newer versions of bootcode use a signature and offset
1224          * while older versions use a fixed address.
1225          */
1226         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
1227         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG)
1228                 /* Multi-port devices use different offsets in shared memory. */
1229                 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 +
1230                     (pci_get_function(sc->bce_dev) << 2));
1231         else
1232                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
1233
1234         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n",
1235             __FUNCTION__, sc->bce_shmem_base);
1236
1237         /* Fetch the bootcode revision. */
1238         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
1239         for (int i = 0, j = 0; i < 3; i++) {
1240                 u8 num;
1241
1242                 num = (u8) (val >> (24 - (i * 8)));
1243                 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
1244                         if (num >= k || !skip0 || k == 1) {
1245                                 sc->bce_bc_ver[j++] = (num / k) + '0';
1246                                 skip0 = 0;
1247                         }
1248                 }
1249
1250                 if (i != 2)
1251                         sc->bce_bc_ver[j++] = '.';
1252         }
1253
1254         /* Check if any management firwmare is enabled. */
1255         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
1256         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
1257                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
1258
1259                 /* Allow time for firmware to enter the running state. */
1260                 for (int i = 0; i < 30; i++) {
1261                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
1262                         if (val & BCE_CONDITION_MFW_RUN_MASK)
1263                                 break;
1264                         DELAY(10000);
1265                 }
1266
1267                 /* Check if management firmware is running. */
1268                 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
1269                 val &= BCE_CONDITION_MFW_RUN_MASK;
1270                 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) &&
1271                     (val != BCE_CONDITION_MFW_RUN_NONE)) {
1272                         u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
1273                         int i = 0;
1274
1275                         /* Read the management firmware version string. */
1276                         for (int j = 0; j < 3; j++) {
1277                                 val = bce_reg_rd_ind(sc, addr + j * 4);
1278                                 val = bswap32(val);
1279                                 memcpy(&sc->bce_mfw_ver[i], &val, 4);
1280                                 i += 4;
1281                         }
1282                 } else {
1283                         /* May cause firmware synchronization timeouts. */
1284                         BCE_PRINTF("%s(%d): Management firmware enabled "
1285                             "but not running!\n", __FILE__, __LINE__);
1286                         strcpy(sc->bce_mfw_ver, "NOT RUNNING!");
1287
1288                         /* ToDo: Any action the driver should take? */
1289                 }
1290         }
1291
1292         /* Get PCI bus information (speed and type). */
1293         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
1294         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
1295                 u32 clkreg;
1296
1297                 sc->bce_flags |= BCE_PCIX_FLAG;
1298
1299                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS);
1300
1301                 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
1302                 switch (clkreg) {
1303                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
1304                         sc->bus_speed_mhz = 133;
1305                         break;
1306
1307                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
1308                         sc->bus_speed_mhz = 100;
1309                         break;
1310
1311                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
1312                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
1313                         sc->bus_speed_mhz = 66;
1314                         break;
1315
1316                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
1317                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
1318                         sc->bus_speed_mhz = 50;
1319                         break;
1320
1321                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
1322                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
1323                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
1324                         sc->bus_speed_mhz = 33;
1325                         break;
1326                 }
1327         } else {
1328                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
1329                         sc->bus_speed_mhz = 66;
1330                 else
1331                         sc->bus_speed_mhz = 33;
1332         }
1333
1334         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
1335                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
1336
1337         /* Find the media type for the adapter. */
1338         bce_get_media(sc);
1339
1340         /* Reset controller and announce to bootcode that driver is present. */
1341         if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
1342                 BCE_PRINTF("%s(%d): Controller reset failed!\n",
1343                     __FILE__, __LINE__);
1344                 rc = ENXIO;
1345                 goto bce_attach_fail;
1346         }
1347
1348         /* Initialize the controller. */
1349         if (bce_chipinit(sc)) {
1350                 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
1351                     __FILE__, __LINE__);
1352                 rc = ENXIO;
1353                 goto bce_attach_fail;
1354         }
1355
1356         /* Perform NVRAM test. */
1357         if (bce_nvram_test(sc)) {
1358                 BCE_PRINTF("%s(%d): NVRAM test failed!\n",
1359                     __FILE__, __LINE__);
1360                 rc = ENXIO;
1361                 goto bce_attach_fail;
1362         }
1363
1364         /* Fetch the permanent Ethernet MAC address. */
1365         bce_get_mac_addr(sc);
1366
1367         /* Update statistics once every second. */
1368         sc->bce_stats_ticks = 1000000 & 0xffff00;
1369
1370         /* Store data needed by PHY driver for backplane applications */
1371         sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
1372         sc->bce_port_hw_cfg   = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG);
1373
1374         /* Allocate DMA memory resources. */
1375         if (bce_dma_alloc(dev)) {
1376                 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n",
1377                     __FILE__, __LINE__);
1378                 rc = ENXIO;
1379                 goto bce_attach_fail;
1380         }
1381
1382         /* Allocate an ifnet structure. */
1383         ifp = sc->bce_ifp = if_alloc(IFT_ETHER);
1384         if (ifp == NULL) {
1385                 BCE_PRINTF("%s(%d): Interface allocation failed!\n",
1386                     __FILE__, __LINE__);
1387                 rc = ENXIO;
1388                 goto bce_attach_fail;
1389         }
1390
1391         /* Initialize the ifnet interface. */
1392         ifp->if_softc   = sc;
1393         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1394         ifp->if_flags   = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1395         ifp->if_ioctl   = bce_ioctl;
1396         ifp->if_start   = bce_start;
1397         ifp->if_get_counter = bce_get_counter;
1398         ifp->if_init    = bce_init;
1399         ifp->if_mtu     = ETHERMTU;
1400
1401         if (bce_tso_enable) {
1402                 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO;
1403                 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 |
1404                     IFCAP_VLAN_HWTSO;
1405         } else {
1406                 ifp->if_hwassist = BCE_IF_HWASSIST;
1407                 ifp->if_capabilities = BCE_IF_CAPABILITIES;
1408         }
1409
1410         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1411                 ifp->if_capabilities |= IFCAP_LINKSTATE;
1412
1413         ifp->if_capenable = ifp->if_capabilities;
1414
1415         /*
1416          * Assume standard mbuf sizes for buffer allocation.
1417          * This may change later if the MTU size is set to
1418          * something other than 1500.
1419          */
1420         bce_get_rx_buffer_sizes(sc,
1421             (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN));
1422
1423         /* Recalculate our buffer allocation sizes. */
1424         ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC;
1425         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
1426         IFQ_SET_READY(&ifp->if_snd);
1427
1428         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1429                 ifp->if_baudrate = IF_Mbps(2500ULL);
1430         else
1431                 ifp->if_baudrate = IF_Mbps(1000);
1432
1433         /* Handle any special PHY initialization for SerDes PHYs. */
1434         bce_init_media(sc);
1435
1436         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
1437                 ifmedia_init(&sc->bce_ifmedia, IFM_IMASK, bce_ifmedia_upd,
1438                     bce_ifmedia_sts);
1439                 /*
1440                  * We can't manually override remote PHY's link and assume
1441                  * PHY port configuration(Fiber or TP) is not changed after
1442                  * device attach.  This may not be correct though.
1443                  */
1444                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) {
1445                         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
1446                                 ifmedia_add(&sc->bce_ifmedia,
1447                                     IFM_ETHER | IFM_2500_SX, 0, NULL);
1448                                 ifmedia_add(&sc->bce_ifmedia,
1449                                     IFM_ETHER | IFM_2500_SX | IFM_FDX, 0, NULL);
1450                         }
1451                         ifmedia_add(&sc->bce_ifmedia,
1452                             IFM_ETHER | IFM_1000_SX, 0, NULL);
1453                         ifmedia_add(&sc->bce_ifmedia,
1454                             IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL);
1455                 } else {
1456                         ifmedia_add(&sc->bce_ifmedia,
1457                             IFM_ETHER | IFM_10_T, 0, NULL);
1458                         ifmedia_add(&sc->bce_ifmedia,
1459                             IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
1460                         ifmedia_add(&sc->bce_ifmedia,
1461                             IFM_ETHER | IFM_100_TX, 0, NULL);
1462                         ifmedia_add(&sc->bce_ifmedia,
1463                             IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
1464                         ifmedia_add(&sc->bce_ifmedia,
1465                             IFM_ETHER | IFM_1000_T, 0, NULL);
1466                         ifmedia_add(&sc->bce_ifmedia,
1467                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1468                 }
1469                 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
1470                 ifmedia_set(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO);
1471                 sc->bce_ifmedia.ifm_media = sc->bce_ifmedia.ifm_cur->ifm_media;
1472         } else {
1473                 /* MII child bus by attaching the PHY. */
1474                 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd,
1475                     bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr,
1476                     MII_OFFSET_ANY, MIIF_DOPAUSE);
1477                 if (rc != 0) {
1478                         BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__,
1479                             __LINE__);
1480                         goto bce_attach_fail;
1481                 }
1482         }
1483
1484         /* Attach to the Ethernet interface list. */
1485         ether_ifattach(ifp, sc->eaddr);
1486
1487         callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0);
1488         callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0);
1489
1490         /* Hookup IRQ last. */
1491         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE,
1492                 NULL, bce_intr, sc, &sc->bce_intrhand);
1493
1494         if (rc) {
1495                 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n",
1496                     __FILE__, __LINE__);
1497                 bce_detach(dev);
1498                 goto bce_attach_exit;
1499         }
1500
1501         /*
1502          * At this point we've acquired all the resources
1503          * we need to run so there's no turning back, we're
1504          * cleared for launch.
1505          */
1506
1507         /* Print some important debugging info. */
1508         DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc));
1509
1510         /* Add the supported sysctls to the kernel. */
1511         bce_add_sysctls(sc);
1512
1513         BCE_LOCK(sc);
1514
1515         /*
1516          * The chip reset earlier notified the bootcode that
1517          * a driver is present.  We now need to start our pulse
1518          * routine so that the bootcode is reminded that we're
1519          * still running.
1520          */
1521         bce_pulse(sc);
1522
1523         bce_mgmt_init_locked(sc);
1524         BCE_UNLOCK(sc);
1525
1526         /* Finally, print some useful adapter info */
1527         bce_print_adapter_info(sc);
1528         DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n",
1529                 __FUNCTION__, sc);
1530
1531         goto bce_attach_exit;
1532
1533 bce_attach_fail:
1534         bce_release_resources(sc);
1535
1536 bce_attach_exit:
1537
1538         DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1539
1540         return(rc);
1541 }
1542
1543
1544 /****************************************************************************/
1545 /* Device detach function.                                                  */
1546 /*                                                                          */
1547 /* Stops the controller, resets the controller, and releases resources.     */
1548 /*                                                                          */
1549 /* Returns:                                                                 */
1550 /*   0 on success, positive value on failure.                               */
1551 /****************************************************************************/
1552 static int
1553 bce_detach(device_t dev)
1554 {
1555         struct bce_softc *sc = device_get_softc(dev);
1556         struct ifnet *ifp;
1557         u32 msg;
1558
1559         DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1560
1561         ifp = sc->bce_ifp;
1562
1563         /* Stop and reset the controller. */
1564         BCE_LOCK(sc);
1565
1566         /* Stop the pulse so the bootcode can go to driver absent state. */
1567         callout_stop(&sc->bce_pulse_callout);
1568
1569         bce_stop(sc);
1570         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1571                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1572         else
1573                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1574         bce_reset(sc, msg);
1575
1576         BCE_UNLOCK(sc);
1577
1578         ether_ifdetach(ifp);
1579
1580         /* If we have a child device on the MII bus remove it too. */
1581         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1582                 ifmedia_removeall(&sc->bce_ifmedia);
1583         else {
1584                 bus_generic_detach(dev);
1585                 device_delete_child(dev, sc->bce_miibus);
1586         }
1587
1588         /* Release all remaining resources. */
1589         bce_release_resources(sc);
1590
1591         DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1592
1593         return(0);
1594 }
1595
1596
1597 /****************************************************************************/
1598 /* Device shutdown function.                                                */
1599 /*                                                                          */
1600 /* Stops and resets the controller.                                         */
1601 /*                                                                          */
1602 /* Returns:                                                                 */
1603 /*   0 on success, positive value on failure.                               */
1604 /****************************************************************************/
1605 static int
1606 bce_shutdown(device_t dev)
1607 {
1608         struct bce_softc *sc = device_get_softc(dev);
1609         u32 msg;
1610
1611         DBENTER(BCE_VERBOSE);
1612
1613         BCE_LOCK(sc);
1614         bce_stop(sc);
1615         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1616                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1617         else
1618                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1619         bce_reset(sc, msg);
1620         BCE_UNLOCK(sc);
1621
1622         DBEXIT(BCE_VERBOSE);
1623
1624         return (0);
1625 }
1626
1627
1628 #ifdef BCE_DEBUG
1629 /****************************************************************************/
1630 /* Register read.                                                           */
1631 /*                                                                          */
1632 /* Returns:                                                                 */
1633 /*   The value of the register.                                             */
1634 /****************************************************************************/
1635 static u32
1636 bce_reg_rd(struct bce_softc *sc, u32 offset)
1637 {
1638         u32 val = REG_RD(sc, offset);
1639         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1640                 __FUNCTION__, offset, val);
1641         return val;
1642 }
1643
1644
1645 /****************************************************************************/
1646 /* Register write (16 bit).                                                 */
1647 /*                                                                          */
1648 /* Returns:                                                                 */
1649 /*   Nothing.                                                               */
1650 /****************************************************************************/
1651 static void
1652 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val)
1653 {
1654         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n",
1655                 __FUNCTION__, offset, val);
1656         REG_WR16(sc, offset, val);
1657 }
1658
1659
1660 /****************************************************************************/
1661 /* Register write.                                                          */
1662 /*                                                                          */
1663 /* Returns:                                                                 */
1664 /*   Nothing.                                                               */
1665 /****************************************************************************/
1666 static void
1667 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val)
1668 {
1669         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1670                 __FUNCTION__, offset, val);
1671         REG_WR(sc, offset, val);
1672 }
1673 #endif
1674
1675 /****************************************************************************/
1676 /* Indirect register read.                                                  */
1677 /*                                                                          */
1678 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1679 /* configuration space.  Using this mechanism avoids issues with posted     */
1680 /* reads but is much slower than memory-mapped I/O.                         */
1681 /*                                                                          */
1682 /* Returns:                                                                 */
1683 /*   The value of the register.                                             */
1684 /****************************************************************************/
1685 static u32
1686 bce_reg_rd_ind(struct bce_softc *sc, u32 offset)
1687 {
1688         device_t dev;
1689         dev = sc->bce_dev;
1690
1691         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1692 #ifdef BCE_DEBUG
1693         {
1694                 u32 val;
1695                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1696                 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1697                         __FUNCTION__, offset, val);
1698                 return val;
1699         }
1700 #else
1701         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1702 #endif
1703 }
1704
1705
1706 /****************************************************************************/
1707 /* Indirect register write.                                                 */
1708 /*                                                                          */
1709 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1710 /* configuration space.  Using this mechanism avoids issues with posted     */
1711 /* writes but is muchh slower than memory-mapped I/O.                       */
1712 /*                                                                          */
1713 /* Returns:                                                                 */
1714 /*   Nothing.                                                               */
1715 /****************************************************************************/
1716 static void
1717 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val)
1718 {
1719         device_t dev;
1720         dev = sc->bce_dev;
1721
1722         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1723                 __FUNCTION__, offset, val);
1724
1725         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1726         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1727 }
1728
1729
1730 /****************************************************************************/
1731 /* Shared memory write.                                                     */
1732 /*                                                                          */
1733 /* Writes NetXtreme II shared memory region.                                */
1734 /*                                                                          */
1735 /* Returns:                                                                 */
1736 /*   Nothing.                                                               */
1737 /****************************************************************************/
1738 static void
1739 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val)
1740 {
1741         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X  to  "
1742             "0x%08X\n", __FUNCTION__, val, offset);
1743
1744         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1745 }
1746
1747
1748 /****************************************************************************/
1749 /* Shared memory read.                                                      */
1750 /*                                                                          */
1751 /* Reads NetXtreme II shared memory region.                                 */
1752 /*                                                                          */
1753 /* Returns:                                                                 */
1754 /*   The 32 bit value read.                                                 */
1755 /****************************************************************************/
1756 static u32
1757 bce_shmem_rd(struct bce_softc *sc, u32 offset)
1758 {
1759         u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1760
1761         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from "
1762             "0x%08X\n", __FUNCTION__, val, offset);
1763
1764         return val;
1765 }
1766
1767
1768 #ifdef BCE_DEBUG
1769 /****************************************************************************/
1770 /* Context memory read.                                                     */
1771 /*                                                                          */
1772 /* The NetXtreme II controller uses context memory to track connection      */
1773 /* information for L2 and higher network protocols.                         */
1774 /*                                                                          */
1775 /* Returns:                                                                 */
1776 /*   The requested 32 bit value of context memory.                          */
1777 /****************************************************************************/
1778 static u32
1779 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset)
1780 {
1781         u32 idx, offset, retry_cnt = 5, val;
1782
1783         DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 ||
1784             cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID "
1785             "address: 0x%08X.\n", __FUNCTION__, cid_addr));
1786
1787         offset = ctx_offset + cid_addr;
1788
1789         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1790
1791                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ));
1792
1793                 for (idx = 0; idx < retry_cnt; idx++) {
1794                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1795                         if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0)
1796                                 break;
1797                         DELAY(5);
1798                 }
1799
1800                 if (val & BCE_CTX_CTX_CTRL_READ_REQ)
1801                         BCE_PRINTF("%s(%d); Unable to read CTX memory: "
1802                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1803                             __FILE__, __LINE__, cid_addr, ctx_offset);
1804
1805                 val = REG_RD(sc, BCE_CTX_CTX_DATA);
1806         } else {
1807                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1808                 val = REG_RD(sc, BCE_CTX_DATA);
1809         }
1810
1811         DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1812                 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val);
1813
1814         return(val);
1815 }
1816 #endif
1817
1818
1819 /****************************************************************************/
1820 /* Context memory write.                                                    */
1821 /*                                                                          */
1822 /* The NetXtreme II controller uses context memory to track connection      */
1823 /* information for L2 and higher network protocols.                         */
1824 /*                                                                          */
1825 /* Returns:                                                                 */
1826 /*   Nothing.                                                               */
1827 /****************************************************************************/
1828 static void
1829 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val)
1830 {
1831         u32 idx, offset = ctx_offset + cid_addr;
1832         u32 val, retry_cnt = 5;
1833
1834         DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1835                 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val);
1836
1837         DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK),
1838                 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n",
1839                     __FUNCTION__, cid_addr));
1840
1841         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1842
1843                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1844                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1845
1846                 for (idx = 0; idx < retry_cnt; idx++) {
1847                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1848                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1849                                 break;
1850                         DELAY(5);
1851                 }
1852
1853                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ)
1854                         BCE_PRINTF("%s(%d); Unable to write CTX memory: "
1855                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1856                             __FILE__, __LINE__, cid_addr, ctx_offset);
1857
1858         } else {
1859                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1860                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1861         }
1862 }
1863
1864
1865 /****************************************************************************/
1866 /* PHY register read.                                                       */
1867 /*                                                                          */
1868 /* Implements register reads on the MII bus.                                */
1869 /*                                                                          */
1870 /* Returns:                                                                 */
1871 /*   The value of the register.                                             */
1872 /****************************************************************************/
1873 static int
1874 bce_miibus_read_reg(device_t dev, int phy, int reg)
1875 {
1876         struct bce_softc *sc;
1877         u32 val;
1878         int i;
1879
1880         sc = device_get_softc(dev);
1881
1882     /*
1883      * The 5709S PHY is an IEEE Clause 45 PHY
1884      * with special mappings to work with IEEE
1885      * Clause 22 register accesses.
1886      */
1887         if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1888                 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1889                         reg += 0x10;
1890         }
1891
1892     if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1893                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1894                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1895
1896                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1897                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1898
1899                 DELAY(40);
1900         }
1901
1902
1903         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1904             BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1905             BCE_EMAC_MDIO_COMM_START_BUSY;
1906         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1907
1908         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1909                 DELAY(10);
1910
1911                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1912                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1913                         DELAY(5);
1914
1915                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1916                         val &= BCE_EMAC_MDIO_COMM_DATA;
1917
1918                         break;
1919                 }
1920         }
1921
1922         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1923                 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, "
1924                     "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg);
1925                 val = 0x0;
1926         } else {
1927                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1928         }
1929
1930
1931         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1932                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1933                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1934
1935                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1936                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1937
1938                 DELAY(40);
1939         }
1940
1941         DB_PRINT_PHY_REG(reg, val);
1942         return (val & 0xffff);
1943 }
1944
1945
1946 /****************************************************************************/
1947 /* PHY register write.                                                      */
1948 /*                                                                          */
1949 /* Implements register writes on the MII bus.                               */
1950 /*                                                                          */
1951 /* Returns:                                                                 */
1952 /*   The value of the register.                                             */
1953 /****************************************************************************/
1954 static int
1955 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1956 {
1957         struct bce_softc *sc;
1958         u32 val1;
1959         int i;
1960
1961         sc = device_get_softc(dev);
1962
1963         DB_PRINT_PHY_REG(reg, val);
1964
1965         /*
1966          * The 5709S PHY is an IEEE Clause 45 PHY
1967          * with special mappings to work with IEEE
1968          * Clause 22 register accesses.
1969          */
1970         if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1971                 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1972                         reg += 0x10;
1973         }
1974
1975         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1976                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1977                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1978
1979                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1980                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1981
1982                 DELAY(40);
1983         }
1984
1985         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1986             BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1987             BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1988         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1989
1990         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1991                 DELAY(10);
1992
1993                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1994                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1995                         DELAY(5);
1996                         break;
1997                 }
1998         }
1999
2000         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
2001                 BCE_PRINTF("%s(%d): PHY write timeout!\n",
2002                     __FILE__, __LINE__);
2003
2004         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
2005                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
2006                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
2007
2008                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
2009                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
2010
2011                 DELAY(40);
2012         }
2013
2014         return 0;
2015 }
2016
2017
2018 /****************************************************************************/
2019 /* MII bus status change.                                                   */
2020 /*                                                                          */
2021 /* Called by the MII bus driver when the PHY establishes link to set the    */
2022 /* MAC interface registers.                                                 */
2023 /*                                                                          */
2024 /* Returns:                                                                 */
2025 /*   Nothing.                                                               */
2026 /****************************************************************************/
2027 static void
2028 bce_miibus_statchg(device_t dev)
2029 {
2030         struct bce_softc *sc;
2031         struct mii_data *mii;
2032         struct ifmediareq ifmr;
2033         int media_active, media_status, val;
2034
2035         sc = device_get_softc(dev);
2036
2037         DBENTER(BCE_VERBOSE_PHY);
2038
2039         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
2040                 bzero(&ifmr, sizeof(ifmr));
2041                 bce_ifmedia_sts_rphy(sc, &ifmr);
2042                 media_active = ifmr.ifm_active;
2043                 media_status = ifmr.ifm_status;
2044         } else {
2045                 mii = device_get_softc(sc->bce_miibus);
2046                 media_active = mii->mii_media_active;
2047                 media_status = mii->mii_media_status;
2048         }
2049
2050         /* Ignore invalid media status. */
2051         if ((media_status & (IFM_ACTIVE | IFM_AVALID)) !=
2052             (IFM_ACTIVE | IFM_AVALID))
2053                 goto bce_miibus_statchg_exit;
2054
2055         val = REG_RD(sc, BCE_EMAC_MODE);
2056         val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX |
2057             BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK |
2058             BCE_EMAC_MODE_25G);
2059
2060         /* Set MII or GMII interface based on the PHY speed. */
2061         switch (IFM_SUBTYPE(media_active)) {
2062         case IFM_10_T:
2063                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2064                         DBPRINT(sc, BCE_INFO_PHY,
2065                             "Enabling 10Mb interface.\n");
2066                         val |= BCE_EMAC_MODE_PORT_MII_10;
2067                         break;
2068                 }
2069                 /* fall-through */
2070         case IFM_100_TX:
2071                 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n");
2072                 val |= BCE_EMAC_MODE_PORT_MII;
2073                 break;
2074         case IFM_2500_SX:
2075                 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n");
2076                 val |= BCE_EMAC_MODE_25G;
2077                 /* fall-through */
2078         case IFM_1000_T:
2079         case IFM_1000_SX:
2080                 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n");
2081                 val |= BCE_EMAC_MODE_PORT_GMII;
2082                 break;
2083         default:
2084                 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling "
2085                     "default GMII interface.\n");
2086                 val |= BCE_EMAC_MODE_PORT_GMII;
2087         }
2088
2089         /* Set half or full duplex based on PHY settings. */
2090         if ((IFM_OPTIONS(media_active) & IFM_FDX) == 0) {
2091                 DBPRINT(sc, BCE_INFO_PHY,
2092                     "Setting Half-Duplex interface.\n");
2093                 val |= BCE_EMAC_MODE_HALF_DUPLEX;
2094         } else
2095                 DBPRINT(sc, BCE_INFO_PHY,
2096                     "Setting Full-Duplex interface.\n");
2097
2098         REG_WR(sc, BCE_EMAC_MODE, val);
2099
2100         if ((IFM_OPTIONS(media_active) & IFM_ETH_RXPAUSE) != 0) {
2101                 DBPRINT(sc, BCE_INFO_PHY,
2102                     "%s(): Enabling RX flow control.\n", __FUNCTION__);
2103                 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
2104                 sc->bce_flags |= BCE_USING_RX_FLOW_CONTROL;
2105         } else {
2106                 DBPRINT(sc, BCE_INFO_PHY,
2107                     "%s(): Disabling RX flow control.\n", __FUNCTION__);
2108                 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
2109                 sc->bce_flags &= ~BCE_USING_RX_FLOW_CONTROL;
2110         }
2111
2112         if ((IFM_OPTIONS(media_active) & IFM_ETH_TXPAUSE) != 0) {
2113                 DBPRINT(sc, BCE_INFO_PHY,
2114                     "%s(): Enabling TX flow control.\n", __FUNCTION__);
2115                 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
2116                 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL;
2117         } else {
2118                 DBPRINT(sc, BCE_INFO_PHY,
2119                     "%s(): Disabling TX flow control.\n", __FUNCTION__);
2120                 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
2121                 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL;
2122         }
2123
2124         /* ToDo: Update watermarks in bce_init_rx_context(). */
2125
2126 bce_miibus_statchg_exit:
2127         DBEXIT(BCE_VERBOSE_PHY);
2128 }
2129
2130
2131 /****************************************************************************/
2132 /* Acquire NVRAM lock.                                                      */
2133 /*                                                                          */
2134 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
2135 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
2136 /* for use by the driver.                                                   */
2137 /*                                                                          */
2138 /* Returns:                                                                 */
2139 /*   0 on success, positive value on failure.                               */
2140 /****************************************************************************/
2141 static int
2142 bce_acquire_nvram_lock(struct bce_softc *sc)
2143 {
2144         u32 val;
2145         int j, rc = 0;
2146
2147         DBENTER(BCE_VERBOSE_NVRAM);
2148
2149         /* Request access to the flash interface. */
2150         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
2151         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2152                 val = REG_RD(sc, BCE_NVM_SW_ARB);
2153                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
2154                         break;
2155
2156                 DELAY(5);
2157         }
2158
2159         if (j >= NVRAM_TIMEOUT_COUNT) {
2160                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
2161                 rc = EBUSY;
2162         }
2163
2164         DBEXIT(BCE_VERBOSE_NVRAM);
2165         return (rc);
2166 }
2167
2168
2169 /****************************************************************************/
2170 /* Release NVRAM lock.                                                      */
2171 /*                                                                          */
2172 /* When the caller is finished accessing NVRAM the lock must be released.   */
2173 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
2174 /* for use by the driver.                                                   */
2175 /*                                                                          */
2176 /* Returns:                                                                 */
2177 /*   0 on success, positive value on failure.                               */
2178 /****************************************************************************/
2179 static int
2180 bce_release_nvram_lock(struct bce_softc *sc)
2181 {
2182         u32 val;
2183         int j, rc = 0;
2184
2185         DBENTER(BCE_VERBOSE_NVRAM);
2186
2187         /*
2188          * Relinquish nvram interface.
2189          */
2190         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
2191
2192         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2193                 val = REG_RD(sc, BCE_NVM_SW_ARB);
2194                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
2195                         break;
2196
2197                 DELAY(5);
2198         }
2199
2200         if (j >= NVRAM_TIMEOUT_COUNT) {
2201                 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n");
2202                 rc = EBUSY;
2203         }
2204
2205         DBEXIT(BCE_VERBOSE_NVRAM);
2206         return (rc);
2207 }
2208
2209
2210 #ifdef BCE_NVRAM_WRITE_SUPPORT
2211 /****************************************************************************/
2212 /* Enable NVRAM write access.                                               */
2213 /*                                                                          */
2214 /* Before writing to NVRAM the caller must enable NVRAM writes.             */
2215 /*                                                                          */
2216 /* Returns:                                                                 */
2217 /*   0 on success, positive value on failure.                               */
2218 /****************************************************************************/
2219 static int
2220 bce_enable_nvram_write(struct bce_softc *sc)
2221 {
2222         u32 val;
2223         int rc = 0;
2224
2225         DBENTER(BCE_VERBOSE_NVRAM);
2226
2227         val = REG_RD(sc, BCE_MISC_CFG);
2228         REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);
2229
2230         if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2231                 int j;
2232
2233                 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2234                 REG_WR(sc, BCE_NVM_COMMAND,     BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT);
2235
2236                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2237                         DELAY(5);
2238
2239                         val = REG_RD(sc, BCE_NVM_COMMAND);
2240                         if (val & BCE_NVM_COMMAND_DONE)
2241                                 break;
2242                 }
2243
2244                 if (j >= NVRAM_TIMEOUT_COUNT) {
2245                         DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n");
2246                         rc = EBUSY;
2247                 }
2248         }
2249
2250         DBENTER(BCE_VERBOSE_NVRAM);
2251         return (rc);
2252 }
2253
2254
2255 /****************************************************************************/
2256 /* Disable NVRAM write access.                                              */
2257 /*                                                                          */
2258 /* When the caller is finished writing to NVRAM write access must be        */
2259 /* disabled.                                                                */
2260 /*                                                                          */
2261 /* Returns:                                                                 */
2262 /*   Nothing.                                                               */
2263 /****************************************************************************/
2264 static void
2265 bce_disable_nvram_write(struct bce_softc *sc)
2266 {
2267         u32 val;
2268
2269         DBENTER(BCE_VERBOSE_NVRAM);
2270
2271         val = REG_RD(sc, BCE_MISC_CFG);
2272         REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);
2273
2274         DBEXIT(BCE_VERBOSE_NVRAM);
2275
2276 }
2277 #endif
2278
2279
2280 /****************************************************************************/
2281 /* Enable NVRAM access.                                                     */
2282 /*                                                                          */
2283 /* Before accessing NVRAM for read or write operations the caller must      */
2284 /* enabled NVRAM access.                                                    */
2285 /*                                                                          */
2286 /* Returns:                                                                 */
2287 /*   Nothing.                                                               */
2288 /****************************************************************************/
2289 static void
2290 bce_enable_nvram_access(struct bce_softc *sc)
2291 {
2292         u32 val;
2293
2294         DBENTER(BCE_VERBOSE_NVRAM);
2295
2296         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
2297         /* Enable both bits, even on read. */
2298         REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val |
2299             BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
2300
2301         DBEXIT(BCE_VERBOSE_NVRAM);
2302 }
2303
2304
2305 /****************************************************************************/
2306 /* Disable NVRAM access.                                                    */
2307 /*                                                                          */
2308 /* When the caller is finished accessing NVRAM access must be disabled.     */
2309 /*                                                                          */
2310 /* Returns:                                                                 */
2311 /*   Nothing.                                                               */
2312 /****************************************************************************/
2313 static void
2314 bce_disable_nvram_access(struct bce_softc *sc)
2315 {
2316         u32 val;
2317
2318         DBENTER(BCE_VERBOSE_NVRAM);
2319
2320         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
2321
2322         /* Disable both bits, even after read. */
2323         REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val &
2324             ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
2325
2326         DBEXIT(BCE_VERBOSE_NVRAM);
2327 }
2328
2329
2330 #ifdef BCE_NVRAM_WRITE_SUPPORT
2331 /****************************************************************************/
2332 /* Erase NVRAM page before writing.                                         */
2333 /*                                                                          */
2334 /* Non-buffered flash parts require that a page be erased before it is      */
2335 /* written.                                                                 */
2336 /*                                                                          */
2337 /* Returns:                                                                 */
2338 /*   0 on success, positive value on failure.                               */
2339 /****************************************************************************/
2340 static int
2341 bce_nvram_erase_page(struct bce_softc *sc, u32 offset)
2342 {
2343         u32 cmd;
2344         int j, rc = 0;
2345
2346         DBENTER(BCE_VERBOSE_NVRAM);
2347
2348         /* Buffered flash doesn't require an erase. */
2349         if (sc->bce_flash_info->flags & BCE_NV_BUFFERED)
2350                 goto bce_nvram_erase_page_exit;
2351
2352         /* Build an erase command. */
2353         cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR |
2354             BCE_NVM_COMMAND_DOIT;
2355
2356         /*
2357          * Clear the DONE bit separately, set the NVRAM address to erase,
2358          * and issue the erase command.
2359          */
2360         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2361         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2362         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2363
2364         /* Wait for completion. */
2365         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2366                 u32 val;
2367
2368                 DELAY(5);
2369
2370                 val = REG_RD(sc, BCE_NVM_COMMAND);
2371                 if (val & BCE_NVM_COMMAND_DONE)
2372                         break;
2373         }
2374
2375         if (j >= NVRAM_TIMEOUT_COUNT) {
2376                 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n");
2377                 rc = EBUSY;
2378         }
2379
2380 bce_nvram_erase_page_exit:
2381         DBEXIT(BCE_VERBOSE_NVRAM);
2382         return (rc);
2383 }
2384 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2385
2386
2387 /****************************************************************************/
2388 /* Read a dword (32 bits) from NVRAM.                                       */
2389 /*                                                                          */
2390 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
2391 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
2392 /*                                                                          */
2393 /* Returns:                                                                 */
2394 /*   0 on success and the 32 bit value read, positive value on failure.     */
2395 /****************************************************************************/
2396 static int
2397 bce_nvram_read_dword(struct bce_softc *sc,
2398     u32 offset, u8 *ret_val, u32 cmd_flags)
2399 {
2400         u32 cmd;
2401         int i, rc = 0;
2402
2403         DBENTER(BCE_EXTREME_NVRAM);
2404
2405         /* Build the command word. */
2406         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
2407
2408         /* Calculate the offset for buffered flash if translation is used. */
2409         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2410                 offset = ((offset / sc->bce_flash_info->page_size) <<
2411                     sc->bce_flash_info->page_bits) +
2412                     (offset % sc->bce_flash_info->page_size);
2413         }
2414
2415         /*
2416          * Clear the DONE bit separately, set the address to read,
2417          * and issue the read.
2418          */
2419         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2420         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2421         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2422
2423         /* Wait for completion. */
2424         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
2425                 u32 val;
2426
2427                 DELAY(5);
2428
2429                 val = REG_RD(sc, BCE_NVM_COMMAND);
2430                 if (val & BCE_NVM_COMMAND_DONE) {
2431                         val = REG_RD(sc, BCE_NVM_READ);
2432
2433                         val = bce_be32toh(val);
2434                         memcpy(ret_val, &val, 4);
2435                         break;
2436                 }
2437         }
2438
2439         /* Check for errors. */
2440         if (i >= NVRAM_TIMEOUT_COUNT) {
2441                 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at "
2442                     "offset 0x%08X!\n", __FILE__, __LINE__, offset);
2443                 rc = EBUSY;
2444         }
2445
2446         DBEXIT(BCE_EXTREME_NVRAM);
2447         return(rc);
2448 }
2449
2450
2451 #ifdef BCE_NVRAM_WRITE_SUPPORT
2452 /****************************************************************************/
2453 /* Write a dword (32 bits) to NVRAM.                                        */
2454 /*                                                                          */
2455 /* Write a 32 bit word to NVRAM.  The caller is assumed to have already     */
2456 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and    */
2457 /* enabled NVRAM write access.                                              */
2458 /*                                                                          */
2459 /* Returns:                                                                 */
2460 /*   0 on success, positive value on failure.                               */
2461 /****************************************************************************/
2462 static int
2463 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val,
2464         u32 cmd_flags)
2465 {
2466         u32 cmd, val32;
2467         int j, rc = 0;
2468
2469         DBENTER(BCE_VERBOSE_NVRAM);
2470
2471         /* Build the command word. */
2472         cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags;
2473
2474         /* Calculate the offset for buffered flash if translation is used. */
2475         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2476                 offset = ((offset / sc->bce_flash_info->page_size) <<
2477                     sc->bce_flash_info->page_bits) +
2478                     (offset % sc->bce_flash_info->page_size);
2479         }
2480
2481         /*
2482          * Clear the DONE bit separately, convert NVRAM data to big-endian,
2483          * set the NVRAM address to write, and issue the write command
2484          */
2485         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2486         memcpy(&val32, val, 4);
2487         val32 = htobe32(val32);
2488         REG_WR(sc, BCE_NVM_WRITE, val32);
2489         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2490         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2491
2492         /* Wait for completion. */
2493         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2494                 DELAY(5);
2495
2496                 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE)
2497                         break;
2498         }
2499         if (j >= NVRAM_TIMEOUT_COUNT) {
2500                 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at "
2501                     "offset 0x%08X\n", __FILE__, __LINE__, offset);
2502                 rc = EBUSY;
2503         }
2504
2505         DBEXIT(BCE_VERBOSE_NVRAM);
2506         return (rc);
2507 }
2508 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2509
2510
2511 /****************************************************************************/
2512 /* Initialize NVRAM access.                                                 */
2513 /*                                                                          */
2514 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
2515 /* access that device.                                                      */
2516 /*                                                                          */
2517 /* Returns:                                                                 */
2518 /*   0 on success, positive value on failure.                               */
2519 /****************************************************************************/
2520 static int
2521 bce_init_nvram(struct bce_softc *sc)
2522 {
2523         u32 val;
2524         int j, entry_count, rc = 0;
2525         const struct flash_spec *flash;
2526
2527         DBENTER(BCE_VERBOSE_NVRAM);
2528
2529         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
2530                 sc->bce_flash_info = &flash_5709;
2531                 goto bce_init_nvram_get_flash_size;
2532         }
2533
2534         /* Determine the selected interface. */
2535         val = REG_RD(sc, BCE_NVM_CFG1);
2536
2537         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2538
2539         /*
2540          * Flash reconfiguration is required to support additional
2541          * NVRAM devices not directly supported in hardware.
2542          * Check if the flash interface was reconfigured
2543          * by the bootcode.
2544          */
2545
2546         if (val & 0x40000000) {
2547                 /* Flash interface reconfigured by bootcode. */
2548
2549                 DBPRINT(sc,BCE_INFO_LOAD,
2550                         "bce_init_nvram(): Flash WAS reconfigured.\n");
2551
2552                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2553                      j++, flash++) {
2554                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
2555                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2556                                 sc->bce_flash_info = flash;
2557                                 break;
2558                         }
2559                 }
2560         } else {
2561                 /* Flash interface not yet reconfigured. */
2562                 u32 mask;
2563
2564                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n",
2565                         __FUNCTION__);
2566
2567                 if (val & (1 << 23))
2568                         mask = FLASH_BACKUP_STRAP_MASK;
2569                 else
2570                         mask = FLASH_STRAP_MASK;
2571
2572                 /* Look for the matching NVRAM device configuration data. */
2573                 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) {
2574
2575                         /* Check if the device matches any of the known devices. */
2576                         if ((val & mask) == (flash->strapping & mask)) {
2577                                 /* Found a device match. */
2578                                 sc->bce_flash_info = flash;
2579
2580                                 /* Request access to the flash interface. */
2581                                 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2582                                         return rc;
2583
2584                                 /* Reconfigure the flash interface. */
2585                                 bce_enable_nvram_access(sc);
2586                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
2587                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
2588                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
2589                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
2590                                 bce_disable_nvram_access(sc);
2591                                 bce_release_nvram_lock(sc);
2592
2593                                 break;
2594                         }
2595                 }
2596         }
2597
2598         /* Check if a matching device was found. */
2599         if (j == entry_count) {
2600                 sc->bce_flash_info = NULL;
2601                 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n",
2602                     __FILE__, __LINE__);
2603                 DBEXIT(BCE_VERBOSE_NVRAM);
2604                 return (ENODEV);
2605         }
2606
2607 bce_init_nvram_get_flash_size:
2608         /* Write the flash config data to the shared memory interface. */
2609         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2);
2610         val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
2611         if (val)
2612                 sc->bce_flash_size = val;
2613         else
2614                 sc->bce_flash_size = sc->bce_flash_info->total_size;
2615
2616         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n",
2617             __FUNCTION__, sc->bce_flash_info->name,
2618             sc->bce_flash_info->total_size);
2619
2620         DBEXIT(BCE_VERBOSE_NVRAM);
2621         return rc;
2622 }
2623
2624
2625 /****************************************************************************/
2626 /* Read an arbitrary range of data from NVRAM.                              */
2627 /*                                                                          */
2628 /* Prepares the NVRAM interface for access and reads the requested data     */
2629 /* into the supplied buffer.                                                */
2630 /*                                                                          */
2631 /* Returns:                                                                 */
2632 /*   0 on success and the data read, positive value on failure.             */
2633 /****************************************************************************/
2634 static int
2635 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf,
2636         int buf_size)
2637 {
2638         int rc = 0;
2639         u32 cmd_flags, offset32, len32, extra;
2640
2641         DBENTER(BCE_VERBOSE_NVRAM);
2642
2643         if (buf_size == 0)
2644                 goto bce_nvram_read_exit;
2645
2646         /* Request access to the flash interface. */
2647         if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2648                 goto bce_nvram_read_exit;
2649
2650         /* Enable access to flash interface */
2651         bce_enable_nvram_access(sc);
2652
2653         len32 = buf_size;
2654         offset32 = offset;
2655         extra = 0;
2656
2657         cmd_flags = 0;
2658
2659         if (offset32 & 3) {
2660                 u8 buf[4];
2661                 u32 pre_len;
2662
2663                 offset32 &= ~3;
2664                 pre_len = 4 - (offset & 3);
2665
2666                 if (pre_len >= len32) {
2667                         pre_len = len32;
2668                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
2669                 }
2670                 else {
2671                         cmd_flags = BCE_NVM_COMMAND_FIRST;
2672                 }
2673
2674                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2675
2676                 if (rc)
2677                         return rc;
2678
2679                 memcpy(ret_buf, buf + (offset & 3), pre_len);
2680
2681                 offset32 += 4;
2682                 ret_buf += pre_len;
2683                 len32 -= pre_len;
2684         }
2685
2686         if (len32 & 3) {
2687                 extra = 4 - (len32 & 3);
2688                 len32 = (len32 + 4) & ~3;
2689         }
2690
2691         if (len32 == 4) {
2692                 u8 buf[4];
2693
2694                 if (cmd_flags)
2695                         cmd_flags = BCE_NVM_COMMAND_LAST;
2696                 else
2697                         cmd_flags = BCE_NVM_COMMAND_FIRST |
2698                                     BCE_NVM_COMMAND_LAST;
2699
2700                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2701
2702                 memcpy(ret_buf, buf, 4 - extra);
2703         }
2704         else if (len32 > 0) {
2705                 u8 buf[4];
2706
2707                 /* Read the first word. */
2708                 if (cmd_flags)
2709                         cmd_flags = 0;
2710                 else
2711                         cmd_flags = BCE_NVM_COMMAND_FIRST;
2712
2713                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
2714
2715                 /* Advance to the next dword. */
2716                 offset32 += 4;
2717                 ret_buf += 4;
2718                 len32 -= 4;
2719
2720                 while (len32 > 4 && rc == 0) {
2721                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
2722
2723                         /* Advance to the next dword. */
2724                         offset32 += 4;
2725                         ret_buf += 4;
2726                         len32 -= 4;
2727                 }
2728
2729                 if (rc)
2730                         goto bce_nvram_read_locked_exit;
2731
2732                 cmd_flags = BCE_NVM_COMMAND_LAST;
2733                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2734
2735                 memcpy(ret_buf, buf, 4 - extra);
2736         }
2737
2738 bce_nvram_read_locked_exit:
2739         /* Disable access to flash interface and release the lock. */
2740         bce_disable_nvram_access(sc);
2741         bce_release_nvram_lock(sc);
2742
2743 bce_nvram_read_exit:
2744         DBEXIT(BCE_VERBOSE_NVRAM);
2745         return rc;
2746 }
2747
2748
2749 #ifdef BCE_NVRAM_WRITE_SUPPORT
2750 /****************************************************************************/
2751 /* Write an arbitrary range of data from NVRAM.                             */
2752 /*                                                                          */
2753 /* Prepares the NVRAM interface for write access and writes the requested   */
2754 /* data from the supplied buffer.  The caller is responsible for            */
2755 /* calculating any appropriate CRCs.                                        */
2756 /*                                                                          */
2757 /* Returns:                                                                 */
2758 /*   0 on success, positive value on failure.                               */
2759 /****************************************************************************/
2760 static int
2761 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf,
2762         int buf_size)
2763 {
2764         u32 written, offset32, len32;
2765         u8 *buf, start[4], end[4];
2766         int rc = 0;
2767         int align_start, align_end;
2768
2769         DBENTER(BCE_VERBOSE_NVRAM);
2770
2771         buf = data_buf;
2772         offset32 = offset;
2773         len32 = buf_size;
2774         align_start = align_end = 0;
2775
2776         if ((align_start = (offset32 & 3))) {
2777                 offset32 &= ~3;
2778                 len32 += align_start;
2779                 if ((rc = bce_nvram_read(sc, offset32, start, 4)))
2780                         goto bce_nvram_write_exit;
2781         }
2782
2783         if (len32 & 3) {
2784                 if ((len32 > 4) || !align_start) {
2785                         align_end = 4 - (len32 & 3);
2786                         len32 += align_end;
2787                         if ((rc = bce_nvram_read(sc, offset32 + len32 - 4,
2788                                 end, 4))) {
2789                                 goto bce_nvram_write_exit;
2790                         }
2791                 }
2792         }
2793
2794         if (align_start || align_end) {
2795                 buf = malloc(len32, M_DEVBUF, M_NOWAIT);
2796                 if (buf == NULL) {
2797                         rc = ENOMEM;
2798                         goto bce_nvram_write_exit;
2799                 }
2800
2801                 if (align_start) {
2802                         memcpy(buf, start, 4);
2803                 }
2804
2805                 if (align_end) {
2806                         memcpy(buf + len32 - 4, end, 4);
2807                 }
2808                 memcpy(buf + align_start, data_buf, buf_size);
2809         }
2810
2811         written = 0;
2812         while ((written < len32) && (rc == 0)) {
2813                 u32 page_start, page_end, data_start, data_end;
2814                 u32 addr, cmd_flags;
2815                 int i;
2816                 u8 flash_buffer[264];
2817
2818             /* Find the page_start addr */
2819                 page_start = offset32 + written;
2820                 page_start -= (page_start % sc->bce_flash_info->page_size);
2821                 /* Find the page_end addr */
2822                 page_end = page_start + sc->bce_flash_info->page_size;
2823                 /* Find the data_start addr */
2824                 data_start = (written == 0) ? offset32 : page_start;
2825                 /* Find the data_end addr */
2826                 data_end = (page_end > offset32 + len32) ?
2827                         (offset32 + len32) : page_end;
2828
2829                 /* Request access to the flash interface. */
2830                 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2831                         goto bce_nvram_write_exit;
2832
2833                 /* Enable access to flash interface */
2834                 bce_enable_nvram_access(sc);
2835
2836                 cmd_flags = BCE_NVM_COMMAND_FIRST;
2837                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2838                         int j;
2839
2840                         /* Read the whole page into the buffer
2841                          * (non-buffer flash only) */
2842                         for (j = 0; j < sc->bce_flash_info->page_size; j += 4) {
2843                                 if (j == (sc->bce_flash_info->page_size - 4)) {
2844                                         cmd_flags |= BCE_NVM_COMMAND_LAST;
2845                                 }
2846                                 rc = bce_nvram_read_dword(sc,
2847                                         page_start + j,
2848                                         &flash_buffer[j],
2849                                         cmd_flags);
2850
2851                                 if (rc)
2852                                         goto bce_nvram_write_locked_exit;
2853
2854                                 cmd_flags = 0;
2855                         }
2856                 }
2857
2858                 /* Enable writes to flash interface (unlock write-protect) */
2859                 if ((rc = bce_enable_nvram_write(sc)) != 0)
2860                         goto bce_nvram_write_locked_exit;
2861
2862                 /* Erase the page */
2863                 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0)
2864                         goto bce_nvram_write_locked_exit;
2865
2866                 /* Re-enable the write again for the actual write */
2867                 bce_enable_nvram_write(sc);
2868
2869                 /* Loop to write back the buffer data from page_start to
2870                  * data_start */
2871                 i = 0;
2872                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2873                         for (addr = page_start; addr < data_start;
2874                                 addr += 4, i += 4) {
2875
2876                                 rc = bce_nvram_write_dword(sc, addr,
2877                                         &flash_buffer[i], cmd_flags);
2878
2879                                 if (rc != 0)
2880                                         goto bce_nvram_write_locked_exit;
2881
2882                                 cmd_flags = 0;
2883                         }
2884                 }
2885
2886                 /* Loop to write the new data from data_start to data_end */
2887                 for (addr = data_start; addr < data_end; addr += 4, i++) {
2888                         if ((addr == page_end - 4) ||
2889                                 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) &&
2890                                 (addr == data_end - 4))) {
2891
2892                                 cmd_flags |= BCE_NVM_COMMAND_LAST;
2893                         }
2894                         rc = bce_nvram_write_dword(sc, addr, buf,
2895                                 cmd_flags);
2896
2897                         if (rc != 0)
2898                                 goto bce_nvram_write_locked_exit;
2899
2900                         cmd_flags = 0;
2901                         buf += 4;
2902                 }
2903
2904                 /* Loop to write back the buffer data from data_end
2905                  * to page_end */
2906                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2907                         for (addr = data_end; addr < page_end;
2908                                 addr += 4, i += 4) {
2909
2910                                 if (addr == page_end-4) {
2911                                         cmd_flags = BCE_NVM_COMMAND_LAST;
2912                                 }
2913                                 rc = bce_nvram_write_dword(sc, addr,
2914                                         &flash_buffer[i], cmd_flags);
2915
2916                                 if (rc != 0)
2917                                         goto bce_nvram_write_locked_exit;
2918
2919                                 cmd_flags = 0;
2920                         }
2921                 }
2922
2923                 /* Disable writes to flash interface (lock write-protect) */
2924                 bce_disable_nvram_write(sc);
2925
2926                 /* Disable access to flash interface */
2927                 bce_disable_nvram_access(sc);
2928                 bce_release_nvram_lock(sc);
2929
2930                 /* Increment written */
2931                 written += data_end - data_start;
2932         }
2933
2934         goto bce_nvram_write_exit;
2935
2936 bce_nvram_write_locked_exit:
2937         bce_disable_nvram_write(sc);
2938         bce_disable_nvram_access(sc);
2939         bce_release_nvram_lock(sc);
2940
2941 bce_nvram_write_exit:
2942         if (align_start || align_end)
2943                 free(buf, M_DEVBUF);
2944
2945         DBEXIT(BCE_VERBOSE_NVRAM);
2946         return (rc);
2947 }
2948 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2949
2950
2951 /****************************************************************************/
2952 /* Verifies that NVRAM is accessible and contains valid data.               */
2953 /*                                                                          */
2954 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
2955 /* correct.                                                                 */
2956 /*                                                                          */
2957 /* Returns:                                                                 */
2958 /*   0 on success, positive value on failure.                               */
2959 /****************************************************************************/
2960 static int
2961 bce_nvram_test(struct bce_softc *sc)
2962 {
2963         u32 buf[BCE_NVRAM_SIZE / 4];
2964         u8 *data = (u8 *) buf;
2965         int rc = 0;
2966         u32 magic, csum;
2967
2968         DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
2969
2970         /*
2971          * Check that the device NVRAM is valid by reading
2972          * the magic value at offset 0.
2973          */
2974         if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) {
2975                 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n",
2976                     __FILE__, __LINE__);
2977                 goto bce_nvram_test_exit;
2978         }
2979
2980         /*
2981          * Verify that offset 0 of the NVRAM contains
2982          * a valid magic number.
2983          */
2984         magic = bce_be32toh(buf[0]);
2985         if (magic != BCE_NVRAM_MAGIC) {
2986                 rc = ENODEV;
2987                 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! "
2988                     "Expected: 0x%08X, Found: 0x%08X\n",
2989                     __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic);
2990                 goto bce_nvram_test_exit;
2991         }
2992
2993         /*
2994          * Verify that the device NVRAM includes valid
2995          * configuration data.
2996          */
2997         if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) {
2998                 BCE_PRINTF("%s(%d): Unable to read manufacturing "
2999                     "Information from  NVRAM!\n", __FILE__, __LINE__);
3000                 goto bce_nvram_test_exit;
3001         }
3002
3003         csum = ether_crc32_le(data, 0x100);
3004         if (csum != BCE_CRC32_RESIDUAL) {
3005                 rc = ENODEV;
3006                 BCE_PRINTF("%s(%d): Invalid manufacturing information "
3007                     "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n",
3008                     __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum);
3009                 goto bce_nvram_test_exit;
3010         }
3011
3012         csum = ether_crc32_le(data + 0x100, 0x100);
3013         if (csum != BCE_CRC32_RESIDUAL) {
3014                 rc = ENODEV;
3015                 BCE_PRINTF("%s(%d): Invalid feature configuration "
3016                     "information NVRAM CRC! Expected: 0x%08X, "
3017                     "Found: 08%08X\n", __FILE__, __LINE__,
3018                     BCE_CRC32_RESIDUAL, csum);
3019         }
3020
3021 bce_nvram_test_exit:
3022         DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
3023         return rc;
3024 }
3025
3026
3027 /****************************************************************************/
3028 /* Calculates the size of the buffers to allocate based on the MTU.         */
3029 /*                                                                          */
3030 /* Returns:                                                                 */
3031 /*   Nothing.                                                               */
3032 /****************************************************************************/
3033 static void
3034 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu)
3035 {
3036         DBENTER(BCE_VERBOSE_LOAD);
3037
3038         /* Use a single allocation type when header splitting enabled. */
3039         if (bce_hdr_split == TRUE) {
3040                 sc->rx_bd_mbuf_alloc_size = MHLEN;
3041                 /* Make sure offset is 16 byte aligned for hardware. */
3042                 sc->rx_bd_mbuf_align_pad =
3043                         roundup2(MSIZE - MHLEN, 16) - (MSIZE - MHLEN);
3044                 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
3045                         sc->rx_bd_mbuf_align_pad;
3046         } else {
3047                 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
3048                     ETHER_CRC_LEN) > MCLBYTES) {
3049                         /* Setup for jumbo RX buffer allocations. */
3050                         sc->rx_bd_mbuf_alloc_size = MJUM9BYTES;
3051                         sc->rx_bd_mbuf_align_pad  =
3052                                 roundup2(MJUM9BYTES, 16) - MJUM9BYTES;
3053                         sc->rx_bd_mbuf_data_len =
3054                             sc->rx_bd_mbuf_alloc_size -
3055                             sc->rx_bd_mbuf_align_pad;
3056                 } else {
3057                         /* Setup for standard RX buffer allocations. */
3058                         sc->rx_bd_mbuf_alloc_size = MCLBYTES;
3059                         sc->rx_bd_mbuf_align_pad  =
3060                             roundup2(MCLBYTES, 16) - MCLBYTES;
3061                         sc->rx_bd_mbuf_data_len =
3062                             sc->rx_bd_mbuf_alloc_size -
3063                             sc->rx_bd_mbuf_align_pad;
3064                 }
3065         }
3066
3067 //      DBPRINT(sc, BCE_INFO_LOAD,
3068         DBPRINT(sc, BCE_WARN,
3069            "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, "
3070            "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__,
3071            sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len,
3072            sc->rx_bd_mbuf_align_pad);
3073
3074         DBEXIT(BCE_VERBOSE_LOAD);
3075 }
3076
3077 /****************************************************************************/
3078 /* Identifies the current media type of the controller and sets the PHY     */
3079 /* address.                                                                 */
3080 /*                                                                          */
3081 /* Returns:                                                                 */
3082 /*   Nothing.                                                               */
3083 /****************************************************************************/
3084 static void
3085 bce_get_media(struct bce_softc *sc)
3086 {
3087         u32 val;
3088
3089         DBENTER(BCE_VERBOSE_PHY);
3090
3091         /* Assume PHY address for copper controllers. */
3092         sc->bce_phy_addr = 1;
3093
3094         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3095                 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
3096                 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
3097                 u32 strap;
3098
3099                 /*
3100                  * The BCM5709S is software configurable
3101                  * for Copper or SerDes operation.
3102                  */
3103                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
3104                         DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
3105                             "for copper.\n");
3106                         goto bce_get_media_exit;
3107                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
3108                         DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
3109                             "for dual media.\n");
3110                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3111                         goto bce_get_media_exit;
3112                 }
3113
3114                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
3115                         strap = (val &
3116                             BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
3117                 else
3118                         strap = (val &
3119                             BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
3120
3121                 if (pci_get_function(sc->bce_dev) == 0) {
3122                         switch (strap) {
3123                         case 0x4:
3124                         case 0x5:
3125                         case 0x6:
3126                                 DBPRINT(sc, BCE_INFO_LOAD,
3127                                     "BCM5709 s/w configured for SerDes.\n");
3128                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3129                                 break;
3130                         default:
3131                                 DBPRINT(sc, BCE_INFO_LOAD,
3132                                     "BCM5709 s/w configured for Copper.\n");
3133                                 break;
3134                         }
3135                 } else {
3136                         switch (strap) {
3137                         case 0x1:
3138                         case 0x2:
3139                         case 0x4:
3140                                 DBPRINT(sc, BCE_INFO_LOAD,
3141                                     "BCM5709 s/w configured for SerDes.\n");
3142                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3143                                 break;
3144                         default:
3145                                 DBPRINT(sc, BCE_INFO_LOAD,
3146                                     "BCM5709 s/w configured for Copper.\n");
3147                                 break;
3148                         }
3149                 }
3150
3151         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT)
3152                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3153
3154         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
3155
3156                 sc->bce_flags |= BCE_NO_WOL_FLAG;
3157
3158                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
3159                         sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG;
3160
3161                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
3162                         /* 5708S/09S/16S use a separate PHY for SerDes. */
3163                         sc->bce_phy_addr = 2;
3164
3165                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
3166                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G) {
3167                                 sc->bce_phy_flags |=
3168                                     BCE_PHY_2_5G_CAPABLE_FLAG;
3169                                 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb "
3170                                     "capable adapter\n");
3171                         }
3172                 }
3173         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
3174             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708))
3175                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
3176
3177 bce_get_media_exit:
3178         DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY),
3179                 "Using PHY address %d.\n", sc->bce_phy_addr);
3180
3181         DBEXIT(BCE_VERBOSE_PHY);
3182 }
3183
3184
3185 /****************************************************************************/
3186 /* Performs PHY initialization required before MII drivers access the       */
3187 /* device.                                                                  */
3188 /*                                                                          */
3189 /* Returns:                                                                 */
3190 /*   Nothing.                                                               */
3191 /****************************************************************************/
3192 static void
3193 bce_init_media(struct bce_softc *sc)
3194 {
3195         if ((sc->bce_phy_flags & (BCE_PHY_IEEE_CLAUSE_45_FLAG |
3196             BCE_PHY_REMOTE_CAP_FLAG)) == BCE_PHY_IEEE_CLAUSE_45_FLAG) {
3197                 /*
3198                  * Configure 5709S/5716S PHYs to use traditional IEEE
3199                  * Clause 22 method. Otherwise we have no way to attach
3200                  * the PHY in mii(4) layer. PHY specific configuration
3201                  * is done in mii layer.
3202                  */
3203
3204                 /* Select auto-negotiation MMD of the PHY. */
3205                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3206                     BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT);
3207                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3208                     BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD);
3209
3210                 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */
3211                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3212                     BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
3213         }
3214 }
3215
3216
3217 /****************************************************************************/
3218 /* Free any DMA memory owned by the driver.                                 */
3219 /*                                                                          */
3220 /* Scans through each data structre that requires DMA memory and frees      */
3221 /* the memory if allocated.                                                 */
3222 /*                                                                          */
3223 /* Returns:                                                                 */
3224 /*   Nothing.                                                               */
3225 /****************************************************************************/
3226 static void
3227 bce_dma_free(struct bce_softc *sc)
3228 {
3229         int i;
3230
3231         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
3232
3233         /* Free, unmap, and destroy the status block. */
3234         if (sc->status_block_paddr != 0) {
3235                 bus_dmamap_unload(
3236                     sc->status_tag,
3237                     sc->status_map);
3238                 sc->status_block_paddr = 0;
3239         }
3240
3241         if (sc->status_block != NULL) {
3242                 bus_dmamem_free(
3243                    sc->status_tag,
3244                     sc->status_block,
3245                     sc->status_map);
3246                 sc->status_block = NULL;
3247         }
3248
3249         if (sc->status_tag != NULL) {
3250                 bus_dma_tag_destroy(sc->status_tag);
3251                 sc->status_tag = NULL;
3252         }
3253
3254
3255         /* Free, unmap, and destroy the statistics block. */
3256         if (sc->stats_block_paddr != 0) {
3257                 bus_dmamap_unload(
3258                     sc->stats_tag,
3259                     sc->stats_map);
3260                 sc->stats_block_paddr = 0;
3261         }
3262
3263         if (sc->stats_block != NULL) {
3264                 bus_dmamem_free(
3265                     sc->stats_tag,
3266                     sc->stats_block,
3267                     sc->stats_map);
3268                 sc->stats_block = NULL;
3269         }
3270
3271         if (sc->stats_tag != NULL) {
3272                 bus_dma_tag_destroy(sc->stats_tag);
3273                 sc->stats_tag = NULL;
3274         }
3275
3276
3277         /* Free, unmap and destroy all context memory pages. */
3278         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3279                 for (i = 0; i < sc->ctx_pages; i++ ) {
3280                         if (sc->ctx_paddr[i] != 0) {
3281                                 bus_dmamap_unload(
3282                                     sc->ctx_tag,
3283                                     sc->ctx_map[i]);
3284                                 sc->ctx_paddr[i] = 0;
3285                         }
3286
3287                         if (sc->ctx_block[i] != NULL) {
3288                                 bus_dmamem_free(
3289                                     sc->ctx_tag,
3290                                     sc->ctx_block[i],
3291                                     sc->ctx_map[i]);
3292                                 sc->ctx_block[i] = NULL;
3293                         }
3294                 }
3295
3296                 /* Destroy the context memory tag. */
3297                 if (sc->ctx_tag != NULL) {
3298                         bus_dma_tag_destroy(sc->ctx_tag);
3299                         sc->ctx_tag = NULL;
3300                 }
3301         }
3302
3303
3304         /* Free, unmap and destroy all TX buffer descriptor chain pages. */
3305         for (i = 0; i < sc->tx_pages; i++ ) {
3306                 if (sc->tx_bd_chain_paddr[i] != 0) {
3307                         bus_dmamap_unload(
3308                             sc->tx_bd_chain_tag,
3309                             sc->tx_bd_chain_map[i]);
3310                         sc->tx_bd_chain_paddr[i] = 0;
3311                 }
3312
3313                 if (sc->tx_bd_chain[i] != NULL) {
3314                         bus_dmamem_free(
3315                             sc->tx_bd_chain_tag,
3316                             sc->tx_bd_chain[i],
3317                             sc->tx_bd_chain_map[i]);
3318                         sc->tx_bd_chain[i] = NULL;
3319                 }
3320         }
3321
3322         /* Destroy the TX buffer descriptor tag. */
3323         if (sc->tx_bd_chain_tag != NULL) {
3324                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
3325                 sc->tx_bd_chain_tag = NULL;
3326         }
3327
3328
3329         /* Free, unmap and destroy all RX buffer descriptor chain pages. */
3330         for (i = 0; i < sc->rx_pages; i++ ) {
3331                 if (sc->rx_bd_chain_paddr[i] != 0) {
3332                         bus_dmamap_unload(
3333                             sc->rx_bd_chain_tag,
3334                             sc->rx_bd_chain_map[i]);
3335                         sc->rx_bd_chain_paddr[i] = 0;
3336                 }
3337
3338                 if (sc->rx_bd_chain[i] != NULL) {
3339                         bus_dmamem_free(
3340                             sc->rx_bd_chain_tag,
3341                             sc->rx_bd_chain[i],
3342                             sc->rx_bd_chain_map[i]);
3343                         sc->rx_bd_chain[i] = NULL;
3344                 }
3345         }
3346
3347         /* Destroy the RX buffer descriptor tag. */
3348         if (sc->rx_bd_chain_tag != NULL) {
3349                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
3350                 sc->rx_bd_chain_tag = NULL;
3351         }
3352
3353
3354         /* Free, unmap and destroy all page buffer descriptor chain pages. */
3355         if (bce_hdr_split == TRUE) {
3356                 for (i = 0; i < sc->pg_pages; i++ ) {
3357                         if (sc->pg_bd_chain_paddr[i] != 0) {
3358                                 bus_dmamap_unload(
3359                                     sc->pg_bd_chain_tag,
3360                                     sc->pg_bd_chain_map[i]);
3361                                 sc->pg_bd_chain_paddr[i] = 0;
3362                         }
3363
3364                         if (sc->pg_bd_chain[i] != NULL) {
3365                                 bus_dmamem_free(
3366                                     sc->pg_bd_chain_tag,
3367                                     sc->pg_bd_chain[i],
3368                                     sc->pg_bd_chain_map[i]);
3369                                 sc->pg_bd_chain[i] = NULL;
3370                         }
3371                 }
3372
3373                 /* Destroy the page buffer descriptor tag. */
3374                 if (sc->pg_bd_chain_tag != NULL) {
3375                         bus_dma_tag_destroy(sc->pg_bd_chain_tag);
3376                         sc->pg_bd_chain_tag = NULL;
3377                 }
3378         }
3379
3380
3381         /* Unload and destroy the TX mbuf maps. */
3382         for (i = 0; i < MAX_TX_BD_AVAIL; i++) {
3383                 if (sc->tx_mbuf_map[i] != NULL) {
3384                         bus_dmamap_unload(sc->tx_mbuf_tag,
3385                             sc->tx_mbuf_map[i]);
3386                         bus_dmamap_destroy(sc->tx_mbuf_tag,
3387                             sc->tx_mbuf_map[i]);
3388                         sc->tx_mbuf_map[i] = NULL;
3389                 }
3390         }
3391
3392         /* Destroy the TX mbuf tag. */
3393         if (sc->tx_mbuf_tag != NULL) {
3394                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
3395                 sc->tx_mbuf_tag = NULL;
3396         }
3397
3398         /* Unload and destroy the RX mbuf maps. */
3399         for (i = 0; i < MAX_RX_BD_AVAIL; i++) {
3400                 if (sc->rx_mbuf_map[i] != NULL) {
3401                         bus_dmamap_unload(sc->rx_mbuf_tag,
3402                             sc->rx_mbuf_map[i]);
3403                         bus_dmamap_destroy(sc->rx_mbuf_tag,
3404                             sc->rx_mbuf_map[i]);
3405                         sc->rx_mbuf_map[i] = NULL;
3406                 }
3407         }
3408
3409         /* Destroy the RX mbuf tag. */
3410         if (sc->rx_mbuf_tag != NULL) {
3411                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
3412                 sc->rx_mbuf_tag = NULL;
3413         }
3414
3415         /* Unload and destroy the page mbuf maps. */
3416         if (bce_hdr_split == TRUE) {
3417                 for (i = 0; i < MAX_PG_BD_AVAIL; i++) {
3418                         if (sc->pg_mbuf_map[i] != NULL) {
3419                                 bus_dmamap_unload(sc->pg_mbuf_tag,
3420                                     sc->pg_mbuf_map[i]);
3421                                 bus_dmamap_destroy(sc->pg_mbuf_tag,
3422                                     sc->pg_mbuf_map[i]);
3423                                 sc->pg_mbuf_map[i] = NULL;
3424                         }
3425                 }
3426
3427                 /* Destroy the page mbuf tag. */
3428                 if (sc->pg_mbuf_tag != NULL) {
3429                         bus_dma_tag_destroy(sc->pg_mbuf_tag);
3430                         sc->pg_mbuf_tag = NULL;
3431                 }
3432         }
3433
3434         /* Destroy the parent tag */
3435         if (sc->parent_tag != NULL) {
3436                 bus_dma_tag_destroy(sc->parent_tag);
3437                 sc->parent_tag = NULL;
3438         }
3439
3440         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
3441 }
3442
3443
3444 /****************************************************************************/
3445 /* Get DMA memory from the OS.                                              */
3446 /*                                                                          */
3447 /* Validates that the OS has provided DMA buffers in response to a          */
3448 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
3449 /* When the callback is used the OS will return 0 for the mapping function  */
3450 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
3451 /* failures back to the caller.                                             */
3452 /*                                                                          */
3453 /* Returns:                                                                 */
3454 /*   Nothing.                                                               */
3455 /****************************************************************************/
3456 static void
3457 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3458 {
3459         bus_addr_t *busaddr = arg;
3460
3461         KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!",
3462             __FUNCTION__, nseg));
3463         /* Simulate a mapping failure. */
3464         DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control),
3465             error = ENOMEM);
3466
3467         /* ToDo: How to increment debug sim_count variable here? */
3468
3469         /* Check for an error and signal the caller that an error occurred. */
3470         if (error) {
3471                 *busaddr = 0;
3472         } else {
3473                 *busaddr = segs->ds_addr;
3474         }
3475 }
3476
3477
3478 /****************************************************************************/
3479 /* Allocate any DMA memory needed by the driver.                            */
3480 /*                                                                          */
3481 /* Allocates DMA memory needed for the various global structures needed by  */
3482 /* hardware.                                                                */
3483 /*                                                                          */
3484 /* Memory alignment requirements:                                           */
3485 /* +-----------------+----------+----------+----------+----------+          */
3486 /* |                 |   5706   |   5708   |   5709   |   5716   |          */
3487 /* +-----------------+----------+----------+----------+----------+          */
3488 /* |Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |          */
3489 /* |Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |          */
3490 /* |RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |          */
3491 /* |PG Buffers       |   none   |   none   |   none   |   none   |          */
3492 /* |TX Buffers       |   none   |   none   |   none   |   none   |          */
3493 /* |Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |          */
3494 /* |Context Memory   |          |          |          |          |          */
3495 /* +-----------------+----------+----------+----------+----------+          */
3496 /*                                                                          */
3497 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
3498 /*                                                                          */
3499 /* Returns:                                                                 */
3500 /*   0 for success, positive value for failure.                             */
3501 /****************************************************************************/
3502 static int
3503 bce_dma_alloc(device_t dev)
3504 {
3505         struct bce_softc *sc;
3506         int i, error, rc = 0;
3507         bus_size_t max_size, max_seg_size;
3508         int max_segments;
3509
3510         sc = device_get_softc(dev);
3511
3512         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3513
3514         /*
3515          * Allocate the parent bus DMA tag appropriate for PCI.
3516          */
3517         if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY,
3518             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3519             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
3520             &sc->parent_tag)) {
3521                 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n",
3522                     __FILE__, __LINE__);
3523                 rc = ENOMEM;
3524                 goto bce_dma_alloc_exit;
3525         }
3526
3527         /*
3528          * Create a DMA tag for the status block, allocate and clear the
3529          * memory, map the memory into DMA space, and fetch the physical
3530          * address of the block.
3531          */
3532         if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3533             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3534             NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ,
3535             0, NULL, NULL, &sc->status_tag)) {
3536                 BCE_PRINTF("%s(%d): Could not allocate status block "
3537                     "DMA tag!\n", __FILE__, __LINE__);
3538                 rc = ENOMEM;
3539                 goto bce_dma_alloc_exit;
3540         }
3541
3542         if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block,
3543             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3544             &sc->status_map)) {
3545                 BCE_PRINTF("%s(%d): Could not allocate status block "
3546                     "DMA memory!\n", __FILE__, __LINE__);
3547                 rc = ENOMEM;
3548                 goto bce_dma_alloc_exit;
3549         }
3550
3551         error = bus_dmamap_load(sc->status_tag, sc->status_map,
3552             sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr,
3553             &sc->status_block_paddr, BUS_DMA_NOWAIT);
3554
3555         if (error || sc->status_block_paddr == 0) {
3556                 BCE_PRINTF("%s(%d): Could not map status block "
3557                     "DMA memory!\n", __FILE__, __LINE__);
3558                 rc = ENOMEM;
3559                 goto bce_dma_alloc_exit;
3560         }
3561
3562         DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n",
3563             __FUNCTION__, (uintmax_t) sc->status_block_paddr);
3564
3565         /*
3566          * Create a DMA tag for the statistics block, allocate and clear the
3567          * memory, map the memory into DMA space, and fetch the physical
3568          * address of the block.
3569          */
3570         if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3571             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3572             NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ,
3573             0, NULL, NULL, &sc->stats_tag)) {
3574                 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3575                     "DMA tag!\n", __FILE__, __LINE__);
3576                 rc = ENOMEM;
3577                 goto bce_dma_alloc_exit;
3578         }
3579
3580         if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block,
3581             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) {
3582                 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3583                     "DMA memory!\n", __FILE__, __LINE__);
3584                 rc = ENOMEM;
3585                 goto bce_dma_alloc_exit;
3586         }
3587
3588         error = bus_dmamap_load(sc->stats_tag, sc->stats_map,
3589             sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr,
3590             &sc->stats_block_paddr, BUS_DMA_NOWAIT);
3591
3592         if (error || sc->stats_block_paddr == 0) {
3593                 BCE_PRINTF("%s(%d): Could not map statistics block "
3594                     "DMA memory!\n", __FILE__, __LINE__);
3595                 rc = ENOMEM;
3596                 goto bce_dma_alloc_exit;
3597         }
3598
3599         DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n",
3600             __FUNCTION__, (uintmax_t) sc->stats_block_paddr);
3601
3602         /* BCM5709 uses host memory as cache for context memory. */
3603         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3604                 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
3605                 if (sc->ctx_pages == 0)
3606                         sc->ctx_pages = 1;
3607
3608                 DBRUNIF((sc->ctx_pages > 512),
3609                     BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n",
3610                     __FILE__, __LINE__, sc->ctx_pages));
3611
3612                 /*
3613                  * Create a DMA tag for the context pages,
3614                  * allocate and clear the memory, map the
3615                  * memory into DMA space, and fetch the
3616                  * physical address of the block.
3617                  */
3618                 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3619                     BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3620                     NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
3621                     0, NULL, NULL, &sc->ctx_tag)) {
3622                         BCE_PRINTF("%s(%d): Could not allocate CTX "
3623                             "DMA tag!\n", __FILE__, __LINE__);
3624                         rc = ENOMEM;
3625                         goto bce_dma_alloc_exit;
3626                 }
3627
3628                 for (i = 0; i < sc->ctx_pages; i++) {
3629
3630                         if(bus_dmamem_alloc(sc->ctx_tag,
3631                             (void **)&sc->ctx_block[i],
3632                             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3633                             &sc->ctx_map[i])) {
3634                                 BCE_PRINTF("%s(%d): Could not allocate CTX "
3635                                     "DMA memory!\n", __FILE__, __LINE__);
3636                                 rc = ENOMEM;
3637                                 goto bce_dma_alloc_exit;
3638                         }
3639
3640                         error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
3641                             sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr,
3642                             &sc->ctx_paddr[i], BUS_DMA_NOWAIT);
3643
3644                         if (error || sc->ctx_paddr[i] == 0) {
3645                                 BCE_PRINTF("%s(%d): Could not map CTX "
3646                                     "DMA memory!\n", __FILE__, __LINE__);
3647                                 rc = ENOMEM;
3648                                 goto bce_dma_alloc_exit;
3649                         }
3650
3651                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] "
3652                             "= 0x%jX\n", __FUNCTION__, i,
3653                             (uintmax_t) sc->ctx_paddr[i]);
3654                 }
3655         }
3656
3657         /*
3658          * Create a DMA tag for the TX buffer descriptor chain,
3659          * allocate and clear the  memory, and fetch the
3660          * physical address of the block.
3661          */
3662         if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY,
3663             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3664             BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0,
3665             NULL, NULL, &sc->tx_bd_chain_tag)) {
3666                 BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3667                     "chain DMA tag!\n", __FILE__, __LINE__);
3668                 rc = ENOMEM;
3669                 goto bce_dma_alloc_exit;
3670         }
3671
3672         for (i = 0; i < sc->tx_pages; i++) {
3673
3674                 if(bus_dmamem_alloc(sc->tx_bd_chain_tag,
3675                     (void **)&sc->tx_bd_chain[i],
3676                     BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3677                     &sc->tx_bd_chain_map[i])) {
3678                         BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3679                             "chain DMA memory!\n", __FILE__, __LINE__);
3680                         rc = ENOMEM;
3681                         goto bce_dma_alloc_exit;
3682                 }
3683
3684                 error = bus_dmamap_load(sc->tx_bd_chain_tag,
3685                     sc->tx_bd_chain_map[i], sc->tx_bd_chain[i],
3686                     BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3687                     &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3688
3689                 if (error || sc->tx_bd_chain_paddr[i] == 0) {
3690                         BCE_PRINTF("%s(%d): Could not map TX descriptor "
3691                             "chain DMA memory!\n", __FILE__, __LINE__);
3692                         rc = ENOMEM;
3693                         goto bce_dma_alloc_exit;
3694                 }
3695
3696                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = "
3697                     "0x%jX\n", __FUNCTION__, i,
3698                     (uintmax_t) sc->tx_bd_chain_paddr[i]);
3699         }
3700
3701         /* Check the required size before mapping to conserve resources. */
3702         if (bce_tso_enable) {
3703                 max_size     = BCE_TSO_MAX_SIZE;
3704                 max_segments = BCE_MAX_SEGMENTS;
3705                 max_seg_size = BCE_TSO_MAX_SEG_SIZE;
3706         } else {
3707                 max_size     = MCLBYTES * BCE_MAX_SEGMENTS;
3708                 max_segments = BCE_MAX_SEGMENTS;
3709                 max_seg_size = MCLBYTES;
3710         }
3711
3712         /* Create a DMA tag for TX mbufs. */
3713         if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3714             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size,
3715             max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) {
3716                 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n",
3717                     __FILE__, __LINE__);
3718                 rc = ENOMEM;
3719                 goto bce_dma_alloc_exit;
3720         }
3721
3722         /* Create DMA maps for the TX mbufs clusters. */
3723         for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) {
3724                 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT,
3725                         &sc->tx_mbuf_map[i])) {
3726                         BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA "
3727                             "map!\n", __FILE__, __LINE__);
3728                         rc = ENOMEM;
3729                         goto bce_dma_alloc_exit;
3730                 }
3731         }
3732
3733         /*
3734          * Create a DMA tag for the RX buffer descriptor chain,
3735          * allocate and clear the memory, and fetch the physical
3736          * address of the blocks.
3737          */
3738         if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3739                         BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR,
3740                         sc->max_bus_addr, NULL, NULL,
3741                         BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
3742                         0, NULL, NULL, &sc->rx_bd_chain_tag)) {
3743                 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain "
3744                     "DMA tag!\n", __FILE__, __LINE__);
3745                 rc = ENOMEM;
3746                 goto bce_dma_alloc_exit;
3747         }
3748
3749         for (i = 0; i < sc->rx_pages; i++) {
3750
3751                 if (bus_dmamem_alloc(sc->rx_bd_chain_tag,
3752                     (void **)&sc->rx_bd_chain[i],
3753                     BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3754                     &sc->rx_bd_chain_map[i])) {
3755                         BCE_PRINTF("%s(%d): Could not allocate RX descriptor "
3756                             "chain DMA memory!\n", __FILE__, __LINE__);
3757                         rc = ENOMEM;
3758                         goto bce_dma_alloc_exit;
3759                 }
3760
3761                 error = bus_dmamap_load(sc->rx_bd_chain_tag,
3762                     sc->rx_bd_chain_map[i], sc->rx_bd_chain[i],
3763                     BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3764                     &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3765
3766                 if (error || sc->rx_bd_chain_paddr[i] == 0) {
3767                         BCE_PRINTF("%s(%d): Could not map RX descriptor "
3768                             "chain DMA memory!\n", __FILE__, __LINE__);
3769                         rc = ENOMEM;
3770                         goto bce_dma_alloc_exit;
3771                 }
3772
3773                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = "
3774                     "0x%jX\n", __FUNCTION__, i,
3775                     (uintmax_t) sc->rx_bd_chain_paddr[i]);
3776         }
3777
3778         /*
3779          * Create a DMA tag for RX mbufs.
3780          */
3781         if (bce_hdr_split == TRUE)
3782                 max_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ?
3783                     MCLBYTES : sc->rx_bd_mbuf_alloc_size);
3784         else
3785                 max_size = MJUM9BYTES;
3786
3787         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag "
3788             "(max size = 0x%jX)\n", __FUNCTION__, (uintmax_t)max_size);
3789
3790         if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN,
3791             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3792             max_size, 1, max_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) {
3793                 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n",
3794                     __FILE__, __LINE__);
3795                 rc = ENOMEM;
3796                 goto bce_dma_alloc_exit;
3797         }
3798
3799         /* Create DMA maps for the RX mbuf clusters. */
3800         for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) {
3801                 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT,
3802                     &sc->rx_mbuf_map[i])) {
3803                         BCE_PRINTF("%s(%d): Unable to create RX mbuf "
3804                             "DMA map!\n", __FILE__, __LINE__);
3805                         rc = ENOMEM;
3806                         goto bce_dma_alloc_exit;
3807                 }
3808         }
3809
3810         if (bce_hdr_split == TRUE) {
3811                 /*
3812                  * Create a DMA tag for the page buffer descriptor chain,
3813                  * allocate and clear the memory, and fetch the physical
3814                  * address of the blocks.
3815                  */
3816                 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3817                             BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr,
3818                             NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ,
3819                             0, NULL, NULL, &sc->pg_bd_chain_tag)) {
3820                         BCE_PRINTF("%s(%d): Could not allocate page descriptor "
3821                             "chain DMA tag!\n", __FILE__, __LINE__);
3822                         rc = ENOMEM;
3823                         goto bce_dma_alloc_exit;
3824                 }
3825
3826                 for (i = 0; i < sc->pg_pages; i++) {
3827                         if (bus_dmamem_alloc(sc->pg_bd_chain_tag,
3828                             (void **)&sc->pg_bd_chain[i],
3829                             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3830                             &sc->pg_bd_chain_map[i])) {
3831                                 BCE_PRINTF("%s(%d): Could not allocate page "
3832                                     "descriptor chain DMA memory!\n",
3833                                     __FILE__, __LINE__);
3834                                 rc = ENOMEM;
3835                                 goto bce_dma_alloc_exit;
3836                         }
3837
3838                         error = bus_dmamap_load(sc->pg_bd_chain_tag,
3839                             sc->pg_bd_chain_map[i], sc->pg_bd_chain[i],
3840                             BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr,
3841                             &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3842
3843                         if (error || sc->pg_bd_chain_paddr[i] == 0) {
3844                                 BCE_PRINTF("%s(%d): Could not map page descriptor "
3845                                         "chain DMA memory!\n", __FILE__, __LINE__);
3846                                 rc = ENOMEM;
3847                                 goto bce_dma_alloc_exit;
3848                         }
3849
3850                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = "
3851                                 "0x%jX\n", __FUNCTION__, i,
3852                                 (uintmax_t) sc->pg_bd_chain_paddr[i]);
3853                 }
3854
3855                 /*
3856                  * Create a DMA tag for page mbufs.
3857                  */
3858                 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3859                     sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
3860                     1, MCLBYTES, 0, NULL, NULL, &sc->pg_mbuf_tag)) {
3861                         BCE_PRINTF("%s(%d): Could not allocate page mbuf "
3862                                 "DMA tag!\n", __FILE__, __LINE__);
3863                         rc = ENOMEM;
3864                         goto bce_dma_alloc_exit;
3865                 }
3866
3867                 /* Create DMA maps for the page mbuf clusters. */
3868                 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) {
3869                         if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT,
3870                                 &sc->pg_mbuf_map[i])) {
3871                                 BCE_PRINTF("%s(%d): Unable to create page mbuf "
3872                                         "DMA map!\n", __FILE__, __LINE__);
3873                                 rc = ENOMEM;
3874                                 goto bce_dma_alloc_exit;
3875                         }
3876                 }
3877         }
3878
3879 bce_dma_alloc_exit:
3880         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3881         return(rc);
3882 }
3883
3884
3885 /****************************************************************************/
3886 /* Release all resources used by the driver.                                */
3887 /*                                                                          */
3888 /* Releases all resources acquired by the driver including interrupts,      */
3889 /* interrupt handler, interfaces, mutexes, and DMA memory.                  */
3890 /*                                                                          */
3891 /* Returns:                                                                 */
3892 /*   Nothing.                                                               */
3893 /****************************************************************************/
3894 static void
3895 bce_release_resources(struct bce_softc *sc)
3896 {
3897         device_t dev;
3898
3899         DBENTER(BCE_VERBOSE_RESET);
3900
3901         dev = sc->bce_dev;
3902
3903         bce_dma_free(sc);
3904
3905         if (sc->bce_intrhand != NULL) {
3906                 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n");
3907                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
3908         }
3909
3910         if (sc->bce_res_irq != NULL) {
3911                 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n");
3912                 bus_release_resource(dev, SYS_RES_IRQ,
3913                     rman_get_rid(sc->bce_res_irq), sc->bce_res_irq);
3914         }
3915
3916         if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) {
3917                 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n");
3918                 pci_release_msi(dev);
3919         }
3920
3921         if (sc->bce_res_mem != NULL) {
3922                 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n");
3923                     bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
3924                     sc->bce_res_mem);
3925         }
3926
3927         if (sc->bce_ifp != NULL) {
3928                 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n");
3929                 if_free(sc->bce_ifp);
3930         }
3931
3932         if (mtx_initialized(&sc->bce_mtx))
3933                 BCE_LOCK_DESTROY(sc);
3934
3935         DBEXIT(BCE_VERBOSE_RESET);
3936 }
3937
3938
3939 /****************************************************************************/
3940 /* Firmware synchronization.                                                */
3941 /*                                                                          */
3942 /* Before performing certain events such as a chip reset, synchronize with  */
3943 /* the firmware first.                                                      */
3944 /*                                                                          */
3945 /* Returns:                                                                 */
3946 /*   0 for success, positive value for failure.                             */
3947 /****************************************************************************/
3948 static int
3949 bce_fw_sync(struct bce_softc *sc, u32 msg_data)
3950 {
3951         int i, rc = 0;
3952         u32 val;
3953
3954         DBENTER(BCE_VERBOSE_RESET);
3955
3956         /* Don't waste any time if we've timed out before. */
3957         if (sc->bce_fw_timed_out == TRUE) {
3958                 rc = EBUSY;
3959                 goto bce_fw_sync_exit;
3960         }
3961
3962         /* Increment the message sequence number. */
3963         sc->bce_fw_wr_seq++;
3964         msg_data |= sc->bce_fw_wr_seq;
3965
3966         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = "
3967             "0x%08X\n", msg_data);
3968
3969         /* Send the message to the bootcode driver mailbox. */
3970         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
3971
3972         /* Wait for the bootcode to acknowledge the message. */
3973         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
3974                 /* Check for a response in the bootcode firmware mailbox. */
3975                 val = bce_shmem_rd(sc, BCE_FW_MB);
3976                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
3977                         break;
3978                 DELAY(1000);
3979         }
3980
3981         /* If we've timed out, tell bootcode that we've stopped waiting. */
3982         if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) &&
3983             ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) {
3984
3985                 BCE_PRINTF("%s(%d): Firmware synchronization timeout! "
3986                     "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data);
3987
3988                 msg_data &= ~BCE_DRV_MSG_CODE;
3989                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
3990
3991                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
3992
3993                 sc->bce_fw_timed_out = TRUE;
3994                 rc = EBUSY;
3995         }
3996
3997 bce_fw_sync_exit:
3998         DBEXIT(BCE_VERBOSE_RESET);
3999         return (rc);
4000 }
4001
4002
4003 /****************************************************************************/
4004 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
4005 /*                                                                          */
4006 /* Returns:                                                                 */
4007 /*   Nothing.                                                               */
4008 /****************************************************************************/
4009 static void
4010 bce_load_rv2p_fw(struct bce_softc *sc, const u32 *rv2p_code,
4011         u32 rv2p_code_len, u32 rv2p_proc)
4012 {
4013         int i;
4014         u32 val;
4015
4016         DBENTER(BCE_VERBOSE_RESET);
4017
4018         /* Set the page size used by RV2P. */
4019         if (rv2p_proc == RV2P_PROC2) {
4020                 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE);
4021         }
4022
4023         for (i = 0; i < rv2p_code_len; i += 8) {
4024                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
4025                 rv2p_code++;
4026                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
4027                 rv2p_code++;
4028
4029                 if (rv2p_proc == RV2P_PROC1) {
4030                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
4031                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
4032                 }
4033                 else {
4034                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
4035                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
4036                 }
4037         }
4038
4039         /* Reset the processor, un-stall is done later. */
4040         if (rv2p_proc == RV2P_PROC1) {
4041                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
4042         }
4043         else {
4044                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
4045         }
4046
4047         DBEXIT(BCE_VERBOSE_RESET);
4048 }
4049
4050
4051 /****************************************************************************/
4052 /* Load RISC processor firmware.                                            */
4053 /*                                                                          */
4054 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
4055 /* associated with a particular processor.                                  */
4056 /*                                                                          */
4057 /* Returns:                                                                 */
4058 /*   Nothing.                                                               */
4059 /****************************************************************************/
4060 static void
4061 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
4062         struct fw_info *fw)
4063 {
4064         u32 offset;
4065
4066         DBENTER(BCE_VERBOSE_RESET);
4067
4068     bce_halt_cpu(sc, cpu_reg);
4069
4070         /* Load the Text area. */
4071         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
4072         if (fw->text) {
4073                 int j;
4074
4075                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
4076                         REG_WR_IND(sc, offset, fw->text[j]);
4077                 }
4078         }
4079
4080         /* Load the Data area. */
4081         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
4082         if (fw->data) {
4083                 int j;
4084
4085                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
4086                         REG_WR_IND(sc, offset, fw->data[j]);
4087                 }
4088         }
4089
4090         /* Load the SBSS area. */
4091         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
4092         if (fw->sbss) {
4093                 int j;
4094
4095                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
4096                         REG_WR_IND(sc, offset, fw->sbss[j]);
4097                 }
4098         }
4099
4100         /* Load the BSS area. */
4101         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
4102         if (fw->bss) {
4103                 int j;
4104
4105                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
4106                         REG_WR_IND(sc, offset, fw->bss[j]);
4107                 }
4108         }
4109
4110         /* Load the Read-Only area. */
4111         offset = cpu_reg->spad_base +
4112                 (fw->rodata_addr - cpu_reg->mips_view_base);
4113         if (fw->rodata) {
4114                 int j;
4115
4116                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
4117                         REG_WR_IND(sc, offset, fw->rodata[j]);
4118                 }
4119         }
4120
4121         /* Clear the pre-fetch instruction and set the FW start address. */
4122         REG_WR_IND(sc, cpu_reg->inst, 0);
4123         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
4124
4125         DBEXIT(BCE_VERBOSE_RESET);
4126 }
4127
4128
4129 /****************************************************************************/
4130 /* Starts the RISC processor.                                               */
4131 /*                                                                          */
4132 /* Assumes the CPU starting address has already been set.                   */
4133 /*                                                                          */
4134 /* Returns:                                                                 */
4135 /*   Nothing.                                                               */
4136 /****************************************************************************/
4137 static void
4138 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4139 {
4140         u32 val;
4141
4142         DBENTER(BCE_VERBOSE_RESET);
4143
4144         /* Start the CPU. */
4145         val = REG_RD_IND(sc, cpu_reg->mode);
4146         val &= ~cpu_reg->mode_value_halt;
4147         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4148         REG_WR_IND(sc, cpu_reg->mode, val);
4149
4150         DBEXIT(BCE_VERBOSE_RESET);
4151 }
4152
4153
4154 /****************************************************************************/
4155 /* Halts the RISC processor.                                                */
4156 /*                                                                          */
4157 /* Returns:                                                                 */
4158 /*   Nothing.                                                               */
4159 /****************************************************************************/
4160 static void
4161 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4162 {
4163         u32 val;
4164
4165         DBENTER(BCE_VERBOSE_RESET);
4166
4167         /* Halt the CPU. */
4168         val = REG_RD_IND(sc, cpu_reg->mode);
4169         val |= cpu_reg->mode_value_halt;
4170         REG_WR_IND(sc, cpu_reg->mode, val);
4171         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4172
4173         DBEXIT(BCE_VERBOSE_RESET);
4174 }
4175
4176
4177 /****************************************************************************/
4178 /* Initialize the RX CPU.                                                   */
4179 /*                                                                          */
4180 /* Returns:                                                                 */
4181 /*   Nothing.                                                               */
4182 /****************************************************************************/
4183 static void
4184 bce_start_rxp_cpu(struct bce_softc *sc)
4185 {
4186         struct cpu_reg cpu_reg;
4187
4188         DBENTER(BCE_VERBOSE_RESET);
4189
4190         cpu_reg.mode = BCE_RXP_CPU_MODE;
4191         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4192         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4193         cpu_reg.state = BCE_RXP_CPU_STATE;
4194         cpu_reg.state_value_clear = 0xffffff;
4195         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4196         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4197         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4198         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4199         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4200         cpu_reg.spad_base = BCE_RXP_SCRATCH;
4201         cpu_reg.mips_view_base = 0x8000000;
4202
4203         DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n");
4204         bce_start_cpu(sc, &cpu_reg);
4205
4206         DBEXIT(BCE_VERBOSE_RESET);
4207 }
4208
4209
4210 /****************************************************************************/
4211 /* Initialize the RX CPU.                                                   */
4212 /*                                                                          */
4213 /* Returns:                                                                 */
4214 /*   Nothing.                                                               */
4215 /****************************************************************************/
4216 static void
4217 bce_init_rxp_cpu(struct bce_softc *sc)
4218 {
4219         struct cpu_reg cpu_reg;
4220         struct fw_info fw;
4221
4222         DBENTER(BCE_VERBOSE_RESET);
4223
4224         cpu_reg.mode = BCE_RXP_CPU_MODE;
4225         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4226         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4227         cpu_reg.state = BCE_RXP_CPU_STATE;
4228         cpu_reg.state_value_clear = 0xffffff;
4229         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4230         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4231         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4232         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4233         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4234         cpu_reg.spad_base = BCE_RXP_SCRATCH;
4235         cpu_reg.mips_view_base = 0x8000000;
4236
4237         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4238                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
4239                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
4240                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
4241                 fw.start_addr = bce_RXP_b09FwStartAddr;
4242
4243                 fw.text_addr = bce_RXP_b09FwTextAddr;
4244                 fw.text_len = bce_RXP_b09FwTextLen;
4245                 fw.text_index = 0;
4246                 fw.text = bce_RXP_b09FwText;
4247
4248                 fw.data_addr = bce_RXP_b09FwDataAddr;
4249                 fw.data_len = bce_RXP_b09FwDataLen;
4250                 fw.data_index = 0;
4251                 fw.data = bce_RXP_b09FwData;
4252
4253                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
4254                 fw.sbss_len = bce_RXP_b09FwSbssLen;
4255                 fw.sbss_index = 0;
4256                 fw.sbss = bce_RXP_b09FwSbss;
4257
4258                 fw.bss_addr = bce_RXP_b09FwBssAddr;
4259                 fw.bss_len = bce_RXP_b09FwBssLen;
4260                 fw.bss_index = 0;
4261                 fw.bss = bce_RXP_b09FwBss;
4262
4263                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
4264                 fw.rodata_len = bce_RXP_b09FwRodataLen;
4265                 fw.rodata_index = 0;
4266                 fw.rodata = bce_RXP_b09FwRodata;
4267         } else {
4268                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
4269                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
4270                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
4271                 fw.start_addr = bce_RXP_b06FwStartAddr;
4272
4273                 fw.text_addr = bce_RXP_b06FwTextAddr;
4274                 fw.text_len = bce_RXP_b06FwTextLen;
4275                 fw.text_index = 0;
4276                 fw.text = bce_RXP_b06FwText;
4277
4278                 fw.data_addr = bce_RXP_b06FwDataAddr;
4279                 fw.data_len = bce_RXP_b06FwDataLen;
4280                 fw.data_index = 0;
4281                 fw.data = bce_RXP_b06FwData;
4282
4283                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
4284                 fw.sbss_len = bce_RXP_b06FwSbssLen;
4285                 fw.sbss_index = 0;
4286                 fw.sbss = bce_RXP_b06FwSbss;
4287
4288                 fw.bss_addr = bce_RXP_b06FwBssAddr;
4289                 fw.bss_len = bce_RXP_b06FwBssLen;
4290                 fw.bss_index = 0;
4291                 fw.bss = bce_RXP_b06FwBss;
4292
4293                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
4294                 fw.rodata_len = bce_RXP_b06FwRodataLen;
4295                 fw.rodata_index = 0;
4296                 fw.rodata = bce_RXP_b06FwRodata;
4297         }
4298
4299         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
4300         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4301
4302     /* Delay RXP start until initialization is complete. */
4303
4304         DBEXIT(BCE_VERBOSE_RESET);
4305 }
4306
4307
4308 /****************************************************************************/
4309 /* Initialize the TX CPU.                                                   */
4310 /*                                                                          */
4311 /* Returns:                                                                 */
4312 /*   Nothing.                                                               */
4313 /****************************************************************************/
4314 static void
4315 bce_init_txp_cpu(struct bce_softc *sc)
4316 {
4317         struct cpu_reg cpu_reg;
4318         struct fw_info fw;
4319
4320         DBENTER(BCE_VERBOSE_RESET);
4321
4322         cpu_reg.mode = BCE_TXP_CPU_MODE;
4323         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
4324         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
4325         cpu_reg.state = BCE_TXP_CPU_STATE;
4326         cpu_reg.state_value_clear = 0xffffff;
4327         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
4328         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
4329         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
4330         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
4331         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
4332         cpu_reg.spad_base = BCE_TXP_SCRATCH;
4333         cpu_reg.mips_view_base = 0x8000000;
4334
4335         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4336                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
4337                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
4338                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
4339                 fw.start_addr = bce_TXP_b09FwStartAddr;
4340
4341                 fw.text_addr = bce_TXP_b09FwTextAddr;
4342                 fw.text_len = bce_TXP_b09FwTextLen;
4343                 fw.text_index = 0;
4344                 fw.text = bce_TXP_b09FwText;
4345
4346                 fw.data_addr = bce_TXP_b09FwDataAddr;
4347                 fw.data_len = bce_TXP_b09FwDataLen;
4348                 fw.data_index = 0;
4349                 fw.data = bce_TXP_b09FwData;
4350
4351                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
4352                 fw.sbss_len = bce_TXP_b09FwSbssLen;
4353                 fw.sbss_index = 0;
4354                 fw.sbss = bce_TXP_b09FwSbss;
4355
4356                 fw.bss_addr = bce_TXP_b09FwBssAddr;
4357                 fw.bss_len = bce_TXP_b09FwBssLen;
4358                 fw.bss_index = 0;
4359                 fw.bss = bce_TXP_b09FwBss;
4360
4361                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
4362                 fw.rodata_len = bce_TXP_b09FwRodataLen;
4363                 fw.rodata_index = 0;
4364                 fw.rodata = bce_TXP_b09FwRodata;
4365         } else {
4366                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
4367                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
4368                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
4369                 fw.start_addr = bce_TXP_b06FwStartAddr;
4370
4371                 fw.text_addr = bce_TXP_b06FwTextAddr;
4372                 fw.text_len = bce_TXP_b06FwTextLen;
4373                 fw.text_index = 0;
4374                 fw.text = bce_TXP_b06FwText;
4375
4376                 fw.data_addr = bce_TXP_b06FwDataAddr;
4377                 fw.data_len = bce_TXP_b06FwDataLen;
4378                 fw.data_index = 0;
4379                 fw.data = bce_TXP_b06FwData;
4380
4381                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
4382                 fw.sbss_len = bce_TXP_b06FwSbssLen;
4383                 fw.sbss_index = 0;
4384                 fw.sbss = bce_TXP_b06FwSbss;
4385
4386                 fw.bss_addr = bce_TXP_b06FwBssAddr;
4387                 fw.bss_len = bce_TXP_b06FwBssLen;
4388                 fw.bss_index = 0;
4389                 fw.bss = bce_TXP_b06FwBss;
4390
4391                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
4392                 fw.rodata_len = bce_TXP_b06FwRodataLen;
4393                 fw.rodata_index = 0;
4394                 fw.rodata = bce_TXP_b06FwRodata;
4395         }
4396
4397         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
4398         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4399     bce_start_cpu(sc, &cpu_reg);
4400
4401         DBEXIT(BCE_VERBOSE_RESET);
4402 }
4403
4404
4405 /****************************************************************************/
4406 /* Initialize the TPAT CPU.                                                 */
4407 /*                                                                          */
4408 /* Returns:                                                                 */
4409 /*   Nothing.                                                               */
4410 /****************************************************************************/
4411 static void
4412 bce_init_tpat_cpu(struct bce_softc *sc)
4413 {
4414         struct cpu_reg cpu_reg;
4415         struct fw_info fw;
4416
4417         DBENTER(BCE_VERBOSE_RESET);
4418
4419         cpu_reg.mode = BCE_TPAT_CPU_MODE;
4420         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
4421         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
4422         cpu_reg.state = BCE_TPAT_CPU_STATE;
4423         cpu_reg.state_value_clear = 0xffffff;
4424         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
4425         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
4426         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
4427         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
4428         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
4429         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
4430         cpu_reg.mips_view_base = 0x8000000;
4431
4432         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4433                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
4434                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
4435                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
4436                 fw.start_addr = bce_TPAT_b09FwStartAddr;
4437
4438                 fw.text_addr = bce_TPAT_b09FwTextAddr;
4439                 fw.text_len = bce_TPAT_b09FwTextLen;
4440                 fw.text_index = 0;
4441                 fw.text = bce_TPAT_b09FwText;
4442
4443                 fw.data_addr = bce_TPAT_b09FwDataAddr;
4444                 fw.data_len = bce_TPAT_b09FwDataLen;
4445                 fw.data_index = 0;
4446                 fw.data = bce_TPAT_b09FwData;
4447
4448                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
4449                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
4450                 fw.sbss_index = 0;
4451                 fw.sbss = bce_TPAT_b09FwSbss;
4452
4453                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
4454                 fw.bss_len = bce_TPAT_b09FwBssLen;
4455                 fw.bss_index = 0;
4456                 fw.bss = bce_TPAT_b09FwBss;
4457
4458                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
4459                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
4460                 fw.rodata_index = 0;
4461                 fw.rodata = bce_TPAT_b09FwRodata;
4462         } else {
4463                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
4464                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
4465                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
4466                 fw.start_addr = bce_TPAT_b06FwStartAddr;
4467
4468                 fw.text_addr = bce_TPAT_b06FwTextAddr;
4469                 fw.text_len = bce_TPAT_b06FwTextLen;
4470                 fw.text_index = 0;
4471                 fw.text = bce_TPAT_b06FwText;
4472
4473                 fw.data_addr = bce_TPAT_b06FwDataAddr;
4474                 fw.data_len = bce_TPAT_b06FwDataLen;
4475                 fw.data_index = 0;
4476                 fw.data = bce_TPAT_b06FwData;
4477
4478                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
4479                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
4480                 fw.sbss_index = 0;
4481                 fw.sbss = bce_TPAT_b06FwSbss;
4482
4483                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
4484                 fw.bss_len = bce_TPAT_b06FwBssLen;
4485                 fw.bss_index = 0;
4486                 fw.bss = bce_TPAT_b06FwBss;
4487
4488                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
4489                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
4490                 fw.rodata_index = 0;
4491                 fw.rodata = bce_TPAT_b06FwRodata;
4492         }
4493
4494         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
4495         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4496         bce_start_cpu(sc, &cpu_reg);
4497
4498         DBEXIT(BCE_VERBOSE_RESET);
4499 }
4500
4501
4502 /****************************************************************************/
4503 /* Initialize the CP CPU.                                                   */
4504 /*                                                                          */
4505 /* Returns:                                                                 */
4506 /*   Nothing.                                                               */
4507 /****************************************************************************/
4508 static void
4509 bce_init_cp_cpu(struct bce_softc *sc)
4510 {
4511         struct cpu_reg cpu_reg;
4512         struct fw_info fw;
4513
4514         DBENTER(BCE_VERBOSE_RESET);
4515
4516         cpu_reg.mode = BCE_CP_CPU_MODE;
4517         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
4518         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
4519         cpu_reg.state = BCE_CP_CPU_STATE;
4520         cpu_reg.state_value_clear = 0xffffff;
4521         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
4522         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
4523         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
4524         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
4525         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
4526         cpu_reg.spad_base = BCE_CP_SCRATCH;
4527         cpu_reg.mips_view_base = 0x8000000;
4528
4529         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4530                 fw.ver_major = bce_CP_b09FwReleaseMajor;
4531                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
4532                 fw.ver_fix = bce_CP_b09FwReleaseFix;
4533                 fw.start_addr = bce_CP_b09FwStartAddr;
4534
4535                 fw.text_addr = bce_CP_b09FwTextAddr;
4536                 fw.text_len = bce_CP_b09FwTextLen;
4537                 fw.text_index = 0;
4538                 fw.text = bce_CP_b09FwText;
4539
4540                 fw.data_addr = bce_CP_b09FwDataAddr;
4541                 fw.data_len = bce_CP_b09FwDataLen;
4542                 fw.data_index = 0;
4543                 fw.data = bce_CP_b09FwData;
4544
4545                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
4546                 fw.sbss_len = bce_CP_b09FwSbssLen;
4547                 fw.sbss_index = 0;
4548                 fw.sbss = bce_CP_b09FwSbss;
4549
4550                 fw.bss_addr = bce_CP_b09FwBssAddr;
4551                 fw.bss_len = bce_CP_b09FwBssLen;
4552                 fw.bss_index = 0;
4553                 fw.bss = bce_CP_b09FwBss;
4554
4555                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
4556                 fw.rodata_len = bce_CP_b09FwRodataLen;
4557                 fw.rodata_index = 0;
4558                 fw.rodata = bce_CP_b09FwRodata;
4559         } else {
4560                 fw.ver_major = bce_CP_b06FwReleaseMajor;
4561                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
4562                 fw.ver_fix = bce_CP_b06FwReleaseFix;
4563                 fw.start_addr = bce_CP_b06FwStartAddr;
4564
4565                 fw.text_addr = bce_CP_b06FwTextAddr;
4566                 fw.text_len = bce_CP_b06FwTextLen;
4567                 fw.text_index = 0;
4568                 fw.text = bce_CP_b06FwText;
4569
4570                 fw.data_addr = bce_CP_b06FwDataAddr;
4571                 fw.data_len = bce_CP_b06FwDataLen;
4572                 fw.data_index = 0;
4573                 fw.data = bce_CP_b06FwData;
4574
4575                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
4576                 fw.sbss_len = bce_CP_b06FwSbssLen;
4577                 fw.sbss_index = 0;
4578                 fw.sbss = bce_CP_b06FwSbss;
4579
4580                 fw.bss_addr = bce_CP_b06FwBssAddr;
4581                 fw.bss_len = bce_CP_b06FwBssLen;
4582                 fw.bss_index = 0;
4583                 fw.bss = bce_CP_b06FwBss;
4584
4585                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
4586                 fw.rodata_len = bce_CP_b06FwRodataLen;
4587                 fw.rodata_index = 0;
4588                 fw.rodata = bce_CP_b06FwRodata;
4589         }
4590
4591         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
4592         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4593         bce_start_cpu(sc, &cpu_reg);
4594
4595         DBEXIT(BCE_VERBOSE_RESET);
4596 }
4597
4598
4599 /****************************************************************************/
4600 /* Initialize the COM CPU.                                                 */
4601 /*                                                                          */
4602 /* Returns:                                                                 */
4603 /*   Nothing.                                                               */
4604 /****************************************************************************/
4605 static void
4606 bce_init_com_cpu(struct bce_softc *sc)
4607 {
4608         struct cpu_reg cpu_reg;
4609         struct fw_info fw;
4610
4611         DBENTER(BCE_VERBOSE_RESET);
4612
4613         cpu_reg.mode = BCE_COM_CPU_MODE;
4614         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
4615         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
4616         cpu_reg.state = BCE_COM_CPU_STATE;
4617         cpu_reg.state_value_clear = 0xffffff;
4618         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
4619         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
4620         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
4621         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
4622         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
4623         cpu_reg.spad_base = BCE_COM_SCRATCH;
4624         cpu_reg.mips_view_base = 0x8000000;
4625
4626         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4627                 fw.ver_major = bce_COM_b09FwReleaseMajor;
4628                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
4629                 fw.ver_fix = bce_COM_b09FwReleaseFix;
4630                 fw.start_addr = bce_COM_b09FwStartAddr;
4631
4632                 fw.text_addr = bce_COM_b09FwTextAddr;
4633                 fw.text_len = bce_COM_b09FwTextLen;
4634                 fw.text_index = 0;
4635                 fw.text = bce_COM_b09FwText;
4636
4637                 fw.data_addr = bce_COM_b09FwDataAddr;
4638                 fw.data_len = bce_COM_b09FwDataLen;
4639                 fw.data_index = 0;
4640                 fw.data = bce_COM_b09FwData;
4641
4642                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
4643                 fw.sbss_len = bce_COM_b09FwSbssLen;
4644                 fw.sbss_index = 0;
4645                 fw.sbss = bce_COM_b09FwSbss;
4646
4647                 fw.bss_addr = bce_COM_b09FwBssAddr;
4648                 fw.bss_len = bce_COM_b09FwBssLen;
4649                 fw.bss_index = 0;
4650                 fw.bss = bce_COM_b09FwBss;
4651
4652                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
4653                 fw.rodata_len = bce_COM_b09FwRodataLen;
4654                 fw.rodata_index = 0;
4655                 fw.rodata = bce_COM_b09FwRodata;
4656         } else {
4657                 fw.ver_major = bce_COM_b06FwReleaseMajor;
4658                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
4659                 fw.ver_fix = bce_COM_b06FwReleaseFix;
4660                 fw.start_addr = bce_COM_b06FwStartAddr;
4661
4662                 fw.text_addr = bce_COM_b06FwTextAddr;
4663                 fw.text_len = bce_COM_b06FwTextLen;
4664                 fw.text_index = 0;
4665                 fw.text = bce_COM_b06FwText;
4666
4667                 fw.data_addr = bce_COM_b06FwDataAddr;
4668                 fw.data_len = bce_COM_b06FwDataLen;
4669                 fw.data_index = 0;
4670                 fw.data = bce_COM_b06FwData;
4671
4672                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
4673                 fw.sbss_len = bce_COM_b06FwSbssLen;
4674                 fw.sbss_index = 0;
4675                 fw.sbss = bce_COM_b06FwSbss;
4676
4677                 fw.bss_addr = bce_COM_b06FwBssAddr;
4678                 fw.bss_len = bce_COM_b06FwBssLen;
4679                 fw.bss_index = 0;
4680                 fw.bss = bce_COM_b06FwBss;
4681
4682                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
4683                 fw.rodata_len = bce_COM_b06FwRodataLen;
4684                 fw.rodata_index = 0;
4685                 fw.rodata = bce_COM_b06FwRodata;
4686         }
4687
4688         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
4689         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4690         bce_start_cpu(sc, &cpu_reg);
4691
4692         DBEXIT(BCE_VERBOSE_RESET);
4693 }
4694
4695
4696 /****************************************************************************/
4697 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
4698 /*                                                                          */
4699 /* Loads the firmware for each CPU and starts the CPU.                      */
4700 /*                                                                          */
4701 /* Returns:                                                                 */
4702 /*   Nothing.                                                               */
4703 /****************************************************************************/
4704 static void
4705 bce_init_cpus(struct bce_softc *sc)
4706 {
4707         DBENTER(BCE_VERBOSE_RESET);
4708
4709         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4710
4711                 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) {
4712                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
4713                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
4714                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
4715                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
4716                 } else {
4717                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
4718                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
4719                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
4720                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
4721                 }
4722
4723         } else {
4724                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
4725                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
4726                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
4727                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
4728         }
4729
4730         bce_init_rxp_cpu(sc);
4731         bce_init_txp_cpu(sc);
4732         bce_init_tpat_cpu(sc);
4733         bce_init_com_cpu(sc);
4734         bce_init_cp_cpu(sc);
4735
4736         DBEXIT(BCE_VERBOSE_RESET);
4737 }
4738
4739
4740 /****************************************************************************/
4741 /* Initialize context memory.                                               */
4742 /*                                                                          */
4743 /* Clears the memory associated with each Context ID (CID).                 */
4744 /*                                                                          */
4745 /* Returns:                                                                 */
4746 /*   Nothing.                                                               */
4747 /****************************************************************************/
4748 static int
4749 bce_init_ctx(struct bce_softc *sc)
4750 {
4751         u32 offset, val, vcid_addr;
4752         int i, j, rc, retry_cnt;
4753
4754         rc = 0;
4755         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4756
4757         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4758                 retry_cnt = CTX_INIT_RETRY_COUNT;
4759
4760                 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n");
4761
4762                 /*
4763                  * BCM5709 context memory may be cached
4764                  * in host memory so prepare the host memory
4765                  * for access.
4766                  */
4767                 val = BCE_CTX_COMMAND_ENABLED |
4768                     BCE_CTX_COMMAND_MEM_INIT | (1 << 12);
4769                 val |= (BCM_PAGE_BITS - 8) << 16;
4770                 REG_WR(sc, BCE_CTX_COMMAND, val);
4771
4772                 /* Wait for mem init command to complete. */
4773                 for (i = 0; i < retry_cnt; i++) {
4774                         val = REG_RD(sc, BCE_CTX_COMMAND);
4775                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
4776                                 break;
4777                         DELAY(2);
4778                 }
4779                 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) {
4780                         BCE_PRINTF("%s(): Context memory initialization failed!\n",
4781                             __FUNCTION__);
4782                         rc = EBUSY;
4783                         goto init_ctx_fail;
4784                 }
4785
4786                 for (i = 0; i < sc->ctx_pages; i++) {
4787                         /* Set the physical address of the context memory. */
4788                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
4789                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
4790                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
4791                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
4792                             BCE_ADDR_HI(sc->ctx_paddr[i]));
4793                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i |
4794                             BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
4795
4796                         /* Verify the context memory write was successful. */
4797                         for (j = 0; j < retry_cnt; j++) {
4798                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
4799                                 if ((val &
4800                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
4801                                         break;
4802                                 DELAY(5);
4803                         }
4804                         if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) {
4805                                 BCE_PRINTF("%s(): Failed to initialize "
4806                                     "context page %d!\n", __FUNCTION__, i);
4807                                 rc = EBUSY;
4808                                 goto init_ctx_fail;
4809                         }
4810                 }
4811         } else {
4812
4813                 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n");
4814
4815                 /*
4816                  * For the 5706/5708, context memory is local to
4817                  * the controller, so initialize the controller
4818                  * context memory.
4819                  */
4820
4821                 vcid_addr = GET_CID_ADDR(96);
4822                 while (vcid_addr) {
4823
4824                         vcid_addr -= PHY_CTX_SIZE;
4825
4826                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
4827                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4828
4829                         for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
4830                                 CTX_WR(sc, 0x00, offset, 0);
4831                         }
4832
4833                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
4834                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4835                 }
4836
4837         }
4838 init_ctx_fail:
4839         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4840         return (rc);
4841 }
4842
4843
4844 /****************************************************************************/
4845 /* Fetch the permanent MAC address of the controller.                       */
4846 /*                                                                          */
4847 /* Returns:                                                                 */
4848 /*   Nothing.                                                               */
4849 /****************************************************************************/
4850 static void
4851 bce_get_mac_addr(struct bce_softc *sc)
4852 {
4853         u32 mac_lo = 0, mac_hi = 0;
4854
4855         DBENTER(BCE_VERBOSE_RESET);
4856
4857         /*
4858          * The NetXtreme II bootcode populates various NIC
4859          * power-on and runtime configuration items in a
4860          * shared memory area.  The factory configured MAC
4861          * address is available from both NVRAM and the
4862          * shared memory area so we'll read the value from
4863          * shared memory for speed.
4864          */
4865
4866         mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER);
4867         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
4868
4869         if ((mac_lo == 0) && (mac_hi == 0)) {
4870                 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n",
4871                     __FILE__, __LINE__);
4872         } else {
4873                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
4874                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
4875                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
4876                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
4877                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
4878                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
4879         }
4880
4881         DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet "
4882             "address = %6D\n", sc->eaddr, ":");
4883         DBEXIT(BCE_VERBOSE_RESET);
4884 }
4885
4886
4887 /****************************************************************************/
4888 /* Program the MAC address.                                                 */
4889 /*                                                                          */
4890 /* Returns:                                                                 */
4891 /*   Nothing.                                                               */
4892 /****************************************************************************/
4893 static void
4894 bce_set_mac_addr(struct bce_softc *sc)
4895 {
4896         u32 val;
4897         u8 *mac_addr = sc->eaddr;
4898
4899         /* ToDo: Add support for setting multiple MAC addresses. */
4900
4901         DBENTER(BCE_VERBOSE_RESET);
4902         DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = "
4903             "%6D\n", sc->eaddr, ":");
4904
4905         val = (mac_addr[0] << 8) | mac_addr[1];
4906
4907         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
4908
4909         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
4910             (mac_addr[4] << 8) | mac_addr[5];
4911
4912         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
4913
4914         DBEXIT(BCE_VERBOSE_RESET);
4915 }
4916
4917
4918 /****************************************************************************/
4919 /* Stop the controller.                                                     */
4920 /*                                                                          */
4921 /* Returns:                                                                 */
4922 /*   Nothing.                                                               */
4923 /****************************************************************************/
4924 static void
4925 bce_stop(struct bce_softc *sc)
4926 {
4927         struct ifnet *ifp;
4928
4929         DBENTER(BCE_VERBOSE_RESET);
4930
4931         BCE_LOCK_ASSERT(sc);
4932
4933         ifp = sc->bce_ifp;
4934
4935         callout_stop(&sc->bce_tick_callout);
4936
4937         /* Disable the transmit/receive blocks. */
4938         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
4939         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
4940         DELAY(20);
4941
4942         bce_disable_intr(sc);
4943
4944         /* Free RX buffers. */
4945         if (bce_hdr_split == TRUE) {
4946                 bce_free_pg_chain(sc);
4947         }
4948         bce_free_rx_chain(sc);
4949
4950         /* Free TX buffers. */
4951         bce_free_tx_chain(sc);
4952
4953         sc->watchdog_timer = 0;
4954
4955         sc->bce_link_up = FALSE;
4956
4957         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4958
4959         DBEXIT(BCE_VERBOSE_RESET);
4960 }
4961
4962
4963 static int
4964 bce_reset(struct bce_softc *sc, u32 reset_code)
4965 {
4966         u32 emac_mode_save, val;
4967         int i, rc = 0;
4968         static const u32 emac_mode_mask = BCE_EMAC_MODE_PORT |
4969             BCE_EMAC_MODE_HALF_DUPLEX | BCE_EMAC_MODE_25G;
4970
4971         DBENTER(BCE_VERBOSE_RESET);
4972
4973         DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n",
4974             __FUNCTION__, reset_code);
4975
4976         /*
4977          * If ASF/IPMI is operational, then the EMAC Mode register already
4978          * contains appropriate values for the link settings that have
4979          * been auto-negotiated.  Resetting the chip will clobber those
4980          * values.  Save the important bits so we can restore them after
4981          * the reset.
4982          */
4983         emac_mode_save = REG_RD(sc, BCE_EMAC_MODE) & emac_mode_mask;
4984
4985         /* Wait for pending PCI transactions to complete. */
4986         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
4987             BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4988             BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4989             BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4990             BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4991         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
4992         DELAY(5);
4993
4994         /* Disable DMA */
4995         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4996                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
4997                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
4998                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
4999         }
5000
5001         /* Assume bootcode is running. */
5002         sc->bce_fw_timed_out = FALSE;
5003         sc->bce_drv_cardiac_arrest = FALSE;
5004
5005         /* Give the firmware a chance to prepare for the reset. */
5006         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
5007         if (rc)
5008                 goto bce_reset_exit;
5009
5010         /* Set a firmware reminder that this is a soft reset. */
5011         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC);
5012
5013         /* Dummy read to force the chip to complete all current transactions. */
5014         val = REG_RD(sc, BCE_MISC_ID);
5015
5016         /* Chip reset. */
5017         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5018                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
5019                 REG_RD(sc, BCE_MISC_COMMAND);
5020                 DELAY(5);
5021
5022                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5023                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
5024
5025                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
5026         } else {
5027                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5028                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5029                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
5030                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
5031
5032                 /* Allow up to 30us for reset to complete. */
5033                 for (i = 0; i < 10; i++) {
5034                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
5035                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5036                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
5037                                 break;
5038                         }
5039                         DELAY(10);
5040                 }
5041
5042                 /* Check that reset completed successfully. */
5043                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5044                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
5045                         BCE_PRINTF("%s(%d): Reset failed!\n",
5046                             __FILE__, __LINE__);
5047                         rc = EBUSY;
5048                         goto bce_reset_exit;
5049                 }
5050         }
5051
5052         /* Make sure byte swapping is properly configured. */
5053         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
5054         if (val != 0x01020304) {
5055                 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n",
5056                     __FILE__, __LINE__);
5057                 rc = ENODEV;
5058                 goto bce_reset_exit;
5059         }
5060
5061         /* Just completed a reset, assume that firmware is running again. */
5062         sc->bce_fw_timed_out = FALSE;
5063         sc->bce_drv_cardiac_arrest = FALSE;
5064
5065         /* Wait for the firmware to finish its initialization. */
5066         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
5067         if (rc)
5068                 BCE_PRINTF("%s(%d): Firmware did not complete "
5069                     "initialization!\n", __FILE__, __LINE__);
5070         /* Get firmware capabilities. */
5071         bce_fw_cap_init(sc);
5072
5073 bce_reset_exit:
5074         /* Restore EMAC Mode bits needed to keep ASF/IPMI running. */
5075         if (reset_code == BCE_DRV_MSG_CODE_RESET) {
5076                 val = REG_RD(sc, BCE_EMAC_MODE);
5077                 val = (val & ~emac_mode_mask) | emac_mode_save;
5078                 REG_WR(sc, BCE_EMAC_MODE, val);
5079         }
5080
5081         DBEXIT(BCE_VERBOSE_RESET);
5082         return (rc);
5083 }
5084
5085
5086 static int
5087 bce_chipinit(struct bce_softc *sc)
5088 {
5089         u32 val;
5090         int rc = 0;
5091
5092         DBENTER(BCE_VERBOSE_RESET);
5093
5094         bce_disable_intr(sc);
5095
5096         /*
5097          * Initialize DMA byte/word swapping, configure the number of DMA
5098          * channels and PCI clock compensation delay.
5099          */
5100         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
5101             BCE_DMA_CONFIG_DATA_WORD_SWAP |
5102 #if BYTE_ORDER == BIG_ENDIAN
5103             BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
5104 #endif
5105             BCE_DMA_CONFIG_CNTL_WORD_SWAP |
5106             DMA_READ_CHANS << 12 |
5107             DMA_WRITE_CHANS << 16;
5108
5109         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
5110
5111         if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133))
5112                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
5113
5114         /*
5115          * This setting resolves a problem observed on certain Intel PCI
5116          * chipsets that cannot handle multiple outstanding DMA operations.
5117          * See errata E9_5706A1_65.
5118          */
5119         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5120             (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) &&
5121             !(sc->bce_flags & BCE_PCIX_FLAG))
5122                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
5123
5124         REG_WR(sc, BCE_DMA_CONFIG, val);
5125
5126         /* Enable the RX_V2P and Context state machines before access. */
5127         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5128             BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
5129             BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
5130             BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
5131
5132         /* Initialize context mapping and zero out the quick contexts. */
5133         if ((rc = bce_init_ctx(sc)) != 0)
5134                 goto bce_chipinit_exit;
5135
5136         /* Initialize the on-boards CPUs */
5137         bce_init_cpus(sc);
5138
5139         /* Enable management frames (NC-SI) to flow to the MCP. */
5140         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5141                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
5142                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5143         }
5144
5145         /* Prepare NVRAM for access. */
5146         if ((rc = bce_init_nvram(sc)) != 0)
5147                 goto bce_chipinit_exit;
5148
5149         /* Set the kernel bypass block size */
5150         val = REG_RD(sc, BCE_MQ_CONFIG);
5151         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
5152         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
5153
5154         /* Enable bins used on the 5709. */
5155         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5156                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
5157                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
5158                         val |= BCE_MQ_CONFIG_HALT_DIS;
5159         }
5160
5161         REG_WR(sc, BCE_MQ_CONFIG, val);
5162
5163         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
5164         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
5165         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
5166
5167         /* Set the page size and clear the RV2P processor stall bits. */
5168         val = (BCM_PAGE_BITS - 8) << 24;
5169         REG_WR(sc, BCE_RV2P_CONFIG, val);
5170
5171         /* Configure page size. */
5172         val = REG_RD(sc, BCE_TBDR_CONFIG);
5173         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
5174         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
5175         REG_WR(sc, BCE_TBDR_CONFIG, val);
5176
5177         /* Set the perfect match control register to default. */
5178         REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
5179
5180 bce_chipinit_exit:
5181         DBEXIT(BCE_VERBOSE_RESET);
5182
5183         return(rc);
5184 }
5185
5186
5187 /****************************************************************************/
5188 /* Initialize the controller in preparation to send/receive traffic.        */
5189 /*                                                                          */
5190 /* Returns:                                                                 */
5191 /*   0 for success, positive value for failure.                             */
5192 /****************************************************************************/
5193 static int
5194 bce_blockinit(struct bce_softc *sc)
5195 {
5196         u32 reg, val;
5197         int rc = 0;
5198
5199         DBENTER(BCE_VERBOSE_RESET);
5200
5201         /* Load the hardware default MAC address. */
5202         bce_set_mac_addr(sc);
5203
5204         /* Set the Ethernet backoff seed value */
5205         val = sc->eaddr[0]         + (sc->eaddr[1] << 8) +
5206               (sc->eaddr[2] << 16) + (sc->eaddr[3]     ) +
5207               (sc->eaddr[4] << 8)  + (sc->eaddr[5] << 16);
5208         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
5209
5210         sc->last_status_idx = 0;
5211         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
5212
5213         /* Set up link change interrupt generation. */
5214         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
5215
5216         /* Program the physical address of the status block. */
5217         REG_WR(sc, BCE_HC_STATUS_ADDR_L,
5218             BCE_ADDR_LO(sc->status_block_paddr));
5219         REG_WR(sc, BCE_HC_STATUS_ADDR_H,
5220             BCE_ADDR_HI(sc->status_block_paddr));
5221
5222         /* Program the physical address of the statistics block. */
5223         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
5224             BCE_ADDR_LO(sc->stats_block_paddr));
5225         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
5226             BCE_ADDR_HI(sc->stats_block_paddr));
5227
5228         /*
5229          * Program various host coalescing parameters.
5230          * Trip points control how many BDs should be ready before generating
5231          * an interrupt while ticks control how long a BD can sit in the chain
5232          * before generating an interrupt.
5233          */
5234         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5235             (sc->bce_tx_quick_cons_trip_int << 16) |
5236             sc->bce_tx_quick_cons_trip);
5237         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5238             (sc->bce_rx_quick_cons_trip_int << 16) |
5239             sc->bce_rx_quick_cons_trip);
5240         REG_WR(sc, BCE_HC_TX_TICKS,
5241             (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
5242         REG_WR(sc, BCE_HC_RX_TICKS,
5243             (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
5244         REG_WR(sc, BCE_HC_STATS_TICKS, sc->bce_stats_ticks & 0xffff00);
5245         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
5246         /* Not used for L2. */
5247         REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 0);
5248         REG_WR(sc, BCE_HC_COM_TICKS, 0);
5249         REG_WR(sc, BCE_HC_CMD_TICKS, 0);
5250
5251         /* Configure the Host Coalescing block. */
5252         val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE |
5253             BCE_HC_CONFIG_COLLECT_STATS;
5254
5255 #if 0
5256         /* ToDo: Add MSI-X support. */
5257         if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
5258                 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) +
5259                     BCE_HC_SB_CONFIG_1;
5260
5261                 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL);
5262
5263                 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE |
5264                     BCE_HC_SB_CONFIG_1_ONE_SHOT);
5265
5266                 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF,
5267                     (sc->tx_quick_cons_trip_int << 16) |
5268                      sc->tx_quick_cons_trip);
5269
5270                 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF,
5271                     (sc->tx_ticks_int << 16) | sc->tx_ticks);
5272
5273                 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
5274         }
5275
5276         /*
5277          * Tell the HC block to automatically set the
5278          * INT_MASK bit after an MSI/MSI-X interrupt
5279          * is generated so the driver doesn't have to.
5280          */
5281         if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG)
5282                 val |= BCE_HC_CONFIG_ONE_SHOT;
5283
5284         /* Set the MSI-X status blocks to 128 byte boundaries. */
5285         if (sc->bce_flags & BCE_USING_MSIX_FLAG)
5286                 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
5287 #endif
5288
5289         REG_WR(sc, BCE_HC_CONFIG, val);
5290
5291         /* Clear the internal statistics counters. */
5292         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
5293
5294         /* Verify that bootcode is running. */
5295         reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
5296
5297         DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control),
5298             BCE_PRINTF("%s(%d): Simulating bootcode failure.\n",
5299             __FILE__, __LINE__);
5300             reg = 0);
5301
5302         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5303             BCE_DEV_INFO_SIGNATURE_MAGIC) {
5304                 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, "
5305                     "Expected: 08%08X\n", __FILE__, __LINE__,
5306                     (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK),
5307                     BCE_DEV_INFO_SIGNATURE_MAGIC);
5308                 rc = ENODEV;
5309                 goto bce_blockinit_exit;
5310         }
5311
5312         /* Enable DMA */
5313         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5314                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
5315                 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
5316                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
5317         }
5318
5319         /* Allow bootcode to apply additional fixes before enabling MAC. */
5320         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 |
5321             BCE_DRV_MSG_CODE_RESET);
5322
5323         /* Enable link state change interrupt generation. */
5324         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
5325
5326         /* Enable the RXP. */
5327         bce_start_rxp_cpu(sc);
5328
5329         /* Disable management frames (NC-SI) from flowing to the MCP. */
5330         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5331                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
5332                     ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
5333                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5334         }
5335
5336         /* Enable all remaining blocks in the MAC. */
5337         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
5338                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5339                     BCE_MISC_ENABLE_DEFAULT_XI);
5340         else
5341                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5342                     BCE_MISC_ENABLE_DEFAULT);
5343
5344         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
5345         DELAY(20);
5346
5347         /* Save the current host coalescing block settings. */
5348         sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
5349
5350 bce_blockinit_exit:
5351         DBEXIT(BCE_VERBOSE_RESET);
5352
5353         return (rc);
5354 }
5355
5356
5357 /****************************************************************************/
5358 /* Encapsulate an mbuf into the rx_bd chain.                                */
5359 /*                                                                          */
5360 /* Returns:                                                                 */
5361 /*   0 for success, positive value for failure.                             */
5362 /****************************************************************************/
5363 static int
5364 bce_get_rx_buf(struct bce_softc *sc, u16 prod, u16 chain_prod, u32 *prod_bseq)
5365 {
5366         bus_dma_segment_t segs[1];
5367         struct mbuf *m_new = NULL;
5368         struct rx_bd *rxbd;
5369         int nsegs, error, rc = 0;
5370 #ifdef BCE_DEBUG
5371         u16 debug_chain_prod = chain_prod;
5372 #endif
5373
5374         DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5375
5376         /* Make sure the inputs are valid. */
5377         DBRUNIF((chain_prod > MAX_RX_BD_ALLOC),
5378             BCE_PRINTF("%s(%d): RX producer out of range: "
5379             "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5380             chain_prod, (u16)MAX_RX_BD_ALLOC));
5381
5382         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5383             "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__,
5384             prod, chain_prod, *prod_bseq);
5385
5386         /* Update some debug statistic counters */
5387         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
5388             sc->rx_low_watermark = sc->free_rx_bd);
5389         DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
5390             sc->rx_empty_count++);
5391
5392         /* Simulate an mbuf allocation failure. */
5393         DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5394             sc->mbuf_alloc_failed_count++;
5395             sc->mbuf_alloc_failed_sim_count++;
5396             rc = ENOBUFS;
5397             goto bce_get_rx_buf_exit);
5398
5399         /* This is a new mbuf allocation. */
5400         if (bce_hdr_split == TRUE)
5401                 MGETHDR(m_new, M_NOWAIT, MT_DATA);
5402         else
5403                 m_new = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
5404                     sc->rx_bd_mbuf_alloc_size);
5405
5406         if (m_new == NULL) {
5407                 sc->mbuf_alloc_failed_count++;
5408                 rc = ENOBUFS;
5409                 goto bce_get_rx_buf_exit;
5410         }
5411
5412         DBRUN(sc->debug_rx_mbuf_alloc++);
5413
5414         /* Make sure we have a valid packet header. */
5415         M_ASSERTPKTHDR(m_new);
5416
5417         /* Initialize the mbuf size and pad if necessary for alignment. */
5418         m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size;
5419         m_adj(m_new, sc->rx_bd_mbuf_align_pad);
5420
5421         /* ToDo: Consider calling m_fragment() to test error handling. */
5422
5423         /* Map the mbuf cluster into device memory. */
5424         error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag,
5425             sc->rx_mbuf_map[chain_prod], m_new, segs, &nsegs, BUS_DMA_NOWAIT);
5426
5427         /* Handle any mapping errors. */
5428         if (error) {
5429                 BCE_PRINTF("%s(%d): Error mapping mbuf into RX "
5430                     "chain (%d)!\n", __FILE__, __LINE__, error);
5431
5432                 sc->dma_map_addr_rx_failed_count++;
5433                 m_freem(m_new);
5434
5435                 DBRUN(sc->debug_rx_mbuf_alloc--);
5436
5437                 rc = ENOBUFS;
5438                 goto bce_get_rx_buf_exit;
5439         }
5440
5441         /* All mbufs must map to a single segment. */
5442         KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",
5443             __FUNCTION__, nsegs));
5444
5445         /* Setup the rx_bd for the segment. */
5446         rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
5447
5448         rxbd->rx_bd_haddr_lo  = htole32(BCE_ADDR_LO(segs[0].ds_addr));
5449         rxbd->rx_bd_haddr_hi  = htole32(BCE_ADDR_HI(segs[0].ds_addr));
5450         rxbd->rx_bd_len       = htole32(segs[0].ds_len);
5451         rxbd->rx_bd_flags     = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5452         *prod_bseq += segs[0].ds_len;
5453
5454         /* Save the mbuf and update our counter. */
5455         sc->rx_mbuf_ptr[chain_prod] = m_new;
5456         sc->free_rx_bd -= nsegs;
5457
5458         DBRUNMSG(BCE_INSANE_RECV,
5459             bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs));
5460
5461         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5462             "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, prod,
5463             chain_prod, *prod_bseq);
5464
5465 bce_get_rx_buf_exit:
5466         DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5467
5468         return(rc);
5469 }
5470
5471
5472 /****************************************************************************/
5473 /* Encapsulate an mbuf cluster into the page chain.                         */
5474 /*                                                                          */
5475 /* Returns:                                                                 */
5476 /*   0 for success, positive value for failure.                             */
5477 /****************************************************************************/
5478 static int
5479 bce_get_pg_buf(struct bce_softc *sc, u16 prod, u16 prod_idx)
5480 {
5481         bus_dma_segment_t segs[1];
5482         struct mbuf *m_new = NULL;
5483         struct rx_bd *pgbd;
5484         int error, nsegs, rc = 0;
5485 #ifdef BCE_DEBUG
5486         u16 debug_prod_idx = prod_idx;
5487 #endif
5488
5489         DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5490
5491         /* Make sure the inputs are valid. */
5492         DBRUNIF((prod_idx > MAX_PG_BD_ALLOC),
5493             BCE_PRINTF("%s(%d): page producer out of range: "
5494             "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5495             prod_idx, (u16)MAX_PG_BD_ALLOC));
5496
5497         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5498             "chain_prod = 0x%04X\n", __FUNCTION__, prod, prod_idx);
5499
5500         /* Update counters if we've hit a new low or run out of pages. */
5501         DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark),
5502             sc->pg_low_watermark = sc->free_pg_bd);
5503         DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++);
5504
5505         /* Simulate an mbuf allocation failure. */
5506         DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5507             sc->mbuf_alloc_failed_count++;
5508             sc->mbuf_alloc_failed_sim_count++;
5509             rc = ENOBUFS;
5510             goto bce_get_pg_buf_exit);
5511
5512         /* This is a new mbuf allocation. */
5513         m_new = m_getcl(M_NOWAIT, MT_DATA, 0);
5514         if (m_new == NULL) {
5515                 sc->mbuf_alloc_failed_count++;
5516                 rc = ENOBUFS;
5517                 goto bce_get_pg_buf_exit;
5518         }
5519
5520         DBRUN(sc->debug_pg_mbuf_alloc++);
5521
5522         m_new->m_len = MCLBYTES;
5523
5524         /* ToDo: Consider calling m_fragment() to test error handling. */
5525
5526         /* Map the mbuf cluster into device memory. */
5527         error = bus_dmamap_load_mbuf_sg(sc->pg_mbuf_tag,
5528             sc->pg_mbuf_map[prod_idx], m_new, segs, &nsegs, BUS_DMA_NOWAIT);
5529
5530         /* Handle any mapping errors. */
5531         if (error) {
5532                 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n",
5533                     __FILE__, __LINE__);
5534
5535                 m_freem(m_new);
5536                 DBRUN(sc->debug_pg_mbuf_alloc--);
5537
5538                 rc = ENOBUFS;
5539                 goto bce_get_pg_buf_exit;
5540         }
5541
5542         /* All mbufs must map to a single segment. */
5543         KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",
5544             __FUNCTION__, nsegs));
5545
5546         /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */
5547
5548         /*
5549          * The page chain uses the same rx_bd data structure
5550          * as the receive chain but doesn't require a byte sequence (bseq).
5551          */
5552         pgbd = &sc->pg_bd_chain[PG_PAGE(prod_idx)][PG_IDX(prod_idx)];
5553
5554         pgbd->rx_bd_haddr_lo  = htole32(BCE_ADDR_LO(segs[0].ds_addr));
5555         pgbd->rx_bd_haddr_hi  = htole32(BCE_ADDR_HI(segs[0].ds_addr));
5556         pgbd->rx_bd_len       = htole32(MCLBYTES);
5557         pgbd->rx_bd_flags     = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5558
5559         /* Save the mbuf and update our counter. */
5560         sc->pg_mbuf_ptr[prod_idx] = m_new;
5561         sc->free_pg_bd--;
5562
5563         DBRUNMSG(BCE_INSANE_RECV,
5564             bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1));
5565
5566         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5567             "prod_idx = 0x%04X\n", __FUNCTION__, prod, prod_idx);
5568
5569 bce_get_pg_buf_exit:
5570         DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5571
5572         return(rc);
5573 }
5574
5575
5576 /****************************************************************************/
5577 /* Initialize the TX context memory.                                        */
5578 /*                                                                          */
5579 /* Returns:                                                                 */
5580 /*   Nothing                                                                */
5581 /****************************************************************************/
5582 static void
5583 bce_init_tx_context(struct bce_softc *sc)
5584 {
5585         u32 val;
5586
5587         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5588
5589         /* Initialize the context ID for an L2 TX chain. */
5590         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5591                 /* Set the CID type to support an L2 connection. */
5592                 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI |
5593                     BCE_L2CTX_TX_TYPE_SIZE_L2_XI;
5594                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
5595                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16);
5596                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5597                     BCE_L2CTX_TX_CMD_TYPE_XI, val);
5598
5599                 /* Point the hardware to the first page in the chain. */
5600                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5601                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5602                     BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
5603                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5604                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5605                     BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
5606         } else {
5607                 /* Set the CID type to support an L2 connection. */
5608                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
5609                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
5610                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
5611                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
5612
5613                 /* Point the hardware to the first page in the chain. */
5614                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5615                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5616                     BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
5617                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5618                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5619                     BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
5620         }
5621
5622         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5623 }
5624
5625
5626 /****************************************************************************/
5627 /* Allocate memory and initialize the TX data structures.                   */
5628 /*                                                                          */
5629 /* Returns:                                                                 */
5630 /*   0 for success, positive value for failure.                             */
5631 /****************************************************************************/
5632 static int
5633 bce_init_tx_chain(struct bce_softc *sc)
5634 {
5635         struct tx_bd *txbd;
5636         int i, rc = 0;
5637
5638         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5639
5640         /* Set the initial TX producer/consumer indices. */
5641         sc->tx_prod        = 0;
5642         sc->tx_cons        = 0;
5643         sc->tx_prod_bseq   = 0;
5644         sc->used_tx_bd     = 0;
5645         sc->max_tx_bd      = USABLE_TX_BD_ALLOC;
5646         DBRUN(sc->tx_hi_watermark = 0);
5647         DBRUN(sc->tx_full_count = 0);
5648
5649         /*
5650          * The NetXtreme II supports a linked-list structre called
5651          * a Buffer Descriptor Chain (or BD chain).  A BD chain
5652          * consists of a series of 1 or more chain pages, each of which
5653          * consists of a fixed number of BD entries.
5654          * The last BD entry on each page is a pointer to the next page
5655          * in the chain, and the last pointer in the BD chain
5656          * points back to the beginning of the chain.
5657          */
5658
5659         /* Set the TX next pointer chain entries. */
5660         for (i = 0; i < sc->tx_pages; i++) {
5661                 int j;
5662
5663                 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
5664
5665                 /* Check if we've reached the last page. */
5666                 if (i == (sc->tx_pages - 1))
5667                         j = 0;
5668                 else
5669                         j = i + 1;
5670
5671                 txbd->tx_bd_haddr_hi =
5672                     htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
5673                 txbd->tx_bd_haddr_lo =
5674                     htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
5675         }
5676
5677         bce_init_tx_context(sc);
5678
5679         DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC));
5680         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5681
5682         return(rc);
5683 }
5684
5685
5686 /****************************************************************************/
5687 /* Free memory and clear the TX data structures.                            */
5688 /*                                                                          */
5689 /* Returns:                                                                 */
5690 /*   Nothing.                                                               */
5691 /****************************************************************************/
5692 static void
5693 bce_free_tx_chain(struct bce_softc *sc)
5694 {
5695         int i;
5696
5697         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5698
5699         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
5700         for (i = 0; i < MAX_TX_BD_AVAIL; i++) {
5701                 if (sc->tx_mbuf_ptr[i] != NULL) {
5702                         if (sc->tx_mbuf_map[i] != NULL)
5703                                 bus_dmamap_sync(sc->tx_mbuf_tag,
5704                                     sc->tx_mbuf_map[i],
5705                                     BUS_DMASYNC_POSTWRITE);
5706                         m_freem(sc->tx_mbuf_ptr[i]);
5707                         sc->tx_mbuf_ptr[i] = NULL;
5708                         DBRUN(sc->debug_tx_mbuf_alloc--);
5709                 }
5710         }
5711
5712         /* Clear each TX chain page. */
5713         for (i = 0; i < sc->tx_pages; i++)
5714                 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
5715
5716         sc->used_tx_bd = 0;
5717
5718         /* Check if we lost any mbufs in the process. */
5719         DBRUNIF((sc->debug_tx_mbuf_alloc),
5720             BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs "
5721             "from tx chain!\n", __FILE__, __LINE__,
5722             sc->debug_tx_mbuf_alloc));
5723
5724         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5725 }
5726
5727
5728 /****************************************************************************/
5729 /* Initialize the RX context memory.                                        */
5730 /*                                                                          */
5731 /* Returns:                                                                 */
5732 /*   Nothing                                                                */
5733 /****************************************************************************/
5734 static void
5735 bce_init_rx_context(struct bce_softc *sc)
5736 {
5737         u32 val;
5738
5739         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5740
5741         /* Init the type, size, and BD cache levels for the RX context. */
5742         val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
5743             BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 |
5744             (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT);
5745
5746         /*
5747          * Set the level for generating pause frames
5748          * when the number of available rx_bd's gets
5749          * too low (the low watermark) and the level
5750          * when pause frames can be stopped (the high
5751          * watermark).
5752          */
5753         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5754                 u32 lo_water, hi_water;
5755
5756                 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) {
5757                         lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
5758                 } else {
5759                         lo_water = 0;
5760                 }
5761
5762                 if (lo_water >= USABLE_RX_BD_ALLOC) {
5763                         lo_water = 0;
5764                 }
5765
5766                 hi_water = USABLE_RX_BD_ALLOC / 4;
5767
5768                 if (hi_water <= lo_water) {
5769                         lo_water = 0;
5770                 }
5771
5772                 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
5773                 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
5774
5775                 if (hi_water > 0xf)
5776                         hi_water = 0xf;
5777                 else if (hi_water == 0)
5778                         lo_water = 0;
5779
5780                 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) |
5781                     (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
5782         }
5783
5784         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
5785
5786         /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
5787         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5788                 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
5789                 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
5790         }
5791
5792         /* Point the hardware to the first page in the chain. */
5793         val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
5794         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
5795         val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
5796         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
5797
5798         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5799 }
5800
5801
5802 /****************************************************************************/
5803 /* Allocate memory and initialize the RX data structures.                   */
5804 /*                                                                          */
5805 /* Returns:                                                                 */
5806 /*   0 for success, positive value for failure.                             */
5807 /****************************************************************************/
5808 static int
5809 bce_init_rx_chain(struct bce_softc *sc)
5810 {
5811         struct rx_bd *rxbd;
5812         int i, rc = 0;
5813
5814         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5815             BCE_VERBOSE_CTX);
5816
5817         /* Initialize the RX producer and consumer indices. */
5818         sc->rx_prod        = 0;
5819         sc->rx_cons        = 0;
5820         sc->rx_prod_bseq   = 0;
5821         sc->free_rx_bd     = USABLE_RX_BD_ALLOC;
5822         sc->max_rx_bd      = USABLE_RX_BD_ALLOC;
5823
5824         /* Initialize the RX next pointer chain entries. */
5825         for (i = 0; i < sc->rx_pages; i++) {
5826                 int j;
5827
5828                 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
5829
5830                 /* Check if we've reached the last page. */
5831                 if (i == (sc->rx_pages - 1))
5832                         j = 0;
5833                 else
5834                         j = i + 1;
5835
5836                 /* Setup the chain page pointers. */
5837                 rxbd->rx_bd_haddr_hi =
5838                     htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
5839                 rxbd->rx_bd_haddr_lo =
5840                     htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
5841         }
5842
5843         /* Fill up the RX chain. */
5844         bce_fill_rx_chain(sc);
5845
5846         DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC);
5847         DBRUN(sc->rx_empty_count = 0);
5848         for (i = 0; i < sc->rx_pages; i++) {
5849                 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i],
5850                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
5851         }
5852
5853         bce_init_rx_context(sc);
5854
5855         DBRUNMSG(BCE_EXTREME_RECV,
5856             bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC));
5857         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5858             BCE_VERBOSE_CTX);
5859
5860         /* ToDo: Are there possible failure modes here? */
5861
5862         return(rc);
5863 }
5864
5865
5866 /****************************************************************************/
5867 /* Add mbufs to the RX chain until its full or an mbuf allocation error     */
5868 /* occurs.                                                                  */
5869 /*                                                                          */
5870 /* Returns:                                                                 */
5871 /*   Nothing                                                                */
5872 /****************************************************************************/
5873 static void
5874 bce_fill_rx_chain(struct bce_softc *sc)
5875 {
5876         u16 prod, prod_idx;
5877         u32 prod_bseq;
5878
5879         DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5880             BCE_VERBOSE_CTX);
5881
5882         /* Get the RX chain producer indices. */
5883         prod      = sc->rx_prod;
5884         prod_bseq = sc->rx_prod_bseq;
5885
5886         /* Keep filling the RX chain until it's full. */
5887         while (sc->free_rx_bd > 0) {
5888                 prod_idx = RX_CHAIN_IDX(prod);
5889                 if (bce_get_rx_buf(sc, prod, prod_idx, &prod_bseq)) {
5890                         /* Bail out if we can't add an mbuf to the chain. */
5891                         break;
5892                 }
5893                 prod = NEXT_RX_BD(prod);
5894         }
5895
5896         /* Save the RX chain producer indices. */
5897         sc->rx_prod      = prod;
5898         sc->rx_prod_bseq = prod_bseq;
5899
5900         /* We should never end up pointing to a next page pointer. */
5901         DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
5902             BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n",
5903             __FUNCTION__, rx_prod));
5904
5905         /* Write the mailbox and tell the chip about the waiting rx_bd's. */
5906         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX, prod);
5907         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ, prod_bseq);
5908
5909         DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5910             BCE_VERBOSE_CTX);
5911 }
5912
5913
5914 /****************************************************************************/
5915 /* Free memory and clear the RX data structures.                            */
5916 /*                                                                          */
5917 /* Returns:                                                                 */
5918 /*   Nothing.                                                               */
5919 /****************************************************************************/
5920 static void
5921 bce_free_rx_chain(struct bce_softc *sc)
5922 {
5923         int i;
5924
5925         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5926
5927         /* Free any mbufs still in the RX mbuf chain. */
5928         for (i = 0; i < MAX_RX_BD_AVAIL; i++) {
5929                 if (sc->rx_mbuf_ptr[i] != NULL) {
5930                         if (sc->rx_mbuf_map[i] != NULL)
5931                                 bus_dmamap_sync(sc->rx_mbuf_tag,
5932                                     sc->rx_mbuf_map[i],
5933                                     BUS_DMASYNC_POSTREAD);
5934                         m_freem(sc->rx_mbuf_ptr[i]);
5935                         sc->rx_mbuf_ptr[i] = NULL;
5936                         DBRUN(sc->debug_rx_mbuf_alloc--);
5937                 }
5938         }
5939
5940         /* Clear each RX chain page. */
5941         for (i = 0; i < sc->rx_pages; i++)
5942                 if (sc->rx_bd_chain[i] != NULL)
5943                         bzero((char *)sc->rx_bd_chain[i],
5944                             BCE_RX_CHAIN_PAGE_SZ);
5945
5946         sc->free_rx_bd = sc->max_rx_bd;
5947
5948         /* Check if we lost any mbufs in the process. */
5949         DBRUNIF((sc->debug_rx_mbuf_alloc),
5950             BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n",
5951             __FUNCTION__, sc->debug_rx_mbuf_alloc));
5952
5953         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5954 }
5955
5956
5957 /****************************************************************************/
5958 /* Allocate memory and initialize the page data structures.                 */
5959 /* Assumes that bce_init_rx_chain() has not already been called.            */
5960 /*                                                                          */
5961 /* Returns:                                                                 */
5962 /*   0 for success, positive value for failure.                             */
5963 /****************************************************************************/
5964 static int
5965 bce_init_pg_chain(struct bce_softc *sc)
5966 {
5967         struct rx_bd *pgbd;
5968         int i, rc = 0;
5969         u32 val;
5970
5971         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5972                 BCE_VERBOSE_CTX);
5973
5974         /* Initialize the page producer and consumer indices. */
5975         sc->pg_prod        = 0;
5976         sc->pg_cons        = 0;
5977         sc->free_pg_bd     = USABLE_PG_BD_ALLOC;
5978         sc->max_pg_bd      = USABLE_PG_BD_ALLOC;
5979         DBRUN(sc->pg_low_watermark = sc->max_pg_bd);
5980         DBRUN(sc->pg_empty_count = 0);
5981
5982         /* Initialize the page next pointer chain entries. */
5983         for (i = 0; i < sc->pg_pages; i++) {
5984                 int j;
5985
5986                 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE];
5987
5988                 /* Check if we've reached the last page. */
5989                 if (i == (sc->pg_pages - 1))
5990                         j = 0;
5991                 else
5992                         j = i + 1;
5993
5994                 /* Setup the chain page pointers. */
5995                 pgbd->rx_bd_haddr_hi =
5996                     htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j]));
5997                 pgbd->rx_bd_haddr_lo =
5998                     htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j]));
5999         }
6000
6001         /* Setup the MQ BIN mapping for host_pg_bidx. */
6002         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
6003                 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT);
6004
6005         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0);
6006
6007         /* Configure the rx_bd and page chain mbuf cluster size. */
6008         val = (sc->rx_bd_mbuf_data_len << 16) | MCLBYTES;
6009         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val);
6010
6011         /* Configure the context reserved for jumbo support. */
6012         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY,
6013                 BCE_L2CTX_RX_RBDC_JUMBO_KEY);
6014
6015         /* Point the hardware to the first page in the page chain. */
6016         val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]);
6017         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val);
6018         val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]);
6019         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val);
6020
6021         /* Fill up the page chain. */
6022         bce_fill_pg_chain(sc);
6023
6024         for (i = 0; i < sc->pg_pages; i++) {
6025                 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i],
6026                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
6027         }
6028
6029         DBRUNMSG(BCE_EXTREME_RECV,
6030             bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC));
6031         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
6032                 BCE_VERBOSE_CTX);
6033         return(rc);
6034 }
6035
6036
6037 /****************************************************************************/
6038 /* Add mbufs to the page chain until its full or an mbuf allocation error   */
6039 /* occurs.                                                                  */
6040 /*                                                                          */
6041 /* Returns:                                                                 */
6042 /*   Nothing                                                                */
6043 /****************************************************************************/
6044 static void
6045 bce_fill_pg_chain(struct bce_softc *sc)
6046 {
6047         u16 prod, prod_idx;
6048
6049         DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
6050             BCE_VERBOSE_CTX);
6051
6052         /* Get the page chain prodcuer index. */
6053         prod = sc->pg_prod;
6054
6055         /* Keep filling the page chain until it's full. */
6056         while (sc->free_pg_bd > 0) {
6057                 prod_idx = PG_CHAIN_IDX(prod);
6058                 if (bce_get_pg_buf(sc, prod, prod_idx)) {
6059                         /* Bail out if we can't add an mbuf to the chain. */
6060                         break;
6061                 }
6062                 prod = NEXT_PG_BD(prod);
6063         }
6064
6065         /* Save the page chain producer index. */
6066         sc->pg_prod = prod;
6067
6068         DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
6069             BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n",
6070             __FUNCTION__, pg_prod));
6071
6072         /*
6073          * Write the mailbox and tell the chip about
6074          * the new rx_bd's in the page chain.
6075          */
6076         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_PG_BDIDX,
6077             prod);
6078
6079         DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
6080             BCE_VERBOSE_CTX);
6081 }
6082
6083
6084 /****************************************************************************/
6085 /* Free memory and clear the RX data structures.                            */
6086 /*                                                                          */
6087 /* Returns:                                                                 */
6088 /*   Nothing.                                                               */
6089 /****************************************************************************/
6090 static void
6091 bce_free_pg_chain(struct bce_softc *sc)
6092 {
6093         int i;
6094
6095         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
6096
6097         /* Free any mbufs still in the mbuf page chain. */
6098         for (i = 0; i < MAX_PG_BD_AVAIL; i++) {
6099                 if (sc->pg_mbuf_ptr[i] != NULL) {
6100                         if (sc->pg_mbuf_map[i] != NULL)
6101                                 bus_dmamap_sync(sc->pg_mbuf_tag,
6102                                     sc->pg_mbuf_map[i],
6103                                     BUS_DMASYNC_POSTREAD);
6104                         m_freem(sc->pg_mbuf_ptr[i]);
6105                         sc->pg_mbuf_ptr[i] = NULL;
6106                         DBRUN(sc->debug_pg_mbuf_alloc--);
6107                 }
6108         }
6109
6110         /* Clear each page chain pages. */
6111         for (i = 0; i < sc->pg_pages; i++)
6112                 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ);
6113
6114         sc->free_pg_bd = sc->max_pg_bd;
6115
6116         /* Check if we lost any mbufs in the process. */
6117         DBRUNIF((sc->debug_pg_mbuf_alloc),
6118             BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n",
6119             __FUNCTION__, sc->debug_pg_mbuf_alloc));
6120
6121         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
6122 }
6123
6124
6125 static u32
6126 bce_get_rphy_link(struct bce_softc *sc)
6127 {
6128         u32 advertise, link;
6129         int fdpx;
6130
6131         advertise = 0;
6132         fdpx = 0;
6133         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0)
6134                 link = bce_shmem_rd(sc, BCE_RPHY_SERDES_LINK);
6135         else
6136                 link = bce_shmem_rd(sc, BCE_RPHY_COPPER_LINK);
6137         if (link & BCE_NETLINK_ANEG_ENB)
6138                 advertise |= BCE_NETLINK_ANEG_ENB;
6139         if (link & BCE_NETLINK_SPEED_10HALF)
6140                 advertise |= BCE_NETLINK_SPEED_10HALF;
6141         if (link & BCE_NETLINK_SPEED_10FULL) {
6142                 advertise |= BCE_NETLINK_SPEED_10FULL;
6143                 fdpx++;
6144         }
6145         if (link & BCE_NETLINK_SPEED_100HALF)
6146                 advertise |= BCE_NETLINK_SPEED_100HALF;
6147         if (link & BCE_NETLINK_SPEED_100FULL) {
6148                 advertise |= BCE_NETLINK_SPEED_100FULL;
6149                 fdpx++;
6150         }
6151         if (link & BCE_NETLINK_SPEED_1000HALF)
6152                 advertise |= BCE_NETLINK_SPEED_1000HALF;
6153         if (link & BCE_NETLINK_SPEED_1000FULL) {
6154                 advertise |= BCE_NETLINK_SPEED_1000FULL;
6155                 fdpx++;
6156         }
6157         if (link & BCE_NETLINK_SPEED_2500HALF)
6158                 advertise |= BCE_NETLINK_SPEED_2500HALF;
6159         if (link & BCE_NETLINK_SPEED_2500FULL) {
6160                 advertise |= BCE_NETLINK_SPEED_2500FULL;
6161                 fdpx++;
6162         }
6163         if (fdpx)
6164                 advertise |= BCE_NETLINK_FC_PAUSE_SYM |
6165                     BCE_NETLINK_FC_PAUSE_ASYM;
6166         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6167                 advertise |= BCE_NETLINK_PHY_APP_REMOTE |
6168                     BCE_NETLINK_ETH_AT_WIRESPEED;
6169
6170         return (advertise);
6171 }
6172
6173
6174 /****************************************************************************/
6175 /* Set media options.                                                       */
6176 /*                                                                          */
6177 /* Returns:                                                                 */
6178 /*   0 for success, positive value for failure.                             */
6179 /****************************************************************************/
6180 static int
6181 bce_ifmedia_upd(struct ifnet *ifp)
6182 {
6183         struct bce_softc *sc = ifp->if_softc;
6184         int error;
6185
6186         DBENTER(BCE_VERBOSE);
6187
6188         BCE_LOCK(sc);
6189         error = bce_ifmedia_upd_locked(ifp);
6190         BCE_UNLOCK(sc);
6191
6192         DBEXIT(BCE_VERBOSE);
6193         return (error);
6194 }
6195
6196
6197 /****************************************************************************/
6198 /* Set media options.                                                       */
6199 /*                                                                          */
6200 /* Returns:                                                                 */
6201 /*   Nothing.                                                               */
6202 /****************************************************************************/
6203 static int
6204 bce_ifmedia_upd_locked(struct ifnet *ifp)
6205 {
6206         struct bce_softc *sc = ifp->if_softc;
6207         struct mii_data *mii;
6208         struct mii_softc *miisc;
6209         struct ifmedia *ifm;
6210         u32 link;
6211         int error, fdx;
6212
6213         DBENTER(BCE_VERBOSE_PHY);
6214
6215         error = 0;
6216         BCE_LOCK_ASSERT(sc);
6217
6218         sc->bce_link_up = FALSE;
6219         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6220                 ifm = &sc->bce_ifmedia;
6221                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
6222                         return (EINVAL);
6223                 link = 0;
6224                 fdx = IFM_OPTIONS(ifm->ifm_media) & IFM_FDX;
6225                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
6226                 case IFM_AUTO:
6227                         /*
6228                          * Check advertised link of remote PHY by reading
6229                          * BCE_RPHY_SERDES_LINK or BCE_RPHY_COPPER_LINK.
6230                          * Always use the same link type of remote PHY.
6231                          */
6232                         link = bce_get_rphy_link(sc);
6233                         break;
6234                 case IFM_2500_SX:
6235                         if ((sc->bce_phy_flags &
6236                             (BCE_PHY_REMOTE_PORT_FIBER_FLAG |
6237                             BCE_PHY_2_5G_CAPABLE_FLAG)) == 0)
6238                                 return (EINVAL);
6239                         /*
6240                          * XXX
6241                          * Have to enable forced 2.5Gbps configuration.
6242                          */
6243                         if (fdx != 0)
6244                                 link |= BCE_NETLINK_SPEED_2500FULL;
6245                         else
6246                                 link |= BCE_NETLINK_SPEED_2500HALF;
6247                         break;
6248                 case IFM_1000_SX:
6249                         if ((sc->bce_phy_flags &
6250                             BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6251                                 return (EINVAL);
6252                         /*
6253                          * XXX
6254                          * Have to disable 2.5Gbps configuration.
6255                          */
6256                         if (fdx != 0)
6257                                 link = BCE_NETLINK_SPEED_1000FULL;
6258                         else
6259                                 link = BCE_NETLINK_SPEED_1000HALF;
6260                         break;
6261                 case IFM_1000_T:
6262                         if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6263                                 return (EINVAL);
6264                         if (fdx != 0)
6265                                 link = BCE_NETLINK_SPEED_1000FULL;
6266                         else
6267                                 link = BCE_NETLINK_SPEED_1000HALF;
6268                         break;
6269                 case IFM_100_TX:
6270                         if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6271                                 return (EINVAL);
6272                         if (fdx != 0)
6273                                 link = BCE_NETLINK_SPEED_100FULL;
6274                         else
6275                                 link = BCE_NETLINK_SPEED_100HALF;
6276                         break;
6277                 case IFM_10_T:
6278                         if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6279                                 return (EINVAL);
6280                         if (fdx != 0)
6281                                 link = BCE_NETLINK_SPEED_10FULL;
6282                         else
6283                                 link = BCE_NETLINK_SPEED_10HALF;
6284                         break;
6285                 default:
6286                         return (EINVAL);
6287                 }
6288                 if (IFM_SUBTYPE(ifm->ifm_media) != IFM_AUTO) {
6289                         /*
6290                          * XXX
6291                          * Advertise pause capability for full-duplex media.
6292                          */
6293                         if (fdx != 0)
6294                                 link |= BCE_NETLINK_FC_PAUSE_SYM |
6295                                     BCE_NETLINK_FC_PAUSE_ASYM;
6296                         if ((sc->bce_phy_flags &
6297                             BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6298                                 link |= BCE_NETLINK_PHY_APP_REMOTE |
6299                                     BCE_NETLINK_ETH_AT_WIRESPEED;
6300                 }
6301
6302                 bce_shmem_wr(sc, BCE_MB_ARGS_0, link);
6303                 error = bce_fw_sync(sc, BCE_DRV_MSG_CODE_CMD_SET_LINK);
6304         } else {
6305                 mii = device_get_softc(sc->bce_miibus);
6306
6307                 /* Make sure the MII bus has been enumerated. */
6308                 if (mii) {
6309                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
6310                                 PHY_RESET(miisc);
6311                         error = mii_mediachg(mii);
6312                 }
6313         }
6314
6315         DBEXIT(BCE_VERBOSE_PHY);
6316         return (error);
6317 }
6318
6319
6320 static void
6321 bce_ifmedia_sts_rphy(struct bce_softc *sc, struct ifmediareq *ifmr)
6322 {
6323         struct ifnet *ifp;
6324         u32 link;
6325
6326         ifp = sc->bce_ifp;
6327         BCE_LOCK_ASSERT(sc);
6328
6329         ifmr->ifm_status = IFM_AVALID;
6330         ifmr->ifm_active = IFM_ETHER;
6331         link = bce_shmem_rd(sc, BCE_LINK_STATUS);
6332         /* XXX Handle heart beat status? */
6333         if ((link & BCE_LINK_STATUS_LINK_UP) != 0)
6334                 ifmr->ifm_status |= IFM_ACTIVE;
6335         else {
6336                 ifmr->ifm_active |= IFM_NONE;
6337                 ifp->if_baudrate = 0;
6338                 return;
6339         }
6340         switch (link & BCE_LINK_STATUS_SPEED_MASK) {
6341         case BCE_LINK_STATUS_10HALF:
6342                 ifmr->ifm_active |= IFM_10_T | IFM_HDX;
6343                 ifp->if_baudrate = IF_Mbps(10UL);
6344                 break;
6345         case BCE_LINK_STATUS_10FULL:
6346                 ifmr->ifm_active |= IFM_10_T | IFM_FDX;
6347                 ifp->if_baudrate = IF_Mbps(10UL);
6348                 break;
6349         case BCE_LINK_STATUS_100HALF:
6350                 ifmr->ifm_active |= IFM_100_TX | IFM_HDX;
6351                 ifp->if_baudrate = IF_Mbps(100UL);
6352                 break;
6353         case BCE_LINK_STATUS_100FULL:
6354                 ifmr->ifm_active |= IFM_100_TX | IFM_FDX;
6355                 ifp->if_baudrate = IF_Mbps(100UL);
6356                 break;
6357         case BCE_LINK_STATUS_1000HALF:
6358                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6359                         ifmr->ifm_active |= IFM_1000_T | IFM_HDX;
6360                 else
6361                         ifmr->ifm_active |= IFM_1000_SX | IFM_HDX;
6362                 ifp->if_baudrate = IF_Mbps(1000UL);
6363                 break;
6364         case BCE_LINK_STATUS_1000FULL:
6365                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6366                         ifmr->ifm_active |= IFM_1000_T | IFM_FDX;
6367                 else
6368                         ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
6369                 ifp->if_baudrate = IF_Mbps(1000UL);
6370                 break;
6371         case BCE_LINK_STATUS_2500HALF:
6372                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6373                         ifmr->ifm_active |= IFM_NONE;
6374                         return;
6375                 } else
6376                         ifmr->ifm_active |= IFM_2500_SX | IFM_HDX;
6377                 ifp->if_baudrate = IF_Mbps(2500UL);
6378                 break;
6379         case BCE_LINK_STATUS_2500FULL:
6380                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6381                         ifmr->ifm_active |= IFM_NONE;
6382                         return;
6383                 } else
6384                         ifmr->ifm_active |= IFM_2500_SX | IFM_FDX;
6385                 ifp->if_baudrate = IF_Mbps(2500UL);
6386                 break;
6387         default:
6388                 ifmr->ifm_active |= IFM_NONE;
6389                 return;
6390         }
6391
6392         if ((link & BCE_LINK_STATUS_RX_FC_ENABLED) != 0)
6393                 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
6394         if ((link & BCE_LINK_STATUS_TX_FC_ENABLED) != 0)
6395                 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
6396 }
6397
6398
6399 /****************************************************************************/
6400 /* Reports current media status.                                            */
6401 /*                                                                          */
6402 /* Returns:                                                                 */
6403 /*   Nothing.                                                               */
6404 /****************************************************************************/
6405 static void
6406 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
6407 {
6408         struct bce_softc *sc = ifp->if_softc;
6409         struct mii_data *mii;
6410
6411         DBENTER(BCE_VERBOSE_PHY);
6412
6413         BCE_LOCK(sc);
6414
6415         if ((ifp->if_flags & IFF_UP) == 0) {
6416                 BCE_UNLOCK(sc);
6417                 return;
6418         }
6419
6420         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
6421                 bce_ifmedia_sts_rphy(sc, ifmr);
6422         else {
6423                 mii = device_get_softc(sc->bce_miibus);
6424                 mii_pollstat(mii);
6425                 ifmr->ifm_active = mii->mii_media_active;
6426                 ifmr->ifm_status = mii->mii_media_status;
6427         }
6428
6429         BCE_UNLOCK(sc);
6430
6431         DBEXIT(BCE_VERBOSE_PHY);
6432 }
6433
6434
6435 /****************************************************************************/
6436 /* Handles PHY generated interrupt events.                                  */
6437 /*                                                                          */
6438 /* Returns:                                                                 */
6439 /*   Nothing.                                                               */
6440 /****************************************************************************/
6441 static void
6442 bce_phy_intr(struct bce_softc *sc)
6443 {
6444         u32 new_link_state, old_link_state;
6445
6446         DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
6447
6448         DBRUN(sc->phy_interrupts++);
6449
6450         new_link_state = sc->status_block->status_attn_bits &
6451             STATUS_ATTN_BITS_LINK_STATE;
6452         old_link_state = sc->status_block->status_attn_bits_ack &
6453             STATUS_ATTN_BITS_LINK_STATE;
6454
6455         /* Handle any changes if the link state has changed. */
6456         if (new_link_state != old_link_state) {
6457
6458                 /* Update the status_attn_bits_ack field. */
6459                 if (new_link_state) {
6460                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
6461                             STATUS_ATTN_BITS_LINK_STATE);
6462                         DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n",
6463                             __FUNCTION__);
6464                 } else {
6465                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
6466                             STATUS_ATTN_BITS_LINK_STATE);
6467                         DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n",
6468                             __FUNCTION__);
6469                 }
6470
6471                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6472                         if (new_link_state) {
6473                                 if (bootverbose)
6474                                         if_printf(sc->bce_ifp, "link UP\n");
6475                                 if_link_state_change(sc->bce_ifp,
6476                                     LINK_STATE_UP);
6477                         } else {
6478                                 if (bootverbose)
6479                                         if_printf(sc->bce_ifp, "link DOWN\n");
6480                                 if_link_state_change(sc->bce_ifp,
6481                                     LINK_STATE_DOWN);
6482                         }
6483                 }
6484                 /*
6485                  * Assume link is down and allow
6486                  * tick routine to update the state
6487                  * based on the actual media state.
6488                  */
6489                 sc->bce_link_up = FALSE;
6490                 callout_stop(&sc->bce_tick_callout);
6491                 bce_tick(sc);
6492         }
6493
6494         /* Acknowledge the link change interrupt. */
6495         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
6496
6497         DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
6498 }
6499
6500
6501 /****************************************************************************/
6502 /* Reads the receive consumer value from the status block (skipping over    */
6503 /* chain page pointer if necessary).                                        */
6504 /*                                                                          */
6505 /* Returns:                                                                 */
6506 /*   hw_cons                                                                */
6507 /****************************************************************************/
6508 static inline u16
6509 bce_get_hw_rx_cons(struct bce_softc *sc)
6510 {
6511         u16 hw_cons;
6512
6513         rmb();
6514         hw_cons = sc->status_block->status_rx_quick_consumer_index0;
6515         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
6516                 hw_cons++;
6517
6518         return hw_cons;
6519 }
6520
6521 /****************************************************************************/
6522 /* Handles received frame interrupt events.                                 */
6523 /*                                                                          */
6524 /* Returns:                                                                 */
6525 /*   Nothing.                                                               */
6526 /****************************************************************************/
6527 static void
6528 bce_rx_intr(struct bce_softc *sc)
6529 {
6530         struct ifnet *ifp = sc->bce_ifp;
6531         struct l2_fhdr *l2fhdr;
6532         struct ether_vlan_header *vh;
6533         unsigned int pkt_len;
6534         u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons;
6535         u32 status;
6536         unsigned int rem_len;
6537         u16 sw_pg_cons, sw_pg_cons_idx;
6538
6539         DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6540         DBRUN(sc->interrupts_rx++);
6541         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, "
6542             "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6543             __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6544
6545         /* Prepare the RX chain pages to be accessed by the host CPU. */
6546         for (int i = 0; i < sc->rx_pages; i++)
6547                 bus_dmamap_sync(sc->rx_bd_chain_tag,
6548                     sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
6549
6550         /* Prepare the page chain pages to be accessed by the host CPU. */
6551         if (bce_hdr_split == TRUE) {
6552                 for (int i = 0; i < sc->pg_pages; i++)
6553                         bus_dmamap_sync(sc->pg_bd_chain_tag,
6554                             sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
6555         }
6556
6557         /* Get the hardware's view of the RX consumer index. */
6558         hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6559
6560         /* Get working copies of the driver's view of the consumer indices. */
6561         sw_rx_cons = sc->rx_cons;
6562         sw_pg_cons = sc->pg_cons;
6563
6564         /* Update some debug statistics counters */
6565         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
6566             sc->rx_low_watermark = sc->free_rx_bd);
6567         DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
6568             sc->rx_empty_count++);
6569
6570         /* Scan through the receive chain as long as there is work to do */
6571         /* ToDo: Consider setting a limit on the number of packets processed. */
6572         rmb();
6573         while (sw_rx_cons != hw_rx_cons) {
6574                 struct mbuf *m0;
6575
6576                 /* Convert the producer/consumer indices to an actual rx_bd index. */
6577                 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons);
6578
6579                 /* Unmap the mbuf from DMA space. */
6580                 bus_dmamap_sync(sc->rx_mbuf_tag,
6581                     sc->rx_mbuf_map[sw_rx_cons_idx],
6582                     BUS_DMASYNC_POSTREAD);
6583                 bus_dmamap_unload(sc->rx_mbuf_tag,
6584                     sc->rx_mbuf_map[sw_rx_cons_idx]);
6585
6586                 /* Remove the mbuf from the RX chain. */
6587                 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx];
6588                 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL;
6589                 DBRUN(sc->debug_rx_mbuf_alloc--);
6590                 sc->free_rx_bd++;
6591
6592                 /*
6593                  * Frames received on the NetXteme II are prepended
6594                  * with an l2_fhdr structure which provides status
6595                  * information about the received frame (including
6596                  * VLAN tags and checksum info).  The frames are
6597                  * also automatically adjusted to word align the IP
6598                  * header (i.e. two null bytes are inserted before
6599                  * the Ethernet header).  As a result the data
6600                  * DMA'd by the controller into the mbuf looks
6601                  * like this:
6602                  *
6603                  * +---------+-----+---------------------+-----+
6604                  * | l2_fhdr | pad | packet data         | FCS |
6605                  * +---------+-----+---------------------+-----+
6606                  *
6607                  * The l2_fhdr needs to be checked and skipped and
6608                  * the FCS needs to be stripped before sending the
6609                  * packet up the stack.
6610                  */
6611                 l2fhdr  = mtod(m0, struct l2_fhdr *);
6612
6613                 /* Get the packet data + FCS length and the status. */
6614                 pkt_len = l2fhdr->l2_fhdr_pkt_len;
6615                 status  = l2fhdr->l2_fhdr_status;
6616
6617                 /*
6618                  * Skip over the l2_fhdr and pad, resulting in the
6619                  * following data in the mbuf:
6620                  * +---------------------+-----+
6621                  * | packet data         | FCS |
6622                  * +---------------------+-----+
6623                  */
6624                 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN);
6625
6626                 /*
6627                  * When split header mode is used, an ethernet frame
6628                  * may be split across the receive chain and the
6629                  * page chain. If that occurs an mbuf cluster must be
6630                  * reassembled from the individual mbuf pieces.
6631                  */
6632                 if (bce_hdr_split == TRUE) {
6633                         /*
6634                          * Check whether the received frame fits in a single
6635                          * mbuf or not (i.e. packet data + FCS <=
6636                          * sc->rx_bd_mbuf_data_len bytes).
6637                          */
6638                         if (pkt_len > m0->m_len) {
6639                                 /*
6640                                  * The received frame is larger than a single mbuf.
6641                                  * If the frame was a TCP frame then only the TCP
6642                                  * header is placed in the mbuf, the remaining
6643                                  * payload (including FCS) is placed in the page
6644                                  * chain, the SPLIT flag is set, and the header
6645                                  * length is placed in the IP checksum field.
6646                                  * If the frame is not a TCP frame then the mbuf
6647                                  * is filled and the remaining bytes are placed
6648                                  * in the page chain.
6649                                  */
6650
6651                                 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large "
6652                                         "packet.\n", __FUNCTION__);
6653                                 DBRUN(sc->split_header_frames_rcvd++);
6654
6655                                 /*
6656                                  * When the page chain is enabled and the TCP
6657                                  * header has been split from the TCP payload,
6658                                  * the ip_xsum structure will reflect the length
6659                                  * of the TCP header, not the IP checksum.  Set
6660                                  * the packet length of the mbuf accordingly.
6661                                  */
6662                                 if (status & L2_FHDR_STATUS_SPLIT) {
6663                                         m0->m_len = l2fhdr->l2_fhdr_ip_xsum;
6664                                         DBRUN(sc->split_header_tcp_frames_rcvd++);
6665                                 }
6666
6667                                 rem_len = pkt_len - m0->m_len;
6668
6669                                 /* Pull mbufs off the page chain for any remaining data. */
6670                                 while (rem_len > 0) {
6671                                         struct mbuf *m_pg;
6672
6673                                         sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons);
6674
6675                                         /* Remove the mbuf from the page chain. */
6676                                         m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx];
6677                                         sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL;
6678                                         DBRUN(sc->debug_pg_mbuf_alloc--);
6679                                         sc->free_pg_bd++;
6680
6681                                         /* Unmap the page chain mbuf from DMA space. */
6682                                         bus_dmamap_sync(sc->pg_mbuf_tag,
6683                                                 sc->pg_mbuf_map[sw_pg_cons_idx],
6684                                                 BUS_DMASYNC_POSTREAD);
6685                                         bus_dmamap_unload(sc->pg_mbuf_tag,
6686                                                 sc->pg_mbuf_map[sw_pg_cons_idx]);
6687
6688                                         /* Adjust the mbuf length. */
6689                                         if (rem_len < m_pg->m_len) {
6690                                                 /* The mbuf chain is complete. */
6691                                                 m_pg->m_len = rem_len;
6692                                                 rem_len = 0;
6693                                         } else {
6694                                                 /* More packet data is waiting. */
6695                                                 rem_len -= m_pg->m_len;
6696                                         }
6697
6698                                         /* Concatenate the mbuf cluster to the mbuf. */
6699                                         m_cat(m0, m_pg);
6700
6701                                         sw_pg_cons = NEXT_PG_BD(sw_pg_cons);
6702                                 }
6703
6704                                 /* Set the total packet length. */
6705                                 m0->m_pkthdr.len = pkt_len;
6706
6707                         } else {
6708                                 /*
6709                                  * The received packet is small and fits in a
6710                                  * single mbuf (i.e. the l2_fhdr + pad + packet +
6711                                  * FCS <= MHLEN).  In other words, the packet is
6712                                  * 154 bytes or less in size.
6713                                  */
6714
6715                                 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small "
6716                                         "packet.\n", __FUNCTION__);
6717
6718                                 /* Set the total packet length. */
6719                                 m0->m_pkthdr.len = m0->m_len = pkt_len;
6720                         }
6721                 } else
6722                         /* Set the total packet length. */
6723                         m0->m_pkthdr.len = m0->m_len = pkt_len;
6724
6725                 /* Remove the trailing Ethernet FCS. */
6726                 m_adj(m0, -ETHER_CRC_LEN);
6727
6728                 /* Check that the resulting mbuf chain is valid. */
6729                 DBRUN(m_sanity(m0, FALSE));
6730                 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) |
6731                     (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)),
6732                     BCE_PRINTF("Invalid Ethernet frame size!\n");
6733                     m_print(m0, 128));
6734
6735                 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control),
6736                     sc->l2fhdr_error_sim_count++;
6737                     status = status | L2_FHDR_ERRORS_PHY_DECODE);
6738
6739                 /* Check the received frame for errors. */
6740                 if (status & (L2_FHDR_ERRORS_BAD_CRC |
6741                     L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT |
6742                     L2_FHDR_ERRORS_TOO_SHORT  | L2_FHDR_ERRORS_GIANT_FRAME)) {
6743
6744                         /* Log the error and release the mbuf. */
6745                         sc->l2fhdr_error_count++;
6746                         m_freem(m0);
6747                         m0 = NULL;
6748                         goto bce_rx_intr_next_rx;
6749                 }
6750
6751                 /* Send the packet to the appropriate interface. */
6752                 m0->m_pkthdr.rcvif = ifp;
6753
6754                 /* Assume no hardware checksum. */
6755                 m0->m_pkthdr.csum_flags = 0;
6756
6757                 /* Validate the checksum if offload enabled. */
6758                 if (ifp->if_capenable & IFCAP_RXCSUM) {
6759                         /* Check for an IP datagram. */
6760                         if (!(status & L2_FHDR_STATUS_SPLIT) &&
6761                             (status & L2_FHDR_STATUS_IP_DATAGRAM)) {
6762                                 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
6763                                 DBRUN(sc->csum_offload_ip++);
6764                                 /* Check if the IP checksum is valid. */
6765                                 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0)
6766                                         m0->m_pkthdr.csum_flags |=
6767                                             CSUM_IP_VALID;
6768                         }
6769
6770                         /* Check for a valid TCP/UDP frame. */
6771                         if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
6772                             L2_FHDR_STATUS_UDP_DATAGRAM)) {
6773
6774                                 /* Check for a good TCP/UDP checksum. */
6775                                 if ((status & (L2_FHDR_ERRORS_TCP_XSUM |
6776                                     L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
6777                                         DBRUN(sc->csum_offload_tcp_udp++);
6778                                         m0->m_pkthdr.csum_data =
6779                                             l2fhdr->l2_fhdr_tcp_udp_xsum;
6780                                         m0->m_pkthdr.csum_flags |=
6781                                             (CSUM_DATA_VALID
6782                                             | CSUM_PSEUDO_HDR);
6783                                 }
6784                         }
6785                 }
6786
6787                 /* Attach the VLAN tag. */
6788                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
6789                     !(sc->rx_mode & BCE_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
6790                         DBRUN(sc->vlan_tagged_frames_rcvd++);
6791                         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
6792                                 DBRUN(sc->vlan_tagged_frames_stripped++);
6793                                 m0->m_pkthdr.ether_vtag =
6794                                     l2fhdr->l2_fhdr_vlan_tag;
6795                                 m0->m_flags |= M_VLANTAG;
6796                         } else {
6797                                 /*
6798                                  * bce(4) controllers can't disable VLAN
6799                                  * tag stripping if management firmware
6800                                  * (ASF/IPMI/UMP) is running. So we always
6801                                  * strip VLAN tag and manually reconstruct
6802                                  * the VLAN frame by appending stripped
6803                                  * VLAN tag in driver if VLAN tag stripping
6804                                  * was disabled.
6805                                  *
6806                                  * TODO: LLC SNAP handling.
6807                                  */
6808                                 bcopy(mtod(m0, uint8_t *),
6809                                     mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN,
6810                                     ETHER_ADDR_LEN * 2);
6811                                 m0->m_data -= ETHER_VLAN_ENCAP_LEN;
6812                                 vh = mtod(m0, struct ether_vlan_header *);
6813                                 vh->evl_encap_proto = htons(ETHERTYPE_VLAN);
6814                                 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag);
6815                                 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN;
6816                                 m0->m_len += ETHER_VLAN_ENCAP_LEN;
6817                         }
6818                 }
6819
6820                 /* Increment received packet statistics. */
6821                 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
6822
6823 bce_rx_intr_next_rx:
6824                 sw_rx_cons = NEXT_RX_BD(sw_rx_cons);
6825
6826                 /* If we have a packet, pass it up the stack */
6827                 if (m0) {
6828                         /* Make sure we don't lose our place when we release the lock. */
6829                         sc->rx_cons = sw_rx_cons;
6830                         sc->pg_cons = sw_pg_cons;
6831
6832                         BCE_UNLOCK(sc);
6833                         (*ifp->if_input)(ifp, m0);
6834                         BCE_LOCK(sc);
6835
6836                         /* Recover our place. */
6837                         sw_rx_cons = sc->rx_cons;
6838                         sw_pg_cons = sc->pg_cons;
6839                 }
6840
6841                 /* Refresh hw_cons to see if there's new work */
6842                 if (sw_rx_cons == hw_rx_cons)
6843                         hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6844         }
6845
6846         /* No new packets.  Refill the page chain. */
6847         if (bce_hdr_split == TRUE) {
6848                 sc->pg_cons = sw_pg_cons;
6849                 bce_fill_pg_chain(sc);
6850         }
6851
6852         /* No new packets.  Refill the RX chain. */
6853         sc->rx_cons = sw_rx_cons;
6854         bce_fill_rx_chain(sc);
6855
6856         /* Prepare the page chain pages to be accessed by the NIC. */
6857         for (int i = 0; i < sc->rx_pages; i++)
6858                 bus_dmamap_sync(sc->rx_bd_chain_tag,
6859                     sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6860
6861         if (bce_hdr_split == TRUE) {
6862                 for (int i = 0; i < sc->pg_pages; i++)
6863                         bus_dmamap_sync(sc->pg_bd_chain_tag,
6864                             sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6865         }
6866
6867         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, "
6868             "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6869             __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6870         DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6871 }
6872
6873
6874 /****************************************************************************/
6875 /* Reads the transmit consumer value from the status block (skipping over   */
6876 /* chain page pointer if necessary).                                        */
6877 /*                                                                          */
6878 /* Returns:                                                                 */
6879 /*   hw_cons                                                                */
6880 /****************************************************************************/
6881 static inline u16
6882 bce_get_hw_tx_cons(struct bce_softc *sc)
6883 {
6884         u16 hw_cons;
6885
6886         mb();
6887         hw_cons = sc->status_block->status_tx_quick_consumer_index0;
6888         if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
6889                 hw_cons++;
6890
6891         return hw_cons;
6892 }
6893
6894
6895 /****************************************************************************/
6896 /* Handles transmit completion interrupt events.                            */
6897 /*                                                                          */
6898 /* Returns:                                                                 */
6899 /*   Nothing.                                                               */
6900 /****************************************************************************/
6901 static void
6902 bce_tx_intr(struct bce_softc *sc)
6903 {
6904         struct ifnet *ifp = sc->bce_ifp;
6905         u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
6906
6907         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
6908         DBRUN(sc->interrupts_tx++);
6909         DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, "
6910             "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
6911             __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
6912
6913         BCE_LOCK_ASSERT(sc);
6914
6915         /* Get the hardware's view of the TX consumer index. */
6916         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6917         sw_tx_cons = sc->tx_cons;
6918
6919         /* Prevent speculative reads of the status block. */
6920         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6921             BUS_SPACE_BARRIER_READ);
6922
6923         /* Cycle through any completed TX chain page entries. */
6924         while (sw_tx_cons != hw_tx_cons) {
6925 #ifdef BCE_DEBUG
6926                 struct tx_bd *txbd = NULL;
6927 #endif
6928                 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
6929
6930                 DBPRINT(sc, BCE_INFO_SEND,
6931                     "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
6932                     "sw_tx_chain_cons = 0x%04X\n",
6933                     __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
6934
6935                 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC),
6936                     BCE_PRINTF("%s(%d): TX chain consumer out of range! "
6937                     " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons,
6938                     (int) MAX_TX_BD_ALLOC);
6939                     bce_breakpoint(sc));
6940
6941                 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
6942                     [TX_IDX(sw_tx_chain_cons)]);
6943
6944                 DBRUNIF((txbd == NULL),
6945                     BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n",
6946                     __FILE__, __LINE__, sw_tx_chain_cons);
6947                     bce_breakpoint(sc));
6948
6949                 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__);
6950                     bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
6951
6952                 /*
6953                  * Free the associated mbuf. Remember
6954                  * that only the last tx_bd of a packet
6955                  * has an mbuf pointer and DMA map.
6956                  */
6957                 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
6958
6959                         /* Validate that this is the last tx_bd. */
6960                         DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
6961                             BCE_PRINTF("%s(%d): tx_bd END flag not set but "
6962                             "txmbuf == NULL!\n", __FILE__, __LINE__);
6963                             bce_breakpoint(sc));
6964
6965                         DBRUNMSG(BCE_INFO_SEND,
6966                             BCE_PRINTF("%s(): Unloading map/freeing mbuf "
6967                             "from tx_bd[0x%04X]\n", __FUNCTION__,
6968                             sw_tx_chain_cons));
6969
6970                         /* Unmap the mbuf. */
6971                         bus_dmamap_unload(sc->tx_mbuf_tag,
6972                             sc->tx_mbuf_map[sw_tx_chain_cons]);
6973
6974                         /* Free the mbuf. */
6975                         m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
6976                         sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
6977                         DBRUN(sc->debug_tx_mbuf_alloc--);
6978
6979                         if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
6980                 }
6981
6982                 sc->used_tx_bd--;
6983                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
6984
6985                 /* Refresh hw_cons to see if there's new work. */
6986                 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6987
6988                 /* Prevent speculative reads of the status block. */
6989                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6990                     BUS_SPACE_BARRIER_READ);
6991         }
6992
6993         /* Clear the TX timeout timer. */
6994         sc->watchdog_timer = 0;
6995
6996         /* Clear the tx hardware queue full flag. */
6997         if (sc->used_tx_bd < sc->max_tx_bd) {
6998                 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE),
6999                     DBPRINT(sc, BCE_INFO_SEND,
7000                     "%s(): Open TX chain! %d/%d (used/total)\n",
7001                     __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd));
7002                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
7003         }
7004
7005         sc->tx_cons = sw_tx_cons;
7006
7007         DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, "
7008             "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
7009             __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
7010         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
7011 }
7012
7013
7014 /****************************************************************************/
7015 /* Disables interrupt generation.                                           */
7016 /*                                                                          */
7017 /* Returns:                                                                 */
7018 /*   Nothing.                                                               */
7019 /****************************************************************************/
7020 static void
7021 bce_disable_intr(struct bce_softc *sc)
7022 {
7023         DBENTER(BCE_VERBOSE_INTR);
7024
7025         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
7026         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
7027
7028         DBEXIT(BCE_VERBOSE_INTR);
7029 }
7030
7031
7032 /****************************************************************************/
7033 /* Enables interrupt generation.                                            */
7034 /*                                                                          */
7035 /* Returns:                                                                 */
7036 /*   Nothing.                                                               */
7037 /****************************************************************************/
7038 static void
7039 bce_enable_intr(struct bce_softc *sc, int coal_now)
7040 {
7041         DBENTER(BCE_VERBOSE_INTR);
7042
7043         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7044             BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
7045             BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
7046
7047         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7048             BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
7049
7050         /* Force an immediate interrupt (whether there is new data or not). */
7051         if (coal_now)
7052                 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
7053
7054         DBEXIT(BCE_VERBOSE_INTR);
7055 }
7056
7057
7058 /****************************************************************************/
7059 /* Handles controller initialization.                                       */
7060 /*                                                                          */
7061 /* Returns:                                                                 */
7062 /*   Nothing.                                                               */
7063 /****************************************************************************/
7064 static void
7065 bce_init_locked(struct bce_softc *sc)
7066 {
7067         struct ifnet *ifp;
7068         u32 ether_mtu = 0;
7069
7070         DBENTER(BCE_VERBOSE_RESET);
7071
7072         BCE_LOCK_ASSERT(sc);
7073
7074         ifp = sc->bce_ifp;
7075
7076         /* Check if the driver is still running and bail out if it is. */
7077         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
7078                 goto bce_init_locked_exit;
7079
7080         bce_stop(sc);
7081
7082         if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
7083                 BCE_PRINTF("%s(%d): Controller reset failed!\n",
7084                     __FILE__, __LINE__);
7085                 goto bce_init_locked_exit;
7086         }
7087
7088         if (bce_chipinit(sc)) {
7089                 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
7090                     __FILE__, __LINE__);
7091                 goto bce_init_locked_exit;
7092         }
7093
7094         if (bce_blockinit(sc)) {
7095                 BCE_PRINTF("%s(%d): Block initialization failed!\n",
7096                     __FILE__, __LINE__);
7097                 goto bce_init_locked_exit;
7098         }
7099
7100         /* Load our MAC address. */
7101         bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN);
7102         bce_set_mac_addr(sc);
7103
7104         if (bce_hdr_split == FALSE)
7105                 bce_get_rx_buffer_sizes(sc, ifp->if_mtu);
7106         /*
7107          * Calculate and program the hardware Ethernet MTU
7108          * size. Be generous on the receive if we have room
7109          * and allowed by the user.
7110          */
7111         if (bce_strict_rx_mtu == TRUE)
7112                 ether_mtu = ifp->if_mtu;
7113         else {
7114                 if (bce_hdr_split == TRUE) {
7115                         if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len + MCLBYTES)
7116                                 ether_mtu = sc->rx_bd_mbuf_data_len +
7117                                     MCLBYTES;
7118                         else
7119                                 ether_mtu = ifp->if_mtu;
7120                 } else {
7121                         if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len)
7122                                 ether_mtu = sc->rx_bd_mbuf_data_len;
7123                         else
7124                                 ether_mtu = ifp->if_mtu;
7125                 }
7126         }
7127
7128         ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
7129
7130         DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n",
7131             __FUNCTION__, ether_mtu);
7132
7133         /* Program the mtu, enabling jumbo frame support if necessary. */
7134         if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN))
7135                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
7136                     min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
7137                     BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
7138         else
7139                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
7140
7141         /* Program appropriate promiscuous/multicast filtering. */
7142         bce_set_rx_mode(sc);
7143
7144         if (bce_hdr_split == TRUE) {
7145                 /* Init page buffer descriptor chain. */
7146                 bce_init_pg_chain(sc);
7147         }
7148
7149         /* Init RX buffer descriptor chain. */
7150         bce_init_rx_chain(sc);
7151
7152         /* Init TX buffer descriptor chain. */
7153         bce_init_tx_chain(sc);
7154
7155         /* Enable host interrupts. */
7156         bce_enable_intr(sc, 1);
7157
7158         bce_ifmedia_upd_locked(ifp);
7159
7160         /* Let the OS know the driver is up and running. */
7161         ifp->if_drv_flags |= IFF_DRV_RUNNING;
7162         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
7163
7164         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
7165
7166 bce_init_locked_exit:
7167         DBEXIT(BCE_VERBOSE_RESET);
7168 }
7169
7170
7171 /****************************************************************************/
7172 /* Initialize the controller just enough so that any management firmware    */
7173 /* running on the device will continue to operate correctly.                */
7174 /*                                                                          */
7175 /* Returns:                                                                 */
7176 /*   Nothing.                                                               */
7177 /****************************************************************************/
7178 static void
7179 bce_mgmt_init_locked(struct bce_softc *sc)
7180 {
7181         struct ifnet *ifp;
7182
7183         DBENTER(BCE_VERBOSE_RESET);
7184
7185         BCE_LOCK_ASSERT(sc);
7186
7187         /* Bail out if management firmware is not running. */
7188         if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) {
7189                 DBPRINT(sc, BCE_VERBOSE_SPECIAL,
7190                     "No management firmware running...\n");
7191                 goto bce_mgmt_init_locked_exit;
7192         }
7193
7194         ifp = sc->bce_ifp;
7195
7196         /* Enable all critical blocks in the MAC. */
7197         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
7198         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
7199         DELAY(20);
7200
7201         bce_ifmedia_upd_locked(ifp);
7202
7203 bce_mgmt_init_locked_exit:
7204         DBEXIT(BCE_VERBOSE_RESET);
7205 }
7206
7207
7208 /****************************************************************************/
7209 /* Handles controller initialization when called from an unlocked routine.  */
7210 /*                                                                          */
7211 /* Returns:                                                                 */
7212 /*   Nothing.                                                               */
7213 /****************************************************************************/
7214 static void
7215 bce_init(void *xsc)
7216 {
7217         struct bce_softc *sc = xsc;
7218
7219         DBENTER(BCE_VERBOSE_RESET);
7220
7221         BCE_LOCK(sc);
7222         bce_init_locked(sc);
7223         BCE_UNLOCK(sc);
7224
7225         DBEXIT(BCE_VERBOSE_RESET);
7226 }
7227
7228
7229 /****************************************************************************/
7230 /* Modifies an mbuf for TSO on the hardware.                                */
7231 /*                                                                          */
7232 /* Returns:                                                                 */
7233 /*   Pointer to a modified mbuf.                                            */
7234 /****************************************************************************/
7235 static struct mbuf *
7236 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags)
7237 {
7238         struct mbuf *m;
7239         struct ether_header *eh;
7240         struct ip *ip;
7241         struct tcphdr *th;
7242         u16 etype;
7243         int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0;
7244
7245         DBRUN(sc->tso_frames_requested++);
7246
7247         /* Controller may modify mbuf chains. */
7248         if (M_WRITABLE(*m_head) == 0) {
7249                 m = m_dup(*m_head, M_NOWAIT);
7250                 m_freem(*m_head);
7251                 if (m == NULL) {
7252                         sc->mbuf_alloc_failed_count++;
7253                         *m_head = NULL;
7254                         return (NULL);
7255                 }
7256                 *m_head = m;
7257         }
7258
7259         /*
7260          * For TSO the controller needs two pieces of info,
7261          * the MSS and the IP+TCP options length.
7262          */
7263         m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip));
7264         if (m == NULL) {
7265                 *m_head = NULL;
7266                 return (NULL);
7267         }
7268         eh = mtod(m, struct ether_header *);
7269         etype = ntohs(eh->ether_type);
7270
7271         /* Check for supported TSO Ethernet types (only IPv4 for now) */
7272         switch (etype) {
7273         case ETHERTYPE_IP:
7274                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7275                 /* TSO only supported for TCP protocol. */
7276                 if (ip->ip_p != IPPROTO_TCP) {
7277                         BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n",
7278                             __FILE__, __LINE__);
7279                         m_freem(*m_head);
7280                         *m_head = NULL;
7281                         return (NULL);
7282                 }
7283
7284                 /* Get IP header length in bytes (min 20) */
7285                 ip_hlen = ip->ip_hl << 2;
7286                 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen +
7287                     sizeof(struct tcphdr));
7288                 if (m == NULL) {
7289                         *m_head = NULL;
7290                         return (NULL);
7291                 }
7292
7293                 /* Get the TCP header length in bytes (min 20) */
7294                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7295                 th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
7296                 tcp_hlen = (th->th_off << 2);
7297
7298                 /* Make sure all IP/TCP options live in the same buffer. */
7299                 m = m_pullup(*m_head,  sizeof(struct ether_header)+ ip_hlen +
7300                     tcp_hlen);
7301                 if (m == NULL) {
7302                         *m_head = NULL;
7303                         return (NULL);
7304                 }
7305
7306                 /* Clear IP header length and checksum, will be calc'd by h/w. */
7307                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7308                 ip_len = ip->ip_len;
7309                 ip->ip_len = 0;
7310                 ip->ip_sum = 0;
7311                 break;
7312         case ETHERTYPE_IPV6:
7313                 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n",
7314                     __FILE__, __LINE__);
7315                 m_freem(*m_head);
7316                 *m_head = NULL;
7317                 return (NULL);
7318                 /* NOT REACHED */
7319         default:
7320                 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n",
7321                     __FILE__, __LINE__);
7322                 m_freem(*m_head);
7323                 *m_head = NULL;
7324                 return (NULL);
7325         }
7326
7327         hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen;
7328
7329         DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, "
7330             "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n",
7331             __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen,
7332             tcp_hlen, ip_len);
7333
7334         /* Set the LSO flag in the TX BD */
7335         *flags |= TX_BD_FLAGS_SW_LSO;
7336
7337         /* Set the length of IP + TCP options (in 32 bit words) */
7338         *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) -
7339             sizeof(struct tcphdr)) >> 2) << 8);
7340
7341         DBRUN(sc->tso_frames_completed++);
7342         return (*m_head);
7343 }
7344
7345
7346 /****************************************************************************/
7347 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
7348 /* memory visible to the controller.                                        */
7349 /*                                                                          */
7350 /* Returns:                                                                 */
7351 /*   0 for success, positive value for failure.                             */
7352 /* Modified:                                                                */
7353 /*   m_head: May be set to NULL if MBUF is excessively fragmented.          */
7354 /****************************************************************************/
7355 static int
7356 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head)
7357 {
7358         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
7359         bus_dmamap_t map;
7360         struct tx_bd *txbd = NULL;
7361         struct mbuf *m0;
7362         u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0;
7363         u32 prod_bseq;
7364
7365 #ifdef BCE_DEBUG
7366         u16 debug_prod;
7367 #endif
7368
7369         int i, error, nsegs, rc = 0;
7370
7371         DBENTER(BCE_VERBOSE_SEND);
7372
7373         /* Make sure we have room in the TX chain. */
7374         if (sc->used_tx_bd >= sc->max_tx_bd)
7375                 goto bce_tx_encap_exit;
7376
7377         /* Transfer any checksum offload flags to the bd. */
7378         m0 = *m_head;
7379         if (m0->m_pkthdr.csum_flags) {
7380                 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
7381                         m0 = bce_tso_setup(sc, m_head, &flags);
7382                         if (m0 == NULL) {
7383                                 DBRUN(sc->tso_frames_failed++);
7384                                 goto bce_tx_encap_exit;
7385                         }
7386                         mss = htole16(m0->m_pkthdr.tso_segsz);
7387                 } else {
7388                         if (m0->m_pkthdr.csum_flags & CSUM_IP)
7389                                 flags |= TX_BD_FLAGS_IP_CKSUM;
7390                         if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
7391                                 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
7392                 }
7393         }
7394
7395         /* Transfer any VLAN tags to the bd. */
7396         if (m0->m_flags & M_VLANTAG) {
7397                 flags |= TX_BD_FLAGS_VLAN_TAG;
7398                 vlan_tag = m0->m_pkthdr.ether_vtag;
7399         }
7400
7401         /* Map the mbuf into DMAable memory. */
7402         prod = sc->tx_prod;
7403         chain_prod = TX_CHAIN_IDX(prod);
7404         map = sc->tx_mbuf_map[chain_prod];
7405
7406         /* Map the mbuf into our DMA address space. */
7407         error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
7408             segs, &nsegs, BUS_DMA_NOWAIT);
7409
7410         /* Check if the DMA mapping was successful */
7411         if (error == EFBIG) {
7412                 sc->mbuf_frag_count++;
7413
7414                 /* Try to defrag the mbuf. */
7415                 m0 = m_collapse(*m_head, M_NOWAIT, BCE_MAX_SEGMENTS);
7416                 if (m0 == NULL) {
7417                         /* Defrag was unsuccessful */
7418                         m_freem(*m_head);
7419                         *m_head = NULL;
7420                         sc->mbuf_alloc_failed_count++;
7421                         rc = ENOBUFS;
7422                         goto bce_tx_encap_exit;
7423                 }
7424
7425                 /* Defrag was successful, try mapping again */
7426                 *m_head = m0;
7427                 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag,
7428                     map, m0, segs, &nsegs, BUS_DMA_NOWAIT);
7429
7430                 /* Still getting an error after a defrag. */
7431                 if (error == ENOMEM) {
7432                         /* Insufficient DMA buffers available. */
7433                         sc->dma_map_addr_tx_failed_count++;
7434                         rc = error;
7435                         goto bce_tx_encap_exit;
7436                 } else if (error != 0) {
7437                         /* Release it and return an error. */
7438                         BCE_PRINTF("%s(%d): Unknown error mapping mbuf into "
7439                             "TX chain!\n", __FILE__, __LINE__);
7440                         m_freem(m0);
7441                         *m_head = NULL;
7442                         sc->dma_map_addr_tx_failed_count++;
7443                         rc = ENOBUFS;
7444                         goto bce_tx_encap_exit;
7445                 }
7446         } else if (error == ENOMEM) {
7447                 /* Insufficient DMA buffers available. */
7448                 sc->dma_map_addr_tx_failed_count++;
7449                 rc = error;
7450                 goto bce_tx_encap_exit;
7451         } else if (error != 0) {
7452                 m_freem(m0);
7453                 *m_head = NULL;
7454                 sc->dma_map_addr_tx_failed_count++;
7455                 rc = error;
7456                 goto bce_tx_encap_exit;
7457         }
7458
7459         /* Make sure there's room in the chain */
7460         if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) {
7461                 bus_dmamap_unload(sc->tx_mbuf_tag, map);
7462                 rc = ENOBUFS;
7463                 goto bce_tx_encap_exit;
7464         }
7465
7466         /* prod points to an empty tx_bd at this point. */
7467         prod_bseq  = sc->tx_prod_bseq;
7468
7469 #ifdef BCE_DEBUG
7470         debug_prod = chain_prod;
7471 #endif
7472
7473         DBPRINT(sc, BCE_INFO_SEND,
7474             "%s(start): prod = 0x%04X, chain_prod = 0x%04X, "
7475             "prod_bseq = 0x%08X\n",
7476             __FUNCTION__, prod, chain_prod, prod_bseq);
7477
7478         /*
7479          * Cycle through each mbuf segment that makes up
7480          * the outgoing frame, gathering the mapping info
7481          * for that segment and creating a tx_bd for
7482          * the mbuf.
7483          */
7484         for (i = 0; i < nsegs ; i++) {
7485
7486                 chain_prod = TX_CHAIN_IDX(prod);
7487                 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)]
7488                     [TX_IDX(chain_prod)];
7489
7490                 txbd->tx_bd_haddr_lo =
7491                     htole32(BCE_ADDR_LO(segs[i].ds_addr));
7492                 txbd->tx_bd_haddr_hi =
7493                     htole32(BCE_ADDR_HI(segs[i].ds_addr));
7494                 txbd->tx_bd_mss_nbytes = htole32(mss << 16) |
7495                     htole16(segs[i].ds_len);
7496                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
7497                 txbd->tx_bd_flags = htole16(flags);
7498                 prod_bseq += segs[i].ds_len;
7499                 if (i == 0)
7500                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
7501                 prod = NEXT_TX_BD(prod);
7502         }
7503
7504         /* Set the END flag on the last TX buffer descriptor. */
7505         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
7506
7507         DBRUNMSG(BCE_EXTREME_SEND,
7508             bce_dump_tx_chain(sc, debug_prod, nsegs));
7509
7510         /*
7511          * Ensure that the mbuf pointer for this transmission
7512          * is placed at the array index of the last
7513          * descriptor in this chain.  This is done
7514          * because a single map is used for all
7515          * segments of the mbuf and we don't want to
7516          * unload the map before all of the segments
7517          * have been freed.
7518          */
7519         sc->tx_mbuf_ptr[chain_prod] = m0;
7520         sc->used_tx_bd += nsegs;
7521
7522         /* Update some debug statistic counters */
7523         DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
7524             sc->tx_hi_watermark = sc->used_tx_bd);
7525         DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
7526         DBRUNIF(sc->debug_tx_mbuf_alloc++);
7527
7528         DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1));
7529
7530         /* prod points to the next free tx_bd at this point. */
7531         sc->tx_prod = prod;
7532         sc->tx_prod_bseq = prod_bseq;
7533
7534         /* Tell the chip about the waiting TX frames. */
7535         REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) +
7536             BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod);
7537         REG_WR(sc, MB_GET_CID_ADDR(TX_CID) +
7538             BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq);
7539
7540 bce_tx_encap_exit:
7541         DBEXIT(BCE_VERBOSE_SEND);
7542         return(rc);
7543 }
7544
7545
7546 /****************************************************************************/
7547 /* Main transmit routine when called from another routine with a lock.      */
7548 /*                                                                          */
7549 /* Returns:                                                                 */
7550 /*   Nothing.                                                               */
7551 /****************************************************************************/
7552 static void
7553 bce_start_locked(struct ifnet *ifp)
7554 {
7555         struct bce_softc *sc = ifp->if_softc;
7556         struct mbuf *m_head = NULL;
7557         int count = 0;
7558         u16 tx_prod, tx_chain_prod;
7559
7560         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7561
7562         BCE_LOCK_ASSERT(sc);
7563
7564         /* prod points to the next free tx_bd. */
7565         tx_prod = sc->tx_prod;
7566         tx_chain_prod = TX_CHAIN_IDX(tx_prod);
7567
7568         DBPRINT(sc, BCE_INFO_SEND,
7569             "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
7570             "tx_prod_bseq = 0x%08X\n",
7571             __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq);
7572
7573         /* If there's no link or the transmit queue is empty then just exit. */
7574         if (sc->bce_link_up == FALSE) {
7575                 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n",
7576                     __FUNCTION__);
7577                 goto bce_start_locked_exit;
7578         }
7579
7580         if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
7581                 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n",
7582                     __FUNCTION__);
7583                 goto bce_start_locked_exit;
7584         }
7585
7586         /*
7587          * Keep adding entries while there is space in the ring.
7588          */
7589         while (sc->used_tx_bd < sc->max_tx_bd) {
7590
7591                 /* Check for any frames to send. */
7592                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
7593
7594                 /* Stop when the transmit queue is empty. */
7595                 if (m_head == NULL)
7596                         break;
7597
7598                 /*
7599                  * Pack the data into the transmit ring. If we
7600                  * don't have room, place the mbuf back at the
7601                  * head of the queue and set the OACTIVE flag
7602                  * to wait for the NIC to drain the chain.
7603                  */
7604                 if (bce_tx_encap(sc, &m_head)) {
7605                         if (m_head != NULL)
7606                                 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
7607                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
7608                         DBPRINT(sc, BCE_INFO_SEND,
7609                             "TX chain is closed for business! Total "
7610                             "tx_bd used = %d\n", sc->used_tx_bd);
7611                         break;
7612                 }
7613
7614                 count++;
7615
7616                 /* Send a copy of the frame to any BPF listeners. */
7617                 ETHER_BPF_MTAP(ifp, m_head);
7618         }
7619
7620         /* Exit if no packets were dequeued. */
7621         if (count == 0) {
7622                 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were "
7623                     "dequeued\n", __FUNCTION__);
7624                 goto bce_start_locked_exit;
7625         }
7626
7627         DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into "
7628             "send queue.\n", __FUNCTION__, count);
7629
7630         /* Set the tx timeout. */
7631         sc->watchdog_timer = BCE_TX_TIMEOUT;
7632
7633         DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID));
7634         DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc));
7635
7636 bce_start_locked_exit:
7637         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7638 }
7639
7640
7641 /****************************************************************************/
7642 /* Main transmit routine when called from another routine without a lock.   */
7643 /*                                                                          */
7644 /* Returns:                                                                 */
7645 /*   Nothing.                                                               */
7646 /****************************************************************************/
7647 static void
7648 bce_start(struct ifnet *ifp)
7649 {
7650         struct bce_softc *sc = ifp->if_softc;
7651
7652         DBENTER(BCE_VERBOSE_SEND);
7653
7654         BCE_LOCK(sc);
7655         bce_start_locked(ifp);
7656         BCE_UNLOCK(sc);
7657
7658         DBEXIT(BCE_VERBOSE_SEND);
7659 }
7660
7661
7662 /****************************************************************************/
7663 /* Handles any IOCTL calls from the operating system.                       */
7664 /*                                                                          */
7665 /* Returns:                                                                 */
7666 /*   0 for success, positive value for failure.                             */
7667 /****************************************************************************/
7668 static int
7669 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
7670 {
7671         struct bce_softc *sc = ifp->if_softc;
7672         struct ifreq *ifr = (struct ifreq *) data;
7673         struct mii_data *mii;
7674         int mask, error = 0;
7675
7676         DBENTER(BCE_VERBOSE_MISC);
7677
7678         switch(command) {
7679
7680         /* Set the interface MTU. */
7681         case SIOCSIFMTU:
7682                 /* Check that the MTU setting is supported. */
7683                 if ((ifr->ifr_mtu < BCE_MIN_MTU) ||
7684                         (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) {
7685                         error = EINVAL;
7686                         break;
7687                 }
7688
7689                 DBPRINT(sc, BCE_INFO_MISC,
7690                     "SIOCSIFMTU: Changing MTU from %d to %d\n",
7691                     (int) ifp->if_mtu, (int) ifr->ifr_mtu);
7692
7693                 BCE_LOCK(sc);
7694                 ifp->if_mtu = ifr->ifr_mtu;
7695                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7696                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
7697                         bce_init_locked(sc);
7698                 }
7699                 BCE_UNLOCK(sc);
7700                 break;
7701
7702         /* Set interface flags. */
7703         case SIOCSIFFLAGS:
7704                 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n");
7705
7706                 BCE_LOCK(sc);
7707
7708                 /* Check if the interface is up. */
7709                 if (ifp->if_flags & IFF_UP) {
7710                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7711                                 /* Change promiscuous/multicast flags as necessary. */
7712                                 bce_set_rx_mode(sc);
7713                         } else {
7714                                 /* Start the HW */
7715                                 bce_init_locked(sc);
7716                         }
7717                 } else {
7718                         /* The interface is down, check if driver is running. */
7719                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7720                                 bce_stop(sc);
7721
7722                                 /* If MFW is running, restart the controller a bit. */
7723                                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
7724                                         bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
7725                                         bce_chipinit(sc);
7726                                         bce_mgmt_init_locked(sc);
7727                                 }
7728                         }
7729                 }
7730
7731                 BCE_UNLOCK(sc);
7732                 break;
7733
7734         /* Add/Delete multicast address */
7735         case SIOCADDMULTI:
7736         case SIOCDELMULTI:
7737                 DBPRINT(sc, BCE_VERBOSE_MISC,
7738                     "Received SIOCADDMULTI/SIOCDELMULTI\n");
7739
7740                 BCE_LOCK(sc);
7741                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
7742                         bce_set_rx_mode(sc);
7743                 BCE_UNLOCK(sc);
7744
7745                 break;
7746
7747         /* Set/Get Interface media */
7748         case SIOCSIFMEDIA:
7749         case SIOCGIFMEDIA:
7750                 DBPRINT(sc, BCE_VERBOSE_MISC,
7751                     "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n");
7752                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
7753                         error = ifmedia_ioctl(ifp, ifr, &sc->bce_ifmedia,
7754                             command);
7755                 else {
7756                         mii = device_get_softc(sc->bce_miibus);
7757                         error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
7758                             command);
7759                 }
7760                 break;
7761
7762         /* Set interface capability */
7763         case SIOCSIFCAP:
7764                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
7765                 DBPRINT(sc, BCE_INFO_MISC,
7766                     "Received SIOCSIFCAP = 0x%08X\n", (u32) mask);
7767
7768                 /* Toggle the TX checksum capabilities enable flag. */
7769                 if (mask & IFCAP_TXCSUM &&
7770                     ifp->if_capabilities & IFCAP_TXCSUM) {
7771                         ifp->if_capenable ^= IFCAP_TXCSUM;
7772                         if (IFCAP_TXCSUM & ifp->if_capenable)
7773                                 ifp->if_hwassist |= BCE_IF_HWASSIST;
7774                         else
7775                                 ifp->if_hwassist &= ~BCE_IF_HWASSIST;
7776                 }
7777
7778                 /* Toggle the RX checksum capabilities enable flag. */
7779                 if (mask & IFCAP_RXCSUM &&
7780                     ifp->if_capabilities & IFCAP_RXCSUM)
7781                         ifp->if_capenable ^= IFCAP_RXCSUM;
7782
7783                 /* Toggle the TSO capabilities enable flag. */
7784                 if (bce_tso_enable && (mask & IFCAP_TSO4) &&
7785                     ifp->if_capabilities & IFCAP_TSO4) {
7786                         ifp->if_capenable ^= IFCAP_TSO4;
7787                         if (IFCAP_TSO4 & ifp->if_capenable)
7788                                 ifp->if_hwassist |= CSUM_TSO;
7789                         else
7790                                 ifp->if_hwassist &= ~CSUM_TSO;
7791                 }
7792
7793                 if (mask & IFCAP_VLAN_HWCSUM &&
7794                     ifp->if_capabilities & IFCAP_VLAN_HWCSUM)
7795                         ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
7796
7797                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
7798                     (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
7799                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
7800                 /*
7801                  * Don't actually disable VLAN tag stripping as
7802                  * management firmware (ASF/IPMI/UMP) requires the
7803                  * feature. If VLAN tag stripping is disabled driver
7804                  * will manually reconstruct the VLAN frame by
7805                  * appending stripped VLAN tag.
7806                  */
7807                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
7808                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) {
7809                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
7810                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
7811                             == 0)
7812                                 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
7813                 }
7814                 VLAN_CAPABILITIES(ifp);
7815                 break;
7816         default:
7817                 /* We don't know how to handle the IOCTL, pass it on. */
7818                 error = ether_ioctl(ifp, command, data);
7819                 break;
7820         }
7821
7822         DBEXIT(BCE_VERBOSE_MISC);
7823         return(error);
7824 }
7825
7826
7827 /****************************************************************************/
7828 /* Transmit timeout handler.                                                */
7829 /*                                                                          */
7830 /* Returns:                                                                 */
7831 /*   Nothing.                                                               */
7832 /****************************************************************************/
7833 static void
7834 bce_watchdog(struct bce_softc *sc)
7835 {
7836         uint32_t status;
7837
7838         DBENTER(BCE_EXTREME_SEND);
7839
7840         BCE_LOCK_ASSERT(sc);
7841
7842         status = 0;
7843         /* If the watchdog timer hasn't expired then just exit. */
7844         if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
7845                 goto bce_watchdog_exit;
7846
7847         status = REG_RD(sc, BCE_EMAC_RX_STATUS);
7848         /* If pause frames are active then don't reset the hardware. */
7849         if ((sc->bce_flags & BCE_USING_RX_FLOW_CONTROL) != 0) {
7850                 if ((status & BCE_EMAC_RX_STATUS_FFED) != 0) {
7851                         /*
7852                          * If link partner has us in XOFF state then wait for
7853                          * the condition to clear.
7854                          */
7855                         sc->watchdog_timer = BCE_TX_TIMEOUT;
7856                         goto bce_watchdog_exit;
7857                 } else if ((status & BCE_EMAC_RX_STATUS_FF_RECEIVED) != 0 &&
7858                         (status & BCE_EMAC_RX_STATUS_N_RECEIVED) != 0) {
7859                         /*
7860                          * If we're not currently XOFF'ed but have recently
7861                          * been XOFF'd/XON'd then assume that's delaying TX
7862                          * this time around.
7863                          */
7864                         sc->watchdog_timer = BCE_TX_TIMEOUT;
7865                         goto bce_watchdog_exit;
7866                 }
7867                 /*
7868                  * Any other condition is unexpected and the controller
7869                  * should be reset.
7870                  */
7871         }
7872
7873         BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n",
7874             __FILE__, __LINE__);
7875
7876         DBRUNMSG(BCE_INFO,
7877             bce_dump_driver_state(sc);
7878             bce_dump_status_block(sc);
7879             bce_dump_stats_block(sc);
7880             bce_dump_ftqs(sc);
7881             bce_dump_txp_state(sc, 0);
7882             bce_dump_rxp_state(sc, 0);
7883             bce_dump_tpat_state(sc, 0);
7884             bce_dump_cp_state(sc, 0);
7885             bce_dump_com_state(sc, 0));
7886
7887         DBRUN(bce_breakpoint(sc));
7888
7889         sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
7890
7891         bce_init_locked(sc);
7892         sc->watchdog_timeouts++;
7893
7894 bce_watchdog_exit:
7895         REG_WR(sc, BCE_EMAC_RX_STATUS, status);
7896         DBEXIT(BCE_EXTREME_SEND);
7897 }
7898
7899
7900 /*
7901  * Interrupt handler.
7902  */
7903 /****************************************************************************/
7904 /* Main interrupt entry point.  Verifies that the controller generated the  */
7905 /* interrupt and then calls a separate routine for handle the various       */
7906 /* interrupt causes (PHY, TX, RX).                                          */
7907 /*                                                                          */
7908 /* Returns:                                                                 */
7909 /*   Nothing.                                                               */
7910 /****************************************************************************/
7911 static void
7912 bce_intr(void *xsc)
7913 {
7914         struct bce_softc *sc;
7915         struct ifnet *ifp;
7916         u32 status_attn_bits;
7917         u16 hw_rx_cons, hw_tx_cons;
7918
7919         sc = xsc;
7920         ifp = sc->bce_ifp;
7921
7922         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
7923         DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
7924         DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc));
7925
7926         BCE_LOCK(sc);
7927
7928         DBRUN(sc->interrupts_generated++);
7929
7930         /* Synchnorize before we read from interface's status block */
7931         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
7932
7933         /*
7934          * If the hardware status block index matches the last value read
7935          * by the driver and we haven't asserted our interrupt then there's
7936          * nothing to do.  This may only happen in case of INTx due to the
7937          * interrupt arriving at the CPU before the status block is updated.
7938          */
7939         if ((sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) == 0 &&
7940             sc->status_block->status_idx == sc->last_status_idx &&
7941             (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
7942              BCE_PCICFG_MISC_STATUS_INTA_VALUE)) {
7943                 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n",
7944                     __FUNCTION__);
7945                 goto bce_intr_exit;
7946         }
7947
7948         /* Ack the interrupt and stop others from occurring. */
7949         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7950             BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
7951             BCE_PCICFG_INT_ACK_CMD_MASK_INT);
7952
7953         /* Check if the hardware has finished any work. */
7954         hw_rx_cons = bce_get_hw_rx_cons(sc);
7955         hw_tx_cons = bce_get_hw_tx_cons(sc);
7956
7957         /* Keep processing data as long as there is work to do. */
7958         for (;;) {
7959
7960                 status_attn_bits = sc->status_block->status_attn_bits;
7961
7962                 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control),
7963                     BCE_PRINTF("Simulating unexpected status attention "
7964                     "bit set.");
7965                     sc->unexpected_attention_sim_count++;
7966                     status_attn_bits = status_attn_bits |
7967                     STATUS_ATTN_BITS_PARITY_ERROR);
7968
7969                 /* Was it a link change interrupt? */
7970                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
7971                     (sc->status_block->status_attn_bits_ack &
7972                      STATUS_ATTN_BITS_LINK_STATE)) {
7973                         bce_phy_intr(sc);
7974
7975                         /* Clear transient updates during link state change. */
7976                         REG_WR(sc, BCE_HC_COMMAND, sc->hc_command |
7977                             BCE_HC_COMMAND_COAL_NOW_WO_INT);
7978                         REG_RD(sc, BCE_HC_COMMAND);
7979                 }
7980
7981                 /* If any other attention is asserted, the chip is toast. */
7982                 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
7983                     (sc->status_block->status_attn_bits_ack &
7984                     ~STATUS_ATTN_BITS_LINK_STATE))) {
7985
7986                         sc->unexpected_attention_count++;
7987
7988                         BCE_PRINTF("%s(%d): Fatal attention detected: "
7989                             "0x%08X\n", __FILE__, __LINE__,
7990                             sc->status_block->status_attn_bits);
7991
7992                         DBRUNMSG(BCE_FATAL,
7993                             if (unexpected_attention_sim_control == 0)
7994                                 bce_breakpoint(sc));
7995
7996                         bce_init_locked(sc);
7997                         goto bce_intr_exit;
7998                 }
7999
8000                 /* Check for any completed RX frames. */
8001                 if (hw_rx_cons != sc->hw_rx_cons)
8002                         bce_rx_intr(sc);
8003
8004                 /* Check for any completed TX frames. */
8005                 if (hw_tx_cons != sc->hw_tx_cons)
8006                         bce_tx_intr(sc);
8007
8008                 /* Save status block index value for the next interrupt. */
8009                 sc->last_status_idx = sc->status_block->status_idx;
8010
8011                 /*
8012                  * Prevent speculative reads from getting
8013                  * ahead of the status block.
8014                  */
8015                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
8016                     BUS_SPACE_BARRIER_READ);
8017
8018                 /*
8019                  * If there's no work left then exit the
8020                  * interrupt service routine.
8021                  */
8022                 hw_rx_cons = bce_get_hw_rx_cons(sc);
8023                 hw_tx_cons = bce_get_hw_tx_cons(sc);
8024
8025                 if ((hw_rx_cons == sc->hw_rx_cons) &&
8026                     (hw_tx_cons == sc->hw_tx_cons))
8027                         break;
8028         }
8029
8030         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREREAD);
8031
8032         /* Re-enable interrupts. */
8033         bce_enable_intr(sc, 0);
8034
8035         /* Handle any frames that arrived while handling the interrupt. */
8036         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
8037             !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
8038                 bce_start_locked(ifp);
8039
8040 bce_intr_exit:
8041         BCE_UNLOCK(sc);
8042
8043         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
8044 }
8045
8046
8047 /****************************************************************************/
8048 /* Programs the various packet receive modes (broadcast and multicast).     */
8049 /*                                                                          */
8050 /* Returns:                                                                 */
8051 /*   Nothing.                                                               */
8052 /****************************************************************************/
8053 static u_int
8054 bce_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
8055 {
8056         u32 *hashes = arg;
8057         int h;
8058
8059         h = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0xFF;
8060         hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
8061
8062         return (1);
8063 }
8064
8065 static void
8066 bce_set_rx_mode(struct bce_softc *sc)
8067 {
8068         struct ifnet *ifp;
8069         u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
8070         u32 rx_mode, sort_mode;
8071         int i;
8072
8073         DBENTER(BCE_VERBOSE_MISC);
8074
8075         BCE_LOCK_ASSERT(sc);
8076
8077         ifp = sc->bce_ifp;
8078
8079         /* Initialize receive mode default settings. */
8080         rx_mode   = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
8081             BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
8082         sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
8083
8084         /*
8085          * ASF/IPMI/UMP firmware requires that VLAN tag stripping
8086          * be enbled.
8087          */
8088         if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
8089             (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)))
8090                 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
8091
8092         /*
8093          * Check for promiscuous, all multicast, or selected
8094          * multicast address filtering.
8095          */
8096         if (ifp->if_flags & IFF_PROMISC) {
8097                 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n");
8098
8099                 /* Enable promiscuous mode. */
8100                 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
8101                 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
8102         } else if (ifp->if_flags & IFF_ALLMULTI) {
8103                 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n");
8104
8105                 /* Enable all multicast addresses. */
8106                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
8107                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
8108                             0xffffffff);
8109                 }
8110                 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
8111         } else {
8112                 /* Accept one or more multicast(s). */
8113                 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n");
8114                 if_foreach_llmaddr(ifp, bce_hash_maddr, hashes);
8115
8116                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++)
8117                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]);
8118
8119                 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
8120         }
8121
8122         /* Only make changes if the recive mode has actually changed. */
8123         if (rx_mode != sc->rx_mode) {
8124                 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: "
8125                     "0x%08X\n", rx_mode);
8126
8127                 sc->rx_mode = rx_mode;
8128                 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
8129         }
8130
8131         /* Disable and clear the exisitng sort before enabling a new sort. */
8132         REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
8133         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
8134         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
8135
8136         DBEXIT(BCE_VERBOSE_MISC);
8137 }
8138
8139
8140 /****************************************************************************/
8141 /* Called periodically to updates statistics from the controllers           */
8142 /* statistics block.                                                        */
8143 /*                                                                          */
8144 /* Returns:                                                                 */
8145 /*   Nothing.                                                               */
8146 /****************************************************************************/
8147 static void
8148 bce_stats_update(struct bce_softc *sc)
8149 {
8150         struct statistics_block *stats;
8151
8152         DBENTER(BCE_EXTREME_MISC);
8153
8154         bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD);
8155
8156         stats = (struct statistics_block *) sc->stats_block;
8157
8158         /*
8159          * Update the sysctl statistics from the
8160          * hardware statistics.
8161          */
8162         sc->stat_IfHCInOctets =
8163             ((u64) stats->stat_IfHCInOctets_hi << 32) +
8164              (u64) stats->stat_IfHCInOctets_lo;
8165
8166         sc->stat_IfHCInBadOctets =
8167             ((u64) stats->stat_IfHCInBadOctets_hi << 32) +
8168              (u64) stats->stat_IfHCInBadOctets_lo;
8169
8170         sc->stat_IfHCOutOctets =
8171             ((u64) stats->stat_IfHCOutOctets_hi << 32) +
8172              (u64) stats->stat_IfHCOutOctets_lo;
8173
8174         sc->stat_IfHCOutBadOctets =
8175             ((u64) stats->stat_IfHCOutBadOctets_hi << 32) +
8176              (u64) stats->stat_IfHCOutBadOctets_lo;
8177
8178         sc->stat_IfHCInUcastPkts =
8179             ((u64) stats->stat_IfHCInUcastPkts_hi << 32) +
8180              (u64) stats->stat_IfHCInUcastPkts_lo;
8181
8182         sc->stat_IfHCInMulticastPkts =
8183             ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) +
8184              (u64) stats->stat_IfHCInMulticastPkts_lo;
8185
8186         sc->stat_IfHCInBroadcastPkts =
8187             ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) +
8188              (u64) stats->stat_IfHCInBroadcastPkts_lo;
8189
8190         sc->stat_IfHCOutUcastPkts =
8191             ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) +
8192              (u64) stats->stat_IfHCOutUcastPkts_lo;
8193
8194         sc->stat_IfHCOutMulticastPkts =
8195             ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) +
8196              (u64) stats->stat_IfHCOutMulticastPkts_lo;
8197
8198         sc->stat_IfHCOutBroadcastPkts =
8199             ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) +
8200              (u64) stats->stat_IfHCOutBroadcastPkts_lo;
8201
8202         /* ToDo: Preserve counters beyond 32 bits? */
8203         /* ToDo: Read the statistics from auto-clear regs? */
8204
8205         sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
8206             stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
8207
8208         sc->stat_Dot3StatsCarrierSenseErrors =
8209             stats->stat_Dot3StatsCarrierSenseErrors;
8210
8211         sc->stat_Dot3StatsFCSErrors =
8212             stats->stat_Dot3StatsFCSErrors;
8213
8214         sc->stat_Dot3StatsAlignmentErrors =
8215             stats->stat_Dot3StatsAlignmentErrors;
8216
8217         sc->stat_Dot3StatsSingleCollisionFrames =
8218             stats->stat_Dot3StatsSingleCollisionFrames;
8219
8220         sc->stat_Dot3StatsMultipleCollisionFrames =
8221             stats->stat_Dot3StatsMultipleCollisionFrames;
8222
8223         sc->stat_Dot3StatsDeferredTransmissions =
8224             stats->stat_Dot3StatsDeferredTransmissions;
8225
8226         sc->stat_Dot3StatsExcessiveCollisions =
8227             stats->stat_Dot3StatsExcessiveCollisions;
8228
8229         sc->stat_Dot3StatsLateCollisions =
8230             stats->stat_Dot3StatsLateCollisions;
8231
8232         sc->stat_EtherStatsCollisions =
8233             stats->stat_EtherStatsCollisions;
8234
8235         sc->stat_EtherStatsFragments =
8236             stats->stat_EtherStatsFragments;
8237
8238         sc->stat_EtherStatsJabbers =
8239             stats->stat_EtherStatsJabbers;
8240
8241         sc->stat_EtherStatsUndersizePkts =
8242             stats->stat_EtherStatsUndersizePkts;
8243
8244         sc->stat_EtherStatsOversizePkts =
8245              stats->stat_EtherStatsOversizePkts;
8246
8247         sc->stat_EtherStatsPktsRx64Octets =
8248             stats->stat_EtherStatsPktsRx64Octets;
8249
8250         sc->stat_EtherStatsPktsRx65Octetsto127Octets =
8251             stats->stat_EtherStatsPktsRx65Octetsto127Octets;
8252
8253         sc->stat_EtherStatsPktsRx128Octetsto255Octets =
8254             stats->stat_EtherStatsPktsRx128Octetsto255Octets;
8255
8256         sc->stat_EtherStatsPktsRx256Octetsto511Octets =
8257             stats->stat_EtherStatsPktsRx256Octetsto511Octets;
8258
8259         sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
8260             stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
8261
8262         sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
8263             stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
8264
8265         sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
8266             stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
8267
8268         sc->stat_EtherStatsPktsTx64Octets =
8269             stats->stat_EtherStatsPktsTx64Octets;
8270
8271         sc->stat_EtherStatsPktsTx65Octetsto127Octets =
8272             stats->stat_EtherStatsPktsTx65Octetsto127Octets;
8273
8274         sc->stat_EtherStatsPktsTx128Octetsto255Octets =
8275             stats->stat_EtherStatsPktsTx128Octetsto255Octets;
8276
8277         sc->stat_EtherStatsPktsTx256Octetsto511Octets =
8278             stats->stat_EtherStatsPktsTx256Octetsto511Octets;
8279
8280         sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
8281             stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
8282
8283         sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
8284             stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
8285
8286         sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
8287             stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
8288
8289         sc->stat_XonPauseFramesReceived =
8290             stats->stat_XonPauseFramesReceived;
8291
8292         sc->stat_XoffPauseFramesReceived =
8293             stats->stat_XoffPauseFramesReceived;
8294
8295         sc->stat_OutXonSent =
8296             stats->stat_OutXonSent;
8297
8298         sc->stat_OutXoffSent =
8299             stats->stat_OutXoffSent;
8300
8301         sc->stat_FlowControlDone =
8302             stats->stat_FlowControlDone;
8303
8304         sc->stat_MacControlFramesReceived =
8305             stats->stat_MacControlFramesReceived;
8306
8307         sc->stat_XoffStateEntered =
8308             stats->stat_XoffStateEntered;
8309
8310         sc->stat_IfInFramesL2FilterDiscards =
8311             stats->stat_IfInFramesL2FilterDiscards;
8312
8313         sc->stat_IfInRuleCheckerDiscards =
8314             stats->stat_IfInRuleCheckerDiscards;
8315
8316         sc->stat_IfInFTQDiscards =
8317             stats->stat_IfInFTQDiscards;
8318
8319         sc->stat_IfInMBUFDiscards =
8320             stats->stat_IfInMBUFDiscards;
8321
8322         sc->stat_IfInRuleCheckerP4Hit =
8323             stats->stat_IfInRuleCheckerP4Hit;
8324
8325         sc->stat_CatchupInRuleCheckerDiscards =
8326             stats->stat_CatchupInRuleCheckerDiscards;
8327
8328         sc->stat_CatchupInFTQDiscards =
8329             stats->stat_CatchupInFTQDiscards;
8330
8331         sc->stat_CatchupInMBUFDiscards =
8332             stats->stat_CatchupInMBUFDiscards;
8333
8334         sc->stat_CatchupInRuleCheckerP4Hit =
8335             stats->stat_CatchupInRuleCheckerP4Hit;
8336
8337         sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
8338
8339         /* ToDo: Add additional statistics? */
8340
8341         DBEXIT(BCE_EXTREME_MISC);
8342 }
8343
8344 static uint64_t
8345 bce_get_counter(struct ifnet *ifp, ift_counter cnt)
8346 {
8347         struct bce_softc *sc;
8348         uint64_t rv;
8349
8350         sc = if_getsoftc(ifp);
8351
8352         switch (cnt) {
8353         case IFCOUNTER_COLLISIONS:
8354                 return (sc->stat_EtherStatsCollisions);
8355         case IFCOUNTER_IERRORS:
8356                 return (sc->stat_EtherStatsUndersizePkts +
8357                     sc->stat_EtherStatsOversizePkts +
8358                     sc->stat_IfInMBUFDiscards +
8359                     sc->stat_Dot3StatsAlignmentErrors +
8360                     sc->stat_Dot3StatsFCSErrors +
8361                     sc->stat_IfInRuleCheckerDiscards +
8362                     sc->stat_IfInFTQDiscards +
8363                     sc->l2fhdr_error_count +
8364                     sc->com_no_buffers);
8365         case IFCOUNTER_OERRORS:
8366                 rv = sc->stat_Dot3StatsExcessiveCollisions +
8367                     sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
8368                     sc->stat_Dot3StatsLateCollisions +
8369                     sc->watchdog_timeouts;
8370                 /*
8371                  * Certain controllers don't report
8372                  * carrier sense errors correctly.
8373                  * See errata E11_5708CA0_1165.
8374                  */
8375                 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
8376                     !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0))
8377                         rv += sc->stat_Dot3StatsCarrierSenseErrors;
8378                 return (rv);
8379         default:
8380                 return (if_get_counter_default(ifp, cnt));
8381         }
8382 }
8383
8384
8385 /****************************************************************************/
8386 /* Periodic function to notify the bootcode that the driver is still        */
8387 /* present.                                                                 */
8388 /*                                                                          */
8389 /* Returns:                                                                 */
8390 /*   Nothing.                                                               */
8391 /****************************************************************************/
8392 static void
8393 bce_pulse(void *xsc)
8394 {
8395         struct bce_softc *sc = xsc;
8396         u32 msg;
8397
8398         DBENTER(BCE_EXTREME_MISC);
8399
8400         BCE_LOCK_ASSERT(sc);
8401
8402         /* Tell the firmware that the driver is still running. */
8403         msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq;
8404         bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
8405
8406         /* Update the bootcode condition. */
8407         sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
8408
8409         /* Report whether the bootcode still knows the driver is running. */
8410         if (bce_verbose || bootverbose) {
8411                 if (sc->bce_drv_cardiac_arrest == FALSE) {
8412                         if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
8413                                 sc->bce_drv_cardiac_arrest = TRUE;
8414                                 BCE_PRINTF("%s(): Warning: bootcode "
8415                                     "thinks driver is absent! "
8416                                     "(bc_state = 0x%08X)\n",
8417                                     __FUNCTION__, sc->bc_state);
8418                         }
8419                 } else {
8420                         /*
8421                          * Not supported by all bootcode versions.
8422                          * (v5.0.11+ and v5.2.1+)  Older bootcode
8423                          * will require the driver to reset the
8424                          * controller to clear this condition.
8425                          */
8426                         if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
8427                                 sc->bce_drv_cardiac_arrest = FALSE;
8428                                 BCE_PRINTF("%s(): Bootcode found the "
8429                                     "driver pulse! (bc_state = 0x%08X)\n",
8430                                     __FUNCTION__, sc->bc_state);
8431                         }
8432                 }
8433         }
8434
8435
8436         /* Schedule the next pulse. */
8437         callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
8438
8439         DBEXIT(BCE_EXTREME_MISC);
8440 }
8441
8442
8443 /****************************************************************************/
8444 /* Periodic function to perform maintenance tasks.                          */
8445 /*                                                                          */
8446 /* Returns:                                                                 */
8447 /*   Nothing.                                                               */
8448 /****************************************************************************/
8449 static void
8450 bce_tick(void *xsc)
8451 {
8452         struct bce_softc *sc = xsc;
8453         struct mii_data *mii;
8454         struct ifnet *ifp;
8455         struct ifmediareq ifmr;
8456
8457         ifp = sc->bce_ifp;
8458
8459         DBENTER(BCE_EXTREME_MISC);
8460
8461         BCE_LOCK_ASSERT(sc);
8462
8463         /* Schedule the next tick. */
8464         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
8465
8466         /* Update the statistics from the hardware statistics block. */
8467         bce_stats_update(sc);
8468
8469         /* Ensure page and RX chains get refilled in low-memory situations. */
8470         if (bce_hdr_split == TRUE)
8471                 bce_fill_pg_chain(sc);
8472         bce_fill_rx_chain(sc);
8473
8474         /* Check that chip hasn't hung. */
8475         bce_watchdog(sc);
8476
8477         /* If link is up already up then we're done. */
8478         if (sc->bce_link_up == TRUE)
8479                 goto bce_tick_exit;
8480
8481         /* Link is down.  Check what the PHY's doing. */
8482         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
8483                 bzero(&ifmr, sizeof(ifmr));
8484                 bce_ifmedia_sts_rphy(sc, &ifmr);
8485                 if ((ifmr.ifm_status & (IFM_ACTIVE | IFM_AVALID)) ==
8486                     (IFM_ACTIVE | IFM_AVALID)) {
8487                         sc->bce_link_up = TRUE;
8488                         bce_miibus_statchg(sc->bce_dev);
8489                 }
8490         } else {
8491                 mii = device_get_softc(sc->bce_miibus);
8492                 mii_tick(mii);
8493                 /* Check if the link has come up. */
8494                 if ((mii->mii_media_status & IFM_ACTIVE) &&
8495                     (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) {
8496                         DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n",
8497                             __FUNCTION__);
8498                         sc->bce_link_up = TRUE;
8499                         if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
8500                             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX ||
8501                             IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) &&
8502                             (bce_verbose || bootverbose))
8503                                 BCE_PRINTF("Gigabit link up!\n");
8504                 }
8505
8506         }
8507         if (sc->bce_link_up == TRUE) {
8508                 /* Now that link is up, handle any outstanding TX traffic. */
8509                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
8510                         DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found "
8511                             "pending TX traffic.\n", __FUNCTION__);
8512                         bce_start_locked(ifp);
8513                 }
8514         }
8515
8516 bce_tick_exit:
8517         DBEXIT(BCE_EXTREME_MISC);
8518 }
8519
8520 static void
8521 bce_fw_cap_init(struct bce_softc *sc)
8522 {
8523         u32 ack, cap, link;
8524
8525         ack = 0;
8526         cap = bce_shmem_rd(sc, BCE_FW_CAP_MB);
8527         if ((cap & BCE_FW_CAP_SIGNATURE_MAGIC_MASK) !=
8528             BCE_FW_CAP_SIGNATURE_MAGIC)
8529                 return;
8530         if ((cap & (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) ==
8531             (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN))
8532                 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC |
8533                     BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN;
8534         if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 &&
8535             (cap & BCE_FW_CAP_REMOTE_PHY_CAP) != 0) {
8536                 sc->bce_phy_flags &= ~BCE_PHY_REMOTE_PORT_FIBER_FLAG;
8537                 sc->bce_phy_flags |= BCE_PHY_REMOTE_CAP_FLAG;
8538                 link = bce_shmem_rd(sc, BCE_LINK_STATUS);
8539                 if ((link & BCE_LINK_STATUS_SERDES_LINK) != 0)
8540                         sc->bce_phy_flags |= BCE_PHY_REMOTE_PORT_FIBER_FLAG;
8541                 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC |
8542                     BCE_FW_CAP_REMOTE_PHY_CAP;
8543         }
8544
8545         if (ack != 0)
8546                 bce_shmem_wr(sc, BCE_DRV_ACK_CAP_MB, ack);
8547 }
8548
8549
8550 #ifdef BCE_DEBUG
8551 /****************************************************************************/
8552 /* Allows the driver state to be dumped through the sysctl interface.       */
8553 /*                                                                          */
8554 /* Returns:                                                                 */
8555 /*   0 for success, positive value for failure.                             */
8556 /****************************************************************************/
8557 static int
8558 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
8559 {
8560         int error;
8561         int result;
8562         struct bce_softc *sc;
8563
8564         result = -1;
8565         error = sysctl_handle_int(oidp, &result, 0, req);
8566
8567         if (error || !req->newptr)
8568                 return (error);
8569
8570         if (result == 1) {
8571                 sc = (struct bce_softc *)arg1;
8572                 bce_dump_driver_state(sc);
8573         }
8574
8575         return error;
8576 }
8577
8578
8579 /****************************************************************************/
8580 /* Allows the hardware state to be dumped through the sysctl interface.     */
8581 /*                                                                          */
8582 /* Returns:                                                                 */
8583 /*   0 for success, positive value for failure.                             */
8584 /****************************************************************************/
8585 static int
8586 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
8587 {
8588         int error;
8589         int result;
8590         struct bce_softc *sc;
8591
8592         result = -1;
8593         error = sysctl_handle_int(oidp, &result, 0, req);
8594
8595         if (error || !req->newptr)
8596                 return (error);
8597
8598         if (result == 1) {
8599                 sc = (struct bce_softc *)arg1;
8600                 bce_dump_hw_state(sc);
8601         }
8602
8603         return error;
8604 }
8605
8606
8607 /****************************************************************************/
8608 /* Allows the status block to be dumped through the sysctl interface.       */
8609 /*                                                                          */
8610 /* Returns:                                                                 */
8611 /*   0 for success, positive value for failure.                             */
8612 /****************************************************************************/
8613 static int
8614 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS)
8615 {
8616         int error;
8617         int result;
8618         struct bce_softc *sc;
8619
8620         result = -1;
8621         error = sysctl_handle_int(oidp, &result, 0, req);
8622
8623         if (error || !req->newptr)
8624                 return (error);
8625
8626         if (result == 1) {
8627                 sc = (struct bce_softc *)arg1;
8628                 bce_dump_status_block(sc);
8629         }
8630
8631         return error;
8632 }
8633
8634
8635 /****************************************************************************/
8636 /* Allows the stats block to be dumped through the sysctl interface.        */
8637 /*                                                                          */
8638 /* Returns:                                                                 */
8639 /*   0 for success, positive value for failure.                             */
8640 /****************************************************************************/
8641 static int
8642 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS)
8643 {
8644         int error;
8645         int result;
8646         struct bce_softc *sc;
8647
8648         result = -1;
8649         error = sysctl_handle_int(oidp, &result, 0, req);
8650
8651         if (error || !req->newptr)
8652                 return (error);
8653
8654         if (result == 1) {
8655                 sc = (struct bce_softc *)arg1;
8656                 bce_dump_stats_block(sc);
8657         }
8658
8659         return error;
8660 }
8661
8662
8663 /****************************************************************************/
8664 /* Allows the stat counters to be cleared without unloading/reloading the   */
8665 /* driver.                                                                  */
8666 /*                                                                          */
8667 /* Returns:                                                                 */
8668 /*   0 for success, positive value for failure.                             */
8669 /****************************************************************************/
8670 static int
8671 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS)
8672 {
8673         int error;
8674         int result;
8675         struct bce_softc *sc;
8676
8677         result = -1;
8678         error = sysctl_handle_int(oidp, &result, 0, req);
8679
8680         if (error || !req->newptr)
8681                 return (error);
8682
8683         if (result == 1) {
8684                 sc = (struct bce_softc *)arg1;
8685                 struct statistics_block *stats;
8686
8687                 stats = (struct statistics_block *) sc->stats_block;
8688                 bzero(stats, sizeof(struct statistics_block));
8689                 bus_dmamap_sync(sc->stats_tag, sc->stats_map,
8690                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
8691
8692                 /* Clear the internal H/W statistics counters. */
8693                 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
8694
8695                 /* Reset the driver maintained statistics. */
8696                 sc->interrupts_rx =
8697                     sc->interrupts_tx = 0;
8698                 sc->tso_frames_requested =
8699                     sc->tso_frames_completed =
8700                     sc->tso_frames_failed = 0;
8701                 sc->rx_empty_count =
8702                     sc->tx_full_count = 0;
8703                 sc->rx_low_watermark = USABLE_RX_BD_ALLOC;
8704                 sc->tx_hi_watermark = 0;
8705                 sc->l2fhdr_error_count =
8706                     sc->l2fhdr_error_sim_count = 0;
8707                 sc->mbuf_alloc_failed_count =
8708                     sc->mbuf_alloc_failed_sim_count = 0;
8709                 sc->dma_map_addr_rx_failed_count =
8710                     sc->dma_map_addr_tx_failed_count = 0;
8711                 sc->mbuf_frag_count = 0;
8712                 sc->csum_offload_tcp_udp =
8713                     sc->csum_offload_ip = 0;
8714                 sc->vlan_tagged_frames_rcvd =
8715                     sc->vlan_tagged_frames_stripped = 0;
8716                 sc->split_header_frames_rcvd =
8717                     sc->split_header_tcp_frames_rcvd = 0;
8718
8719                 /* Clear firmware maintained statistics. */
8720                 REG_WR_IND(sc, 0x120084, 0);
8721         }
8722
8723         return error;
8724 }
8725
8726
8727 /****************************************************************************/
8728 /* Allows the shared memory contents to be dumped through the sysctl  .     */
8729 /* interface.                                                               */
8730 /*                                                                          */
8731 /* Returns:                                                                 */
8732 /*   0 for success, positive value for failure.                             */
8733 /****************************************************************************/
8734 static int
8735 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS)
8736 {
8737         int error;
8738         int result;
8739         struct bce_softc *sc;
8740
8741         result = -1;
8742         error = sysctl_handle_int(oidp, &result, 0, req);
8743
8744         if (error || !req->newptr)
8745                 return (error);
8746
8747         if (result == 1) {
8748                 sc = (struct bce_softc *)arg1;
8749                 bce_dump_shmem_state(sc);
8750         }
8751
8752         return error;
8753 }
8754
8755
8756 /****************************************************************************/
8757 /* Allows the bootcode state to be dumped through the sysctl interface.     */
8758 /*                                                                          */
8759 /* Returns:                                                                 */
8760 /*   0 for success, positive value for failure.                             */
8761 /****************************************************************************/
8762 static int
8763 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS)
8764 {
8765         int error;
8766         int result;
8767         struct bce_softc *sc;
8768
8769         result = -1;
8770         error = sysctl_handle_int(oidp, &result, 0, req);
8771
8772         if (error || !req->newptr)
8773                 return (error);
8774
8775         if (result == 1) {
8776                 sc = (struct bce_softc *)arg1;
8777                 bce_dump_bc_state(sc);
8778         }
8779
8780         return error;
8781 }
8782
8783
8784 /****************************************************************************/
8785 /* Provides a sysctl interface to allow dumping the RX BD chain.            */
8786 /*                                                                          */
8787 /* Returns:                                                                 */
8788 /*   0 for success, positive value for failure.                             */
8789 /****************************************************************************/
8790 static int
8791 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS)
8792 {
8793         int error;
8794         int result;
8795         struct bce_softc *sc;
8796
8797         result = -1;
8798         error = sysctl_handle_int(oidp, &result, 0, req);
8799
8800         if (error || !req->newptr)
8801                 return (error);
8802
8803         if (result == 1) {
8804                 sc = (struct bce_softc *)arg1;
8805                 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC);
8806         }
8807
8808         return error;
8809 }
8810
8811
8812 /****************************************************************************/
8813 /* Provides a sysctl interface to allow dumping the RX MBUF chain.          */
8814 /*                                                                          */
8815 /* Returns:                                                                 */
8816 /*   0 for success, positive value for failure.                             */
8817 /****************************************************************************/
8818 static int
8819 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS)
8820 {
8821         int error;
8822         int result;
8823         struct bce_softc *sc;
8824
8825         result = -1;
8826         error = sysctl_handle_int(oidp, &result, 0, req);
8827
8828         if (error || !req->newptr)
8829                 return (error);
8830
8831         if (result == 1) {
8832                 sc = (struct bce_softc *)arg1;
8833                 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC);
8834         }
8835
8836         return error;
8837 }
8838
8839
8840 /****************************************************************************/
8841 /* Provides a sysctl interface to allow dumping the TX chain.               */
8842 /*                                                                          */
8843 /* Returns:                                                                 */
8844 /*   0 for success, positive value for failure.                             */
8845 /****************************************************************************/
8846 static int
8847 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
8848 {
8849         int error;
8850         int result;
8851         struct bce_softc *sc;
8852
8853         result = -1;
8854         error = sysctl_handle_int(oidp, &result, 0, req);
8855
8856         if (error || !req->newptr)
8857                 return (error);
8858
8859         if (result == 1) {
8860                 sc = (struct bce_softc *)arg1;
8861                 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC);
8862         }
8863
8864         return error;
8865 }
8866
8867
8868 /****************************************************************************/
8869 /* Provides a sysctl interface to allow dumping the page chain.             */
8870 /*                                                                          */
8871 /* Returns:                                                                 */
8872 /*   0 for success, positive value for failure.                             */
8873 /****************************************************************************/
8874 static int
8875 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS)
8876 {
8877         int error;
8878         int result;
8879         struct bce_softc *sc;
8880
8881         result = -1;
8882         error = sysctl_handle_int(oidp, &result, 0, req);
8883
8884         if (error || !req->newptr)
8885                 return (error);
8886
8887         if (result == 1) {
8888                 sc = (struct bce_softc *)arg1;
8889                 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC);
8890         }
8891
8892         return error;
8893 }
8894
8895 /****************************************************************************/
8896 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in  */
8897 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
8898 /*                                                                          */
8899 /* Returns:                                                                 */
8900 /*   0 for success, positive value for failure.                             */
8901 /****************************************************************************/
8902 static int
8903 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS)
8904 {
8905         struct bce_softc *sc = (struct bce_softc *)arg1;
8906         int error;
8907         u32 result;
8908         u32 val[1];
8909         u8 *data = (u8 *) val;
8910
8911         result = -1;
8912         error = sysctl_handle_int(oidp, &result, 0, req);
8913         if (error || (req->newptr == NULL))
8914                 return (error);
8915
8916         error = bce_nvram_read(sc, result, data, 4);
8917
8918         BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0]));
8919
8920         return (error);
8921 }
8922
8923
8924 /****************************************************************************/
8925 /* Provides a sysctl interface to allow reading arbitrary registers in the  */
8926 /* device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                            */
8927 /*                                                                          */
8928 /* Returns:                                                                 */
8929 /*   0 for success, positive value for failure.                             */
8930 /****************************************************************************/
8931 static int
8932 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
8933 {
8934         struct bce_softc *sc = (struct bce_softc *)arg1;
8935         int error;
8936         u32 val, result;
8937
8938         result = -1;
8939         error = sysctl_handle_int(oidp, &result, 0, req);
8940         if (error || (req->newptr == NULL))
8941                 return (error);
8942
8943         /* Make sure the register is accessible. */
8944         if (result < 0x8000) {
8945                 val = REG_RD(sc, result);
8946                 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8947         } else if (result < 0x0280000) {
8948                 val = REG_RD_IND(sc, result);
8949                 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8950         }
8951
8952         return (error);
8953 }
8954
8955
8956 /****************************************************************************/
8957 /* Provides a sysctl interface to allow reading arbitrary PHY registers in  */
8958 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
8959 /*                                                                          */
8960 /* Returns:                                                                 */
8961 /*   0 for success, positive value for failure.                             */
8962 /****************************************************************************/
8963 static int
8964 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
8965 {
8966         struct bce_softc *sc;
8967         device_t dev;
8968         int error, result;
8969         u16 val;
8970
8971         result = -1;
8972         error = sysctl_handle_int(oidp, &result, 0, req);
8973         if (error || (req->newptr == NULL))
8974                 return (error);
8975
8976         /* Make sure the register is accessible. */
8977         if (result < 0x20) {
8978                 sc = (struct bce_softc *)arg1;
8979                 dev = sc->bce_dev;
8980                 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
8981                 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val);
8982         }
8983         return (error);
8984 }
8985
8986
8987 /****************************************************************************/
8988 /* Provides a sysctl interface for dumping the nvram contents.              */
8989 /* DO NOT ENABLE ON PRODUCTION SYSTEMS!                                     */
8990 /*                                                                          */
8991 /* Returns:                                                                 */
8992 /*   0 for success, positive errno for failure.                             */
8993 /****************************************************************************/
8994 static int
8995 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS)
8996 {
8997         struct bce_softc *sc = (struct bce_softc *)arg1;
8998         int error, i;
8999
9000         if (sc->nvram_buf == NULL)
9001                 sc->nvram_buf = malloc(sc->bce_flash_size,
9002                                     M_TEMP, M_ZERO | M_WAITOK);
9003
9004         error = 0;
9005         if (req->oldlen == sc->bce_flash_size) {
9006                 for (i = 0; i < sc->bce_flash_size && error == 0; i++)
9007                         error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1);
9008         }
9009
9010         if (error == 0)
9011                 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size);
9012
9013         return error;
9014 }
9015
9016 #ifdef BCE_NVRAM_WRITE_SUPPORT
9017 /****************************************************************************/
9018 /* Provides a sysctl interface for writing to nvram.                        */
9019 /* DO NOT ENABLE ON PRODUCTION SYSTEMS!                                     */
9020 /*                                                                          */
9021 /* Returns:                                                                 */
9022 /*   0 for success, positive errno for failure.                             */
9023 /****************************************************************************/
9024 static int
9025 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS)
9026 {
9027         struct bce_softc *sc = (struct bce_softc *)arg1;
9028         int error;
9029
9030         if (sc->nvram_buf == NULL)
9031                 sc->nvram_buf = malloc(sc->bce_flash_size,
9032                                     M_TEMP, M_ZERO | M_WAITOK);
9033         else
9034                 bzero(sc->nvram_buf, sc->bce_flash_size);
9035
9036         error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size);
9037         if (error == 0)
9038                 return (error);
9039
9040         if (req->newlen == sc->bce_flash_size)
9041                 error = bce_nvram_write(sc, 0, sc->nvram_buf,
9042                             sc->bce_flash_size);
9043
9044
9045         return error;
9046 }
9047 #endif
9048
9049
9050 /****************************************************************************/
9051 /* Provides a sysctl interface to allow reading a CID.                      */
9052 /*                                                                          */
9053 /* Returns:                                                                 */
9054 /*   0 for success, positive value for failure.                             */
9055 /****************************************************************************/
9056 static int
9057 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS)
9058 {
9059         struct bce_softc *sc;
9060         int error, result;
9061
9062         result = -1;
9063         error = sysctl_handle_int(oidp, &result, 0, req);
9064         if (error || (req->newptr == NULL))
9065                 return (error);
9066
9067         /* Make sure the register is accessible. */
9068         if (result <= TX_CID) {
9069                 sc = (struct bce_softc *)arg1;
9070                 bce_dump_ctx(sc, result);
9071         }
9072
9073         return (error);
9074 }
9075
9076
9077 /****************************************************************************/
9078 /* Provides a sysctl interface to forcing the driver to dump state and      */
9079 /* enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                */
9080 /*                                                                          */
9081 /* Returns:                                                                 */
9082 /*   0 for success, positive value for failure.                             */
9083 /****************************************************************************/
9084 static int
9085 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
9086 {
9087         int error;
9088         int result;
9089         struct bce_softc *sc;
9090
9091         result = -1;
9092         error = sysctl_handle_int(oidp, &result, 0, req);
9093
9094         if (error || !req->newptr)
9095                 return (error);
9096
9097         if (result == 1) {
9098                 sc = (struct bce_softc *)arg1;
9099                 bce_breakpoint(sc);
9100         }
9101
9102         return error;
9103 }
9104 #endif
9105
9106 /****************************************************************************/
9107 /* Adds any sysctl parameters for tuning or debugging purposes.             */
9108 /*                                                                          */
9109 /* Returns:                                                                 */
9110 /*   0 for success, positive value for failure.                             */
9111 /****************************************************************************/
9112 static void
9113 bce_add_sysctls(struct bce_softc *sc)
9114 {
9115         struct sysctl_ctx_list *ctx;
9116         struct sysctl_oid_list *children;
9117
9118         DBENTER(BCE_VERBOSE_MISC);
9119
9120         ctx = device_get_sysctl_ctx(sc->bce_dev);
9121         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev));
9122
9123 #ifdef BCE_DEBUG
9124         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9125             "l2fhdr_error_sim_control",
9126             CTLFLAG_RW, &l2fhdr_error_sim_control,
9127             0, "Debug control to force l2fhdr errors");
9128
9129         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9130             "l2fhdr_error_sim_count",
9131             CTLFLAG_RD, &sc->l2fhdr_error_sim_count,
9132             0, "Number of simulated l2_fhdr errors");
9133 #endif
9134
9135         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9136             "l2fhdr_error_count",
9137             CTLFLAG_RD, &sc->l2fhdr_error_count,
9138             0, "Number of l2_fhdr errors");
9139
9140 #ifdef BCE_DEBUG
9141         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9142             "mbuf_alloc_failed_sim_control",
9143             CTLFLAG_RW, &mbuf_alloc_failed_sim_control,
9144             0, "Debug control to force mbuf allocation failures");
9145
9146         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9147             "mbuf_alloc_failed_sim_count",
9148             CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count,
9149             0, "Number of simulated mbuf cluster allocation failures");
9150 #endif
9151
9152         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9153             "mbuf_alloc_failed_count",
9154             CTLFLAG_RD, &sc->mbuf_alloc_failed_count,
9155             0, "Number of mbuf allocation failures");
9156
9157         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9158             "mbuf_frag_count",
9159             CTLFLAG_RD, &sc->mbuf_frag_count,
9160             0, "Number of fragmented mbufs");
9161
9162 #ifdef BCE_DEBUG
9163         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9164             "dma_map_addr_failed_sim_control",
9165             CTLFLAG_RW, &dma_map_addr_failed_sim_control,
9166             0, "Debug control to force DMA mapping failures");
9167
9168         /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */
9169         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9170             "dma_map_addr_failed_sim_count",
9171             CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count,
9172             0, "Number of simulated DMA mapping failures");
9173
9174 #endif
9175
9176         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9177             "dma_map_addr_rx_failed_count",
9178             CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count,
9179             0, "Number of RX DMA mapping failures");
9180
9181         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9182             "dma_map_addr_tx_failed_count",
9183             CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count,
9184             0, "Number of TX DMA mapping failures");
9185
9186 #ifdef BCE_DEBUG
9187         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9188             "unexpected_attention_sim_control",
9189             CTLFLAG_RW, &unexpected_attention_sim_control,
9190             0, "Debug control to simulate unexpected attentions");
9191
9192         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9193             "unexpected_attention_sim_count",
9194             CTLFLAG_RW, &sc->unexpected_attention_sim_count,
9195             0, "Number of simulated unexpected attentions");
9196 #endif
9197
9198         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9199             "unexpected_attention_count",
9200             CTLFLAG_RW, &sc->unexpected_attention_count,
9201             0, "Number of unexpected attentions");
9202
9203 #ifdef BCE_DEBUG
9204         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9205             "debug_bootcode_running_failure",
9206             CTLFLAG_RW, &bootcode_running_failure_sim_control,
9207             0, "Debug control to force bootcode running failures");
9208
9209         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9210             "rx_low_watermark",
9211             CTLFLAG_RD, &sc->rx_low_watermark,
9212             0, "Lowest level of free rx_bd's");
9213
9214         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9215             "rx_empty_count",
9216             CTLFLAG_RD, &sc->rx_empty_count,
9217             "Number of times the RX chain was empty");
9218
9219         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9220             "tx_hi_watermark",
9221             CTLFLAG_RD, &sc->tx_hi_watermark,
9222             0, "Highest level of used tx_bd's");
9223
9224         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9225             "tx_full_count",
9226             CTLFLAG_RD, &sc->tx_full_count,
9227             "Number of times the TX chain was full");
9228
9229         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9230             "tso_frames_requested",
9231             CTLFLAG_RD, &sc->tso_frames_requested,
9232             "Number of TSO frames requested");
9233
9234         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9235             "tso_frames_completed",
9236             CTLFLAG_RD, &sc->tso_frames_completed,
9237             "Number of TSO frames completed");
9238
9239         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9240             "tso_frames_failed",
9241             CTLFLAG_RD, &sc->tso_frames_failed,
9242             "Number of TSO frames failed");
9243
9244         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9245             "csum_offload_ip",
9246             CTLFLAG_RD, &sc->csum_offload_ip,
9247             "Number of IP checksum offload frames");
9248
9249         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9250             "csum_offload_tcp_udp",
9251             CTLFLAG_RD, &sc->csum_offload_tcp_udp,
9252             "Number of TCP/UDP checksum offload frames");
9253
9254         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9255             "vlan_tagged_frames_rcvd",
9256             CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd,
9257             "Number of VLAN tagged frames received");
9258
9259         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9260             "vlan_tagged_frames_stripped",
9261             CTLFLAG_RD, &sc->vlan_tagged_frames_stripped,
9262             "Number of VLAN tagged frames stripped");
9263
9264         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9265             "interrupts_rx",
9266             CTLFLAG_RD, &sc->interrupts_rx,
9267             "Number of RX interrupts");
9268
9269         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9270             "interrupts_tx",
9271             CTLFLAG_RD, &sc->interrupts_tx,
9272             "Number of TX interrupts");
9273
9274         if (bce_hdr_split == TRUE) {
9275                 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9276                     "split_header_frames_rcvd",
9277                     CTLFLAG_RD, &sc->split_header_frames_rcvd,
9278                     "Number of split header frames received");
9279
9280                 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9281                     "split_header_tcp_frames_rcvd",
9282                     CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd,
9283                     "Number of split header TCP frames received");
9284         }
9285
9286         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9287             "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
9288             (void *)sc, 0,
9289             bce_sysctl_nvram_dump, "S", "");
9290
9291 #ifdef BCE_NVRAM_WRITE_SUPPORT
9292         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9293             "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR | CTLFLAG_NEEDGIANT,
9294             (void *)sc, 0,
9295             bce_sysctl_nvram_write, "S", "");
9296 #endif
9297 #endif /* BCE_DEBUG */
9298
9299         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9300             "stat_IfHcInOctets",
9301             CTLFLAG_RD, &sc->stat_IfHCInOctets,
9302             "Bytes received");
9303
9304         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9305             "stat_IfHCInBadOctets",
9306             CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
9307             "Bad bytes received");
9308
9309         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9310             "stat_IfHCOutOctets",
9311             CTLFLAG_RD, &sc->stat_IfHCOutOctets,
9312             "Bytes sent");
9313
9314         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9315             "stat_IfHCOutBadOctets",
9316             CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
9317             "Bad bytes sent");
9318
9319         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9320             "stat_IfHCInUcastPkts",
9321             CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
9322             "Unicast packets received");
9323
9324         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9325             "stat_IfHCInMulticastPkts",
9326             CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
9327             "Multicast packets received");
9328
9329         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9330             "stat_IfHCInBroadcastPkts",
9331             CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
9332             "Broadcast packets received");
9333
9334         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9335             "stat_IfHCOutUcastPkts",
9336             CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
9337             "Unicast packets sent");
9338
9339         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9340             "stat_IfHCOutMulticastPkts",
9341             CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
9342             "Multicast packets sent");
9343
9344         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9345             "stat_IfHCOutBroadcastPkts",
9346             CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
9347             "Broadcast packets sent");
9348
9349         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9350             "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
9351             CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
9352             0, "Internal MAC transmit errors");
9353
9354         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9355             "stat_Dot3StatsCarrierSenseErrors",
9356             CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
9357             0, "Carrier sense errors");
9358
9359         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9360             "stat_Dot3StatsFCSErrors",
9361             CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
9362             0, "Frame check sequence errors");
9363
9364         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9365             "stat_Dot3StatsAlignmentErrors",
9366             CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
9367             0, "Alignment errors");
9368
9369         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9370             "stat_Dot3StatsSingleCollisionFrames",
9371             CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
9372             0, "Single Collision Frames");
9373
9374         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9375             "stat_Dot3StatsMultipleCollisionFrames",
9376             CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
9377             0, "Multiple Collision Frames");
9378
9379         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9380             "stat_Dot3StatsDeferredTransmissions",
9381             CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
9382             0, "Deferred Transmissions");
9383
9384         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9385             "stat_Dot3StatsExcessiveCollisions",
9386             CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
9387             0, "Excessive Collisions");
9388
9389         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9390             "stat_Dot3StatsLateCollisions",
9391             CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
9392             0, "Late Collisions");
9393
9394         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9395             "stat_EtherStatsCollisions",
9396             CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
9397             0, "Collisions");
9398
9399         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9400             "stat_EtherStatsFragments",
9401             CTLFLAG_RD, &sc->stat_EtherStatsFragments,
9402             0, "Fragments");
9403
9404         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9405             "stat_EtherStatsJabbers",
9406             CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
9407             0, "Jabbers");
9408
9409         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9410             "stat_EtherStatsUndersizePkts",
9411             CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
9412             0, "Undersize packets");
9413
9414         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9415             "stat_EtherStatsOversizePkts",
9416             CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts,
9417             0, "stat_EtherStatsOversizePkts");
9418
9419         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9420             "stat_EtherStatsPktsRx64Octets",
9421             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
9422             0, "Bytes received in 64 byte packets");
9423
9424         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9425             "stat_EtherStatsPktsRx65Octetsto127Octets",
9426             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
9427             0, "Bytes received in 65 to 127 byte packets");
9428
9429         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9430             "stat_EtherStatsPktsRx128Octetsto255Octets",
9431             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
9432             0, "Bytes received in 128 to 255 byte packets");
9433
9434         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9435             "stat_EtherStatsPktsRx256Octetsto511Octets",
9436             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
9437             0, "Bytes received in 256 to 511 byte packets");
9438
9439         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9440             "stat_EtherStatsPktsRx512Octetsto1023Octets",
9441             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
9442             0, "Bytes received in 512 to 1023 byte packets");
9443
9444         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9445             "stat_EtherStatsPktsRx1024Octetsto1522Octets",
9446             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
9447             0, "Bytes received in 1024 t0 1522 byte packets");
9448
9449         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9450             "stat_EtherStatsPktsRx1523Octetsto9022Octets",
9451             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
9452             0, "Bytes received in 1523 to 9022 byte packets");
9453
9454         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9455             "stat_EtherStatsPktsTx64Octets",
9456             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
9457             0, "Bytes sent in 64 byte packets");
9458
9459         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9460             "stat_EtherStatsPktsTx65Octetsto127Octets",
9461             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
9462             0, "Bytes sent in 65 to 127 byte packets");
9463
9464         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9465             "stat_EtherStatsPktsTx128Octetsto255Octets",
9466             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
9467             0, "Bytes sent in 128 to 255 byte packets");
9468
9469         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9470             "stat_EtherStatsPktsTx256Octetsto511Octets",
9471             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
9472             0, "Bytes sent in 256 to 511 byte packets");
9473
9474         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9475             "stat_EtherStatsPktsTx512Octetsto1023Octets",
9476             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
9477             0, "Bytes sent in 512 to 1023 byte packets");
9478
9479         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9480             "stat_EtherStatsPktsTx1024Octetsto1522Octets",
9481             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
9482             0, "Bytes sent in 1024 to 1522 byte packets");
9483
9484         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9485             "stat_EtherStatsPktsTx1523Octetsto9022Octets",
9486             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
9487             0, "Bytes sent in 1523 to 9022 byte packets");
9488
9489         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9490             "stat_XonPauseFramesReceived",
9491             CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
9492             0, "XON pause frames receved");
9493
9494         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9495             "stat_XoffPauseFramesReceived",
9496             CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
9497             0, "XOFF pause frames received");
9498
9499         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9500             "stat_OutXonSent",
9501             CTLFLAG_RD, &sc->stat_OutXonSent,
9502             0, "XON pause frames sent");
9503
9504         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9505             "stat_OutXoffSent",
9506             CTLFLAG_RD, &sc->stat_OutXoffSent,
9507             0, "XOFF pause frames sent");
9508
9509         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9510             "stat_FlowControlDone",
9511             CTLFLAG_RD, &sc->stat_FlowControlDone,
9512             0, "Flow control done");
9513
9514         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9515             "stat_MacControlFramesReceived",
9516             CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
9517             0, "MAC control frames received");
9518
9519         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9520             "stat_XoffStateEntered",
9521             CTLFLAG_RD, &sc->stat_XoffStateEntered,
9522             0, "XOFF state entered");
9523
9524         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9525             "stat_IfInFramesL2FilterDiscards",
9526             CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
9527             0, "Received L2 packets discarded");
9528
9529         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9530             "stat_IfInRuleCheckerDiscards",
9531             CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
9532             0, "Received packets discarded by rule");
9533
9534         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9535             "stat_IfInFTQDiscards",
9536             CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
9537             0, "Received packet FTQ discards");
9538
9539         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9540             "stat_IfInMBUFDiscards",
9541             CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
9542             0, "Received packets discarded due to lack "
9543             "of controller buffer memory");
9544
9545         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9546             "stat_IfInRuleCheckerP4Hit",
9547             CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
9548             0, "Received packets rule checker hits");
9549
9550         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9551             "stat_CatchupInRuleCheckerDiscards",
9552             CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
9553             0, "Received packets discarded in Catchup path");
9554
9555         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9556             "stat_CatchupInFTQDiscards",
9557             CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
9558             0, "Received packets discarded in FTQ in Catchup path");
9559
9560         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9561             "stat_CatchupInMBUFDiscards",
9562             CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
9563             0, "Received packets discarded in controller "
9564             "buffer memory in Catchup path");
9565
9566         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9567             "stat_CatchupInRuleCheckerP4Hit",
9568             CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
9569             0, "Received packets rule checker hits in Catchup path");
9570
9571         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9572             "com_no_buffers",
9573             CTLFLAG_RD, &sc->com_no_buffers,
9574             0, "Valid packets received but no RX buffers available");
9575
9576 #ifdef BCE_DEBUG
9577         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9578             "driver_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9579             (void *)sc, 0,
9580             bce_sysctl_driver_state, "I", "Drive state information");
9581
9582         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9583             "hw_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9584             (void *)sc, 0,
9585             bce_sysctl_hw_state, "I", "Hardware state information");
9586
9587         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9588             "status_block", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9589             (void *)sc, 0,
9590             bce_sysctl_status_block, "I", "Dump status block");
9591
9592         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9593             "stats_block", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9594             (void *)sc, 0,
9595             bce_sysctl_stats_block, "I", "Dump statistics block");
9596
9597         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9598             "stats_clear", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9599             (void *)sc, 0,
9600             bce_sysctl_stats_clear, "I", "Clear statistics block");
9601
9602         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9603             "shmem_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9604             (void *)sc, 0,
9605             bce_sysctl_shmem_state, "I", "Shared memory state information");
9606
9607         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9608             "bc_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9609             (void *)sc, 0,
9610             bce_sysctl_bc_state, "I", "Bootcode state information");
9611
9612         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9613             "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9614             (void *)sc, 0,
9615             bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain");
9616
9617         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9618             "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9619             (void *)sc, 0,
9620             bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain");
9621
9622         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9623             "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9624             (void *)sc, 0,
9625             bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
9626
9627         if (bce_hdr_split == TRUE) {
9628                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9629                     "dump_pg_chain",
9630                     CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9631                     (void *)sc, 0,
9632                     bce_sysctl_dump_pg_chain, "I", "Dump page chain");
9633         }
9634
9635         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9636             "dump_ctx", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9637             (void *)sc, 0,
9638             bce_sysctl_dump_ctx, "I", "Dump context memory");
9639
9640         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9641             "breakpoint", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9642             (void *)sc, 0,
9643             bce_sysctl_breakpoint, "I", "Driver breakpoint");
9644
9645         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9646             "reg_read", CTLTYPE_INT | CTLFLAG_RW| CTLFLAG_NEEDGIANT,
9647             (void *)sc, 0,
9648             bce_sysctl_reg_read, "I", "Register read");
9649
9650         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9651             "nvram_read", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9652             (void *)sc, 0,
9653             bce_sysctl_nvram_read, "I", "NVRAM read");
9654
9655         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9656             "phy_read", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
9657             (void *)sc, 0,
9658             bce_sysctl_phy_read, "I", "PHY register read");
9659
9660 #endif
9661
9662         DBEXIT(BCE_VERBOSE_MISC);
9663 }
9664
9665
9666 /****************************************************************************/
9667 /* BCE Debug Routines                                                       */
9668 /****************************************************************************/
9669 #ifdef BCE_DEBUG
9670
9671 /****************************************************************************/
9672 /* Freezes the controller to allow for a cohesive state dump.               */
9673 /*                                                                          */
9674 /* Returns:                                                                 */
9675 /*   Nothing.                                                               */
9676 /****************************************************************************/
9677 static __attribute__ ((noinline)) void
9678 bce_freeze_controller(struct bce_softc *sc)
9679 {
9680         u32 val;
9681         val = REG_RD(sc, BCE_MISC_COMMAND);
9682         val |= BCE_MISC_COMMAND_DISABLE_ALL;
9683         REG_WR(sc, BCE_MISC_COMMAND, val);
9684 }
9685
9686
9687 /****************************************************************************/
9688 /* Unfreezes the controller after a freeze operation.  This may not always  */
9689 /* work and the controller will require a reset!                            */
9690 /*                                                                          */
9691 /* Returns:                                                                 */
9692 /*   Nothing.                                                               */
9693 /****************************************************************************/
9694 static __attribute__ ((noinline)) void
9695 bce_unfreeze_controller(struct bce_softc *sc)
9696 {
9697         u32 val;
9698         val = REG_RD(sc, BCE_MISC_COMMAND);
9699         val |= BCE_MISC_COMMAND_ENABLE_ALL;
9700         REG_WR(sc, BCE_MISC_COMMAND, val);
9701 }
9702
9703
9704 /****************************************************************************/
9705 /* Prints out Ethernet frame information from an mbuf.                      */
9706 /*                                                                          */
9707 /* Partially decode an Ethernet frame to look at some important headers.    */
9708 /*                                                                          */
9709 /* Returns:                                                                 */
9710 /*   Nothing.                                                               */
9711 /****************************************************************************/
9712 static __attribute__ ((noinline)) void
9713 bce_dump_enet(struct bce_softc *sc, struct mbuf *m)
9714 {
9715         struct ether_vlan_header *eh;
9716         u16 etype;
9717         int ehlen;
9718         struct ip *ip;
9719         struct tcphdr *th;
9720         struct udphdr *uh;
9721         struct arphdr *ah;
9722
9723         BCE_PRINTF(
9724             "-----------------------------"
9725             " Frame Decode "
9726             "-----------------------------\n");
9727
9728         eh = mtod(m, struct ether_vlan_header *);
9729
9730         /* Handle VLAN encapsulation if present. */
9731         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
9732                 etype = ntohs(eh->evl_proto);
9733                 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
9734         } else {
9735                 etype = ntohs(eh->evl_encap_proto);
9736                 ehlen = ETHER_HDR_LEN;
9737         }
9738
9739         /* ToDo: Add VLAN output. */
9740         BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n",
9741             eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen);
9742
9743         switch (etype) {
9744         case ETHERTYPE_IP:
9745                 ip = (struct ip *)(m->m_data + ehlen);
9746                 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, "
9747                     "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n",
9748                     ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr),
9749                     ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum));
9750
9751                 switch (ip->ip_p) {
9752                 case IPPROTO_TCP:
9753                         th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9754                         BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = "
9755                             "%d bytes, flags = 0x%b, csum = 0x%04X\n",
9756                             ntohs(th->th_dport), ntohs(th->th_sport),
9757                             (th->th_off << 2), th->th_flags,
9758                             "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST"
9759                             "\02SYN\01FIN", ntohs(th->th_sum));
9760                         break;
9761                 case IPPROTO_UDP:
9762                         uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9763                         BCE_PRINTF("-udp: dest = %d, src = %d, len = %d "
9764                             "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport),
9765                             ntohs(uh->uh_sport), ntohs(uh->uh_ulen),
9766                             ntohs(uh->uh_sum));
9767                         break;
9768                 case IPPROTO_ICMP:
9769                         BCE_PRINTF("icmp:\n");
9770                         break;
9771                 default:
9772                         BCE_PRINTF("----: Other IP protocol.\n");
9773                         }
9774                 break;
9775         case ETHERTYPE_IPV6:
9776                 BCE_PRINTF("ipv6: No decode supported.\n");
9777                 break;
9778         case ETHERTYPE_ARP:
9779                 BCE_PRINTF("-arp: ");
9780                 ah = (struct arphdr *) (m->m_data + ehlen);
9781                 switch (ntohs(ah->ar_op)) {
9782                 case ARPOP_REVREQUEST:
9783                         printf("reverse ARP request\n");
9784                         break;
9785                 case ARPOP_REVREPLY:
9786                         printf("reverse ARP reply\n");
9787                         break;
9788                 case ARPOP_REQUEST:
9789                         printf("ARP request\n");
9790                         break;
9791                 case ARPOP_REPLY:
9792                         printf("ARP reply\n");
9793                         break;
9794                 default:
9795                         printf("other ARP operation\n");
9796                 }
9797                 break;
9798         default:
9799                 BCE_PRINTF("----: Other protocol.\n");
9800         }
9801
9802         BCE_PRINTF(
9803                 "-----------------------------"
9804                 "--------------"
9805                 "-----------------------------\n");
9806 }
9807
9808
9809 /****************************************************************************/
9810 /* Prints out information about an mbuf.                                    */
9811 /*                                                                          */
9812 /* Returns:                                                                 */
9813 /*   Nothing.                                                               */
9814 /****************************************************************************/
9815 static __attribute__ ((noinline)) void
9816 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
9817 {
9818         struct mbuf *mp = m;
9819
9820         if (m == NULL) {
9821                 BCE_PRINTF("mbuf: null pointer\n");
9822                 return;
9823         }
9824
9825         while (mp) {
9826                 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, "
9827                     "m_data = %p\n", mp, mp->m_len, mp->m_flags,
9828                     "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data);
9829
9830                 if (mp->m_flags & M_PKTHDR) {
9831                         BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, "
9832                             "csum_flags = %b\n", mp->m_pkthdr.len,
9833                             mp->m_flags, M_FLAG_PRINTF,
9834                             mp->m_pkthdr.csum_flags, CSUM_BITS);
9835                 }
9836
9837                 if (mp->m_flags & M_EXT) {
9838                         BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ",
9839                             mp->m_ext.ext_buf, mp->m_ext.ext_size);
9840                         switch (mp->m_ext.ext_type) {
9841                         case EXT_CLUSTER:
9842                                 printf("EXT_CLUSTER\n"); break;
9843                         case EXT_SFBUF:
9844                                 printf("EXT_SFBUF\n"); break;
9845                         case EXT_JUMBO9:
9846                                 printf("EXT_JUMBO9\n"); break;
9847                         case EXT_JUMBO16:
9848                                 printf("EXT_JUMBO16\n"); break;
9849                         case EXT_PACKET:
9850                                 printf("EXT_PACKET\n"); break;
9851                         case EXT_MBUF:
9852                                 printf("EXT_MBUF\n"); break;
9853                         case EXT_NET_DRV:
9854                                 printf("EXT_NET_DRV\n"); break;
9855                         case EXT_MOD_TYPE:
9856                                 printf("EXT_MDD_TYPE\n"); break;
9857                         case EXT_DISPOSABLE:
9858                                 printf("EXT_DISPOSABLE\n"); break;
9859                         case EXT_EXTREF:
9860                                 printf("EXT_EXTREF\n"); break;
9861                         default:
9862                                 printf("UNKNOWN\n");
9863                         }
9864                 }
9865
9866                 mp = mp->m_next;
9867         }
9868 }
9869
9870
9871 /****************************************************************************/
9872 /* Prints out the mbufs in the TX mbuf chain.                               */
9873 /*                                                                          */
9874 /* Returns:                                                                 */
9875 /*   Nothing.                                                               */
9876 /****************************************************************************/
9877 static __attribute__ ((noinline)) void
9878 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9879 {
9880         struct mbuf *m;
9881
9882         BCE_PRINTF(
9883                 "----------------------------"
9884                 "  tx mbuf data  "
9885                 "----------------------------\n");
9886
9887         for (int i = 0; i < count; i++) {
9888                 m = sc->tx_mbuf_ptr[chain_prod];
9889                 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod);
9890                 bce_dump_mbuf(sc, m);
9891                 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
9892         }
9893
9894         BCE_PRINTF(
9895                 "----------------------------"
9896                 "----------------"
9897                 "----------------------------\n");
9898 }
9899
9900
9901 /****************************************************************************/
9902 /* Prints out the mbufs in the RX mbuf chain.                               */
9903 /*                                                                          */
9904 /* Returns:                                                                 */
9905 /*   Nothing.                                                               */
9906 /****************************************************************************/
9907 static __attribute__ ((noinline)) void
9908 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9909 {
9910         struct mbuf *m;
9911
9912         BCE_PRINTF(
9913                 "----------------------------"
9914                 "  rx mbuf data  "
9915                 "----------------------------\n");
9916
9917         for (int i = 0; i < count; i++) {
9918                 m = sc->rx_mbuf_ptr[chain_prod];
9919                 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod);
9920                 bce_dump_mbuf(sc, m);
9921                 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
9922         }
9923
9924
9925         BCE_PRINTF(
9926                 "----------------------------"
9927                 "----------------"
9928                 "----------------------------\n");
9929 }
9930
9931
9932 /****************************************************************************/
9933 /* Prints out the mbufs in the mbuf page chain.                             */
9934 /*                                                                          */
9935 /* Returns:                                                                 */
9936 /*   Nothing.                                                               */
9937 /****************************************************************************/
9938 static __attribute__ ((noinline)) void
9939 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9940 {
9941         struct mbuf *m;
9942
9943         BCE_PRINTF(
9944                 "----------------------------"
9945                 "  pg mbuf data  "
9946                 "----------------------------\n");
9947
9948         for (int i = 0; i < count; i++) {
9949                 m = sc->pg_mbuf_ptr[chain_prod];
9950                 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod);
9951                 bce_dump_mbuf(sc, m);
9952                 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod));
9953         }
9954
9955
9956         BCE_PRINTF(
9957                 "----------------------------"
9958                 "----------------"
9959                 "----------------------------\n");
9960 }
9961
9962
9963 /****************************************************************************/
9964 /* Prints out a tx_bd structure.                                            */
9965 /*                                                                          */
9966 /* Returns:                                                                 */
9967 /*   Nothing.                                                               */
9968 /****************************************************************************/
9969 static __attribute__ ((noinline)) void
9970 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
9971 {
9972         int i = 0;
9973
9974         if (idx > MAX_TX_BD_ALLOC)
9975                 /* Index out of range. */
9976                 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
9977         else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
9978                 /* TX Chain page pointer. */
9979                 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
9980                     "pointer\n", idx, txbd->tx_bd_haddr_hi,
9981                     txbd->tx_bd_haddr_lo);
9982         else {
9983                 /* Normal tx_bd entry. */
9984                 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
9985                     "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = "
9986                     "0x%04X (", idx, txbd->tx_bd_haddr_hi,
9987                     txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes,
9988                     txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
9989
9990                 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) {
9991                         if (i>0)
9992                                 printf("|");
9993                         printf("CONN_FAULT");
9994                         i++;
9995                 }
9996
9997                 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) {
9998                         if (i>0)
9999                                 printf("|");
10000                         printf("TCP_UDP_CKSUM");
10001                         i++;
10002                 }
10003
10004                 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) {
10005                         if (i>0)
10006                                 printf("|");
10007                         printf("IP_CKSUM");
10008                         i++;
10009                 }
10010
10011                 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) {
10012                         if (i>0)
10013                                 printf("|");
10014                         printf("VLAN");
10015                         i++;
10016                 }
10017
10018                 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) {
10019                         if (i>0)
10020                                 printf("|");
10021                         printf("COAL_NOW");
10022                         i++;
10023                 }
10024
10025                 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) {
10026                         if (i>0)
10027                                 printf("|");
10028                         printf("DONT_GEN_CRC");
10029                         i++;
10030                 }
10031
10032                 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) {
10033                         if (i>0)
10034                                 printf("|");
10035                         printf("START");
10036                         i++;
10037                 }
10038
10039                 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) {
10040                         if (i>0)
10041                                 printf("|");
10042                         printf("END");
10043                         i++;
10044                 }
10045
10046                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) {
10047                         if (i>0)
10048                                 printf("|");
10049                         printf("LSO");
10050                         i++;
10051                 }
10052
10053                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) {
10054                         if (i>0)
10055                                 printf("|");
10056                         printf("SW_OPTION=%d", ((txbd->tx_bd_flags &
10057                             TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++;
10058                 }
10059
10060                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) {
10061                         if (i>0)
10062                                 printf("|");
10063                         printf("SW_FLAGS");
10064                         i++;
10065                 }
10066
10067                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) {
10068                         if (i>0)
10069                                 printf("|");
10070                         printf("SNAP)");
10071                 } else {
10072                         printf(")\n");
10073                 }
10074         }
10075 }
10076
10077
10078 /****************************************************************************/
10079 /* Prints out a rx_bd structure.                                            */
10080 /*                                                                          */
10081 /* Returns:                                                                 */
10082 /*   Nothing.                                                               */
10083 /****************************************************************************/
10084 static __attribute__ ((noinline)) void
10085 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
10086 {
10087         if (idx > MAX_RX_BD_ALLOC)
10088                 /* Index out of range. */
10089                 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
10090         else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
10091                 /* RX Chain page pointer. */
10092                 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
10093                     "pointer\n", idx, rxbd->rx_bd_haddr_hi,
10094                     rxbd->rx_bd_haddr_lo);
10095         else
10096                 /* Normal rx_bd entry. */
10097                 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = "
10098                     "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi,
10099                     rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len,
10100                     rxbd->rx_bd_flags);
10101 }
10102
10103
10104 /****************************************************************************/
10105 /* Prints out a rx_bd structure in the page chain.                          */
10106 /*                                                                          */
10107 /* Returns:                                                                 */
10108 /*   Nothing.                                                               */
10109 /****************************************************************************/
10110 static __attribute__ ((noinline)) void
10111 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd)
10112 {
10113         if (idx > MAX_PG_BD_ALLOC)
10114                 /* Index out of range. */
10115                 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx);
10116         else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE)
10117                 /* Page Chain page pointer. */
10118                 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n",
10119                         idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo);
10120         else
10121                 /* Normal rx_bd entry. */
10122                 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, "
10123                         "flags = 0x%08X\n", idx,
10124                         pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo,
10125                         pgbd->rx_bd_len, pgbd->rx_bd_flags);
10126 }
10127
10128
10129 /****************************************************************************/
10130 /* Prints out a l2_fhdr structure.                                          */
10131 /*                                                                          */
10132 /* Returns:                                                                 */
10133 /*   Nothing.                                                               */
10134 /****************************************************************************/
10135 static __attribute__ ((noinline)) void
10136 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
10137 {
10138         BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, "
10139                 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, "
10140                 "tcp_udp_xsum = 0x%04X\n", idx,
10141                 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB,
10142                 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
10143                 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
10144 }
10145
10146
10147 /****************************************************************************/
10148 /* Prints out context memory info.  (Only useful for CID 0 to 16.)          */
10149 /*                                                                          */
10150 /* Returns:                                                                 */
10151 /*   Nothing.                                                               */
10152 /****************************************************************************/
10153 static __attribute__ ((noinline)) void
10154 bce_dump_ctx(struct bce_softc *sc, u16 cid)
10155 {
10156         if (cid > TX_CID) {
10157                 BCE_PRINTF(" Unknown CID\n");
10158                 return;
10159         }
10160
10161         BCE_PRINTF(
10162             "----------------------------"
10163             "    CTX Data    "
10164             "----------------------------\n");
10165
10166         BCE_PRINTF("     0x%04X - (CID) Context ID\n", cid);
10167
10168         if (cid == RX_CID) {
10169                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx "
10170                    "producer index\n",
10171                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX));
10172                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host "
10173                     "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
10174                     BCE_L2CTX_RX_HOST_BSEQ));
10175                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n",
10176                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ));
10177                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer "
10178                     "descriptor address\n",
10179                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI));
10180                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer "
10181                     "descriptor address\n",
10182                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO));
10183                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer "
10184                     "index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10185                     BCE_L2CTX_RX_NX_BDIDX));
10186                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page "
10187                     "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10188                     BCE_L2CTX_RX_HOST_PG_BDIDX));
10189                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page "
10190                     "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid),
10191                     BCE_L2CTX_RX_PG_BUF_SIZE));
10192                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page "
10193                     "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
10194                     BCE_L2CTX_RX_NX_PG_BDHADDR_HI));
10195                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page "
10196                     "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
10197                     BCE_L2CTX_RX_NX_PG_BDHADDR_LO));
10198                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page "
10199                     "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10200                     BCE_L2CTX_RX_NX_PG_BDIDX));
10201         } else if (cid == TX_CID) {
10202                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
10203                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n",
10204                             CTX_RD(sc, GET_CID_ADDR(cid),
10205                             BCE_L2CTX_TX_TYPE_XI));
10206                         BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx "
10207                             "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid),
10208                             BCE_L2CTX_TX_CMD_TYPE_XI));
10209                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) "
10210                             "h/w buffer descriptor address\n",
10211                             CTX_RD(sc, GET_CID_ADDR(cid),
10212                             BCE_L2CTX_TX_TBDR_BHADDR_HI_XI));
10213                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) "
10214                             "h/w buffer descriptor address\n",
10215                             CTX_RD(sc, GET_CID_ADDR(cid),
10216                             BCE_L2CTX_TX_TBDR_BHADDR_LO_XI));
10217                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) "
10218                             "host producer index\n",
10219                             CTX_RD(sc, GET_CID_ADDR(cid),
10220                             BCE_L2CTX_TX_HOST_BIDX_XI));
10221                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) "
10222                             "host byte sequence\n",
10223                             CTX_RD(sc, GET_CID_ADDR(cid),
10224                             BCE_L2CTX_TX_HOST_BSEQ_XI));
10225                 } else {
10226                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n",
10227                             CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE));
10228                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n",
10229                             CTX_RD(sc, GET_CID_ADDR(cid),
10230                             BCE_L2CTX_TX_CMD_TYPE));
10231                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) "
10232                             "h/w buffer descriptor address\n",
10233                             CTX_RD(sc, GET_CID_ADDR(cid),
10234                             BCE_L2CTX_TX_TBDR_BHADDR_HI));
10235                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) "
10236                             "h/w buffer descriptor address\n",
10237                             CTX_RD(sc, GET_CID_ADDR(cid),
10238                             BCE_L2CTX_TX_TBDR_BHADDR_LO));
10239                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host "
10240                             "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10241                             BCE_L2CTX_TX_HOST_BIDX));
10242                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte "
10243                             "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
10244                             BCE_L2CTX_TX_HOST_BSEQ));
10245                 }
10246         }
10247
10248         BCE_PRINTF(
10249            "----------------------------"
10250            "    Raw CTX     "
10251            "----------------------------\n");
10252
10253         for (int i = 0x0; i < 0x300; i += 0x10) {
10254                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
10255                    CTX_RD(sc, GET_CID_ADDR(cid), i),
10256                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4),
10257                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8),
10258                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc));
10259         }
10260
10261
10262         BCE_PRINTF(
10263            "----------------------------"
10264            "----------------"
10265            "----------------------------\n");
10266 }
10267
10268
10269 /****************************************************************************/
10270 /* Prints out the FTQ data.                                                 */
10271 /*                                                                          */
10272 /* Returns:                                                                */
10273 /*   Nothing.                                                               */
10274 /****************************************************************************/
10275 static __attribute__ ((noinline)) void
10276 bce_dump_ftqs(struct bce_softc *sc)
10277 {
10278         u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val;
10279
10280         BCE_PRINTF(
10281             "----------------------------"
10282             "    FTQ Data    "
10283             "----------------------------\n");
10284
10285         BCE_PRINTF("   FTQ    Command    Control   Depth_Now  "
10286             "Max_Depth  Valid_Cnt \n");
10287         BCE_PRINTF(" ------- ---------- ---------- ---------- "
10288             "---------- ----------\n");
10289
10290         /* Setup the generic statistic counters for the FTQ valid count. */
10291         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) |
10292             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT  << 16) |
10293             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT   <<  8) |
10294             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT);
10295         REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10296
10297         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT  << 24) |
10298             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT  << 16) |
10299             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT <<  8) |
10300             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT);
10301         REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val);
10302
10303         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT  << 24) |
10304             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT  << 16) |
10305             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT   <<  8) |
10306             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT);
10307         REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val);
10308
10309         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT   << 24) |
10310             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT  << 16) |
10311             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT  <<  8) |
10312             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT);
10313         REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val);
10314
10315         /* Input queue to the Receive Lookup state machine */
10316         cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD);
10317         ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL);
10318         cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22;
10319         max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12;
10320         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
10321         BCE_PRINTF(" RLUP    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10322             cmd, ctl, cur_depth, max_depth, valid_cnt);
10323
10324         /* Input queue to the Receive Processor */
10325         cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD);
10326         ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL);
10327         cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22;
10328         max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12;
10329         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
10330         BCE_PRINTF(" RXP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10331             cmd, ctl, cur_depth, max_depth, valid_cnt);
10332
10333         /* Input queue to the Recevie Processor */
10334         cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD);
10335         ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL);
10336         cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22;
10337         max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12;
10338         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
10339         BCE_PRINTF(" RXPC    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10340             cmd, ctl, cur_depth, max_depth, valid_cnt);
10341
10342         /* Input queue to the Receive Virtual to Physical state machine */
10343         cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD);
10344         ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL);
10345         cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22;
10346         max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12;
10347         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
10348         BCE_PRINTF(" RV2PP   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10349             cmd, ctl, cur_depth, max_depth, valid_cnt);
10350
10351         /* Input queue to the Recevie Virtual to Physical state machine */
10352         cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD);
10353         ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL);
10354         cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22;
10355         max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12;
10356         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4);
10357         BCE_PRINTF(" RV2PM   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10358             cmd, ctl, cur_depth, max_depth, valid_cnt);
10359
10360         /* Input queue to the Receive Virtual to Physical state machine */
10361         cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD);
10362         ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL);
10363         cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22;
10364         max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12;
10365         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5);
10366         BCE_PRINTF(" RV2PT   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10367             cmd, ctl, cur_depth, max_depth, valid_cnt);
10368
10369         /* Input queue to the Receive DMA state machine */
10370         cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD);
10371         ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL);
10372         cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22;
10373         max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12;
10374         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6);
10375         BCE_PRINTF(" RDMA    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10376             cmd, ctl, cur_depth, max_depth, valid_cnt);
10377
10378         /* Input queue to the Transmit Scheduler state machine */
10379         cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD);
10380         ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL);
10381         cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22;
10382         max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12;
10383         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7);
10384         BCE_PRINTF(" TSCH    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10385             cmd, ctl, cur_depth, max_depth, valid_cnt);
10386
10387         /* Input queue to the Transmit Buffer Descriptor state machine */
10388         cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD);
10389         ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL);
10390         cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22;
10391         max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12;
10392         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8);
10393         BCE_PRINTF(" TBDR    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10394             cmd, ctl, cur_depth, max_depth, valid_cnt);
10395
10396         /* Input queue to the Transmit Processor */
10397         cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD);
10398         ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL);
10399         cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22;
10400         max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12;
10401         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9);
10402         BCE_PRINTF(" TXP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10403             cmd, ctl, cur_depth, max_depth, valid_cnt);
10404
10405         /* Input queue to the Transmit DMA state machine */
10406         cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD);
10407         ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL);
10408         cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22;
10409         max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12;
10410         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10);
10411         BCE_PRINTF(" TDMA    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10412             cmd, ctl, cur_depth, max_depth, valid_cnt);
10413
10414         /* Input queue to the Transmit Patch-Up Processor */
10415         cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD);
10416         ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL);
10417         cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22;
10418         max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12;
10419         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11);
10420         BCE_PRINTF(" TPAT    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10421             cmd, ctl, cur_depth, max_depth, valid_cnt);
10422
10423         /* Input queue to the Transmit Assembler state machine */
10424         cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD);
10425         ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL);
10426         cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22;
10427         max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12;
10428         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12);
10429         BCE_PRINTF(" TAS     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10430             cmd, ctl, cur_depth, max_depth, valid_cnt);
10431
10432         /* Input queue to the Completion Processor */
10433         cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD);
10434         ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL);
10435         cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22;
10436         max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12;
10437         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13);
10438         BCE_PRINTF(" COMX    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10439             cmd, ctl, cur_depth, max_depth, valid_cnt);
10440
10441         /* Input queue to the Completion Processor */
10442         cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD);
10443         ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL);
10444         cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22;
10445         max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12;
10446         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14);
10447         BCE_PRINTF(" COMT    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10448             cmd, ctl, cur_depth, max_depth, valid_cnt);
10449
10450         /* Input queue to the Completion Processor */
10451         cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD);
10452         ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL);
10453         cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22;
10454         max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12;
10455         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15);
10456         BCE_PRINTF(" COMX    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10457             cmd, ctl, cur_depth, max_depth, valid_cnt);
10458
10459         /* Setup the generic statistic counters for the FTQ valid count. */
10460         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT  << 16) |
10461             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT  <<  8) |
10462             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT);
10463
10464         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
10465                 val = val |
10466                     (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI <<
10467                      24);
10468         REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10469
10470         /* Input queue to the Management Control Processor */
10471         cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD);
10472         ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL);
10473         cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22;
10474         max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12;
10475         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
10476         BCE_PRINTF(" MCP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10477             cmd, ctl, cur_depth, max_depth, valid_cnt);
10478
10479         /* Input queue to the Command Processor */
10480         cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD);
10481         ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL);
10482         cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22;
10483         max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12;
10484         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
10485         BCE_PRINTF(" CP      0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10486             cmd, ctl, cur_depth, max_depth, valid_cnt);
10487
10488         /* Input queue to the Completion Scheduler state machine */
10489         cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD);
10490         ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL);
10491         cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22;
10492         max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12;
10493         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
10494         BCE_PRINTF(" CS      0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10495             cmd, ctl, cur_depth, max_depth, valid_cnt);
10496
10497         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
10498                 /* Input queue to the RV2P Command Scheduler */
10499                 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD);
10500                 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL);
10501                 cur_depth = (ctl & 0xFFC00000) >> 22;
10502                 max_depth = (ctl & 0x003FF000) >> 12;
10503                 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
10504                 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10505                     cmd, ctl, cur_depth, max_depth, valid_cnt);
10506         }
10507
10508         BCE_PRINTF(
10509             "----------------------------"
10510             "----------------"
10511             "----------------------------\n");
10512 }
10513
10514
10515 /****************************************************************************/
10516 /* Prints out the TX chain.                                                 */
10517 /*                                                                          */
10518 /* Returns:                                                                 */
10519 /*   Nothing.                                                               */
10520 /****************************************************************************/
10521 static __attribute__ ((noinline)) void
10522 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count)
10523 {
10524         struct tx_bd *txbd;
10525
10526         /* First some info about the tx_bd chain structure. */
10527         BCE_PRINTF(
10528             "----------------------------"
10529             "  tx_bd  chain  "
10530             "----------------------------\n");
10531
10532         BCE_PRINTF("page size      = 0x%08X, tx chain pages        = 0x%08X\n",
10533             (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages);
10534         BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n",
10535             (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE);
10536         BCE_PRINTF("total tx_bd    = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC);
10537
10538         BCE_PRINTF(
10539             "----------------------------"
10540             "   tx_bd data   "
10541             "----------------------------\n");
10542
10543         /* Now print out a decoded list of TX buffer descriptors. */
10544         for (int i = 0; i < count; i++) {
10545                 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
10546                 bce_dump_txbd(sc, tx_prod, txbd);
10547                 tx_prod++;
10548         }
10549
10550         BCE_PRINTF(
10551             "----------------------------"
10552             "----------------"
10553             "----------------------------\n");
10554 }
10555
10556
10557 /****************************************************************************/
10558 /* Prints out the RX chain.                                                 */
10559 /*                                                                          */
10560 /* Returns:                                                                 */
10561 /*   Nothing.                                                               */
10562 /****************************************************************************/
10563 static __attribute__ ((noinline)) void
10564 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count)
10565 {
10566         struct rx_bd *rxbd;
10567
10568         /* First some info about the rx_bd chain structure. */
10569         BCE_PRINTF(
10570             "----------------------------"
10571             "  rx_bd  chain  "
10572             "----------------------------\n");
10573
10574         BCE_PRINTF("page size      = 0x%08X, rx chain pages        = 0x%08X\n",
10575             (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages);
10576
10577         BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
10578             (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE);
10579
10580         BCE_PRINTF("total rx_bd    = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC);
10581
10582         BCE_PRINTF(
10583             "----------------------------"
10584             "   rx_bd data   "
10585             "----------------------------\n");
10586
10587         /* Now print out the rx_bd's themselves. */
10588         for (int i = 0; i < count; i++) {
10589                 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
10590                 bce_dump_rxbd(sc, rx_prod, rxbd);
10591                 rx_prod = RX_CHAIN_IDX(rx_prod + 1);
10592         }
10593
10594         BCE_PRINTF(
10595             "----------------------------"
10596             "----------------"
10597             "----------------------------\n");
10598 }
10599
10600
10601 /****************************************************************************/
10602 /* Prints out the page chain.                                               */
10603 /*                                                                          */
10604 /* Returns:                                                                 */
10605 /*   Nothing.                                                               */
10606 /****************************************************************************/
10607 static __attribute__ ((noinline)) void
10608 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count)
10609 {
10610         struct rx_bd *pgbd;
10611
10612         /* First some info about the page chain structure. */
10613         BCE_PRINTF(
10614             "----------------------------"
10615             "   page chain   "
10616             "----------------------------\n");
10617
10618         BCE_PRINTF("page size      = 0x%08X, pg chain pages        = 0x%08X\n",
10619             (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages);
10620
10621         BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
10622             (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE);
10623
10624         BCE_PRINTF("total pg_bd             = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC);
10625
10626         BCE_PRINTF(
10627             "----------------------------"
10628             "   page data    "
10629             "----------------------------\n");
10630
10631         /* Now print out the rx_bd's themselves. */
10632         for (int i = 0; i < count; i++) {
10633                 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)];
10634                 bce_dump_pgbd(sc, pg_prod, pgbd);
10635                 pg_prod = PG_CHAIN_IDX(pg_prod + 1);
10636         }
10637
10638         BCE_PRINTF(
10639             "----------------------------"
10640             "----------------"
10641             "----------------------------\n");
10642 }
10643
10644
10645 #define BCE_PRINT_RX_CONS(arg)                                          \
10646 if (sblk->status_rx_quick_consumer_index##arg)                          \
10647         BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n",      \
10648             sblk->status_rx_quick_consumer_index##arg, (u16)            \
10649             RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg),    \
10650             arg);
10651
10652
10653 #define BCE_PRINT_TX_CONS(arg)                                          \
10654 if (sblk->status_tx_quick_consumer_index##arg)                          \
10655         BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n",      \
10656             sblk->status_tx_quick_consumer_index##arg, (u16)            \
10657             TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg),    \
10658             arg);
10659
10660 /****************************************************************************/
10661 /* Prints out the status block from host memory.                            */
10662 /*                                                                          */
10663 /* Returns:                                                                 */
10664 /*   Nothing.                                                               */
10665 /****************************************************************************/
10666 static __attribute__ ((noinline)) void
10667 bce_dump_status_block(struct bce_softc *sc)
10668 {
10669         struct status_block *sblk;
10670
10671         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
10672
10673         sblk = sc->status_block;
10674
10675         BCE_PRINTF(
10676             "----------------------------"
10677             "  Status Block  "
10678             "----------------------------\n");
10679
10680         /* Theses indices are used for normal L2 drivers. */
10681         BCE_PRINTF("    0x%08X - attn_bits\n",
10682             sblk->status_attn_bits);
10683
10684         BCE_PRINTF("    0x%08X - attn_bits_ack\n",
10685             sblk->status_attn_bits_ack);
10686
10687         BCE_PRINT_RX_CONS(0);
10688         BCE_PRINT_TX_CONS(0)
10689
10690         BCE_PRINTF("        0x%04X - status_idx\n", sblk->status_idx);
10691
10692         /* Theses indices are not used for normal L2 drivers. */
10693         BCE_PRINT_RX_CONS(1);   BCE_PRINT_RX_CONS(2);   BCE_PRINT_RX_CONS(3);
10694         BCE_PRINT_RX_CONS(4);   BCE_PRINT_RX_CONS(5);   BCE_PRINT_RX_CONS(6);
10695         BCE_PRINT_RX_CONS(7);   BCE_PRINT_RX_CONS(8);   BCE_PRINT_RX_CONS(9);
10696         BCE_PRINT_RX_CONS(10);  BCE_PRINT_RX_CONS(11);  BCE_PRINT_RX_CONS(12);
10697         BCE_PRINT_RX_CONS(13);  BCE_PRINT_RX_CONS(14);  BCE_PRINT_RX_CONS(15);
10698
10699         BCE_PRINT_TX_CONS(1);   BCE_PRINT_TX_CONS(2);   BCE_PRINT_TX_CONS(3);
10700
10701         if (sblk->status_completion_producer_index ||
10702             sblk->status_cmd_consumer_index)
10703                 BCE_PRINTF("com_prod  = 0x%08X, cmd_cons      = 0x%08X\n",
10704                     sblk->status_completion_producer_index,
10705                     sblk->status_cmd_consumer_index);
10706
10707         BCE_PRINTF(
10708             "----------------------------"
10709             "----------------"
10710             "----------------------------\n");
10711 }
10712
10713
10714 #define BCE_PRINT_64BIT_STAT(arg)                               \
10715 if (sblk->arg##_lo || sblk->arg##_hi)                           \
10716         BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi,        \
10717             sblk->arg##_lo, #arg);
10718
10719 #define BCE_PRINT_32BIT_STAT(arg)                               \
10720 if (sblk->arg)                                                  \
10721         BCE_PRINTF("         0x%08X : %s\n",                    \
10722             sblk->arg, #arg);
10723
10724 /****************************************************************************/
10725 /* Prints out the statistics block from host memory.                        */
10726 /*                                                                          */
10727 /* Returns:                                                                 */
10728 /*   Nothing.                                                               */
10729 /****************************************************************************/
10730 static __attribute__ ((noinline)) void
10731 bce_dump_stats_block(struct bce_softc *sc)
10732 {
10733         struct statistics_block *sblk;
10734
10735         bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD);
10736
10737         sblk = sc->stats_block;
10738
10739         BCE_PRINTF(
10740             "---------------"
10741             " Stats Block  (All Stats Not Shown Are 0) "
10742             "---------------\n");
10743
10744         BCE_PRINT_64BIT_STAT(stat_IfHCInOctets);
10745         BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets);
10746         BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets);
10747         BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets);
10748         BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts);
10749         BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts);
10750         BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts);
10751         BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts);
10752         BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts);
10753         BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts);
10754         BCE_PRINT_32BIT_STAT(
10755             stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
10756         BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors);
10757         BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors);
10758         BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors);
10759         BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames);
10760         BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames);
10761         BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions);
10762         BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions);
10763         BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions);
10764         BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions);
10765         BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments);
10766         BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers);
10767         BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts);
10768         BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts);
10769         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets);
10770         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets);
10771         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets);
10772         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets);
10773         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets);
10774         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets);
10775         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets);
10776         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets);
10777         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets);
10778         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets);
10779         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets);
10780         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets);
10781         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets);
10782         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets);
10783         BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived);
10784         BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived);
10785         BCE_PRINT_32BIT_STAT(stat_OutXonSent);
10786         BCE_PRINT_32BIT_STAT(stat_OutXoffSent);
10787         BCE_PRINT_32BIT_STAT(stat_FlowControlDone);
10788         BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived);
10789         BCE_PRINT_32BIT_STAT(stat_XoffStateEntered);
10790         BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards);
10791         BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards);
10792         BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards);
10793         BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards);
10794         BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit);
10795         BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards);
10796         BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards);
10797         BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards);
10798         BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit);
10799
10800         BCE_PRINTF(
10801             "----------------------------"
10802             "----------------"
10803             "----------------------------\n");
10804 }
10805
10806
10807 /****************************************************************************/
10808 /* Prints out a summary of the driver state.                                */
10809 /*                                                                          */
10810 /* Returns:                                                                 */
10811 /*   Nothing.                                                               */
10812 /****************************************************************************/
10813 static __attribute__ ((noinline)) void
10814 bce_dump_driver_state(struct bce_softc *sc)
10815 {
10816         u32 val_hi, val_lo;
10817
10818         BCE_PRINTF(
10819             "-----------------------------"
10820             " Driver State "
10821             "-----------------------------\n");
10822
10823         val_hi = BCE_ADDR_HI(sc);
10824         val_lo = BCE_ADDR_LO(sc);
10825         BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual "
10826             "address\n", val_hi, val_lo);
10827
10828         val_hi = BCE_ADDR_HI(sc->bce_vhandle);
10829         val_lo = BCE_ADDR_LO(sc->bce_vhandle);
10830         BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual "
10831             "address\n", val_hi, val_lo);
10832
10833         val_hi = BCE_ADDR_HI(sc->status_block);
10834         val_lo = BCE_ADDR_LO(sc->status_block);
10835         BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block "
10836             "virtual address\n",        val_hi, val_lo);
10837
10838         val_hi = BCE_ADDR_HI(sc->stats_block);
10839         val_lo = BCE_ADDR_LO(sc->stats_block);
10840         BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block "
10841             "virtual address\n", val_hi, val_lo);
10842
10843         val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
10844         val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
10845         BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
10846             "virtual adddress\n", val_hi, val_lo);
10847
10848         val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
10849         val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
10850         BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
10851             "virtual address\n", val_hi, val_lo);
10852
10853         if (bce_hdr_split == TRUE) {
10854                 val_hi = BCE_ADDR_HI(sc->pg_bd_chain);
10855                 val_lo = BCE_ADDR_LO(sc->pg_bd_chain);
10856                 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain "
10857                     "virtual address\n", val_hi, val_lo);
10858         }
10859
10860         val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
10861         val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
10862         BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
10863             "virtual address\n",        val_hi, val_lo);
10864
10865         val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
10866         val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
10867         BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
10868             "virtual address\n", val_hi, val_lo);
10869
10870         if (bce_hdr_split == TRUE) {
10871                 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr);
10872                 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr);
10873                 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain "
10874                     "virtual address\n", val_hi, val_lo);
10875         }
10876
10877         BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) "
10878             "h/w intrs\n",
10879             (long long unsigned int) sc->interrupts_generated);
10880
10881         BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) "
10882             "rx interrupts handled\n",
10883             (long long unsigned int) sc->interrupts_rx);
10884
10885         BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) "
10886             "tx interrupts handled\n",
10887             (long long unsigned int) sc->interrupts_tx);
10888
10889         BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) "
10890             "phy interrupts handled\n",
10891             (long long unsigned int) sc->phy_interrupts);
10892
10893         BCE_PRINTF("         0x%08X - (sc->last_status_idx) "
10894             "status block index\n", sc->last_status_idx);
10895
10896         BCE_PRINTF("     0x%04X(0x%04X) - (sc->tx_prod) tx producer "
10897             "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod));
10898
10899         BCE_PRINTF("     0x%04X(0x%04X) - (sc->tx_cons) tx consumer "
10900             "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons));
10901
10902         BCE_PRINTF("         0x%08X - (sc->tx_prod_bseq) tx producer "
10903             "byte seq index\n", sc->tx_prod_bseq);
10904
10905         BCE_PRINTF("         0x%08X - (sc->debug_tx_mbuf_alloc) tx "
10906             "mbufs allocated\n", sc->debug_tx_mbuf_alloc);
10907
10908         BCE_PRINTF("         0x%08X - (sc->used_tx_bd) used "
10909             "tx_bd's\n", sc->used_tx_bd);
10910
10911         BCE_PRINTF("      0x%04X/0x%04X - (sc->tx_hi_watermark)/"
10912             "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd);
10913
10914         BCE_PRINTF("     0x%04X(0x%04X) - (sc->rx_prod) rx producer "
10915             "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod));
10916
10917         BCE_PRINTF("     0x%04X(0x%04X) - (sc->rx_cons) rx consumer "
10918             "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons));
10919
10920         BCE_PRINTF("         0x%08X - (sc->rx_prod_bseq) rx producer "
10921             "byte seq index\n", sc->rx_prod_bseq);
10922
10923         BCE_PRINTF("      0x%04X/0x%04X - (sc->rx_low_watermark)/"
10924                    "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd);
10925
10926         BCE_PRINTF("         0x%08X - (sc->debug_rx_mbuf_alloc) rx "
10927             "mbufs allocated\n", sc->debug_rx_mbuf_alloc);
10928
10929         BCE_PRINTF("         0x%08X - (sc->free_rx_bd) free "
10930             "rx_bd's\n", sc->free_rx_bd);
10931
10932         if (bce_hdr_split == TRUE) {
10933                 BCE_PRINTF("     0x%04X(0x%04X) - (sc->pg_prod) page producer "
10934                     "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod));
10935
10936                 BCE_PRINTF("     0x%04X(0x%04X) - (sc->pg_cons) page consumer "
10937                     "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons));
10938
10939                 BCE_PRINTF("         0x%08X - (sc->debug_pg_mbuf_alloc) page "
10940                     "mbufs allocated\n", sc->debug_pg_mbuf_alloc);
10941         }
10942
10943         BCE_PRINTF("         0x%08X - (sc->free_pg_bd) free page "
10944             "rx_bd's\n", sc->free_pg_bd);
10945
10946         BCE_PRINTF("      0x%04X/0x%04X - (sc->pg_low_watermark)/"
10947             "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd);
10948
10949         BCE_PRINTF("         0x%08X - (sc->mbuf_alloc_failed_count) "
10950             "mbuf alloc failures\n", sc->mbuf_alloc_failed_count);
10951
10952         BCE_PRINTF("         0x%08X - (sc->bce_flags) "
10953             "bce mac flags\n", sc->bce_flags);
10954
10955         BCE_PRINTF("         0x%08X - (sc->bce_phy_flags) "
10956             "bce phy flags\n", sc->bce_phy_flags);
10957
10958         BCE_PRINTF(
10959             "----------------------------"
10960             "----------------"
10961             "----------------------------\n");
10962 }
10963
10964
10965 /****************************************************************************/
10966 /* Prints out the hardware state through a summary of important register,   */
10967 /* followed by a complete register dump.                                    */
10968 /*                                                                          */
10969 /* Returns:                                                                 */
10970 /*   Nothing.                                                               */
10971 /****************************************************************************/
10972 static __attribute__ ((noinline)) void
10973 bce_dump_hw_state(struct bce_softc *sc)
10974 {
10975         u32 val;
10976
10977         BCE_PRINTF(
10978             "----------------------------"
10979             " Hardware State "
10980             "----------------------------\n");
10981
10982         BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
10983
10984         val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
10985         BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n",
10986             val, BCE_MISC_ENABLE_STATUS_BITS);
10987
10988         val = REG_RD(sc, BCE_DMA_STATUS);
10989         BCE_PRINTF("0x%08X - (0x%06X) dma_status\n",
10990             val, BCE_DMA_STATUS);
10991
10992         val = REG_RD(sc, BCE_CTX_STATUS);
10993         BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n",
10994             val, BCE_CTX_STATUS);
10995
10996         val = REG_RD(sc, BCE_EMAC_STATUS);
10997         BCE_PRINTF("0x%08X - (0x%06X) emac_status\n",
10998             val, BCE_EMAC_STATUS);
10999
11000         val = REG_RD(sc, BCE_RPM_STATUS);
11001         BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n",
11002             val, BCE_RPM_STATUS);
11003
11004         /* ToDo: Create a #define for this constant. */
11005         val = REG_RD(sc, 0x2004);
11006         BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n",
11007             val, 0x2004);
11008
11009         val = REG_RD(sc, BCE_RV2P_STATUS);
11010         BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n",
11011             val, BCE_RV2P_STATUS);
11012
11013         /* ToDo: Create a #define for this constant. */
11014         val = REG_RD(sc, 0x2c04);
11015         BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n",
11016             val, 0x2c04);
11017
11018         val = REG_RD(sc, BCE_TBDR_STATUS);
11019         BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n",
11020             val, BCE_TBDR_STATUS);
11021
11022         val = REG_RD(sc, BCE_TDMA_STATUS);
11023         BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n",
11024             val, BCE_TDMA_STATUS);
11025
11026         val = REG_RD(sc, BCE_HC_STATUS);
11027         BCE_PRINTF("0x%08X - (0x%06X) hc_status\n",
11028             val, BCE_HC_STATUS);
11029
11030         val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
11031         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
11032             val, BCE_TXP_CPU_STATE);
11033
11034         val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11035         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
11036             val, BCE_TPAT_CPU_STATE);
11037
11038         val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11039         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
11040             val, BCE_RXP_CPU_STATE);
11041
11042         val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11043         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
11044             val, BCE_COM_CPU_STATE);
11045
11046         val = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
11047         BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n",
11048             val, BCE_MCP_CPU_STATE);
11049
11050         val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11051         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
11052             val, BCE_CP_CPU_STATE);
11053
11054         BCE_PRINTF(
11055             "----------------------------"
11056             "----------------"
11057             "----------------------------\n");
11058
11059         BCE_PRINTF(
11060             "----------------------------"
11061             " Register  Dump "
11062             "----------------------------\n");
11063
11064         for (int i = 0x400; i < 0x8000; i += 0x10) {
11065                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11066                     i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
11067                     REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
11068         }
11069
11070         BCE_PRINTF(
11071             "----------------------------"
11072             "----------------"
11073             "----------------------------\n");
11074 }
11075
11076
11077 /****************************************************************************/
11078 /* Prints out the contentst of shared memory which is used for host driver  */
11079 /* to bootcode firmware communication.                                      */
11080 /*                                                                          */
11081 /* Returns:                                                                 */
11082 /*   Nothing.                                                               */
11083 /****************************************************************************/
11084 static __attribute__ ((noinline)) void
11085 bce_dump_shmem_state(struct bce_softc *sc)
11086 {
11087         BCE_PRINTF(
11088             "----------------------------"
11089             " Hardware State "
11090             "----------------------------\n");
11091
11092         BCE_PRINTF("0x%08X - Shared memory base address\n",
11093             sc->bce_shmem_base);
11094         BCE_PRINTF("%s - bootcode version\n",
11095             sc->bce_bc_ver);
11096
11097         BCE_PRINTF(
11098             "----------------------------"
11099             "   Shared Mem   "
11100             "----------------------------\n");
11101
11102         for (int i = 0x0; i < 0x200; i += 0x10) {
11103                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11104                     i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4),
11105                     bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC));
11106         }
11107
11108         BCE_PRINTF(
11109             "----------------------------"
11110             "----------------"
11111             "----------------------------\n");
11112 }
11113
11114
11115 /****************************************************************************/
11116 /* Prints out the mailbox queue registers.                                  */
11117 /*                                                                          */
11118 /* Returns:                                                                 */
11119 /*   Nothing.                                                               */
11120 /****************************************************************************/
11121 static __attribute__ ((noinline)) void
11122 bce_dump_mq_regs(struct bce_softc *sc)
11123 {
11124         BCE_PRINTF(
11125             "----------------------------"
11126             "    MQ Regs     "
11127             "----------------------------\n");
11128
11129         BCE_PRINTF(
11130             "----------------------------"
11131             "----------------"
11132             "----------------------------\n");
11133
11134         for (int i = 0x3c00; i < 0x4000; i += 0x10) {
11135                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11136                     i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
11137                     REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
11138         }
11139
11140         BCE_PRINTF(
11141             "----------------------------"
11142             "----------------"
11143             "----------------------------\n");
11144 }
11145
11146
11147 /****************************************************************************/
11148 /* Prints out the bootcode state.                                           */
11149 /*                                                                          */
11150 /* Returns:                                                                 */
11151 /*   Nothing.                                                               */
11152 /****************************************************************************/
11153 static __attribute__ ((noinline)) void
11154 bce_dump_bc_state(struct bce_softc *sc)
11155 {
11156         u32 val;
11157
11158         BCE_PRINTF(
11159             "----------------------------"
11160             " Bootcode State "
11161             "----------------------------\n");
11162
11163         BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
11164
11165         val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE);
11166         BCE_PRINTF("0x%08X - (0x%06X) reset_type\n",
11167             val, BCE_BC_RESET_TYPE);
11168
11169         val = bce_shmem_rd(sc, BCE_BC_STATE);
11170         BCE_PRINTF("0x%08X - (0x%06X) state\n",
11171             val, BCE_BC_STATE);
11172
11173         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
11174         BCE_PRINTF("0x%08X - (0x%06X) condition\n",
11175             val, BCE_BC_STATE_CONDITION);
11176
11177         val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD);
11178         BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n",
11179             val, BCE_BC_STATE_DEBUG_CMD);
11180
11181         BCE_PRINTF(
11182             "----------------------------"
11183             "----------------"
11184             "----------------------------\n");
11185 }
11186
11187
11188 /****************************************************************************/
11189 /* Prints out the TXP processor state.                                      */
11190 /*                                                                          */
11191 /* Returns:                                                                 */
11192 /*   Nothing.                                                               */
11193 /****************************************************************************/
11194 static __attribute__ ((noinline)) void
11195 bce_dump_txp_state(struct bce_softc *sc, int regs)
11196 {
11197         u32 val;
11198         u32 fw_version[3];
11199
11200         BCE_PRINTF(
11201             "----------------------------"
11202             "   TXP  State   "
11203             "----------------------------\n");
11204
11205         for (int i = 0; i < 3; i++)
11206                 fw_version[i] = htonl(REG_RD_IND(sc,
11207                     (BCE_TXP_SCRATCH + 0x10 + i * 4)));
11208         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11209
11210         val = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
11211         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n",
11212             val, BCE_TXP_CPU_MODE);
11213
11214         val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
11215         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
11216             val, BCE_TXP_CPU_STATE);
11217
11218         val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
11219         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n",
11220             val, BCE_TXP_CPU_EVENT_MASK);
11221
11222         if (regs) {
11223                 BCE_PRINTF(
11224                     "----------------------------"
11225                     " Register  Dump "
11226                     "----------------------------\n");
11227
11228                 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
11229                         /* Skip the big blank spaces */
11230                         if (i < 0x454000 && i > 0x5ffff)
11231                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11232                                     "0x%08X 0x%08X\n", i,
11233                                     REG_RD_IND(sc, i),
11234                                     REG_RD_IND(sc, i + 0x4),
11235                                     REG_RD_IND(sc, i + 0x8),
11236                                     REG_RD_IND(sc, i + 0xC));
11237                 }
11238         }
11239
11240         BCE_PRINTF(
11241             "----------------------------"
11242             "----------------"
11243             "----------------------------\n");
11244 }
11245
11246
11247 /****************************************************************************/
11248 /* Prints out the RXP processor state.                                      */
11249 /*                                                                          */
11250 /* Returns:                                                                 */
11251 /*   Nothing.                                                               */
11252 /****************************************************************************/
11253 static __attribute__ ((noinline)) void
11254 bce_dump_rxp_state(struct bce_softc *sc, int regs)
11255 {
11256         u32 val;
11257         u32 fw_version[3];
11258
11259         BCE_PRINTF(
11260             "----------------------------"
11261             "   RXP  State   "
11262             "----------------------------\n");
11263
11264         for (int i = 0; i < 3; i++)
11265                 fw_version[i] = htonl(REG_RD_IND(sc,
11266                     (BCE_RXP_SCRATCH + 0x10 + i * 4)));
11267
11268         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11269
11270         val = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
11271         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n",
11272             val, BCE_RXP_CPU_MODE);
11273
11274         val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11275         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
11276             val, BCE_RXP_CPU_STATE);
11277
11278         val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
11279         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n",
11280             val, BCE_RXP_CPU_EVENT_MASK);
11281
11282         if (regs) {
11283                 BCE_PRINTF(
11284                     "----------------------------"
11285                     " Register  Dump "
11286                     "----------------------------\n");
11287
11288                 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
11289                         /* Skip the big blank sapces */
11290                         if (i < 0xc5400 && i > 0xdffff)
11291                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11292                                     "0x%08X 0x%08X\n", i,
11293                                     REG_RD_IND(sc, i),
11294                                     REG_RD_IND(sc, i + 0x4),
11295                                     REG_RD_IND(sc, i + 0x8),
11296                                     REG_RD_IND(sc, i + 0xC));
11297                 }
11298         }
11299
11300         BCE_PRINTF(
11301             "----------------------------"
11302             "----------------"
11303             "----------------------------\n");
11304 }
11305
11306
11307 /****************************************************************************/
11308 /* Prints out the TPAT processor state.                                     */
11309 /*                                                                          */
11310 /* Returns:                                                                 */
11311 /*   Nothing.                                                               */
11312 /****************************************************************************/
11313 static __attribute__ ((noinline)) void
11314 bce_dump_tpat_state(struct bce_softc *sc, int regs)
11315 {
11316         u32 val;
11317         u32 fw_version[3];
11318
11319         BCE_PRINTF(
11320             "----------------------------"
11321             "   TPAT State   "
11322             "----------------------------\n");
11323
11324         for (int i = 0; i < 3; i++)
11325                 fw_version[i] = htonl(REG_RD_IND(sc,
11326                     (BCE_TPAT_SCRATCH + 0x410 + i * 4)));
11327
11328         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11329
11330         val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
11331         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n",
11332             val, BCE_TPAT_CPU_MODE);
11333
11334         val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11335         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
11336             val, BCE_TPAT_CPU_STATE);
11337
11338         val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
11339         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n",
11340             val, BCE_TPAT_CPU_EVENT_MASK);
11341
11342         if (regs) {
11343                 BCE_PRINTF(
11344                     "----------------------------"
11345                     " Register  Dump "
11346                     "----------------------------\n");
11347
11348                 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
11349                         /* Skip the big blank spaces */
11350                         if (i < 0x854000 && i > 0x9ffff)
11351                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11352                                     "0x%08X 0x%08X\n", i,
11353                                     REG_RD_IND(sc, i),
11354                                     REG_RD_IND(sc, i + 0x4),
11355                                     REG_RD_IND(sc, i + 0x8),
11356                                     REG_RD_IND(sc, i + 0xC));
11357                 }
11358         }
11359
11360         BCE_PRINTF(
11361                 "----------------------------"
11362                 "----------------"
11363                 "----------------------------\n");
11364 }
11365
11366
11367 /****************************************************************************/
11368 /* Prints out the Command Procesor (CP) state.                              */
11369 /*                                                                          */
11370 /* Returns:                                                                 */
11371 /*   Nothing.                                                               */
11372 /****************************************************************************/
11373 static __attribute__ ((noinline)) void
11374 bce_dump_cp_state(struct bce_softc *sc, int regs)
11375 {
11376         u32 val;
11377         u32 fw_version[3];
11378
11379         BCE_PRINTF(
11380             "----------------------------"
11381             "    CP State    "
11382             "----------------------------\n");
11383
11384         for (int i = 0; i < 3; i++)
11385                 fw_version[i] = htonl(REG_RD_IND(sc,
11386                     (BCE_CP_SCRATCH + 0x10 + i * 4)));
11387
11388         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11389
11390         val = REG_RD_IND(sc, BCE_CP_CPU_MODE);
11391         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n",
11392             val, BCE_CP_CPU_MODE);
11393
11394         val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11395         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
11396             val, BCE_CP_CPU_STATE);
11397
11398         val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK);
11399         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val,
11400             BCE_CP_CPU_EVENT_MASK);
11401
11402         if (regs) {
11403                 BCE_PRINTF(
11404                     "----------------------------"
11405                     " Register  Dump "
11406                     "----------------------------\n");
11407
11408                 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) {
11409                         /* Skip the big blank spaces */
11410                         if (i < 0x185400 && i > 0x19ffff)
11411                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11412                                     "0x%08X 0x%08X\n", i,
11413                                     REG_RD_IND(sc, i),
11414                                     REG_RD_IND(sc, i + 0x4),
11415                                     REG_RD_IND(sc, i + 0x8),
11416                                     REG_RD_IND(sc, i + 0xC));
11417                 }
11418         }
11419
11420         BCE_PRINTF(
11421             "----------------------------"
11422             "----------------"
11423             "----------------------------\n");
11424 }
11425
11426
11427 /****************************************************************************/
11428 /* Prints out the Completion Procesor (COM) state.                          */
11429 /*                                                                          */
11430 /* Returns:                                                                 */
11431 /*   Nothing.                                                               */
11432 /****************************************************************************/
11433 static __attribute__ ((noinline)) void
11434 bce_dump_com_state(struct bce_softc *sc, int regs)
11435 {
11436         u32 val;
11437         u32 fw_version[4];
11438
11439         BCE_PRINTF(
11440             "----------------------------"
11441             "   COM State    "
11442             "----------------------------\n");
11443
11444         for (int i = 0; i < 3; i++)
11445                 fw_version[i] = htonl(REG_RD_IND(sc,
11446                     (BCE_COM_SCRATCH + 0x10 + i * 4)));
11447
11448         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11449
11450         val = REG_RD_IND(sc, BCE_COM_CPU_MODE);
11451         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n",
11452             val, BCE_COM_CPU_MODE);
11453
11454         val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11455         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
11456             val, BCE_COM_CPU_STATE);
11457
11458         val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK);
11459         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val,
11460             BCE_COM_CPU_EVENT_MASK);
11461
11462         if (regs) {
11463                 BCE_PRINTF(
11464                     "----------------------------"
11465                     " Register  Dump "
11466                     "----------------------------\n");
11467
11468                 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) {
11469                         BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11470                             "0x%08X 0x%08X\n", i,
11471                             REG_RD_IND(sc, i),
11472                             REG_RD_IND(sc, i + 0x4),
11473                             REG_RD_IND(sc, i + 0x8),
11474                             REG_RD_IND(sc, i + 0xC));
11475                 }
11476         }
11477
11478         BCE_PRINTF(
11479                 "----------------------------"
11480                 "----------------"
11481                 "----------------------------\n");
11482 }
11483
11484
11485 /****************************************************************************/
11486 /* Prints out the Receive Virtual 2 Physical (RV2P) state.                  */
11487 /*                                                                          */
11488 /* Returns:                                                                 */
11489 /*   Nothing.                                                               */
11490 /****************************************************************************/
11491 static __attribute__ ((noinline)) void
11492 bce_dump_rv2p_state(struct bce_softc *sc)
11493 {
11494         u32 val, pc1, pc2, fw_ver_high, fw_ver_low;
11495
11496         BCE_PRINTF(
11497             "----------------------------"
11498             "   RV2P State   "
11499             "----------------------------\n");
11500
11501         /* Stall the RV2P processors. */
11502         val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11503         val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2;
11504         REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
11505
11506         /* Read the firmware version. */
11507         val = 0x00000001;
11508         REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
11509         fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
11510         fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
11511             BCE_RV2P_INSTR_HIGH_HIGH;
11512         BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n",
11513             fw_ver_high, fw_ver_low);
11514
11515         val = 0x00000001;
11516         REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
11517         fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
11518         fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
11519             BCE_RV2P_INSTR_HIGH_HIGH;
11520         BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n",
11521             fw_ver_high, fw_ver_low);
11522
11523         /* Resume the RV2P processors. */
11524         val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11525         val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2);
11526         REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
11527
11528         /* Fetch the program counter value. */
11529         val = 0x68007800;
11530         REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
11531         val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11532         pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
11533         pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
11534         BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1);
11535         BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2);
11536
11537         /* Fetch the program counter value again to see if it is advancing. */
11538         val = 0x68007800;
11539         REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
11540         val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11541         pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
11542         pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
11543         BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1);
11544         BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2);
11545
11546         BCE_PRINTF(
11547             "----------------------------"
11548             "----------------"
11549             "----------------------------\n");
11550 }
11551
11552
11553 /****************************************************************************/
11554 /* Prints out the driver state and then enters the debugger.                */
11555 /*                                                                          */
11556 /* Returns:                                                                 */
11557 /*   Nothing.                                                               */
11558 /****************************************************************************/
11559 static __attribute__ ((noinline)) void
11560 bce_breakpoint(struct bce_softc *sc)
11561 {
11562
11563         /*
11564          * Unreachable code to silence compiler warnings
11565          * about unused functions.
11566          */
11567         if (0) {
11568                 bce_freeze_controller(sc);
11569                 bce_unfreeze_controller(sc);
11570                 bce_dump_enet(sc, NULL);
11571                 bce_dump_txbd(sc, 0, NULL);
11572                 bce_dump_rxbd(sc, 0, NULL);
11573                 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC);
11574                 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC);
11575                 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC);
11576                 bce_dump_l2fhdr(sc, 0, NULL);
11577                 bce_dump_ctx(sc, RX_CID);
11578                 bce_dump_ftqs(sc);
11579                 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC);
11580                 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC);
11581                 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC);
11582                 bce_dump_status_block(sc);
11583                 bce_dump_stats_block(sc);
11584                 bce_dump_driver_state(sc);
11585                 bce_dump_hw_state(sc);
11586                 bce_dump_bc_state(sc);
11587                 bce_dump_txp_state(sc, 0);
11588                 bce_dump_rxp_state(sc, 0);
11589                 bce_dump_tpat_state(sc, 0);
11590                 bce_dump_cp_state(sc, 0);
11591                 bce_dump_com_state(sc, 0);
11592                 bce_dump_rv2p_state(sc);
11593                 bce_dump_pgbd(sc, 0, NULL);
11594         }
11595
11596         bce_dump_status_block(sc);
11597         bce_dump_driver_state(sc);
11598
11599         /* Call the debugger. */
11600         breakpoint();
11601 }
11602 #endif