2 * Copyright (c) 2006-2010 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written consent.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
35 * The following controllers are supported by this driver:
45 * The following controllers are not supported by this driver:
46 * BCM5706C A0, A1 (pre-production)
47 * BCM5706S A0, A1 (pre-production)
48 * BCM5708C A0, B0 (pre-production)
49 * BCM5708S A0, B0 (pre-production)
50 * BCM5709C A0 B0, B1, B2 (pre-production)
51 * BCM5709S A0, B0, B1, B2 (pre-production)
56 #include <dev/bce/if_bcereg.h>
57 #include <dev/bce/if_bcefw.h>
59 /****************************************************************************/
60 /* BCE Debug Options */
61 /****************************************************************************/
63 u32 bce_debug = BCE_WARN;
66 /* 1 = 1 in 2,147,483,648 */
67 /* 256 = 1 in 8,388,608 */
68 /* 2048 = 1 in 1,048,576 */
69 /* 65536 = 1 in 32,768 */
70 /* 1048576 = 1 in 2,048 */
71 /* 268435456 = 1 in 8 */
72 /* 536870912 = 1 in 4 */
73 /* 1073741824 = 1 in 2 */
75 /* Controls how often the l2_fhdr frame error check will fail. */
76 int l2fhdr_error_sim_control = 0;
78 /* Controls how often the unexpected attention check will fail. */
79 int unexpected_attention_sim_control = 0;
81 /* Controls how often to simulate an mbuf allocation failure. */
82 int mbuf_alloc_failed_sim_control = 0;
84 /* Controls how often to simulate a DMA mapping failure. */
85 int dma_map_addr_failed_sim_control = 0;
87 /* Controls how often to simulate a bootcode failure. */
88 int bootcode_running_failure_sim_control = 0;
91 /****************************************************************************/
92 /* PCI Device ID Table */
94 /* Used by bce_probe() to identify the devices supported by this driver. */
95 /****************************************************************************/
96 #define BCE_DEVDESC_MAX 64
98 static const struct bce_type bce_devs[] = {
99 /* BCM5706C Controllers and OEM boards. */
100 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101,
101 "HP NC370T Multifunction Gigabit Server Adapter" },
102 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106,
103 "HP NC370i Multifunction Gigabit Server Adapter" },
104 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070,
105 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
106 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709,
107 "HP NC371i Multifunction Gigabit Server Adapter" },
108 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID,
109 "Broadcom NetXtreme II BCM5706 1000Base-T" },
111 /* BCM5706S controllers and OEM boards. */
112 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
113 "HP NC370F Multifunction Gigabit Server Adapter" },
114 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID,
115 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
117 /* BCM5708C controllers and OEM boards. */
118 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037,
119 "HP NC373T PCIe Multifunction Gig Server Adapter" },
120 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038,
121 "HP NC373i Multifunction Gigabit Server Adapter" },
122 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045,
123 "HP NC374m PCIe Multifunction Adapter" },
124 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID,
125 "Broadcom NetXtreme II BCM5708 1000Base-T" },
127 /* BCM5708S controllers and OEM boards. */
128 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706,
129 "HP NC373m Multifunction Gigabit Server Adapter" },
130 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b,
131 "HP NC373i Multifunction Gigabit Server Adapter" },
132 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d,
133 "HP NC373F PCIe Multifunc Giga Server Adapter" },
134 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID,
135 "Broadcom NetXtreme II BCM5708 1000Base-SX" },
137 /* BCM5709C controllers and OEM boards. */
138 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055,
139 "HP NC382i DP Multifunction Gigabit Server Adapter" },
140 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059,
141 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
142 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID,
143 "Broadcom NetXtreme II BCM5709 1000Base-T" },
145 /* BCM5709S controllers and OEM boards. */
146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d,
147 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056,
149 "HP NC382i DP Multifunction Gigabit Server Adapter" },
150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID,
151 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
153 /* BCM5716 controllers and OEM boards. */
154 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID,
155 "Broadcom NetXtreme II BCM5716 1000Base-T" },
161 /****************************************************************************/
162 /* Supported Flash NVRAM device data. */
163 /****************************************************************************/
164 static const struct flash_spec flash_table[] =
166 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
167 #define NONBUFFERED_FLAGS (BCE_NV_WREN)
170 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
171 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
172 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
174 /* Expansion entry 0001 */
175 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
176 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
177 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
179 /* Saifun SA25F010 (non-buffered flash) */
180 /* strap, cfg1, & write1 need updates */
181 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
182 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
183 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
184 "Non-buffered flash (128kB)"},
185 /* Saifun SA25F020 (non-buffered flash) */
186 /* strap, cfg1, & write1 need updates */
187 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
189 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
190 "Non-buffered flash (256kB)"},
191 /* Expansion entry 0100 */
192 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
194 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
196 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
197 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
198 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
199 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
200 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
201 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
202 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
203 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
204 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
205 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
206 /* Saifun SA25F005 (non-buffered flash) */
207 /* strap, cfg1, & write1 need updates */
208 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
209 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
210 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
211 "Non-buffered flash (64kB)"},
213 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
214 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
215 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
217 /* Expansion entry 1001 */
218 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
219 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
220 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
222 /* Expansion entry 1010 */
223 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
224 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
225 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
227 /* ATMEL AT45DB011B (buffered flash) */
228 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
229 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
230 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
231 "Buffered flash (128kB)"},
232 /* Expansion entry 1100 */
233 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
234 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
235 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
237 /* Expansion entry 1101 */
238 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
239 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
240 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
242 /* Ateml Expansion entry 1110 */
243 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
244 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
245 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
246 "Entry 1110 (Atmel)"},
247 /* ATMEL AT45DB021B (buffered flash) */
248 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
249 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
250 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
251 "Buffered flash (256kB)"},
255 * The BCM5709 controllers transparently handle the
256 * differences between Atmel 264 byte pages and all
257 * flash devices which use 256 byte pages, so no
258 * logical-to-physical mapping is required in the
261 static const struct flash_spec flash_5709 = {
262 .flags = BCE_NV_BUFFERED,
263 .page_bits = BCM5709_FLASH_PAGE_BITS,
264 .page_size = BCM5709_FLASH_PAGE_SIZE,
265 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
266 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2,
267 .name = "5709/5716 buffered flash (256kB)",
271 /****************************************************************************/
272 /* FreeBSD device entry points. */
273 /****************************************************************************/
274 static int bce_probe (device_t);
275 static int bce_attach (device_t);
276 static int bce_detach (device_t);
277 static int bce_shutdown (device_t);
280 /****************************************************************************/
281 /* BCE Debug Data Structure Dump Routines */
282 /****************************************************************************/
284 static u32 bce_reg_rd (struct bce_softc *, u32);
285 static void bce_reg_wr (struct bce_softc *, u32, u32);
286 static void bce_reg_wr16 (struct bce_softc *, u32, u16);
287 static u32 bce_ctx_rd (struct bce_softc *, u32, u32);
288 static void bce_dump_enet (struct bce_softc *, struct mbuf *);
289 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *);
290 static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int);
291 static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int);
292 static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int);
293 static void bce_dump_txbd (struct bce_softc *,
294 int, struct tx_bd *);
295 static void bce_dump_rxbd (struct bce_softc *,
296 int, struct rx_bd *);
297 static void bce_dump_pgbd (struct bce_softc *,
298 int, struct rx_bd *);
299 static void bce_dump_l2fhdr (struct bce_softc *,
300 int, struct l2_fhdr *);
301 static void bce_dump_ctx (struct bce_softc *, u16);
302 static void bce_dump_ftqs (struct bce_softc *);
303 static void bce_dump_tx_chain (struct bce_softc *, u16, int);
304 static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int);
305 static void bce_dump_pg_chain (struct bce_softc *, u16, int);
306 static void bce_dump_status_block (struct bce_softc *);
307 static void bce_dump_stats_block (struct bce_softc *);
308 static void bce_dump_driver_state (struct bce_softc *);
309 static void bce_dump_hw_state (struct bce_softc *);
310 static void bce_dump_shmem_state (struct bce_softc *);
311 static void bce_dump_mq_regs (struct bce_softc *);
312 static void bce_dump_bc_state (struct bce_softc *);
313 static void bce_dump_txp_state (struct bce_softc *, int);
314 static void bce_dump_rxp_state (struct bce_softc *, int);
315 static void bce_dump_tpat_state (struct bce_softc *, int);
316 static void bce_dump_cp_state (struct bce_softc *, int);
317 static void bce_dump_com_state (struct bce_softc *, int);
318 static void bce_dump_rv2p_state (struct bce_softc *);
319 static void bce_breakpoint (struct bce_softc *);
320 #endif /*BCE_DEBUG */
323 /****************************************************************************/
324 /* BCE Register/Memory Access Routines */
325 /****************************************************************************/
326 static u32 bce_reg_rd_ind (struct bce_softc *, u32);
327 static void bce_reg_wr_ind (struct bce_softc *, u32, u32);
328 static void bce_shmem_wr (struct bce_softc *, u32, u32);
329 static u32 bce_shmem_rd (struct bce_softc *, u32);
330 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32);
331 static int bce_miibus_read_reg (device_t, int, int);
332 static int bce_miibus_write_reg (device_t, int, int, int);
333 static void bce_miibus_statchg (device_t);
336 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS);
337 #ifdef BCE_NVRAM_WRITE_SUPPORT
338 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS);
342 /****************************************************************************/
343 /* BCE NVRAM Access Routines */
344 /****************************************************************************/
345 static int bce_acquire_nvram_lock (struct bce_softc *);
346 static int bce_release_nvram_lock (struct bce_softc *);
347 static void bce_enable_nvram_access(struct bce_softc *);
348 static void bce_disable_nvram_access(struct bce_softc *);
349 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32);
350 static int bce_init_nvram (struct bce_softc *);
351 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int);
352 static int bce_nvram_test (struct bce_softc *);
353 #ifdef BCE_NVRAM_WRITE_SUPPORT
354 static int bce_enable_nvram_write (struct bce_softc *);
355 static void bce_disable_nvram_write(struct bce_softc *);
356 static int bce_nvram_erase_page (struct bce_softc *, u32);
357 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32);
358 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int);
361 /****************************************************************************/
363 /****************************************************************************/
364 static void bce_get_rx_buffer_sizes(struct bce_softc *, int);
365 static void bce_get_media (struct bce_softc *);
366 static void bce_init_media (struct bce_softc *);
367 static u32 bce_get_rphy_link (struct bce_softc *);
368 static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int);
369 static int bce_dma_alloc (device_t);
370 static void bce_dma_free (struct bce_softc *);
371 static void bce_release_resources (struct bce_softc *);
373 /****************************************************************************/
374 /* BCE Firmware Synchronization and Load */
375 /****************************************************************************/
376 static void bce_fw_cap_init (struct bce_softc *);
377 static int bce_fw_sync (struct bce_softc *, u32);
378 static void bce_load_rv2p_fw (struct bce_softc *, const u32 *, u32,
380 static void bce_load_cpu_fw (struct bce_softc *,
381 struct cpu_reg *, struct fw_info *);
382 static void bce_start_cpu (struct bce_softc *, struct cpu_reg *);
383 static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *);
384 static void bce_start_rxp_cpu (struct bce_softc *);
385 static void bce_init_rxp_cpu (struct bce_softc *);
386 static void bce_init_txp_cpu (struct bce_softc *);
387 static void bce_init_tpat_cpu (struct bce_softc *);
388 static void bce_init_cp_cpu (struct bce_softc *);
389 static void bce_init_com_cpu (struct bce_softc *);
390 static void bce_init_cpus (struct bce_softc *);
392 static void bce_print_adapter_info (struct bce_softc *);
393 static void bce_probe_pci_caps (device_t, struct bce_softc *);
394 static void bce_stop (struct bce_softc *);
395 static int bce_reset (struct bce_softc *, u32);
396 static int bce_chipinit (struct bce_softc *);
397 static int bce_blockinit (struct bce_softc *);
399 static int bce_init_tx_chain (struct bce_softc *);
400 static void bce_free_tx_chain (struct bce_softc *);
402 static int bce_get_rx_buf (struct bce_softc *, u16, u16, u32 *);
403 static int bce_init_rx_chain (struct bce_softc *);
404 static void bce_fill_rx_chain (struct bce_softc *);
405 static void bce_free_rx_chain (struct bce_softc *);
407 static int bce_get_pg_buf (struct bce_softc *, u16, u16);
408 static int bce_init_pg_chain (struct bce_softc *);
409 static void bce_fill_pg_chain (struct bce_softc *);
410 static void bce_free_pg_chain (struct bce_softc *);
412 static struct mbuf *bce_tso_setup (struct bce_softc *,
413 struct mbuf **, u16 *);
414 static int bce_tx_encap (struct bce_softc *, struct mbuf **);
415 static void bce_start_locked (struct ifnet *);
416 static void bce_start (struct ifnet *);
417 static int bce_ioctl (struct ifnet *, u_long, caddr_t);
418 static void bce_watchdog (struct bce_softc *);
419 static int bce_ifmedia_upd (struct ifnet *);
420 static int bce_ifmedia_upd_locked (struct ifnet *);
421 static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *);
422 static void bce_ifmedia_sts_rphy (struct bce_softc *, struct ifmediareq *);
423 static void bce_init_locked (struct bce_softc *);
424 static void bce_init (void *);
425 static void bce_mgmt_init_locked (struct bce_softc *sc);
427 static int bce_init_ctx (struct bce_softc *);
428 static void bce_get_mac_addr (struct bce_softc *);
429 static void bce_set_mac_addr (struct bce_softc *);
430 static void bce_phy_intr (struct bce_softc *);
431 static inline u16 bce_get_hw_rx_cons (struct bce_softc *);
432 static void bce_rx_intr (struct bce_softc *);
433 static void bce_tx_intr (struct bce_softc *);
434 static void bce_disable_intr (struct bce_softc *);
435 static void bce_enable_intr (struct bce_softc *, int);
437 static void bce_intr (void *);
438 static void bce_set_rx_mode (struct bce_softc *);
439 static void bce_stats_update (struct bce_softc *);
440 static void bce_tick (void *);
441 static void bce_pulse (void *);
442 static void bce_add_sysctls (struct bce_softc *);
445 /****************************************************************************/
446 /* FreeBSD device dispatch table. */
447 /****************************************************************************/
448 static device_method_t bce_methods[] = {
449 /* Device interface (device_if.h) */
450 DEVMETHOD(device_probe, bce_probe),
451 DEVMETHOD(device_attach, bce_attach),
452 DEVMETHOD(device_detach, bce_detach),
453 DEVMETHOD(device_shutdown, bce_shutdown),
454 /* Supported by device interface but not used here. */
455 /* DEVMETHOD(device_identify, bce_identify), */
456 /* DEVMETHOD(device_suspend, bce_suspend), */
457 /* DEVMETHOD(device_resume, bce_resume), */
458 /* DEVMETHOD(device_quiesce, bce_quiesce), */
460 /* MII interface (miibus_if.h) */
461 DEVMETHOD(miibus_readreg, bce_miibus_read_reg),
462 DEVMETHOD(miibus_writereg, bce_miibus_write_reg),
463 DEVMETHOD(miibus_statchg, bce_miibus_statchg),
464 /* Supported by MII interface but not used here. */
465 /* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */
466 /* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */
471 static driver_t bce_driver = {
474 sizeof(struct bce_softc)
477 static devclass_t bce_devclass;
479 MODULE_DEPEND(bce, pci, 1, 1, 1);
480 MODULE_DEPEND(bce, ether, 1, 1, 1);
481 MODULE_DEPEND(bce, miibus, 1, 1, 1);
483 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, NULL, NULL);
484 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
487 /****************************************************************************/
488 /* Tunable device values */
489 /****************************************************************************/
490 static SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters");
492 /* Allowable values are TRUE or FALSE */
493 static int bce_verbose = TRUE;
494 TUNABLE_INT("hw.bce.verbose", &bce_verbose);
495 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0,
496 "Verbose output enable/disable");
498 /* Allowable values are TRUE or FALSE */
499 static int bce_tso_enable = TRUE;
500 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable);
501 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0,
502 "TSO Enable/Disable");
504 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
505 /* ToDo: Add MSI-X support. */
506 static int bce_msi_enable = 1;
507 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable);
508 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0,
509 "MSI-X|MSI|INTx selector");
511 /* Allowable values are 1, 2, 4, 8. */
512 static int bce_rx_pages = DEFAULT_RX_PAGES;
513 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages);
514 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0,
515 "Receive buffer descriptor pages (1 page = 255 buffer descriptors)");
517 /* Allowable values are 1, 2, 4, 8. */
518 static int bce_tx_pages = DEFAULT_TX_PAGES;
519 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages);
520 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0,
521 "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)");
523 /* Allowable values are TRUE or FALSE. */
524 static int bce_hdr_split = TRUE;
525 TUNABLE_INT("hw.bce.hdr_split", &bce_hdr_split);
526 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0,
527 "Frame header/payload splitting Enable/Disable");
529 /* Allowable values are TRUE or FALSE. */
530 static int bce_strict_rx_mtu = FALSE;
531 TUNABLE_INT("hw.bce.strict_rx_mtu", &bce_strict_rx_mtu);
532 SYSCTL_UINT(_hw_bce, OID_AUTO, strict_rx_mtu, CTLFLAG_RDTUN,
533 &bce_strict_rx_mtu, 0,
534 "Enable/Disable strict RX frame size checking");
536 /* Allowable values are 0 ... 100 */
538 /* Generate 1 interrupt for every transmit completion. */
539 static int bce_tx_quick_cons_trip_int = 1;
541 /* Generate 1 interrupt for every 20 transmit completions. */
542 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT;
544 TUNABLE_INT("hw.bce.tx_quick_cons_trip_int", &bce_tx_quick_cons_trip_int);
545 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN,
546 &bce_tx_quick_cons_trip_int, 0,
547 "Transmit BD trip point during interrupts");
549 /* Allowable values are 0 ... 100 */
550 /* Generate 1 interrupt for every transmit completion. */
552 static int bce_tx_quick_cons_trip = 1;
554 /* Generate 1 interrupt for every 20 transmit completions. */
555 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
557 TUNABLE_INT("hw.bce.tx_quick_cons_trip", &bce_tx_quick_cons_trip);
558 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN,
559 &bce_tx_quick_cons_trip, 0,
560 "Transmit BD trip point");
562 /* Allowable values are 0 ... 100 */
564 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
565 static int bce_tx_ticks_int = 0;
567 /* Generate an interrupt if 80us have elapsed since the last TX completion. */
568 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT;
570 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
571 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN,
572 &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt");
574 /* Allowable values are 0 ... 100 */
576 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
577 static int bce_tx_ticks = 0;
579 /* Generate an interrupt if 80us have elapsed since the last TX completion. */
580 static int bce_tx_ticks = DEFAULT_TX_TICKS;
582 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
583 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN,
584 &bce_tx_ticks, 0, "Transmit ticks count");
586 /* Allowable values are 1 ... 100 */
588 /* Generate 1 interrupt for every received frame. */
589 static int bce_rx_quick_cons_trip_int = 1;
591 /* Generate 1 interrupt for every 6 received frames. */
592 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT;
594 TUNABLE_INT("hw.bce.rx_quick_cons_trip_int", &bce_rx_quick_cons_trip_int);
595 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN,
596 &bce_rx_quick_cons_trip_int, 0,
597 "Receive BD trip point duirng interrupts");
599 /* Allowable values are 1 ... 100 */
601 /* Generate 1 interrupt for every received frame. */
602 static int bce_rx_quick_cons_trip = 1;
604 /* Generate 1 interrupt for every 6 received frames. */
605 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP;
607 TUNABLE_INT("hw.bce.rx_quick_cons_trip", &bce_rx_quick_cons_trip);
608 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN,
609 &bce_rx_quick_cons_trip, 0,
610 "Receive BD trip point");
612 /* Allowable values are 0 ... 100 */
614 /* Generate an int. if 0us have elapsed since the last received frame. */
615 static int bce_rx_ticks_int = 0;
617 /* Generate an int. if 18us have elapsed since the last received frame. */
618 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT;
620 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
621 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN,
622 &bce_rx_ticks_int, 0, "Receive ticks count during interrupt");
624 /* Allowable values are 0 ... 100 */
626 /* Generate an int. if 0us have elapsed since the last received frame. */
627 static int bce_rx_ticks = 0;
629 /* Generate an int. if 18us have elapsed since the last received frame. */
630 static int bce_rx_ticks = DEFAULT_RX_TICKS;
632 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
633 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN,
634 &bce_rx_ticks, 0, "Receive ticks count");
637 /****************************************************************************/
638 /* Device probe function. */
640 /* Compares the device to the driver's list of supported devices and */
641 /* reports back to the OS whether this is the right driver for the device. */
644 /* BUS_PROBE_DEFAULT on success, positive value on failure. */
645 /****************************************************************************/
647 bce_probe(device_t dev)
649 const struct bce_type *t;
650 struct bce_softc *sc;
652 u16 vid = 0, did = 0, svid = 0, sdid = 0;
656 sc = device_get_softc(dev);
657 sc->bce_unit = device_get_unit(dev);
660 /* Get the data for the device to be probed. */
661 vid = pci_get_vendor(dev);
662 did = pci_get_device(dev);
663 svid = pci_get_subvendor(dev);
664 sdid = pci_get_subdevice(dev);
666 DBPRINT(sc, BCE_EXTREME_LOAD,
667 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
668 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
670 /* Look through the list of known devices for a match. */
671 while(t->bce_name != NULL) {
673 if ((vid == t->bce_vid) && (did == t->bce_did) &&
674 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) &&
675 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) {
677 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
682 /* Print out the device identity. */
683 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
684 t->bce_name, (((pci_read_config(dev,
685 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'),
686 (pci_read_config(dev, PCIR_REVID, 4) & 0xf));
688 device_set_desc_copy(dev, descbuf);
689 free(descbuf, M_TEMP);
690 return(BUS_PROBE_DEFAULT);
699 /****************************************************************************/
700 /* PCI Capabilities Probe Function. */
702 /* Walks the PCI capabiites list for the device to find what features are */
707 /****************************************************************************/
709 bce_print_adapter_info(struct bce_softc *sc)
713 DBENTER(BCE_VERBOSE_LOAD);
715 if (bce_verbose || bootverbose) {
716 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid);
717 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >>
718 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
722 if (sc->bce_flags & BCE_PCIE_FLAG) {
723 printf("Bus (PCIe x%d, ", sc->link_width);
724 switch (sc->link_speed) {
725 case 1: printf("2.5Gbps); "); break;
726 case 2: printf("5Gbps); "); break;
727 default: printf("Unknown link speed); ");
730 printf("Bus (PCI%s, %s, %dMHz); ",
731 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
732 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ?
733 "32-bit" : "64-bit"), sc->bus_speed_mhz);
736 /* Firmware version and device features. */
737 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (",
738 sc->bce_bc_ver, sc->rx_pages, sc->tx_pages,
739 (bce_hdr_split == TRUE ? sc->pg_pages: 0));
741 if (bce_hdr_split == TRUE) {
746 if (sc->bce_flags & BCE_USING_MSI_FLAG) {
747 if (i > 0) printf("|");
751 if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
752 if (i > 0) printf("|");
753 printf("MSI-X"); i++;
756 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
757 if (i > 0) printf("|");
761 if (sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) {
762 if (i > 0) printf("|");
763 printf("Remote PHY(%s)",
764 sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG ?
765 "FIBER" : "TP"); i++;
768 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
769 if (i > 0) printf("|");
770 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver);
775 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n",
776 sc->bce_rx_quick_cons_trip_int,
777 sc->bce_rx_quick_cons_trip,
778 sc->bce_rx_ticks_int,
780 sc->bce_tx_quick_cons_trip_int,
781 sc->bce_tx_quick_cons_trip,
782 sc->bce_tx_ticks_int,
787 DBEXIT(BCE_VERBOSE_LOAD);
791 /****************************************************************************/
792 /* PCI Capabilities Probe Function. */
794 /* Walks the PCI capabiites list for the device to find what features are */
799 /****************************************************************************/
801 bce_probe_pci_caps(device_t dev, struct bce_softc *sc)
805 DBENTER(BCE_VERBOSE_LOAD);
807 /* Check if PCI-X capability is enabled. */
808 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) {
810 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
813 /* Check if PCIe capability is enabled. */
814 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
816 u16 link_status = pci_read_config(dev, reg + 0x12, 2);
817 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = "
818 "0x%08X\n", link_status);
819 sc->link_speed = link_status & 0xf;
820 sc->link_width = (link_status >> 4) & 0x3f;
821 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
822 sc->bce_flags |= BCE_PCIE_FLAG;
826 /* Check if MSI capability is enabled. */
827 if (pci_find_cap(dev, PCIY_MSI, ®) == 0) {
829 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG;
832 /* Check if MSI-X capability is enabled. */
833 if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) {
835 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG;
838 DBEXIT(BCE_VERBOSE_LOAD);
842 /****************************************************************************/
843 /* Load and validate user tunable settings. */
847 /****************************************************************************/
849 bce_set_tunables(struct bce_softc *sc)
851 /* Set sysctl values for RX page count. */
852 switch (bce_rx_pages) {
860 sc->rx_pages = bce_rx_pages;
863 sc->rx_pages = DEFAULT_RX_PAGES;
864 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
865 "hw.bce.rx_pages! Setting default of %d.\n",
866 __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES);
869 /* ToDo: Consider allowing user setting for pg_pages. */
870 sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES);
872 /* Set sysctl values for TX page count. */
873 switch (bce_tx_pages) {
881 sc->tx_pages = bce_tx_pages;
884 sc->tx_pages = DEFAULT_TX_PAGES;
885 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
886 "hw.bce.tx_pages! Setting default of %d.\n",
887 __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES);
891 * Validate the TX trip point (i.e. the number of
892 * TX completions before a status block update is
893 * generated and an interrupt is asserted.
895 if (bce_tx_quick_cons_trip_int <= 100) {
896 sc->bce_tx_quick_cons_trip_int =
897 bce_tx_quick_cons_trip_int;
899 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
900 "hw.bce.tx_quick_cons_trip_int! Setting default of %d.\n",
901 __FILE__, __LINE__, bce_tx_quick_cons_trip_int,
902 DEFAULT_TX_QUICK_CONS_TRIP_INT);
903 sc->bce_tx_quick_cons_trip_int =
904 DEFAULT_TX_QUICK_CONS_TRIP_INT;
907 if (bce_tx_quick_cons_trip <= 100) {
908 sc->bce_tx_quick_cons_trip =
909 bce_tx_quick_cons_trip;
911 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
912 "hw.bce.tx_quick_cons_trip! Setting default of %d.\n",
913 __FILE__, __LINE__, bce_tx_quick_cons_trip,
914 DEFAULT_TX_QUICK_CONS_TRIP);
915 sc->bce_tx_quick_cons_trip =
916 DEFAULT_TX_QUICK_CONS_TRIP;
920 * Validate the TX ticks count (i.e. the maximum amount
921 * of time to wait after the last TX completion has
922 * occurred before a status block update is generated
923 * and an interrupt is asserted.
925 if (bce_tx_ticks_int <= 100) {
926 sc->bce_tx_ticks_int =
929 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
930 "hw.bce.tx_ticks_int! Setting default of %d.\n",
931 __FILE__, __LINE__, bce_tx_ticks_int,
932 DEFAULT_TX_TICKS_INT);
933 sc->bce_tx_ticks_int =
934 DEFAULT_TX_TICKS_INT;
937 if (bce_tx_ticks <= 100) {
941 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
942 "hw.bce.tx_ticks! Setting default of %d.\n",
943 __FILE__, __LINE__, bce_tx_ticks,
950 * Validate the RX trip point (i.e. the number of
951 * RX frames received before a status block update is
952 * generated and an interrupt is asserted.
954 if (bce_rx_quick_cons_trip_int <= 100) {
955 sc->bce_rx_quick_cons_trip_int =
956 bce_rx_quick_cons_trip_int;
958 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
959 "hw.bce.rx_quick_cons_trip_int! Setting default of %d.\n",
960 __FILE__, __LINE__, bce_rx_quick_cons_trip_int,
961 DEFAULT_RX_QUICK_CONS_TRIP_INT);
962 sc->bce_rx_quick_cons_trip_int =
963 DEFAULT_RX_QUICK_CONS_TRIP_INT;
966 if (bce_rx_quick_cons_trip <= 100) {
967 sc->bce_rx_quick_cons_trip =
968 bce_rx_quick_cons_trip;
970 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
971 "hw.bce.rx_quick_cons_trip! Setting default of %d.\n",
972 __FILE__, __LINE__, bce_rx_quick_cons_trip,
973 DEFAULT_RX_QUICK_CONS_TRIP);
974 sc->bce_rx_quick_cons_trip =
975 DEFAULT_RX_QUICK_CONS_TRIP;
979 * Validate the RX ticks count (i.e. the maximum amount
980 * of time to wait after the last RX frame has been
981 * received before a status block update is generated
982 * and an interrupt is asserted.
984 if (bce_rx_ticks_int <= 100) {
985 sc->bce_rx_ticks_int = bce_rx_ticks_int;
987 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
988 "hw.bce.rx_ticks_int! Setting default of %d.\n",
989 __FILE__, __LINE__, bce_rx_ticks_int,
990 DEFAULT_RX_TICKS_INT);
991 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT;
994 if (bce_rx_ticks <= 100) {
995 sc->bce_rx_ticks = bce_rx_ticks;
997 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
998 "hw.bce.rx_ticks! Setting default of %d.\n",
999 __FILE__, __LINE__, bce_rx_ticks,
1001 sc->bce_rx_ticks = DEFAULT_RX_TICKS;
1004 /* Disabling both RX ticks and RX trips will prevent interrupts. */
1005 if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) {
1006 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and "
1007 "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n",
1008 __FILE__, __LINE__);
1009 sc->bce_rx_ticks = DEFAULT_RX_TICKS;
1010 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP;
1013 /* Disabling both TX ticks and TX trips will prevent interrupts. */
1014 if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) {
1015 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and "
1016 "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n",
1017 __FILE__, __LINE__);
1018 sc->bce_tx_ticks = DEFAULT_TX_TICKS;
1019 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
1024 /****************************************************************************/
1025 /* Device attach function. */
1027 /* Allocates device resources, performs secondary chip identification, */
1028 /* resets and initializes the hardware, and initializes driver instance */
1032 /* 0 on success, positive value on failure. */
1033 /****************************************************************************/
1035 bce_attach(device_t dev)
1037 struct bce_softc *sc;
1040 int count, error, rc = 0, rid;
1042 sc = device_get_softc(dev);
1045 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1047 sc->bce_unit = device_get_unit(dev);
1049 /* Set initial device and PHY flags */
1051 sc->bce_phy_flags = 0;
1053 bce_set_tunables(sc);
1055 pci_enable_busmaster(dev);
1057 /* Allocate PCI memory resources. */
1059 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1062 if (sc->bce_res_mem == NULL) {
1063 BCE_PRINTF("%s(%d): PCI memory allocation failed\n",
1064 __FILE__, __LINE__);
1066 goto bce_attach_fail;
1069 /* Get various resource handles. */
1070 sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
1071 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
1072 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem);
1074 bce_probe_pci_caps(dev, sc);
1079 /* Try allocating MSI-X interrupts. */
1080 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) &&
1081 (bce_msi_enable >= 2) &&
1082 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1083 &rid, RF_ACTIVE)) != NULL)) {
1085 msi_needed = count = 1;
1087 if (((error = pci_alloc_msix(dev, &count)) != 0) ||
1088 (count != msi_needed)) {
1089 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d,"
1090 "Received = %d, error = %d\n", __FILE__, __LINE__,
1091 msi_needed, count, error);
1093 pci_release_msi(dev);
1094 bus_release_resource(dev, SYS_RES_MEMORY, rid,
1096 sc->bce_res_irq = NULL;
1098 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n",
1100 sc->bce_flags |= BCE_USING_MSIX_FLAG;
1105 /* Try allocating a MSI interrupt. */
1106 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) &&
1107 (bce_msi_enable >= 1) && (count == 0)) {
1109 if ((error = pci_alloc_msi(dev, &count)) != 0) {
1110 BCE_PRINTF("%s(%d): MSI allocation failed! "
1111 "error = %d\n", __FILE__, __LINE__, error);
1113 pci_release_msi(dev);
1115 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI "
1116 "interrupt.\n", __FUNCTION__);
1117 sc->bce_flags |= BCE_USING_MSI_FLAG;
1118 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
1119 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG;
1124 /* Try allocating a legacy interrupt. */
1126 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n",
1131 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1132 &rid, RF_ACTIVE | (count != 0 ? 0 : RF_SHAREABLE));
1134 /* Report any IRQ allocation errors. */
1135 if (sc->bce_res_irq == NULL) {
1136 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n",
1137 __FILE__, __LINE__);
1139 goto bce_attach_fail;
1142 /* Initialize mutex for the current device instance. */
1143 BCE_LOCK_INIT(sc, device_get_nameunit(dev));
1146 * Configure byte swap and enable indirect register access.
1147 * Rely on CPU to do target byte swapping on big endian systems.
1148 * Access to registers outside of PCI configurtion space are not
1149 * valid until this is done.
1151 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
1152 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
1153 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
1155 /* Save ASIC revsion info. */
1156 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID);
1158 /* Weed out any non-production controller revisions. */
1159 switch(BCE_CHIP_ID(sc)) {
1160 case BCE_CHIP_ID_5706_A0:
1161 case BCE_CHIP_ID_5706_A1:
1162 case BCE_CHIP_ID_5708_A0:
1163 case BCE_CHIP_ID_5708_B0:
1164 case BCE_CHIP_ID_5709_A0:
1165 case BCE_CHIP_ID_5709_B0:
1166 case BCE_CHIP_ID_5709_B1:
1167 case BCE_CHIP_ID_5709_B2:
1168 BCE_PRINTF("%s(%d): Unsupported controller "
1169 "revision (%c%d)!\n", __FILE__, __LINE__,
1170 (((pci_read_config(dev, PCIR_REVID, 4) &
1171 0xf0) >> 4) + 'A'), (pci_read_config(dev,
1172 PCIR_REVID, 4) & 0xf));
1174 goto bce_attach_fail;
1178 * The embedded PCIe to PCI-X bridge (EPB)
1179 * in the 5708 cannot address memory above
1180 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
1182 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
1183 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR;
1185 sc->max_bus_addr = BUS_SPACE_MAXADDR;
1188 * Find the base address for shared memory access.
1189 * Newer versions of bootcode use a signature and offset
1190 * while older versions use a fixed address.
1192 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
1193 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG)
1194 /* Multi-port devices use different offsets in shared memory. */
1195 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 +
1196 (pci_get_function(sc->bce_dev) << 2));
1198 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
1200 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n",
1201 __FUNCTION__, sc->bce_shmem_base);
1203 /* Fetch the bootcode revision. */
1204 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
1205 for (int i = 0, j = 0; i < 3; i++) {
1208 num = (u8) (val >> (24 - (i * 8)));
1209 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
1210 if (num >= k || !skip0 || k == 1) {
1211 sc->bce_bc_ver[j++] = (num / k) + '0';
1217 sc->bce_bc_ver[j++] = '.';
1220 /* Check if any management firwmare is enabled. */
1221 val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
1222 if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
1223 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
1225 /* Allow time for firmware to enter the running state. */
1226 for (int i = 0; i < 30; i++) {
1227 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
1228 if (val & BCE_CONDITION_MFW_RUN_MASK)
1233 /* Check if management firmware is running. */
1234 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
1235 val &= BCE_CONDITION_MFW_RUN_MASK;
1236 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) &&
1237 (val != BCE_CONDITION_MFW_RUN_NONE)) {
1238 u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
1241 /* Read the management firmware version string. */
1242 for (int j = 0; j < 3; j++) {
1243 val = bce_reg_rd_ind(sc, addr + j * 4);
1245 memcpy(&sc->bce_mfw_ver[i], &val, 4);
1249 /* May cause firmware synchronization timeouts. */
1250 BCE_PRINTF("%s(%d): Management firmware enabled "
1251 "but not running!\n", __FILE__, __LINE__);
1252 strcpy(sc->bce_mfw_ver, "NOT RUNNING!");
1254 /* ToDo: Any action the driver should take? */
1258 /* Get PCI bus information (speed and type). */
1259 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
1260 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
1263 sc->bce_flags |= BCE_PCIX_FLAG;
1265 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS);
1267 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
1269 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
1270 sc->bus_speed_mhz = 133;
1273 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
1274 sc->bus_speed_mhz = 100;
1277 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
1278 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
1279 sc->bus_speed_mhz = 66;
1282 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
1283 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
1284 sc->bus_speed_mhz = 50;
1287 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
1288 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
1289 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
1290 sc->bus_speed_mhz = 33;
1294 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
1295 sc->bus_speed_mhz = 66;
1297 sc->bus_speed_mhz = 33;
1300 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
1301 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
1303 /* Find the media type for the adapter. */
1306 /* Reset controller and announce to bootcode that driver is present. */
1307 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
1308 BCE_PRINTF("%s(%d): Controller reset failed!\n",
1309 __FILE__, __LINE__);
1311 goto bce_attach_fail;
1314 /* Initialize the controller. */
1315 if (bce_chipinit(sc)) {
1316 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
1317 __FILE__, __LINE__);
1319 goto bce_attach_fail;
1322 /* Perform NVRAM test. */
1323 if (bce_nvram_test(sc)) {
1324 BCE_PRINTF("%s(%d): NVRAM test failed!\n",
1325 __FILE__, __LINE__);
1327 goto bce_attach_fail;
1330 /* Fetch the permanent Ethernet MAC address. */
1331 bce_get_mac_addr(sc);
1333 /* Update statistics once every second. */
1334 sc->bce_stats_ticks = 1000000 & 0xffff00;
1336 /* Store data needed by PHY driver for backplane applications */
1337 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
1338 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG);
1340 /* Allocate DMA memory resources. */
1341 if (bce_dma_alloc(dev)) {
1342 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n",
1343 __FILE__, __LINE__);
1345 goto bce_attach_fail;
1348 /* Allocate an ifnet structure. */
1349 ifp = sc->bce_ifp = if_alloc(IFT_ETHER);
1351 BCE_PRINTF("%s(%d): Interface allocation failed!\n",
1352 __FILE__, __LINE__);
1354 goto bce_attach_fail;
1357 /* Initialize the ifnet interface. */
1359 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1360 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1361 ifp->if_ioctl = bce_ioctl;
1362 ifp->if_start = bce_start;
1363 ifp->if_init = bce_init;
1364 ifp->if_mtu = ETHERMTU;
1366 if (bce_tso_enable) {
1367 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO;
1368 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 |
1371 ifp->if_hwassist = BCE_IF_HWASSIST;
1372 ifp->if_capabilities = BCE_IF_CAPABILITIES;
1375 #if __FreeBSD_version >= 800505
1377 * Introducing IFCAP_LINKSTATE didn't bump __FreeBSD_version
1378 * so it's approximate value.
1380 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1381 ifp->if_capabilities |= IFCAP_LINKSTATE;
1384 ifp->if_capenable = ifp->if_capabilities;
1387 * Assume standard mbuf sizes for buffer allocation.
1388 * This may change later if the MTU size is set to
1389 * something other than 1500.
1391 bce_get_rx_buffer_sizes(sc,
1392 (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN));
1394 /* Recalculate our buffer allocation sizes. */
1395 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC;
1396 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
1397 IFQ_SET_READY(&ifp->if_snd);
1399 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1400 ifp->if_baudrate = IF_Mbps(2500ULL);
1402 ifp->if_baudrate = IF_Mbps(1000);
1404 /* Handle any special PHY initialization for SerDes PHYs. */
1407 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
1408 ifmedia_init(&sc->bce_ifmedia, IFM_IMASK, bce_ifmedia_upd,
1411 * We can't manually override remote PHY's link and assume
1412 * PHY port configuration(Fiber or TP) is not changed after
1413 * device attach. This may not be correct though.
1415 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) {
1416 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
1417 ifmedia_add(&sc->bce_ifmedia,
1418 IFM_ETHER | IFM_2500_SX, 0, NULL);
1419 ifmedia_add(&sc->bce_ifmedia,
1420 IFM_ETHER | IFM_2500_SX | IFM_FDX, 0, NULL);
1422 ifmedia_add(&sc->bce_ifmedia,
1423 IFM_ETHER | IFM_1000_SX, 0, NULL);
1424 ifmedia_add(&sc->bce_ifmedia,
1425 IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL);
1427 ifmedia_add(&sc->bce_ifmedia,
1428 IFM_ETHER | IFM_10_T, 0, NULL);
1429 ifmedia_add(&sc->bce_ifmedia,
1430 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
1431 ifmedia_add(&sc->bce_ifmedia,
1432 IFM_ETHER | IFM_100_TX, 0, NULL);
1433 ifmedia_add(&sc->bce_ifmedia,
1434 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
1435 ifmedia_add(&sc->bce_ifmedia,
1436 IFM_ETHER | IFM_1000_T, 0, NULL);
1437 ifmedia_add(&sc->bce_ifmedia,
1438 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1440 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
1441 ifmedia_set(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO);
1442 sc->bce_ifmedia.ifm_media = sc->bce_ifmedia.ifm_cur->ifm_media;
1444 /* MII child bus by attaching the PHY. */
1445 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd,
1446 bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr,
1447 MII_OFFSET_ANY, MIIF_DOPAUSE);
1449 BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__,
1451 goto bce_attach_fail;
1455 /* Attach to the Ethernet interface list. */
1456 ether_ifattach(ifp, sc->eaddr);
1458 #if __FreeBSD_version < 500000
1459 callout_init(&sc->bce_tick_callout);
1460 callout_init(&sc->bce_pulse_callout);
1462 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0);
1463 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0);
1466 /* Hookup IRQ last. */
1467 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE,
1468 NULL, bce_intr, sc, &sc->bce_intrhand);
1471 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n",
1472 __FILE__, __LINE__);
1474 goto bce_attach_exit;
1478 * At this point we've acquired all the resources
1479 * we need to run so there's no turning back, we're
1480 * cleared for launch.
1483 /* Print some important debugging info. */
1484 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc));
1486 /* Add the supported sysctls to the kernel. */
1487 bce_add_sysctls(sc);
1492 * The chip reset earlier notified the bootcode that
1493 * a driver is present. We now need to start our pulse
1494 * routine so that the bootcode is reminded that we're
1499 bce_mgmt_init_locked(sc);
1502 /* Finally, print some useful adapter info */
1503 bce_print_adapter_info(sc);
1504 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n",
1507 goto bce_attach_exit;
1510 bce_release_resources(sc);
1514 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1520 /****************************************************************************/
1521 /* Device detach function. */
1523 /* Stops the controller, resets the controller, and releases resources. */
1526 /* 0 on success, positive value on failure. */
1527 /****************************************************************************/
1529 bce_detach(device_t dev)
1531 struct bce_softc *sc = device_get_softc(dev);
1535 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1539 /* Stop and reset the controller. */
1542 /* Stop the pulse so the bootcode can go to driver absent state. */
1543 callout_stop(&sc->bce_pulse_callout);
1546 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1547 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1549 msg = BCE_DRV_MSG_CODE_UNLOAD;
1554 ether_ifdetach(ifp);
1556 /* If we have a child device on the MII bus remove it too. */
1557 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1558 ifmedia_removeall(&sc->bce_ifmedia);
1560 bus_generic_detach(dev);
1561 device_delete_child(dev, sc->bce_miibus);
1564 /* Release all remaining resources. */
1565 bce_release_resources(sc);
1567 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1573 /****************************************************************************/
1574 /* Device shutdown function. */
1576 /* Stops and resets the controller. */
1579 /* 0 on success, positive value on failure. */
1580 /****************************************************************************/
1582 bce_shutdown(device_t dev)
1584 struct bce_softc *sc = device_get_softc(dev);
1587 DBENTER(BCE_VERBOSE);
1591 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1592 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1594 msg = BCE_DRV_MSG_CODE_UNLOAD;
1598 DBEXIT(BCE_VERBOSE);
1605 /****************************************************************************/
1606 /* Register read. */
1609 /* The value of the register. */
1610 /****************************************************************************/
1612 bce_reg_rd(struct bce_softc *sc, u32 offset)
1614 u32 val = REG_RD(sc, offset);
1615 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1616 __FUNCTION__, offset, val);
1621 /****************************************************************************/
1622 /* Register write (16 bit). */
1626 /****************************************************************************/
1628 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val)
1630 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n",
1631 __FUNCTION__, offset, val);
1632 REG_WR16(sc, offset, val);
1636 /****************************************************************************/
1637 /* Register write. */
1641 /****************************************************************************/
1643 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val)
1645 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1646 __FUNCTION__, offset, val);
1647 REG_WR(sc, offset, val);
1651 /****************************************************************************/
1652 /* Indirect register read. */
1654 /* Reads NetXtreme II registers using an index/data register pair in PCI */
1655 /* configuration space. Using this mechanism avoids issues with posted */
1656 /* reads but is much slower than memory-mapped I/O. */
1659 /* The value of the register. */
1660 /****************************************************************************/
1662 bce_reg_rd_ind(struct bce_softc *sc, u32 offset)
1667 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1671 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1672 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1673 __FUNCTION__, offset, val);
1677 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1682 /****************************************************************************/
1683 /* Indirect register write. */
1685 /* Writes NetXtreme II registers using an index/data register pair in PCI */
1686 /* configuration space. Using this mechanism avoids issues with posted */
1687 /* writes but is muchh slower than memory-mapped I/O. */
1691 /****************************************************************************/
1693 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val)
1698 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1699 __FUNCTION__, offset, val);
1701 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1702 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1706 /****************************************************************************/
1707 /* Shared memory write. */
1709 /* Writes NetXtreme II shared memory region. */
1713 /****************************************************************************/
1715 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val)
1717 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to "
1718 "0x%08X\n", __FUNCTION__, val, offset);
1720 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1724 /****************************************************************************/
1725 /* Shared memory read. */
1727 /* Reads NetXtreme II shared memory region. */
1730 /* The 32 bit value read. */
1731 /****************************************************************************/
1733 bce_shmem_rd(struct bce_softc *sc, u32 offset)
1735 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1737 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from "
1738 "0x%08X\n", __FUNCTION__, val, offset);
1745 /****************************************************************************/
1746 /* Context memory read. */
1748 /* The NetXtreme II controller uses context memory to track connection */
1749 /* information for L2 and higher network protocols. */
1752 /* The requested 32 bit value of context memory. */
1753 /****************************************************************************/
1755 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset)
1757 u32 idx, offset, retry_cnt = 5, val;
1759 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 ||
1760 cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID "
1761 "address: 0x%08X.\n", __FUNCTION__, cid_addr));
1763 offset = ctx_offset + cid_addr;
1765 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1767 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ));
1769 for (idx = 0; idx < retry_cnt; idx++) {
1770 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1771 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0)
1776 if (val & BCE_CTX_CTX_CTRL_READ_REQ)
1777 BCE_PRINTF("%s(%d); Unable to read CTX memory: "
1778 "cid_addr = 0x%08X, offset = 0x%08X!\n",
1779 __FILE__, __LINE__, cid_addr, ctx_offset);
1781 val = REG_RD(sc, BCE_CTX_CTX_DATA);
1783 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1784 val = REG_RD(sc, BCE_CTX_DATA);
1787 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1788 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val);
1795 /****************************************************************************/
1796 /* Context memory write. */
1798 /* The NetXtreme II controller uses context memory to track connection */
1799 /* information for L2 and higher network protocols. */
1803 /****************************************************************************/
1805 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val)
1807 u32 idx, offset = ctx_offset + cid_addr;
1808 u32 val, retry_cnt = 5;
1810 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1811 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val);
1813 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK),
1814 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n",
1815 __FUNCTION__, cid_addr));
1817 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1819 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1820 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1822 for (idx = 0; idx < retry_cnt; idx++) {
1823 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1824 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1829 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ)
1830 BCE_PRINTF("%s(%d); Unable to write CTX memory: "
1831 "cid_addr = 0x%08X, offset = 0x%08X!\n",
1832 __FILE__, __LINE__, cid_addr, ctx_offset);
1835 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1836 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1841 /****************************************************************************/
1842 /* PHY register read. */
1844 /* Implements register reads on the MII bus. */
1847 /* The value of the register. */
1848 /****************************************************************************/
1850 bce_miibus_read_reg(device_t dev, int phy, int reg)
1852 struct bce_softc *sc;
1856 sc = device_get_softc(dev);
1859 * The 5709S PHY is an IEEE Clause 45 PHY
1860 * with special mappings to work with IEEE
1861 * Clause 22 register accesses.
1863 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1864 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1868 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1869 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1870 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1872 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1873 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1879 val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1880 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1881 BCE_EMAC_MDIO_COMM_START_BUSY;
1882 REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1884 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1887 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1888 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1891 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1892 val &= BCE_EMAC_MDIO_COMM_DATA;
1898 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1899 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, "
1900 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg);
1903 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1907 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1908 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1909 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1911 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1912 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1917 DB_PRINT_PHY_REG(reg, val);
1918 return (val & 0xffff);
1922 /****************************************************************************/
1923 /* PHY register write. */
1925 /* Implements register writes on the MII bus. */
1928 /* The value of the register. */
1929 /****************************************************************************/
1931 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1933 struct bce_softc *sc;
1937 sc = device_get_softc(dev);
1939 DB_PRINT_PHY_REG(reg, val);
1942 * The 5709S PHY is an IEEE Clause 45 PHY
1943 * with special mappings to work with IEEE
1944 * Clause 22 register accesses.
1946 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1947 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1951 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1952 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1953 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1955 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1956 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1961 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1962 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1963 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1964 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1966 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1969 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1970 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1976 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1977 BCE_PRINTF("%s(%d): PHY write timeout!\n",
1978 __FILE__, __LINE__);
1980 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1981 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1982 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1984 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1985 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1994 /****************************************************************************/
1995 /* MII bus status change. */
1997 /* Called by the MII bus driver when the PHY establishes link to set the */
1998 /* MAC interface registers. */
2002 /****************************************************************************/
2004 bce_miibus_statchg(device_t dev)
2006 struct bce_softc *sc;
2007 struct mii_data *mii;
2008 struct ifmediareq ifmr;
2009 int media_active, media_status, val;
2011 sc = device_get_softc(dev);
2013 DBENTER(BCE_VERBOSE_PHY);
2015 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
2016 bzero(&ifmr, sizeof(ifmr));
2017 bce_ifmedia_sts_rphy(sc, &ifmr);
2018 media_active = ifmr.ifm_active;
2019 media_status = ifmr.ifm_status;
2021 mii = device_get_softc(sc->bce_miibus);
2022 media_active = mii->mii_media_active;
2023 media_status = mii->mii_media_status;
2026 /* Ignore invalid media status. */
2027 if ((media_status & (IFM_ACTIVE | IFM_AVALID)) !=
2028 (IFM_ACTIVE | IFM_AVALID))
2029 goto bce_miibus_statchg_exit;
2031 val = REG_RD(sc, BCE_EMAC_MODE);
2032 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX |
2033 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK |
2036 /* Set MII or GMII interface based on the PHY speed. */
2037 switch (IFM_SUBTYPE(media_active)) {
2039 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2040 DBPRINT(sc, BCE_INFO_PHY,
2041 "Enabling 10Mb interface.\n");
2042 val |= BCE_EMAC_MODE_PORT_MII_10;
2047 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n");
2048 val |= BCE_EMAC_MODE_PORT_MII;
2051 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n");
2052 val |= BCE_EMAC_MODE_25G;
2056 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n");
2057 val |= BCE_EMAC_MODE_PORT_GMII;
2060 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling "
2061 "default GMII interface.\n");
2062 val |= BCE_EMAC_MODE_PORT_GMII;
2065 /* Set half or full duplex based on PHY settings. */
2066 if ((IFM_OPTIONS(media_active) & IFM_FDX) == 0) {
2067 DBPRINT(sc, BCE_INFO_PHY,
2068 "Setting Half-Duplex interface.\n");
2069 val |= BCE_EMAC_MODE_HALF_DUPLEX;
2071 DBPRINT(sc, BCE_INFO_PHY,
2072 "Setting Full-Duplex interface.\n");
2074 REG_WR(sc, BCE_EMAC_MODE, val);
2076 if ((IFM_OPTIONS(media_active) & IFM_ETH_RXPAUSE) != 0) {
2077 DBPRINT(sc, BCE_INFO_PHY,
2078 "%s(): Enabling RX flow control.\n", __FUNCTION__);
2079 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
2080 sc->bce_flags |= BCE_USING_RX_FLOW_CONTROL;
2082 DBPRINT(sc, BCE_INFO_PHY,
2083 "%s(): Disabling RX flow control.\n", __FUNCTION__);
2084 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
2085 sc->bce_flags &= ~BCE_USING_RX_FLOW_CONTROL;
2088 if ((IFM_OPTIONS(media_active) & IFM_ETH_TXPAUSE) != 0) {
2089 DBPRINT(sc, BCE_INFO_PHY,
2090 "%s(): Enabling TX flow control.\n", __FUNCTION__);
2091 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
2092 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL;
2094 DBPRINT(sc, BCE_INFO_PHY,
2095 "%s(): Disabling TX flow control.\n", __FUNCTION__);
2096 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
2097 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL;
2100 /* ToDo: Update watermarks in bce_init_rx_context(). */
2102 bce_miibus_statchg_exit:
2103 DBEXIT(BCE_VERBOSE_PHY);
2107 /****************************************************************************/
2108 /* Acquire NVRAM lock. */
2110 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */
2111 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
2112 /* for use by the driver. */
2115 /* 0 on success, positive value on failure. */
2116 /****************************************************************************/
2118 bce_acquire_nvram_lock(struct bce_softc *sc)
2123 DBENTER(BCE_VERBOSE_NVRAM);
2125 /* Request access to the flash interface. */
2126 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
2127 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2128 val = REG_RD(sc, BCE_NVM_SW_ARB);
2129 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
2135 if (j >= NVRAM_TIMEOUT_COUNT) {
2136 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
2140 DBEXIT(BCE_VERBOSE_NVRAM);
2145 /****************************************************************************/
2146 /* Release NVRAM lock. */
2148 /* When the caller is finished accessing NVRAM the lock must be released. */
2149 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
2150 /* for use by the driver. */
2153 /* 0 on success, positive value on failure. */
2154 /****************************************************************************/
2156 bce_release_nvram_lock(struct bce_softc *sc)
2161 DBENTER(BCE_VERBOSE_NVRAM);
2164 * Relinquish nvram interface.
2166 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
2168 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2169 val = REG_RD(sc, BCE_NVM_SW_ARB);
2170 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
2176 if (j >= NVRAM_TIMEOUT_COUNT) {
2177 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n");
2181 DBEXIT(BCE_VERBOSE_NVRAM);
2186 #ifdef BCE_NVRAM_WRITE_SUPPORT
2187 /****************************************************************************/
2188 /* Enable NVRAM write access. */
2190 /* Before writing to NVRAM the caller must enable NVRAM writes. */
2193 /* 0 on success, positive value on failure. */
2194 /****************************************************************************/
2196 bce_enable_nvram_write(struct bce_softc *sc)
2201 DBENTER(BCE_VERBOSE_NVRAM);
2203 val = REG_RD(sc, BCE_MISC_CFG);
2204 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);
2206 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2209 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2210 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT);
2212 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2215 val = REG_RD(sc, BCE_NVM_COMMAND);
2216 if (val & BCE_NVM_COMMAND_DONE)
2220 if (j >= NVRAM_TIMEOUT_COUNT) {
2221 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n");
2226 DBENTER(BCE_VERBOSE_NVRAM);
2231 /****************************************************************************/
2232 /* Disable NVRAM write access. */
2234 /* When the caller is finished writing to NVRAM write access must be */
2239 /****************************************************************************/
2241 bce_disable_nvram_write(struct bce_softc *sc)
2245 DBENTER(BCE_VERBOSE_NVRAM);
2247 val = REG_RD(sc, BCE_MISC_CFG);
2248 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);
2250 DBEXIT(BCE_VERBOSE_NVRAM);
2256 /****************************************************************************/
2257 /* Enable NVRAM access. */
2259 /* Before accessing NVRAM for read or write operations the caller must */
2260 /* enabled NVRAM access. */
2264 /****************************************************************************/
2266 bce_enable_nvram_access(struct bce_softc *sc)
2270 DBENTER(BCE_VERBOSE_NVRAM);
2272 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
2273 /* Enable both bits, even on read. */
2274 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val |
2275 BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
2277 DBEXIT(BCE_VERBOSE_NVRAM);
2281 /****************************************************************************/
2282 /* Disable NVRAM access. */
2284 /* When the caller is finished accessing NVRAM access must be disabled. */
2288 /****************************************************************************/
2290 bce_disable_nvram_access(struct bce_softc *sc)
2294 DBENTER(BCE_VERBOSE_NVRAM);
2296 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
2298 /* Disable both bits, even after read. */
2299 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val &
2300 ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
2302 DBEXIT(BCE_VERBOSE_NVRAM);
2306 #ifdef BCE_NVRAM_WRITE_SUPPORT
2307 /****************************************************************************/
2308 /* Erase NVRAM page before writing. */
2310 /* Non-buffered flash parts require that a page be erased before it is */
2314 /* 0 on success, positive value on failure. */
2315 /****************************************************************************/
2317 bce_nvram_erase_page(struct bce_softc *sc, u32 offset)
2322 DBENTER(BCE_VERBOSE_NVRAM);
2324 /* Buffered flash doesn't require an erase. */
2325 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED)
2326 goto bce_nvram_erase_page_exit;
2328 /* Build an erase command. */
2329 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR |
2330 BCE_NVM_COMMAND_DOIT;
2333 * Clear the DONE bit separately, set the NVRAM adress to erase,
2334 * and issue the erase command.
2336 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2337 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2338 REG_WR(sc, BCE_NVM_COMMAND, cmd);
2340 /* Wait for completion. */
2341 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2346 val = REG_RD(sc, BCE_NVM_COMMAND);
2347 if (val & BCE_NVM_COMMAND_DONE)
2351 if (j >= NVRAM_TIMEOUT_COUNT) {
2352 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n");
2356 bce_nvram_erase_page_exit:
2357 DBEXIT(BCE_VERBOSE_NVRAM);
2360 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2363 /****************************************************************************/
2364 /* Read a dword (32 bits) from NVRAM. */
2366 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */
2367 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */
2370 /* 0 on success and the 32 bit value read, positive value on failure. */
2371 /****************************************************************************/
2373 bce_nvram_read_dword(struct bce_softc *sc,
2374 u32 offset, u8 *ret_val, u32 cmd_flags)
2379 DBENTER(BCE_EXTREME_NVRAM);
2381 /* Build the command word. */
2382 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
2384 /* Calculate the offset for buffered flash if translation is used. */
2385 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2386 offset = ((offset / sc->bce_flash_info->page_size) <<
2387 sc->bce_flash_info->page_bits) +
2388 (offset % sc->bce_flash_info->page_size);
2392 * Clear the DONE bit separately, set the address to read,
2393 * and issue the read.
2395 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2396 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2397 REG_WR(sc, BCE_NVM_COMMAND, cmd);
2399 /* Wait for completion. */
2400 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
2405 val = REG_RD(sc, BCE_NVM_COMMAND);
2406 if (val & BCE_NVM_COMMAND_DONE) {
2407 val = REG_RD(sc, BCE_NVM_READ);
2409 val = bce_be32toh(val);
2410 memcpy(ret_val, &val, 4);
2415 /* Check for errors. */
2416 if (i >= NVRAM_TIMEOUT_COUNT) {
2417 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at "
2418 "offset 0x%08X!\n", __FILE__, __LINE__, offset);
2422 DBEXIT(BCE_EXTREME_NVRAM);
2427 #ifdef BCE_NVRAM_WRITE_SUPPORT
2428 /****************************************************************************/
2429 /* Write a dword (32 bits) to NVRAM. */
2431 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */
2432 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */
2433 /* enabled NVRAM write access. */
2436 /* 0 on success, positive value on failure. */
2437 /****************************************************************************/
2439 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val,
2445 DBENTER(BCE_VERBOSE_NVRAM);
2447 /* Build the command word. */
2448 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags;
2450 /* Calculate the offset for buffered flash if translation is used. */
2451 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2452 offset = ((offset / sc->bce_flash_info->page_size) <<
2453 sc->bce_flash_info->page_bits) +
2454 (offset % sc->bce_flash_info->page_size);
2458 * Clear the DONE bit separately, convert NVRAM data to big-endian,
2459 * set the NVRAM address to write, and issue the write command
2461 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2462 memcpy(&val32, val, 4);
2463 val32 = htobe32(val32);
2464 REG_WR(sc, BCE_NVM_WRITE, val32);
2465 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2466 REG_WR(sc, BCE_NVM_COMMAND, cmd);
2468 /* Wait for completion. */
2469 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2472 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE)
2475 if (j >= NVRAM_TIMEOUT_COUNT) {
2476 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at "
2477 "offset 0x%08X\n", __FILE__, __LINE__, offset);
2481 DBEXIT(BCE_VERBOSE_NVRAM);
2484 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2487 /****************************************************************************/
2488 /* Initialize NVRAM access. */
2490 /* Identify the NVRAM device in use and prepare the NVRAM interface to */
2491 /* access that device. */
2494 /* 0 on success, positive value on failure. */
2495 /****************************************************************************/
2497 bce_init_nvram(struct bce_softc *sc)
2500 int j, entry_count, rc = 0;
2501 const struct flash_spec *flash;
2503 DBENTER(BCE_VERBOSE_NVRAM);
2505 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
2506 sc->bce_flash_info = &flash_5709;
2507 goto bce_init_nvram_get_flash_size;
2510 /* Determine the selected interface. */
2511 val = REG_RD(sc, BCE_NVM_CFG1);
2513 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2516 * Flash reconfiguration is required to support additional
2517 * NVRAM devices not directly supported in hardware.
2518 * Check if the flash interface was reconfigured
2522 if (val & 0x40000000) {
2523 /* Flash interface reconfigured by bootcode. */
2525 DBPRINT(sc,BCE_INFO_LOAD,
2526 "bce_init_nvram(): Flash WAS reconfigured.\n");
2528 for (j = 0, flash = &flash_table[0]; j < entry_count;
2530 if ((val & FLASH_BACKUP_STRAP_MASK) ==
2531 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2532 sc->bce_flash_info = flash;
2537 /* Flash interface not yet reconfigured. */
2540 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n",
2543 if (val & (1 << 23))
2544 mask = FLASH_BACKUP_STRAP_MASK;
2546 mask = FLASH_STRAP_MASK;
2548 /* Look for the matching NVRAM device configuration data. */
2549 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) {
2551 /* Check if the device matches any of the known devices. */
2552 if ((val & mask) == (flash->strapping & mask)) {
2553 /* Found a device match. */
2554 sc->bce_flash_info = flash;
2556 /* Request access to the flash interface. */
2557 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2560 /* Reconfigure the flash interface. */
2561 bce_enable_nvram_access(sc);
2562 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
2563 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
2564 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
2565 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
2566 bce_disable_nvram_access(sc);
2567 bce_release_nvram_lock(sc);
2574 /* Check if a matching device was found. */
2575 if (j == entry_count) {
2576 sc->bce_flash_info = NULL;
2577 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n",
2578 __FILE__, __LINE__);
2579 DBEXIT(BCE_VERBOSE_NVRAM);
2583 bce_init_nvram_get_flash_size:
2584 /* Write the flash config data to the shared memory interface. */
2585 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2);
2586 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
2588 sc->bce_flash_size = val;
2590 sc->bce_flash_size = sc->bce_flash_info->total_size;
2592 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n",
2593 __FUNCTION__, sc->bce_flash_info->name,
2594 sc->bce_flash_info->total_size);
2596 DBEXIT(BCE_VERBOSE_NVRAM);
2601 /****************************************************************************/
2602 /* Read an arbitrary range of data from NVRAM. */
2604 /* Prepares the NVRAM interface for access and reads the requested data */
2605 /* into the supplied buffer. */
2608 /* 0 on success and the data read, positive value on failure. */
2609 /****************************************************************************/
2611 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf,
2615 u32 cmd_flags, offset32, len32, extra;
2617 DBENTER(BCE_VERBOSE_NVRAM);
2620 goto bce_nvram_read_exit;
2622 /* Request access to the flash interface. */
2623 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2624 goto bce_nvram_read_exit;
2626 /* Enable access to flash interface */
2627 bce_enable_nvram_access(sc);
2640 pre_len = 4 - (offset & 3);
2642 if (pre_len >= len32) {
2644 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
2647 cmd_flags = BCE_NVM_COMMAND_FIRST;
2650 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2655 memcpy(ret_buf, buf + (offset & 3), pre_len);
2663 extra = 4 - (len32 & 3);
2664 len32 = (len32 + 4) & ~3;
2671 cmd_flags = BCE_NVM_COMMAND_LAST;
2673 cmd_flags = BCE_NVM_COMMAND_FIRST |
2674 BCE_NVM_COMMAND_LAST;
2676 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2678 memcpy(ret_buf, buf, 4 - extra);
2680 else if (len32 > 0) {
2683 /* Read the first word. */
2687 cmd_flags = BCE_NVM_COMMAND_FIRST;
2689 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
2691 /* Advance to the next dword. */
2696 while (len32 > 4 && rc == 0) {
2697 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
2699 /* Advance to the next dword. */
2706 goto bce_nvram_read_locked_exit;
2708 cmd_flags = BCE_NVM_COMMAND_LAST;
2709 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2711 memcpy(ret_buf, buf, 4 - extra);
2714 bce_nvram_read_locked_exit:
2715 /* Disable access to flash interface and release the lock. */
2716 bce_disable_nvram_access(sc);
2717 bce_release_nvram_lock(sc);
2719 bce_nvram_read_exit:
2720 DBEXIT(BCE_VERBOSE_NVRAM);
2725 #ifdef BCE_NVRAM_WRITE_SUPPORT
2726 /****************************************************************************/
2727 /* Write an arbitrary range of data from NVRAM. */
2729 /* Prepares the NVRAM interface for write access and writes the requested */
2730 /* data from the supplied buffer. The caller is responsible for */
2731 /* calculating any appropriate CRCs. */
2734 /* 0 on success, positive value on failure. */
2735 /****************************************************************************/
2737 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf,
2740 u32 written, offset32, len32;
2741 u8 *buf, start[4], end[4];
2743 int align_start, align_end;
2745 DBENTER(BCE_VERBOSE_NVRAM);
2750 align_start = align_end = 0;
2752 if ((align_start = (offset32 & 3))) {
2754 len32 += align_start;
2755 if ((rc = bce_nvram_read(sc, offset32, start, 4)))
2756 goto bce_nvram_write_exit;
2760 if ((len32 > 4) || !align_start) {
2761 align_end = 4 - (len32 & 3);
2763 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4,
2765 goto bce_nvram_write_exit;
2770 if (align_start || align_end) {
2771 buf = malloc(len32, M_DEVBUF, M_NOWAIT);
2774 goto bce_nvram_write_exit;
2778 memcpy(buf, start, 4);
2782 memcpy(buf + len32 - 4, end, 4);
2784 memcpy(buf + align_start, data_buf, buf_size);
2788 while ((written < len32) && (rc == 0)) {
2789 u32 page_start, page_end, data_start, data_end;
2790 u32 addr, cmd_flags;
2792 u8 flash_buffer[264];
2794 /* Find the page_start addr */
2795 page_start = offset32 + written;
2796 page_start -= (page_start % sc->bce_flash_info->page_size);
2797 /* Find the page_end addr */
2798 page_end = page_start + sc->bce_flash_info->page_size;
2799 /* Find the data_start addr */
2800 data_start = (written == 0) ? offset32 : page_start;
2801 /* Find the data_end addr */
2802 data_end = (page_end > offset32 + len32) ?
2803 (offset32 + len32) : page_end;
2805 /* Request access to the flash interface. */
2806 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2807 goto bce_nvram_write_exit;
2809 /* Enable access to flash interface */
2810 bce_enable_nvram_access(sc);
2812 cmd_flags = BCE_NVM_COMMAND_FIRST;
2813 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2816 /* Read the whole page into the buffer
2817 * (non-buffer flash only) */
2818 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) {
2819 if (j == (sc->bce_flash_info->page_size - 4)) {
2820 cmd_flags |= BCE_NVM_COMMAND_LAST;
2822 rc = bce_nvram_read_dword(sc,
2828 goto bce_nvram_write_locked_exit;
2834 /* Enable writes to flash interface (unlock write-protect) */
2835 if ((rc = bce_enable_nvram_write(sc)) != 0)
2836 goto bce_nvram_write_locked_exit;
2838 /* Erase the page */
2839 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0)
2840 goto bce_nvram_write_locked_exit;
2842 /* Re-enable the write again for the actual write */
2843 bce_enable_nvram_write(sc);
2845 /* Loop to write back the buffer data from page_start to
2848 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2849 for (addr = page_start; addr < data_start;
2850 addr += 4, i += 4) {
2852 rc = bce_nvram_write_dword(sc, addr,
2853 &flash_buffer[i], cmd_flags);
2856 goto bce_nvram_write_locked_exit;
2862 /* Loop to write the new data from data_start to data_end */
2863 for (addr = data_start; addr < data_end; addr += 4, i++) {
2864 if ((addr == page_end - 4) ||
2865 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) &&
2866 (addr == data_end - 4))) {
2868 cmd_flags |= BCE_NVM_COMMAND_LAST;
2870 rc = bce_nvram_write_dword(sc, addr, buf,
2874 goto bce_nvram_write_locked_exit;
2880 /* Loop to write back the buffer data from data_end
2882 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2883 for (addr = data_end; addr < page_end;
2884 addr += 4, i += 4) {
2886 if (addr == page_end-4) {
2887 cmd_flags = BCE_NVM_COMMAND_LAST;
2889 rc = bce_nvram_write_dword(sc, addr,
2890 &flash_buffer[i], cmd_flags);
2893 goto bce_nvram_write_locked_exit;
2899 /* Disable writes to flash interface (lock write-protect) */
2900 bce_disable_nvram_write(sc);
2902 /* Disable access to flash interface */
2903 bce_disable_nvram_access(sc);
2904 bce_release_nvram_lock(sc);
2906 /* Increment written */
2907 written += data_end - data_start;
2910 goto bce_nvram_write_exit;
2912 bce_nvram_write_locked_exit:
2913 bce_disable_nvram_write(sc);
2914 bce_disable_nvram_access(sc);
2915 bce_release_nvram_lock(sc);
2917 bce_nvram_write_exit:
2918 if (align_start || align_end)
2919 free(buf, M_DEVBUF);
2921 DBEXIT(BCE_VERBOSE_NVRAM);
2924 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2927 /****************************************************************************/
2928 /* Verifies that NVRAM is accessible and contains valid data. */
2930 /* Reads the configuration data from NVRAM and verifies that the CRC is */
2934 /* 0 on success, positive value on failure. */
2935 /****************************************************************************/
2937 bce_nvram_test(struct bce_softc *sc)
2939 u32 buf[BCE_NVRAM_SIZE / 4];
2940 u8 *data = (u8 *) buf;
2944 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
2947 * Check that the device NVRAM is valid by reading
2948 * the magic value at offset 0.
2950 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) {
2951 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n",
2952 __FILE__, __LINE__);
2953 goto bce_nvram_test_exit;
2957 * Verify that offset 0 of the NVRAM contains
2958 * a valid magic number.
2960 magic = bce_be32toh(buf[0]);
2961 if (magic != BCE_NVRAM_MAGIC) {
2963 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! "
2964 "Expected: 0x%08X, Found: 0x%08X\n",
2965 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic);
2966 goto bce_nvram_test_exit;
2970 * Verify that the device NVRAM includes valid
2971 * configuration data.
2973 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) {
2974 BCE_PRINTF("%s(%d): Unable to read manufacturing "
2975 "Information from NVRAM!\n", __FILE__, __LINE__);
2976 goto bce_nvram_test_exit;
2979 csum = ether_crc32_le(data, 0x100);
2980 if (csum != BCE_CRC32_RESIDUAL) {
2982 BCE_PRINTF("%s(%d): Invalid manufacturing information "
2983 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n",
2984 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum);
2985 goto bce_nvram_test_exit;
2988 csum = ether_crc32_le(data + 0x100, 0x100);
2989 if (csum != BCE_CRC32_RESIDUAL) {
2991 BCE_PRINTF("%s(%d): Invalid feature configuration "
2992 "information NVRAM CRC! Expected: 0x%08X, "
2993 "Found: 08%08X\n", __FILE__, __LINE__,
2994 BCE_CRC32_RESIDUAL, csum);
2997 bce_nvram_test_exit:
2998 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
3003 /****************************************************************************/
3004 /* Calculates the size of the buffers to allocate based on the MTU. */
3008 /****************************************************************************/
3010 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu)
3012 DBENTER(BCE_VERBOSE_LOAD);
3014 /* Use a single allocation type when header splitting enabled. */
3015 if (bce_hdr_split == TRUE) {
3016 sc->rx_bd_mbuf_alloc_size = MHLEN;
3017 /* Make sure offset is 16 byte aligned for hardware. */
3018 sc->rx_bd_mbuf_align_pad =
3019 roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN);
3020 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
3021 sc->rx_bd_mbuf_align_pad;
3023 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
3024 ETHER_CRC_LEN) > MCLBYTES) {
3025 /* Setup for jumbo RX buffer allocations. */
3026 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES;
3027 sc->rx_bd_mbuf_align_pad =
3028 roundup2(MJUM9BYTES, 16) - MJUM9BYTES;
3029 sc->rx_bd_mbuf_data_len =
3030 sc->rx_bd_mbuf_alloc_size -
3031 sc->rx_bd_mbuf_align_pad;
3033 /* Setup for standard RX buffer allocations. */
3034 sc->rx_bd_mbuf_alloc_size = MCLBYTES;
3035 sc->rx_bd_mbuf_align_pad =
3036 roundup2(MCLBYTES, 16) - MCLBYTES;
3037 sc->rx_bd_mbuf_data_len =
3038 sc->rx_bd_mbuf_alloc_size -
3039 sc->rx_bd_mbuf_align_pad;
3043 // DBPRINT(sc, BCE_INFO_LOAD,
3044 DBPRINT(sc, BCE_WARN,
3045 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, "
3046 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__,
3047 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len,
3048 sc->rx_bd_mbuf_align_pad);
3050 DBEXIT(BCE_VERBOSE_LOAD);
3053 /****************************************************************************/
3054 /* Identifies the current media type of the controller and sets the PHY */
3059 /****************************************************************************/
3061 bce_get_media(struct bce_softc *sc)
3065 DBENTER(BCE_VERBOSE_PHY);
3067 /* Assume PHY address for copper controllers. */
3068 sc->bce_phy_addr = 1;
3070 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3071 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
3072 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
3076 * The BCM5709S is software configurable
3077 * for Copper or SerDes operation.
3079 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
3080 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
3082 goto bce_get_media_exit;
3083 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
3084 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
3085 "for dual media.\n");
3086 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3087 goto bce_get_media_exit;
3090 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
3092 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
3095 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
3097 if (pci_get_function(sc->bce_dev) == 0) {
3102 DBPRINT(sc, BCE_INFO_LOAD,
3103 "BCM5709 s/w configured for SerDes.\n");
3104 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3107 DBPRINT(sc, BCE_INFO_LOAD,
3108 "BCM5709 s/w configured for Copper.\n");
3116 DBPRINT(sc, BCE_INFO_LOAD,
3117 "BCM5709 s/w configured for SerDes.\n");
3118 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3121 DBPRINT(sc, BCE_INFO_LOAD,
3122 "BCM5709 s/w configured for Copper.\n");
3127 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT)
3128 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3130 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
3132 sc->bce_flags |= BCE_NO_WOL_FLAG;
3134 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
3135 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG;
3137 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
3138 /* 5708S/09S/16S use a separate PHY for SerDes. */
3139 sc->bce_phy_addr = 2;
3141 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
3142 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) {
3143 sc->bce_phy_flags |=
3144 BCE_PHY_2_5G_CAPABLE_FLAG;
3145 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb "
3146 "capable adapter\n");
3149 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
3150 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708))
3151 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
3154 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY),
3155 "Using PHY address %d.\n", sc->bce_phy_addr);
3157 DBEXIT(BCE_VERBOSE_PHY);
3161 /****************************************************************************/
3162 /* Performs PHY initialization required before MII drivers access the */
3167 /****************************************************************************/
3169 bce_init_media(struct bce_softc *sc)
3171 if ((sc->bce_phy_flags & (BCE_PHY_IEEE_CLAUSE_45_FLAG |
3172 BCE_PHY_REMOTE_CAP_FLAG)) == BCE_PHY_IEEE_CLAUSE_45_FLAG) {
3174 * Configure 5709S/5716S PHYs to use traditional IEEE
3175 * Clause 22 method. Otherwise we have no way to attach
3176 * the PHY in mii(4) layer. PHY specific configuration
3177 * is done in mii layer.
3180 /* Select auto-negotiation MMD of the PHY. */
3181 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3182 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT);
3183 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3184 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD);
3186 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */
3187 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3188 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
3193 /****************************************************************************/
3194 /* Free any DMA memory owned by the driver. */
3196 /* Scans through each data structre that requires DMA memory and frees */
3197 /* the memory if allocated. */
3201 /****************************************************************************/
3203 bce_dma_free(struct bce_softc *sc)
3207 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
3209 /* Free, unmap, and destroy the status block. */
3210 if (sc->status_block != NULL) {
3215 sc->status_block = NULL;
3218 if (sc->status_map != NULL) {
3222 bus_dmamap_destroy(sc->status_tag,
3224 sc->status_map = NULL;
3227 if (sc->status_tag != NULL) {
3228 bus_dma_tag_destroy(sc->status_tag);
3229 sc->status_tag = NULL;
3233 /* Free, unmap, and destroy the statistics block. */
3234 if (sc->stats_block != NULL) {
3239 sc->stats_block = NULL;
3242 if (sc->stats_map != NULL) {
3246 bus_dmamap_destroy(sc->stats_tag,
3248 sc->stats_map = NULL;
3251 if (sc->stats_tag != NULL) {
3252 bus_dma_tag_destroy(sc->stats_tag);
3253 sc->stats_tag = NULL;
3257 /* Free, unmap and destroy all context memory pages. */
3258 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3259 for (i = 0; i < sc->ctx_pages; i++ ) {
3260 if (sc->ctx_block[i] != NULL) {
3265 sc->ctx_block[i] = NULL;
3268 if (sc->ctx_map[i] != NULL) {
3275 sc->ctx_map[i] = NULL;
3279 /* Destroy the context memory tag. */
3280 if (sc->ctx_tag != NULL) {
3281 bus_dma_tag_destroy(sc->ctx_tag);
3287 /* Free, unmap and destroy all TX buffer descriptor chain pages. */
3288 for (i = 0; i < sc->tx_pages; i++ ) {
3289 if (sc->tx_bd_chain[i] != NULL) {
3291 sc->tx_bd_chain_tag,
3293 sc->tx_bd_chain_map[i]);
3294 sc->tx_bd_chain[i] = NULL;
3297 if (sc->tx_bd_chain_map[i] != NULL) {
3299 sc->tx_bd_chain_tag,
3300 sc->tx_bd_chain_map[i]);
3302 sc->tx_bd_chain_tag,
3303 sc->tx_bd_chain_map[i]);
3304 sc->tx_bd_chain_map[i] = NULL;
3308 /* Destroy the TX buffer descriptor tag. */
3309 if (sc->tx_bd_chain_tag != NULL) {
3310 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
3311 sc->tx_bd_chain_tag = NULL;
3315 /* Free, unmap and destroy all RX buffer descriptor chain pages. */
3316 for (i = 0; i < sc->rx_pages; i++ ) {
3317 if (sc->rx_bd_chain[i] != NULL) {
3319 sc->rx_bd_chain_tag,
3321 sc->rx_bd_chain_map[i]);
3322 sc->rx_bd_chain[i] = NULL;
3325 if (sc->rx_bd_chain_map[i] != NULL) {
3327 sc->rx_bd_chain_tag,
3328 sc->rx_bd_chain_map[i]);
3330 sc->rx_bd_chain_tag,
3331 sc->rx_bd_chain_map[i]);
3332 sc->rx_bd_chain_map[i] = NULL;
3336 /* Destroy the RX buffer descriptor tag. */
3337 if (sc->rx_bd_chain_tag != NULL) {
3338 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
3339 sc->rx_bd_chain_tag = NULL;
3343 /* Free, unmap and destroy all page buffer descriptor chain pages. */
3344 if (bce_hdr_split == TRUE) {
3345 for (i = 0; i < sc->pg_pages; i++ ) {
3346 if (sc->pg_bd_chain[i] != NULL) {
3348 sc->pg_bd_chain_tag,
3350 sc->pg_bd_chain_map[i]);
3351 sc->pg_bd_chain[i] = NULL;
3354 if (sc->pg_bd_chain_map[i] != NULL) {
3356 sc->pg_bd_chain_tag,
3357 sc->pg_bd_chain_map[i]);
3359 sc->pg_bd_chain_tag,
3360 sc->pg_bd_chain_map[i]);
3361 sc->pg_bd_chain_map[i] = NULL;
3365 /* Destroy the page buffer descriptor tag. */
3366 if (sc->pg_bd_chain_tag != NULL) {
3367 bus_dma_tag_destroy(sc->pg_bd_chain_tag);
3368 sc->pg_bd_chain_tag = NULL;
3373 /* Unload and destroy the TX mbuf maps. */
3374 for (i = 0; i < MAX_TX_BD_AVAIL; i++) {
3375 if (sc->tx_mbuf_map[i] != NULL) {
3376 bus_dmamap_unload(sc->tx_mbuf_tag,
3377 sc->tx_mbuf_map[i]);
3378 bus_dmamap_destroy(sc->tx_mbuf_tag,
3379 sc->tx_mbuf_map[i]);
3380 sc->tx_mbuf_map[i] = NULL;
3384 /* Destroy the TX mbuf tag. */
3385 if (sc->tx_mbuf_tag != NULL) {
3386 bus_dma_tag_destroy(sc->tx_mbuf_tag);
3387 sc->tx_mbuf_tag = NULL;
3390 /* Unload and destroy the RX mbuf maps. */
3391 for (i = 0; i < MAX_RX_BD_AVAIL; i++) {
3392 if (sc->rx_mbuf_map[i] != NULL) {
3393 bus_dmamap_unload(sc->rx_mbuf_tag,
3394 sc->rx_mbuf_map[i]);
3395 bus_dmamap_destroy(sc->rx_mbuf_tag,
3396 sc->rx_mbuf_map[i]);
3397 sc->rx_mbuf_map[i] = NULL;
3401 /* Destroy the RX mbuf tag. */
3402 if (sc->rx_mbuf_tag != NULL) {
3403 bus_dma_tag_destroy(sc->rx_mbuf_tag);
3404 sc->rx_mbuf_tag = NULL;
3407 /* Unload and destroy the page mbuf maps. */
3408 if (bce_hdr_split == TRUE) {
3409 for (i = 0; i < MAX_PG_BD_AVAIL; i++) {
3410 if (sc->pg_mbuf_map[i] != NULL) {
3411 bus_dmamap_unload(sc->pg_mbuf_tag,
3412 sc->pg_mbuf_map[i]);
3413 bus_dmamap_destroy(sc->pg_mbuf_tag,
3414 sc->pg_mbuf_map[i]);
3415 sc->pg_mbuf_map[i] = NULL;
3419 /* Destroy the page mbuf tag. */
3420 if (sc->pg_mbuf_tag != NULL) {
3421 bus_dma_tag_destroy(sc->pg_mbuf_tag);
3422 sc->pg_mbuf_tag = NULL;
3426 /* Destroy the parent tag */
3427 if (sc->parent_tag != NULL) {
3428 bus_dma_tag_destroy(sc->parent_tag);
3429 sc->parent_tag = NULL;
3432 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
3436 /****************************************************************************/
3437 /* Get DMA memory from the OS. */
3439 /* Validates that the OS has provided DMA buffers in response to a */
3440 /* bus_dmamap_load() call and saves the physical address of those buffers. */
3441 /* When the callback is used the OS will return 0 for the mapping function */
3442 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */
3443 /* failures back to the caller. */
3447 /****************************************************************************/
3449 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3451 bus_addr_t *busaddr = arg;
3453 KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!",
3454 __FUNCTION__, nseg));
3455 /* Simulate a mapping failure. */
3456 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control),
3459 /* ToDo: How to increment debug sim_count variable here? */
3461 /* Check for an error and signal the caller that an error occurred. */
3465 *busaddr = segs->ds_addr;
3470 /****************************************************************************/
3471 /* Allocate any DMA memory needed by the driver. */
3473 /* Allocates DMA memory needed for the various global structures needed by */
3476 /* Memory alignment requirements: */
3477 /* +-----------------+----------+----------+----------+----------+ */
3478 /* | | 5706 | 5708 | 5709 | 5716 | */
3479 /* +-----------------+----------+----------+----------+----------+ */
3480 /* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
3481 /* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
3482 /* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */
3483 /* |PG Buffers | none | none | none | none | */
3484 /* |TX Buffers | none | none | none | none | */
3485 /* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */
3486 /* |Context Memory | | | | | */
3487 /* +-----------------+----------+----------+----------+----------+ */
3489 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */
3492 /* 0 for success, positive value for failure. */
3493 /****************************************************************************/
3495 bce_dma_alloc(device_t dev)
3497 struct bce_softc *sc;
3498 int i, error, rc = 0;
3499 bus_size_t max_size, max_seg_size;
3502 sc = device_get_softc(dev);
3504 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3507 * Allocate the parent bus DMA tag appropriate for PCI.
3509 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY,
3510 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3511 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
3513 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n",
3514 __FILE__, __LINE__);
3516 goto bce_dma_alloc_exit;
3520 * Create a DMA tag for the status block, allocate and clear the
3521 * memory, map the memory into DMA space, and fetch the physical
3522 * address of the block.
3524 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3525 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3526 NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ,
3527 0, NULL, NULL, &sc->status_tag)) {
3528 BCE_PRINTF("%s(%d): Could not allocate status block "
3529 "DMA tag!\n", __FILE__, __LINE__);
3531 goto bce_dma_alloc_exit;
3534 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block,
3535 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3537 BCE_PRINTF("%s(%d): Could not allocate status block "
3538 "DMA memory!\n", __FILE__, __LINE__);
3540 goto bce_dma_alloc_exit;
3543 error = bus_dmamap_load(sc->status_tag, sc->status_map,
3544 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr,
3545 &sc->status_block_paddr, BUS_DMA_NOWAIT);
3547 if (error || sc->status_block_paddr == 0) {
3548 BCE_PRINTF("%s(%d): Could not map status block "
3549 "DMA memory!\n", __FILE__, __LINE__);
3551 goto bce_dma_alloc_exit;
3554 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n",
3555 __FUNCTION__, (uintmax_t) sc->status_block_paddr);
3558 * Create a DMA tag for the statistics block, allocate and clear the
3559 * memory, map the memory into DMA space, and fetch the physical
3560 * address of the block.
3562 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3563 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3564 NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ,
3565 0, NULL, NULL, &sc->stats_tag)) {
3566 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3567 "DMA tag!\n", __FILE__, __LINE__);
3569 goto bce_dma_alloc_exit;
3572 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block,
3573 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) {
3574 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3575 "DMA memory!\n", __FILE__, __LINE__);
3577 goto bce_dma_alloc_exit;
3580 error = bus_dmamap_load(sc->stats_tag, sc->stats_map,
3581 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr,
3582 &sc->stats_block_paddr, BUS_DMA_NOWAIT);
3584 if (error || sc->stats_block_paddr == 0) {
3585 BCE_PRINTF("%s(%d): Could not map statistics block "
3586 "DMA memory!\n", __FILE__, __LINE__);
3588 goto bce_dma_alloc_exit;
3591 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n",
3592 __FUNCTION__, (uintmax_t) sc->stats_block_paddr);
3594 /* BCM5709 uses host memory as cache for context memory. */
3595 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3596 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
3597 if (sc->ctx_pages == 0)
3600 DBRUNIF((sc->ctx_pages > 512),
3601 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n",
3602 __FILE__, __LINE__, sc->ctx_pages));
3605 * Create a DMA tag for the context pages,
3606 * allocate and clear the memory, map the
3607 * memory into DMA space, and fetch the
3608 * physical address of the block.
3610 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3611 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3612 NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
3613 0, NULL, NULL, &sc->ctx_tag)) {
3614 BCE_PRINTF("%s(%d): Could not allocate CTX "
3615 "DMA tag!\n", __FILE__, __LINE__);
3617 goto bce_dma_alloc_exit;
3620 for (i = 0; i < sc->ctx_pages; i++) {
3622 if(bus_dmamem_alloc(sc->ctx_tag,
3623 (void **)&sc->ctx_block[i],
3624 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3626 BCE_PRINTF("%s(%d): Could not allocate CTX "
3627 "DMA memory!\n", __FILE__, __LINE__);
3629 goto bce_dma_alloc_exit;
3632 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
3633 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr,
3634 &sc->ctx_paddr[i], BUS_DMA_NOWAIT);
3636 if (error || sc->ctx_paddr[i] == 0) {
3637 BCE_PRINTF("%s(%d): Could not map CTX "
3638 "DMA memory!\n", __FILE__, __LINE__);
3640 goto bce_dma_alloc_exit;
3643 DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] "
3644 "= 0x%jX\n", __FUNCTION__, i,
3645 (uintmax_t) sc->ctx_paddr[i]);
3650 * Create a DMA tag for the TX buffer descriptor chain,
3651 * allocate and clear the memory, and fetch the
3652 * physical address of the block.
3654 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY,
3655 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3656 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0,
3657 NULL, NULL, &sc->tx_bd_chain_tag)) {
3658 BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3659 "chain DMA tag!\n", __FILE__, __LINE__);
3661 goto bce_dma_alloc_exit;
3664 for (i = 0; i < sc->tx_pages; i++) {
3666 if(bus_dmamem_alloc(sc->tx_bd_chain_tag,
3667 (void **)&sc->tx_bd_chain[i],
3668 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3669 &sc->tx_bd_chain_map[i])) {
3670 BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3671 "chain DMA memory!\n", __FILE__, __LINE__);
3673 goto bce_dma_alloc_exit;
3676 error = bus_dmamap_load(sc->tx_bd_chain_tag,
3677 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i],
3678 BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3679 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3681 if (error || sc->tx_bd_chain_paddr[i] == 0) {
3682 BCE_PRINTF("%s(%d): Could not map TX descriptor "
3683 "chain DMA memory!\n", __FILE__, __LINE__);
3685 goto bce_dma_alloc_exit;
3688 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = "
3689 "0x%jX\n", __FUNCTION__, i,
3690 (uintmax_t) sc->tx_bd_chain_paddr[i]);
3693 /* Check the required size before mapping to conserve resources. */
3694 if (bce_tso_enable) {
3695 max_size = BCE_TSO_MAX_SIZE;
3696 max_segments = BCE_MAX_SEGMENTS;
3697 max_seg_size = BCE_TSO_MAX_SEG_SIZE;
3699 max_size = MCLBYTES * BCE_MAX_SEGMENTS;
3700 max_segments = BCE_MAX_SEGMENTS;
3701 max_seg_size = MCLBYTES;
3704 /* Create a DMA tag for TX mbufs. */
3705 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3706 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size,
3707 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) {
3708 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n",
3709 __FILE__, __LINE__);
3711 goto bce_dma_alloc_exit;
3714 /* Create DMA maps for the TX mbufs clusters. */
3715 for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) {
3716 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT,
3717 &sc->tx_mbuf_map[i])) {
3718 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA "
3719 "map!\n", __FILE__, __LINE__);
3721 goto bce_dma_alloc_exit;
3726 * Create a DMA tag for the RX buffer descriptor chain,
3727 * allocate and clear the memory, and fetch the physical
3728 * address of the blocks.
3730 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3731 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR,
3732 sc->max_bus_addr, NULL, NULL,
3733 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
3734 0, NULL, NULL, &sc->rx_bd_chain_tag)) {
3735 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain "
3736 "DMA tag!\n", __FILE__, __LINE__);
3738 goto bce_dma_alloc_exit;
3741 for (i = 0; i < sc->rx_pages; i++) {
3743 if (bus_dmamem_alloc(sc->rx_bd_chain_tag,
3744 (void **)&sc->rx_bd_chain[i],
3745 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3746 &sc->rx_bd_chain_map[i])) {
3747 BCE_PRINTF("%s(%d): Could not allocate RX descriptor "
3748 "chain DMA memory!\n", __FILE__, __LINE__);
3750 goto bce_dma_alloc_exit;
3753 error = bus_dmamap_load(sc->rx_bd_chain_tag,
3754 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i],
3755 BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3756 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3758 if (error || sc->rx_bd_chain_paddr[i] == 0) {
3759 BCE_PRINTF("%s(%d): Could not map RX descriptor "
3760 "chain DMA memory!\n", __FILE__, __LINE__);
3762 goto bce_dma_alloc_exit;
3765 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = "
3766 "0x%jX\n", __FUNCTION__, i,
3767 (uintmax_t) sc->rx_bd_chain_paddr[i]);
3771 * Create a DMA tag for RX mbufs.
3773 if (bce_hdr_split == TRUE)
3774 max_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ?
3775 MCLBYTES : sc->rx_bd_mbuf_alloc_size);
3777 max_size = MJUM9BYTES;
3779 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag "
3780 "(max size = 0x%jX)\n", __FUNCTION__, (uintmax_t)max_size);
3782 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN,
3783 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3784 max_size, 1, max_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) {
3785 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n",
3786 __FILE__, __LINE__);
3788 goto bce_dma_alloc_exit;
3791 /* Create DMA maps for the RX mbuf clusters. */
3792 for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) {
3793 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT,
3794 &sc->rx_mbuf_map[i])) {
3795 BCE_PRINTF("%s(%d): Unable to create RX mbuf "
3796 "DMA map!\n", __FILE__, __LINE__);
3798 goto bce_dma_alloc_exit;
3802 if (bce_hdr_split == TRUE) {
3804 * Create a DMA tag for the page buffer descriptor chain,
3805 * allocate and clear the memory, and fetch the physical
3806 * address of the blocks.
3808 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3809 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr,
3810 NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ,
3811 0, NULL, NULL, &sc->pg_bd_chain_tag)) {
3812 BCE_PRINTF("%s(%d): Could not allocate page descriptor "
3813 "chain DMA tag!\n", __FILE__, __LINE__);
3815 goto bce_dma_alloc_exit;
3818 for (i = 0; i < sc->pg_pages; i++) {
3819 if (bus_dmamem_alloc(sc->pg_bd_chain_tag,
3820 (void **)&sc->pg_bd_chain[i],
3821 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3822 &sc->pg_bd_chain_map[i])) {
3823 BCE_PRINTF("%s(%d): Could not allocate page "
3824 "descriptor chain DMA memory!\n",
3825 __FILE__, __LINE__);
3827 goto bce_dma_alloc_exit;
3830 error = bus_dmamap_load(sc->pg_bd_chain_tag,
3831 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i],
3832 BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr,
3833 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3835 if (error || sc->pg_bd_chain_paddr[i] == 0) {
3836 BCE_PRINTF("%s(%d): Could not map page descriptor "
3837 "chain DMA memory!\n", __FILE__, __LINE__);
3839 goto bce_dma_alloc_exit;
3842 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = "
3843 "0x%jX\n", __FUNCTION__, i,
3844 (uintmax_t) sc->pg_bd_chain_paddr[i]);
3848 * Create a DMA tag for page mbufs.
3850 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3851 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
3852 1, MCLBYTES, 0, NULL, NULL, &sc->pg_mbuf_tag)) {
3853 BCE_PRINTF("%s(%d): Could not allocate page mbuf "
3854 "DMA tag!\n", __FILE__, __LINE__);
3856 goto bce_dma_alloc_exit;
3859 /* Create DMA maps for the page mbuf clusters. */
3860 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) {
3861 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT,
3862 &sc->pg_mbuf_map[i])) {
3863 BCE_PRINTF("%s(%d): Unable to create page mbuf "
3864 "DMA map!\n", __FILE__, __LINE__);
3866 goto bce_dma_alloc_exit;
3872 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3877 /****************************************************************************/
3878 /* Release all resources used by the driver. */
3880 /* Releases all resources acquired by the driver including interrupts, */
3881 /* interrupt handler, interfaces, mutexes, and DMA memory. */
3885 /****************************************************************************/
3887 bce_release_resources(struct bce_softc *sc)
3891 DBENTER(BCE_VERBOSE_RESET);
3897 if (sc->bce_intrhand != NULL) {
3898 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n");
3899 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
3902 if (sc->bce_res_irq != NULL) {
3903 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n");
3904 bus_release_resource(dev, SYS_RES_IRQ,
3905 rman_get_rid(sc->bce_res_irq), sc->bce_res_irq);
3908 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) {
3909 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n");
3910 pci_release_msi(dev);
3913 if (sc->bce_res_mem != NULL) {
3914 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n");
3915 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
3919 if (sc->bce_ifp != NULL) {
3920 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n");
3921 if_free(sc->bce_ifp);
3924 if (mtx_initialized(&sc->bce_mtx))
3925 BCE_LOCK_DESTROY(sc);
3927 DBEXIT(BCE_VERBOSE_RESET);
3931 /****************************************************************************/
3932 /* Firmware synchronization. */
3934 /* Before performing certain events such as a chip reset, synchronize with */
3935 /* the firmware first. */
3938 /* 0 for success, positive value for failure. */
3939 /****************************************************************************/
3941 bce_fw_sync(struct bce_softc *sc, u32 msg_data)
3946 DBENTER(BCE_VERBOSE_RESET);
3948 /* Don't waste any time if we've timed out before. */
3949 if (sc->bce_fw_timed_out == TRUE) {
3951 goto bce_fw_sync_exit;
3954 /* Increment the message sequence number. */
3955 sc->bce_fw_wr_seq++;
3956 msg_data |= sc->bce_fw_wr_seq;
3958 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = "
3959 "0x%08X\n", msg_data);
3961 /* Send the message to the bootcode driver mailbox. */
3962 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
3964 /* Wait for the bootcode to acknowledge the message. */
3965 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
3966 /* Check for a response in the bootcode firmware mailbox. */
3967 val = bce_shmem_rd(sc, BCE_FW_MB);
3968 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
3973 /* If we've timed out, tell bootcode that we've stopped waiting. */
3974 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) &&
3975 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) {
3977 BCE_PRINTF("%s(%d): Firmware synchronization timeout! "
3978 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data);
3980 msg_data &= ~BCE_DRV_MSG_CODE;
3981 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
3983 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
3985 sc->bce_fw_timed_out = TRUE;
3990 DBEXIT(BCE_VERBOSE_RESET);
3995 /****************************************************************************/
3996 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */
4000 /****************************************************************************/
4002 bce_load_rv2p_fw(struct bce_softc *sc, const u32 *rv2p_code,
4003 u32 rv2p_code_len, u32 rv2p_proc)
4008 DBENTER(BCE_VERBOSE_RESET);
4010 /* Set the page size used by RV2P. */
4011 if (rv2p_proc == RV2P_PROC2) {
4012 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE);
4015 for (i = 0; i < rv2p_code_len; i += 8) {
4016 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
4018 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
4021 if (rv2p_proc == RV2P_PROC1) {
4022 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
4023 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
4026 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
4027 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
4031 /* Reset the processor, un-stall is done later. */
4032 if (rv2p_proc == RV2P_PROC1) {
4033 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
4036 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
4039 DBEXIT(BCE_VERBOSE_RESET);
4043 /****************************************************************************/
4044 /* Load RISC processor firmware. */
4046 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */
4047 /* associated with a particular processor. */
4051 /****************************************************************************/
4053 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
4058 DBENTER(BCE_VERBOSE_RESET);
4060 bce_halt_cpu(sc, cpu_reg);
4062 /* Load the Text area. */
4063 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
4067 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
4068 REG_WR_IND(sc, offset, fw->text[j]);
4072 /* Load the Data area. */
4073 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
4077 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
4078 REG_WR_IND(sc, offset, fw->data[j]);
4082 /* Load the SBSS area. */
4083 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
4087 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
4088 REG_WR_IND(sc, offset, fw->sbss[j]);
4092 /* Load the BSS area. */
4093 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
4097 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
4098 REG_WR_IND(sc, offset, fw->bss[j]);
4102 /* Load the Read-Only area. */
4103 offset = cpu_reg->spad_base +
4104 (fw->rodata_addr - cpu_reg->mips_view_base);
4108 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
4109 REG_WR_IND(sc, offset, fw->rodata[j]);
4113 /* Clear the pre-fetch instruction and set the FW start address. */
4114 REG_WR_IND(sc, cpu_reg->inst, 0);
4115 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
4117 DBEXIT(BCE_VERBOSE_RESET);
4121 /****************************************************************************/
4122 /* Starts the RISC processor. */
4124 /* Assumes the CPU starting address has already been set. */
4128 /****************************************************************************/
4130 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4134 DBENTER(BCE_VERBOSE_RESET);
4136 /* Start the CPU. */
4137 val = REG_RD_IND(sc, cpu_reg->mode);
4138 val &= ~cpu_reg->mode_value_halt;
4139 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4140 REG_WR_IND(sc, cpu_reg->mode, val);
4142 DBEXIT(BCE_VERBOSE_RESET);
4146 /****************************************************************************/
4147 /* Halts the RISC processor. */
4151 /****************************************************************************/
4153 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4157 DBENTER(BCE_VERBOSE_RESET);
4160 val = REG_RD_IND(sc, cpu_reg->mode);
4161 val |= cpu_reg->mode_value_halt;
4162 REG_WR_IND(sc, cpu_reg->mode, val);
4163 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4165 DBEXIT(BCE_VERBOSE_RESET);
4169 /****************************************************************************/
4170 /* Initialize the RX CPU. */
4174 /****************************************************************************/
4176 bce_start_rxp_cpu(struct bce_softc *sc)
4178 struct cpu_reg cpu_reg;
4180 DBENTER(BCE_VERBOSE_RESET);
4182 cpu_reg.mode = BCE_RXP_CPU_MODE;
4183 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4184 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4185 cpu_reg.state = BCE_RXP_CPU_STATE;
4186 cpu_reg.state_value_clear = 0xffffff;
4187 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4188 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4189 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4190 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4191 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4192 cpu_reg.spad_base = BCE_RXP_SCRATCH;
4193 cpu_reg.mips_view_base = 0x8000000;
4195 DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n");
4196 bce_start_cpu(sc, &cpu_reg);
4198 DBEXIT(BCE_VERBOSE_RESET);
4202 /****************************************************************************/
4203 /* Initialize the RX CPU. */
4207 /****************************************************************************/
4209 bce_init_rxp_cpu(struct bce_softc *sc)
4211 struct cpu_reg cpu_reg;
4214 DBENTER(BCE_VERBOSE_RESET);
4216 cpu_reg.mode = BCE_RXP_CPU_MODE;
4217 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4218 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4219 cpu_reg.state = BCE_RXP_CPU_STATE;
4220 cpu_reg.state_value_clear = 0xffffff;
4221 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4222 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4223 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4224 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4225 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4226 cpu_reg.spad_base = BCE_RXP_SCRATCH;
4227 cpu_reg.mips_view_base = 0x8000000;
4229 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4230 fw.ver_major = bce_RXP_b09FwReleaseMajor;
4231 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
4232 fw.ver_fix = bce_RXP_b09FwReleaseFix;
4233 fw.start_addr = bce_RXP_b09FwStartAddr;
4235 fw.text_addr = bce_RXP_b09FwTextAddr;
4236 fw.text_len = bce_RXP_b09FwTextLen;
4238 fw.text = bce_RXP_b09FwText;
4240 fw.data_addr = bce_RXP_b09FwDataAddr;
4241 fw.data_len = bce_RXP_b09FwDataLen;
4243 fw.data = bce_RXP_b09FwData;
4245 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
4246 fw.sbss_len = bce_RXP_b09FwSbssLen;
4248 fw.sbss = bce_RXP_b09FwSbss;
4250 fw.bss_addr = bce_RXP_b09FwBssAddr;
4251 fw.bss_len = bce_RXP_b09FwBssLen;
4253 fw.bss = bce_RXP_b09FwBss;
4255 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
4256 fw.rodata_len = bce_RXP_b09FwRodataLen;
4257 fw.rodata_index = 0;
4258 fw.rodata = bce_RXP_b09FwRodata;
4260 fw.ver_major = bce_RXP_b06FwReleaseMajor;
4261 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
4262 fw.ver_fix = bce_RXP_b06FwReleaseFix;
4263 fw.start_addr = bce_RXP_b06FwStartAddr;
4265 fw.text_addr = bce_RXP_b06FwTextAddr;
4266 fw.text_len = bce_RXP_b06FwTextLen;
4268 fw.text = bce_RXP_b06FwText;
4270 fw.data_addr = bce_RXP_b06FwDataAddr;
4271 fw.data_len = bce_RXP_b06FwDataLen;
4273 fw.data = bce_RXP_b06FwData;
4275 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
4276 fw.sbss_len = bce_RXP_b06FwSbssLen;
4278 fw.sbss = bce_RXP_b06FwSbss;
4280 fw.bss_addr = bce_RXP_b06FwBssAddr;
4281 fw.bss_len = bce_RXP_b06FwBssLen;
4283 fw.bss = bce_RXP_b06FwBss;
4285 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
4286 fw.rodata_len = bce_RXP_b06FwRodataLen;
4287 fw.rodata_index = 0;
4288 fw.rodata = bce_RXP_b06FwRodata;
4291 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
4292 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4294 /* Delay RXP start until initialization is complete. */
4296 DBEXIT(BCE_VERBOSE_RESET);
4300 /****************************************************************************/
4301 /* Initialize the TX CPU. */
4305 /****************************************************************************/
4307 bce_init_txp_cpu(struct bce_softc *sc)
4309 struct cpu_reg cpu_reg;
4312 DBENTER(BCE_VERBOSE_RESET);
4314 cpu_reg.mode = BCE_TXP_CPU_MODE;
4315 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
4316 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
4317 cpu_reg.state = BCE_TXP_CPU_STATE;
4318 cpu_reg.state_value_clear = 0xffffff;
4319 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
4320 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
4321 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
4322 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
4323 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
4324 cpu_reg.spad_base = BCE_TXP_SCRATCH;
4325 cpu_reg.mips_view_base = 0x8000000;
4327 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4328 fw.ver_major = bce_TXP_b09FwReleaseMajor;
4329 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
4330 fw.ver_fix = bce_TXP_b09FwReleaseFix;
4331 fw.start_addr = bce_TXP_b09FwStartAddr;
4333 fw.text_addr = bce_TXP_b09FwTextAddr;
4334 fw.text_len = bce_TXP_b09FwTextLen;
4336 fw.text = bce_TXP_b09FwText;
4338 fw.data_addr = bce_TXP_b09FwDataAddr;
4339 fw.data_len = bce_TXP_b09FwDataLen;
4341 fw.data = bce_TXP_b09FwData;
4343 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
4344 fw.sbss_len = bce_TXP_b09FwSbssLen;
4346 fw.sbss = bce_TXP_b09FwSbss;
4348 fw.bss_addr = bce_TXP_b09FwBssAddr;
4349 fw.bss_len = bce_TXP_b09FwBssLen;
4351 fw.bss = bce_TXP_b09FwBss;
4353 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
4354 fw.rodata_len = bce_TXP_b09FwRodataLen;
4355 fw.rodata_index = 0;
4356 fw.rodata = bce_TXP_b09FwRodata;
4358 fw.ver_major = bce_TXP_b06FwReleaseMajor;
4359 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
4360 fw.ver_fix = bce_TXP_b06FwReleaseFix;
4361 fw.start_addr = bce_TXP_b06FwStartAddr;
4363 fw.text_addr = bce_TXP_b06FwTextAddr;
4364 fw.text_len = bce_TXP_b06FwTextLen;
4366 fw.text = bce_TXP_b06FwText;
4368 fw.data_addr = bce_TXP_b06FwDataAddr;
4369 fw.data_len = bce_TXP_b06FwDataLen;
4371 fw.data = bce_TXP_b06FwData;
4373 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
4374 fw.sbss_len = bce_TXP_b06FwSbssLen;
4376 fw.sbss = bce_TXP_b06FwSbss;
4378 fw.bss_addr = bce_TXP_b06FwBssAddr;
4379 fw.bss_len = bce_TXP_b06FwBssLen;
4381 fw.bss = bce_TXP_b06FwBss;
4383 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
4384 fw.rodata_len = bce_TXP_b06FwRodataLen;
4385 fw.rodata_index = 0;
4386 fw.rodata = bce_TXP_b06FwRodata;
4389 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
4390 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4391 bce_start_cpu(sc, &cpu_reg);
4393 DBEXIT(BCE_VERBOSE_RESET);
4397 /****************************************************************************/
4398 /* Initialize the TPAT CPU. */
4402 /****************************************************************************/
4404 bce_init_tpat_cpu(struct bce_softc *sc)
4406 struct cpu_reg cpu_reg;
4409 DBENTER(BCE_VERBOSE_RESET);
4411 cpu_reg.mode = BCE_TPAT_CPU_MODE;
4412 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
4413 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
4414 cpu_reg.state = BCE_TPAT_CPU_STATE;
4415 cpu_reg.state_value_clear = 0xffffff;
4416 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
4417 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
4418 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
4419 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
4420 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
4421 cpu_reg.spad_base = BCE_TPAT_SCRATCH;
4422 cpu_reg.mips_view_base = 0x8000000;
4424 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4425 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
4426 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
4427 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
4428 fw.start_addr = bce_TPAT_b09FwStartAddr;
4430 fw.text_addr = bce_TPAT_b09FwTextAddr;
4431 fw.text_len = bce_TPAT_b09FwTextLen;
4433 fw.text = bce_TPAT_b09FwText;
4435 fw.data_addr = bce_TPAT_b09FwDataAddr;
4436 fw.data_len = bce_TPAT_b09FwDataLen;
4438 fw.data = bce_TPAT_b09FwData;
4440 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
4441 fw.sbss_len = bce_TPAT_b09FwSbssLen;
4443 fw.sbss = bce_TPAT_b09FwSbss;
4445 fw.bss_addr = bce_TPAT_b09FwBssAddr;
4446 fw.bss_len = bce_TPAT_b09FwBssLen;
4448 fw.bss = bce_TPAT_b09FwBss;
4450 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
4451 fw.rodata_len = bce_TPAT_b09FwRodataLen;
4452 fw.rodata_index = 0;
4453 fw.rodata = bce_TPAT_b09FwRodata;
4455 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
4456 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
4457 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
4458 fw.start_addr = bce_TPAT_b06FwStartAddr;
4460 fw.text_addr = bce_TPAT_b06FwTextAddr;
4461 fw.text_len = bce_TPAT_b06FwTextLen;
4463 fw.text = bce_TPAT_b06FwText;
4465 fw.data_addr = bce_TPAT_b06FwDataAddr;
4466 fw.data_len = bce_TPAT_b06FwDataLen;
4468 fw.data = bce_TPAT_b06FwData;
4470 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
4471 fw.sbss_len = bce_TPAT_b06FwSbssLen;
4473 fw.sbss = bce_TPAT_b06FwSbss;
4475 fw.bss_addr = bce_TPAT_b06FwBssAddr;
4476 fw.bss_len = bce_TPAT_b06FwBssLen;
4478 fw.bss = bce_TPAT_b06FwBss;
4480 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
4481 fw.rodata_len = bce_TPAT_b06FwRodataLen;
4482 fw.rodata_index = 0;
4483 fw.rodata = bce_TPAT_b06FwRodata;
4486 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
4487 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4488 bce_start_cpu(sc, &cpu_reg);
4490 DBEXIT(BCE_VERBOSE_RESET);
4494 /****************************************************************************/
4495 /* Initialize the CP CPU. */
4499 /****************************************************************************/
4501 bce_init_cp_cpu(struct bce_softc *sc)
4503 struct cpu_reg cpu_reg;
4506 DBENTER(BCE_VERBOSE_RESET);
4508 cpu_reg.mode = BCE_CP_CPU_MODE;
4509 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
4510 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
4511 cpu_reg.state = BCE_CP_CPU_STATE;
4512 cpu_reg.state_value_clear = 0xffffff;
4513 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
4514 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
4515 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
4516 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
4517 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
4518 cpu_reg.spad_base = BCE_CP_SCRATCH;
4519 cpu_reg.mips_view_base = 0x8000000;
4521 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4522 fw.ver_major = bce_CP_b09FwReleaseMajor;
4523 fw.ver_minor = bce_CP_b09FwReleaseMinor;
4524 fw.ver_fix = bce_CP_b09FwReleaseFix;
4525 fw.start_addr = bce_CP_b09FwStartAddr;
4527 fw.text_addr = bce_CP_b09FwTextAddr;
4528 fw.text_len = bce_CP_b09FwTextLen;
4530 fw.text = bce_CP_b09FwText;
4532 fw.data_addr = bce_CP_b09FwDataAddr;
4533 fw.data_len = bce_CP_b09FwDataLen;
4535 fw.data = bce_CP_b09FwData;
4537 fw.sbss_addr = bce_CP_b09FwSbssAddr;
4538 fw.sbss_len = bce_CP_b09FwSbssLen;
4540 fw.sbss = bce_CP_b09FwSbss;
4542 fw.bss_addr = bce_CP_b09FwBssAddr;
4543 fw.bss_len = bce_CP_b09FwBssLen;
4545 fw.bss = bce_CP_b09FwBss;
4547 fw.rodata_addr = bce_CP_b09FwRodataAddr;
4548 fw.rodata_len = bce_CP_b09FwRodataLen;
4549 fw.rodata_index = 0;
4550 fw.rodata = bce_CP_b09FwRodata;
4552 fw.ver_major = bce_CP_b06FwReleaseMajor;
4553 fw.ver_minor = bce_CP_b06FwReleaseMinor;
4554 fw.ver_fix = bce_CP_b06FwReleaseFix;
4555 fw.start_addr = bce_CP_b06FwStartAddr;
4557 fw.text_addr = bce_CP_b06FwTextAddr;
4558 fw.text_len = bce_CP_b06FwTextLen;
4560 fw.text = bce_CP_b06FwText;
4562 fw.data_addr = bce_CP_b06FwDataAddr;
4563 fw.data_len = bce_CP_b06FwDataLen;
4565 fw.data = bce_CP_b06FwData;
4567 fw.sbss_addr = bce_CP_b06FwSbssAddr;
4568 fw.sbss_len = bce_CP_b06FwSbssLen;
4570 fw.sbss = bce_CP_b06FwSbss;
4572 fw.bss_addr = bce_CP_b06FwBssAddr;
4573 fw.bss_len = bce_CP_b06FwBssLen;
4575 fw.bss = bce_CP_b06FwBss;
4577 fw.rodata_addr = bce_CP_b06FwRodataAddr;
4578 fw.rodata_len = bce_CP_b06FwRodataLen;
4579 fw.rodata_index = 0;
4580 fw.rodata = bce_CP_b06FwRodata;
4583 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
4584 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4585 bce_start_cpu(sc, &cpu_reg);
4587 DBEXIT(BCE_VERBOSE_RESET);
4591 /****************************************************************************/
4592 /* Initialize the COM CPU. */
4596 /****************************************************************************/
4598 bce_init_com_cpu(struct bce_softc *sc)
4600 struct cpu_reg cpu_reg;
4603 DBENTER(BCE_VERBOSE_RESET);
4605 cpu_reg.mode = BCE_COM_CPU_MODE;
4606 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
4607 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
4608 cpu_reg.state = BCE_COM_CPU_STATE;
4609 cpu_reg.state_value_clear = 0xffffff;
4610 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
4611 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
4612 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
4613 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
4614 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
4615 cpu_reg.spad_base = BCE_COM_SCRATCH;
4616 cpu_reg.mips_view_base = 0x8000000;
4618 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4619 fw.ver_major = bce_COM_b09FwReleaseMajor;
4620 fw.ver_minor = bce_COM_b09FwReleaseMinor;
4621 fw.ver_fix = bce_COM_b09FwReleaseFix;
4622 fw.start_addr = bce_COM_b09FwStartAddr;
4624 fw.text_addr = bce_COM_b09FwTextAddr;
4625 fw.text_len = bce_COM_b09FwTextLen;
4627 fw.text = bce_COM_b09FwText;
4629 fw.data_addr = bce_COM_b09FwDataAddr;
4630 fw.data_len = bce_COM_b09FwDataLen;
4632 fw.data = bce_COM_b09FwData;
4634 fw.sbss_addr = bce_COM_b09FwSbssAddr;
4635 fw.sbss_len = bce_COM_b09FwSbssLen;
4637 fw.sbss = bce_COM_b09FwSbss;
4639 fw.bss_addr = bce_COM_b09FwBssAddr;
4640 fw.bss_len = bce_COM_b09FwBssLen;
4642 fw.bss = bce_COM_b09FwBss;
4644 fw.rodata_addr = bce_COM_b09FwRodataAddr;
4645 fw.rodata_len = bce_COM_b09FwRodataLen;
4646 fw.rodata_index = 0;
4647 fw.rodata = bce_COM_b09FwRodata;
4649 fw.ver_major = bce_COM_b06FwReleaseMajor;
4650 fw.ver_minor = bce_COM_b06FwReleaseMinor;
4651 fw.ver_fix = bce_COM_b06FwReleaseFix;
4652 fw.start_addr = bce_COM_b06FwStartAddr;
4654 fw.text_addr = bce_COM_b06FwTextAddr;
4655 fw.text_len = bce_COM_b06FwTextLen;
4657 fw.text = bce_COM_b06FwText;
4659 fw.data_addr = bce_COM_b06FwDataAddr;
4660 fw.data_len = bce_COM_b06FwDataLen;
4662 fw.data = bce_COM_b06FwData;
4664 fw.sbss_addr = bce_COM_b06FwSbssAddr;
4665 fw.sbss_len = bce_COM_b06FwSbssLen;
4667 fw.sbss = bce_COM_b06FwSbss;
4669 fw.bss_addr = bce_COM_b06FwBssAddr;
4670 fw.bss_len = bce_COM_b06FwBssLen;
4672 fw.bss = bce_COM_b06FwBss;
4674 fw.rodata_addr = bce_COM_b06FwRodataAddr;
4675 fw.rodata_len = bce_COM_b06FwRodataLen;
4676 fw.rodata_index = 0;
4677 fw.rodata = bce_COM_b06FwRodata;
4680 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
4681 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4682 bce_start_cpu(sc, &cpu_reg);
4684 DBEXIT(BCE_VERBOSE_RESET);
4688 /****************************************************************************/
4689 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */
4691 /* Loads the firmware for each CPU and starts the CPU. */
4695 /****************************************************************************/
4697 bce_init_cpus(struct bce_softc *sc)
4699 DBENTER(BCE_VERBOSE_RESET);
4701 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4703 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) {
4704 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
4705 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
4706 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
4707 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
4709 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
4710 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
4711 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
4712 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
4716 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
4717 sizeof(bce_rv2p_proc1), RV2P_PROC1);
4718 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
4719 sizeof(bce_rv2p_proc2), RV2P_PROC2);
4722 bce_init_rxp_cpu(sc);
4723 bce_init_txp_cpu(sc);
4724 bce_init_tpat_cpu(sc);
4725 bce_init_com_cpu(sc);
4726 bce_init_cp_cpu(sc);
4728 DBEXIT(BCE_VERBOSE_RESET);
4732 /****************************************************************************/
4733 /* Initialize context memory. */
4735 /* Clears the memory associated with each Context ID (CID). */
4739 /****************************************************************************/
4741 bce_init_ctx(struct bce_softc *sc)
4743 u32 offset, val, vcid_addr;
4744 int i, j, rc, retry_cnt;
4747 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4749 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4750 retry_cnt = CTX_INIT_RETRY_COUNT;
4752 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n");
4755 * BCM5709 context memory may be cached
4756 * in host memory so prepare the host memory
4759 val = BCE_CTX_COMMAND_ENABLED |
4760 BCE_CTX_COMMAND_MEM_INIT | (1 << 12);
4761 val |= (BCM_PAGE_BITS - 8) << 16;
4762 REG_WR(sc, BCE_CTX_COMMAND, val);
4764 /* Wait for mem init command to complete. */
4765 for (i = 0; i < retry_cnt; i++) {
4766 val = REG_RD(sc, BCE_CTX_COMMAND);
4767 if (!(val & BCE_CTX_COMMAND_MEM_INIT))
4771 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) {
4772 BCE_PRINTF("%s(): Context memory initialization failed!\n",
4778 for (i = 0; i < sc->ctx_pages; i++) {
4779 /* Set the physical address of the context memory. */
4780 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
4781 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
4782 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
4783 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
4784 BCE_ADDR_HI(sc->ctx_paddr[i]));
4785 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i |
4786 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
4788 /* Verify the context memory write was successful. */
4789 for (j = 0; j < retry_cnt; j++) {
4790 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
4792 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
4796 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) {
4797 BCE_PRINTF("%s(): Failed to initialize "
4798 "context page %d!\n", __FUNCTION__, i);
4805 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n");
4808 * For the 5706/5708, context memory is local to
4809 * the controller, so initialize the controller
4813 vcid_addr = GET_CID_ADDR(96);
4816 vcid_addr -= PHY_CTX_SIZE;
4818 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
4819 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4821 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
4822 CTX_WR(sc, 0x00, offset, 0);
4825 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
4826 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4831 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4836 /****************************************************************************/
4837 /* Fetch the permanent MAC address of the controller. */
4841 /****************************************************************************/
4843 bce_get_mac_addr(struct bce_softc *sc)
4845 u32 mac_lo = 0, mac_hi = 0;
4847 DBENTER(BCE_VERBOSE_RESET);
4850 * The NetXtreme II bootcode populates various NIC
4851 * power-on and runtime configuration items in a
4852 * shared memory area. The factory configured MAC
4853 * address is available from both NVRAM and the
4854 * shared memory area so we'll read the value from
4855 * shared memory for speed.
4858 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER);
4859 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
4861 if ((mac_lo == 0) && (mac_hi == 0)) {
4862 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n",
4863 __FILE__, __LINE__);
4865 sc->eaddr[0] = (u_char)(mac_hi >> 8);
4866 sc->eaddr[1] = (u_char)(mac_hi >> 0);
4867 sc->eaddr[2] = (u_char)(mac_lo >> 24);
4868 sc->eaddr[3] = (u_char)(mac_lo >> 16);
4869 sc->eaddr[4] = (u_char)(mac_lo >> 8);
4870 sc->eaddr[5] = (u_char)(mac_lo >> 0);
4873 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet "
4874 "address = %6D\n", sc->eaddr, ":");
4875 DBEXIT(BCE_VERBOSE_RESET);
4879 /****************************************************************************/
4880 /* Program the MAC address. */
4884 /****************************************************************************/
4886 bce_set_mac_addr(struct bce_softc *sc)
4889 u8 *mac_addr = sc->eaddr;
4891 /* ToDo: Add support for setting multiple MAC addresses. */
4893 DBENTER(BCE_VERBOSE_RESET);
4894 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = "
4895 "%6D\n", sc->eaddr, ":");
4897 val = (mac_addr[0] << 8) | mac_addr[1];
4899 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
4901 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
4902 (mac_addr[4] << 8) | mac_addr[5];
4904 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
4906 DBEXIT(BCE_VERBOSE_RESET);
4910 /****************************************************************************/
4911 /* Stop the controller. */
4915 /****************************************************************************/
4917 bce_stop(struct bce_softc *sc)
4921 DBENTER(BCE_VERBOSE_RESET);
4923 BCE_LOCK_ASSERT(sc);
4927 callout_stop(&sc->bce_tick_callout);
4929 /* Disable the transmit/receive blocks. */
4930 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
4931 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
4934 bce_disable_intr(sc);
4936 /* Free RX buffers. */
4937 if (bce_hdr_split == TRUE) {
4938 bce_free_pg_chain(sc);
4940 bce_free_rx_chain(sc);
4942 /* Free TX buffers. */
4943 bce_free_tx_chain(sc);
4945 sc->watchdog_timer = 0;
4947 sc->bce_link_up = FALSE;
4949 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4951 DBEXIT(BCE_VERBOSE_RESET);
4956 bce_reset(struct bce_softc *sc, u32 reset_code)
4958 u32 emac_mode_save, val;
4960 static const u32 emac_mode_mask = BCE_EMAC_MODE_PORT |
4961 BCE_EMAC_MODE_HALF_DUPLEX | BCE_EMAC_MODE_25G;
4963 DBENTER(BCE_VERBOSE_RESET);
4965 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n",
4966 __FUNCTION__, reset_code);
4969 * If ASF/IPMI is operational, then the EMAC Mode register already
4970 * contains appropriate values for the link settings that have
4971 * been auto-negotiated. Resetting the chip will clobber those
4972 * values. Save the important bits so we can restore them after
4975 emac_mode_save = REG_RD(sc, BCE_EMAC_MODE) & emac_mode_mask;
4977 /* Wait for pending PCI transactions to complete. */
4978 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
4979 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4980 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4981 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4982 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4983 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
4987 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4988 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
4989 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
4990 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
4993 /* Assume bootcode is running. */
4994 sc->bce_fw_timed_out = FALSE;
4995 sc->bce_drv_cardiac_arrest = FALSE;
4997 /* Give the firmware a chance to prepare for the reset. */
4998 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
5000 goto bce_reset_exit;
5002 /* Set a firmware reminder that this is a soft reset. */
5003 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC);
5005 /* Dummy read to force the chip to complete all current transactions. */
5006 val = REG_RD(sc, BCE_MISC_ID);
5009 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5010 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
5011 REG_RD(sc, BCE_MISC_COMMAND);
5014 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5015 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
5017 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
5019 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5020 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5021 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
5022 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
5024 /* Allow up to 30us for reset to complete. */
5025 for (i = 0; i < 10; i++) {
5026 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
5027 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5028 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
5034 /* Check that reset completed successfully. */
5035 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5036 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
5037 BCE_PRINTF("%s(%d): Reset failed!\n",
5038 __FILE__, __LINE__);
5040 goto bce_reset_exit;
5044 /* Make sure byte swapping is properly configured. */
5045 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
5046 if (val != 0x01020304) {
5047 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n",
5048 __FILE__, __LINE__);
5050 goto bce_reset_exit;
5053 /* Just completed a reset, assume that firmware is running again. */
5054 sc->bce_fw_timed_out = FALSE;
5055 sc->bce_drv_cardiac_arrest = FALSE;
5057 /* Wait for the firmware to finish its initialization. */
5058 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
5060 BCE_PRINTF("%s(%d): Firmware did not complete "
5061 "initialization!\n", __FILE__, __LINE__);
5062 /* Get firmware capabilities. */
5063 bce_fw_cap_init(sc);
5066 /* Restore EMAC Mode bits needed to keep ASF/IPMI running. */
5067 if (reset_code == BCE_DRV_MSG_CODE_RESET) {
5068 val = REG_RD(sc, BCE_EMAC_MODE);
5069 val = (val & ~emac_mode_mask) | emac_mode_save;
5070 REG_WR(sc, BCE_EMAC_MODE, val);
5073 DBEXIT(BCE_VERBOSE_RESET);
5079 bce_chipinit(struct bce_softc *sc)
5084 DBENTER(BCE_VERBOSE_RESET);
5086 bce_disable_intr(sc);
5089 * Initialize DMA byte/word swapping, configure the number of DMA
5090 * channels and PCI clock compensation delay.
5092 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
5093 BCE_DMA_CONFIG_DATA_WORD_SWAP |
5094 #if BYTE_ORDER == BIG_ENDIAN
5095 BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
5097 BCE_DMA_CONFIG_CNTL_WORD_SWAP |
5098 DMA_READ_CHANS << 12 |
5099 DMA_WRITE_CHANS << 16;
5101 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
5103 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133))
5104 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
5107 * This setting resolves a problem observed on certain Intel PCI
5108 * chipsets that cannot handle multiple outstanding DMA operations.
5109 * See errata E9_5706A1_65.
5111 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5112 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) &&
5113 !(sc->bce_flags & BCE_PCIX_FLAG))
5114 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
5116 REG_WR(sc, BCE_DMA_CONFIG, val);
5118 /* Enable the RX_V2P and Context state machines before access. */
5119 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5120 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
5121 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
5122 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
5124 /* Initialize context mapping and zero out the quick contexts. */
5125 if ((rc = bce_init_ctx(sc)) != 0)
5126 goto bce_chipinit_exit;
5128 /* Initialize the on-boards CPUs */
5131 /* Enable management frames (NC-SI) to flow to the MCP. */
5132 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5133 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
5134 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5137 /* Prepare NVRAM for access. */
5138 if ((rc = bce_init_nvram(sc)) != 0)
5139 goto bce_chipinit_exit;
5141 /* Set the kernel bypass block size */
5142 val = REG_RD(sc, BCE_MQ_CONFIG);
5143 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
5144 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
5146 /* Enable bins used on the 5709. */
5147 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5148 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
5149 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
5150 val |= BCE_MQ_CONFIG_HALT_DIS;
5153 REG_WR(sc, BCE_MQ_CONFIG, val);
5155 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
5156 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
5157 REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
5159 /* Set the page size and clear the RV2P processor stall bits. */
5160 val = (BCM_PAGE_BITS - 8) << 24;
5161 REG_WR(sc, BCE_RV2P_CONFIG, val);
5163 /* Configure page size. */
5164 val = REG_RD(sc, BCE_TBDR_CONFIG);
5165 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
5166 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
5167 REG_WR(sc, BCE_TBDR_CONFIG, val);
5169 /* Set the perfect match control register to default. */
5170 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
5173 DBEXIT(BCE_VERBOSE_RESET);
5179 /****************************************************************************/
5180 /* Initialize the controller in preparation to send/receive traffic. */
5183 /* 0 for success, positive value for failure. */
5184 /****************************************************************************/
5186 bce_blockinit(struct bce_softc *sc)
5191 DBENTER(BCE_VERBOSE_RESET);
5193 /* Load the hardware default MAC address. */
5194 bce_set_mac_addr(sc);
5196 /* Set the Ethernet backoff seed value */
5197 val = sc->eaddr[0] + (sc->eaddr[1] << 8) +
5198 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) +
5199 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
5200 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
5202 sc->last_status_idx = 0;
5203 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
5205 /* Set up link change interrupt generation. */
5206 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
5208 /* Program the physical address of the status block. */
5209 REG_WR(sc, BCE_HC_STATUS_ADDR_L,
5210 BCE_ADDR_LO(sc->status_block_paddr));
5211 REG_WR(sc, BCE_HC_STATUS_ADDR_H,
5212 BCE_ADDR_HI(sc->status_block_paddr));
5214 /* Program the physical address of the statistics block. */
5215 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
5216 BCE_ADDR_LO(sc->stats_block_paddr));
5217 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
5218 BCE_ADDR_HI(sc->stats_block_paddr));
5221 * Program various host coalescing parameters.
5222 * Trip points control how many BDs should be ready before generating
5223 * an interrupt while ticks control how long a BD can sit in the chain
5224 * before generating an interrupt.
5226 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5227 (sc->bce_tx_quick_cons_trip_int << 16) |
5228 sc->bce_tx_quick_cons_trip);
5229 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5230 (sc->bce_rx_quick_cons_trip_int << 16) |
5231 sc->bce_rx_quick_cons_trip);
5232 REG_WR(sc, BCE_HC_TX_TICKS,
5233 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
5234 REG_WR(sc, BCE_HC_RX_TICKS,
5235 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
5236 REG_WR(sc, BCE_HC_STATS_TICKS, sc->bce_stats_ticks & 0xffff00);
5237 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
5238 /* Not used for L2. */
5239 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 0);
5240 REG_WR(sc, BCE_HC_COM_TICKS, 0);
5241 REG_WR(sc, BCE_HC_CMD_TICKS, 0);
5243 /* Configure the Host Coalescing block. */
5244 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE |
5245 BCE_HC_CONFIG_COLLECT_STATS;
5248 /* ToDo: Add MSI-X support. */
5249 if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
5250 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) +
5253 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL);
5255 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE |
5256 BCE_HC_SB_CONFIG_1_ONE_SHOT);
5258 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF,
5259 (sc->tx_quick_cons_trip_int << 16) |
5260 sc->tx_quick_cons_trip);
5262 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF,
5263 (sc->tx_ticks_int << 16) | sc->tx_ticks);
5265 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
5269 * Tell the HC block to automatically set the
5270 * INT_MASK bit after an MSI/MSI-X interrupt
5271 * is generated so the driver doesn't have to.
5273 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG)
5274 val |= BCE_HC_CONFIG_ONE_SHOT;
5276 /* Set the MSI-X status blocks to 128 byte boundaries. */
5277 if (sc->bce_flags & BCE_USING_MSIX_FLAG)
5278 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
5281 REG_WR(sc, BCE_HC_CONFIG, val);
5283 /* Clear the internal statistics counters. */
5284 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
5286 /* Verify that bootcode is running. */
5287 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
5289 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control),
5290 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n",
5291 __FILE__, __LINE__);
5294 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5295 BCE_DEV_INFO_SIGNATURE_MAGIC) {
5296 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, "
5297 "Expected: 08%08X\n", __FILE__, __LINE__,
5298 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK),
5299 BCE_DEV_INFO_SIGNATURE_MAGIC);
5301 goto bce_blockinit_exit;
5305 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5306 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
5307 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
5308 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
5311 /* Allow bootcode to apply additional fixes before enabling MAC. */
5312 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 |
5313 BCE_DRV_MSG_CODE_RESET);
5315 /* Enable link state change interrupt generation. */
5316 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
5318 /* Enable the RXP. */
5319 bce_start_rxp_cpu(sc);
5321 /* Disable management frames (NC-SI) from flowing to the MCP. */
5322 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5323 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
5324 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
5325 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5328 /* Enable all remaining blocks in the MAC. */
5329 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
5330 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5331 BCE_MISC_ENABLE_DEFAULT_XI);
5333 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5334 BCE_MISC_ENABLE_DEFAULT);
5336 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
5339 /* Save the current host coalescing block settings. */
5340 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
5343 DBEXIT(BCE_VERBOSE_RESET);
5349 /****************************************************************************/
5350 /* Encapsulate an mbuf into the rx_bd chain. */
5353 /* 0 for success, positive value for failure. */
5354 /****************************************************************************/
5356 bce_get_rx_buf(struct bce_softc *sc, u16 prod, u16 chain_prod, u32 *prod_bseq)
5358 bus_dma_segment_t segs[1];
5359 struct mbuf *m_new = NULL;
5361 int nsegs, error, rc = 0;
5363 u16 debug_chain_prod = chain_prod;
5366 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5368 /* Make sure the inputs are valid. */
5369 DBRUNIF((chain_prod > MAX_RX_BD_ALLOC),
5370 BCE_PRINTF("%s(%d): RX producer out of range: "
5371 "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5372 chain_prod, (u16)MAX_RX_BD_ALLOC));
5374 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5375 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__,
5376 prod, chain_prod, *prod_bseq);
5378 /* Update some debug statistic counters */
5379 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
5380 sc->rx_low_watermark = sc->free_rx_bd);
5381 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
5382 sc->rx_empty_count++);
5384 /* Simulate an mbuf allocation failure. */
5385 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5386 sc->mbuf_alloc_failed_count++;
5387 sc->mbuf_alloc_failed_sim_count++;
5389 goto bce_get_rx_buf_exit);
5391 /* This is a new mbuf allocation. */
5392 if (bce_hdr_split == TRUE)
5393 MGETHDR(m_new, M_NOWAIT, MT_DATA);
5395 m_new = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
5396 sc->rx_bd_mbuf_alloc_size);
5398 if (m_new == NULL) {
5399 sc->mbuf_alloc_failed_count++;
5401 goto bce_get_rx_buf_exit;
5404 DBRUN(sc->debug_rx_mbuf_alloc++);
5406 /* Make sure we have a valid packet header. */
5407 M_ASSERTPKTHDR(m_new);
5409 /* Initialize the mbuf size and pad if necessary for alignment. */
5410 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size;
5411 m_adj(m_new, sc->rx_bd_mbuf_align_pad);
5413 /* ToDo: Consider calling m_fragment() to test error handling. */
5415 /* Map the mbuf cluster into device memory. */
5416 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag,
5417 sc->rx_mbuf_map[chain_prod], m_new, segs, &nsegs, BUS_DMA_NOWAIT);
5419 /* Handle any mapping errors. */
5421 BCE_PRINTF("%s(%d): Error mapping mbuf into RX "
5422 "chain (%d)!\n", __FILE__, __LINE__, error);
5424 sc->dma_map_addr_rx_failed_count++;
5427 DBRUN(sc->debug_rx_mbuf_alloc--);
5430 goto bce_get_rx_buf_exit;
5433 /* All mbufs must map to a single segment. */
5434 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",
5435 __FUNCTION__, nsegs));
5437 /* Setup the rx_bd for the segment. */
5438 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
5440 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr));
5441 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr));
5442 rxbd->rx_bd_len = htole32(segs[0].ds_len);
5443 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5444 *prod_bseq += segs[0].ds_len;
5446 /* Save the mbuf and update our counter. */
5447 sc->rx_mbuf_ptr[chain_prod] = m_new;
5448 sc->free_rx_bd -= nsegs;
5450 DBRUNMSG(BCE_INSANE_RECV,
5451 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs));
5453 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5454 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, prod,
5455 chain_prod, *prod_bseq);
5457 bce_get_rx_buf_exit:
5458 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5464 /****************************************************************************/
5465 /* Encapsulate an mbuf cluster into the page chain. */
5468 /* 0 for success, positive value for failure. */
5469 /****************************************************************************/
5471 bce_get_pg_buf(struct bce_softc *sc, u16 prod, u16 prod_idx)
5473 bus_dma_segment_t segs[1];
5474 struct mbuf *m_new = NULL;
5476 int error, nsegs, rc = 0;
5478 u16 debug_prod_idx = prod_idx;
5481 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5483 /* Make sure the inputs are valid. */
5484 DBRUNIF((prod_idx > MAX_PG_BD_ALLOC),
5485 BCE_PRINTF("%s(%d): page producer out of range: "
5486 "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5487 prod_idx, (u16)MAX_PG_BD_ALLOC));
5489 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5490 "chain_prod = 0x%04X\n", __FUNCTION__, prod, prod_idx);
5492 /* Update counters if we've hit a new low or run out of pages. */
5493 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark),
5494 sc->pg_low_watermark = sc->free_pg_bd);
5495 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++);
5497 /* Simulate an mbuf allocation failure. */
5498 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5499 sc->mbuf_alloc_failed_count++;
5500 sc->mbuf_alloc_failed_sim_count++;
5502 goto bce_get_pg_buf_exit);
5504 /* This is a new mbuf allocation. */
5505 m_new = m_getcl(M_NOWAIT, MT_DATA, 0);
5506 if (m_new == NULL) {
5507 sc->mbuf_alloc_failed_count++;
5509 goto bce_get_pg_buf_exit;
5512 DBRUN(sc->debug_pg_mbuf_alloc++);
5514 m_new->m_len = MCLBYTES;
5516 /* ToDo: Consider calling m_fragment() to test error handling. */
5518 /* Map the mbuf cluster into device memory. */
5519 error = bus_dmamap_load_mbuf_sg(sc->pg_mbuf_tag,
5520 sc->pg_mbuf_map[prod_idx], m_new, segs, &nsegs, BUS_DMA_NOWAIT);
5522 /* Handle any mapping errors. */
5524 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n",
5525 __FILE__, __LINE__);
5528 DBRUN(sc->debug_pg_mbuf_alloc--);
5531 goto bce_get_pg_buf_exit;
5534 /* All mbufs must map to a single segment. */
5535 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",
5536 __FUNCTION__, nsegs));
5538 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */
5541 * The page chain uses the same rx_bd data structure
5542 * as the receive chain but doesn't require a byte sequence (bseq).
5544 pgbd = &sc->pg_bd_chain[PG_PAGE(prod_idx)][PG_IDX(prod_idx)];
5546 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr));
5547 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr));
5548 pgbd->rx_bd_len = htole32(MCLBYTES);
5549 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5551 /* Save the mbuf and update our counter. */
5552 sc->pg_mbuf_ptr[prod_idx] = m_new;
5555 DBRUNMSG(BCE_INSANE_RECV,
5556 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1));
5558 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5559 "prod_idx = 0x%04X\n", __FUNCTION__, prod, prod_idx);
5561 bce_get_pg_buf_exit:
5562 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5568 /****************************************************************************/
5569 /* Initialize the TX context memory. */
5573 /****************************************************************************/
5575 bce_init_tx_context(struct bce_softc *sc)
5579 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5581 /* Initialize the context ID for an L2 TX chain. */
5582 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5583 /* Set the CID type to support an L2 connection. */
5584 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI |
5585 BCE_L2CTX_TX_TYPE_SIZE_L2_XI;
5586 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
5587 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16);
5588 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5589 BCE_L2CTX_TX_CMD_TYPE_XI, val);
5591 /* Point the hardware to the first page in the chain. */
5592 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5593 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5594 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
5595 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5596 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5597 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
5599 /* Set the CID type to support an L2 connection. */
5600 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
5601 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
5602 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
5603 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
5605 /* Point the hardware to the first page in the chain. */
5606 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5607 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5608 BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
5609 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5610 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5611 BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
5614 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5618 /****************************************************************************/
5619 /* Allocate memory and initialize the TX data structures. */
5622 /* 0 for success, positive value for failure. */
5623 /****************************************************************************/
5625 bce_init_tx_chain(struct bce_softc *sc)
5630 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5632 /* Set the initial TX producer/consumer indices. */
5635 sc->tx_prod_bseq = 0;
5637 sc->max_tx_bd = USABLE_TX_BD_ALLOC;
5638 DBRUN(sc->tx_hi_watermark = 0);
5639 DBRUN(sc->tx_full_count = 0);
5642 * The NetXtreme II supports a linked-list structre called
5643 * a Buffer Descriptor Chain (or BD chain). A BD chain
5644 * consists of a series of 1 or more chain pages, each of which
5645 * consists of a fixed number of BD entries.
5646 * The last BD entry on each page is a pointer to the next page
5647 * in the chain, and the last pointer in the BD chain
5648 * points back to the beginning of the chain.
5651 /* Set the TX next pointer chain entries. */
5652 for (i = 0; i < sc->tx_pages; i++) {
5655 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
5657 /* Check if we've reached the last page. */
5658 if (i == (sc->tx_pages - 1))
5663 txbd->tx_bd_haddr_hi =
5664 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
5665 txbd->tx_bd_haddr_lo =
5666 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
5669 bce_init_tx_context(sc);
5671 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC));
5672 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5678 /****************************************************************************/
5679 /* Free memory and clear the TX data structures. */
5683 /****************************************************************************/
5685 bce_free_tx_chain(struct bce_softc *sc)
5689 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5691 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
5692 for (i = 0; i < MAX_TX_BD_AVAIL; i++) {
5693 if (sc->tx_mbuf_ptr[i] != NULL) {
5694 if (sc->tx_mbuf_map[i] != NULL)
5695 bus_dmamap_sync(sc->tx_mbuf_tag,
5697 BUS_DMASYNC_POSTWRITE);
5698 m_freem(sc->tx_mbuf_ptr[i]);
5699 sc->tx_mbuf_ptr[i] = NULL;
5700 DBRUN(sc->debug_tx_mbuf_alloc--);
5704 /* Clear each TX chain page. */
5705 for (i = 0; i < sc->tx_pages; i++)
5706 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
5710 /* Check if we lost any mbufs in the process. */
5711 DBRUNIF((sc->debug_tx_mbuf_alloc),
5712 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs "
5713 "from tx chain!\n", __FILE__, __LINE__,
5714 sc->debug_tx_mbuf_alloc));
5716 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5720 /****************************************************************************/
5721 /* Initialize the RX context memory. */
5725 /****************************************************************************/
5727 bce_init_rx_context(struct bce_softc *sc)
5731 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5733 /* Init the type, size, and BD cache levels for the RX context. */
5734 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
5735 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 |
5736 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT);
5739 * Set the level for generating pause frames
5740 * when the number of available rx_bd's gets
5741 * too low (the low watermark) and the level
5742 * when pause frames can be stopped (the high
5745 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5746 u32 lo_water, hi_water;
5748 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) {
5749 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
5754 if (lo_water >= USABLE_RX_BD_ALLOC) {
5758 hi_water = USABLE_RX_BD_ALLOC / 4;
5760 if (hi_water <= lo_water) {
5764 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
5765 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
5769 else if (hi_water == 0)
5772 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) |
5773 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
5776 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
5778 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
5779 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5780 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
5781 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
5784 /* Point the hardware to the first page in the chain. */
5785 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
5786 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
5787 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
5788 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
5790 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5794 /****************************************************************************/
5795 /* Allocate memory and initialize the RX data structures. */
5798 /* 0 for success, positive value for failure. */
5799 /****************************************************************************/
5801 bce_init_rx_chain(struct bce_softc *sc)
5806 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5809 /* Initialize the RX producer and consumer indices. */
5812 sc->rx_prod_bseq = 0;
5813 sc->free_rx_bd = USABLE_RX_BD_ALLOC;
5814 sc->max_rx_bd = USABLE_RX_BD_ALLOC;
5816 /* Initialize the RX next pointer chain entries. */
5817 for (i = 0; i < sc->rx_pages; i++) {
5820 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
5822 /* Check if we've reached the last page. */
5823 if (i == (sc->rx_pages - 1))
5828 /* Setup the chain page pointers. */
5829 rxbd->rx_bd_haddr_hi =
5830 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
5831 rxbd->rx_bd_haddr_lo =
5832 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
5835 /* Fill up the RX chain. */
5836 bce_fill_rx_chain(sc);
5838 DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC);
5839 DBRUN(sc->rx_empty_count = 0);
5840 for (i = 0; i < sc->rx_pages; i++) {
5841 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i],
5842 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
5845 bce_init_rx_context(sc);
5847 DBRUNMSG(BCE_EXTREME_RECV,
5848 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC));
5849 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5852 /* ToDo: Are there possible failure modes here? */
5858 /****************************************************************************/
5859 /* Add mbufs to the RX chain until its full or an mbuf allocation error */
5864 /****************************************************************************/
5866 bce_fill_rx_chain(struct bce_softc *sc)
5871 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5874 /* Get the RX chain producer indices. */
5876 prod_bseq = sc->rx_prod_bseq;
5878 /* Keep filling the RX chain until it's full. */
5879 while (sc->free_rx_bd > 0) {
5880 prod_idx = RX_CHAIN_IDX(prod);
5881 if (bce_get_rx_buf(sc, prod, prod_idx, &prod_bseq)) {
5882 /* Bail out if we can't add an mbuf to the chain. */
5885 prod = NEXT_RX_BD(prod);
5888 /* Save the RX chain producer indices. */
5890 sc->rx_prod_bseq = prod_bseq;
5892 /* We should never end up pointing to a next page pointer. */
5893 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
5894 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n",
5895 __FUNCTION__, rx_prod));
5897 /* Write the mailbox and tell the chip about the waiting rx_bd's. */
5898 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX, prod);
5899 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ, prod_bseq);
5901 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5906 /****************************************************************************/
5907 /* Free memory and clear the RX data structures. */
5911 /****************************************************************************/
5913 bce_free_rx_chain(struct bce_softc *sc)
5917 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5919 /* Free any mbufs still in the RX mbuf chain. */
5920 for (i = 0; i < MAX_RX_BD_AVAIL; i++) {
5921 if (sc->rx_mbuf_ptr[i] != NULL) {
5922 if (sc->rx_mbuf_map[i] != NULL)
5923 bus_dmamap_sync(sc->rx_mbuf_tag,
5925 BUS_DMASYNC_POSTREAD);
5926 m_freem(sc->rx_mbuf_ptr[i]);
5927 sc->rx_mbuf_ptr[i] = NULL;
5928 DBRUN(sc->debug_rx_mbuf_alloc--);
5932 /* Clear each RX chain page. */
5933 for (i = 0; i < sc->rx_pages; i++)
5934 if (sc->rx_bd_chain[i] != NULL)
5935 bzero((char *)sc->rx_bd_chain[i],
5936 BCE_RX_CHAIN_PAGE_SZ);
5938 sc->free_rx_bd = sc->max_rx_bd;
5940 /* Check if we lost any mbufs in the process. */
5941 DBRUNIF((sc->debug_rx_mbuf_alloc),
5942 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n",
5943 __FUNCTION__, sc->debug_rx_mbuf_alloc));
5945 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5949 /****************************************************************************/
5950 /* Allocate memory and initialize the page data structures. */
5951 /* Assumes that bce_init_rx_chain() has not already been called. */
5954 /* 0 for success, positive value for failure. */
5955 /****************************************************************************/
5957 bce_init_pg_chain(struct bce_softc *sc)
5963 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5966 /* Initialize the page producer and consumer indices. */
5969 sc->free_pg_bd = USABLE_PG_BD_ALLOC;
5970 sc->max_pg_bd = USABLE_PG_BD_ALLOC;
5971 DBRUN(sc->pg_low_watermark = sc->max_pg_bd);
5972 DBRUN(sc->pg_empty_count = 0);
5974 /* Initialize the page next pointer chain entries. */
5975 for (i = 0; i < sc->pg_pages; i++) {
5978 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE];
5980 /* Check if we've reached the last page. */
5981 if (i == (sc->pg_pages - 1))
5986 /* Setup the chain page pointers. */
5987 pgbd->rx_bd_haddr_hi =
5988 htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j]));
5989 pgbd->rx_bd_haddr_lo =
5990 htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j]));
5993 /* Setup the MQ BIN mapping for host_pg_bidx. */
5994 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
5995 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT);
5997 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0);
5999 /* Configure the rx_bd and page chain mbuf cluster size. */
6000 val = (sc->rx_bd_mbuf_data_len << 16) | MCLBYTES;
6001 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val);
6003 /* Configure the context reserved for jumbo support. */
6004 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY,
6005 BCE_L2CTX_RX_RBDC_JUMBO_KEY);
6007 /* Point the hardware to the first page in the page chain. */
6008 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]);
6009 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val);
6010 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]);
6011 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val);
6013 /* Fill up the page chain. */
6014 bce_fill_pg_chain(sc);
6016 for (i = 0; i < sc->pg_pages; i++) {
6017 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i],
6018 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
6021 DBRUNMSG(BCE_EXTREME_RECV,
6022 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC));
6023 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
6029 /****************************************************************************/
6030 /* Add mbufs to the page chain until its full or an mbuf allocation error */
6035 /****************************************************************************/
6037 bce_fill_pg_chain(struct bce_softc *sc)
6041 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
6044 /* Get the page chain prodcuer index. */
6047 /* Keep filling the page chain until it's full. */
6048 while (sc->free_pg_bd > 0) {
6049 prod_idx = PG_CHAIN_IDX(prod);
6050 if (bce_get_pg_buf(sc, prod, prod_idx)) {
6051 /* Bail out if we can't add an mbuf to the chain. */
6054 prod = NEXT_PG_BD(prod);
6057 /* Save the page chain producer index. */
6060 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
6061 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n",
6062 __FUNCTION__, pg_prod));
6065 * Write the mailbox and tell the chip about
6066 * the new rx_bd's in the page chain.
6068 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_PG_BDIDX,
6071 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
6076 /****************************************************************************/
6077 /* Free memory and clear the RX data structures. */
6081 /****************************************************************************/
6083 bce_free_pg_chain(struct bce_softc *sc)
6087 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
6089 /* Free any mbufs still in the mbuf page chain. */
6090 for (i = 0; i < MAX_PG_BD_AVAIL; i++) {
6091 if (sc->pg_mbuf_ptr[i] != NULL) {
6092 if (sc->pg_mbuf_map[i] != NULL)
6093 bus_dmamap_sync(sc->pg_mbuf_tag,
6095 BUS_DMASYNC_POSTREAD);
6096 m_freem(sc->pg_mbuf_ptr[i]);
6097 sc->pg_mbuf_ptr[i] = NULL;
6098 DBRUN(sc->debug_pg_mbuf_alloc--);
6102 /* Clear each page chain pages. */
6103 for (i = 0; i < sc->pg_pages; i++)
6104 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ);
6106 sc->free_pg_bd = sc->max_pg_bd;
6108 /* Check if we lost any mbufs in the process. */
6109 DBRUNIF((sc->debug_pg_mbuf_alloc),
6110 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n",
6111 __FUNCTION__, sc->debug_pg_mbuf_alloc));
6113 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
6118 bce_get_rphy_link(struct bce_softc *sc)
6120 u32 advertise, link;
6125 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0)
6126 link = bce_shmem_rd(sc, BCE_RPHY_SERDES_LINK);
6128 link = bce_shmem_rd(sc, BCE_RPHY_COPPER_LINK);
6129 if (link & BCE_NETLINK_ANEG_ENB)
6130 advertise |= BCE_NETLINK_ANEG_ENB;
6131 if (link & BCE_NETLINK_SPEED_10HALF)
6132 advertise |= BCE_NETLINK_SPEED_10HALF;
6133 if (link & BCE_NETLINK_SPEED_10FULL) {
6134 advertise |= BCE_NETLINK_SPEED_10FULL;
6137 if (link & BCE_NETLINK_SPEED_100HALF)
6138 advertise |= BCE_NETLINK_SPEED_100HALF;
6139 if (link & BCE_NETLINK_SPEED_100FULL) {
6140 advertise |= BCE_NETLINK_SPEED_100FULL;
6143 if (link & BCE_NETLINK_SPEED_1000HALF)
6144 advertise |= BCE_NETLINK_SPEED_1000HALF;
6145 if (link & BCE_NETLINK_SPEED_1000FULL) {
6146 advertise |= BCE_NETLINK_SPEED_1000FULL;
6149 if (link & BCE_NETLINK_SPEED_2500HALF)
6150 advertise |= BCE_NETLINK_SPEED_2500HALF;
6151 if (link & BCE_NETLINK_SPEED_2500FULL) {
6152 advertise |= BCE_NETLINK_SPEED_2500FULL;
6156 advertise |= BCE_NETLINK_FC_PAUSE_SYM |
6157 BCE_NETLINK_FC_PAUSE_ASYM;
6158 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6159 advertise |= BCE_NETLINK_PHY_APP_REMOTE |
6160 BCE_NETLINK_ETH_AT_WIRESPEED;
6166 /****************************************************************************/
6167 /* Set media options. */
6170 /* 0 for success, positive value for failure. */
6171 /****************************************************************************/
6173 bce_ifmedia_upd(struct ifnet *ifp)
6175 struct bce_softc *sc = ifp->if_softc;
6178 DBENTER(BCE_VERBOSE);
6181 error = bce_ifmedia_upd_locked(ifp);
6184 DBEXIT(BCE_VERBOSE);
6189 /****************************************************************************/
6190 /* Set media options. */
6194 /****************************************************************************/
6196 bce_ifmedia_upd_locked(struct ifnet *ifp)
6198 struct bce_softc *sc = ifp->if_softc;
6199 struct mii_data *mii;
6200 struct mii_softc *miisc;
6201 struct ifmedia *ifm;
6205 DBENTER(BCE_VERBOSE_PHY);
6208 BCE_LOCK_ASSERT(sc);
6210 sc->bce_link_up = FALSE;
6211 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6212 ifm = &sc->bce_ifmedia;
6213 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
6216 fdx = IFM_OPTIONS(ifm->ifm_media) & IFM_FDX;
6217 switch(IFM_SUBTYPE(ifm->ifm_media)) {
6220 * Check advertised link of remote PHY by reading
6221 * BCE_RPHY_SERDES_LINK or BCE_RPHY_COPPER_LINK.
6222 * Always use the same link type of remote PHY.
6224 link = bce_get_rphy_link(sc);
6227 if ((sc->bce_phy_flags &
6228 (BCE_PHY_REMOTE_PORT_FIBER_FLAG |
6229 BCE_PHY_2_5G_CAPABLE_FLAG)) == 0)
6233 * Have to enable forced 2.5Gbps configuration.
6236 link |= BCE_NETLINK_SPEED_2500FULL;
6238 link |= BCE_NETLINK_SPEED_2500HALF;
6241 if ((sc->bce_phy_flags &
6242 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6246 * Have to disable 2.5Gbps configuration.
6249 link = BCE_NETLINK_SPEED_1000FULL;
6251 link = BCE_NETLINK_SPEED_1000HALF;
6254 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6257 link = BCE_NETLINK_SPEED_1000FULL;
6259 link = BCE_NETLINK_SPEED_1000HALF;
6262 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6265 link = BCE_NETLINK_SPEED_100FULL;
6267 link = BCE_NETLINK_SPEED_100HALF;
6270 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6273 link = BCE_NETLINK_SPEED_10FULL;
6275 link = BCE_NETLINK_SPEED_10HALF;
6280 if (IFM_SUBTYPE(ifm->ifm_media) != IFM_AUTO) {
6283 * Advertise pause capability for full-duplex media.
6286 link |= BCE_NETLINK_FC_PAUSE_SYM |
6287 BCE_NETLINK_FC_PAUSE_ASYM;
6288 if ((sc->bce_phy_flags &
6289 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6290 link |= BCE_NETLINK_PHY_APP_REMOTE |
6291 BCE_NETLINK_ETH_AT_WIRESPEED;
6294 bce_shmem_wr(sc, BCE_MB_ARGS_0, link);
6295 error = bce_fw_sync(sc, BCE_DRV_MSG_CODE_CMD_SET_LINK);
6297 mii = device_get_softc(sc->bce_miibus);
6299 /* Make sure the MII bus has been enumerated. */
6301 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
6303 error = mii_mediachg(mii);
6307 DBEXIT(BCE_VERBOSE_PHY);
6313 bce_ifmedia_sts_rphy(struct bce_softc *sc, struct ifmediareq *ifmr)
6319 BCE_LOCK_ASSERT(sc);
6321 ifmr->ifm_status = IFM_AVALID;
6322 ifmr->ifm_active = IFM_ETHER;
6323 link = bce_shmem_rd(sc, BCE_LINK_STATUS);
6324 /* XXX Handle heart beat status? */
6325 if ((link & BCE_LINK_STATUS_LINK_UP) != 0)
6326 ifmr->ifm_status |= IFM_ACTIVE;
6328 ifmr->ifm_active |= IFM_NONE;
6329 ifp->if_baudrate = 0;
6332 switch (link & BCE_LINK_STATUS_SPEED_MASK) {
6333 case BCE_LINK_STATUS_10HALF:
6334 ifmr->ifm_active |= IFM_10_T | IFM_HDX;
6335 ifp->if_baudrate = IF_Mbps(10UL);
6337 case BCE_LINK_STATUS_10FULL:
6338 ifmr->ifm_active |= IFM_10_T | IFM_FDX;
6339 ifp->if_baudrate = IF_Mbps(10UL);
6341 case BCE_LINK_STATUS_100HALF:
6342 ifmr->ifm_active |= IFM_100_TX | IFM_HDX;
6343 ifp->if_baudrate = IF_Mbps(100UL);
6345 case BCE_LINK_STATUS_100FULL:
6346 ifmr->ifm_active |= IFM_100_TX | IFM_FDX;
6347 ifp->if_baudrate = IF_Mbps(100UL);
6349 case BCE_LINK_STATUS_1000HALF:
6350 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6351 ifmr->ifm_active |= IFM_1000_T | IFM_HDX;
6353 ifmr->ifm_active |= IFM_1000_SX | IFM_HDX;
6354 ifp->if_baudrate = IF_Mbps(1000UL);
6356 case BCE_LINK_STATUS_1000FULL:
6357 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6358 ifmr->ifm_active |= IFM_1000_T | IFM_FDX;
6360 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
6361 ifp->if_baudrate = IF_Mbps(1000UL);
6363 case BCE_LINK_STATUS_2500HALF:
6364 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6365 ifmr->ifm_active |= IFM_NONE;
6368 ifmr->ifm_active |= IFM_2500_SX | IFM_HDX;
6369 ifp->if_baudrate = IF_Mbps(2500UL);
6371 case BCE_LINK_STATUS_2500FULL:
6372 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6373 ifmr->ifm_active |= IFM_NONE;
6376 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX;
6377 ifp->if_baudrate = IF_Mbps(2500UL);
6380 ifmr->ifm_active |= IFM_NONE;
6384 if ((link & BCE_LINK_STATUS_RX_FC_ENABLED) != 0)
6385 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
6386 if ((link & BCE_LINK_STATUS_TX_FC_ENABLED) != 0)
6387 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
6391 /****************************************************************************/
6392 /* Reports current media status. */
6396 /****************************************************************************/
6398 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
6400 struct bce_softc *sc = ifp->if_softc;
6401 struct mii_data *mii;
6403 DBENTER(BCE_VERBOSE_PHY);
6407 if ((ifp->if_flags & IFF_UP) == 0) {
6412 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
6413 bce_ifmedia_sts_rphy(sc, ifmr);
6415 mii = device_get_softc(sc->bce_miibus);
6417 ifmr->ifm_active = mii->mii_media_active;
6418 ifmr->ifm_status = mii->mii_media_status;
6423 DBEXIT(BCE_VERBOSE_PHY);
6427 /****************************************************************************/
6428 /* Handles PHY generated interrupt events. */
6432 /****************************************************************************/
6434 bce_phy_intr(struct bce_softc *sc)
6436 u32 new_link_state, old_link_state;
6438 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
6440 DBRUN(sc->phy_interrupts++);
6442 new_link_state = sc->status_block->status_attn_bits &
6443 STATUS_ATTN_BITS_LINK_STATE;
6444 old_link_state = sc->status_block->status_attn_bits_ack &
6445 STATUS_ATTN_BITS_LINK_STATE;
6447 /* Handle any changes if the link state has changed. */
6448 if (new_link_state != old_link_state) {
6450 /* Update the status_attn_bits_ack field. */
6451 if (new_link_state) {
6452 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
6453 STATUS_ATTN_BITS_LINK_STATE);
6454 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n",
6457 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
6458 STATUS_ATTN_BITS_LINK_STATE);
6459 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n",
6463 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6464 if (new_link_state) {
6466 if_printf(sc->bce_ifp, "link UP\n");
6467 if_link_state_change(sc->bce_ifp,
6471 if_printf(sc->bce_ifp, "link DOWN\n");
6472 if_link_state_change(sc->bce_ifp,
6477 * Assume link is down and allow
6478 * tick routine to update the state
6479 * based on the actual media state.
6481 sc->bce_link_up = FALSE;
6482 callout_stop(&sc->bce_tick_callout);
6486 /* Acknowledge the link change interrupt. */
6487 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
6489 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
6493 /****************************************************************************/
6494 /* Reads the receive consumer value from the status block (skipping over */
6495 /* chain page pointer if necessary). */
6499 /****************************************************************************/
6501 bce_get_hw_rx_cons(struct bce_softc *sc)
6506 hw_cons = sc->status_block->status_rx_quick_consumer_index0;
6507 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
6513 /****************************************************************************/
6514 /* Handles received frame interrupt events. */
6518 /****************************************************************************/
6520 bce_rx_intr(struct bce_softc *sc)
6522 struct ifnet *ifp = sc->bce_ifp;
6523 struct l2_fhdr *l2fhdr;
6524 struct ether_vlan_header *vh;
6525 unsigned int pkt_len;
6526 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons;
6528 unsigned int rem_len;
6529 u16 sw_pg_cons, sw_pg_cons_idx;
6531 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6532 DBRUN(sc->interrupts_rx++);
6533 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, "
6534 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6535 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6537 /* Prepare the RX chain pages to be accessed by the host CPU. */
6538 for (int i = 0; i < sc->rx_pages; i++)
6539 bus_dmamap_sync(sc->rx_bd_chain_tag,
6540 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
6542 /* Prepare the page chain pages to be accessed by the host CPU. */
6543 if (bce_hdr_split == TRUE) {
6544 for (int i = 0; i < sc->pg_pages; i++)
6545 bus_dmamap_sync(sc->pg_bd_chain_tag,
6546 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
6549 /* Get the hardware's view of the RX consumer index. */
6550 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6552 /* Get working copies of the driver's view of the consumer indices. */
6553 sw_rx_cons = sc->rx_cons;
6554 sw_pg_cons = sc->pg_cons;
6556 /* Update some debug statistics counters */
6557 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
6558 sc->rx_low_watermark = sc->free_rx_bd);
6559 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
6560 sc->rx_empty_count++);
6562 /* Scan through the receive chain as long as there is work to do */
6563 /* ToDo: Consider setting a limit on the number of packets processed. */
6565 while (sw_rx_cons != hw_rx_cons) {
6568 /* Convert the producer/consumer indices to an actual rx_bd index. */
6569 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons);
6571 /* Unmap the mbuf from DMA space. */
6572 bus_dmamap_sync(sc->rx_mbuf_tag,
6573 sc->rx_mbuf_map[sw_rx_cons_idx],
6574 BUS_DMASYNC_POSTREAD);
6575 bus_dmamap_unload(sc->rx_mbuf_tag,
6576 sc->rx_mbuf_map[sw_rx_cons_idx]);
6578 /* Remove the mbuf from the RX chain. */
6579 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx];
6580 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL;
6581 DBRUN(sc->debug_rx_mbuf_alloc--);
6585 * Frames received on the NetXteme II are prepended
6586 * with an l2_fhdr structure which provides status
6587 * information about the received frame (including
6588 * VLAN tags and checksum info). The frames are
6589 * also automatically adjusted to word align the IP
6590 * header (i.e. two null bytes are inserted before
6591 * the Ethernet header). As a result the data
6592 * DMA'd by the controller into the mbuf looks
6595 * +---------+-----+---------------------+-----+
6596 * | l2_fhdr | pad | packet data | FCS |
6597 * +---------+-----+---------------------+-----+
6599 * The l2_fhdr needs to be checked and skipped and
6600 * the FCS needs to be stripped before sending the
6601 * packet up the stack.
6603 l2fhdr = mtod(m0, struct l2_fhdr *);
6605 /* Get the packet data + FCS length and the status. */
6606 pkt_len = l2fhdr->l2_fhdr_pkt_len;
6607 status = l2fhdr->l2_fhdr_status;
6610 * Skip over the l2_fhdr and pad, resulting in the
6611 * following data in the mbuf:
6612 * +---------------------+-----+
6613 * | packet data | FCS |
6614 * +---------------------+-----+
6616 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN);
6619 * When split header mode is used, an ethernet frame
6620 * may be split across the receive chain and the
6621 * page chain. If that occurs an mbuf cluster must be
6622 * reassembled from the individual mbuf pieces.
6624 if (bce_hdr_split == TRUE) {
6626 * Check whether the received frame fits in a single
6627 * mbuf or not (i.e. packet data + FCS <=
6628 * sc->rx_bd_mbuf_data_len bytes).
6630 if (pkt_len > m0->m_len) {
6632 * The received frame is larger than a single mbuf.
6633 * If the frame was a TCP frame then only the TCP
6634 * header is placed in the mbuf, the remaining
6635 * payload (including FCS) is placed in the page
6636 * chain, the SPLIT flag is set, and the header
6637 * length is placed in the IP checksum field.
6638 * If the frame is not a TCP frame then the mbuf
6639 * is filled and the remaining bytes are placed
6640 * in the page chain.
6643 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large "
6644 "packet.\n", __FUNCTION__);
6645 DBRUN(sc->split_header_frames_rcvd++);
6648 * When the page chain is enabled and the TCP
6649 * header has been split from the TCP payload,
6650 * the ip_xsum structure will reflect the length
6651 * of the TCP header, not the IP checksum. Set
6652 * the packet length of the mbuf accordingly.
6654 if (status & L2_FHDR_STATUS_SPLIT) {
6655 m0->m_len = l2fhdr->l2_fhdr_ip_xsum;
6656 DBRUN(sc->split_header_tcp_frames_rcvd++);
6659 rem_len = pkt_len - m0->m_len;
6661 /* Pull mbufs off the page chain for any remaining data. */
6662 while (rem_len > 0) {
6665 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons);
6667 /* Remove the mbuf from the page chain. */
6668 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx];
6669 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL;
6670 DBRUN(sc->debug_pg_mbuf_alloc--);
6673 /* Unmap the page chain mbuf from DMA space. */
6674 bus_dmamap_sync(sc->pg_mbuf_tag,
6675 sc->pg_mbuf_map[sw_pg_cons_idx],
6676 BUS_DMASYNC_POSTREAD);
6677 bus_dmamap_unload(sc->pg_mbuf_tag,
6678 sc->pg_mbuf_map[sw_pg_cons_idx]);
6680 /* Adjust the mbuf length. */
6681 if (rem_len < m_pg->m_len) {
6682 /* The mbuf chain is complete. */
6683 m_pg->m_len = rem_len;
6686 /* More packet data is waiting. */
6687 rem_len -= m_pg->m_len;
6690 /* Concatenate the mbuf cluster to the mbuf. */
6693 sw_pg_cons = NEXT_PG_BD(sw_pg_cons);
6696 /* Set the total packet length. */
6697 m0->m_pkthdr.len = pkt_len;
6701 * The received packet is small and fits in a
6702 * single mbuf (i.e. the l2_fhdr + pad + packet +
6703 * FCS <= MHLEN). In other words, the packet is
6704 * 154 bytes or less in size.
6707 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small "
6708 "packet.\n", __FUNCTION__);
6710 /* Set the total packet length. */
6711 m0->m_pkthdr.len = m0->m_len = pkt_len;
6714 /* Set the total packet length. */
6715 m0->m_pkthdr.len = m0->m_len = pkt_len;
6717 /* Remove the trailing Ethernet FCS. */
6718 m_adj(m0, -ETHER_CRC_LEN);
6720 /* Check that the resulting mbuf chain is valid. */
6721 DBRUN(m_sanity(m0, FALSE));
6722 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) |
6723 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)),
6724 BCE_PRINTF("Invalid Ethernet frame size!\n");
6727 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control),
6728 sc->l2fhdr_error_sim_count++;
6729 status = status | L2_FHDR_ERRORS_PHY_DECODE);
6731 /* Check the received frame for errors. */
6732 if (status & (L2_FHDR_ERRORS_BAD_CRC |
6733 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT |
6734 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) {
6736 /* Log the error and release the mbuf. */
6738 sc->l2fhdr_error_count++;
6742 goto bce_rx_intr_next_rx;
6745 /* Send the packet to the appropriate interface. */
6746 m0->m_pkthdr.rcvif = ifp;
6748 /* Assume no hardware checksum. */
6749 m0->m_pkthdr.csum_flags = 0;
6751 /* Validate the checksum if offload enabled. */
6752 if (ifp->if_capenable & IFCAP_RXCSUM) {
6753 /* Check for an IP datagram. */
6754 if (!(status & L2_FHDR_STATUS_SPLIT) &&
6755 (status & L2_FHDR_STATUS_IP_DATAGRAM)) {
6756 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
6757 DBRUN(sc->csum_offload_ip++);
6758 /* Check if the IP checksum is valid. */
6759 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0)
6760 m0->m_pkthdr.csum_flags |=
6764 /* Check for a valid TCP/UDP frame. */
6765 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
6766 L2_FHDR_STATUS_UDP_DATAGRAM)) {
6768 /* Check for a good TCP/UDP checksum. */
6769 if ((status & (L2_FHDR_ERRORS_TCP_XSUM |
6770 L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
6771 DBRUN(sc->csum_offload_tcp_udp++);
6772 m0->m_pkthdr.csum_data =
6773 l2fhdr->l2_fhdr_tcp_udp_xsum;
6774 m0->m_pkthdr.csum_flags |=
6781 /* Attach the VLAN tag. */
6782 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
6783 !(sc->rx_mode & BCE_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
6784 DBRUN(sc->vlan_tagged_frames_rcvd++);
6785 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
6786 DBRUN(sc->vlan_tagged_frames_stripped++);
6787 #if __FreeBSD_version < 700000
6788 VLAN_INPUT_TAG(ifp, m0,
6789 l2fhdr->l2_fhdr_vlan_tag, continue);
6791 m0->m_pkthdr.ether_vtag =
6792 l2fhdr->l2_fhdr_vlan_tag;
6793 m0->m_flags |= M_VLANTAG;
6797 * bce(4) controllers can't disable VLAN
6798 * tag stripping if management firmware
6799 * (ASF/IPMI/UMP) is running. So we always
6800 * strip VLAN tag and manually reconstruct
6801 * the VLAN frame by appending stripped
6802 * VLAN tag in driver if VLAN tag stripping
6805 * TODO: LLC SNAP handling.
6807 bcopy(mtod(m0, uint8_t *),
6808 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN,
6809 ETHER_ADDR_LEN * 2);
6810 m0->m_data -= ETHER_VLAN_ENCAP_LEN;
6811 vh = mtod(m0, struct ether_vlan_header *);
6812 vh->evl_encap_proto = htons(ETHERTYPE_VLAN);
6813 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag);
6814 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN;
6815 m0->m_len += ETHER_VLAN_ENCAP_LEN;
6819 /* Increment received packet statistics. */
6822 bce_rx_intr_next_rx:
6823 sw_rx_cons = NEXT_RX_BD(sw_rx_cons);
6825 /* If we have a packet, pass it up the stack */
6827 /* Make sure we don't lose our place when we release the lock. */
6828 sc->rx_cons = sw_rx_cons;
6829 sc->pg_cons = sw_pg_cons;
6832 (*ifp->if_input)(ifp, m0);
6835 /* Recover our place. */
6836 sw_rx_cons = sc->rx_cons;
6837 sw_pg_cons = sc->pg_cons;
6840 /* Refresh hw_cons to see if there's new work */
6841 if (sw_rx_cons == hw_rx_cons)
6842 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6845 /* No new packets. Refill the page chain. */
6846 if (bce_hdr_split == TRUE) {
6847 sc->pg_cons = sw_pg_cons;
6848 bce_fill_pg_chain(sc);
6851 /* No new packets. Refill the RX chain. */
6852 sc->rx_cons = sw_rx_cons;
6853 bce_fill_rx_chain(sc);
6855 /* Prepare the page chain pages to be accessed by the NIC. */
6856 for (int i = 0; i < sc->rx_pages; i++)
6857 bus_dmamap_sync(sc->rx_bd_chain_tag,
6858 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6860 if (bce_hdr_split == TRUE) {
6861 for (int i = 0; i < sc->pg_pages; i++)
6862 bus_dmamap_sync(sc->pg_bd_chain_tag,
6863 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6866 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, "
6867 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6868 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6869 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6873 /****************************************************************************/
6874 /* Reads the transmit consumer value from the status block (skipping over */
6875 /* chain page pointer if necessary). */
6879 /****************************************************************************/
6881 bce_get_hw_tx_cons(struct bce_softc *sc)
6886 hw_cons = sc->status_block->status_tx_quick_consumer_index0;
6887 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
6894 /****************************************************************************/
6895 /* Handles transmit completion interrupt events. */
6899 /****************************************************************************/
6901 bce_tx_intr(struct bce_softc *sc)
6903 struct ifnet *ifp = sc->bce_ifp;
6904 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
6906 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
6907 DBRUN(sc->interrupts_tx++);
6908 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, "
6909 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
6910 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
6912 BCE_LOCK_ASSERT(sc);
6914 /* Get the hardware's view of the TX consumer index. */
6915 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6916 sw_tx_cons = sc->tx_cons;
6918 /* Prevent speculative reads of the status block. */
6919 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6920 BUS_SPACE_BARRIER_READ);
6922 /* Cycle through any completed TX chain page entries. */
6923 while (sw_tx_cons != hw_tx_cons) {
6925 struct tx_bd *txbd = NULL;
6927 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
6929 DBPRINT(sc, BCE_INFO_SEND,
6930 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
6931 "sw_tx_chain_cons = 0x%04X\n",
6932 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
6934 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC),
6935 BCE_PRINTF("%s(%d): TX chain consumer out of range! "
6936 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons,
6937 (int) MAX_TX_BD_ALLOC);
6938 bce_breakpoint(sc));
6940 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
6941 [TX_IDX(sw_tx_chain_cons)]);
6943 DBRUNIF((txbd == NULL),
6944 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n",
6945 __FILE__, __LINE__, sw_tx_chain_cons);
6946 bce_breakpoint(sc));
6948 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__);
6949 bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
6952 * Free the associated mbuf. Remember
6953 * that only the last tx_bd of a packet
6954 * has an mbuf pointer and DMA map.
6956 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
6958 /* Validate that this is the last tx_bd. */
6959 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
6960 BCE_PRINTF("%s(%d): tx_bd END flag not set but "
6961 "txmbuf == NULL!\n", __FILE__, __LINE__);
6962 bce_breakpoint(sc));
6964 DBRUNMSG(BCE_INFO_SEND,
6965 BCE_PRINTF("%s(): Unloading map/freeing mbuf "
6966 "from tx_bd[0x%04X]\n", __FUNCTION__,
6969 /* Unmap the mbuf. */
6970 bus_dmamap_unload(sc->tx_mbuf_tag,
6971 sc->tx_mbuf_map[sw_tx_chain_cons]);
6973 /* Free the mbuf. */
6974 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
6975 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
6976 DBRUN(sc->debug_tx_mbuf_alloc--);
6982 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
6984 /* Refresh hw_cons to see if there's new work. */
6985 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6987 /* Prevent speculative reads of the status block. */
6988 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6989 BUS_SPACE_BARRIER_READ);
6992 /* Clear the TX timeout timer. */
6993 sc->watchdog_timer = 0;
6995 /* Clear the tx hardware queue full flag. */
6996 if (sc->used_tx_bd < sc->max_tx_bd) {
6997 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE),
6998 DBPRINT(sc, BCE_INFO_SEND,
6999 "%s(): Open TX chain! %d/%d (used/total)\n",
7000 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd));
7001 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
7004 sc->tx_cons = sw_tx_cons;
7006 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, "
7007 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
7008 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
7009 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
7013 /****************************************************************************/
7014 /* Disables interrupt generation. */
7018 /****************************************************************************/
7020 bce_disable_intr(struct bce_softc *sc)
7022 DBENTER(BCE_VERBOSE_INTR);
7024 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
7025 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
7027 DBEXIT(BCE_VERBOSE_INTR);
7031 /****************************************************************************/
7032 /* Enables interrupt generation. */
7036 /****************************************************************************/
7038 bce_enable_intr(struct bce_softc *sc, int coal_now)
7040 DBENTER(BCE_VERBOSE_INTR);
7042 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7043 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
7044 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
7046 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7047 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
7049 /* Force an immediate interrupt (whether there is new data or not). */
7051 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
7053 DBEXIT(BCE_VERBOSE_INTR);
7057 /****************************************************************************/
7058 /* Handles controller initialization. */
7062 /****************************************************************************/
7064 bce_init_locked(struct bce_softc *sc)
7069 DBENTER(BCE_VERBOSE_RESET);
7071 BCE_LOCK_ASSERT(sc);
7075 /* Check if the driver is still running and bail out if it is. */
7076 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
7077 goto bce_init_locked_exit;
7081 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
7082 BCE_PRINTF("%s(%d): Controller reset failed!\n",
7083 __FILE__, __LINE__);
7084 goto bce_init_locked_exit;
7087 if (bce_chipinit(sc)) {
7088 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
7089 __FILE__, __LINE__);
7090 goto bce_init_locked_exit;
7093 if (bce_blockinit(sc)) {
7094 BCE_PRINTF("%s(%d): Block initialization failed!\n",
7095 __FILE__, __LINE__);
7096 goto bce_init_locked_exit;
7099 /* Load our MAC address. */
7100 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN);
7101 bce_set_mac_addr(sc);
7103 if (bce_hdr_split == FALSE)
7104 bce_get_rx_buffer_sizes(sc, ifp->if_mtu);
7106 * Calculate and program the hardware Ethernet MTU
7107 * size. Be generous on the receive if we have room
7108 * and allowed by the user.
7110 if (bce_strict_rx_mtu == TRUE)
7111 ether_mtu = ifp->if_mtu;
7113 if (bce_hdr_split == TRUE) {
7114 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len + MCLBYTES)
7115 ether_mtu = sc->rx_bd_mbuf_data_len +
7118 ether_mtu = ifp->if_mtu;
7120 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len)
7121 ether_mtu = sc->rx_bd_mbuf_data_len;
7123 ether_mtu = ifp->if_mtu;
7127 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
7129 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n",
7130 __FUNCTION__, ether_mtu);
7132 /* Program the mtu, enabling jumbo frame support if necessary. */
7133 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN))
7134 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
7135 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
7136 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
7138 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
7140 /* Program appropriate promiscuous/multicast filtering. */
7141 bce_set_rx_mode(sc);
7143 if (bce_hdr_split == TRUE) {
7144 /* Init page buffer descriptor chain. */
7145 bce_init_pg_chain(sc);
7148 /* Init RX buffer descriptor chain. */
7149 bce_init_rx_chain(sc);
7151 /* Init TX buffer descriptor chain. */
7152 bce_init_tx_chain(sc);
7154 /* Enable host interrupts. */
7155 bce_enable_intr(sc, 1);
7157 bce_ifmedia_upd_locked(ifp);
7159 /* Let the OS know the driver is up and running. */
7160 ifp->if_drv_flags |= IFF_DRV_RUNNING;
7161 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
7163 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
7165 bce_init_locked_exit:
7166 DBEXIT(BCE_VERBOSE_RESET);
7170 /****************************************************************************/
7171 /* Initialize the controller just enough so that any management firmware */
7172 /* running on the device will continue to operate correctly. */
7176 /****************************************************************************/
7178 bce_mgmt_init_locked(struct bce_softc *sc)
7182 DBENTER(BCE_VERBOSE_RESET);
7184 BCE_LOCK_ASSERT(sc);
7186 /* Bail out if management firmware is not running. */
7187 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) {
7188 DBPRINT(sc, BCE_VERBOSE_SPECIAL,
7189 "No management firmware running...\n");
7190 goto bce_mgmt_init_locked_exit;
7195 /* Enable all critical blocks in the MAC. */
7196 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
7197 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
7200 bce_ifmedia_upd_locked(ifp);
7202 bce_mgmt_init_locked_exit:
7203 DBEXIT(BCE_VERBOSE_RESET);
7207 /****************************************************************************/
7208 /* Handles controller initialization when called from an unlocked routine. */
7212 /****************************************************************************/
7216 struct bce_softc *sc = xsc;
7218 DBENTER(BCE_VERBOSE_RESET);
7221 bce_init_locked(sc);
7224 DBEXIT(BCE_VERBOSE_RESET);
7228 /****************************************************************************/
7229 /* Modifies an mbuf for TSO on the hardware. */
7232 /* Pointer to a modified mbuf. */
7233 /****************************************************************************/
7234 static struct mbuf *
7235 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags)
7238 struct ether_header *eh;
7242 int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0;
7244 DBRUN(sc->tso_frames_requested++);
7246 /* Controller may modify mbuf chains. */
7247 if (M_WRITABLE(*m_head) == 0) {
7248 m = m_dup(*m_head, M_NOWAIT);
7251 sc->mbuf_alloc_failed_count++;
7259 * For TSO the controller needs two pieces of info,
7260 * the MSS and the IP+TCP options length.
7262 m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip));
7267 eh = mtod(m, struct ether_header *);
7268 etype = ntohs(eh->ether_type);
7270 /* Check for supported TSO Ethernet types (only IPv4 for now) */
7273 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7274 /* TSO only supported for TCP protocol. */
7275 if (ip->ip_p != IPPROTO_TCP) {
7276 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n",
7277 __FILE__, __LINE__);
7283 /* Get IP header length in bytes (min 20) */
7284 ip_hlen = ip->ip_hl << 2;
7285 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen +
7286 sizeof(struct tcphdr));
7292 /* Get the TCP header length in bytes (min 20) */
7293 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7294 th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
7295 tcp_hlen = (th->th_off << 2);
7297 /* Make sure all IP/TCP options live in the same buffer. */
7298 m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen +
7305 /* Clear IP header length and checksum, will be calc'd by h/w. */
7306 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7307 ip_len = ip->ip_len;
7311 case ETHERTYPE_IPV6:
7312 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n",
7313 __FILE__, __LINE__);
7319 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n",
7320 __FILE__, __LINE__);
7326 hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen;
7328 DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, "
7329 "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n",
7330 __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen,
7333 /* Set the LSO flag in the TX BD */
7334 *flags |= TX_BD_FLAGS_SW_LSO;
7336 /* Set the length of IP + TCP options (in 32 bit words) */
7337 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) -
7338 sizeof(struct tcphdr)) >> 2) << 8);
7340 DBRUN(sc->tso_frames_completed++);
7345 /****************************************************************************/
7346 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
7347 /* memory visible to the controller. */
7350 /* 0 for success, positive value for failure. */
7352 /* m_head: May be set to NULL if MBUF is excessively fragmented. */
7353 /****************************************************************************/
7355 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head)
7357 bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
7359 struct tx_bd *txbd = NULL;
7361 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0;
7368 int i, error, nsegs, rc = 0;
7370 DBENTER(BCE_VERBOSE_SEND);
7372 /* Make sure we have room in the TX chain. */
7373 if (sc->used_tx_bd >= sc->max_tx_bd)
7374 goto bce_tx_encap_exit;
7376 /* Transfer any checksum offload flags to the bd. */
7378 if (m0->m_pkthdr.csum_flags) {
7379 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
7380 m0 = bce_tso_setup(sc, m_head, &flags);
7382 DBRUN(sc->tso_frames_failed++);
7383 goto bce_tx_encap_exit;
7385 mss = htole16(m0->m_pkthdr.tso_segsz);
7387 if (m0->m_pkthdr.csum_flags & CSUM_IP)
7388 flags |= TX_BD_FLAGS_IP_CKSUM;
7389 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
7390 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
7394 /* Transfer any VLAN tags to the bd. */
7395 if (m0->m_flags & M_VLANTAG) {
7396 flags |= TX_BD_FLAGS_VLAN_TAG;
7397 vlan_tag = m0->m_pkthdr.ether_vtag;
7400 /* Map the mbuf into DMAable memory. */
7402 chain_prod = TX_CHAIN_IDX(prod);
7403 map = sc->tx_mbuf_map[chain_prod];
7405 /* Map the mbuf into our DMA address space. */
7406 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
7407 segs, &nsegs, BUS_DMA_NOWAIT);
7409 /* Check if the DMA mapping was successful */
7410 if (error == EFBIG) {
7411 sc->mbuf_frag_count++;
7413 /* Try to defrag the mbuf. */
7414 m0 = m_collapse(*m_head, M_NOWAIT, BCE_MAX_SEGMENTS);
7416 /* Defrag was unsuccessful */
7419 sc->mbuf_alloc_failed_count++;
7421 goto bce_tx_encap_exit;
7424 /* Defrag was successful, try mapping again */
7426 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag,
7427 map, m0, segs, &nsegs, BUS_DMA_NOWAIT);
7429 /* Still getting an error after a defrag. */
7430 if (error == ENOMEM) {
7431 /* Insufficient DMA buffers available. */
7432 sc->dma_map_addr_tx_failed_count++;
7434 goto bce_tx_encap_exit;
7435 } else if (error != 0) {
7436 /* Release it and return an error. */
7437 BCE_PRINTF("%s(%d): Unknown error mapping mbuf into "
7438 "TX chain!\n", __FILE__, __LINE__);
7441 sc->dma_map_addr_tx_failed_count++;
7443 goto bce_tx_encap_exit;
7445 } else if (error == ENOMEM) {
7446 /* Insufficient DMA buffers available. */
7447 sc->dma_map_addr_tx_failed_count++;
7449 goto bce_tx_encap_exit;
7450 } else if (error != 0) {
7453 sc->dma_map_addr_tx_failed_count++;
7455 goto bce_tx_encap_exit;
7458 /* Make sure there's room in the chain */
7459 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) {
7460 bus_dmamap_unload(sc->tx_mbuf_tag, map);
7462 goto bce_tx_encap_exit;
7465 /* prod points to an empty tx_bd at this point. */
7466 prod_bseq = sc->tx_prod_bseq;
7469 debug_prod = chain_prod;
7472 DBPRINT(sc, BCE_INFO_SEND,
7473 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, "
7474 "prod_bseq = 0x%08X\n",
7475 __FUNCTION__, prod, chain_prod, prod_bseq);
7478 * Cycle through each mbuf segment that makes up
7479 * the outgoing frame, gathering the mapping info
7480 * for that segment and creating a tx_bd for
7483 for (i = 0; i < nsegs ; i++) {
7485 chain_prod = TX_CHAIN_IDX(prod);
7486 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)]
7487 [TX_IDX(chain_prod)];
7489 txbd->tx_bd_haddr_lo =
7490 htole32(BCE_ADDR_LO(segs[i].ds_addr));
7491 txbd->tx_bd_haddr_hi =
7492 htole32(BCE_ADDR_HI(segs[i].ds_addr));
7493 txbd->tx_bd_mss_nbytes = htole32(mss << 16) |
7494 htole16(segs[i].ds_len);
7495 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
7496 txbd->tx_bd_flags = htole16(flags);
7497 prod_bseq += segs[i].ds_len;
7499 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
7500 prod = NEXT_TX_BD(prod);
7503 /* Set the END flag on the last TX buffer descriptor. */
7504 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
7506 DBRUNMSG(BCE_EXTREME_SEND,
7507 bce_dump_tx_chain(sc, debug_prod, nsegs));
7510 * Ensure that the mbuf pointer for this transmission
7511 * is placed at the array index of the last
7512 * descriptor in this chain. This is done
7513 * because a single map is used for all
7514 * segments of the mbuf and we don't want to
7515 * unload the map before all of the segments
7518 sc->tx_mbuf_ptr[chain_prod] = m0;
7519 sc->used_tx_bd += nsegs;
7521 /* Update some debug statistic counters */
7522 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
7523 sc->tx_hi_watermark = sc->used_tx_bd);
7524 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
7525 DBRUNIF(sc->debug_tx_mbuf_alloc++);
7527 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1));
7529 /* prod points to the next free tx_bd at this point. */
7531 sc->tx_prod_bseq = prod_bseq;
7533 /* Tell the chip about the waiting TX frames. */
7534 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) +
7535 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod);
7536 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) +
7537 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq);
7540 DBEXIT(BCE_VERBOSE_SEND);
7545 /****************************************************************************/
7546 /* Main transmit routine when called from another routine with a lock. */
7550 /****************************************************************************/
7552 bce_start_locked(struct ifnet *ifp)
7554 struct bce_softc *sc = ifp->if_softc;
7555 struct mbuf *m_head = NULL;
7557 u16 tx_prod, tx_chain_prod;
7559 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7561 BCE_LOCK_ASSERT(sc);
7563 /* prod points to the next free tx_bd. */
7564 tx_prod = sc->tx_prod;
7565 tx_chain_prod = TX_CHAIN_IDX(tx_prod);
7567 DBPRINT(sc, BCE_INFO_SEND,
7568 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
7569 "tx_prod_bseq = 0x%08X\n",
7570 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq);
7572 /* If there's no link or the transmit queue is empty then just exit. */
7573 if (sc->bce_link_up == FALSE) {
7574 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n",
7576 goto bce_start_locked_exit;
7579 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
7580 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n",
7582 goto bce_start_locked_exit;
7586 * Keep adding entries while there is space in the ring.
7588 while (sc->used_tx_bd < sc->max_tx_bd) {
7590 /* Check for any frames to send. */
7591 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
7593 /* Stop when the transmit queue is empty. */
7598 * Pack the data into the transmit ring. If we
7599 * don't have room, place the mbuf back at the
7600 * head of the queue and set the OACTIVE flag
7601 * to wait for the NIC to drain the chain.
7603 if (bce_tx_encap(sc, &m_head)) {
7605 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
7606 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
7607 DBPRINT(sc, BCE_INFO_SEND,
7608 "TX chain is closed for business! Total "
7609 "tx_bd used = %d\n", sc->used_tx_bd);
7615 /* Send a copy of the frame to any BPF listeners. */
7616 ETHER_BPF_MTAP(ifp, m_head);
7619 /* Exit if no packets were dequeued. */
7621 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were "
7622 "dequeued\n", __FUNCTION__);
7623 goto bce_start_locked_exit;
7626 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into "
7627 "send queue.\n", __FUNCTION__, count);
7629 /* Set the tx timeout. */
7630 sc->watchdog_timer = BCE_TX_TIMEOUT;
7632 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID));
7633 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc));
7635 bce_start_locked_exit:
7636 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7640 /****************************************************************************/
7641 /* Main transmit routine when called from another routine without a lock. */
7645 /****************************************************************************/
7647 bce_start(struct ifnet *ifp)
7649 struct bce_softc *sc = ifp->if_softc;
7651 DBENTER(BCE_VERBOSE_SEND);
7654 bce_start_locked(ifp);
7657 DBEXIT(BCE_VERBOSE_SEND);
7661 /****************************************************************************/
7662 /* Handles any IOCTL calls from the operating system. */
7665 /* 0 for success, positive value for failure. */
7666 /****************************************************************************/
7668 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
7670 struct bce_softc *sc = ifp->if_softc;
7671 struct ifreq *ifr = (struct ifreq *) data;
7672 struct mii_data *mii;
7673 int mask, error = 0;
7675 DBENTER(BCE_VERBOSE_MISC);
7679 /* Set the interface MTU. */
7681 /* Check that the MTU setting is supported. */
7682 if ((ifr->ifr_mtu < BCE_MIN_MTU) ||
7683 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) {
7688 DBPRINT(sc, BCE_INFO_MISC,
7689 "SIOCSIFMTU: Changing MTU from %d to %d\n",
7690 (int) ifp->if_mtu, (int) ifr->ifr_mtu);
7693 ifp->if_mtu = ifr->ifr_mtu;
7694 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7695 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
7696 bce_init_locked(sc);
7701 /* Set interface flags. */
7703 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n");
7707 /* Check if the interface is up. */
7708 if (ifp->if_flags & IFF_UP) {
7709 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7710 /* Change promiscuous/multicast flags as necessary. */
7711 bce_set_rx_mode(sc);
7714 bce_init_locked(sc);
7717 /* The interface is down, check if driver is running. */
7718 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7721 /* If MFW is running, restart the controller a bit. */
7722 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
7723 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
7725 bce_mgmt_init_locked(sc);
7733 /* Add/Delete multicast address */
7736 DBPRINT(sc, BCE_VERBOSE_MISC,
7737 "Received SIOCADDMULTI/SIOCDELMULTI\n");
7740 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
7741 bce_set_rx_mode(sc);
7746 /* Set/Get Interface media */
7749 DBPRINT(sc, BCE_VERBOSE_MISC,
7750 "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n");
7751 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
7752 error = ifmedia_ioctl(ifp, ifr, &sc->bce_ifmedia,
7755 mii = device_get_softc(sc->bce_miibus);
7756 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
7761 /* Set interface capability */
7763 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
7764 DBPRINT(sc, BCE_INFO_MISC,
7765 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask);
7767 /* Toggle the TX checksum capabilities enable flag. */
7768 if (mask & IFCAP_TXCSUM &&
7769 ifp->if_capabilities & IFCAP_TXCSUM) {
7770 ifp->if_capenable ^= IFCAP_TXCSUM;
7771 if (IFCAP_TXCSUM & ifp->if_capenable)
7772 ifp->if_hwassist |= BCE_IF_HWASSIST;
7774 ifp->if_hwassist &= ~BCE_IF_HWASSIST;
7777 /* Toggle the RX checksum capabilities enable flag. */
7778 if (mask & IFCAP_RXCSUM &&
7779 ifp->if_capabilities & IFCAP_RXCSUM)
7780 ifp->if_capenable ^= IFCAP_RXCSUM;
7782 /* Toggle the TSO capabilities enable flag. */
7783 if (bce_tso_enable && (mask & IFCAP_TSO4) &&
7784 ifp->if_capabilities & IFCAP_TSO4) {
7785 ifp->if_capenable ^= IFCAP_TSO4;
7786 if (IFCAP_TSO4 & ifp->if_capenable)
7787 ifp->if_hwassist |= CSUM_TSO;
7789 ifp->if_hwassist &= ~CSUM_TSO;
7792 if (mask & IFCAP_VLAN_HWCSUM &&
7793 ifp->if_capabilities & IFCAP_VLAN_HWCSUM)
7794 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
7796 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
7797 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
7798 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
7800 * Don't actually disable VLAN tag stripping as
7801 * management firmware (ASF/IPMI/UMP) requires the
7802 * feature. If VLAN tag stripping is disabled driver
7803 * will manually reconstruct the VLAN frame by
7804 * appending stripped VLAN tag.
7806 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
7807 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) {
7808 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
7809 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
7811 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
7813 VLAN_CAPABILITIES(ifp);
7816 /* We don't know how to handle the IOCTL, pass it on. */
7817 error = ether_ioctl(ifp, command, data);
7821 DBEXIT(BCE_VERBOSE_MISC);
7826 /****************************************************************************/
7827 /* Transmit timeout handler. */
7831 /****************************************************************************/
7833 bce_watchdog(struct bce_softc *sc)
7837 DBENTER(BCE_EXTREME_SEND);
7839 BCE_LOCK_ASSERT(sc);
7842 /* If the watchdog timer hasn't expired then just exit. */
7843 if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
7844 goto bce_watchdog_exit;
7846 status = REG_RD(sc, BCE_EMAC_RX_STATUS);
7847 /* If pause frames are active then don't reset the hardware. */
7848 if ((sc->bce_flags & BCE_USING_RX_FLOW_CONTROL) != 0) {
7849 if ((status & BCE_EMAC_RX_STATUS_FFED) != 0) {
7851 * If link partner has us in XOFF state then wait for
7852 * the condition to clear.
7854 sc->watchdog_timer = BCE_TX_TIMEOUT;
7855 goto bce_watchdog_exit;
7856 } else if ((status & BCE_EMAC_RX_STATUS_FF_RECEIVED) != 0 &&
7857 (status & BCE_EMAC_RX_STATUS_N_RECEIVED) != 0) {
7859 * If we're not currently XOFF'ed but have recently
7860 * been XOFF'd/XON'd then assume that's delaying TX
7863 sc->watchdog_timer = BCE_TX_TIMEOUT;
7864 goto bce_watchdog_exit;
7867 * Any other condition is unexpected and the controller
7872 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n",
7873 __FILE__, __LINE__);
7876 bce_dump_driver_state(sc);
7877 bce_dump_status_block(sc);
7878 bce_dump_stats_block(sc);
7880 bce_dump_txp_state(sc, 0);
7881 bce_dump_rxp_state(sc, 0);
7882 bce_dump_tpat_state(sc, 0);
7883 bce_dump_cp_state(sc, 0);
7884 bce_dump_com_state(sc, 0));
7886 DBRUN(bce_breakpoint(sc));
7888 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
7890 bce_init_locked(sc);
7891 sc->bce_ifp->if_oerrors++;
7894 REG_WR(sc, BCE_EMAC_RX_STATUS, status);
7895 DBEXIT(BCE_EXTREME_SEND);
7900 * Interrupt handler.
7902 /****************************************************************************/
7903 /* Main interrupt entry point. Verifies that the controller generated the */
7904 /* interrupt and then calls a separate routine for handle the various */
7905 /* interrupt causes (PHY, TX, RX). */
7909 /****************************************************************************/
7913 struct bce_softc *sc;
7915 u32 status_attn_bits;
7916 u16 hw_rx_cons, hw_tx_cons;
7921 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
7922 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
7923 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc));
7927 DBRUN(sc->interrupts_generated++);
7929 /* Synchnorize before we read from interface's status block */
7930 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
7933 * If the hardware status block index matches the last value read
7934 * by the driver and we haven't asserted our interrupt then there's
7935 * nothing to do. This may only happen in case of INTx due to the
7936 * interrupt arriving at the CPU before the status block is updated.
7938 if ((sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) == 0 &&
7939 sc->status_block->status_idx == sc->last_status_idx &&
7940 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
7941 BCE_PCICFG_MISC_STATUS_INTA_VALUE)) {
7942 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n",
7947 /* Ack the interrupt and stop others from occuring. */
7948 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7949 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
7950 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
7952 /* Check if the hardware has finished any work. */
7953 hw_rx_cons = bce_get_hw_rx_cons(sc);
7954 hw_tx_cons = bce_get_hw_tx_cons(sc);
7956 /* Keep processing data as long as there is work to do. */
7959 status_attn_bits = sc->status_block->status_attn_bits;
7961 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control),
7962 BCE_PRINTF("Simulating unexpected status attention "
7964 sc->unexpected_attention_sim_count++;
7965 status_attn_bits = status_attn_bits |
7966 STATUS_ATTN_BITS_PARITY_ERROR);
7968 /* Was it a link change interrupt? */
7969 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
7970 (sc->status_block->status_attn_bits_ack &
7971 STATUS_ATTN_BITS_LINK_STATE)) {
7974 /* Clear transient updates during link state change. */
7975 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command |
7976 BCE_HC_COMMAND_COAL_NOW_WO_INT);
7977 REG_RD(sc, BCE_HC_COMMAND);
7980 /* If any other attention is asserted, the chip is toast. */
7981 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
7982 (sc->status_block->status_attn_bits_ack &
7983 ~STATUS_ATTN_BITS_LINK_STATE))) {
7985 sc->unexpected_attention_count++;
7987 BCE_PRINTF("%s(%d): Fatal attention detected: "
7988 "0x%08X\n", __FILE__, __LINE__,
7989 sc->status_block->status_attn_bits);
7992 if (unexpected_attention_sim_control == 0)
7993 bce_breakpoint(sc));
7995 bce_init_locked(sc);
7999 /* Check for any completed RX frames. */
8000 if (hw_rx_cons != sc->hw_rx_cons)
8003 /* Check for any completed TX frames. */
8004 if (hw_tx_cons != sc->hw_tx_cons)
8007 /* Save status block index value for the next interrupt. */
8008 sc->last_status_idx = sc->status_block->status_idx;
8011 * Prevent speculative reads from getting
8012 * ahead of the status block.
8014 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
8015 BUS_SPACE_BARRIER_READ);
8018 * If there's no work left then exit the
8019 * interrupt service routine.
8021 hw_rx_cons = bce_get_hw_rx_cons(sc);
8022 hw_tx_cons = bce_get_hw_tx_cons(sc);
8024 if ((hw_rx_cons == sc->hw_rx_cons) &&
8025 (hw_tx_cons == sc->hw_tx_cons))
8029 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREREAD);
8031 /* Re-enable interrupts. */
8032 bce_enable_intr(sc, 0);
8034 /* Handle any frames that arrived while handling the interrupt. */
8035 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
8036 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
8037 bce_start_locked(ifp);
8042 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
8046 /****************************************************************************/
8047 /* Programs the various packet receive modes (broadcast and multicast). */
8051 /****************************************************************************/
8053 bce_set_rx_mode(struct bce_softc *sc)
8056 struct ifmultiaddr *ifma;
8057 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
8058 u32 rx_mode, sort_mode;
8061 DBENTER(BCE_VERBOSE_MISC);
8063 BCE_LOCK_ASSERT(sc);
8067 /* Initialize receive mode default settings. */
8068 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
8069 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
8070 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
8073 * ASF/IPMI/UMP firmware requires that VLAN tag stripping
8076 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
8077 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)))
8078 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
8081 * Check for promiscuous, all multicast, or selected
8082 * multicast address filtering.
8084 if (ifp->if_flags & IFF_PROMISC) {
8085 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n");
8087 /* Enable promiscuous mode. */
8088 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
8089 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
8090 } else if (ifp->if_flags & IFF_ALLMULTI) {
8091 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n");
8093 /* Enable all multicast addresses. */
8094 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
8095 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
8098 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
8100 /* Accept one or more multicast(s). */
8101 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n");
8103 if_maddr_rlock(ifp);
8104 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
8105 if (ifma->ifma_addr->sa_family != AF_LINK)
8107 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
8108 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF;
8109 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
8111 if_maddr_runlock(ifp);
8113 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++)
8114 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]);
8116 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
8119 /* Only make changes if the recive mode has actually changed. */
8120 if (rx_mode != sc->rx_mode) {
8121 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: "
8122 "0x%08X\n", rx_mode);
8124 sc->rx_mode = rx_mode;
8125 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
8128 /* Disable and clear the exisitng sort before enabling a new sort. */
8129 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
8130 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
8131 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
8133 DBEXIT(BCE_VERBOSE_MISC);
8137 /****************************************************************************/
8138 /* Called periodically to updates statistics from the controllers */
8139 /* statistics block. */
8143 /****************************************************************************/
8145 bce_stats_update(struct bce_softc *sc)
8148 struct statistics_block *stats;
8150 DBENTER(BCE_EXTREME_MISC);
8154 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD);
8156 stats = (struct statistics_block *) sc->stats_block;
8159 * Certain controllers don't report
8160 * carrier sense errors correctly.
8161 * See errata E11_5708CA0_1165.
8163 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
8164 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0))
8166 (u_long) stats->stat_Dot3StatsCarrierSenseErrors;
8169 * Update the sysctl statistics from the
8170 * hardware statistics.
8172 sc->stat_IfHCInOctets =
8173 ((u64) stats->stat_IfHCInOctets_hi << 32) +
8174 (u64) stats->stat_IfHCInOctets_lo;
8176 sc->stat_IfHCInBadOctets =
8177 ((u64) stats->stat_IfHCInBadOctets_hi << 32) +
8178 (u64) stats->stat_IfHCInBadOctets_lo;
8180 sc->stat_IfHCOutOctets =
8181 ((u64) stats->stat_IfHCOutOctets_hi << 32) +
8182 (u64) stats->stat_IfHCOutOctets_lo;
8184 sc->stat_IfHCOutBadOctets =
8185 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) +
8186 (u64) stats->stat_IfHCOutBadOctets_lo;
8188 sc->stat_IfHCInUcastPkts =
8189 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) +
8190 (u64) stats->stat_IfHCInUcastPkts_lo;
8192 sc->stat_IfHCInMulticastPkts =
8193 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) +
8194 (u64) stats->stat_IfHCInMulticastPkts_lo;
8196 sc->stat_IfHCInBroadcastPkts =
8197 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) +
8198 (u64) stats->stat_IfHCInBroadcastPkts_lo;
8200 sc->stat_IfHCOutUcastPkts =
8201 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) +
8202 (u64) stats->stat_IfHCOutUcastPkts_lo;
8204 sc->stat_IfHCOutMulticastPkts =
8205 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) +
8206 (u64) stats->stat_IfHCOutMulticastPkts_lo;
8208 sc->stat_IfHCOutBroadcastPkts =
8209 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) +
8210 (u64) stats->stat_IfHCOutBroadcastPkts_lo;
8212 /* ToDo: Preserve counters beyond 32 bits? */
8213 /* ToDo: Read the statistics from auto-clear regs? */
8215 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
8216 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
8218 sc->stat_Dot3StatsCarrierSenseErrors =
8219 stats->stat_Dot3StatsCarrierSenseErrors;
8221 sc->stat_Dot3StatsFCSErrors =
8222 stats->stat_Dot3StatsFCSErrors;
8224 sc->stat_Dot3StatsAlignmentErrors =
8225 stats->stat_Dot3StatsAlignmentErrors;
8227 sc->stat_Dot3StatsSingleCollisionFrames =
8228 stats->stat_Dot3StatsSingleCollisionFrames;
8230 sc->stat_Dot3StatsMultipleCollisionFrames =
8231 stats->stat_Dot3StatsMultipleCollisionFrames;
8233 sc->stat_Dot3StatsDeferredTransmissions =
8234 stats->stat_Dot3StatsDeferredTransmissions;
8236 sc->stat_Dot3StatsExcessiveCollisions =
8237 stats->stat_Dot3StatsExcessiveCollisions;
8239 sc->stat_Dot3StatsLateCollisions =
8240 stats->stat_Dot3StatsLateCollisions;
8242 sc->stat_EtherStatsCollisions =
8243 stats->stat_EtherStatsCollisions;
8245 sc->stat_EtherStatsFragments =
8246 stats->stat_EtherStatsFragments;
8248 sc->stat_EtherStatsJabbers =
8249 stats->stat_EtherStatsJabbers;
8251 sc->stat_EtherStatsUndersizePkts =
8252 stats->stat_EtherStatsUndersizePkts;
8254 sc->stat_EtherStatsOversizePkts =
8255 stats->stat_EtherStatsOversizePkts;
8257 sc->stat_EtherStatsPktsRx64Octets =
8258 stats->stat_EtherStatsPktsRx64Octets;
8260 sc->stat_EtherStatsPktsRx65Octetsto127Octets =
8261 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
8263 sc->stat_EtherStatsPktsRx128Octetsto255Octets =
8264 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
8266 sc->stat_EtherStatsPktsRx256Octetsto511Octets =
8267 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
8269 sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
8270 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
8272 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
8273 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
8275 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
8276 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
8278 sc->stat_EtherStatsPktsTx64Octets =
8279 stats->stat_EtherStatsPktsTx64Octets;
8281 sc->stat_EtherStatsPktsTx65Octetsto127Octets =
8282 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
8284 sc->stat_EtherStatsPktsTx128Octetsto255Octets =
8285 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
8287 sc->stat_EtherStatsPktsTx256Octetsto511Octets =
8288 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
8290 sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
8291 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
8293 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
8294 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
8296 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
8297 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
8299 sc->stat_XonPauseFramesReceived =
8300 stats->stat_XonPauseFramesReceived;
8302 sc->stat_XoffPauseFramesReceived =
8303 stats->stat_XoffPauseFramesReceived;
8305 sc->stat_OutXonSent =
8306 stats->stat_OutXonSent;
8308 sc->stat_OutXoffSent =
8309 stats->stat_OutXoffSent;
8311 sc->stat_FlowControlDone =
8312 stats->stat_FlowControlDone;
8314 sc->stat_MacControlFramesReceived =
8315 stats->stat_MacControlFramesReceived;
8317 sc->stat_XoffStateEntered =
8318 stats->stat_XoffStateEntered;
8320 sc->stat_IfInFramesL2FilterDiscards =
8321 stats->stat_IfInFramesL2FilterDiscards;
8323 sc->stat_IfInRuleCheckerDiscards =
8324 stats->stat_IfInRuleCheckerDiscards;
8326 sc->stat_IfInFTQDiscards =
8327 stats->stat_IfInFTQDiscards;
8329 sc->stat_IfInMBUFDiscards =
8330 stats->stat_IfInMBUFDiscards;
8332 sc->stat_IfInRuleCheckerP4Hit =
8333 stats->stat_IfInRuleCheckerP4Hit;
8335 sc->stat_CatchupInRuleCheckerDiscards =
8336 stats->stat_CatchupInRuleCheckerDiscards;
8338 sc->stat_CatchupInFTQDiscards =
8339 stats->stat_CatchupInFTQDiscards;
8341 sc->stat_CatchupInMBUFDiscards =
8342 stats->stat_CatchupInMBUFDiscards;
8344 sc->stat_CatchupInRuleCheckerP4Hit =
8345 stats->stat_CatchupInRuleCheckerP4Hit;
8347 sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
8350 * Update the interface statistics from the
8351 * hardware statistics.
8353 ifp->if_collisions =
8354 (u_long) sc->stat_EtherStatsCollisions;
8356 /* ToDo: This method loses soft errors. */
8358 (u_long) sc->stat_EtherStatsUndersizePkts +
8359 (u_long) sc->stat_EtherStatsOversizePkts +
8360 (u_long) sc->stat_IfInMBUFDiscards +
8361 (u_long) sc->stat_Dot3StatsAlignmentErrors +
8362 (u_long) sc->stat_Dot3StatsFCSErrors +
8363 (u_long) sc->stat_IfInRuleCheckerDiscards +
8364 (u_long) sc->stat_IfInFTQDiscards +
8365 (u_long) sc->com_no_buffers;
8367 /* ToDo: This method loses soft errors. */
8369 (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
8370 (u_long) sc->stat_Dot3StatsExcessiveCollisions +
8371 (u_long) sc->stat_Dot3StatsLateCollisions;
8373 /* ToDo: Add additional statistics? */
8375 DBEXIT(BCE_EXTREME_MISC);
8379 /****************************************************************************/
8380 /* Periodic function to notify the bootcode that the driver is still */
8385 /****************************************************************************/
8387 bce_pulse(void *xsc)
8389 struct bce_softc *sc = xsc;
8392 DBENTER(BCE_EXTREME_MISC);
8394 BCE_LOCK_ASSERT(sc);
8396 /* Tell the firmware that the driver is still running. */
8397 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq;
8398 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
8400 /* Update the bootcode condition. */
8401 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
8403 /* Report whether the bootcode still knows the driver is running. */
8404 if (bce_verbose || bootverbose) {
8405 if (sc->bce_drv_cardiac_arrest == FALSE) {
8406 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
8407 sc->bce_drv_cardiac_arrest = TRUE;
8408 BCE_PRINTF("%s(): Warning: bootcode "
8409 "thinks driver is absent! "
8410 "(bc_state = 0x%08X)\n",
8411 __FUNCTION__, sc->bc_state);
8415 * Not supported by all bootcode versions.
8416 * (v5.0.11+ and v5.2.1+) Older bootcode
8417 * will require the driver to reset the
8418 * controller to clear this condition.
8420 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
8421 sc->bce_drv_cardiac_arrest = FALSE;
8422 BCE_PRINTF("%s(): Bootcode found the "
8423 "driver pulse! (bc_state = 0x%08X)\n",
8424 __FUNCTION__, sc->bc_state);
8430 /* Schedule the next pulse. */
8431 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
8433 DBEXIT(BCE_EXTREME_MISC);
8437 /****************************************************************************/
8438 /* Periodic function to perform maintenance tasks. */
8442 /****************************************************************************/
8446 struct bce_softc *sc = xsc;
8447 struct mii_data *mii;
8449 struct ifmediareq ifmr;
8453 DBENTER(BCE_EXTREME_MISC);
8455 BCE_LOCK_ASSERT(sc);
8457 /* Schedule the next tick. */
8458 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
8460 /* Update the statistics from the hardware statistics block. */
8461 bce_stats_update(sc);
8463 /* Ensure page and RX chains get refilled in low-memory situations. */
8464 if (bce_hdr_split == TRUE)
8465 bce_fill_pg_chain(sc);
8466 bce_fill_rx_chain(sc);
8468 /* Check that chip hasn't hung. */
8471 /* If link is up already up then we're done. */
8472 if (sc->bce_link_up == TRUE)
8475 /* Link is down. Check what the PHY's doing. */
8476 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
8477 bzero(&ifmr, sizeof(ifmr));
8478 bce_ifmedia_sts_rphy(sc, &ifmr);
8479 if ((ifmr.ifm_status & (IFM_ACTIVE | IFM_AVALID)) ==
8480 (IFM_ACTIVE | IFM_AVALID)) {
8481 sc->bce_link_up = TRUE;
8482 bce_miibus_statchg(sc->bce_dev);
8485 mii = device_get_softc(sc->bce_miibus);
8487 /* Check if the link has come up. */
8488 if ((mii->mii_media_status & IFM_ACTIVE) &&
8489 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) {
8490 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n",
8492 sc->bce_link_up = TRUE;
8493 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
8494 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX ||
8495 IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) &&
8496 (bce_verbose || bootverbose))
8497 BCE_PRINTF("Gigabit link up!\n");
8501 if (sc->bce_link_up == TRUE) {
8502 /* Now that link is up, handle any outstanding TX traffic. */
8503 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
8504 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found "
8505 "pending TX traffic.\n", __FUNCTION__);
8506 bce_start_locked(ifp);
8511 DBEXIT(BCE_EXTREME_MISC);
8515 bce_fw_cap_init(struct bce_softc *sc)
8520 cap = bce_shmem_rd(sc, BCE_FW_CAP_MB);
8521 if ((cap & BCE_FW_CAP_SIGNATURE_MAGIC_MASK) !=
8522 BCE_FW_CAP_SIGNATURE_MAGIC)
8524 if ((cap & (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) ==
8525 (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN))
8526 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC |
8527 BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN;
8528 if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 &&
8529 (cap & BCE_FW_CAP_REMOTE_PHY_CAP) != 0) {
8530 sc->bce_phy_flags &= ~BCE_PHY_REMOTE_PORT_FIBER_FLAG;
8531 sc->bce_phy_flags |= BCE_PHY_REMOTE_CAP_FLAG;
8532 link = bce_shmem_rd(sc, BCE_LINK_STATUS);
8533 if ((link & BCE_LINK_STATUS_SERDES_LINK) != 0)
8534 sc->bce_phy_flags |= BCE_PHY_REMOTE_PORT_FIBER_FLAG;
8535 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC |
8536 BCE_FW_CAP_REMOTE_PHY_CAP;
8540 bce_shmem_wr(sc, BCE_DRV_ACK_CAP_MB, ack);
8545 /****************************************************************************/
8546 /* Allows the driver state to be dumped through the sysctl interface. */
8549 /* 0 for success, positive value for failure. */
8550 /****************************************************************************/
8552 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
8556 struct bce_softc *sc;
8559 error = sysctl_handle_int(oidp, &result, 0, req);
8561 if (error || !req->newptr)
8565 sc = (struct bce_softc *)arg1;
8566 bce_dump_driver_state(sc);
8573 /****************************************************************************/
8574 /* Allows the hardware state to be dumped through the sysctl interface. */
8577 /* 0 for success, positive value for failure. */
8578 /****************************************************************************/
8580 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
8584 struct bce_softc *sc;
8587 error = sysctl_handle_int(oidp, &result, 0, req);
8589 if (error || !req->newptr)
8593 sc = (struct bce_softc *)arg1;
8594 bce_dump_hw_state(sc);
8601 /****************************************************************************/
8602 /* Allows the status block to be dumped through the sysctl interface. */
8605 /* 0 for success, positive value for failure. */
8606 /****************************************************************************/
8608 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS)
8612 struct bce_softc *sc;
8615 error = sysctl_handle_int(oidp, &result, 0, req);
8617 if (error || !req->newptr)
8621 sc = (struct bce_softc *)arg1;
8622 bce_dump_status_block(sc);
8629 /****************************************************************************/
8630 /* Allows the stats block to be dumped through the sysctl interface. */
8633 /* 0 for success, positive value for failure. */
8634 /****************************************************************************/
8636 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS)
8640 struct bce_softc *sc;
8643 error = sysctl_handle_int(oidp, &result, 0, req);
8645 if (error || !req->newptr)
8649 sc = (struct bce_softc *)arg1;
8650 bce_dump_stats_block(sc);
8657 /****************************************************************************/
8658 /* Allows the stat counters to be cleared without unloading/reloading the */
8662 /* 0 for success, positive value for failure. */
8663 /****************************************************************************/
8665 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS)
8669 struct bce_softc *sc;
8672 error = sysctl_handle_int(oidp, &result, 0, req);
8674 if (error || !req->newptr)
8678 sc = (struct bce_softc *)arg1;
8679 struct statistics_block *stats;
8681 stats = (struct statistics_block *) sc->stats_block;
8682 bzero(stats, sizeof(struct statistics_block));
8683 bus_dmamap_sync(sc->stats_tag, sc->stats_map,
8684 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
8686 /* Clear the internal H/W statistics counters. */
8687 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
8689 /* Reset the driver maintained statistics. */
8691 sc->interrupts_tx = 0;
8692 sc->tso_frames_requested =
8693 sc->tso_frames_completed =
8694 sc->tso_frames_failed = 0;
8695 sc->rx_empty_count =
8696 sc->tx_full_count = 0;
8697 sc->rx_low_watermark = USABLE_RX_BD_ALLOC;
8698 sc->tx_hi_watermark = 0;
8699 sc->l2fhdr_error_count =
8700 sc->l2fhdr_error_sim_count = 0;
8701 sc->mbuf_alloc_failed_count =
8702 sc->mbuf_alloc_failed_sim_count = 0;
8703 sc->dma_map_addr_rx_failed_count =
8704 sc->dma_map_addr_tx_failed_count = 0;
8705 sc->mbuf_frag_count = 0;
8706 sc->csum_offload_tcp_udp =
8707 sc->csum_offload_ip = 0;
8708 sc->vlan_tagged_frames_rcvd =
8709 sc->vlan_tagged_frames_stripped = 0;
8710 sc->split_header_frames_rcvd =
8711 sc->split_header_tcp_frames_rcvd = 0;
8713 /* Clear firmware maintained statistics. */
8714 REG_WR_IND(sc, 0x120084, 0);
8721 /****************************************************************************/
8722 /* Allows the shared memory contents to be dumped through the sysctl . */
8726 /* 0 for success, positive value for failure. */
8727 /****************************************************************************/
8729 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS)
8733 struct bce_softc *sc;
8736 error = sysctl_handle_int(oidp, &result, 0, req);
8738 if (error || !req->newptr)
8742 sc = (struct bce_softc *)arg1;
8743 bce_dump_shmem_state(sc);
8750 /****************************************************************************/
8751 /* Allows the bootcode state to be dumped through the sysctl interface. */
8754 /* 0 for success, positive value for failure. */
8755 /****************************************************************************/
8757 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS)
8761 struct bce_softc *sc;
8764 error = sysctl_handle_int(oidp, &result, 0, req);
8766 if (error || !req->newptr)
8770 sc = (struct bce_softc *)arg1;
8771 bce_dump_bc_state(sc);
8778 /****************************************************************************/
8779 /* Provides a sysctl interface to allow dumping the RX BD chain. */
8782 /* 0 for success, positive value for failure. */
8783 /****************************************************************************/
8785 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS)
8789 struct bce_softc *sc;
8792 error = sysctl_handle_int(oidp, &result, 0, req);
8794 if (error || !req->newptr)
8798 sc = (struct bce_softc *)arg1;
8799 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC);
8806 /****************************************************************************/
8807 /* Provides a sysctl interface to allow dumping the RX MBUF chain. */
8810 /* 0 for success, positive value for failure. */
8811 /****************************************************************************/
8813 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS)
8817 struct bce_softc *sc;
8820 error = sysctl_handle_int(oidp, &result, 0, req);
8822 if (error || !req->newptr)
8826 sc = (struct bce_softc *)arg1;
8827 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC);
8834 /****************************************************************************/
8835 /* Provides a sysctl interface to allow dumping the TX chain. */
8838 /* 0 for success, positive value for failure. */
8839 /****************************************************************************/
8841 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
8845 struct bce_softc *sc;
8848 error = sysctl_handle_int(oidp, &result, 0, req);
8850 if (error || !req->newptr)
8854 sc = (struct bce_softc *)arg1;
8855 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC);
8862 /****************************************************************************/
8863 /* Provides a sysctl interface to allow dumping the page chain. */
8866 /* 0 for success, positive value for failure. */
8867 /****************************************************************************/
8869 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS)
8873 struct bce_softc *sc;
8876 error = sysctl_handle_int(oidp, &result, 0, req);
8878 if (error || !req->newptr)
8882 sc = (struct bce_softc *)arg1;
8883 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC);
8889 /****************************************************************************/
8890 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */
8891 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
8894 /* 0 for success, positive value for failure. */
8895 /****************************************************************************/
8897 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS)
8899 struct bce_softc *sc = (struct bce_softc *)arg1;
8903 u8 *data = (u8 *) val;
8906 error = sysctl_handle_int(oidp, &result, 0, req);
8907 if (error || (req->newptr == NULL))
8910 error = bce_nvram_read(sc, result, data, 4);
8912 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0]));
8918 /****************************************************************************/
8919 /* Provides a sysctl interface to allow reading arbitrary registers in the */
8920 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
8923 /* 0 for success, positive value for failure. */
8924 /****************************************************************************/
8926 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
8928 struct bce_softc *sc = (struct bce_softc *)arg1;
8933 error = sysctl_handle_int(oidp, &result, 0, req);
8934 if (error || (req->newptr == NULL))
8937 /* Make sure the register is accessible. */
8938 if (result < 0x8000) {
8939 val = REG_RD(sc, result);
8940 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8941 } else if (result < 0x0280000) {
8942 val = REG_RD_IND(sc, result);
8943 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8950 /****************************************************************************/
8951 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */
8952 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
8955 /* 0 for success, positive value for failure. */
8956 /****************************************************************************/
8958 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
8960 struct bce_softc *sc;
8966 error = sysctl_handle_int(oidp, &result, 0, req);
8967 if (error || (req->newptr == NULL))
8970 /* Make sure the register is accessible. */
8971 if (result < 0x20) {
8972 sc = (struct bce_softc *)arg1;
8974 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
8975 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val);
8981 /****************************************************************************/
8982 /* Provides a sysctl interface for dumping the nvram contents. */
8983 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */
8986 /* 0 for success, positive errno for failure. */
8987 /****************************************************************************/
8989 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS)
8991 struct bce_softc *sc = (struct bce_softc *)arg1;
8994 if (sc->nvram_buf == NULL)
8995 sc->nvram_buf = malloc(sc->bce_flash_size,
8996 M_TEMP, M_ZERO | M_WAITOK);
8999 if (req->oldlen == sc->bce_flash_size) {
9000 for (i = 0; i < sc->bce_flash_size && error == 0; i++)
9001 error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1);
9005 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size);
9010 #ifdef BCE_NVRAM_WRITE_SUPPORT
9011 /****************************************************************************/
9012 /* Provides a sysctl interface for writing to nvram. */
9013 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */
9016 /* 0 for success, positive errno for failure. */
9017 /****************************************************************************/
9019 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS)
9021 struct bce_softc *sc = (struct bce_softc *)arg1;
9024 if (sc->nvram_buf == NULL)
9025 sc->nvram_buf = malloc(sc->bce_flash_size,
9026 M_TEMP, M_ZERO | M_WAITOK);
9028 bzero(sc->nvram_buf, sc->bce_flash_size);
9030 error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size);
9034 if (req->newlen == sc->bce_flash_size)
9035 error = bce_nvram_write(sc, 0, sc->nvram_buf,
9036 sc->bce_flash_size);
9044 /****************************************************************************/
9045 /* Provides a sysctl interface to allow reading a CID. */
9048 /* 0 for success, positive value for failure. */
9049 /****************************************************************************/
9051 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS)
9053 struct bce_softc *sc;
9057 error = sysctl_handle_int(oidp, &result, 0, req);
9058 if (error || (req->newptr == NULL))
9061 /* Make sure the register is accessible. */
9062 if (result <= TX_CID) {
9063 sc = (struct bce_softc *)arg1;
9064 bce_dump_ctx(sc, result);
9071 /****************************************************************************/
9072 /* Provides a sysctl interface to forcing the driver to dump state and */
9073 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
9076 /* 0 for success, positive value for failure. */
9077 /****************************************************************************/
9079 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
9083 struct bce_softc *sc;
9086 error = sysctl_handle_int(oidp, &result, 0, req);
9088 if (error || !req->newptr)
9092 sc = (struct bce_softc *)arg1;
9100 /****************************************************************************/
9101 /* Adds any sysctl parameters for tuning or debugging purposes. */
9104 /* 0 for success, positive value for failure. */
9105 /****************************************************************************/
9107 bce_add_sysctls(struct bce_softc *sc)
9109 struct sysctl_ctx_list *ctx;
9110 struct sysctl_oid_list *children;
9112 DBENTER(BCE_VERBOSE_MISC);
9114 ctx = device_get_sysctl_ctx(sc->bce_dev);
9115 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev));
9118 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9119 "l2fhdr_error_sim_control",
9120 CTLFLAG_RW, &l2fhdr_error_sim_control,
9121 0, "Debug control to force l2fhdr errors");
9123 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9124 "l2fhdr_error_sim_count",
9125 CTLFLAG_RD, &sc->l2fhdr_error_sim_count,
9126 0, "Number of simulated l2_fhdr errors");
9129 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9130 "l2fhdr_error_count",
9131 CTLFLAG_RD, &sc->l2fhdr_error_count,
9132 0, "Number of l2_fhdr errors");
9135 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9136 "mbuf_alloc_failed_sim_control",
9137 CTLFLAG_RW, &mbuf_alloc_failed_sim_control,
9138 0, "Debug control to force mbuf allocation failures");
9140 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9141 "mbuf_alloc_failed_sim_count",
9142 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count,
9143 0, "Number of simulated mbuf cluster allocation failures");
9146 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9147 "mbuf_alloc_failed_count",
9148 CTLFLAG_RD, &sc->mbuf_alloc_failed_count,
9149 0, "Number of mbuf allocation failures");
9151 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9153 CTLFLAG_RD, &sc->mbuf_frag_count,
9154 0, "Number of fragmented mbufs");
9157 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9158 "dma_map_addr_failed_sim_control",
9159 CTLFLAG_RW, &dma_map_addr_failed_sim_control,
9160 0, "Debug control to force DMA mapping failures");
9162 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */
9163 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9164 "dma_map_addr_failed_sim_count",
9165 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count,
9166 0, "Number of simulated DMA mapping failures");
9170 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9171 "dma_map_addr_rx_failed_count",
9172 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count,
9173 0, "Number of RX DMA mapping failures");
9175 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9176 "dma_map_addr_tx_failed_count",
9177 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count,
9178 0, "Number of TX DMA mapping failures");
9181 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9182 "unexpected_attention_sim_control",
9183 CTLFLAG_RW, &unexpected_attention_sim_control,
9184 0, "Debug control to simulate unexpected attentions");
9186 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9187 "unexpected_attention_sim_count",
9188 CTLFLAG_RW, &sc->unexpected_attention_sim_count,
9189 0, "Number of simulated unexpected attentions");
9192 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9193 "unexpected_attention_count",
9194 CTLFLAG_RW, &sc->unexpected_attention_count,
9195 0, "Number of unexpected attentions");
9198 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9199 "debug_bootcode_running_failure",
9200 CTLFLAG_RW, &bootcode_running_failure_sim_control,
9201 0, "Debug control to force bootcode running failures");
9203 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9205 CTLFLAG_RD, &sc->rx_low_watermark,
9206 0, "Lowest level of free rx_bd's");
9208 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9210 CTLFLAG_RD, &sc->rx_empty_count,
9211 "Number of times the RX chain was empty");
9213 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9215 CTLFLAG_RD, &sc->tx_hi_watermark,
9216 0, "Highest level of used tx_bd's");
9218 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9220 CTLFLAG_RD, &sc->tx_full_count,
9221 "Number of times the TX chain was full");
9223 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9224 "tso_frames_requested",
9225 CTLFLAG_RD, &sc->tso_frames_requested,
9226 "Number of TSO frames requested");
9228 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9229 "tso_frames_completed",
9230 CTLFLAG_RD, &sc->tso_frames_completed,
9231 "Number of TSO frames completed");
9233 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9234 "tso_frames_failed",
9235 CTLFLAG_RD, &sc->tso_frames_failed,
9236 "Number of TSO frames failed");
9238 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9240 CTLFLAG_RD, &sc->csum_offload_ip,
9241 "Number of IP checksum offload frames");
9243 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9244 "csum_offload_tcp_udp",
9245 CTLFLAG_RD, &sc->csum_offload_tcp_udp,
9246 "Number of TCP/UDP checksum offload frames");
9248 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9249 "vlan_tagged_frames_rcvd",
9250 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd,
9251 "Number of VLAN tagged frames received");
9253 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9254 "vlan_tagged_frames_stripped",
9255 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped,
9256 "Number of VLAN tagged frames stripped");
9258 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9260 CTLFLAG_RD, &sc->interrupts_rx,
9261 "Number of RX interrupts");
9263 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9265 CTLFLAG_RD, &sc->interrupts_tx,
9266 "Number of TX interrupts");
9268 if (bce_hdr_split == TRUE) {
9269 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9270 "split_header_frames_rcvd",
9271 CTLFLAG_RD, &sc->split_header_frames_rcvd,
9272 "Number of split header frames received");
9274 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9275 "split_header_tcp_frames_rcvd",
9276 CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd,
9277 "Number of split header TCP frames received");
9280 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9281 "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD,
9283 bce_sysctl_nvram_dump, "S", "");
9285 #ifdef BCE_NVRAM_WRITE_SUPPORT
9286 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9287 "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR,
9289 bce_sysctl_nvram_write, "S", "");
9291 #endif /* BCE_DEBUG */
9293 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9294 "stat_IfHcInOctets",
9295 CTLFLAG_RD, &sc->stat_IfHCInOctets,
9298 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9299 "stat_IfHCInBadOctets",
9300 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
9301 "Bad bytes received");
9303 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9304 "stat_IfHCOutOctets",
9305 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
9308 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9309 "stat_IfHCOutBadOctets",
9310 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
9313 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9314 "stat_IfHCInUcastPkts",
9315 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
9316 "Unicast packets received");
9318 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9319 "stat_IfHCInMulticastPkts",
9320 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
9321 "Multicast packets received");
9323 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9324 "stat_IfHCInBroadcastPkts",
9325 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
9326 "Broadcast packets received");
9328 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9329 "stat_IfHCOutUcastPkts",
9330 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
9331 "Unicast packets sent");
9333 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9334 "stat_IfHCOutMulticastPkts",
9335 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
9336 "Multicast packets sent");
9338 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9339 "stat_IfHCOutBroadcastPkts",
9340 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
9341 "Broadcast packets sent");
9343 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9344 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
9345 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
9346 0, "Internal MAC transmit errors");
9348 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9349 "stat_Dot3StatsCarrierSenseErrors",
9350 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
9351 0, "Carrier sense errors");
9353 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9354 "stat_Dot3StatsFCSErrors",
9355 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
9356 0, "Frame check sequence errors");
9358 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9359 "stat_Dot3StatsAlignmentErrors",
9360 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
9361 0, "Alignment errors");
9363 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9364 "stat_Dot3StatsSingleCollisionFrames",
9365 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
9366 0, "Single Collision Frames");
9368 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9369 "stat_Dot3StatsMultipleCollisionFrames",
9370 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
9371 0, "Multiple Collision Frames");
9373 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9374 "stat_Dot3StatsDeferredTransmissions",
9375 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
9376 0, "Deferred Transmissions");
9378 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9379 "stat_Dot3StatsExcessiveCollisions",
9380 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
9381 0, "Excessive Collisions");
9383 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9384 "stat_Dot3StatsLateCollisions",
9385 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
9386 0, "Late Collisions");
9388 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9389 "stat_EtherStatsCollisions",
9390 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
9393 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9394 "stat_EtherStatsFragments",
9395 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
9398 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9399 "stat_EtherStatsJabbers",
9400 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
9403 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9404 "stat_EtherStatsUndersizePkts",
9405 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
9406 0, "Undersize packets");
9408 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9409 "stat_EtherStatsOversizePkts",
9410 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts,
9411 0, "stat_EtherStatsOversizePkts");
9413 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9414 "stat_EtherStatsPktsRx64Octets",
9415 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
9416 0, "Bytes received in 64 byte packets");
9418 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9419 "stat_EtherStatsPktsRx65Octetsto127Octets",
9420 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
9421 0, "Bytes received in 65 to 127 byte packets");
9423 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9424 "stat_EtherStatsPktsRx128Octetsto255Octets",
9425 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
9426 0, "Bytes received in 128 to 255 byte packets");
9428 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9429 "stat_EtherStatsPktsRx256Octetsto511Octets",
9430 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
9431 0, "Bytes received in 256 to 511 byte packets");
9433 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9434 "stat_EtherStatsPktsRx512Octetsto1023Octets",
9435 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
9436 0, "Bytes received in 512 to 1023 byte packets");
9438 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9439 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
9440 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
9441 0, "Bytes received in 1024 t0 1522 byte packets");
9443 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9444 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
9445 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
9446 0, "Bytes received in 1523 to 9022 byte packets");
9448 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9449 "stat_EtherStatsPktsTx64Octets",
9450 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
9451 0, "Bytes sent in 64 byte packets");
9453 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9454 "stat_EtherStatsPktsTx65Octetsto127Octets",
9455 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
9456 0, "Bytes sent in 65 to 127 byte packets");
9458 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9459 "stat_EtherStatsPktsTx128Octetsto255Octets",
9460 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
9461 0, "Bytes sent in 128 to 255 byte packets");
9463 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9464 "stat_EtherStatsPktsTx256Octetsto511Octets",
9465 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
9466 0, "Bytes sent in 256 to 511 byte packets");
9468 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9469 "stat_EtherStatsPktsTx512Octetsto1023Octets",
9470 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
9471 0, "Bytes sent in 512 to 1023 byte packets");
9473 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9474 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
9475 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
9476 0, "Bytes sent in 1024 to 1522 byte packets");
9478 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9479 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
9480 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
9481 0, "Bytes sent in 1523 to 9022 byte packets");
9483 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9484 "stat_XonPauseFramesReceived",
9485 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
9486 0, "XON pause frames receved");
9488 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9489 "stat_XoffPauseFramesReceived",
9490 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
9491 0, "XOFF pause frames received");
9493 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9495 CTLFLAG_RD, &sc->stat_OutXonSent,
9496 0, "XON pause frames sent");
9498 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9500 CTLFLAG_RD, &sc->stat_OutXoffSent,
9501 0, "XOFF pause frames sent");
9503 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9504 "stat_FlowControlDone",
9505 CTLFLAG_RD, &sc->stat_FlowControlDone,
9506 0, "Flow control done");
9508 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9509 "stat_MacControlFramesReceived",
9510 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
9511 0, "MAC control frames received");
9513 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9514 "stat_XoffStateEntered",
9515 CTLFLAG_RD, &sc->stat_XoffStateEntered,
9516 0, "XOFF state entered");
9518 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9519 "stat_IfInFramesL2FilterDiscards",
9520 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
9521 0, "Received L2 packets discarded");
9523 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9524 "stat_IfInRuleCheckerDiscards",
9525 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
9526 0, "Received packets discarded by rule");
9528 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9529 "stat_IfInFTQDiscards",
9530 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
9531 0, "Received packet FTQ discards");
9533 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9534 "stat_IfInMBUFDiscards",
9535 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
9536 0, "Received packets discarded due to lack "
9537 "of controller buffer memory");
9539 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9540 "stat_IfInRuleCheckerP4Hit",
9541 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
9542 0, "Received packets rule checker hits");
9544 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9545 "stat_CatchupInRuleCheckerDiscards",
9546 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
9547 0, "Received packets discarded in Catchup path");
9549 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9550 "stat_CatchupInFTQDiscards",
9551 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
9552 0, "Received packets discarded in FTQ in Catchup path");
9554 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9555 "stat_CatchupInMBUFDiscards",
9556 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
9557 0, "Received packets discarded in controller "
9558 "buffer memory in Catchup path");
9560 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9561 "stat_CatchupInRuleCheckerP4Hit",
9562 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
9563 0, "Received packets rule checker hits in Catchup path");
9565 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9567 CTLFLAG_RD, &sc->com_no_buffers,
9568 0, "Valid packets received but no RX buffers available");
9571 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9572 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
9574 bce_sysctl_driver_state, "I", "Drive state information");
9576 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9577 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
9579 bce_sysctl_hw_state, "I", "Hardware state information");
9581 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9582 "status_block", CTLTYPE_INT | CTLFLAG_RW,
9584 bce_sysctl_status_block, "I", "Dump status block");
9586 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9587 "stats_block", CTLTYPE_INT | CTLFLAG_RW,
9589 bce_sysctl_stats_block, "I", "Dump statistics block");
9591 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9592 "stats_clear", CTLTYPE_INT | CTLFLAG_RW,
9594 bce_sysctl_stats_clear, "I", "Clear statistics block");
9596 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9597 "shmem_state", CTLTYPE_INT | CTLFLAG_RW,
9599 bce_sysctl_shmem_state, "I", "Shared memory state information");
9601 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9602 "bc_state", CTLTYPE_INT | CTLFLAG_RW,
9604 bce_sysctl_bc_state, "I", "Bootcode state information");
9606 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9607 "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW,
9609 bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain");
9611 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9612 "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW,
9614 bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain");
9616 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9617 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
9619 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
9621 if (bce_hdr_split == TRUE) {
9622 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9623 "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW,
9625 bce_sysctl_dump_pg_chain, "I", "Dump page chain");
9628 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9629 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW,
9631 bce_sysctl_dump_ctx, "I", "Dump context memory");
9633 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9634 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
9636 bce_sysctl_breakpoint, "I", "Driver breakpoint");
9638 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9639 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
9641 bce_sysctl_reg_read, "I", "Register read");
9643 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9644 "nvram_read", CTLTYPE_INT | CTLFLAG_RW,
9646 bce_sysctl_nvram_read, "I", "NVRAM read");
9648 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9649 "phy_read", CTLTYPE_INT | CTLFLAG_RW,
9651 bce_sysctl_phy_read, "I", "PHY register read");
9655 DBEXIT(BCE_VERBOSE_MISC);
9659 /****************************************************************************/
9660 /* BCE Debug Routines */
9661 /****************************************************************************/
9664 /****************************************************************************/
9665 /* Freezes the controller to allow for a cohesive state dump. */
9669 /****************************************************************************/
9670 static __attribute__ ((noinline)) void
9671 bce_freeze_controller(struct bce_softc *sc)
9674 val = REG_RD(sc, BCE_MISC_COMMAND);
9675 val |= BCE_MISC_COMMAND_DISABLE_ALL;
9676 REG_WR(sc, BCE_MISC_COMMAND, val);
9680 /****************************************************************************/
9681 /* Unfreezes the controller after a freeze operation. This may not always */
9682 /* work and the controller will require a reset! */
9686 /****************************************************************************/
9687 static __attribute__ ((noinline)) void
9688 bce_unfreeze_controller(struct bce_softc *sc)
9691 val = REG_RD(sc, BCE_MISC_COMMAND);
9692 val |= BCE_MISC_COMMAND_ENABLE_ALL;
9693 REG_WR(sc, BCE_MISC_COMMAND, val);
9697 /****************************************************************************/
9698 /* Prints out Ethernet frame information from an mbuf. */
9700 /* Partially decode an Ethernet frame to look at some important headers. */
9704 /****************************************************************************/
9705 static __attribute__ ((noinline)) void
9706 bce_dump_enet(struct bce_softc *sc, struct mbuf *m)
9708 struct ether_vlan_header *eh;
9717 "-----------------------------"
9719 "-----------------------------\n");
9721 eh = mtod(m, struct ether_vlan_header *);
9723 /* Handle VLAN encapsulation if present. */
9724 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
9725 etype = ntohs(eh->evl_proto);
9726 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
9728 etype = ntohs(eh->evl_encap_proto);
9729 ehlen = ETHER_HDR_LEN;
9732 /* ToDo: Add VLAN output. */
9733 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n",
9734 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen);
9738 ip = (struct ip *)(m->m_data + ehlen);
9739 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, "
9740 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n",
9741 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr),
9742 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum));
9746 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9747 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = "
9748 "%d bytes, flags = 0x%b, csum = 0x%04X\n",
9749 ntohs(th->th_dport), ntohs(th->th_sport),
9750 (th->th_off << 2), th->th_flags,
9751 "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST"
9752 "\02SYN\01FIN", ntohs(th->th_sum));
9755 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9756 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d "
9757 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport),
9758 ntohs(uh->uh_sport), ntohs(uh->uh_ulen),
9762 BCE_PRINTF("icmp:\n");
9765 BCE_PRINTF("----: Other IP protocol.\n");
9768 case ETHERTYPE_IPV6:
9769 BCE_PRINTF("ipv6: No decode supported.\n");
9772 BCE_PRINTF("-arp: ");
9773 ah = (struct arphdr *) (m->m_data + ehlen);
9774 switch (ntohs(ah->ar_op)) {
9775 case ARPOP_REVREQUEST:
9776 printf("reverse ARP request\n");
9778 case ARPOP_REVREPLY:
9779 printf("reverse ARP reply\n");
9782 printf("ARP request\n");
9785 printf("ARP reply\n");
9788 printf("other ARP operation\n");
9792 BCE_PRINTF("----: Other protocol.\n");
9796 "-----------------------------"
9798 "-----------------------------\n");
9802 /****************************************************************************/
9803 /* Prints out information about an mbuf. */
9807 /****************************************************************************/
9808 static __attribute__ ((noinline)) void
9809 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
9811 struct mbuf *mp = m;
9814 BCE_PRINTF("mbuf: null pointer\n");
9819 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, "
9820 "m_data = %p\n", mp, mp->m_len, mp->m_flags,
9821 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data);
9823 if (mp->m_flags & M_PKTHDR) {
9824 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, "
9825 "csum_flags = %b\n", mp->m_pkthdr.len,
9826 mp->m_flags, M_FLAG_PRINTF,
9827 mp->m_pkthdr.csum_flags,
9828 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP"
9829 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED"
9830 "\12CSUM_IP_VALID\13CSUM_DATA_VALID"
9831 "\14CSUM_PSEUDO_HDR");
9834 if (mp->m_flags & M_EXT) {
9835 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ",
9836 mp->m_ext.ext_buf, mp->m_ext.ext_size);
9837 switch (mp->m_ext.ext_type) {
9839 printf("EXT_CLUSTER\n"); break;
9841 printf("EXT_SFBUF\n"); break;
9843 printf("EXT_JUMBO9\n"); break;
9845 printf("EXT_JUMBO16\n"); break;
9847 printf("EXT_PACKET\n"); break;
9849 printf("EXT_MBUF\n"); break;
9851 printf("EXT_NET_DRV\n"); break;
9853 printf("EXT_MDD_TYPE\n"); break;
9854 case EXT_DISPOSABLE:
9855 printf("EXT_DISPOSABLE\n"); break;
9857 printf("EXT_EXTREF\n"); break;
9859 printf("UNKNOWN\n");
9868 /****************************************************************************/
9869 /* Prints out the mbufs in the TX mbuf chain. */
9873 /****************************************************************************/
9874 static __attribute__ ((noinline)) void
9875 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9880 "----------------------------"
9882 "----------------------------\n");
9884 for (int i = 0; i < count; i++) {
9885 m = sc->tx_mbuf_ptr[chain_prod];
9886 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod);
9887 bce_dump_mbuf(sc, m);
9888 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
9892 "----------------------------"
9894 "----------------------------\n");
9898 /****************************************************************************/
9899 /* Prints out the mbufs in the RX mbuf chain. */
9903 /****************************************************************************/
9904 static __attribute__ ((noinline)) void
9905 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9910 "----------------------------"
9912 "----------------------------\n");
9914 for (int i = 0; i < count; i++) {
9915 m = sc->rx_mbuf_ptr[chain_prod];
9916 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod);
9917 bce_dump_mbuf(sc, m);
9918 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
9923 "----------------------------"
9925 "----------------------------\n");
9929 /****************************************************************************/
9930 /* Prints out the mbufs in the mbuf page chain. */
9934 /****************************************************************************/
9935 static __attribute__ ((noinline)) void
9936 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9941 "----------------------------"
9943 "----------------------------\n");
9945 for (int i = 0; i < count; i++) {
9946 m = sc->pg_mbuf_ptr[chain_prod];
9947 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod);
9948 bce_dump_mbuf(sc, m);
9949 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod));
9954 "----------------------------"
9956 "----------------------------\n");
9960 /****************************************************************************/
9961 /* Prints out a tx_bd structure. */
9965 /****************************************************************************/
9966 static __attribute__ ((noinline)) void
9967 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
9971 if (idx > MAX_TX_BD_ALLOC)
9972 /* Index out of range. */
9973 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
9974 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
9975 /* TX Chain page pointer. */
9976 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
9977 "pointer\n", idx, txbd->tx_bd_haddr_hi,
9978 txbd->tx_bd_haddr_lo);
9980 /* Normal tx_bd entry. */
9981 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
9982 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = "
9983 "0x%04X (", idx, txbd->tx_bd_haddr_hi,
9984 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes,
9985 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
9987 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) {
9990 printf("CONN_FAULT");
9994 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) {
9997 printf("TCP_UDP_CKSUM");
10001 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) {
10004 printf("IP_CKSUM");
10008 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) {
10015 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) {
10018 printf("COAL_NOW");
10022 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) {
10025 printf("DONT_GEN_CRC");
10029 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) {
10036 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) {
10043 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) {
10050 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) {
10053 printf("SW_OPTION=%d", ((txbd->tx_bd_flags &
10054 TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++;
10057 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) {
10060 printf("SW_FLAGS");
10064 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) {
10075 /****************************************************************************/
10076 /* Prints out a rx_bd structure. */
10080 /****************************************************************************/
10081 static __attribute__ ((noinline)) void
10082 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
10084 if (idx > MAX_RX_BD_ALLOC)
10085 /* Index out of range. */
10086 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
10087 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
10088 /* RX Chain page pointer. */
10089 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
10090 "pointer\n", idx, rxbd->rx_bd_haddr_hi,
10091 rxbd->rx_bd_haddr_lo);
10093 /* Normal rx_bd entry. */
10094 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = "
10095 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi,
10096 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len,
10097 rxbd->rx_bd_flags);
10101 /****************************************************************************/
10102 /* Prints out a rx_bd structure in the page chain. */
10106 /****************************************************************************/
10107 static __attribute__ ((noinline)) void
10108 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd)
10110 if (idx > MAX_PG_BD_ALLOC)
10111 /* Index out of range. */
10112 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx);
10113 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE)
10114 /* Page Chain page pointer. */
10115 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n",
10116 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo);
10118 /* Normal rx_bd entry. */
10119 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, "
10120 "flags = 0x%08X\n", idx,
10121 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo,
10122 pgbd->rx_bd_len, pgbd->rx_bd_flags);
10126 /****************************************************************************/
10127 /* Prints out a l2_fhdr structure. */
10131 /****************************************************************************/
10132 static __attribute__ ((noinline)) void
10133 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
10135 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, "
10136 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, "
10137 "tcp_udp_xsum = 0x%04X\n", idx,
10138 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB,
10139 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
10140 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
10144 /****************************************************************************/
10145 /* Prints out context memory info. (Only useful for CID 0 to 16.) */
10149 /****************************************************************************/
10150 static __attribute__ ((noinline)) void
10151 bce_dump_ctx(struct bce_softc *sc, u16 cid)
10153 if (cid > TX_CID) {
10154 BCE_PRINTF(" Unknown CID\n");
10159 "----------------------------"
10161 "----------------------------\n");
10163 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid);
10165 if (cid == RX_CID) {
10166 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx "
10167 "producer index\n",
10168 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX));
10169 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host "
10170 "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
10171 BCE_L2CTX_RX_HOST_BSEQ));
10172 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n",
10173 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ));
10174 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer "
10175 "descriptor address\n",
10176 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI));
10177 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer "
10178 "descriptor address\n",
10179 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO));
10180 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer "
10181 "index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10182 BCE_L2CTX_RX_NX_BDIDX));
10183 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page "
10184 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10185 BCE_L2CTX_RX_HOST_PG_BDIDX));
10186 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page "
10187 "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid),
10188 BCE_L2CTX_RX_PG_BUF_SIZE));
10189 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page "
10190 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
10191 BCE_L2CTX_RX_NX_PG_BDHADDR_HI));
10192 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page "
10193 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
10194 BCE_L2CTX_RX_NX_PG_BDHADDR_LO));
10195 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page "
10196 "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10197 BCE_L2CTX_RX_NX_PG_BDIDX));
10198 } else if (cid == TX_CID) {
10199 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
10200 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n",
10201 CTX_RD(sc, GET_CID_ADDR(cid),
10202 BCE_L2CTX_TX_TYPE_XI));
10203 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx "
10204 "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid),
10205 BCE_L2CTX_TX_CMD_TYPE_XI));
10206 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) "
10207 "h/w buffer descriptor address\n",
10208 CTX_RD(sc, GET_CID_ADDR(cid),
10209 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI));
10210 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) "
10211 "h/w buffer descriptor address\n",
10212 CTX_RD(sc, GET_CID_ADDR(cid),
10213 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI));
10214 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) "
10215 "host producer index\n",
10216 CTX_RD(sc, GET_CID_ADDR(cid),
10217 BCE_L2CTX_TX_HOST_BIDX_XI));
10218 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) "
10219 "host byte sequence\n",
10220 CTX_RD(sc, GET_CID_ADDR(cid),
10221 BCE_L2CTX_TX_HOST_BSEQ_XI));
10223 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n",
10224 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE));
10225 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n",
10226 CTX_RD(sc, GET_CID_ADDR(cid),
10227 BCE_L2CTX_TX_CMD_TYPE));
10228 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) "
10229 "h/w buffer descriptor address\n",
10230 CTX_RD(sc, GET_CID_ADDR(cid),
10231 BCE_L2CTX_TX_TBDR_BHADDR_HI));
10232 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) "
10233 "h/w buffer descriptor address\n",
10234 CTX_RD(sc, GET_CID_ADDR(cid),
10235 BCE_L2CTX_TX_TBDR_BHADDR_LO));
10236 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host "
10237 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10238 BCE_L2CTX_TX_HOST_BIDX));
10239 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte "
10240 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
10241 BCE_L2CTX_TX_HOST_BSEQ));
10246 "----------------------------"
10248 "----------------------------\n");
10250 for (int i = 0x0; i < 0x300; i += 0x10) {
10251 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
10252 CTX_RD(sc, GET_CID_ADDR(cid), i),
10253 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4),
10254 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8),
10255 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc));
10260 "----------------------------"
10262 "----------------------------\n");
10266 /****************************************************************************/
10267 /* Prints out the FTQ data. */
10271 /****************************************************************************/
10272 static __attribute__ ((noinline)) void
10273 bce_dump_ftqs(struct bce_softc *sc)
10275 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val;
10278 "----------------------------"
10280 "----------------------------\n");
10282 BCE_PRINTF(" FTQ Command Control Depth_Now "
10283 "Max_Depth Valid_Cnt \n");
10284 BCE_PRINTF(" ------- ---------- ---------- ---------- "
10285 "---------- ----------\n");
10287 /* Setup the generic statistic counters for the FTQ valid count. */
10288 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) |
10289 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) |
10290 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) |
10291 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT);
10292 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10294 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) |
10295 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) |
10296 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) |
10297 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT);
10298 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val);
10300 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) |
10301 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) |
10302 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) |
10303 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT);
10304 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val);
10306 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) |
10307 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) |
10308 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) |
10309 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT);
10310 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val);
10312 /* Input queue to the Receive Lookup state machine */
10313 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD);
10314 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL);
10315 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22;
10316 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12;
10317 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
10318 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10319 cmd, ctl, cur_depth, max_depth, valid_cnt);
10321 /* Input queue to the Receive Processor */
10322 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD);
10323 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL);
10324 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22;
10325 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12;
10326 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
10327 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10328 cmd, ctl, cur_depth, max_depth, valid_cnt);
10330 /* Input queue to the Recevie Processor */
10331 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD);
10332 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL);
10333 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22;
10334 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12;
10335 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
10336 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10337 cmd, ctl, cur_depth, max_depth, valid_cnt);
10339 /* Input queue to the Receive Virtual to Physical state machine */
10340 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD);
10341 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL);
10342 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22;
10343 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12;
10344 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
10345 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10346 cmd, ctl, cur_depth, max_depth, valid_cnt);
10348 /* Input queue to the Recevie Virtual to Physical state machine */
10349 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD);
10350 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL);
10351 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22;
10352 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12;
10353 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4);
10354 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10355 cmd, ctl, cur_depth, max_depth, valid_cnt);
10357 /* Input queue to the Receive Virtual to Physical state machine */
10358 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD);
10359 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL);
10360 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22;
10361 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12;
10362 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5);
10363 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10364 cmd, ctl, cur_depth, max_depth, valid_cnt);
10366 /* Input queue to the Receive DMA state machine */
10367 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD);
10368 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL);
10369 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22;
10370 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12;
10371 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6);
10372 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10373 cmd, ctl, cur_depth, max_depth, valid_cnt);
10375 /* Input queue to the Transmit Scheduler state machine */
10376 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD);
10377 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL);
10378 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22;
10379 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12;
10380 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7);
10381 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10382 cmd, ctl, cur_depth, max_depth, valid_cnt);
10384 /* Input queue to the Transmit Buffer Descriptor state machine */
10385 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD);
10386 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL);
10387 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22;
10388 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12;
10389 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8);
10390 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10391 cmd, ctl, cur_depth, max_depth, valid_cnt);
10393 /* Input queue to the Transmit Processor */
10394 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD);
10395 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL);
10396 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22;
10397 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12;
10398 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9);
10399 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10400 cmd, ctl, cur_depth, max_depth, valid_cnt);
10402 /* Input queue to the Transmit DMA state machine */
10403 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD);
10404 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL);
10405 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22;
10406 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12;
10407 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10);
10408 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10409 cmd, ctl, cur_depth, max_depth, valid_cnt);
10411 /* Input queue to the Transmit Patch-Up Processor */
10412 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD);
10413 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL);
10414 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22;
10415 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12;
10416 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11);
10417 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10418 cmd, ctl, cur_depth, max_depth, valid_cnt);
10420 /* Input queue to the Transmit Assembler state machine */
10421 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD);
10422 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL);
10423 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22;
10424 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12;
10425 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12);
10426 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10427 cmd, ctl, cur_depth, max_depth, valid_cnt);
10429 /* Input queue to the Completion Processor */
10430 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD);
10431 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL);
10432 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22;
10433 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12;
10434 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13);
10435 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10436 cmd, ctl, cur_depth, max_depth, valid_cnt);
10438 /* Input queue to the Completion Processor */
10439 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD);
10440 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL);
10441 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22;
10442 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12;
10443 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14);
10444 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10445 cmd, ctl, cur_depth, max_depth, valid_cnt);
10447 /* Input queue to the Completion Processor */
10448 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD);
10449 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL);
10450 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22;
10451 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12;
10452 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15);
10453 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10454 cmd, ctl, cur_depth, max_depth, valid_cnt);
10456 /* Setup the generic statistic counters for the FTQ valid count. */
10457 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) |
10458 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) |
10459 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT);
10461 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
10463 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI <<
10465 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10467 /* Input queue to the Management Control Processor */
10468 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD);
10469 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL);
10470 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22;
10471 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12;
10472 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
10473 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10474 cmd, ctl, cur_depth, max_depth, valid_cnt);
10476 /* Input queue to the Command Processor */
10477 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD);
10478 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL);
10479 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22;
10480 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12;
10481 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
10482 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10483 cmd, ctl, cur_depth, max_depth, valid_cnt);
10485 /* Input queue to the Completion Scheduler state machine */
10486 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD);
10487 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL);
10488 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22;
10489 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12;
10490 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
10491 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10492 cmd, ctl, cur_depth, max_depth, valid_cnt);
10494 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
10495 /* Input queue to the RV2P Command Scheduler */
10496 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD);
10497 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL);
10498 cur_depth = (ctl & 0xFFC00000) >> 22;
10499 max_depth = (ctl & 0x003FF000) >> 12;
10500 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
10501 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10502 cmd, ctl, cur_depth, max_depth, valid_cnt);
10506 "----------------------------"
10508 "----------------------------\n");
10512 /****************************************************************************/
10513 /* Prints out the TX chain. */
10517 /****************************************************************************/
10518 static __attribute__ ((noinline)) void
10519 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count)
10521 struct tx_bd *txbd;
10523 /* First some info about the tx_bd chain structure. */
10525 "----------------------------"
10527 "----------------------------\n");
10529 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n",
10530 (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages);
10531 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n",
10532 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE);
10533 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC);
10536 "----------------------------"
10538 "----------------------------\n");
10540 /* Now print out a decoded list of TX buffer descriptors. */
10541 for (int i = 0; i < count; i++) {
10542 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
10543 bce_dump_txbd(sc, tx_prod, txbd);
10548 "----------------------------"
10550 "----------------------------\n");
10554 /****************************************************************************/
10555 /* Prints out the RX chain. */
10559 /****************************************************************************/
10560 static __attribute__ ((noinline)) void
10561 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count)
10563 struct rx_bd *rxbd;
10565 /* First some info about the rx_bd chain structure. */
10567 "----------------------------"
10569 "----------------------------\n");
10571 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n",
10572 (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages);
10574 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
10575 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE);
10577 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC);
10580 "----------------------------"
10582 "----------------------------\n");
10584 /* Now print out the rx_bd's themselves. */
10585 for (int i = 0; i < count; i++) {
10586 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
10587 bce_dump_rxbd(sc, rx_prod, rxbd);
10588 rx_prod = RX_CHAIN_IDX(rx_prod + 1);
10592 "----------------------------"
10594 "----------------------------\n");
10598 /****************************************************************************/
10599 /* Prints out the page chain. */
10603 /****************************************************************************/
10604 static __attribute__ ((noinline)) void
10605 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count)
10607 struct rx_bd *pgbd;
10609 /* First some info about the page chain structure. */
10611 "----------------------------"
10613 "----------------------------\n");
10615 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n",
10616 (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages);
10618 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
10619 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE);
10621 BCE_PRINTF("total pg_bd = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC);
10624 "----------------------------"
10626 "----------------------------\n");
10628 /* Now print out the rx_bd's themselves. */
10629 for (int i = 0; i < count; i++) {
10630 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)];
10631 bce_dump_pgbd(sc, pg_prod, pgbd);
10632 pg_prod = PG_CHAIN_IDX(pg_prod + 1);
10636 "----------------------------"
10638 "----------------------------\n");
10642 #define BCE_PRINT_RX_CONS(arg) \
10643 if (sblk->status_rx_quick_consumer_index##arg) \
10644 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \
10645 sblk->status_rx_quick_consumer_index##arg, (u16) \
10646 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \
10650 #define BCE_PRINT_TX_CONS(arg) \
10651 if (sblk->status_tx_quick_consumer_index##arg) \
10652 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \
10653 sblk->status_tx_quick_consumer_index##arg, (u16) \
10654 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \
10657 /****************************************************************************/
10658 /* Prints out the status block from host memory. */
10662 /****************************************************************************/
10663 static __attribute__ ((noinline)) void
10664 bce_dump_status_block(struct bce_softc *sc)
10666 struct status_block *sblk;
10668 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
10670 sblk = sc->status_block;
10673 "----------------------------"
10675 "----------------------------\n");
10677 /* Theses indices are used for normal L2 drivers. */
10678 BCE_PRINTF(" 0x%08X - attn_bits\n",
10679 sblk->status_attn_bits);
10681 BCE_PRINTF(" 0x%08X - attn_bits_ack\n",
10682 sblk->status_attn_bits_ack);
10684 BCE_PRINT_RX_CONS(0);
10685 BCE_PRINT_TX_CONS(0)
10687 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx);
10689 /* Theses indices are not used for normal L2 drivers. */
10690 BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3);
10691 BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6);
10692 BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9);
10693 BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12);
10694 BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15);
10696 BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3);
10698 if (sblk->status_completion_producer_index ||
10699 sblk->status_cmd_consumer_index)
10700 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n",
10701 sblk->status_completion_producer_index,
10702 sblk->status_cmd_consumer_index);
10705 "----------------------------"
10707 "----------------------------\n");
10711 #define BCE_PRINT_64BIT_STAT(arg) \
10712 if (sblk->arg##_lo || sblk->arg##_hi) \
10713 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \
10714 sblk->arg##_lo, #arg);
10716 #define BCE_PRINT_32BIT_STAT(arg) \
10718 BCE_PRINTF(" 0x%08X : %s\n", \
10721 /****************************************************************************/
10722 /* Prints out the statistics block from host memory. */
10726 /****************************************************************************/
10727 static __attribute__ ((noinline)) void
10728 bce_dump_stats_block(struct bce_softc *sc)
10730 struct statistics_block *sblk;
10732 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD);
10734 sblk = sc->stats_block;
10738 " Stats Block (All Stats Not Shown Are 0) "
10739 "---------------\n");
10741 BCE_PRINT_64BIT_STAT(stat_IfHCInOctets);
10742 BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets);
10743 BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets);
10744 BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets);
10745 BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts);
10746 BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts);
10747 BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts);
10748 BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts);
10749 BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts);
10750 BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts);
10751 BCE_PRINT_32BIT_STAT(
10752 stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
10753 BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors);
10754 BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors);
10755 BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors);
10756 BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames);
10757 BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames);
10758 BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions);
10759 BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions);
10760 BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions);
10761 BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions);
10762 BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments);
10763 BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers);
10764 BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts);
10765 BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts);
10766 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets);
10767 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets);
10768 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets);
10769 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets);
10770 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets);
10771 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets);
10772 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets);
10773 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets);
10774 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets);
10775 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets);
10776 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets);
10777 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets);
10778 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets);
10779 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets);
10780 BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived);
10781 BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived);
10782 BCE_PRINT_32BIT_STAT(stat_OutXonSent);
10783 BCE_PRINT_32BIT_STAT(stat_OutXoffSent);
10784 BCE_PRINT_32BIT_STAT(stat_FlowControlDone);
10785 BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived);
10786 BCE_PRINT_32BIT_STAT(stat_XoffStateEntered);
10787 BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards);
10788 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards);
10789 BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards);
10790 BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards);
10791 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit);
10792 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards);
10793 BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards);
10794 BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards);
10795 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit);
10798 "----------------------------"
10800 "----------------------------\n");
10804 /****************************************************************************/
10805 /* Prints out a summary of the driver state. */
10809 /****************************************************************************/
10810 static __attribute__ ((noinline)) void
10811 bce_dump_driver_state(struct bce_softc *sc)
10813 u32 val_hi, val_lo;
10816 "-----------------------------"
10818 "-----------------------------\n");
10820 val_hi = BCE_ADDR_HI(sc);
10821 val_lo = BCE_ADDR_LO(sc);
10822 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual "
10823 "address\n", val_hi, val_lo);
10825 val_hi = BCE_ADDR_HI(sc->bce_vhandle);
10826 val_lo = BCE_ADDR_LO(sc->bce_vhandle);
10827 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual "
10828 "address\n", val_hi, val_lo);
10830 val_hi = BCE_ADDR_HI(sc->status_block);
10831 val_lo = BCE_ADDR_LO(sc->status_block);
10832 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block "
10833 "virtual address\n", val_hi, val_lo);
10835 val_hi = BCE_ADDR_HI(sc->stats_block);
10836 val_lo = BCE_ADDR_LO(sc->stats_block);
10837 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block "
10838 "virtual address\n", val_hi, val_lo);
10840 val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
10841 val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
10842 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
10843 "virtual adddress\n", val_hi, val_lo);
10845 val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
10846 val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
10847 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
10848 "virtual address\n", val_hi, val_lo);
10850 if (bce_hdr_split == TRUE) {
10851 val_hi = BCE_ADDR_HI(sc->pg_bd_chain);
10852 val_lo = BCE_ADDR_LO(sc->pg_bd_chain);
10853 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain "
10854 "virtual address\n", val_hi, val_lo);
10857 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
10858 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
10859 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
10860 "virtual address\n", val_hi, val_lo);
10862 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
10863 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
10864 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
10865 "virtual address\n", val_hi, val_lo);
10867 if (bce_hdr_split == TRUE) {
10868 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr);
10869 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr);
10870 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain "
10871 "virtual address\n", val_hi, val_lo);
10874 BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) "
10876 (long long unsigned int) sc->interrupts_generated);
10878 BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) "
10879 "rx interrupts handled\n",
10880 (long long unsigned int) sc->interrupts_rx);
10882 BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) "
10883 "tx interrupts handled\n",
10884 (long long unsigned int) sc->interrupts_tx);
10886 BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) "
10887 "phy interrupts handled\n",
10888 (long long unsigned int) sc->phy_interrupts);
10890 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) "
10891 "status block index\n", sc->last_status_idx);
10893 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer "
10894 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod));
10896 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer "
10897 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons));
10899 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer "
10900 "byte seq index\n", sc->tx_prod_bseq);
10902 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx "
10903 "mbufs allocated\n", sc->debug_tx_mbuf_alloc);
10905 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used "
10906 "tx_bd's\n", sc->used_tx_bd);
10908 BCE_PRINTF(" 0x%04X/0x%04X - (sc->tx_hi_watermark)/"
10909 "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd);
10911 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer "
10912 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod));
10914 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer "
10915 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons));
10917 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer "
10918 "byte seq index\n", sc->rx_prod_bseq);
10920 BCE_PRINTF(" 0x%04X/0x%04X - (sc->rx_low_watermark)/"
10921 "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd);
10923 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx "
10924 "mbufs allocated\n", sc->debug_rx_mbuf_alloc);
10926 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free "
10927 "rx_bd's\n", sc->free_rx_bd);
10929 if (bce_hdr_split == TRUE) {
10930 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer "
10931 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod));
10933 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer "
10934 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons));
10936 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page "
10937 "mbufs allocated\n", sc->debug_pg_mbuf_alloc);
10940 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page "
10941 "rx_bd's\n", sc->free_pg_bd);
10943 BCE_PRINTF(" 0x%04X/0x%04X - (sc->pg_low_watermark)/"
10944 "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd);
10946 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) "
10947 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count);
10949 BCE_PRINTF(" 0x%08X - (sc->bce_flags) "
10950 "bce mac flags\n", sc->bce_flags);
10952 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) "
10953 "bce phy flags\n", sc->bce_phy_flags);
10956 "----------------------------"
10958 "----------------------------\n");
10962 /****************************************************************************/
10963 /* Prints out the hardware state through a summary of important register, */
10964 /* followed by a complete register dump. */
10968 /****************************************************************************/
10969 static __attribute__ ((noinline)) void
10970 bce_dump_hw_state(struct bce_softc *sc)
10975 "----------------------------"
10977 "----------------------------\n");
10979 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
10981 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
10982 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n",
10983 val, BCE_MISC_ENABLE_STATUS_BITS);
10985 val = REG_RD(sc, BCE_DMA_STATUS);
10986 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n",
10987 val, BCE_DMA_STATUS);
10989 val = REG_RD(sc, BCE_CTX_STATUS);
10990 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n",
10991 val, BCE_CTX_STATUS);
10993 val = REG_RD(sc, BCE_EMAC_STATUS);
10994 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n",
10995 val, BCE_EMAC_STATUS);
10997 val = REG_RD(sc, BCE_RPM_STATUS);
10998 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n",
10999 val, BCE_RPM_STATUS);
11001 /* ToDo: Create a #define for this constant. */
11002 val = REG_RD(sc, 0x2004);
11003 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n",
11006 val = REG_RD(sc, BCE_RV2P_STATUS);
11007 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n",
11008 val, BCE_RV2P_STATUS);
11010 /* ToDo: Create a #define for this constant. */
11011 val = REG_RD(sc, 0x2c04);
11012 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n",
11015 val = REG_RD(sc, BCE_TBDR_STATUS);
11016 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n",
11017 val, BCE_TBDR_STATUS);
11019 val = REG_RD(sc, BCE_TDMA_STATUS);
11020 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n",
11021 val, BCE_TDMA_STATUS);
11023 val = REG_RD(sc, BCE_HC_STATUS);
11024 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n",
11025 val, BCE_HC_STATUS);
11027 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
11028 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
11029 val, BCE_TXP_CPU_STATE);
11031 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11032 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
11033 val, BCE_TPAT_CPU_STATE);
11035 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11036 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
11037 val, BCE_RXP_CPU_STATE);
11039 val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11040 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
11041 val, BCE_COM_CPU_STATE);
11043 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
11044 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n",
11045 val, BCE_MCP_CPU_STATE);
11047 val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11048 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
11049 val, BCE_CP_CPU_STATE);
11052 "----------------------------"
11054 "----------------------------\n");
11057 "----------------------------"
11059 "----------------------------\n");
11061 for (int i = 0x400; i < 0x8000; i += 0x10) {
11062 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11063 i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
11064 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
11068 "----------------------------"
11070 "----------------------------\n");
11074 /****************************************************************************/
11075 /* Prints out the contentst of shared memory which is used for host driver */
11076 /* to bootcode firmware communication. */
11080 /****************************************************************************/
11081 static __attribute__ ((noinline)) void
11082 bce_dump_shmem_state(struct bce_softc *sc)
11085 "----------------------------"
11087 "----------------------------\n");
11089 BCE_PRINTF("0x%08X - Shared memory base address\n",
11090 sc->bce_shmem_base);
11091 BCE_PRINTF("%s - bootcode version\n",
11095 "----------------------------"
11097 "----------------------------\n");
11099 for (int i = 0x0; i < 0x200; i += 0x10) {
11100 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11101 i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4),
11102 bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC));
11106 "----------------------------"
11108 "----------------------------\n");
11112 /****************************************************************************/
11113 /* Prints out the mailbox queue registers. */
11117 /****************************************************************************/
11118 static __attribute__ ((noinline)) void
11119 bce_dump_mq_regs(struct bce_softc *sc)
11122 "----------------------------"
11124 "----------------------------\n");
11127 "----------------------------"
11129 "----------------------------\n");
11131 for (int i = 0x3c00; i < 0x4000; i += 0x10) {
11132 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11133 i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
11134 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
11138 "----------------------------"
11140 "----------------------------\n");
11144 /****************************************************************************/
11145 /* Prints out the bootcode state. */
11149 /****************************************************************************/
11150 static __attribute__ ((noinline)) void
11151 bce_dump_bc_state(struct bce_softc *sc)
11156 "----------------------------"
11158 "----------------------------\n");
11160 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
11162 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE);
11163 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n",
11164 val, BCE_BC_RESET_TYPE);
11166 val = bce_shmem_rd(sc, BCE_BC_STATE);
11167 BCE_PRINTF("0x%08X - (0x%06X) state\n",
11168 val, BCE_BC_STATE);
11170 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
11171 BCE_PRINTF("0x%08X - (0x%06X) condition\n",
11172 val, BCE_BC_STATE_CONDITION);
11174 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD);
11175 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n",
11176 val, BCE_BC_STATE_DEBUG_CMD);
11179 "----------------------------"
11181 "----------------------------\n");
11185 /****************************************************************************/
11186 /* Prints out the TXP processor state. */
11190 /****************************************************************************/
11191 static __attribute__ ((noinline)) void
11192 bce_dump_txp_state(struct bce_softc *sc, int regs)
11198 "----------------------------"
11200 "----------------------------\n");
11202 for (int i = 0; i < 3; i++)
11203 fw_version[i] = htonl(REG_RD_IND(sc,
11204 (BCE_TXP_SCRATCH + 0x10 + i * 4)));
11205 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11207 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
11208 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n",
11209 val, BCE_TXP_CPU_MODE);
11211 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
11212 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
11213 val, BCE_TXP_CPU_STATE);
11215 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
11216 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n",
11217 val, BCE_TXP_CPU_EVENT_MASK);
11221 "----------------------------"
11223 "----------------------------\n");
11225 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
11226 /* Skip the big blank spaces */
11227 if (i < 0x454000 && i > 0x5ffff)
11228 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11229 "0x%08X 0x%08X\n", i,
11231 REG_RD_IND(sc, i + 0x4),
11232 REG_RD_IND(sc, i + 0x8),
11233 REG_RD_IND(sc, i + 0xC));
11238 "----------------------------"
11240 "----------------------------\n");
11244 /****************************************************************************/
11245 /* Prints out the RXP processor state. */
11249 /****************************************************************************/
11250 static __attribute__ ((noinline)) void
11251 bce_dump_rxp_state(struct bce_softc *sc, int regs)
11257 "----------------------------"
11259 "----------------------------\n");
11261 for (int i = 0; i < 3; i++)
11262 fw_version[i] = htonl(REG_RD_IND(sc,
11263 (BCE_RXP_SCRATCH + 0x10 + i * 4)));
11265 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11267 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
11268 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n",
11269 val, BCE_RXP_CPU_MODE);
11271 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11272 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
11273 val, BCE_RXP_CPU_STATE);
11275 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
11276 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n",
11277 val, BCE_RXP_CPU_EVENT_MASK);
11281 "----------------------------"
11283 "----------------------------\n");
11285 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
11286 /* Skip the big blank sapces */
11287 if (i < 0xc5400 && i > 0xdffff)
11288 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11289 "0x%08X 0x%08X\n", i,
11291 REG_RD_IND(sc, i + 0x4),
11292 REG_RD_IND(sc, i + 0x8),
11293 REG_RD_IND(sc, i + 0xC));
11298 "----------------------------"
11300 "----------------------------\n");
11304 /****************************************************************************/
11305 /* Prints out the TPAT processor state. */
11309 /****************************************************************************/
11310 static __attribute__ ((noinline)) void
11311 bce_dump_tpat_state(struct bce_softc *sc, int regs)
11317 "----------------------------"
11319 "----------------------------\n");
11321 for (int i = 0; i < 3; i++)
11322 fw_version[i] = htonl(REG_RD_IND(sc,
11323 (BCE_TPAT_SCRATCH + 0x410 + i * 4)));
11325 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11327 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
11328 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n",
11329 val, BCE_TPAT_CPU_MODE);
11331 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11332 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
11333 val, BCE_TPAT_CPU_STATE);
11335 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
11336 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n",
11337 val, BCE_TPAT_CPU_EVENT_MASK);
11341 "----------------------------"
11343 "----------------------------\n");
11345 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
11346 /* Skip the big blank spaces */
11347 if (i < 0x854000 && i > 0x9ffff)
11348 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11349 "0x%08X 0x%08X\n", i,
11351 REG_RD_IND(sc, i + 0x4),
11352 REG_RD_IND(sc, i + 0x8),
11353 REG_RD_IND(sc, i + 0xC));
11358 "----------------------------"
11360 "----------------------------\n");
11364 /****************************************************************************/
11365 /* Prints out the Command Procesor (CP) state. */
11369 /****************************************************************************/
11370 static __attribute__ ((noinline)) void
11371 bce_dump_cp_state(struct bce_softc *sc, int regs)
11377 "----------------------------"
11379 "----------------------------\n");
11381 for (int i = 0; i < 3; i++)
11382 fw_version[i] = htonl(REG_RD_IND(sc,
11383 (BCE_CP_SCRATCH + 0x10 + i * 4)));
11385 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11387 val = REG_RD_IND(sc, BCE_CP_CPU_MODE);
11388 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n",
11389 val, BCE_CP_CPU_MODE);
11391 val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11392 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
11393 val, BCE_CP_CPU_STATE);
11395 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK);
11396 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val,
11397 BCE_CP_CPU_EVENT_MASK);
11401 "----------------------------"
11403 "----------------------------\n");
11405 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) {
11406 /* Skip the big blank spaces */
11407 if (i < 0x185400 && i > 0x19ffff)
11408 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11409 "0x%08X 0x%08X\n", i,
11411 REG_RD_IND(sc, i + 0x4),
11412 REG_RD_IND(sc, i + 0x8),
11413 REG_RD_IND(sc, i + 0xC));
11418 "----------------------------"
11420 "----------------------------\n");
11424 /****************************************************************************/
11425 /* Prints out the Completion Procesor (COM) state. */
11429 /****************************************************************************/
11430 static __attribute__ ((noinline)) void
11431 bce_dump_com_state(struct bce_softc *sc, int regs)
11437 "----------------------------"
11439 "----------------------------\n");
11441 for (int i = 0; i < 3; i++)
11442 fw_version[i] = htonl(REG_RD_IND(sc,
11443 (BCE_COM_SCRATCH + 0x10 + i * 4)));
11445 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11447 val = REG_RD_IND(sc, BCE_COM_CPU_MODE);
11448 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n",
11449 val, BCE_COM_CPU_MODE);
11451 val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11452 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
11453 val, BCE_COM_CPU_STATE);
11455 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK);
11456 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val,
11457 BCE_COM_CPU_EVENT_MASK);
11461 "----------------------------"
11463 "----------------------------\n");
11465 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) {
11466 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11467 "0x%08X 0x%08X\n", i,
11469 REG_RD_IND(sc, i + 0x4),
11470 REG_RD_IND(sc, i + 0x8),
11471 REG_RD_IND(sc, i + 0xC));
11476 "----------------------------"
11478 "----------------------------\n");
11482 /****************************************************************************/
11483 /* Prints out the Receive Virtual 2 Physical (RV2P) state. */
11487 /****************************************************************************/
11488 static __attribute__ ((noinline)) void
11489 bce_dump_rv2p_state(struct bce_softc *sc)
11491 u32 val, pc1, pc2, fw_ver_high, fw_ver_low;
11494 "----------------------------"
11496 "----------------------------\n");
11498 /* Stall the RV2P processors. */
11499 val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11500 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2;
11501 REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
11503 /* Read the firmware version. */
11505 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
11506 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
11507 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
11508 BCE_RV2P_INSTR_HIGH_HIGH;
11509 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n",
11510 fw_ver_high, fw_ver_low);
11513 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
11514 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
11515 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
11516 BCE_RV2P_INSTR_HIGH_HIGH;
11517 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n",
11518 fw_ver_high, fw_ver_low);
11520 /* Resume the RV2P processors. */
11521 val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11522 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2);
11523 REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
11525 /* Fetch the program counter value. */
11527 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
11528 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11529 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
11530 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
11531 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1);
11532 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2);
11534 /* Fetch the program counter value again to see if it is advancing. */
11536 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
11537 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11538 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
11539 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
11540 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1);
11541 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2);
11544 "----------------------------"
11546 "----------------------------\n");
11550 /****************************************************************************/
11551 /* Prints out the driver state and then enters the debugger. */
11555 /****************************************************************************/
11556 static __attribute__ ((noinline)) void
11557 bce_breakpoint(struct bce_softc *sc)
11561 * Unreachable code to silence compiler warnings
11562 * about unused functions.
11565 bce_freeze_controller(sc);
11566 bce_unfreeze_controller(sc);
11567 bce_dump_enet(sc, NULL);
11568 bce_dump_txbd(sc, 0, NULL);
11569 bce_dump_rxbd(sc, 0, NULL);
11570 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC);
11571 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC);
11572 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC);
11573 bce_dump_l2fhdr(sc, 0, NULL);
11574 bce_dump_ctx(sc, RX_CID);
11576 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC);
11577 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC);
11578 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC);
11579 bce_dump_status_block(sc);
11580 bce_dump_stats_block(sc);
11581 bce_dump_driver_state(sc);
11582 bce_dump_hw_state(sc);
11583 bce_dump_bc_state(sc);
11584 bce_dump_txp_state(sc, 0);
11585 bce_dump_rxp_state(sc, 0);
11586 bce_dump_tpat_state(sc, 0);
11587 bce_dump_cp_state(sc, 0);
11588 bce_dump_com_state(sc, 0);
11589 bce_dump_rv2p_state(sc);
11590 bce_dump_pgbd(sc, 0, NULL);
11593 bce_dump_status_block(sc);
11594 bce_dump_driver_state(sc);
11596 /* Call the debugger. */