sys/dev/bce/if_bce.c

   1 /*-
   2  * Copyright (c) 2006-2014 QLogic Corporation
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  18  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  19  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  20  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  21  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  22  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  23  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  24  * THE POSSIBILITY OF SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 /*
  31  * The following controllers are supported by this driver:
  32  *   BCM5706C A2, A3
  33  *   BCM5706S A2, A3
  34  *   BCM5708C B1, B2
  35  *   BCM5708S B1, B2
  36  *   BCM5709C A1, C0
  37  *   BCM5709S A1, C0
  38  *   BCM5716C C0
  39  *   BCM5716S C0
  40  *
  41  * The following controllers are not supported by this driver:
  42  *   BCM5706C A0, A1 (pre-production)
  43  *   BCM5706S A0, A1 (pre-production)
  44  *   BCM5708C A0, B0 (pre-production)
  45  *   BCM5708S A0, B0 (pre-production)
  46  *   BCM5709C A0  B0, B1, B2 (pre-production)
  47  *   BCM5709S A0, B0, B1, B2 (pre-production)
  48  */
  49
  50 #include "opt_bce.h"
  51
  52 #include <sys/param.h>
  53 #include <sys/endian.h>
  54 #include <sys/systm.h>
  55 #include <sys/sockio.h>
  56 #include <sys/lock.h>
  57 #include <sys/mbuf.h>
  58 #include <sys/malloc.h>
  59 #include <sys/mutex.h>
  60 #include <sys/kernel.h>
  61 #include <sys/module.h>
  62 #include <sys/socket.h>
  63 #include <sys/sysctl.h>
  64 #include <sys/queue.h>
  65
  66 #include <net/bpf.h>
  67 #include <net/ethernet.h>
  68 #include <net/if.h>
  69 #include <net/if_var.h>
  70 #include <net/if_arp.h>
  71 #include <net/if_dl.h>
  72 #include <net/if_media.h>
  73
  74 #include <net/if_types.h>
  75 #include <net/if_vlan_var.h>
  76
  77 #include <netinet/in_systm.h>
  78 #include <netinet/in.h>
  79 #include <netinet/if_ether.h>
  80 #include <netinet/ip.h>
  81 #include <netinet/ip6.h>
  82 #include <netinet/tcp.h>
  83 #include <netinet/udp.h>
  84
  85 #include <machine/bus.h>
  86 #include <machine/resource.h>
  87 #include <sys/bus.h>
  88 #include <sys/rman.h>
  89
  90 #include <dev/mii/mii.h>
  91 #include <dev/mii/miivar.h>
  92 #include "miidevs.h"
  93 #include <dev/mii/brgphyreg.h>
  94
  95 #include <dev/pci/pcireg.h>
  96 #include <dev/pci/pcivar.h>
  97
  98 #include "miibus_if.h"
  99
 100 #include <dev/bce/if_bcereg.h>
 101 #include <dev/bce/if_bcefw.h>
 102
 103 /****************************************************************************/
 104 /* BCE Debug Options                                                        */
 105 /****************************************************************************/
 106 #ifdef BCE_DEBUG
 107         u32 bce_debug = BCE_WARN;
 108
 109         /*          0 = Never              */
 110         /*          1 = 1 in 2,147,483,648 */
 111         /*        256 = 1 in     8,388,608 */
 112         /*       2048 = 1 in     1,048,576 */
 113         /*      65536 = 1 in        32,768 */
 114         /*    1048576 = 1 in         2,048 */
 115         /*  268435456 = 1 in             8 */
 116         /*  536870912 = 1 in             4 */
 117         /* 1073741824 = 1 in             2 */
 118
 119         /* Controls how often the l2_fhdr frame error check will fail. */
 120         int l2fhdr_error_sim_control = 0;
 121
 122         /* Controls how often the unexpected attention check will fail. */
 123         int unexpected_attention_sim_control = 0;
 124
 125         /* Controls how often to simulate an mbuf allocation failure. */
 126         int mbuf_alloc_failed_sim_control = 0;
 127
 128         /* Controls how often to simulate a DMA mapping failure. */
 129         int dma_map_addr_failed_sim_control = 0;
 130
 131         /* Controls how often to simulate a bootcode failure. */
 132         int bootcode_running_failure_sim_control = 0;
 133 #endif
 134
 135 /****************************************************************************/
 136 /* PCI Device ID Table                                                      */
 137 /*                                                                          */
 138 /* Used by bce_probe() to identify the devices supported by this driver.    */
 139 /****************************************************************************/
 140 #define BCE_DEVDESC_MAX         64
 141
 142 static const struct bce_type bce_devs[] = {
 143         /* BCM5706C Controllers and OEM boards. */
 144         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
 145                 "HP NC370T Multifunction Gigabit Server Adapter" },
 146         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
 147                 "HP NC370i Multifunction Gigabit Server Adapter" },
 148         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
 149                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
 150         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
 151                 "HP NC371i Multifunction Gigabit Server Adapter" },
 152         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 153                 "QLogic NetXtreme II BCM5706 1000Base-T" },
 154
 155         /* BCM5706S controllers and OEM boards. */
 156         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 157                 "HP NC370F Multifunction Gigabit Server Adapter" },
 158         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 159                 "QLogic NetXtreme II BCM5706 1000Base-SX" },
 160
 161         /* BCM5708C controllers and OEM boards. */
 162         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
 163                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
 164         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
 165                 "HP NC373i Multifunction Gigabit Server Adapter" },
 166         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
 167                 "HP NC374m PCIe Multifunction Adapter" },
 168         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 169                 "QLogic NetXtreme II BCM5708 1000Base-T" },
 170
 171         /* BCM5708S controllers and OEM boards. */
 172         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
 173                 "HP NC373m Multifunction Gigabit Server Adapter" },
 174         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
 175                 "HP NC373i Multifunction Gigabit Server Adapter" },
 176         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
 177                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
 178         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 179                 "QLogic NetXtreme II BCM5708 1000Base-SX" },
 180
 181         /* BCM5709C controllers and OEM boards. */
 182         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
 183                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 184         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
 185                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
 186         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
 187                 "QLogic NetXtreme II BCM5709 1000Base-T" },
 188
 189         /* BCM5709S controllers and OEM boards. */
 190         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
 191                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
 192         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
 193                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 194         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
 195                 "QLogic NetXtreme II BCM5709 1000Base-SX" },
 196
 197         /* BCM5716 controllers and OEM boards. */
 198         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,  PCI_ANY_ID,  PCI_ANY_ID,
 199                 "QLogic NetXtreme II BCM5716 1000Base-T" },
 200
 201         { 0, 0, 0, 0, NULL }
 202 };
 203
 204
 205 /****************************************************************************/
 206 /* Supported Flash NVRAM device data.                                       */
 207 /****************************************************************************/
 208 static const struct flash_spec flash_table[] =
 209 {
 210 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
 211 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
 212
 213         /* Slow EEPROM */
 214         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 215          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 216          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 217          "EEPROM - slow"},
 218         /* Expansion entry 0001 */
 219         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 220          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 221          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 222          "Entry 0001"},
 223         /* Saifun SA25F010 (non-buffered flash) */
 224         /* strap, cfg1, & write1 need updates */
 225         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 226          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 227          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 228          "Non-buffered flash (128kB)"},
 229         /* Saifun SA25F020 (non-buffered flash) */
 230         /* strap, cfg1, & write1 need updates */
 231         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 232          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 233          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 234          "Non-buffered flash (256kB)"},
 235         /* Expansion entry 0100 */
 236         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 237          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 238          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 239          "Entry 0100"},
 240         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 241         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 242          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 243          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 244          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 245         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 246         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 247          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 248          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 249          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 250         /* Saifun SA25F005 (non-buffered flash) */
 251         /* strap, cfg1, & write1 need updates */
 252         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 253          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 254          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 255          "Non-buffered flash (64kB)"},
 256         /* Fast EEPROM */
 257         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 258          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 259          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 260          "EEPROM - fast"},
 261         /* Expansion entry 1001 */
 262         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 263          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 264          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 265          "Entry 1001"},
 266         /* Expansion entry 1010 */
 267         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 268          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 269          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 270          "Entry 1010"},
 271         /* ATMEL AT45DB011B (buffered flash) */
 272         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 273          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 274          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 275          "Buffered flash (128kB)"},
 276         /* Expansion entry 1100 */
 277         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 278          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 279          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 280          "Entry 1100"},
 281         /* Expansion entry 1101 */
 282         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 283          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 284          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 285          "Entry 1101"},
 286         /* Ateml Expansion entry 1110 */
 287         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 288          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 289          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 290          "Entry 1110 (Atmel)"},
 291         /* ATMEL AT45DB021B (buffered flash) */
 292         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 293          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 294          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 295          "Buffered flash (256kB)"},
 296 };
 297
 298 /*
 299  * The BCM5709 controllers transparently handle the
 300  * differences between Atmel 264 byte pages and all
 301  * flash devices which use 256 byte pages, so no
 302  * logical-to-physical mapping is required in the
 303  * driver.
 304  */
 305 static const struct flash_spec flash_5709 = {
 306         .flags          = BCE_NV_BUFFERED,
 307         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 308         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 309         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 310         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
 311         .name           = "5709/5716 buffered flash (256kB)",
 312 };
 313
 314
 315 /****************************************************************************/
 316 /* FreeBSD device entry points.                                             */
 317 /****************************************************************************/
 318 static int  bce_probe                   (device_t);
 319 static int  bce_attach                  (device_t);
 320 static int  bce_detach                  (device_t);
 321 static int  bce_shutdown                (device_t);
 322
 323
 324 /****************************************************************************/
 325 /* BCE Debug Data Structure Dump Routines                                   */
 326 /****************************************************************************/
 327 #ifdef BCE_DEBUG
 328 static u32  bce_reg_rd                          (struct bce_softc *, u32);
 329 static void bce_reg_wr                          (struct bce_softc *, u32, u32);
 330 static void bce_reg_wr16                        (struct bce_softc *, u32, u16);
 331 static u32  bce_ctx_rd                          (struct bce_softc *, u32, u32);
 332 static void bce_dump_enet                       (struct bce_softc *, struct mbuf *);
 333 static void bce_dump_mbuf                       (struct bce_softc *, struct mbuf *);
 334 static void bce_dump_tx_mbuf_chain      (struct bce_softc *, u16, int);
 335 static void bce_dump_rx_mbuf_chain      (struct bce_softc *, u16, int);
 336 static void bce_dump_pg_mbuf_chain      (struct bce_softc *, u16, int);
 337 static void bce_dump_txbd                       (struct bce_softc *,
 338     int, struct tx_bd *);
 339 static void bce_dump_rxbd                       (struct bce_softc *,
 340     int, struct rx_bd *);
 341 static void bce_dump_pgbd                       (struct bce_softc *,
 342     int, struct rx_bd *);
 343 static void bce_dump_l2fhdr             (struct bce_softc *,
 344     int, struct l2_fhdr *);
 345 static void bce_dump_ctx                        (struct bce_softc *, u16);
 346 static void bce_dump_ftqs                       (struct bce_softc *);
 347 static void bce_dump_tx_chain           (struct bce_softc *, u16, int);
 348 static void bce_dump_rx_bd_chain        (struct bce_softc *, u16, int);
 349 static void bce_dump_pg_chain           (struct bce_softc *, u16, int);
 350 static void bce_dump_status_block       (struct bce_softc *);
 351 static void bce_dump_stats_block        (struct bce_softc *);
 352 static void bce_dump_driver_state       (struct bce_softc *);
 353 static void bce_dump_hw_state           (struct bce_softc *);
 354 static void bce_dump_shmem_state        (struct bce_softc *);
 355 static void bce_dump_mq_regs            (struct bce_softc *);
 356 static void bce_dump_bc_state           (struct bce_softc *);
 357 static void bce_dump_txp_state          (struct bce_softc *, int);
 358 static void bce_dump_rxp_state          (struct bce_softc *, int);
 359 static void bce_dump_tpat_state (struct bce_softc *, int);
 360 static void bce_dump_cp_state           (struct bce_softc *, int);
 361 static void bce_dump_com_state          (struct bce_softc *, int);
 362 static void bce_dump_rv2p_state (struct bce_softc *);
 363 static void bce_breakpoint                      (struct bce_softc *);
 364 #endif /*BCE_DEBUG */
 365
 366
 367 /****************************************************************************/
 368 /* BCE Register/Memory Access Routines                                      */
 369 /****************************************************************************/
 370 static u32  bce_reg_rd_ind              (struct bce_softc *, u32);
 371 static void bce_reg_wr_ind              (struct bce_softc *, u32, u32);
 372 static void bce_shmem_wr                (struct bce_softc *, u32, u32);
 373 static u32  bce_shmem_rd                (struct bce_softc *, u32);
 374 static void bce_ctx_wr                  (struct bce_softc *, u32, u32, u32);
 375 static int  bce_miibus_read_reg         (device_t, int, int);
 376 static int  bce_miibus_write_reg        (device_t, int, int, int);
 377 static void bce_miibus_statchg          (device_t);
 378
 379 #ifdef BCE_DEBUG
 380 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS);
 381 #ifdef BCE_NVRAM_WRITE_SUPPORT
 382 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS);
 383 #endif
 384 #endif
 385
 386 /****************************************************************************/
 387 /* BCE NVRAM Access Routines                                                */
 388 /****************************************************************************/
 389 static int  bce_acquire_nvram_lock      (struct bce_softc *);
 390 static int  bce_release_nvram_lock      (struct bce_softc *);
 391 static void bce_enable_nvram_access(struct bce_softc *);
 392 static void bce_disable_nvram_access(struct bce_softc *);
 393 static int  bce_nvram_read_dword        (struct bce_softc *, u32, u8 *, u32);
 394 static int  bce_init_nvram                      (struct bce_softc *);
 395 static int  bce_nvram_read                      (struct bce_softc *, u32, u8 *, int);
 396 static int  bce_nvram_test                      (struct bce_softc *);
 397 #ifdef BCE_NVRAM_WRITE_SUPPORT
 398 static int  bce_enable_nvram_write      (struct bce_softc *);
 399 static void bce_disable_nvram_write(struct bce_softc *);
 400 static int  bce_nvram_erase_page        (struct bce_softc *, u32);
 401 static int  bce_nvram_write_dword       (struct bce_softc *, u32, u8 *, u32);
 402 static int  bce_nvram_write             (struct bce_softc *, u32, u8 *, int);
 403 #endif
 404
 405 /****************************************************************************/
 406 /*                                                                          */
 407 /****************************************************************************/
 408 static void bce_get_rx_buffer_sizes(struct bce_softc *, int);
 409 static void bce_get_media                       (struct bce_softc *);
 410 static void bce_init_media                      (struct bce_softc *);
 411 static u32 bce_get_rphy_link            (struct bce_softc *);
 412 static void bce_dma_map_addr            (void *, bus_dma_segment_t *, int, int);
 413 static int  bce_dma_alloc                       (device_t);
 414 static void bce_dma_free                        (struct bce_softc *);
 415 static void bce_release_resources       (struct bce_softc *);
 416
 417 /****************************************************************************/
 418 /* BCE Firmware Synchronization and Load                                    */
 419 /****************************************************************************/
 420 static void bce_fw_cap_init                     (struct bce_softc *);
 421 static int  bce_fw_sync                 (struct bce_softc *, u32);
 422 static void bce_load_rv2p_fw            (struct bce_softc *, const u32 *, u32,
 423     u32);
 424 static void bce_load_cpu_fw             (struct bce_softc *,
 425     struct cpu_reg *, struct fw_info *);
 426 static void bce_start_cpu                       (struct bce_softc *, struct cpu_reg *);
 427 static void bce_halt_cpu                        (struct bce_softc *, struct cpu_reg *);
 428 static void bce_start_rxp_cpu           (struct bce_softc *);
 429 static void bce_init_rxp_cpu            (struct bce_softc *);
 430 static void bce_init_txp_cpu            (struct bce_softc *);
 431 static void bce_init_tpat_cpu           (struct bce_softc *);
 432 static void bce_init_cp_cpu             (struct bce_softc *);
 433 static void bce_init_com_cpu            (struct bce_softc *);
 434 static void bce_init_cpus                       (struct bce_softc *);
 435
 436 static void bce_print_adapter_info      (struct bce_softc *);
 437 static void bce_probe_pci_caps          (device_t, struct bce_softc *);
 438 static void bce_stop                            (struct bce_softc *);
 439 static int  bce_reset                           (struct bce_softc *, u32);
 440 static int  bce_chipinit                        (struct bce_softc *);
 441 static int  bce_blockinit                       (struct bce_softc *);
 442
 443 static int  bce_init_tx_chain           (struct bce_softc *);
 444 static void bce_free_tx_chain           (struct bce_softc *);
 445
 446 static int  bce_get_rx_buf              (struct bce_softc *, u16, u16, u32 *);
 447 static int  bce_init_rx_chain           (struct bce_softc *);
 448 static void bce_fill_rx_chain           (struct bce_softc *);
 449 static void bce_free_rx_chain           (struct bce_softc *);
 450
 451 static int  bce_get_pg_buf              (struct bce_softc *, u16, u16);
 452 static int  bce_init_pg_chain           (struct bce_softc *);
 453 static void bce_fill_pg_chain           (struct bce_softc *);
 454 static void bce_free_pg_chain           (struct bce_softc *);
 455
 456 static struct mbuf *bce_tso_setup       (struct bce_softc *,
 457     struct mbuf **, u16 *);
 458 static int  bce_tx_encap                        (struct bce_softc *, struct mbuf **);
 459 static void bce_start_locked            (struct ifnet *);
 460 static void bce_start                           (struct ifnet *);
 461 static int  bce_ioctl                           (struct ifnet *, u_long, caddr_t);
 462 static void bce_watchdog                        (struct bce_softc *);
 463 static int  bce_ifmedia_upd             (struct ifnet *);
 464 static int  bce_ifmedia_upd_locked      (struct ifnet *);
 465 static void bce_ifmedia_sts             (struct ifnet *, struct ifmediareq *);
 466 static void bce_ifmedia_sts_rphy        (struct bce_softc *, struct ifmediareq *);
 467 static void bce_init_locked             (struct bce_softc *);
 468 static void bce_init                            (void *);
 469 static void bce_mgmt_init_locked        (struct bce_softc *sc);
 470
 471 static int  bce_init_ctx                        (struct bce_softc *);
 472 static void bce_get_mac_addr            (struct bce_softc *);
 473 static void bce_set_mac_addr            (struct bce_softc *);
 474 static void bce_phy_intr                        (struct bce_softc *);
 475 static inline u16 bce_get_hw_rx_cons    (struct bce_softc *);
 476 static void bce_rx_intr                 (struct bce_softc *);
 477 static void bce_tx_intr                 (struct bce_softc *);
 478 static void bce_disable_intr            (struct bce_softc *);
 479 static void bce_enable_intr             (struct bce_softc *, int);
 480
 481 static void bce_intr                            (void *);
 482 static void bce_set_rx_mode             (struct bce_softc *);
 483 static void bce_stats_update            (struct bce_softc *);
 484 static void bce_tick                            (void *);
 485 static void bce_pulse                           (void *);
 486 static void bce_add_sysctls             (struct bce_softc *);
 487
 488
 489 /****************************************************************************/
 490 /* FreeBSD device dispatch table.                                           */
 491 /****************************************************************************/
 492 static device_method_t bce_methods[] = {
 493         /* Device interface (device_if.h) */
 494         DEVMETHOD(device_probe,         bce_probe),
 495         DEVMETHOD(device_attach,        bce_attach),
 496         DEVMETHOD(device_detach,        bce_detach),
 497         DEVMETHOD(device_shutdown,      bce_shutdown),
 498 /* Supported by device interface but not used here. */
 499 /*      DEVMETHOD(device_identify,      bce_identify),      */
 500 /*      DEVMETHOD(device_suspend,       bce_suspend),       */
 501 /*      DEVMETHOD(device_resume,        bce_resume),        */
 502 /*      DEVMETHOD(device_quiesce,       bce_quiesce),       */
 503
 504         /* MII interface (miibus_if.h) */
 505         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 506         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 507         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 508 /* Supported by MII interface but not used here.       */
 509 /*      DEVMETHOD(miibus_linkchg,       bce_miibus_linkchg),   */
 510 /*      DEVMETHOD(miibus_mediainit,     bce_miibus_mediainit), */
 511
 512         DEVMETHOD_END
 513 };
 514
 515 static driver_t bce_driver = {
 516         "bce",
 517         bce_methods,
 518         sizeof(struct bce_softc)
 519 };
 520
 521 static devclass_t bce_devclass;
 522
 523 MODULE_DEPEND(bce, pci, 1, 1, 1);
 524 MODULE_DEPEND(bce, ether, 1, 1, 1);
 525 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 526
 527 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, NULL, NULL);
 528 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
 529
 530
 531 /****************************************************************************/
 532 /* Tunable device values                                                    */
 533 /****************************************************************************/
 534 static SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters");
 535
 536 /* Allowable values are TRUE or FALSE */
 537 static int bce_verbose = TRUE;
 538 TUNABLE_INT("hw.bce.verbose", &bce_verbose);
 539 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0,
 540     "Verbose output enable/disable");
 541
 542 /* Allowable values are TRUE or FALSE */
 543 static int bce_tso_enable = TRUE;
 544 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable);
 545 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0,
 546     "TSO Enable/Disable");
 547
 548 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
 549 /* ToDo: Add MSI-X support. */
 550 static int bce_msi_enable = 1;
 551 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable);
 552 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0,
 553     "MSI-X|MSI|INTx selector");
 554
 555 /* Allowable values are 1, 2, 4, 8. */
 556 static int bce_rx_pages = DEFAULT_RX_PAGES;
 557 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages);
 558 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0,
 559     "Receive buffer descriptor pages (1 page = 255 buffer descriptors)");
 560
 561 /* Allowable values are 1, 2, 4, 8. */
 562 static int bce_tx_pages = DEFAULT_TX_PAGES;
 563 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages);
 564 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0,
 565     "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)");
 566
 567 /* Allowable values are TRUE or FALSE. */
 568 static int bce_hdr_split = TRUE;
 569 TUNABLE_INT("hw.bce.hdr_split", &bce_hdr_split);
 570 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0,
 571     "Frame header/payload splitting Enable/Disable");
 572
 573 /* Allowable values are TRUE or FALSE. */
 574 static int bce_strict_rx_mtu = FALSE;
 575 TUNABLE_INT("hw.bce.strict_rx_mtu", &bce_strict_rx_mtu);
 576 SYSCTL_UINT(_hw_bce, OID_AUTO, strict_rx_mtu, CTLFLAG_RDTUN,
 577     &bce_strict_rx_mtu, 0,
 578     "Enable/Disable strict RX frame size checking");
 579
 580 /* Allowable values are 0 ... 100 */
 581 #ifdef BCE_DEBUG
 582 /* Generate 1 interrupt for every transmit completion. */
 583 static int bce_tx_quick_cons_trip_int = 1;
 584 #else
 585 /* Generate 1 interrupt for every 20 transmit completions. */
 586 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT;
 587 #endif
 588 TUNABLE_INT("hw.bce.tx_quick_cons_trip_int", &bce_tx_quick_cons_trip_int);
 589 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN,
 590     &bce_tx_quick_cons_trip_int, 0,
 591     "Transmit BD trip point during interrupts");
 592
 593 /* Allowable values are 0 ... 100 */
 594 /* Generate 1 interrupt for every transmit completion. */
 595 #ifdef BCE_DEBUG
 596 static int bce_tx_quick_cons_trip = 1;
 597 #else
 598 /* Generate 1 interrupt for every 20 transmit completions. */
 599 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
 600 #endif
 601 TUNABLE_INT("hw.bce.tx_quick_cons_trip", &bce_tx_quick_cons_trip);
 602 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN,
 603     &bce_tx_quick_cons_trip, 0,
 604     "Transmit BD trip point");
 605
 606 /* Allowable values are 0 ... 100 */
 607 #ifdef BCE_DEBUG
 608 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
 609 static int bce_tx_ticks_int = 0;
 610 #else
 611 /* Generate an interrupt if 80us have elapsed since the last TX completion. */
 612 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT;
 613 #endif
 614 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
 615 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN,
 616     &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt");
 617
 618 /* Allowable values are 0 ... 100 */
 619 #ifdef BCE_DEBUG
 620 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
 621 static int bce_tx_ticks = 0;
 622 #else
 623 /* Generate an interrupt if 80us have elapsed since the last TX completion. */
 624 static int bce_tx_ticks = DEFAULT_TX_TICKS;
 625 #endif
 626 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
 627 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN,
 628     &bce_tx_ticks, 0, "Transmit ticks count");
 629
 630 /* Allowable values are 1 ... 100 */
 631 #ifdef BCE_DEBUG
 632 /* Generate 1 interrupt for every received frame. */
 633 static int bce_rx_quick_cons_trip_int = 1;
 634 #else
 635 /* Generate 1 interrupt for every 6 received frames. */
 636 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT;
 637 #endif
 638 TUNABLE_INT("hw.bce.rx_quick_cons_trip_int", &bce_rx_quick_cons_trip_int);
 639 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN,
 640     &bce_rx_quick_cons_trip_int, 0,
 641     "Receive BD trip point duirng interrupts");
 642
 643 /* Allowable values are 1 ... 100 */
 644 #ifdef BCE_DEBUG
 645 /* Generate 1 interrupt for every received frame. */
 646 static int bce_rx_quick_cons_trip = 1;
 647 #else
 648 /* Generate 1 interrupt for every 6 received frames. */
 649 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP;
 650 #endif
 651 TUNABLE_INT("hw.bce.rx_quick_cons_trip", &bce_rx_quick_cons_trip);
 652 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN,
 653     &bce_rx_quick_cons_trip, 0,
 654     "Receive BD trip point");
 655
 656 /* Allowable values are 0 ... 100 */
 657 #ifdef BCE_DEBUG
 658 /* Generate an int. if 0us have elapsed since the last received frame. */
 659 static int bce_rx_ticks_int = 0;
 660 #else
 661 /* Generate an int. if 18us have elapsed since the last received frame. */
 662 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT;
 663 #endif
 664 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
 665 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN,
 666     &bce_rx_ticks_int, 0, "Receive ticks count during interrupt");
 667
 668 /* Allowable values are 0 ... 100 */
 669 #ifdef BCE_DEBUG
 670 /* Generate an int. if 0us have elapsed since the last received frame. */
 671 static int bce_rx_ticks = 0;
 672 #else
 673 /* Generate an int. if 18us have elapsed since the last received frame. */
 674 static int bce_rx_ticks = DEFAULT_RX_TICKS;
 675 #endif
 676 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
 677 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN,
 678     &bce_rx_ticks, 0, "Receive ticks count");
 679
 680
 681 /****************************************************************************/
 682 /* Device probe function.                                                   */
 683 /*                                                                          */
 684 /* Compares the device to the driver's list of supported devices and        */
 685 /* reports back to the OS whether this is the right driver for the device.  */
 686 /*                                                                          */
 687 /* Returns:                                                                 */
 688 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 689 /****************************************************************************/
 690 static int
 691 bce_probe(device_t dev)
 692 {
 693         const struct bce_type *t;
 694         struct bce_softc *sc;
 695         char *descbuf;
 696         u16 vid = 0, did = 0, svid = 0, sdid = 0;
 697
 698         t = bce_devs;
 699
 700         sc = device_get_softc(dev);
 701         sc->bce_unit = device_get_unit(dev);
 702         sc->bce_dev = dev;
 703
 704         /* Get the data for the device to be probed. */
 705         vid  = pci_get_vendor(dev);
 706         did  = pci_get_device(dev);
 707         svid = pci_get_subvendor(dev);
 708         sdid = pci_get_subdevice(dev);
 709
 710         DBPRINT(sc, BCE_EXTREME_LOAD,
 711             "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
 712             "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
 713
 714         /* Look through the list of known devices for a match. */
 715         while(t->bce_name != NULL) {
 716
 717                 if ((vid == t->bce_vid) && (did == t->bce_did) &&
 718                     ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) &&
 719                     ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) {
 720
 721                         descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
 722
 723                         if (descbuf == NULL)
 724                                 return(ENOMEM);
 725
 726                         /* Print out the device identity. */
 727                         snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 728                             t->bce_name, (((pci_read_config(dev,
 729                             PCIR_REVID, 4) & 0xf0) >> 4) + 'A'),
 730                             (pci_read_config(dev, PCIR_REVID, 4) & 0xf));
 731
 732                         device_set_desc_copy(dev, descbuf);
 733                         free(descbuf, M_TEMP);
 734                         return(BUS_PROBE_DEFAULT);
 735                 }
 736                 t++;
 737         }
 738
 739         return(ENXIO);
 740 }
 741
 742
 743 /****************************************************************************/
 744 /* PCI Capabilities Probe Function.                                         */
 745 /*                                                                          */
 746 /* Walks the PCI capabiites list for the device to find what features are   */
 747 /* supported.                                                               */
 748 /*                                                                          */
 749 /* Returns:                                                                 */
 750 /*   None.                                                                  */
 751 /****************************************************************************/
 752 static void
 753 bce_print_adapter_info(struct bce_softc *sc)
 754 {
 755         int i = 0;
 756
 757         DBENTER(BCE_VERBOSE_LOAD);
 758
 759         if (bce_verbose || bootverbose) {
 760                 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid);
 761                 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >>
 762                     12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
 763
 764
 765                 /* Bus info. */
 766                 if (sc->bce_flags & BCE_PCIE_FLAG) {
 767                         printf("Bus (PCIe x%d, ", sc->link_width);
 768                         switch (sc->link_speed) {
 769                         case 1: printf("2.5Gbps); "); break;
 770                         case 2: printf("5Gbps); "); break;
 771                         default: printf("Unknown link speed); ");
 772                         }
 773                 } else {
 774                         printf("Bus (PCI%s, %s, %dMHz); ",
 775                             ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
 776                             ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ?
 777                             "32-bit" : "64-bit"), sc->bus_speed_mhz);
 778                 }
 779
 780                 /* Firmware version and device features. */
 781                 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (",
 782                     sc->bce_bc_ver,     sc->rx_pages, sc->tx_pages,
 783                     (bce_hdr_split == TRUE ? sc->pg_pages: 0));
 784
 785                 if (bce_hdr_split == TRUE) {
 786                         printf("SPLT");
 787                         i++;
 788                 }
 789
 790                 if (sc->bce_flags & BCE_USING_MSI_FLAG) {
 791                         if (i > 0) printf("|");
 792                         printf("MSI"); i++;
 793                 }
 794
 795                 if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
 796                         if (i > 0) printf("|");
 797                         printf("MSI-X"); i++;
 798                 }
 799
 800                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
 801                         if (i > 0) printf("|");
 802                         printf("2.5G"); i++;
 803                 }
 804
 805                 if (sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) {
 806                         if (i > 0) printf("|");
 807                         printf("Remote PHY(%s)",
 808                             sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG ?
 809                             "FIBER" : "TP"); i++;
 810                 }
 811
 812                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
 813                         if (i > 0) printf("|");
 814                         printf("MFW); MFW (%s)\n", sc->bce_mfw_ver);
 815                 } else {
 816                         printf(")\n");
 817                 }
 818
 819                 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n",
 820                     sc->bce_rx_quick_cons_trip_int,
 821                     sc->bce_rx_quick_cons_trip,
 822                     sc->bce_rx_ticks_int,
 823                     sc->bce_rx_ticks,
 824                     sc->bce_tx_quick_cons_trip_int,
 825                     sc->bce_tx_quick_cons_trip,
 826                     sc->bce_tx_ticks_int,
 827                     sc->bce_tx_ticks);
 828
 829         }
 830
 831         DBEXIT(BCE_VERBOSE_LOAD);
 832 }
 833
 834
 835 /****************************************************************************/
 836 /* PCI Capabilities Probe Function.                                         */
 837 /*                                                                          */
 838 /* Walks the PCI capabiites list for the device to find what features are   */
 839 /* supported.                                                               */
 840 /*                                                                          */
 841 /* Returns:                                                                 */
 842 /*   None.                                                                  */
 843 /****************************************************************************/
 844 static void
 845 bce_probe_pci_caps(device_t dev, struct bce_softc *sc)
 846 {
 847         u32 reg;
 848
 849         DBENTER(BCE_VERBOSE_LOAD);
 850
 851         /* Check if PCI-X capability is enabled. */
 852         if (pci_find_cap(dev, PCIY_PCIX, &reg) == 0) {
 853                 if (reg != 0)
 854                         sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
 855         }
 856
 857         /* Check if PCIe capability is enabled. */
 858         if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
 859                 if (reg != 0) {
 860                         u16 link_status = pci_read_config(dev, reg + 0x12, 2);
 861                         DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = "
 862                             "0x%08X\n", link_status);
 863                         sc->link_speed = link_status & 0xf;
 864                         sc->link_width = (link_status >> 4) & 0x3f;
 865                         sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
 866                         sc->bce_flags |= BCE_PCIE_FLAG;
 867                 }
 868         }
 869
 870         /* Check if MSI capability is enabled. */
 871         if (pci_find_cap(dev, PCIY_MSI, &reg) == 0) {
 872                 if (reg != 0)
 873                         sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG;
 874         }
 875
 876         /* Check if MSI-X capability is enabled. */
 877         if (pci_find_cap(dev, PCIY_MSIX, &reg) == 0) {
 878                 if (reg != 0)
 879                         sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG;
 880         }
 881
 882         DBEXIT(BCE_VERBOSE_LOAD);
 883 }
 884
 885
 886 /****************************************************************************/
 887 /* Load and validate user tunable settings.                                 */
 888 /*                                                                          */
 889 /* Returns:                                                                 */
 890 /*   Nothing.                                                               */
 891 /****************************************************************************/
 892 static void
 893 bce_set_tunables(struct bce_softc *sc)
 894 {
 895         /* Set sysctl values for RX page count. */
 896         switch (bce_rx_pages) {
 897         case 1:
 898                 /* fall-through */
 899         case 2:
 900                 /* fall-through */
 901         case 4:
 902                 /* fall-through */
 903         case 8:
 904                 sc->rx_pages = bce_rx_pages;
 905                 break;
 906         default:
 907                 sc->rx_pages = DEFAULT_RX_PAGES;
 908                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 909                     "hw.bce.rx_pages!  Setting default of %d.\n",
 910                     __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES);
 911         }
 912
 913         /* ToDo: Consider allowing user setting for pg_pages. */
 914         sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES);
 915
 916         /* Set sysctl values for TX page count. */
 917         switch (bce_tx_pages) {
 918         case 1:
 919                 /* fall-through */
 920         case 2:
 921                 /* fall-through */
 922         case 4:
 923                 /* fall-through */
 924         case 8:
 925                 sc->tx_pages = bce_tx_pages;
 926                 break;
 927         default:
 928                 sc->tx_pages = DEFAULT_TX_PAGES;
 929                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 930                     "hw.bce.tx_pages!  Setting default of %d.\n",
 931                     __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES);
 932         }
 933
 934         /*
 935          * Validate the TX trip point (i.e. the number of
 936          * TX completions before a status block update is
 937          * generated and an interrupt is asserted.
 938          */
 939         if (bce_tx_quick_cons_trip_int <= 100) {
 940                 sc->bce_tx_quick_cons_trip_int =
 941                     bce_tx_quick_cons_trip_int;
 942         } else {
 943                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 944                     "hw.bce.tx_quick_cons_trip_int!  Setting default of %d.\n",
 945                     __FILE__, __LINE__, bce_tx_quick_cons_trip_int,
 946                     DEFAULT_TX_QUICK_CONS_TRIP_INT);
 947                 sc->bce_tx_quick_cons_trip_int =
 948                     DEFAULT_TX_QUICK_CONS_TRIP_INT;
 949         }
 950
 951         if (bce_tx_quick_cons_trip <= 100) {
 952                 sc->bce_tx_quick_cons_trip =
 953                     bce_tx_quick_cons_trip;
 954         } else {
 955                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 956                     "hw.bce.tx_quick_cons_trip!  Setting default of %d.\n",
 957                     __FILE__, __LINE__, bce_tx_quick_cons_trip,
 958                     DEFAULT_TX_QUICK_CONS_TRIP);
 959                 sc->bce_tx_quick_cons_trip =
 960                     DEFAULT_TX_QUICK_CONS_TRIP;
 961         }
 962
 963         /*
 964          * Validate the TX ticks count (i.e. the maximum amount
 965          * of time to wait after the last TX completion has
 966          * occurred before a status block update is generated
 967          * and an interrupt is asserted.
 968          */
 969         if (bce_tx_ticks_int <= 100) {
 970                 sc->bce_tx_ticks_int =
 971                     bce_tx_ticks_int;
 972         } else {
 973                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 974                     "hw.bce.tx_ticks_int!  Setting default of %d.\n",
 975                     __FILE__, __LINE__, bce_tx_ticks_int,
 976                     DEFAULT_TX_TICKS_INT);
 977                 sc->bce_tx_ticks_int =
 978                     DEFAULT_TX_TICKS_INT;
 979            }
 980
 981         if (bce_tx_ticks <= 100) {
 982                 sc->bce_tx_ticks =
 983                     bce_tx_ticks;
 984         } else {
 985                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 986                     "hw.bce.tx_ticks!  Setting default of %d.\n",
 987                     __FILE__, __LINE__, bce_tx_ticks,
 988                     DEFAULT_TX_TICKS);
 989                 sc->bce_tx_ticks =
 990                     DEFAULT_TX_TICKS;
 991         }
 992
 993         /*
 994          * Validate the RX trip point (i.e. the number of
 995          * RX frames received before a status block update is
 996          * generated and an interrupt is asserted.
 997          */
 998         if (bce_rx_quick_cons_trip_int <= 100) {
 999                 sc->bce_rx_quick_cons_trip_int =
1000                     bce_rx_quick_cons_trip_int;
1001         } else {
1002                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
1003                     "hw.bce.rx_quick_cons_trip_int!  Setting default of %d.\n",
1004                     __FILE__, __LINE__, bce_rx_quick_cons_trip_int,
1005                     DEFAULT_RX_QUICK_CONS_TRIP_INT);
1006                 sc->bce_rx_quick_cons_trip_int =
1007                     DEFAULT_RX_QUICK_CONS_TRIP_INT;
1008         }
1009
1010         if (bce_rx_quick_cons_trip <= 100) {
1011                 sc->bce_rx_quick_cons_trip =
1012                     bce_rx_quick_cons_trip;
1013         } else {
1014                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
1015                     "hw.bce.rx_quick_cons_trip!  Setting default of %d.\n",
1016                     __FILE__, __LINE__, bce_rx_quick_cons_trip,
1017                     DEFAULT_RX_QUICK_CONS_TRIP);
1018                 sc->bce_rx_quick_cons_trip =
1019                     DEFAULT_RX_QUICK_CONS_TRIP;
1020         }
1021
1022         /*
1023          * Validate the RX ticks count (i.e. the maximum amount
1024          * of time to wait after the last RX frame has been
1025          * received before a status block update is generated
1026          * and an interrupt is asserted.
1027          */
1028         if (bce_rx_ticks_int <= 100) {
1029                 sc->bce_rx_ticks_int = bce_rx_ticks_int;
1030         } else {
1031                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
1032                     "hw.bce.rx_ticks_int!  Setting default of %d.\n",
1033                     __FILE__, __LINE__, bce_rx_ticks_int,
1034                     DEFAULT_RX_TICKS_INT);
1035                 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT;
1036         }
1037
1038         if (bce_rx_ticks <= 100) {
1039                 sc->bce_rx_ticks = bce_rx_ticks;
1040         } else {
1041                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
1042                     "hw.bce.rx_ticks!  Setting default of %d.\n",
1043                     __FILE__, __LINE__, bce_rx_ticks,
1044                     DEFAULT_RX_TICKS);
1045                 sc->bce_rx_ticks = DEFAULT_RX_TICKS;
1046         }
1047
1048         /* Disabling both RX ticks and RX trips will prevent interrupts. */
1049         if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) {
1050                 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and "
1051                     "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n",
1052                    __FILE__, __LINE__);
1053                 sc->bce_rx_ticks = DEFAULT_RX_TICKS;
1054                 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP;
1055         }
1056
1057         /* Disabling both TX ticks and TX trips will prevent interrupts. */
1058         if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) {
1059                 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and "
1060                     "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n",
1061                    __FILE__, __LINE__);
1062                 sc->bce_tx_ticks = DEFAULT_TX_TICKS;
1063                 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
1064         }
1065 }
1066
1067
1068 /****************************************************************************/
1069 /* Device attach function.                                                  */
1070 /*                                                                          */
1071 /* Allocates device resources, performs secondary chip identification,      */
1072 /* resets and initializes the hardware, and initializes driver instance     */
1073 /* variables.                                                               */
1074 /*                                                                          */
1075 /* Returns:                                                                 */
1076 /*   0 on success, positive value on failure.                               */
1077 /****************************************************************************/
1078 static int
1079 bce_attach(device_t dev)
1080 {
1081         struct bce_softc *sc;
1082         struct ifnet *ifp;
1083         u32 val;
1084         int count, error, rc = 0, rid;
1085
1086         sc = device_get_softc(dev);
1087         sc->bce_dev = dev;
1088
1089         DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1090
1091         sc->bce_unit = device_get_unit(dev);
1092
1093         /* Set initial device and PHY flags */
1094         sc->bce_flags = 0;
1095         sc->bce_phy_flags = 0;
1096
1097         bce_set_tunables(sc);
1098
1099         pci_enable_busmaster(dev);
1100
1101         /* Allocate PCI memory resources. */
1102         rid = PCIR_BAR(0);
1103         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1104                 &rid, RF_ACTIVE);
1105
1106         if (sc->bce_res_mem == NULL) {
1107                 BCE_PRINTF("%s(%d): PCI memory allocation failed\n",
1108                     __FILE__, __LINE__);
1109                 rc = ENXIO;
1110                 goto bce_attach_fail;
1111         }
1112
1113         /* Get various resource handles. */
1114         sc->bce_btag    = rman_get_bustag(sc->bce_res_mem);
1115         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
1116         sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem);
1117
1118         bce_probe_pci_caps(dev, sc);
1119
1120         rid = 1;
1121         count = 0;
1122 #if 0
1123         /* Try allocating MSI-X interrupts. */
1124         if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) &&
1125                 (bce_msi_enable >= 2) &&
1126                 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1127                 &rid, RF_ACTIVE)) != NULL)) {
1128
1129                 msi_needed = count = 1;
1130
1131                 if (((error = pci_alloc_msix(dev, &count)) != 0) ||
1132                         (count != msi_needed)) {
1133                         BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d,"
1134                                 "Received = %d, error = %d\n", __FILE__, __LINE__,
1135                                 msi_needed, count, error);
1136                         count = 0;
1137                         pci_release_msi(dev);
1138                         bus_release_resource(dev, SYS_RES_MEMORY, rid,
1139                                 sc->bce_res_irq);
1140                         sc->bce_res_irq = NULL;
1141                 } else {
1142                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n",
1143                                 __FUNCTION__);
1144                         sc->bce_flags |= BCE_USING_MSIX_FLAG;
1145                 }
1146         }
1147 #endif
1148
1149         /* Try allocating a MSI interrupt. */
1150         if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) &&
1151                 (bce_msi_enable >= 1) && (count == 0)) {
1152                 count = 1;
1153                 if ((error = pci_alloc_msi(dev, &count)) != 0) {
1154                         BCE_PRINTF("%s(%d): MSI allocation failed! "
1155                             "error = %d\n", __FILE__, __LINE__, error);
1156                         count = 0;
1157                         pci_release_msi(dev);
1158                 } else {
1159                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI "
1160                             "interrupt.\n", __FUNCTION__);
1161                         sc->bce_flags |= BCE_USING_MSI_FLAG;
1162                         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
1163                                 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG;
1164                         rid = 1;
1165                 }
1166         }
1167
1168         /* Try allocating a legacy interrupt. */
1169         if (count == 0) {
1170                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n",
1171                         __FUNCTION__);
1172                 rid = 0;
1173         }
1174
1175         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1176             &rid, RF_ACTIVE | (count != 0 ? 0 : RF_SHAREABLE));
1177
1178         /* Report any IRQ allocation errors. */
1179         if (sc->bce_res_irq == NULL) {
1180                 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n",
1181                     __FILE__, __LINE__);
1182                 rc = ENXIO;
1183                 goto bce_attach_fail;
1184         }
1185
1186         /* Initialize mutex for the current device instance. */
1187         BCE_LOCK_INIT(sc, device_get_nameunit(dev));
1188
1189         /*
1190          * Configure byte swap and enable indirect register access.
1191          * Rely on CPU to do target byte swapping on big endian systems.
1192          * Access to registers outside of PCI configurtion space are not
1193          * valid until this is done.
1194          */
1195         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
1196             BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
1197             BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
1198
1199         /* Save ASIC revsion info. */
1200         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
1201
1202         /* Weed out any non-production controller revisions. */
1203         switch(BCE_CHIP_ID(sc)) {
1204         case BCE_CHIP_ID_5706_A0:
1205         case BCE_CHIP_ID_5706_A1:
1206         case BCE_CHIP_ID_5708_A0:
1207         case BCE_CHIP_ID_5708_B0:
1208         case BCE_CHIP_ID_5709_A0:
1209         case BCE_CHIP_ID_5709_B0:
1210         case BCE_CHIP_ID_5709_B1:
1211         case BCE_CHIP_ID_5709_B2:
1212                 BCE_PRINTF("%s(%d): Unsupported controller "
1213                     "revision (%c%d)!\n", __FILE__, __LINE__,
1214                     (((pci_read_config(dev, PCIR_REVID, 4) &
1215                     0xf0) >> 4) + 'A'), (pci_read_config(dev,
1216                     PCIR_REVID, 4) & 0xf));
1217                 rc = ENODEV;
1218                 goto bce_attach_fail;
1219         }
1220
1221         /*
1222          * The embedded PCIe to PCI-X bridge (EPB)
1223          * in the 5708 cannot address memory above
1224          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
1225          */
1226         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
1227                 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR;
1228         else
1229                 sc->max_bus_addr = BUS_SPACE_MAXADDR;
1230
1231         /*
1232          * Find the base address for shared memory access.
1233          * Newer versions of bootcode use a signature and offset
1234          * while older versions use a fixed address.
1235          */
1236         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
1237         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG)
1238                 /* Multi-port devices use different offsets in shared memory. */
1239                 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 +
1240                     (pci_get_function(sc->bce_dev) << 2));
1241         else
1242                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
1243
1244         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n",
1245             __FUNCTION__, sc->bce_shmem_base);
1246
1247         /* Fetch the bootcode revision. */
1248         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
1249         for (int i = 0, j = 0; i < 3; i++) {
1250                 u8 num;
1251
1252                 num = (u8) (val >> (24 - (i * 8)));
1253                 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
1254                         if (num >= k || !skip0 || k == 1) {
1255                                 sc->bce_bc_ver[j++] = (num / k) + '0';
1256                                 skip0 = 0;
1257                         }
1258                 }
1259
1260                 if (i != 2)
1261                         sc->bce_bc_ver[j++] = '.';
1262         }
1263
1264         /* Check if any management firwmare is enabled. */
1265         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
1266         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
1267                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
1268
1269                 /* Allow time for firmware to enter the running state. */
1270                 for (int i = 0; i < 30; i++) {
1271                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
1272                         if (val & BCE_CONDITION_MFW_RUN_MASK)
1273                                 break;
1274                         DELAY(10000);
1275                 }
1276
1277                 /* Check if management firmware is running. */
1278                 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
1279                 val &= BCE_CONDITION_MFW_RUN_MASK;
1280                 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) &&
1281                     (val != BCE_CONDITION_MFW_RUN_NONE)) {
1282                         u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
1283                         int i = 0;
1284
1285                         /* Read the management firmware version string. */
1286                         for (int j = 0; j < 3; j++) {
1287                                 val = bce_reg_rd_ind(sc, addr + j * 4);
1288                                 val = bswap32(val);
1289                                 memcpy(&sc->bce_mfw_ver[i], &val, 4);
1290                                 i += 4;
1291                         }
1292                 } else {
1293                         /* May cause firmware synchronization timeouts. */
1294                         BCE_PRINTF("%s(%d): Management firmware enabled "
1295                             "but not running!\n", __FILE__, __LINE__);
1296                         strcpy(sc->bce_mfw_ver, "NOT RUNNING!");
1297
1298                         /* ToDo: Any action the driver should take? */
1299                 }
1300         }
1301
1302         /* Get PCI bus information (speed and type). */
1303         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
1304         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
1305                 u32 clkreg;
1306
1307                 sc->bce_flags |= BCE_PCIX_FLAG;
1308
1309                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS);
1310
1311                 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
1312                 switch (clkreg) {
1313                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
1314                         sc->bus_speed_mhz = 133;
1315                         break;
1316
1317                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
1318                         sc->bus_speed_mhz = 100;
1319                         break;
1320
1321                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
1322                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
1323                         sc->bus_speed_mhz = 66;
1324                         break;
1325
1326                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
1327                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
1328                         sc->bus_speed_mhz = 50;
1329                         break;
1330
1331                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
1332                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
1333                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
1334                         sc->bus_speed_mhz = 33;
1335                         break;
1336                 }
1337         } else {
1338                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
1339                         sc->bus_speed_mhz = 66;
1340                 else
1341                         sc->bus_speed_mhz = 33;
1342         }
1343
1344         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
1345                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
1346
1347         /* Find the media type for the adapter. */
1348         bce_get_media(sc);
1349
1350         /* Reset controller and announce to bootcode that driver is present. */
1351         if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
1352                 BCE_PRINTF("%s(%d): Controller reset failed!\n",
1353                     __FILE__, __LINE__);
1354                 rc = ENXIO;
1355                 goto bce_attach_fail;
1356         }
1357
1358         /* Initialize the controller. */
1359         if (bce_chipinit(sc)) {
1360                 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
1361                     __FILE__, __LINE__);
1362                 rc = ENXIO;
1363                 goto bce_attach_fail;
1364         }
1365
1366         /* Perform NVRAM test. */
1367         if (bce_nvram_test(sc)) {
1368                 BCE_PRINTF("%s(%d): NVRAM test failed!\n",
1369                     __FILE__, __LINE__);
1370                 rc = ENXIO;
1371                 goto bce_attach_fail;
1372         }
1373
1374         /* Fetch the permanent Ethernet MAC address. */
1375         bce_get_mac_addr(sc);
1376
1377         /* Update statistics once every second. */
1378         sc->bce_stats_ticks = 1000000 & 0xffff00;
1379
1380         /* Store data needed by PHY driver for backplane applications */
1381         sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
1382         sc->bce_port_hw_cfg   = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG);
1383
1384         /* Allocate DMA memory resources. */
1385         if (bce_dma_alloc(dev)) {
1386                 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n",
1387                     __FILE__, __LINE__);
1388                 rc = ENXIO;
1389                 goto bce_attach_fail;
1390         }
1391
1392         /* Allocate an ifnet structure. */
1393         ifp = sc->bce_ifp = if_alloc(IFT_ETHER);
1394         if (ifp == NULL) {
1395                 BCE_PRINTF("%s(%d): Interface allocation failed!\n",
1396                     __FILE__, __LINE__);
1397                 rc = ENXIO;
1398                 goto bce_attach_fail;
1399         }
1400
1401         /* Initialize the ifnet interface. */
1402         ifp->if_softc   = sc;
1403         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1404         ifp->if_flags   = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1405         ifp->if_ioctl   = bce_ioctl;
1406         ifp->if_start   = bce_start;
1407         ifp->if_init    = bce_init;
1408         ifp->if_mtu     = ETHERMTU;
1409
1410         if (bce_tso_enable) {
1411                 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO;
1412                 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 |
1413                     IFCAP_VLAN_HWTSO;
1414         } else {
1415                 ifp->if_hwassist = BCE_IF_HWASSIST;
1416                 ifp->if_capabilities = BCE_IF_CAPABILITIES;
1417         }
1418
1419 #if __FreeBSD_version >= 800505
1420         /*
1421          * Introducing IFCAP_LINKSTATE didn't bump __FreeBSD_version
1422          * so it's approximate value.
1423          */
1424         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1425                 ifp->if_capabilities |= IFCAP_LINKSTATE;
1426 #endif
1427
1428         ifp->if_capenable = ifp->if_capabilities;
1429
1430         /*
1431          * Assume standard mbuf sizes for buffer allocation.
1432          * This may change later if the MTU size is set to
1433          * something other than 1500.
1434          */
1435         bce_get_rx_buffer_sizes(sc,
1436             (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN));
1437
1438         /* Recalculate our buffer allocation sizes. */
1439         ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC;
1440         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
1441         IFQ_SET_READY(&ifp->if_snd);
1442
1443         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1444                 ifp->if_baudrate = IF_Mbps(2500ULL);
1445         else
1446                 ifp->if_baudrate = IF_Mbps(1000);
1447
1448         /* Handle any special PHY initialization for SerDes PHYs. */
1449         bce_init_media(sc);
1450
1451         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
1452                 ifmedia_init(&sc->bce_ifmedia, IFM_IMASK, bce_ifmedia_upd,
1453                     bce_ifmedia_sts);
1454                 /*
1455                  * We can't manually override remote PHY's link and assume
1456                  * PHY port configuration(Fiber or TP) is not changed after
1457                  * device attach.  This may not be correct though.
1458                  */
1459                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) {
1460                         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
1461                                 ifmedia_add(&sc->bce_ifmedia,
1462                                     IFM_ETHER | IFM_2500_SX, 0, NULL);
1463                                 ifmedia_add(&sc->bce_ifmedia,
1464                                     IFM_ETHER | IFM_2500_SX | IFM_FDX, 0, NULL);
1465                         }
1466                         ifmedia_add(&sc->bce_ifmedia,
1467                             IFM_ETHER | IFM_1000_SX, 0, NULL);
1468                         ifmedia_add(&sc->bce_ifmedia,
1469                             IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL);
1470                 } else {
1471                         ifmedia_add(&sc->bce_ifmedia,
1472                             IFM_ETHER | IFM_10_T, 0, NULL);
1473                         ifmedia_add(&sc->bce_ifmedia,
1474                             IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
1475                         ifmedia_add(&sc->bce_ifmedia,
1476                             IFM_ETHER | IFM_100_TX, 0, NULL);
1477                         ifmedia_add(&sc->bce_ifmedia,
1478                             IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
1479                         ifmedia_add(&sc->bce_ifmedia,
1480                             IFM_ETHER | IFM_1000_T, 0, NULL);
1481                         ifmedia_add(&sc->bce_ifmedia,
1482                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1483                 }
1484                 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
1485                 ifmedia_set(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO);
1486                 sc->bce_ifmedia.ifm_media = sc->bce_ifmedia.ifm_cur->ifm_media;
1487         } else {
1488                 /* MII child bus by attaching the PHY. */
1489                 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd,
1490                     bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr,
1491                     MII_OFFSET_ANY, MIIF_DOPAUSE);
1492                 if (rc != 0) {
1493                         BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__,
1494                             __LINE__);
1495                         goto bce_attach_fail;
1496                 }
1497         }
1498
1499         /* Attach to the Ethernet interface list. */
1500         ether_ifattach(ifp, sc->eaddr);
1501
1502 #if __FreeBSD_version < 500000
1503         callout_init(&sc->bce_tick_callout);
1504         callout_init(&sc->bce_pulse_callout);
1505 #else
1506         callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0);
1507         callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0);
1508 #endif
1509
1510         /* Hookup IRQ last. */
1511         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE,
1512                 NULL, bce_intr, sc, &sc->bce_intrhand);
1513
1514         if (rc) {
1515                 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n",
1516                     __FILE__, __LINE__);
1517                 bce_detach(dev);
1518                 goto bce_attach_exit;
1519         }
1520
1521         /*
1522          * At this point we've acquired all the resources
1523          * we need to run so there's no turning back, we're
1524          * cleared for launch.
1525          */
1526
1527         /* Print some important debugging info. */
1528         DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc));
1529
1530         /* Add the supported sysctls to the kernel. */
1531         bce_add_sysctls(sc);
1532
1533         BCE_LOCK(sc);
1534
1535         /*
1536          * The chip reset earlier notified the bootcode that
1537          * a driver is present.  We now need to start our pulse
1538          * routine so that the bootcode is reminded that we're
1539          * still running.
1540          */
1541         bce_pulse(sc);
1542
1543         bce_mgmt_init_locked(sc);
1544         BCE_UNLOCK(sc);
1545
1546         /* Finally, print some useful adapter info */
1547         bce_print_adapter_info(sc);
1548         DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n",
1549                 __FUNCTION__, sc);
1550
1551         goto bce_attach_exit;
1552
1553 bce_attach_fail:
1554         bce_release_resources(sc);
1555
1556 bce_attach_exit:
1557
1558         DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1559
1560         return(rc);
1561 }
1562
1563
1564 /****************************************************************************/
1565 /* Device detach function.                                                  */
1566 /*                                                                          */
1567 /* Stops the controller, resets the controller, and releases resources.     */
1568 /*                                                                          */
1569 /* Returns:                                                                 */
1570 /*   0 on success, positive value on failure.                               */
1571 /****************************************************************************/
1572 static int
1573 bce_detach(device_t dev)
1574 {
1575         struct bce_softc *sc = device_get_softc(dev);
1576         struct ifnet *ifp;
1577         u32 msg;
1578
1579         DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1580
1581         ifp = sc->bce_ifp;
1582
1583         /* Stop and reset the controller. */
1584         BCE_LOCK(sc);
1585
1586         /* Stop the pulse so the bootcode can go to driver absent state. */
1587         callout_stop(&sc->bce_pulse_callout);
1588
1589         bce_stop(sc);
1590         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1591                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1592         else
1593                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1594         bce_reset(sc, msg);
1595
1596         BCE_UNLOCK(sc);
1597
1598         ether_ifdetach(ifp);
1599
1600         /* If we have a child device on the MII bus remove it too. */
1601         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1602                 ifmedia_removeall(&sc->bce_ifmedia);
1603         else {
1604                 bus_generic_detach(dev);
1605                 device_delete_child(dev, sc->bce_miibus);
1606         }
1607
1608         /* Release all remaining resources. */
1609         bce_release_resources(sc);
1610
1611         DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1612
1613         return(0);
1614 }
1615
1616
1617 /****************************************************************************/
1618 /* Device shutdown function.                                                */
1619 /*                                                                          */
1620 /* Stops and resets the controller.                                         */
1621 /*                                                                          */
1622 /* Returns:                                                                 */
1623 /*   0 on success, positive value on failure.                               */
1624 /****************************************************************************/
1625 static int
1626 bce_shutdown(device_t dev)
1627 {
1628         struct bce_softc *sc = device_get_softc(dev);
1629         u32 msg;
1630
1631         DBENTER(BCE_VERBOSE);
1632
1633         BCE_LOCK(sc);
1634         bce_stop(sc);
1635         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1636                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1637         else
1638                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1639         bce_reset(sc, msg);
1640         BCE_UNLOCK(sc);
1641
1642         DBEXIT(BCE_VERBOSE);
1643
1644         return (0);
1645 }
1646
1647
1648 #ifdef BCE_DEBUG
1649 /****************************************************************************/
1650 /* Register read.                                                           */
1651 /*                                                                          */
1652 /* Returns:                                                                 */
1653 /*   The value of the register.                                             */
1654 /****************************************************************************/
1655 static u32
1656 bce_reg_rd(struct bce_softc *sc, u32 offset)
1657 {
1658         u32 val = REG_RD(sc, offset);
1659         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1660                 __FUNCTION__, offset, val);
1661         return val;
1662 }
1663
1664
1665 /****************************************************************************/
1666 /* Register write (16 bit).                                                 */
1667 /*                                                                          */
1668 /* Returns:                                                                 */
1669 /*   Nothing.                                                               */
1670 /****************************************************************************/
1671 static void
1672 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val)
1673 {
1674         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n",
1675                 __FUNCTION__, offset, val);
1676         REG_WR16(sc, offset, val);
1677 }
1678
1679
1680 /****************************************************************************/
1681 /* Register write.                                                          */
1682 /*                                                                          */
1683 /* Returns:                                                                 */
1684 /*   Nothing.                                                               */
1685 /****************************************************************************/
1686 static void
1687 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val)
1688 {
1689         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1690                 __FUNCTION__, offset, val);
1691         REG_WR(sc, offset, val);
1692 }
1693 #endif
1694
1695 /****************************************************************************/
1696 /* Indirect register read.                                                  */
1697 /*                                                                          */
1698 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1699 /* configuration space.  Using this mechanism avoids issues with posted     */
1700 /* reads but is much slower than memory-mapped I/O.                         */
1701 /*                                                                          */
1702 /* Returns:                                                                 */
1703 /*   The value of the register.                                             */
1704 /****************************************************************************/
1705 static u32
1706 bce_reg_rd_ind(struct bce_softc *sc, u32 offset)
1707 {
1708         device_t dev;
1709         dev = sc->bce_dev;
1710
1711         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1712 #ifdef BCE_DEBUG
1713         {
1714                 u32 val;
1715                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1716                 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1717                         __FUNCTION__, offset, val);
1718                 return val;
1719         }
1720 #else
1721         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1722 #endif
1723 }
1724
1725
1726 /****************************************************************************/
1727 /* Indirect register write.                                                 */
1728 /*                                                                          */
1729 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1730 /* configuration space.  Using this mechanism avoids issues with posted     */
1731 /* writes but is muchh slower than memory-mapped I/O.                       */
1732 /*                                                                          */
1733 /* Returns:                                                                 */
1734 /*   Nothing.                                                               */
1735 /****************************************************************************/
1736 static void
1737 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val)
1738 {
1739         device_t dev;
1740         dev = sc->bce_dev;
1741
1742         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1743                 __FUNCTION__, offset, val);
1744
1745         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1746         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1747 }
1748
1749
1750 /****************************************************************************/
1751 /* Shared memory write.                                                     */
1752 /*                                                                          */
1753 /* Writes NetXtreme II shared memory region.                                */
1754 /*                                                                          */
1755 /* Returns:                                                                 */
1756 /*   Nothing.                                                               */
1757 /****************************************************************************/
1758 static void
1759 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val)
1760 {
1761         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X  to  "
1762             "0x%08X\n", __FUNCTION__, val, offset);
1763
1764         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1765 }
1766
1767
1768 /****************************************************************************/
1769 /* Shared memory read.                                                      */
1770 /*                                                                          */
1771 /* Reads NetXtreme II shared memory region.                                 */
1772 /*                                                                          */
1773 /* Returns:                                                                 */
1774 /*   The 32 bit value read.                                                 */
1775 /****************************************************************************/
1776 static u32
1777 bce_shmem_rd(struct bce_softc *sc, u32 offset)
1778 {
1779         u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1780
1781         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from "
1782             "0x%08X\n", __FUNCTION__, val, offset);
1783
1784         return val;
1785 }
1786
1787
1788 #ifdef BCE_DEBUG
1789 /****************************************************************************/
1790 /* Context memory read.                                                     */
1791 /*                                                                          */
1792 /* The NetXtreme II controller uses context memory to track connection      */
1793 /* information for L2 and higher network protocols.                         */
1794 /*                                                                          */
1795 /* Returns:                                                                 */
1796 /*   The requested 32 bit value of context memory.                          */
1797 /****************************************************************************/
1798 static u32
1799 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset)
1800 {
1801         u32 idx, offset, retry_cnt = 5, val;
1802
1803         DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 ||
1804             cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID "
1805             "address: 0x%08X.\n", __FUNCTION__, cid_addr));
1806
1807         offset = ctx_offset + cid_addr;
1808
1809         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1810
1811                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ));
1812
1813                 for (idx = 0; idx < retry_cnt; idx++) {
1814                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1815                         if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0)
1816                                 break;
1817                         DELAY(5);
1818                 }
1819
1820                 if (val & BCE_CTX_CTX_CTRL_READ_REQ)
1821                         BCE_PRINTF("%s(%d); Unable to read CTX memory: "
1822                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1823                             __FILE__, __LINE__, cid_addr, ctx_offset);
1824
1825                 val = REG_RD(sc, BCE_CTX_CTX_DATA);
1826         } else {
1827                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1828                 val = REG_RD(sc, BCE_CTX_DATA);
1829         }
1830
1831         DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1832                 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val);
1833
1834         return(val);
1835 }
1836 #endif
1837
1838
1839 /****************************************************************************/
1840 /* Context memory write.                                                    */
1841 /*                                                                          */
1842 /* The NetXtreme II controller uses context memory to track connection      */
1843 /* information for L2 and higher network protocols.                         */
1844 /*                                                                          */
1845 /* Returns:                                                                 */
1846 /*   Nothing.                                                               */
1847 /****************************************************************************/
1848 static void
1849 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val)
1850 {
1851         u32 idx, offset = ctx_offset + cid_addr;
1852         u32 val, retry_cnt = 5;
1853
1854         DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1855                 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val);
1856
1857         DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK),
1858                 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n",
1859                     __FUNCTION__, cid_addr));
1860
1861         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1862
1863                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1864                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1865
1866                 for (idx = 0; idx < retry_cnt; idx++) {
1867                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1868                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1869                                 break;
1870                         DELAY(5);
1871                 }
1872
1873                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ)
1874                         BCE_PRINTF("%s(%d); Unable to write CTX memory: "
1875                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1876                             __FILE__, __LINE__, cid_addr, ctx_offset);
1877
1878         } else {
1879                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1880                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1881         }
1882 }
1883
1884
1885 /****************************************************************************/
1886 /* PHY register read.                                                       */
1887 /*                                                                          */
1888 /* Implements register reads on the MII bus.                                */
1889 /*                                                                          */
1890 /* Returns:                                                                 */
1891 /*   The value of the register.                                             */
1892 /****************************************************************************/
1893 static int
1894 bce_miibus_read_reg(device_t dev, int phy, int reg)
1895 {
1896         struct bce_softc *sc;
1897         u32 val;
1898         int i;
1899
1900         sc = device_get_softc(dev);
1901
1902     /*
1903      * The 5709S PHY is an IEEE Clause 45 PHY
1904      * with special mappings to work with IEEE
1905      * Clause 22 register accesses.
1906      */
1907         if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1908                 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1909                         reg += 0x10;
1910         }
1911
1912     if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1913                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1914                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1915
1916                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1917                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1918
1919                 DELAY(40);
1920         }
1921
1922
1923         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1924             BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1925             BCE_EMAC_MDIO_COMM_START_BUSY;
1926         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1927
1928         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1929                 DELAY(10);
1930
1931                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1932                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1933                         DELAY(5);
1934
1935                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1936                         val &= BCE_EMAC_MDIO_COMM_DATA;
1937
1938                         break;
1939                 }
1940         }
1941
1942         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1943                 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, "
1944                     "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg);
1945                 val = 0x0;
1946         } else {
1947                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1948         }
1949
1950
1951         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1952                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1953                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1954
1955                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1956                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1957
1958                 DELAY(40);
1959         }
1960
1961         DB_PRINT_PHY_REG(reg, val);
1962         return (val & 0xffff);
1963 }
1964
1965
1966 /****************************************************************************/
1967 /* PHY register write.                                                      */
1968 /*                                                                          */
1969 /* Implements register writes on the MII bus.                               */
1970 /*                                                                          */
1971 /* Returns:                                                                 */
1972 /*   The value of the register.                                             */
1973 /****************************************************************************/
1974 static int
1975 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1976 {
1977         struct bce_softc *sc;
1978         u32 val1;
1979         int i;
1980
1981         sc = device_get_softc(dev);
1982
1983         DB_PRINT_PHY_REG(reg, val);
1984
1985         /*
1986          * The 5709S PHY is an IEEE Clause 45 PHY
1987          * with special mappings to work with IEEE
1988          * Clause 22 register accesses.
1989          */
1990         if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1991                 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1992                         reg += 0x10;
1993         }
1994
1995         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1996                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1997                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1998
1999                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
2000                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
2001
2002                 DELAY(40);
2003         }
2004
2005         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
2006             BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
2007             BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
2008         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
2009
2010         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
2011                 DELAY(10);
2012
2013                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
2014                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
2015                         DELAY(5);
2016                         break;
2017                 }
2018         }
2019
2020         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
2021                 BCE_PRINTF("%s(%d): PHY write timeout!\n",
2022                     __FILE__, __LINE__);
2023
2024         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
2025                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
2026                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
2027
2028                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
2029                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
2030
2031                 DELAY(40);
2032         }
2033
2034         return 0;
2035 }
2036
2037
2038 /****************************************************************************/
2039 /* MII bus status change.                                                   */
2040 /*                                                                          */
2041 /* Called by the MII bus driver when the PHY establishes link to set the    */
2042 /* MAC interface registers.                                                 */
2043 /*                                                                          */
2044 /* Returns:                                                                 */
2045 /*   Nothing.                                                               */
2046 /****************************************************************************/
2047 static void
2048 bce_miibus_statchg(device_t dev)
2049 {
2050         struct bce_softc *sc;
2051         struct mii_data *mii;
2052         struct ifmediareq ifmr;
2053         int media_active, media_status, val;
2054
2055         sc = device_get_softc(dev);
2056
2057         DBENTER(BCE_VERBOSE_PHY);
2058
2059         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
2060                 bzero(&ifmr, sizeof(ifmr));
2061                 bce_ifmedia_sts_rphy(sc, &ifmr);
2062                 media_active = ifmr.ifm_active;
2063                 media_status = ifmr.ifm_status;
2064         } else {
2065                 mii = device_get_softc(sc->bce_miibus);
2066                 media_active = mii->mii_media_active;
2067                 media_status = mii->mii_media_status;
2068         }
2069
2070         /* Ignore invalid media status. */
2071         if ((media_status & (IFM_ACTIVE | IFM_AVALID)) !=
2072             (IFM_ACTIVE | IFM_AVALID))
2073                 goto bce_miibus_statchg_exit;
2074
2075         val = REG_RD(sc, BCE_EMAC_MODE);
2076         val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX |
2077             BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK |
2078             BCE_EMAC_MODE_25G);
2079
2080         /* Set MII or GMII interface based on the PHY speed. */
2081         switch (IFM_SUBTYPE(media_active)) {
2082         case IFM_10_T:
2083                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2084                         DBPRINT(sc, BCE_INFO_PHY,
2085                             "Enabling 10Mb interface.\n");
2086                         val |= BCE_EMAC_MODE_PORT_MII_10;
2087                         break;
2088                 }
2089                 /* fall-through */
2090         case IFM_100_TX:
2091                 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n");
2092                 val |= BCE_EMAC_MODE_PORT_MII;
2093                 break;
2094         case IFM_2500_SX:
2095                 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n");
2096                 val |= BCE_EMAC_MODE_25G;
2097                 /* fall-through */
2098         case IFM_1000_T:
2099         case IFM_1000_SX:
2100                 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n");
2101                 val |= BCE_EMAC_MODE_PORT_GMII;
2102                 break;
2103         default:
2104                 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling "
2105                     "default GMII interface.\n");
2106                 val |= BCE_EMAC_MODE_PORT_GMII;
2107         }
2108
2109         /* Set half or full duplex based on PHY settings. */
2110         if ((IFM_OPTIONS(media_active) & IFM_FDX) == 0) {
2111                 DBPRINT(sc, BCE_INFO_PHY,
2112                     "Setting Half-Duplex interface.\n");
2113                 val |= BCE_EMAC_MODE_HALF_DUPLEX;
2114         } else
2115                 DBPRINT(sc, BCE_INFO_PHY,
2116                     "Setting Full-Duplex interface.\n");
2117
2118         REG_WR(sc, BCE_EMAC_MODE, val);
2119
2120         if ((IFM_OPTIONS(media_active) & IFM_ETH_RXPAUSE) != 0) {
2121                 DBPRINT(sc, BCE_INFO_PHY,
2122                     "%s(): Enabling RX flow control.\n", __FUNCTION__);
2123                 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
2124                 sc->bce_flags |= BCE_USING_RX_FLOW_CONTROL;
2125         } else {
2126                 DBPRINT(sc, BCE_INFO_PHY,
2127                     "%s(): Disabling RX flow control.\n", __FUNCTION__);
2128                 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
2129                 sc->bce_flags &= ~BCE_USING_RX_FLOW_CONTROL;
2130         }
2131
2132         if ((IFM_OPTIONS(media_active) & IFM_ETH_TXPAUSE) != 0) {
2133                 DBPRINT(sc, BCE_INFO_PHY,
2134                     "%s(): Enabling TX flow control.\n", __FUNCTION__);
2135                 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
2136                 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL;
2137         } else {
2138                 DBPRINT(sc, BCE_INFO_PHY,
2139                     "%s(): Disabling TX flow control.\n", __FUNCTION__);
2140                 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
2141                 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL;
2142         }
2143
2144         /* ToDo: Update watermarks in bce_init_rx_context(). */
2145
2146 bce_miibus_statchg_exit:
2147         DBEXIT(BCE_VERBOSE_PHY);
2148 }
2149
2150
2151 /****************************************************************************/
2152 /* Acquire NVRAM lock.                                                      */
2153 /*                                                                          */
2154 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
2155 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
2156 /* for use by the driver.                                                   */
2157 /*                                                                          */
2158 /* Returns:                                                                 */
2159 /*   0 on success, positive value on failure.                               */
2160 /****************************************************************************/
2161 static int
2162 bce_acquire_nvram_lock(struct bce_softc *sc)
2163 {
2164         u32 val;
2165         int j, rc = 0;
2166
2167         DBENTER(BCE_VERBOSE_NVRAM);
2168
2169         /* Request access to the flash interface. */
2170         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
2171         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2172                 val = REG_RD(sc, BCE_NVM_SW_ARB);
2173                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
2174                         break;
2175
2176                 DELAY(5);
2177         }
2178
2179         if (j >= NVRAM_TIMEOUT_COUNT) {
2180                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
2181                 rc = EBUSY;
2182         }
2183
2184         DBEXIT(BCE_VERBOSE_NVRAM);
2185         return (rc);
2186 }
2187
2188
2189 /****************************************************************************/
2190 /* Release NVRAM lock.                                                      */
2191 /*                                                                          */
2192 /* When the caller is finished accessing NVRAM the lock must be released.   */
2193 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
2194 /* for use by the driver.                                                   */
2195 /*                                                                          */
2196 /* Returns:                                                                 */
2197 /*   0 on success, positive value on failure.                               */
2198 /****************************************************************************/
2199 static int
2200 bce_release_nvram_lock(struct bce_softc *sc)
2201 {
2202         u32 val;
2203         int j, rc = 0;
2204
2205         DBENTER(BCE_VERBOSE_NVRAM);
2206
2207         /*
2208          * Relinquish nvram interface.
2209          */
2210         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
2211
2212         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2213                 val = REG_RD(sc, BCE_NVM_SW_ARB);
2214                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
2215                         break;
2216
2217                 DELAY(5);
2218         }
2219
2220         if (j >= NVRAM_TIMEOUT_COUNT) {
2221                 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n");
2222                 rc = EBUSY;
2223         }
2224
2225         DBEXIT(BCE_VERBOSE_NVRAM);
2226         return (rc);
2227 }
2228
2229
2230 #ifdef BCE_NVRAM_WRITE_SUPPORT
2231 /****************************************************************************/
2232 /* Enable NVRAM write access.                                               */
2233 /*                                                                          */
2234 /* Before writing to NVRAM the caller must enable NVRAM writes.             */
2235 /*                                                                          */
2236 /* Returns:                                                                 */
2237 /*   0 on success, positive value on failure.                               */
2238 /****************************************************************************/
2239 static int
2240 bce_enable_nvram_write(struct bce_softc *sc)
2241 {
2242         u32 val;
2243         int rc = 0;
2244
2245         DBENTER(BCE_VERBOSE_NVRAM);
2246
2247         val = REG_RD(sc, BCE_MISC_CFG);
2248         REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);
2249
2250         if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2251                 int j;
2252
2253                 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2254                 REG_WR(sc, BCE_NVM_COMMAND,     BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT);
2255
2256                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2257                         DELAY(5);
2258
2259                         val = REG_RD(sc, BCE_NVM_COMMAND);
2260                         if (val & BCE_NVM_COMMAND_DONE)
2261                                 break;
2262                 }
2263
2264                 if (j >= NVRAM_TIMEOUT_COUNT) {
2265                         DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n");
2266                         rc = EBUSY;
2267                 }
2268         }
2269
2270         DBENTER(BCE_VERBOSE_NVRAM);
2271         return (rc);
2272 }
2273
2274
2275 /****************************************************************************/
2276 /* Disable NVRAM write access.                                              */
2277 /*                                                                          */
2278 /* When the caller is finished writing to NVRAM write access must be        */
2279 /* disabled.                                                                */
2280 /*                                                                          */
2281 /* Returns:                                                                 */
2282 /*   Nothing.                                                               */
2283 /****************************************************************************/
2284 static void
2285 bce_disable_nvram_write(struct bce_softc *sc)
2286 {
2287         u32 val;
2288
2289         DBENTER(BCE_VERBOSE_NVRAM);
2290
2291         val = REG_RD(sc, BCE_MISC_CFG);
2292         REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);
2293
2294         DBEXIT(BCE_VERBOSE_NVRAM);
2295
2296 }
2297 #endif
2298
2299
2300 /****************************************************************************/
2301 /* Enable NVRAM access.                                                     */
2302 /*                                                                          */
2303 /* Before accessing NVRAM for read or write operations the caller must      */
2304 /* enabled NVRAM access.                                                    */
2305 /*                                                                          */
2306 /* Returns:                                                                 */
2307 /*   Nothing.                                                               */
2308 /****************************************************************************/
2309 static void
2310 bce_enable_nvram_access(struct bce_softc *sc)
2311 {
2312         u32 val;
2313
2314         DBENTER(BCE_VERBOSE_NVRAM);
2315
2316         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
2317         /* Enable both bits, even on read. */
2318         REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val |
2319             BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
2320
2321         DBEXIT(BCE_VERBOSE_NVRAM);
2322 }
2323
2324
2325 /****************************************************************************/
2326 /* Disable NVRAM access.                                                    */
2327 /*                                                                          */
2328 /* When the caller is finished accessing NVRAM access must be disabled.     */
2329 /*                                                                          */
2330 /* Returns:                                                                 */
2331 /*   Nothing.                                                               */
2332 /****************************************************************************/
2333 static void
2334 bce_disable_nvram_access(struct bce_softc *sc)
2335 {
2336         u32 val;
2337
2338         DBENTER(BCE_VERBOSE_NVRAM);
2339
2340         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
2341
2342         /* Disable both bits, even after read. */
2343         REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val &
2344             ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
2345
2346         DBEXIT(BCE_VERBOSE_NVRAM);
2347 }
2348
2349
2350 #ifdef BCE_NVRAM_WRITE_SUPPORT
2351 /****************************************************************************/
2352 /* Erase NVRAM page before writing.                                         */
2353 /*                                                                          */
2354 /* Non-buffered flash parts require that a page be erased before it is      */
2355 /* written.                                                                 */
2356 /*                                                                          */
2357 /* Returns:                                                                 */
2358 /*   0 on success, positive value on failure.                               */
2359 /****************************************************************************/
2360 static int
2361 bce_nvram_erase_page(struct bce_softc *sc, u32 offset)
2362 {
2363         u32 cmd;
2364         int j, rc = 0;
2365
2366         DBENTER(BCE_VERBOSE_NVRAM);
2367
2368         /* Buffered flash doesn't require an erase. */
2369         if (sc->bce_flash_info->flags & BCE_NV_BUFFERED)
2370                 goto bce_nvram_erase_page_exit;
2371
2372         /* Build an erase command. */
2373         cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR |
2374             BCE_NVM_COMMAND_DOIT;
2375
2376         /*
2377          * Clear the DONE bit separately, set the NVRAM adress to erase,
2378          * and issue the erase command.
2379          */
2380         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2381         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2382         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2383
2384         /* Wait for completion. */
2385         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2386                 u32 val;
2387
2388                 DELAY(5);
2389
2390                 val = REG_RD(sc, BCE_NVM_COMMAND);
2391                 if (val & BCE_NVM_COMMAND_DONE)
2392                         break;
2393         }
2394
2395         if (j >= NVRAM_TIMEOUT_COUNT) {
2396                 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n");
2397                 rc = EBUSY;
2398         }
2399
2400 bce_nvram_erase_page_exit:
2401         DBEXIT(BCE_VERBOSE_NVRAM);
2402         return (rc);
2403 }
2404 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2405
2406
2407 /****************************************************************************/
2408 /* Read a dword (32 bits) from NVRAM.                                       */
2409 /*                                                                          */
2410 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
2411 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
2412 /*                                                                          */
2413 /* Returns:                                                                 */
2414 /*   0 on success and the 32 bit value read, positive value on failure.     */
2415 /****************************************************************************/
2416 static int
2417 bce_nvram_read_dword(struct bce_softc *sc,
2418     u32 offset, u8 *ret_val, u32 cmd_flags)
2419 {
2420         u32 cmd;
2421         int i, rc = 0;
2422
2423         DBENTER(BCE_EXTREME_NVRAM);
2424
2425         /* Build the command word. */
2426         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
2427
2428         /* Calculate the offset for buffered flash if translation is used. */
2429         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2430                 offset = ((offset / sc->bce_flash_info->page_size) <<
2431                     sc->bce_flash_info->page_bits) +
2432                     (offset % sc->bce_flash_info->page_size);
2433         }
2434
2435         /*
2436          * Clear the DONE bit separately, set the address to read,
2437          * and issue the read.
2438          */
2439         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2440         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2441         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2442
2443         /* Wait for completion. */
2444         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
2445                 u32 val;
2446
2447                 DELAY(5);
2448
2449                 val = REG_RD(sc, BCE_NVM_COMMAND);
2450                 if (val & BCE_NVM_COMMAND_DONE) {
2451                         val = REG_RD(sc, BCE_NVM_READ);
2452
2453                         val = bce_be32toh(val);
2454                         memcpy(ret_val, &val, 4);
2455                         break;
2456                 }
2457         }
2458
2459         /* Check for errors. */
2460         if (i >= NVRAM_TIMEOUT_COUNT) {
2461                 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at "
2462                     "offset 0x%08X!\n", __FILE__, __LINE__, offset);
2463                 rc = EBUSY;
2464         }
2465
2466         DBEXIT(BCE_EXTREME_NVRAM);
2467         return(rc);
2468 }
2469
2470
2471 #ifdef BCE_NVRAM_WRITE_SUPPORT
2472 /****************************************************************************/
2473 /* Write a dword (32 bits) to NVRAM.                                        */
2474 /*                                                                          */
2475 /* Write a 32 bit word to NVRAM.  The caller is assumed to have already     */
2476 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and    */
2477 /* enabled NVRAM write access.                                              */
2478 /*                                                                          */
2479 /* Returns:                                                                 */
2480 /*   0 on success, positive value on failure.                               */
2481 /****************************************************************************/
2482 static int
2483 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val,
2484         u32 cmd_flags)
2485 {
2486         u32 cmd, val32;
2487         int j, rc = 0;
2488
2489         DBENTER(BCE_VERBOSE_NVRAM);
2490
2491         /* Build the command word. */
2492         cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags;
2493
2494         /* Calculate the offset for buffered flash if translation is used. */
2495         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2496                 offset = ((offset / sc->bce_flash_info->page_size) <<
2497                     sc->bce_flash_info->page_bits) +
2498                     (offset % sc->bce_flash_info->page_size);
2499         }
2500
2501         /*
2502          * Clear the DONE bit separately, convert NVRAM data to big-endian,
2503          * set the NVRAM address to write, and issue the write command
2504          */
2505         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2506         memcpy(&val32, val, 4);
2507         val32 = htobe32(val32);
2508         REG_WR(sc, BCE_NVM_WRITE, val32);
2509         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2510         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2511
2512         /* Wait for completion. */
2513         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2514                 DELAY(5);
2515
2516                 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE)
2517                         break;
2518         }
2519         if (j >= NVRAM_TIMEOUT_COUNT) {
2520                 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at "
2521                     "offset 0x%08X\n", __FILE__, __LINE__, offset);
2522                 rc = EBUSY;
2523         }
2524
2525         DBEXIT(BCE_VERBOSE_NVRAM);
2526         return (rc);
2527 }
2528 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2529
2530
2531 /****************************************************************************/
2532 /* Initialize NVRAM access.                                                 */
2533 /*                                                                          */
2534 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
2535 /* access that device.                                                      */
2536 /*                                                                          */
2537 /* Returns:                                                                 */
2538 /*   0 on success, positive value on failure.                               */
2539 /****************************************************************************/
2540 static int
2541 bce_init_nvram(struct bce_softc *sc)
2542 {
2543         u32 val;
2544         int j, entry_count, rc = 0;
2545         const struct flash_spec *flash;
2546
2547         DBENTER(BCE_VERBOSE_NVRAM);
2548
2549         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
2550                 sc->bce_flash_info = &flash_5709;
2551                 goto bce_init_nvram_get_flash_size;
2552         }
2553
2554         /* Determine the selected interface. */
2555         val = REG_RD(sc, BCE_NVM_CFG1);
2556
2557         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2558
2559         /*
2560          * Flash reconfiguration is required to support additional
2561          * NVRAM devices not directly supported in hardware.
2562          * Check if the flash interface was reconfigured
2563          * by the bootcode.
2564          */
2565
2566         if (val & 0x40000000) {
2567                 /* Flash interface reconfigured by bootcode. */
2568
2569                 DBPRINT(sc,BCE_INFO_LOAD,
2570                         "bce_init_nvram(): Flash WAS reconfigured.\n");
2571
2572                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2573                      j++, flash++) {
2574                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
2575                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2576                                 sc->bce_flash_info = flash;
2577                                 break;
2578                         }
2579                 }
2580         } else {
2581                 /* Flash interface not yet reconfigured. */
2582                 u32 mask;
2583
2584                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n",
2585                         __FUNCTION__);
2586
2587                 if (val & (1 << 23))
2588                         mask = FLASH_BACKUP_STRAP_MASK;
2589                 else
2590                         mask = FLASH_STRAP_MASK;
2591
2592                 /* Look for the matching NVRAM device configuration data. */
2593                 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) {
2594
2595                         /* Check if the device matches any of the known devices. */
2596                         if ((val & mask) == (flash->strapping & mask)) {
2597                                 /* Found a device match. */
2598                                 sc->bce_flash_info = flash;
2599
2600                                 /* Request access to the flash interface. */
2601                                 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2602                                         return rc;
2603
2604                                 /* Reconfigure the flash interface. */
2605                                 bce_enable_nvram_access(sc);
2606                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
2607                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
2608                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
2609                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
2610                                 bce_disable_nvram_access(sc);
2611                                 bce_release_nvram_lock(sc);
2612
2613                                 break;
2614                         }
2615                 }
2616         }
2617
2618         /* Check if a matching device was found. */
2619         if (j == entry_count) {
2620                 sc->bce_flash_info = NULL;
2621                 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n",
2622                     __FILE__, __LINE__);
2623                 DBEXIT(BCE_VERBOSE_NVRAM);
2624                 return (ENODEV);
2625         }
2626
2627 bce_init_nvram_get_flash_size:
2628         /* Write the flash config data to the shared memory interface. */
2629         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2);
2630         val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
2631         if (val)
2632                 sc->bce_flash_size = val;
2633         else
2634                 sc->bce_flash_size = sc->bce_flash_info->total_size;
2635
2636         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n",
2637             __FUNCTION__, sc->bce_flash_info->name,
2638             sc->bce_flash_info->total_size);
2639
2640         DBEXIT(BCE_VERBOSE_NVRAM);
2641         return rc;
2642 }
2643
2644
2645 /****************************************************************************/
2646 /* Read an arbitrary range of data from NVRAM.                              */
2647 /*                                                                          */
2648 /* Prepares the NVRAM interface for access and reads the requested data     */
2649 /* into the supplied buffer.                                                */
2650 /*                                                                          */
2651 /* Returns:                                                                 */
2652 /*   0 on success and the data read, positive value on failure.             */
2653 /****************************************************************************/
2654 static int
2655 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf,
2656         int buf_size)
2657 {
2658         int rc = 0;
2659         u32 cmd_flags, offset32, len32, extra;
2660
2661         DBENTER(BCE_VERBOSE_NVRAM);
2662
2663         if (buf_size == 0)
2664                 goto bce_nvram_read_exit;
2665
2666         /* Request access to the flash interface. */
2667         if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2668                 goto bce_nvram_read_exit;
2669
2670         /* Enable access to flash interface */
2671         bce_enable_nvram_access(sc);
2672
2673         len32 = buf_size;
2674         offset32 = offset;
2675         extra = 0;
2676
2677         cmd_flags = 0;
2678
2679         if (offset32 & 3) {
2680                 u8 buf[4];
2681                 u32 pre_len;
2682
2683                 offset32 &= ~3;
2684                 pre_len = 4 - (offset & 3);
2685
2686                 if (pre_len >= len32) {
2687                         pre_len = len32;
2688                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
2689                 }
2690                 else {
2691                         cmd_flags = BCE_NVM_COMMAND_FIRST;
2692                 }
2693
2694                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2695
2696                 if (rc)
2697                         return rc;
2698
2699                 memcpy(ret_buf, buf + (offset & 3), pre_len);
2700
2701                 offset32 += 4;
2702                 ret_buf += pre_len;
2703                 len32 -= pre_len;
2704         }
2705
2706         if (len32 & 3) {
2707                 extra = 4 - (len32 & 3);
2708                 len32 = (len32 + 4) & ~3;
2709         }
2710
2711         if (len32 == 4) {
2712                 u8 buf[4];
2713
2714                 if (cmd_flags)
2715                         cmd_flags = BCE_NVM_COMMAND_LAST;
2716                 else
2717                         cmd_flags = BCE_NVM_COMMAND_FIRST |
2718                                     BCE_NVM_COMMAND_LAST;
2719
2720                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2721
2722                 memcpy(ret_buf, buf, 4 - extra);
2723         }
2724         else if (len32 > 0) {
2725                 u8 buf[4];
2726
2727                 /* Read the first word. */
2728                 if (cmd_flags)
2729                         cmd_flags = 0;
2730                 else
2731                         cmd_flags = BCE_NVM_COMMAND_FIRST;
2732
2733                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
2734
2735                 /* Advance to the next dword. */
2736                 offset32 += 4;
2737                 ret_buf += 4;
2738                 len32 -= 4;
2739
2740                 while (len32 > 4 && rc == 0) {
2741                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
2742
2743                         /* Advance to the next dword. */
2744                         offset32 += 4;
2745                         ret_buf += 4;
2746                         len32 -= 4;
2747                 }
2748
2749                 if (rc)
2750                         goto bce_nvram_read_locked_exit;
2751
2752                 cmd_flags = BCE_NVM_COMMAND_LAST;
2753                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2754
2755                 memcpy(ret_buf, buf, 4 - extra);
2756         }
2757
2758 bce_nvram_read_locked_exit:
2759         /* Disable access to flash interface and release the lock. */
2760         bce_disable_nvram_access(sc);
2761         bce_release_nvram_lock(sc);
2762
2763 bce_nvram_read_exit:
2764         DBEXIT(BCE_VERBOSE_NVRAM);
2765         return rc;
2766 }
2767
2768
2769 #ifdef BCE_NVRAM_WRITE_SUPPORT
2770 /****************************************************************************/
2771 /* Write an arbitrary range of data from NVRAM.                             */
2772 /*                                                                          */
2773 /* Prepares the NVRAM interface for write access and writes the requested   */
2774 /* data from the supplied buffer.  The caller is responsible for            */
2775 /* calculating any appropriate CRCs.                                        */
2776 /*                                                                          */
2777 /* Returns:                                                                 */
2778 /*   0 on success, positive value on failure.                               */
2779 /****************************************************************************/
2780 static int
2781 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf,
2782         int buf_size)
2783 {
2784         u32 written, offset32, len32;
2785         u8 *buf, start[4], end[4];
2786         int rc = 0;
2787         int align_start, align_end;
2788
2789         DBENTER(BCE_VERBOSE_NVRAM);
2790
2791         buf = data_buf;
2792         offset32 = offset;
2793         len32 = buf_size;
2794         align_start = align_end = 0;
2795
2796         if ((align_start = (offset32 & 3))) {
2797                 offset32 &= ~3;
2798                 len32 += align_start;
2799                 if ((rc = bce_nvram_read(sc, offset32, start, 4)))
2800                         goto bce_nvram_write_exit;
2801         }
2802
2803         if (len32 & 3) {
2804                 if ((len32 > 4) || !align_start) {
2805                         align_end = 4 - (len32 & 3);
2806                         len32 += align_end;
2807                         if ((rc = bce_nvram_read(sc, offset32 + len32 - 4,
2808                                 end, 4))) {
2809                                 goto bce_nvram_write_exit;
2810                         }
2811                 }
2812         }
2813
2814         if (align_start || align_end) {
2815                 buf = malloc(len32, M_DEVBUF, M_NOWAIT);
2816                 if (buf == 0) {
2817                         rc = ENOMEM;
2818                         goto bce_nvram_write_exit;
2819                 }
2820
2821                 if (align_start) {
2822                         memcpy(buf, start, 4);
2823                 }
2824
2825                 if (align_end) {
2826                         memcpy(buf + len32 - 4, end, 4);
2827                 }
2828                 memcpy(buf + align_start, data_buf, buf_size);
2829         }
2830
2831         written = 0;
2832         while ((written < len32) && (rc == 0)) {
2833                 u32 page_start, page_end, data_start, data_end;
2834                 u32 addr, cmd_flags;
2835                 int i;
2836                 u8 flash_buffer[264];
2837
2838             /* Find the page_start addr */
2839                 page_start = offset32 + written;
2840                 page_start -= (page_start % sc->bce_flash_info->page_size);
2841                 /* Find the page_end addr */
2842                 page_end = page_start + sc->bce_flash_info->page_size;
2843                 /* Find the data_start addr */
2844                 data_start = (written == 0) ? offset32 : page_start;
2845                 /* Find the data_end addr */
2846                 data_end = (page_end > offset32 + len32) ?
2847                         (offset32 + len32) : page_end;
2848
2849                 /* Request access to the flash interface. */
2850                 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2851                         goto bce_nvram_write_exit;
2852
2853                 /* Enable access to flash interface */
2854                 bce_enable_nvram_access(sc);
2855
2856                 cmd_flags = BCE_NVM_COMMAND_FIRST;
2857                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2858                         int j;
2859
2860                         /* Read the whole page into the buffer
2861                          * (non-buffer flash only) */
2862                         for (j = 0; j < sc->bce_flash_info->page_size; j += 4) {
2863                                 if (j == (sc->bce_flash_info->page_size - 4)) {
2864                                         cmd_flags |= BCE_NVM_COMMAND_LAST;
2865                                 }
2866                                 rc = bce_nvram_read_dword(sc,
2867                                         page_start + j,
2868                                         &flash_buffer[j],
2869                                         cmd_flags);
2870
2871                                 if (rc)
2872                                         goto bce_nvram_write_locked_exit;
2873
2874                                 cmd_flags = 0;
2875                         }
2876                 }
2877
2878                 /* Enable writes to flash interface (unlock write-protect) */
2879                 if ((rc = bce_enable_nvram_write(sc)) != 0)
2880                         goto bce_nvram_write_locked_exit;
2881
2882                 /* Erase the page */
2883                 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0)
2884                         goto bce_nvram_write_locked_exit;
2885
2886                 /* Re-enable the write again for the actual write */
2887                 bce_enable_nvram_write(sc);
2888
2889                 /* Loop to write back the buffer data from page_start to
2890                  * data_start */
2891                 i = 0;
2892                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2893                         for (addr = page_start; addr < data_start;
2894                                 addr += 4, i += 4) {
2895
2896                                 rc = bce_nvram_write_dword(sc, addr,
2897                                         &flash_buffer[i], cmd_flags);
2898
2899                                 if (rc != 0)
2900                                         goto bce_nvram_write_locked_exit;
2901
2902                                 cmd_flags = 0;
2903                         }
2904                 }
2905
2906                 /* Loop to write the new data from data_start to data_end */
2907                 for (addr = data_start; addr < data_end; addr += 4, i++) {
2908                         if ((addr == page_end - 4) ||
2909                                 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) &&
2910                                 (addr == data_end - 4))) {
2911
2912                                 cmd_flags |= BCE_NVM_COMMAND_LAST;
2913                         }
2914                         rc = bce_nvram_write_dword(sc, addr, buf,
2915                                 cmd_flags);
2916
2917                         if (rc != 0)
2918                                 goto bce_nvram_write_locked_exit;
2919
2920                         cmd_flags = 0;
2921                         buf += 4;
2922                 }
2923
2924                 /* Loop to write back the buffer data from data_end
2925                  * to page_end */
2926                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2927                         for (addr = data_end; addr < page_end;
2928                                 addr += 4, i += 4) {
2929
2930                                 if (addr == page_end-4) {
2931                                         cmd_flags = BCE_NVM_COMMAND_LAST;
2932                                 }
2933                                 rc = bce_nvram_write_dword(sc, addr,
2934                                         &flash_buffer[i], cmd_flags);
2935
2936                                 if (rc != 0)
2937                                         goto bce_nvram_write_locked_exit;
2938
2939                                 cmd_flags = 0;
2940                         }
2941                 }
2942
2943                 /* Disable writes to flash interface (lock write-protect) */
2944                 bce_disable_nvram_write(sc);
2945
2946                 /* Disable access to flash interface */
2947                 bce_disable_nvram_access(sc);
2948                 bce_release_nvram_lock(sc);
2949
2950                 /* Increment written */
2951                 written += data_end - data_start;
2952         }
2953
2954         goto bce_nvram_write_exit;
2955
2956 bce_nvram_write_locked_exit:
2957         bce_disable_nvram_write(sc);
2958         bce_disable_nvram_access(sc);
2959         bce_release_nvram_lock(sc);
2960
2961 bce_nvram_write_exit:
2962         if (align_start || align_end)
2963                 free(buf, M_DEVBUF);
2964
2965         DBEXIT(BCE_VERBOSE_NVRAM);
2966         return (rc);
2967 }
2968 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2969
2970
2971 /****************************************************************************/
2972 /* Verifies that NVRAM is accessible and contains valid data.               */
2973 /*                                                                          */
2974 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
2975 /* correct.                                                                 */
2976 /*                                                                          */
2977 /* Returns:                                                                 */
2978 /*   0 on success, positive value on failure.                               */
2979 /****************************************************************************/
2980 static int
2981 bce_nvram_test(struct bce_softc *sc)
2982 {
2983         u32 buf[BCE_NVRAM_SIZE / 4];
2984         u8 *data = (u8 *) buf;
2985         int rc = 0;
2986         u32 magic, csum;
2987
2988         DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
2989
2990         /*
2991          * Check that the device NVRAM is valid by reading
2992          * the magic value at offset 0.
2993          */
2994         if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) {
2995                 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n",
2996                     __FILE__, __LINE__);
2997                 goto bce_nvram_test_exit;
2998         }
2999
3000         /*
3001          * Verify that offset 0 of the NVRAM contains
3002          * a valid magic number.
3003          */
3004         magic = bce_be32toh(buf[0]);
3005         if (magic != BCE_NVRAM_MAGIC) {
3006                 rc = ENODEV;
3007                 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! "
3008                     "Expected: 0x%08X, Found: 0x%08X\n",
3009                     __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic);
3010                 goto bce_nvram_test_exit;
3011         }
3012
3013         /*
3014          * Verify that the device NVRAM includes valid
3015          * configuration data.
3016          */
3017         if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) {
3018                 BCE_PRINTF("%s(%d): Unable to read manufacturing "
3019                     "Information from  NVRAM!\n", __FILE__, __LINE__);
3020                 goto bce_nvram_test_exit;
3021         }
3022
3023         csum = ether_crc32_le(data, 0x100);
3024         if (csum != BCE_CRC32_RESIDUAL) {
3025                 rc = ENODEV;
3026                 BCE_PRINTF("%s(%d): Invalid manufacturing information "
3027                     "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n",
3028                     __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum);
3029                 goto bce_nvram_test_exit;
3030         }
3031
3032         csum = ether_crc32_le(data + 0x100, 0x100);
3033         if (csum != BCE_CRC32_RESIDUAL) {
3034                 rc = ENODEV;
3035                 BCE_PRINTF("%s(%d): Invalid feature configuration "
3036                     "information NVRAM CRC! Expected: 0x%08X, "
3037                     "Found: 08%08X\n", __FILE__, __LINE__,
3038                     BCE_CRC32_RESIDUAL, csum);
3039         }
3040
3041 bce_nvram_test_exit:
3042         DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
3043         return rc;
3044 }
3045
3046
3047 /****************************************************************************/
3048 /* Calculates the size of the buffers to allocate based on the MTU.         */
3049 /*                                                                          */
3050 /* Returns:                                                                 */
3051 /*   Nothing.                                                               */
3052 /****************************************************************************/
3053 static void
3054 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu)
3055 {
3056         DBENTER(BCE_VERBOSE_LOAD);
3057
3058         /* Use a single allocation type when header splitting enabled. */
3059         if (bce_hdr_split == TRUE) {
3060                 sc->rx_bd_mbuf_alloc_size = MHLEN;
3061                 /* Make sure offset is 16 byte aligned for hardware. */
3062                 sc->rx_bd_mbuf_align_pad =
3063                         roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN);
3064                 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
3065                         sc->rx_bd_mbuf_align_pad;
3066         } else {
3067                 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
3068                     ETHER_CRC_LEN) > MCLBYTES) {
3069                         /* Setup for jumbo RX buffer allocations. */
3070                         sc->rx_bd_mbuf_alloc_size = MJUM9BYTES;
3071                         sc->rx_bd_mbuf_align_pad  =
3072                                 roundup2(MJUM9BYTES, 16) - MJUM9BYTES;
3073                         sc->rx_bd_mbuf_data_len =
3074                             sc->rx_bd_mbuf_alloc_size -
3075                             sc->rx_bd_mbuf_align_pad;
3076                 } else {
3077                         /* Setup for standard RX buffer allocations. */
3078                         sc->rx_bd_mbuf_alloc_size = MCLBYTES;
3079                         sc->rx_bd_mbuf_align_pad  =
3080                             roundup2(MCLBYTES, 16) - MCLBYTES;
3081                         sc->rx_bd_mbuf_data_len =
3082                             sc->rx_bd_mbuf_alloc_size -
3083                             sc->rx_bd_mbuf_align_pad;
3084                 }
3085         }
3086
3087 //      DBPRINT(sc, BCE_INFO_LOAD,
3088         DBPRINT(sc, BCE_WARN,
3089            "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, "
3090            "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__,
3091            sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len,
3092            sc->rx_bd_mbuf_align_pad);
3093
3094         DBEXIT(BCE_VERBOSE_LOAD);
3095 }
3096
3097 /****************************************************************************/
3098 /* Identifies the current media type of the controller and sets the PHY     */
3099 /* address.                                                                 */
3100 /*                                                                          */
3101 /* Returns:                                                                 */
3102 /*   Nothing.                                                               */
3103 /****************************************************************************/
3104 static void
3105 bce_get_media(struct bce_softc *sc)
3106 {
3107         u32 val;
3108
3109         DBENTER(BCE_VERBOSE_PHY);
3110
3111         /* Assume PHY address for copper controllers. */
3112         sc->bce_phy_addr = 1;
3113
3114         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3115                 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
3116                 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
3117                 u32 strap;
3118
3119                 /*
3120                  * The BCM5709S is software configurable
3121                  * for Copper or SerDes operation.
3122                  */
3123                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
3124                         DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
3125                             "for copper.\n");
3126                         goto bce_get_media_exit;
3127                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
3128                         DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
3129                             "for dual media.\n");
3130                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3131                         goto bce_get_media_exit;
3132                 }
3133
3134                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
3135                         strap = (val &
3136                             BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
3137                 else
3138                         strap = (val &
3139                             BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
3140
3141                 if (pci_get_function(sc->bce_dev) == 0) {
3142                         switch (strap) {
3143                         case 0x4:
3144                         case 0x5:
3145                         case 0x6:
3146                                 DBPRINT(sc, BCE_INFO_LOAD,
3147                                     "BCM5709 s/w configured for SerDes.\n");
3148                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3149                                 break;
3150                         default:
3151                                 DBPRINT(sc, BCE_INFO_LOAD,
3152                                     "BCM5709 s/w configured for Copper.\n");
3153                                 break;
3154                         }
3155                 } else {
3156                         switch (strap) {
3157                         case 0x1:
3158                         case 0x2:
3159                         case 0x4:
3160                                 DBPRINT(sc, BCE_INFO_LOAD,
3161                                     "BCM5709 s/w configured for SerDes.\n");
3162                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3163                                 break;
3164                         default:
3165                                 DBPRINT(sc, BCE_INFO_LOAD,
3166                                     "BCM5709 s/w configured for Copper.\n");
3167                                 break;
3168                         }
3169                 }
3170
3171         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT)
3172                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3173
3174         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
3175
3176                 sc->bce_flags |= BCE_NO_WOL_FLAG;
3177
3178                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
3179                         sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG;
3180
3181                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
3182                         /* 5708S/09S/16S use a separate PHY for SerDes. */
3183                         sc->bce_phy_addr = 2;
3184
3185                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
3186                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G) {
3187                                 sc->bce_phy_flags |=
3188                                     BCE_PHY_2_5G_CAPABLE_FLAG;
3189                                 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb "
3190                                     "capable adapter\n");
3191                         }
3192                 }
3193         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
3194             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708))
3195                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
3196
3197 bce_get_media_exit:
3198         DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY),
3199                 "Using PHY address %d.\n", sc->bce_phy_addr);
3200
3201         DBEXIT(BCE_VERBOSE_PHY);
3202 }
3203
3204
3205 /****************************************************************************/
3206 /* Performs PHY initialization required before MII drivers access the       */
3207 /* device.                                                                  */
3208 /*                                                                          */
3209 /* Returns:                                                                 */
3210 /*   Nothing.                                                               */
3211 /****************************************************************************/
3212 static void
3213 bce_init_media(struct bce_softc *sc)
3214 {
3215         if ((sc->bce_phy_flags & (BCE_PHY_IEEE_CLAUSE_45_FLAG |
3216             BCE_PHY_REMOTE_CAP_FLAG)) == BCE_PHY_IEEE_CLAUSE_45_FLAG) {
3217                 /*
3218                  * Configure 5709S/5716S PHYs to use traditional IEEE
3219                  * Clause 22 method. Otherwise we have no way to attach
3220                  * the PHY in mii(4) layer. PHY specific configuration
3221                  * is done in mii layer.
3222                  */
3223
3224                 /* Select auto-negotiation MMD of the PHY. */
3225                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3226                     BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT);
3227                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3228                     BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD);
3229
3230                 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */
3231                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3232                     BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
3233         }
3234 }
3235
3236
3237 /****************************************************************************/
3238 /* Free any DMA memory owned by the driver.                                 */
3239 /*                                                                          */
3240 /* Scans through each data structre that requires DMA memory and frees      */
3241 /* the memory if allocated.                                                 */
3242 /*                                                                          */
3243 /* Returns:                                                                 */
3244 /*   Nothing.                                                               */
3245 /****************************************************************************/
3246 static void
3247 bce_dma_free(struct bce_softc *sc)
3248 {
3249         int i;
3250
3251         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
3252
3253         /* Free, unmap, and destroy the status block. */
3254         if (sc->status_block != NULL) {
3255                 bus_dmamem_free(
3256                    sc->status_tag,
3257                     sc->status_block,
3258                     sc->status_map);
3259                 sc->status_block = NULL;
3260         }
3261
3262         if (sc->status_map != NULL) {
3263                 bus_dmamap_unload(
3264                     sc->status_tag,
3265                     sc->status_map);
3266                 bus_dmamap_destroy(sc->status_tag,
3267                     sc->status_map);
3268                 sc->status_map = NULL;
3269         }
3270
3271         if (sc->status_tag != NULL) {
3272                 bus_dma_tag_destroy(sc->status_tag);
3273                 sc->status_tag = NULL;
3274         }
3275
3276
3277         /* Free, unmap, and destroy the statistics block. */
3278         if (sc->stats_block != NULL) {
3279                 bus_dmamem_free(
3280                     sc->stats_tag,
3281                     sc->stats_block,
3282                     sc->stats_map);
3283                 sc->stats_block = NULL;
3284         }
3285
3286         if (sc->stats_map != NULL) {
3287                 bus_dmamap_unload(
3288                     sc->stats_tag,
3289                     sc->stats_map);
3290                 bus_dmamap_destroy(sc->stats_tag,
3291                     sc->stats_map);
3292                 sc->stats_map = NULL;
3293         }
3294
3295         if (sc->stats_tag != NULL) {
3296                 bus_dma_tag_destroy(sc->stats_tag);
3297                 sc->stats_tag = NULL;
3298         }
3299
3300
3301         /* Free, unmap and destroy all context memory pages. */
3302         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3303                 for (i = 0; i < sc->ctx_pages; i++ ) {
3304                         if (sc->ctx_block[i] != NULL) {
3305                                 bus_dmamem_free(
3306                                     sc->ctx_tag,
3307                                     sc->ctx_block[i],
3308                                     sc->ctx_map[i]);
3309                                 sc->ctx_block[i] = NULL;
3310                         }
3311
3312                         if (sc->ctx_map[i] != NULL) {
3313                                 bus_dmamap_unload(
3314                                     sc->ctx_tag,
3315                                     sc->ctx_map[i]);
3316                                 bus_dmamap_destroy(
3317                                     sc->ctx_tag,
3318                                     sc->ctx_map[i]);
3319                                 sc->ctx_map[i] = NULL;
3320                         }
3321                 }
3322
3323                 /* Destroy the context memory tag. */
3324                 if (sc->ctx_tag != NULL) {
3325                         bus_dma_tag_destroy(sc->ctx_tag);
3326                         sc->ctx_tag = NULL;
3327                 }
3328         }
3329
3330
3331         /* Free, unmap and destroy all TX buffer descriptor chain pages. */
3332         for (i = 0; i < sc->tx_pages; i++ ) {
3333                 if (sc->tx_bd_chain[i] != NULL) {
3334                         bus_dmamem_free(
3335                             sc->tx_bd_chain_tag,
3336                             sc->tx_bd_chain[i],
3337                             sc->tx_bd_chain_map[i]);
3338                         sc->tx_bd_chain[i] = NULL;
3339                 }
3340
3341                 if (sc->tx_bd_chain_map[i] != NULL) {
3342                         bus_dmamap_unload(
3343                             sc->tx_bd_chain_tag,
3344                             sc->tx_bd_chain_map[i]);
3345                         bus_dmamap_destroy(
3346                             sc->tx_bd_chain_tag,
3347                             sc->tx_bd_chain_map[i]);
3348                         sc->tx_bd_chain_map[i] = NULL;
3349                 }
3350         }
3351
3352         /* Destroy the TX buffer descriptor tag. */
3353         if (sc->tx_bd_chain_tag != NULL) {
3354                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
3355                 sc->tx_bd_chain_tag = NULL;
3356         }
3357
3358
3359         /* Free, unmap and destroy all RX buffer descriptor chain pages. */
3360         for (i = 0; i < sc->rx_pages; i++ ) {
3361                 if (sc->rx_bd_chain[i] != NULL) {
3362                         bus_dmamem_free(
3363                             sc->rx_bd_chain_tag,
3364                             sc->rx_bd_chain[i],
3365                             sc->rx_bd_chain_map[i]);
3366                         sc->rx_bd_chain[i] = NULL;
3367                 }
3368
3369                 if (sc->rx_bd_chain_map[i] != NULL) {
3370                         bus_dmamap_unload(
3371                             sc->rx_bd_chain_tag,
3372                             sc->rx_bd_chain_map[i]);
3373                         bus_dmamap_destroy(
3374                             sc->rx_bd_chain_tag,
3375                             sc->rx_bd_chain_map[i]);
3376                         sc->rx_bd_chain_map[i] = NULL;
3377                 }
3378         }
3379
3380         /* Destroy the RX buffer descriptor tag. */
3381         if (sc->rx_bd_chain_tag != NULL) {
3382                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
3383                 sc->rx_bd_chain_tag = NULL;
3384         }
3385
3386
3387         /* Free, unmap and destroy all page buffer descriptor chain pages. */
3388         if (bce_hdr_split == TRUE) {
3389                 for (i = 0; i < sc->pg_pages; i++ ) {
3390                         if (sc->pg_bd_chain[i] != NULL) {
3391                                 bus_dmamem_free(
3392                                     sc->pg_bd_chain_tag,
3393                                     sc->pg_bd_chain[i],
3394                                     sc->pg_bd_chain_map[i]);
3395                                 sc->pg_bd_chain[i] = NULL;
3396                         }
3397
3398                         if (sc->pg_bd_chain_map[i] != NULL) {
3399                                 bus_dmamap_unload(
3400                                     sc->pg_bd_chain_tag,
3401                                     sc->pg_bd_chain_map[i]);
3402                                 bus_dmamap_destroy(
3403                                     sc->pg_bd_chain_tag,
3404                                     sc->pg_bd_chain_map[i]);
3405                                 sc->pg_bd_chain_map[i] = NULL;
3406                         }
3407                 }
3408
3409                 /* Destroy the page buffer descriptor tag. */
3410                 if (sc->pg_bd_chain_tag != NULL) {
3411                         bus_dma_tag_destroy(sc->pg_bd_chain_tag);
3412                         sc->pg_bd_chain_tag = NULL;
3413                 }
3414         }
3415
3416
3417         /* Unload and destroy the TX mbuf maps. */
3418         for (i = 0; i < MAX_TX_BD_AVAIL; i++) {
3419                 if (sc->tx_mbuf_map[i] != NULL) {
3420                         bus_dmamap_unload(sc->tx_mbuf_tag,
3421                             sc->tx_mbuf_map[i]);
3422                         bus_dmamap_destroy(sc->tx_mbuf_tag,
3423                             sc->tx_mbuf_map[i]);
3424                         sc->tx_mbuf_map[i] = NULL;
3425                 }
3426         }
3427
3428         /* Destroy the TX mbuf tag. */
3429         if (sc->tx_mbuf_tag != NULL) {
3430                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
3431                 sc->tx_mbuf_tag = NULL;
3432         }
3433
3434         /* Unload and destroy the RX mbuf maps. */
3435         for (i = 0; i < MAX_RX_BD_AVAIL; i++) {
3436                 if (sc->rx_mbuf_map[i] != NULL) {
3437                         bus_dmamap_unload(sc->rx_mbuf_tag,
3438                             sc->rx_mbuf_map[i]);
3439                         bus_dmamap_destroy(sc->rx_mbuf_tag,
3440                             sc->rx_mbuf_map[i]);
3441                         sc->rx_mbuf_map[i] = NULL;
3442                 }
3443         }
3444
3445         /* Destroy the RX mbuf tag. */
3446         if (sc->rx_mbuf_tag != NULL) {
3447                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
3448                 sc->rx_mbuf_tag = NULL;
3449         }
3450
3451         /* Unload and destroy the page mbuf maps. */
3452         if (bce_hdr_split == TRUE) {
3453                 for (i = 0; i < MAX_PG_BD_AVAIL; i++) {
3454                         if (sc->pg_mbuf_map[i] != NULL) {
3455                                 bus_dmamap_unload(sc->pg_mbuf_tag,
3456                                     sc->pg_mbuf_map[i]);
3457                                 bus_dmamap_destroy(sc->pg_mbuf_tag,
3458                                     sc->pg_mbuf_map[i]);
3459                                 sc->pg_mbuf_map[i] = NULL;
3460                         }
3461                 }
3462
3463                 /* Destroy the page mbuf tag. */
3464                 if (sc->pg_mbuf_tag != NULL) {
3465                         bus_dma_tag_destroy(sc->pg_mbuf_tag);
3466                         sc->pg_mbuf_tag = NULL;
3467                 }
3468         }
3469
3470         /* Destroy the parent tag */
3471         if (sc->parent_tag != NULL) {
3472                 bus_dma_tag_destroy(sc->parent_tag);
3473                 sc->parent_tag = NULL;
3474         }
3475
3476         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
3477 }
3478
3479
3480 /****************************************************************************/
3481 /* Get DMA memory from the OS.                                              */
3482 /*                                                                          */
3483 /* Validates that the OS has provided DMA buffers in response to a          */
3484 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
3485 /* When the callback is used the OS will return 0 for the mapping function  */
3486 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
3487 /* failures back to the caller.                                             */
3488 /*                                                                          */
3489 /* Returns:                                                                 */
3490 /*   Nothing.                                                               */
3491 /****************************************************************************/
3492 static void
3493 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3494 {
3495         bus_addr_t *busaddr = arg;
3496
3497         KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!",
3498             __FUNCTION__, nseg));
3499         /* Simulate a mapping failure. */
3500         DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control),
3501             error = ENOMEM);
3502
3503         /* ToDo: How to increment debug sim_count variable here? */
3504
3505         /* Check for an error and signal the caller that an error occurred. */
3506         if (error) {
3507                 *busaddr = 0;
3508         } else {
3509                 *busaddr = segs->ds_addr;
3510         }
3511 }
3512
3513
3514 /****************************************************************************/
3515 /* Allocate any DMA memory needed by the driver.                            */
3516 /*                                                                          */
3517 /* Allocates DMA memory needed for the various global structures needed by  */
3518 /* hardware.                                                                */
3519 /*                                                                          */
3520 /* Memory alignment requirements:                                           */
3521 /* +-----------------+----------+----------+----------+----------+          */
3522 /* |                 |   5706   |   5708   |   5709   |   5716   |          */
3523 /* +-----------------+----------+----------+----------+----------+          */
3524 /* |Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |          */
3525 /* |Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |          */
3526 /* |RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |          */
3527 /* |PG Buffers       |   none   |   none   |   none   |   none   |          */
3528 /* |TX Buffers       |   none   |   none   |   none   |   none   |          */
3529 /* |Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |          */
3530 /* |Context Memory   |          |          |          |          |          */
3531 /* +-----------------+----------+----------+----------+----------+          */
3532 /*                                                                          */
3533 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
3534 /*                                                                          */
3535 /* Returns:                                                                 */
3536 /*   0 for success, positive value for failure.                             */
3537 /****************************************************************************/
3538 static int
3539 bce_dma_alloc(device_t dev)
3540 {
3541         struct bce_softc *sc;
3542         int i, error, rc = 0;
3543         bus_size_t max_size, max_seg_size;
3544         int max_segments;
3545
3546         sc = device_get_softc(dev);
3547
3548         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3549
3550         /*
3551          * Allocate the parent bus DMA tag appropriate for PCI.
3552          */
3553         if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY,
3554             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3555             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
3556             &sc->parent_tag)) {
3557                 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n",
3558                     __FILE__, __LINE__);
3559                 rc = ENOMEM;
3560                 goto bce_dma_alloc_exit;
3561         }
3562
3563         /*
3564          * Create a DMA tag for the status block, allocate and clear the
3565          * memory, map the memory into DMA space, and fetch the physical
3566          * address of the block.
3567          */
3568         if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3569             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3570             NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ,
3571             0, NULL, NULL, &sc->status_tag)) {
3572                 BCE_PRINTF("%s(%d): Could not allocate status block "
3573                     "DMA tag!\n", __FILE__, __LINE__);
3574                 rc = ENOMEM;
3575                 goto bce_dma_alloc_exit;
3576         }
3577
3578         if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block,
3579             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3580             &sc->status_map)) {
3581                 BCE_PRINTF("%s(%d): Could not allocate status block "
3582                     "DMA memory!\n", __FILE__, __LINE__);
3583                 rc = ENOMEM;
3584                 goto bce_dma_alloc_exit;
3585         }
3586
3587         error = bus_dmamap_load(sc->status_tag, sc->status_map,
3588             sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr,
3589             &sc->status_block_paddr, BUS_DMA_NOWAIT);
3590
3591         if (error || sc->status_block_paddr == 0) {
3592                 BCE_PRINTF("%s(%d): Could not map status block "
3593                     "DMA memory!\n", __FILE__, __LINE__);
3594                 rc = ENOMEM;
3595                 goto bce_dma_alloc_exit;
3596         }
3597
3598         DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n",
3599             __FUNCTION__, (uintmax_t) sc->status_block_paddr);
3600
3601         /*
3602          * Create a DMA tag for the statistics block, allocate and clear the
3603          * memory, map the memory into DMA space, and fetch the physical
3604          * address of the block.
3605          */
3606         if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3607             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3608             NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ,
3609             0, NULL, NULL, &sc->stats_tag)) {
3610                 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3611                     "DMA tag!\n", __FILE__, __LINE__);
3612                 rc = ENOMEM;
3613                 goto bce_dma_alloc_exit;
3614         }
3615
3616         if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block,
3617             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) {
3618                 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3619                     "DMA memory!\n", __FILE__, __LINE__);
3620                 rc = ENOMEM;
3621                 goto bce_dma_alloc_exit;
3622         }
3623
3624         error = bus_dmamap_load(sc->stats_tag, sc->stats_map,
3625             sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr,
3626             &sc->stats_block_paddr, BUS_DMA_NOWAIT);
3627
3628         if (error || sc->stats_block_paddr == 0) {
3629                 BCE_PRINTF("%s(%d): Could not map statistics block "
3630                     "DMA memory!\n", __FILE__, __LINE__);
3631                 rc = ENOMEM;
3632                 goto bce_dma_alloc_exit;
3633         }
3634
3635         DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n",
3636             __FUNCTION__, (uintmax_t) sc->stats_block_paddr);
3637
3638         /* BCM5709 uses host memory as cache for context memory. */
3639         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3640                 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
3641                 if (sc->ctx_pages == 0)
3642                         sc->ctx_pages = 1;
3643
3644                 DBRUNIF((sc->ctx_pages > 512),
3645                     BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n",
3646                     __FILE__, __LINE__, sc->ctx_pages));
3647
3648                 /*
3649                  * Create a DMA tag for the context pages,
3650                  * allocate and clear the memory, map the
3651                  * memory into DMA space, and fetch the
3652                  * physical address of the block.
3653                  */
3654                 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3655                     BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3656                     NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
3657                     0, NULL, NULL, &sc->ctx_tag)) {
3658                         BCE_PRINTF("%s(%d): Could not allocate CTX "
3659                             "DMA tag!\n", __FILE__, __LINE__);
3660                         rc = ENOMEM;
3661                         goto bce_dma_alloc_exit;
3662                 }
3663
3664                 for (i = 0; i < sc->ctx_pages; i++) {
3665
3666                         if(bus_dmamem_alloc(sc->ctx_tag,
3667                             (void **)&sc->ctx_block[i],
3668                             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3669                             &sc->ctx_map[i])) {
3670                                 BCE_PRINTF("%s(%d): Could not allocate CTX "
3671                                     "DMA memory!\n", __FILE__, __LINE__);
3672                                 rc = ENOMEM;
3673                                 goto bce_dma_alloc_exit;
3674                         }
3675
3676                         error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
3677                             sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr,
3678                             &sc->ctx_paddr[i], BUS_DMA_NOWAIT);
3679
3680                         if (error || sc->ctx_paddr[i] == 0) {
3681                                 BCE_PRINTF("%s(%d): Could not map CTX "
3682                                     "DMA memory!\n", __FILE__, __LINE__);
3683                                 rc = ENOMEM;
3684                                 goto bce_dma_alloc_exit;
3685                         }
3686
3687                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] "
3688                             "= 0x%jX\n", __FUNCTION__, i,
3689                             (uintmax_t) sc->ctx_paddr[i]);
3690                 }
3691         }
3692
3693         /*
3694          * Create a DMA tag for the TX buffer descriptor chain,
3695          * allocate and clear the  memory, and fetch the
3696          * physical address of the block.
3697          */
3698         if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY,
3699             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3700             BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0,
3701             NULL, NULL, &sc->tx_bd_chain_tag)) {
3702                 BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3703                     "chain DMA tag!\n", __FILE__, __LINE__);
3704                 rc = ENOMEM;
3705                 goto bce_dma_alloc_exit;
3706         }
3707
3708         for (i = 0; i < sc->tx_pages; i++) {
3709
3710                 if(bus_dmamem_alloc(sc->tx_bd_chain_tag,
3711                     (void **)&sc->tx_bd_chain[i],
3712                     BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3713                     &sc->tx_bd_chain_map[i])) {
3714                         BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3715                             "chain DMA memory!\n", __FILE__, __LINE__);
3716                         rc = ENOMEM;
3717                         goto bce_dma_alloc_exit;
3718                 }
3719
3720                 error = bus_dmamap_load(sc->tx_bd_chain_tag,
3721                     sc->tx_bd_chain_map[i], sc->tx_bd_chain[i],
3722                     BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3723                     &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3724
3725                 if (error || sc->tx_bd_chain_paddr[i] == 0) {
3726                         BCE_PRINTF("%s(%d): Could not map TX descriptor "
3727                             "chain DMA memory!\n", __FILE__, __LINE__);
3728                         rc = ENOMEM;
3729                         goto bce_dma_alloc_exit;
3730                 }
3731
3732                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = "
3733                     "0x%jX\n", __FUNCTION__, i,
3734                     (uintmax_t) sc->tx_bd_chain_paddr[i]);
3735         }
3736
3737         /* Check the required size before mapping to conserve resources. */
3738         if (bce_tso_enable) {
3739                 max_size     = BCE_TSO_MAX_SIZE;
3740                 max_segments = BCE_MAX_SEGMENTS;
3741                 max_seg_size = BCE_TSO_MAX_SEG_SIZE;
3742         } else {
3743                 max_size     = MCLBYTES * BCE_MAX_SEGMENTS;
3744                 max_segments = BCE_MAX_SEGMENTS;
3745                 max_seg_size = MCLBYTES;
3746         }
3747
3748         /* Create a DMA tag for TX mbufs. */
3749         if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3750             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size,
3751             max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) {
3752                 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n",
3753                     __FILE__, __LINE__);
3754                 rc = ENOMEM;
3755                 goto bce_dma_alloc_exit;
3756         }
3757
3758         /* Create DMA maps for the TX mbufs clusters. */
3759         for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) {
3760                 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT,
3761                         &sc->tx_mbuf_map[i])) {
3762                         BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA "
3763                             "map!\n", __FILE__, __LINE__);
3764                         rc = ENOMEM;
3765                         goto bce_dma_alloc_exit;
3766                 }
3767         }
3768
3769         /*
3770          * Create a DMA tag for the RX buffer descriptor chain,
3771          * allocate and clear the memory, and fetch the physical
3772          * address of the blocks.
3773          */
3774         if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3775                         BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR,
3776                         sc->max_bus_addr, NULL, NULL,
3777                         BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
3778                         0, NULL, NULL, &sc->rx_bd_chain_tag)) {
3779                 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain "
3780                     "DMA tag!\n", __FILE__, __LINE__);
3781                 rc = ENOMEM;
3782                 goto bce_dma_alloc_exit;
3783         }
3784
3785         for (i = 0; i < sc->rx_pages; i++) {
3786
3787                 if (bus_dmamem_alloc(sc->rx_bd_chain_tag,
3788                     (void **)&sc->rx_bd_chain[i],
3789                     BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3790                     &sc->rx_bd_chain_map[i])) {
3791                         BCE_PRINTF("%s(%d): Could not allocate RX descriptor "
3792                             "chain DMA memory!\n", __FILE__, __LINE__);
3793                         rc = ENOMEM;
3794                         goto bce_dma_alloc_exit;
3795                 }
3796
3797                 error = bus_dmamap_load(sc->rx_bd_chain_tag,
3798                     sc->rx_bd_chain_map[i], sc->rx_bd_chain[i],
3799                     BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3800                     &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3801
3802                 if (error || sc->rx_bd_chain_paddr[i] == 0) {
3803                         BCE_PRINTF("%s(%d): Could not map RX descriptor "
3804                             "chain DMA memory!\n", __FILE__, __LINE__);
3805                         rc = ENOMEM;
3806                         goto bce_dma_alloc_exit;
3807                 }
3808
3809                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = "
3810                     "0x%jX\n", __FUNCTION__, i,
3811                     (uintmax_t) sc->rx_bd_chain_paddr[i]);
3812         }
3813
3814         /*
3815          * Create a DMA tag for RX mbufs.
3816          */
3817         if (bce_hdr_split == TRUE)
3818                 max_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ?
3819                     MCLBYTES : sc->rx_bd_mbuf_alloc_size);
3820         else
3821                 max_size = MJUM9BYTES;
3822
3823         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag "
3824             "(max size = 0x%jX)\n", __FUNCTION__, (uintmax_t)max_size);
3825
3826         if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN,
3827             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3828             max_size, 1, max_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) {
3829                 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n",
3830                     __FILE__, __LINE__);
3831                 rc = ENOMEM;
3832                 goto bce_dma_alloc_exit;
3833         }
3834
3835         /* Create DMA maps for the RX mbuf clusters. */
3836         for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) {
3837                 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT,
3838                     &sc->rx_mbuf_map[i])) {
3839                         BCE_PRINTF("%s(%d): Unable to create RX mbuf "
3840                             "DMA map!\n", __FILE__, __LINE__);
3841                         rc = ENOMEM;
3842                         goto bce_dma_alloc_exit;
3843                 }
3844         }
3845
3846         if (bce_hdr_split == TRUE) {
3847                 /*
3848                  * Create a DMA tag for the page buffer descriptor chain,
3849                  * allocate and clear the memory, and fetch the physical
3850                  * address of the blocks.
3851                  */
3852                 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3853                             BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr,
3854                             NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ,
3855                             0, NULL, NULL, &sc->pg_bd_chain_tag)) {
3856                         BCE_PRINTF("%s(%d): Could not allocate page descriptor "
3857                             "chain DMA tag!\n", __FILE__, __LINE__);
3858                         rc = ENOMEM;
3859                         goto bce_dma_alloc_exit;
3860                 }
3861
3862                 for (i = 0; i < sc->pg_pages; i++) {
3863                         if (bus_dmamem_alloc(sc->pg_bd_chain_tag,
3864                             (void **)&sc->pg_bd_chain[i],
3865                             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3866                             &sc->pg_bd_chain_map[i])) {
3867                                 BCE_PRINTF("%s(%d): Could not allocate page "
3868                                     "descriptor chain DMA memory!\n",
3869                                     __FILE__, __LINE__);
3870                                 rc = ENOMEM;
3871                                 goto bce_dma_alloc_exit;
3872                         }
3873
3874                         error = bus_dmamap_load(sc->pg_bd_chain_tag,
3875                             sc->pg_bd_chain_map[i], sc->pg_bd_chain[i],
3876                             BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr,
3877                             &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3878
3879                         if (error || sc->pg_bd_chain_paddr[i] == 0) {
3880                                 BCE_PRINTF("%s(%d): Could not map page descriptor "
3881                                         "chain DMA memory!\n", __FILE__, __LINE__);
3882                                 rc = ENOMEM;
3883                                 goto bce_dma_alloc_exit;
3884                         }
3885
3886                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = "
3887                                 "0x%jX\n", __FUNCTION__, i,
3888                                 (uintmax_t) sc->pg_bd_chain_paddr[i]);
3889                 }
3890
3891                 /*
3892                  * Create a DMA tag for page mbufs.
3893                  */
3894                 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3895                     sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
3896                     1, MCLBYTES, 0, NULL, NULL, &sc->pg_mbuf_tag)) {
3897                         BCE_PRINTF("%s(%d): Could not allocate page mbuf "
3898                                 "DMA tag!\n", __FILE__, __LINE__);
3899                         rc = ENOMEM;
3900                         goto bce_dma_alloc_exit;
3901                 }
3902
3903                 /* Create DMA maps for the page mbuf clusters. */
3904                 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) {
3905                         if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT,
3906                                 &sc->pg_mbuf_map[i])) {
3907                                 BCE_PRINTF("%s(%d): Unable to create page mbuf "
3908                                         "DMA map!\n", __FILE__, __LINE__);
3909                                 rc = ENOMEM;
3910                                 goto bce_dma_alloc_exit;
3911                         }
3912                 }
3913         }
3914
3915 bce_dma_alloc_exit:
3916         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3917         return(rc);
3918 }
3919
3920
3921 /****************************************************************************/
3922 /* Release all resources used by the driver.                                */
3923 /*                                                                          */
3924 /* Releases all resources acquired by the driver including interrupts,      */
3925 /* interrupt handler, interfaces, mutexes, and DMA memory.                  */
3926 /*                                                                          */
3927 /* Returns:                                                                 */
3928 /*   Nothing.                                                               */
3929 /****************************************************************************/
3930 static void
3931 bce_release_resources(struct bce_softc *sc)
3932 {
3933         device_t dev;
3934
3935         DBENTER(BCE_VERBOSE_RESET);
3936
3937         dev = sc->bce_dev;
3938
3939         bce_dma_free(sc);
3940
3941         if (sc->bce_intrhand != NULL) {
3942                 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n");
3943                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
3944         }
3945
3946         if (sc->bce_res_irq != NULL) {
3947                 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n");
3948                 bus_release_resource(dev, SYS_RES_IRQ,
3949                     rman_get_rid(sc->bce_res_irq), sc->bce_res_irq);
3950         }
3951
3952         if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) {
3953                 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n");
3954                 pci_release_msi(dev);
3955         }
3956
3957         if (sc->bce_res_mem != NULL) {
3958                 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n");
3959                     bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
3960                     sc->bce_res_mem);
3961         }
3962
3963         if (sc->bce_ifp != NULL) {
3964                 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n");
3965                 if_free(sc->bce_ifp);
3966         }
3967
3968         if (mtx_initialized(&sc->bce_mtx))
3969                 BCE_LOCK_DESTROY(sc);
3970
3971         DBEXIT(BCE_VERBOSE_RESET);
3972 }
3973
3974
3975 /****************************************************************************/
3976 /* Firmware synchronization.                                                */
3977 /*                                                                          */
3978 /* Before performing certain events such as a chip reset, synchronize with  */
3979 /* the firmware first.                                                      */
3980 /*                                                                          */
3981 /* Returns:                                                                 */
3982 /*   0 for success, positive value for failure.                             */
3983 /****************************************************************************/
3984 static int
3985 bce_fw_sync(struct bce_softc *sc, u32 msg_data)
3986 {
3987         int i, rc = 0;
3988         u32 val;
3989
3990         DBENTER(BCE_VERBOSE_RESET);
3991
3992         /* Don't waste any time if we've timed out before. */
3993         if (sc->bce_fw_timed_out == TRUE) {
3994                 rc = EBUSY;
3995                 goto bce_fw_sync_exit;
3996         }
3997
3998         /* Increment the message sequence number. */
3999         sc->bce_fw_wr_seq++;
4000         msg_data |= sc->bce_fw_wr_seq;
4001
4002         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = "
4003             "0x%08X\n", msg_data);
4004
4005         /* Send the message to the bootcode driver mailbox. */
4006         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
4007
4008         /* Wait for the bootcode to acknowledge the message. */
4009         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
4010                 /* Check for a response in the bootcode firmware mailbox. */
4011                 val = bce_shmem_rd(sc, BCE_FW_MB);
4012                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
4013                         break;
4014                 DELAY(1000);
4015         }
4016
4017         /* If we've timed out, tell bootcode that we've stopped waiting. */
4018         if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) &&
4019             ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) {
4020
4021                 BCE_PRINTF("%s(%d): Firmware synchronization timeout! "
4022                     "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data);
4023
4024                 msg_data &= ~BCE_DRV_MSG_CODE;
4025                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
4026
4027                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
4028
4029                 sc->bce_fw_timed_out = TRUE;
4030                 rc = EBUSY;
4031         }
4032
4033 bce_fw_sync_exit:
4034         DBEXIT(BCE_VERBOSE_RESET);
4035         return (rc);
4036 }
4037
4038
4039 /****************************************************************************/
4040 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
4041 /*                                                                          */
4042 /* Returns:                                                                 */
4043 /*   Nothing.                                                               */
4044 /****************************************************************************/
4045 static void
4046 bce_load_rv2p_fw(struct bce_softc *sc, const u32 *rv2p_code,
4047         u32 rv2p_code_len, u32 rv2p_proc)
4048 {
4049         int i;
4050         u32 val;
4051
4052         DBENTER(BCE_VERBOSE_RESET);
4053
4054         /* Set the page size used by RV2P. */
4055         if (rv2p_proc == RV2P_PROC2) {
4056                 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE);
4057         }
4058
4059         for (i = 0; i < rv2p_code_len; i += 8) {
4060                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
4061                 rv2p_code++;
4062                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
4063                 rv2p_code++;
4064
4065                 if (rv2p_proc == RV2P_PROC1) {
4066                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
4067                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
4068                 }
4069                 else {
4070                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
4071                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
4072                 }
4073         }
4074
4075         /* Reset the processor, un-stall is done later. */
4076         if (rv2p_proc == RV2P_PROC1) {
4077                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
4078         }
4079         else {
4080                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
4081         }
4082
4083         DBEXIT(BCE_VERBOSE_RESET);
4084 }
4085
4086
4087 /****************************************************************************/
4088 /* Load RISC processor firmware.                                            */
4089 /*                                                                          */
4090 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
4091 /* associated with a particular processor.                                  */
4092 /*                                                                          */
4093 /* Returns:                                                                 */
4094 /*   Nothing.                                                               */
4095 /****************************************************************************/
4096 static void
4097 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
4098         struct fw_info *fw)
4099 {
4100         u32 offset;
4101
4102         DBENTER(BCE_VERBOSE_RESET);
4103
4104     bce_halt_cpu(sc, cpu_reg);
4105
4106         /* Load the Text area. */
4107         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
4108         if (fw->text) {
4109                 int j;
4110
4111                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
4112                         REG_WR_IND(sc, offset, fw->text[j]);
4113                 }
4114         }
4115
4116         /* Load the Data area. */
4117         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
4118         if (fw->data) {
4119                 int j;
4120
4121                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
4122                         REG_WR_IND(sc, offset, fw->data[j]);
4123                 }
4124         }
4125
4126         /* Load the SBSS area. */
4127         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
4128         if (fw->sbss) {
4129                 int j;
4130
4131                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
4132                         REG_WR_IND(sc, offset, fw->sbss[j]);
4133                 }
4134         }
4135
4136         /* Load the BSS area. */
4137         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
4138         if (fw->bss) {
4139                 int j;
4140
4141                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
4142                         REG_WR_IND(sc, offset, fw->bss[j]);
4143                 }
4144         }
4145
4146         /* Load the Read-Only area. */
4147         offset = cpu_reg->spad_base +
4148                 (fw->rodata_addr - cpu_reg->mips_view_base);
4149         if (fw->rodata) {
4150                 int j;
4151
4152                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
4153                         REG_WR_IND(sc, offset, fw->rodata[j]);
4154                 }
4155         }
4156
4157         /* Clear the pre-fetch instruction and set the FW start address. */
4158         REG_WR_IND(sc, cpu_reg->inst, 0);
4159         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
4160
4161         DBEXIT(BCE_VERBOSE_RESET);
4162 }
4163
4164
4165 /****************************************************************************/
4166 /* Starts the RISC processor.                                               */
4167 /*                                                                          */
4168 /* Assumes the CPU starting address has already been set.                   */
4169 /*                                                                          */
4170 /* Returns:                                                                 */
4171 /*   Nothing.                                                               */
4172 /****************************************************************************/
4173 static void
4174 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4175 {
4176         u32 val;
4177
4178         DBENTER(BCE_VERBOSE_RESET);
4179
4180         /* Start the CPU. */
4181         val = REG_RD_IND(sc, cpu_reg->mode);
4182         val &= ~cpu_reg->mode_value_halt;
4183         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4184         REG_WR_IND(sc, cpu_reg->mode, val);
4185
4186         DBEXIT(BCE_VERBOSE_RESET);
4187 }
4188
4189
4190 /****************************************************************************/
4191 /* Halts the RISC processor.                                                */
4192 /*                                                                          */
4193 /* Returns:                                                                 */
4194 /*   Nothing.                                                               */
4195 /****************************************************************************/
4196 static void
4197 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4198 {
4199         u32 val;
4200
4201         DBENTER(BCE_VERBOSE_RESET);
4202
4203         /* Halt the CPU. */
4204         val = REG_RD_IND(sc, cpu_reg->mode);
4205         val |= cpu_reg->mode_value_halt;
4206         REG_WR_IND(sc, cpu_reg->mode, val);
4207         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4208
4209         DBEXIT(BCE_VERBOSE_RESET);
4210 }
4211
4212
4213 /****************************************************************************/
4214 /* Initialize the RX CPU.                                                   */
4215 /*                                                                          */
4216 /* Returns:                                                                 */
4217 /*   Nothing.                                                               */
4218 /****************************************************************************/
4219 static void
4220 bce_start_rxp_cpu(struct bce_softc *sc)
4221 {
4222         struct cpu_reg cpu_reg;
4223
4224         DBENTER(BCE_VERBOSE_RESET);
4225
4226         cpu_reg.mode = BCE_RXP_CPU_MODE;
4227         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4228         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4229         cpu_reg.state = BCE_RXP_CPU_STATE;
4230         cpu_reg.state_value_clear = 0xffffff;
4231         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4232         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4233         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4234         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4235         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4236         cpu_reg.spad_base = BCE_RXP_SCRATCH;
4237         cpu_reg.mips_view_base = 0x8000000;
4238
4239         DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n");
4240         bce_start_cpu(sc, &cpu_reg);
4241
4242         DBEXIT(BCE_VERBOSE_RESET);
4243 }
4244
4245
4246 /****************************************************************************/
4247 /* Initialize the RX CPU.                                                   */
4248 /*                                                                          */
4249 /* Returns:                                                                 */
4250 /*   Nothing.                                                               */
4251 /****************************************************************************/
4252 static void
4253 bce_init_rxp_cpu(struct bce_softc *sc)
4254 {
4255         struct cpu_reg cpu_reg;
4256         struct fw_info fw;
4257
4258         DBENTER(BCE_VERBOSE_RESET);
4259
4260         cpu_reg.mode = BCE_RXP_CPU_MODE;
4261         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4262         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4263         cpu_reg.state = BCE_RXP_CPU_STATE;
4264         cpu_reg.state_value_clear = 0xffffff;
4265         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4266         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4267         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4268         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4269         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4270         cpu_reg.spad_base = BCE_RXP_SCRATCH;
4271         cpu_reg.mips_view_base = 0x8000000;
4272
4273         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4274                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
4275                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
4276                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
4277                 fw.start_addr = bce_RXP_b09FwStartAddr;
4278
4279                 fw.text_addr = bce_RXP_b09FwTextAddr;
4280                 fw.text_len = bce_RXP_b09FwTextLen;
4281                 fw.text_index = 0;
4282                 fw.text = bce_RXP_b09FwText;
4283
4284                 fw.data_addr = bce_RXP_b09FwDataAddr;
4285                 fw.data_len = bce_RXP_b09FwDataLen;
4286                 fw.data_index = 0;
4287                 fw.data = bce_RXP_b09FwData;
4288
4289                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
4290                 fw.sbss_len = bce_RXP_b09FwSbssLen;
4291                 fw.sbss_index = 0;
4292                 fw.sbss = bce_RXP_b09FwSbss;
4293
4294                 fw.bss_addr = bce_RXP_b09FwBssAddr;
4295                 fw.bss_len = bce_RXP_b09FwBssLen;
4296                 fw.bss_index = 0;
4297                 fw.bss = bce_RXP_b09FwBss;
4298
4299                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
4300                 fw.rodata_len = bce_RXP_b09FwRodataLen;
4301                 fw.rodata_index = 0;
4302                 fw.rodata = bce_RXP_b09FwRodata;
4303         } else {
4304                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
4305                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
4306                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
4307                 fw.start_addr = bce_RXP_b06FwStartAddr;
4308
4309                 fw.text_addr = bce_RXP_b06FwTextAddr;
4310                 fw.text_len = bce_RXP_b06FwTextLen;
4311                 fw.text_index = 0;
4312                 fw.text = bce_RXP_b06FwText;
4313
4314                 fw.data_addr = bce_RXP_b06FwDataAddr;
4315                 fw.data_len = bce_RXP_b06FwDataLen;
4316                 fw.data_index = 0;
4317                 fw.data = bce_RXP_b06FwData;
4318
4319                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
4320                 fw.sbss_len = bce_RXP_b06FwSbssLen;
4321                 fw.sbss_index = 0;
4322                 fw.sbss = bce_RXP_b06FwSbss;
4323
4324                 fw.bss_addr = bce_RXP_b06FwBssAddr;
4325                 fw.bss_len = bce_RXP_b06FwBssLen;
4326                 fw.bss_index = 0;
4327                 fw.bss = bce_RXP_b06FwBss;
4328
4329                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
4330                 fw.rodata_len = bce_RXP_b06FwRodataLen;
4331                 fw.rodata_index = 0;
4332                 fw.rodata = bce_RXP_b06FwRodata;
4333         }
4334
4335         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
4336         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4337
4338     /* Delay RXP start until initialization is complete. */
4339
4340         DBEXIT(BCE_VERBOSE_RESET);
4341 }
4342
4343
4344 /****************************************************************************/
4345 /* Initialize the TX CPU.                                                   */
4346 /*                                                                          */
4347 /* Returns:                                                                 */
4348 /*   Nothing.                                                               */
4349 /****************************************************************************/
4350 static void
4351 bce_init_txp_cpu(struct bce_softc *sc)
4352 {
4353         struct cpu_reg cpu_reg;
4354         struct fw_info fw;
4355
4356         DBENTER(BCE_VERBOSE_RESET);
4357
4358         cpu_reg.mode = BCE_TXP_CPU_MODE;
4359         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
4360         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
4361         cpu_reg.state = BCE_TXP_CPU_STATE;
4362         cpu_reg.state_value_clear = 0xffffff;
4363         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
4364         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
4365         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
4366         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
4367         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
4368         cpu_reg.spad_base = BCE_TXP_SCRATCH;
4369         cpu_reg.mips_view_base = 0x8000000;
4370
4371         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4372                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
4373                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
4374                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
4375                 fw.start_addr = bce_TXP_b09FwStartAddr;
4376
4377                 fw.text_addr = bce_TXP_b09FwTextAddr;
4378                 fw.text_len = bce_TXP_b09FwTextLen;
4379                 fw.text_index = 0;
4380                 fw.text = bce_TXP_b09FwText;
4381
4382                 fw.data_addr = bce_TXP_b09FwDataAddr;
4383                 fw.data_len = bce_TXP_b09FwDataLen;
4384                 fw.data_index = 0;
4385                 fw.data = bce_TXP_b09FwData;
4386
4387                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
4388                 fw.sbss_len = bce_TXP_b09FwSbssLen;
4389                 fw.sbss_index = 0;
4390                 fw.sbss = bce_TXP_b09FwSbss;
4391
4392                 fw.bss_addr = bce_TXP_b09FwBssAddr;
4393                 fw.bss_len = bce_TXP_b09FwBssLen;
4394                 fw.bss_index = 0;
4395                 fw.bss = bce_TXP_b09FwBss;
4396
4397                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
4398                 fw.rodata_len = bce_TXP_b09FwRodataLen;
4399                 fw.rodata_index = 0;
4400                 fw.rodata = bce_TXP_b09FwRodata;
4401         } else {
4402                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
4403                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
4404                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
4405                 fw.start_addr = bce_TXP_b06FwStartAddr;
4406
4407                 fw.text_addr = bce_TXP_b06FwTextAddr;
4408                 fw.text_len = bce_TXP_b06FwTextLen;
4409                 fw.text_index = 0;
4410                 fw.text = bce_TXP_b06FwText;
4411
4412                 fw.data_addr = bce_TXP_b06FwDataAddr;
4413                 fw.data_len = bce_TXP_b06FwDataLen;
4414                 fw.data_index = 0;
4415                 fw.data = bce_TXP_b06FwData;
4416
4417                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
4418                 fw.sbss_len = bce_TXP_b06FwSbssLen;
4419                 fw.sbss_index = 0;
4420                 fw.sbss = bce_TXP_b06FwSbss;
4421
4422                 fw.bss_addr = bce_TXP_b06FwBssAddr;
4423                 fw.bss_len = bce_TXP_b06FwBssLen;
4424                 fw.bss_index = 0;
4425                 fw.bss = bce_TXP_b06FwBss;
4426
4427                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
4428                 fw.rodata_len = bce_TXP_b06FwRodataLen;
4429                 fw.rodata_index = 0;
4430                 fw.rodata = bce_TXP_b06FwRodata;
4431         }
4432
4433         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
4434         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4435     bce_start_cpu(sc, &cpu_reg);
4436
4437         DBEXIT(BCE_VERBOSE_RESET);
4438 }
4439
4440
4441 /****************************************************************************/
4442 /* Initialize the TPAT CPU.                                                 */
4443 /*                                                                          */
4444 /* Returns:                                                                 */
4445 /*   Nothing.                                                               */
4446 /****************************************************************************/
4447 static void
4448 bce_init_tpat_cpu(struct bce_softc *sc)
4449 {
4450         struct cpu_reg cpu_reg;
4451         struct fw_info fw;
4452
4453         DBENTER(BCE_VERBOSE_RESET);
4454
4455         cpu_reg.mode = BCE_TPAT_CPU_MODE;
4456         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
4457         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
4458         cpu_reg.state = BCE_TPAT_CPU_STATE;
4459         cpu_reg.state_value_clear = 0xffffff;
4460         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
4461         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
4462         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
4463         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
4464         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
4465         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
4466         cpu_reg.mips_view_base = 0x8000000;
4467
4468         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4469                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
4470                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
4471                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
4472                 fw.start_addr = bce_TPAT_b09FwStartAddr;
4473
4474                 fw.text_addr = bce_TPAT_b09FwTextAddr;
4475                 fw.text_len = bce_TPAT_b09FwTextLen;
4476                 fw.text_index = 0;
4477                 fw.text = bce_TPAT_b09FwText;
4478
4479                 fw.data_addr = bce_TPAT_b09FwDataAddr;
4480                 fw.data_len = bce_TPAT_b09FwDataLen;
4481                 fw.data_index = 0;
4482                 fw.data = bce_TPAT_b09FwData;
4483
4484                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
4485                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
4486                 fw.sbss_index = 0;
4487                 fw.sbss = bce_TPAT_b09FwSbss;
4488
4489                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
4490                 fw.bss_len = bce_TPAT_b09FwBssLen;
4491                 fw.bss_index = 0;
4492                 fw.bss = bce_TPAT_b09FwBss;
4493
4494                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
4495                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
4496                 fw.rodata_index = 0;
4497                 fw.rodata = bce_TPAT_b09FwRodata;
4498         } else {
4499                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
4500                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
4501                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
4502                 fw.start_addr = bce_TPAT_b06FwStartAddr;
4503
4504                 fw.text_addr = bce_TPAT_b06FwTextAddr;
4505                 fw.text_len = bce_TPAT_b06FwTextLen;
4506                 fw.text_index = 0;
4507                 fw.text = bce_TPAT_b06FwText;
4508
4509                 fw.data_addr = bce_TPAT_b06FwDataAddr;
4510                 fw.data_len = bce_TPAT_b06FwDataLen;
4511                 fw.data_index = 0;
4512                 fw.data = bce_TPAT_b06FwData;
4513
4514                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
4515                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
4516                 fw.sbss_index = 0;
4517                 fw.sbss = bce_TPAT_b06FwSbss;
4518
4519                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
4520                 fw.bss_len = bce_TPAT_b06FwBssLen;
4521                 fw.bss_index = 0;
4522                 fw.bss = bce_TPAT_b06FwBss;
4523
4524                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
4525                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
4526                 fw.rodata_index = 0;
4527                 fw.rodata = bce_TPAT_b06FwRodata;
4528         }
4529
4530         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
4531         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4532         bce_start_cpu(sc, &cpu_reg);
4533
4534         DBEXIT(BCE_VERBOSE_RESET);
4535 }
4536
4537
4538 /****************************************************************************/
4539 /* Initialize the CP CPU.                                                   */
4540 /*                                                                          */
4541 /* Returns:                                                                 */
4542 /*   Nothing.                                                               */
4543 /****************************************************************************/
4544 static void
4545 bce_init_cp_cpu(struct bce_softc *sc)
4546 {
4547         struct cpu_reg cpu_reg;
4548         struct fw_info fw;
4549
4550         DBENTER(BCE_VERBOSE_RESET);
4551
4552         cpu_reg.mode = BCE_CP_CPU_MODE;
4553         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
4554         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
4555         cpu_reg.state = BCE_CP_CPU_STATE;
4556         cpu_reg.state_value_clear = 0xffffff;
4557         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
4558         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
4559         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
4560         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
4561         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
4562         cpu_reg.spad_base = BCE_CP_SCRATCH;
4563         cpu_reg.mips_view_base = 0x8000000;
4564
4565         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4566                 fw.ver_major = bce_CP_b09FwReleaseMajor;
4567                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
4568                 fw.ver_fix = bce_CP_b09FwReleaseFix;
4569                 fw.start_addr = bce_CP_b09FwStartAddr;
4570
4571                 fw.text_addr = bce_CP_b09FwTextAddr;
4572                 fw.text_len = bce_CP_b09FwTextLen;
4573                 fw.text_index = 0;
4574                 fw.text = bce_CP_b09FwText;
4575
4576                 fw.data_addr = bce_CP_b09FwDataAddr;
4577                 fw.data_len = bce_CP_b09FwDataLen;
4578                 fw.data_index = 0;
4579                 fw.data = bce_CP_b09FwData;
4580
4581                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
4582                 fw.sbss_len = bce_CP_b09FwSbssLen;
4583                 fw.sbss_index = 0;
4584                 fw.sbss = bce_CP_b09FwSbss;
4585
4586                 fw.bss_addr = bce_CP_b09FwBssAddr;
4587                 fw.bss_len = bce_CP_b09FwBssLen;
4588                 fw.bss_index = 0;
4589                 fw.bss = bce_CP_b09FwBss;
4590
4591                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
4592                 fw.rodata_len = bce_CP_b09FwRodataLen;
4593                 fw.rodata_index = 0;
4594                 fw.rodata = bce_CP_b09FwRodata;
4595         } else {
4596                 fw.ver_major = bce_CP_b06FwReleaseMajor;
4597                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
4598                 fw.ver_fix = bce_CP_b06FwReleaseFix;
4599                 fw.start_addr = bce_CP_b06FwStartAddr;
4600
4601                 fw.text_addr = bce_CP_b06FwTextAddr;
4602                 fw.text_len = bce_CP_b06FwTextLen;
4603                 fw.text_index = 0;
4604                 fw.text = bce_CP_b06FwText;
4605
4606                 fw.data_addr = bce_CP_b06FwDataAddr;
4607                 fw.data_len = bce_CP_b06FwDataLen;
4608                 fw.data_index = 0;
4609                 fw.data = bce_CP_b06FwData;
4610
4611                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
4612                 fw.sbss_len = bce_CP_b06FwSbssLen;
4613                 fw.sbss_index = 0;
4614                 fw.sbss = bce_CP_b06FwSbss;
4615
4616                 fw.bss_addr = bce_CP_b06FwBssAddr;
4617                 fw.bss_len = bce_CP_b06FwBssLen;
4618                 fw.bss_index = 0;
4619                 fw.bss = bce_CP_b06FwBss;
4620
4621                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
4622                 fw.rodata_len = bce_CP_b06FwRodataLen;
4623                 fw.rodata_index = 0;
4624                 fw.rodata = bce_CP_b06FwRodata;
4625         }
4626
4627         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
4628         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4629         bce_start_cpu(sc, &cpu_reg);
4630
4631         DBEXIT(BCE_VERBOSE_RESET);
4632 }
4633
4634
4635 /****************************************************************************/
4636 /* Initialize the COM CPU.                                                 */
4637 /*                                                                          */
4638 /* Returns:                                                                 */
4639 /*   Nothing.                                                               */
4640 /****************************************************************************/
4641 static void
4642 bce_init_com_cpu(struct bce_softc *sc)
4643 {
4644         struct cpu_reg cpu_reg;
4645         struct fw_info fw;
4646
4647         DBENTER(BCE_VERBOSE_RESET);
4648
4649         cpu_reg.mode = BCE_COM_CPU_MODE;
4650         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
4651         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
4652         cpu_reg.state = BCE_COM_CPU_STATE;
4653         cpu_reg.state_value_clear = 0xffffff;
4654         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
4655         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
4656         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
4657         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
4658         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
4659         cpu_reg.spad_base = BCE_COM_SCRATCH;
4660         cpu_reg.mips_view_base = 0x8000000;
4661
4662         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4663                 fw.ver_major = bce_COM_b09FwReleaseMajor;
4664                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
4665                 fw.ver_fix = bce_COM_b09FwReleaseFix;
4666                 fw.start_addr = bce_COM_b09FwStartAddr;
4667
4668                 fw.text_addr = bce_COM_b09FwTextAddr;
4669                 fw.text_len = bce_COM_b09FwTextLen;
4670                 fw.text_index = 0;
4671                 fw.text = bce_COM_b09FwText;
4672
4673                 fw.data_addr = bce_COM_b09FwDataAddr;
4674                 fw.data_len = bce_COM_b09FwDataLen;
4675                 fw.data_index = 0;
4676                 fw.data = bce_COM_b09FwData;
4677
4678                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
4679                 fw.sbss_len = bce_COM_b09FwSbssLen;
4680                 fw.sbss_index = 0;
4681                 fw.sbss = bce_COM_b09FwSbss;
4682
4683                 fw.bss_addr = bce_COM_b09FwBssAddr;
4684                 fw.bss_len = bce_COM_b09FwBssLen;
4685                 fw.bss_index = 0;
4686                 fw.bss = bce_COM_b09FwBss;
4687
4688                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
4689                 fw.rodata_len = bce_COM_b09FwRodataLen;
4690                 fw.rodata_index = 0;
4691                 fw.rodata = bce_COM_b09FwRodata;
4692         } else {
4693                 fw.ver_major = bce_COM_b06FwReleaseMajor;
4694                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
4695                 fw.ver_fix = bce_COM_b06FwReleaseFix;
4696                 fw.start_addr = bce_COM_b06FwStartAddr;
4697
4698                 fw.text_addr = bce_COM_b06FwTextAddr;
4699                 fw.text_len = bce_COM_b06FwTextLen;
4700                 fw.text_index = 0;
4701                 fw.text = bce_COM_b06FwText;
4702
4703                 fw.data_addr = bce_COM_b06FwDataAddr;
4704                 fw.data_len = bce_COM_b06FwDataLen;
4705                 fw.data_index = 0;
4706                 fw.data = bce_COM_b06FwData;
4707
4708                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
4709                 fw.sbss_len = bce_COM_b06FwSbssLen;
4710                 fw.sbss_index = 0;
4711                 fw.sbss = bce_COM_b06FwSbss;
4712
4713                 fw.bss_addr = bce_COM_b06FwBssAddr;
4714                 fw.bss_len = bce_COM_b06FwBssLen;
4715                 fw.bss_index = 0;
4716                 fw.bss = bce_COM_b06FwBss;
4717
4718                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
4719                 fw.rodata_len = bce_COM_b06FwRodataLen;
4720                 fw.rodata_index = 0;
4721                 fw.rodata = bce_COM_b06FwRodata;
4722         }
4723
4724         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
4725         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4726         bce_start_cpu(sc, &cpu_reg);
4727
4728         DBEXIT(BCE_VERBOSE_RESET);
4729 }
4730
4731
4732 /****************************************************************************/
4733 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
4734 /*                                                                          */
4735 /* Loads the firmware for each CPU and starts the CPU.                      */
4736 /*                                                                          */
4737 /* Returns:                                                                 */
4738 /*   Nothing.                                                               */
4739 /****************************************************************************/
4740 static void
4741 bce_init_cpus(struct bce_softc *sc)
4742 {
4743         DBENTER(BCE_VERBOSE_RESET);
4744
4745         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4746
4747                 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) {
4748                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
4749                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
4750                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
4751                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
4752                 } else {
4753                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
4754                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
4755                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
4756                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
4757                 }
4758
4759         } else {
4760                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
4761                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
4762                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
4763                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
4764         }
4765
4766         bce_init_rxp_cpu(sc);
4767         bce_init_txp_cpu(sc);
4768         bce_init_tpat_cpu(sc);
4769         bce_init_com_cpu(sc);
4770         bce_init_cp_cpu(sc);
4771
4772         DBEXIT(BCE_VERBOSE_RESET);
4773 }
4774
4775
4776 /****************************************************************************/
4777 /* Initialize context memory.                                               */
4778 /*                                                                          */
4779 /* Clears the memory associated with each Context ID (CID).                 */
4780 /*                                                                          */
4781 /* Returns:                                                                 */
4782 /*   Nothing.                                                               */
4783 /****************************************************************************/
4784 static int
4785 bce_init_ctx(struct bce_softc *sc)
4786 {
4787         u32 offset, val, vcid_addr;
4788         int i, j, rc, retry_cnt;
4789
4790         rc = 0;
4791         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4792
4793         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4794                 retry_cnt = CTX_INIT_RETRY_COUNT;
4795
4796                 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n");
4797
4798                 /*
4799                  * BCM5709 context memory may be cached
4800                  * in host memory so prepare the host memory
4801                  * for access.
4802                  */
4803                 val = BCE_CTX_COMMAND_ENABLED |
4804                     BCE_CTX_COMMAND_MEM_INIT | (1 << 12);
4805                 val |= (BCM_PAGE_BITS - 8) << 16;
4806                 REG_WR(sc, BCE_CTX_COMMAND, val);
4807
4808                 /* Wait for mem init command to complete. */
4809                 for (i = 0; i < retry_cnt; i++) {
4810                         val = REG_RD(sc, BCE_CTX_COMMAND);
4811                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
4812                                 break;
4813                         DELAY(2);
4814                 }
4815                 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) {
4816                         BCE_PRINTF("%s(): Context memory initialization failed!\n",
4817                             __FUNCTION__);
4818                         rc = EBUSY;
4819                         goto init_ctx_fail;
4820                 }
4821
4822                 for (i = 0; i < sc->ctx_pages; i++) {
4823                         /* Set the physical address of the context memory. */
4824                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
4825                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
4826                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
4827                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
4828                             BCE_ADDR_HI(sc->ctx_paddr[i]));
4829                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i |
4830                             BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
4831
4832                         /* Verify the context memory write was successful. */
4833                         for (j = 0; j < retry_cnt; j++) {
4834                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
4835                                 if ((val &
4836                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
4837                                         break;
4838                                 DELAY(5);
4839                         }
4840                         if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) {
4841                                 BCE_PRINTF("%s(): Failed to initialize "
4842                                     "context page %d!\n", __FUNCTION__, i);
4843                                 rc = EBUSY;
4844                                 goto init_ctx_fail;
4845                         }
4846                 }
4847         } else {
4848
4849                 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n");
4850
4851                 /*
4852                  * For the 5706/5708, context memory is local to
4853                  * the controller, so initialize the controller
4854                  * context memory.
4855                  */
4856
4857                 vcid_addr = GET_CID_ADDR(96);
4858                 while (vcid_addr) {
4859
4860                         vcid_addr -= PHY_CTX_SIZE;
4861
4862                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
4863                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4864
4865                         for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
4866                                 CTX_WR(sc, 0x00, offset, 0);
4867                         }
4868
4869                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
4870                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4871                 }
4872
4873         }
4874 init_ctx_fail:
4875         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4876         return (rc);
4877 }
4878
4879
4880 /****************************************************************************/
4881 /* Fetch the permanent MAC address of the controller.                       */
4882 /*                                                                          */
4883 /* Returns:                                                                 */
4884 /*   Nothing.                                                               */
4885 /****************************************************************************/
4886 static void
4887 bce_get_mac_addr(struct bce_softc *sc)
4888 {
4889         u32 mac_lo = 0, mac_hi = 0;
4890
4891         DBENTER(BCE_VERBOSE_RESET);
4892
4893         /*
4894          * The NetXtreme II bootcode populates various NIC
4895          * power-on and runtime configuration items in a
4896          * shared memory area.  The factory configured MAC
4897          * address is available from both NVRAM and the
4898          * shared memory area so we'll read the value from
4899          * shared memory for speed.
4900          */
4901
4902         mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER);
4903         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
4904
4905         if ((mac_lo == 0) && (mac_hi == 0)) {
4906                 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n",
4907                     __FILE__, __LINE__);
4908         } else {
4909                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
4910                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
4911                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
4912                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
4913                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
4914                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
4915         }
4916
4917         DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet "
4918             "address = %6D\n", sc->eaddr, ":");
4919         DBEXIT(BCE_VERBOSE_RESET);
4920 }
4921
4922
4923 /****************************************************************************/
4924 /* Program the MAC address.                                                 */
4925 /*                                                                          */
4926 /* Returns:                                                                 */
4927 /*   Nothing.                                                               */
4928 /****************************************************************************/
4929 static void
4930 bce_set_mac_addr(struct bce_softc *sc)
4931 {
4932         u32 val;
4933         u8 *mac_addr = sc->eaddr;
4934
4935         /* ToDo: Add support for setting multiple MAC addresses. */
4936
4937         DBENTER(BCE_VERBOSE_RESET);
4938         DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = "
4939             "%6D\n", sc->eaddr, ":");
4940
4941         val = (mac_addr[0] << 8) | mac_addr[1];
4942
4943         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
4944
4945         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
4946             (mac_addr[4] << 8) | mac_addr[5];
4947
4948         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
4949
4950         DBEXIT(BCE_VERBOSE_RESET);
4951 }
4952
4953
4954 /****************************************************************************/
4955 /* Stop the controller.                                                     */
4956 /*                                                                          */
4957 /* Returns:                                                                 */
4958 /*   Nothing.                                                               */
4959 /****************************************************************************/
4960 static void
4961 bce_stop(struct bce_softc *sc)
4962 {
4963         struct ifnet *ifp;
4964
4965         DBENTER(BCE_VERBOSE_RESET);
4966
4967         BCE_LOCK_ASSERT(sc);
4968
4969         ifp = sc->bce_ifp;
4970
4971         callout_stop(&sc->bce_tick_callout);
4972
4973         /* Disable the transmit/receive blocks. */
4974         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
4975         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
4976         DELAY(20);
4977
4978         bce_disable_intr(sc);
4979
4980         /* Free RX buffers. */
4981         if (bce_hdr_split == TRUE) {
4982                 bce_free_pg_chain(sc);
4983         }
4984         bce_free_rx_chain(sc);
4985
4986         /* Free TX buffers. */
4987         bce_free_tx_chain(sc);
4988
4989         sc->watchdog_timer = 0;
4990
4991         sc->bce_link_up = FALSE;
4992
4993         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4994
4995         DBEXIT(BCE_VERBOSE_RESET);
4996 }
4997
4998
4999 static int
5000 bce_reset(struct bce_softc *sc, u32 reset_code)
5001 {
5002         u32 emac_mode_save, val;
5003         int i, rc = 0;
5004         static const u32 emac_mode_mask = BCE_EMAC_MODE_PORT |
5005             BCE_EMAC_MODE_HALF_DUPLEX | BCE_EMAC_MODE_25G;
5006
5007         DBENTER(BCE_VERBOSE_RESET);
5008
5009         DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n",
5010             __FUNCTION__, reset_code);
5011
5012         /*
5013          * If ASF/IPMI is operational, then the EMAC Mode register already
5014          * contains appropriate values for the link settings that have
5015          * been auto-negotiated.  Resetting the chip will clobber those
5016          * values.  Save the important bits so we can restore them after
5017          * the reset.
5018          */
5019         emac_mode_save = REG_RD(sc, BCE_EMAC_MODE) & emac_mode_mask;
5020
5021         /* Wait for pending PCI transactions to complete. */
5022         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
5023             BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
5024             BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
5025             BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
5026             BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
5027         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
5028         DELAY(5);
5029
5030         /* Disable DMA */
5031         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5032                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
5033                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
5034                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
5035         }
5036
5037         /* Assume bootcode is running. */
5038         sc->bce_fw_timed_out = FALSE;
5039         sc->bce_drv_cardiac_arrest = FALSE;
5040
5041         /* Give the firmware a chance to prepare for the reset. */
5042         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
5043         if (rc)
5044                 goto bce_reset_exit;
5045
5046         /* Set a firmware reminder that this is a soft reset. */
5047         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC);
5048
5049         /* Dummy read to force the chip to complete all current transactions. */
5050         val = REG_RD(sc, BCE_MISC_ID);
5051
5052         /* Chip reset. */
5053         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5054                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
5055                 REG_RD(sc, BCE_MISC_COMMAND);
5056                 DELAY(5);
5057
5058                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5059                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
5060
5061                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
5062         } else {
5063                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5064                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5065                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
5066                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
5067
5068                 /* Allow up to 30us for reset to complete. */
5069                 for (i = 0; i < 10; i++) {
5070                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
5071                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5072                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
5073                                 break;
5074                         }
5075                         DELAY(10);
5076                 }
5077
5078                 /* Check that reset completed successfully. */
5079                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5080                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
5081                         BCE_PRINTF("%s(%d): Reset failed!\n",
5082                             __FILE__, __LINE__);
5083                         rc = EBUSY;
5084                         goto bce_reset_exit;
5085                 }
5086         }
5087
5088         /* Make sure byte swapping is properly configured. */
5089         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
5090         if (val != 0x01020304) {
5091                 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n",
5092                     __FILE__, __LINE__);
5093                 rc = ENODEV;
5094                 goto bce_reset_exit;
5095         }
5096
5097         /* Just completed a reset, assume that firmware is running again. */
5098         sc->bce_fw_timed_out = FALSE;
5099         sc->bce_drv_cardiac_arrest = FALSE;
5100
5101         /* Wait for the firmware to finish its initialization. */
5102         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
5103         if (rc)
5104                 BCE_PRINTF("%s(%d): Firmware did not complete "
5105                     "initialization!\n", __FILE__, __LINE__);
5106         /* Get firmware capabilities. */
5107         bce_fw_cap_init(sc);
5108
5109 bce_reset_exit:
5110         /* Restore EMAC Mode bits needed to keep ASF/IPMI running. */
5111         if (reset_code == BCE_DRV_MSG_CODE_RESET) {
5112                 val = REG_RD(sc, BCE_EMAC_MODE);
5113                 val = (val & ~emac_mode_mask) | emac_mode_save;
5114                 REG_WR(sc, BCE_EMAC_MODE, val);
5115         }
5116
5117         DBEXIT(BCE_VERBOSE_RESET);
5118         return (rc);
5119 }
5120
5121
5122 static int
5123 bce_chipinit(struct bce_softc *sc)
5124 {
5125         u32 val;
5126         int rc = 0;
5127
5128         DBENTER(BCE_VERBOSE_RESET);
5129
5130         bce_disable_intr(sc);
5131
5132         /*
5133          * Initialize DMA byte/word swapping, configure the number of DMA
5134          * channels and PCI clock compensation delay.
5135          */
5136         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
5137             BCE_DMA_CONFIG_DATA_WORD_SWAP |
5138 #if BYTE_ORDER == BIG_ENDIAN
5139             BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
5140 #endif
5141             BCE_DMA_CONFIG_CNTL_WORD_SWAP |
5142             DMA_READ_CHANS << 12 |
5143             DMA_WRITE_CHANS << 16;
5144
5145         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
5146
5147         if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133))
5148                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
5149
5150         /*
5151          * This setting resolves a problem observed on certain Intel PCI
5152          * chipsets that cannot handle multiple outstanding DMA operations.
5153          * See errata E9_5706A1_65.
5154          */
5155         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5156             (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) &&
5157             !(sc->bce_flags & BCE_PCIX_FLAG))
5158                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
5159
5160         REG_WR(sc, BCE_DMA_CONFIG, val);
5161
5162         /* Enable the RX_V2P and Context state machines before access. */
5163         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5164             BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
5165             BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
5166             BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
5167
5168         /* Initialize context mapping and zero out the quick contexts. */
5169         if ((rc = bce_init_ctx(sc)) != 0)
5170                 goto bce_chipinit_exit;
5171
5172         /* Initialize the on-boards CPUs */
5173         bce_init_cpus(sc);
5174
5175         /* Enable management frames (NC-SI) to flow to the MCP. */
5176         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5177                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
5178                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5179         }
5180
5181         /* Prepare NVRAM for access. */
5182         if ((rc = bce_init_nvram(sc)) != 0)
5183                 goto bce_chipinit_exit;
5184
5185         /* Set the kernel bypass block size */
5186         val = REG_RD(sc, BCE_MQ_CONFIG);
5187         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
5188         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
5189
5190         /* Enable bins used on the 5709. */
5191         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5192                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
5193                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
5194                         val |= BCE_MQ_CONFIG_HALT_DIS;
5195         }
5196
5197         REG_WR(sc, BCE_MQ_CONFIG, val);
5198
5199         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
5200         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
5201         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
5202
5203         /* Set the page size and clear the RV2P processor stall bits. */
5204         val = (BCM_PAGE_BITS - 8) << 24;
5205         REG_WR(sc, BCE_RV2P_CONFIG, val);
5206
5207         /* Configure page size. */
5208         val = REG_RD(sc, BCE_TBDR_CONFIG);
5209         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
5210         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
5211         REG_WR(sc, BCE_TBDR_CONFIG, val);
5212
5213         /* Set the perfect match control register to default. */
5214         REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
5215
5216 bce_chipinit_exit:
5217         DBEXIT(BCE_VERBOSE_RESET);
5218
5219         return(rc);
5220 }
5221
5222
5223 /****************************************************************************/
5224 /* Initialize the controller in preparation to send/receive traffic.        */
5225 /*                                                                          */
5226 /* Returns:                                                                 */
5227 /*   0 for success, positive value for failure.                             */
5228 /****************************************************************************/
5229 static int
5230 bce_blockinit(struct bce_softc *sc)
5231 {
5232         u32 reg, val;
5233         int rc = 0;
5234
5235         DBENTER(BCE_VERBOSE_RESET);
5236
5237         /* Load the hardware default MAC address. */
5238         bce_set_mac_addr(sc);
5239
5240         /* Set the Ethernet backoff seed value */
5241         val = sc->eaddr[0]         + (sc->eaddr[1] << 8) +
5242               (sc->eaddr[2] << 16) + (sc->eaddr[3]     ) +
5243               (sc->eaddr[4] << 8)  + (sc->eaddr[5] << 16);
5244         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
5245
5246         sc->last_status_idx = 0;
5247         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
5248
5249         /* Set up link change interrupt generation. */
5250         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
5251
5252         /* Program the physical address of the status block. */
5253         REG_WR(sc, BCE_HC_STATUS_ADDR_L,
5254             BCE_ADDR_LO(sc->status_block_paddr));
5255         REG_WR(sc, BCE_HC_STATUS_ADDR_H,
5256             BCE_ADDR_HI(sc->status_block_paddr));
5257
5258         /* Program the physical address of the statistics block. */
5259         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
5260             BCE_ADDR_LO(sc->stats_block_paddr));
5261         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
5262             BCE_ADDR_HI(sc->stats_block_paddr));
5263
5264         /*
5265          * Program various host coalescing parameters.
5266          * Trip points control how many BDs should be ready before generating
5267          * an interrupt while ticks control how long a BD can sit in the chain
5268          * before generating an interrupt.
5269          */
5270         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5271             (sc->bce_tx_quick_cons_trip_int << 16) |
5272             sc->bce_tx_quick_cons_trip);
5273         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5274             (sc->bce_rx_quick_cons_trip_int << 16) |
5275             sc->bce_rx_quick_cons_trip);
5276         REG_WR(sc, BCE_HC_TX_TICKS,
5277             (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
5278         REG_WR(sc, BCE_HC_RX_TICKS,
5279             (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
5280         REG_WR(sc, BCE_HC_STATS_TICKS, sc->bce_stats_ticks & 0xffff00);
5281         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
5282         /* Not used for L2. */
5283         REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 0);
5284         REG_WR(sc, BCE_HC_COM_TICKS, 0);
5285         REG_WR(sc, BCE_HC_CMD_TICKS, 0);
5286
5287         /* Configure the Host Coalescing block. */
5288         val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE |
5289             BCE_HC_CONFIG_COLLECT_STATS;
5290
5291 #if 0
5292         /* ToDo: Add MSI-X support. */
5293         if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
5294                 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) +
5295                     BCE_HC_SB_CONFIG_1;
5296
5297                 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL);
5298
5299                 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE |
5300                     BCE_HC_SB_CONFIG_1_ONE_SHOT);
5301
5302                 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF,
5303                     (sc->tx_quick_cons_trip_int << 16) |
5304                      sc->tx_quick_cons_trip);
5305
5306                 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF,
5307                     (sc->tx_ticks_int << 16) | sc->tx_ticks);
5308
5309                 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
5310         }
5311
5312         /*
5313          * Tell the HC block to automatically set the
5314          * INT_MASK bit after an MSI/MSI-X interrupt
5315          * is generated so the driver doesn't have to.
5316          */
5317         if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG)
5318                 val |= BCE_HC_CONFIG_ONE_SHOT;
5319
5320         /* Set the MSI-X status blocks to 128 byte boundaries. */
5321         if (sc->bce_flags & BCE_USING_MSIX_FLAG)
5322                 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
5323 #endif
5324
5325         REG_WR(sc, BCE_HC_CONFIG, val);
5326
5327         /* Clear the internal statistics counters. */
5328         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
5329
5330         /* Verify that bootcode is running. */
5331         reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
5332
5333         DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control),
5334             BCE_PRINTF("%s(%d): Simulating bootcode failure.\n",
5335             __FILE__, __LINE__);
5336             reg = 0);
5337
5338         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5339             BCE_DEV_INFO_SIGNATURE_MAGIC) {
5340                 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, "
5341                     "Expected: 08%08X\n", __FILE__, __LINE__,
5342                     (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK),
5343                     BCE_DEV_INFO_SIGNATURE_MAGIC);
5344                 rc = ENODEV;
5345                 goto bce_blockinit_exit;
5346         }
5347
5348         /* Enable DMA */
5349         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5350                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
5351                 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
5352                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
5353         }
5354
5355         /* Allow bootcode to apply additional fixes before enabling MAC. */
5356         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 |
5357             BCE_DRV_MSG_CODE_RESET);
5358
5359         /* Enable link state change interrupt generation. */
5360         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
5361
5362         /* Enable the RXP. */
5363         bce_start_rxp_cpu(sc);
5364
5365         /* Disable management frames (NC-SI) from flowing to the MCP. */
5366         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5367                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
5368                     ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
5369                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5370         }
5371
5372         /* Enable all remaining blocks in the MAC. */
5373         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
5374                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5375                     BCE_MISC_ENABLE_DEFAULT_XI);
5376         else
5377                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5378                     BCE_MISC_ENABLE_DEFAULT);
5379
5380         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
5381         DELAY(20);
5382
5383         /* Save the current host coalescing block settings. */
5384         sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
5385
5386 bce_blockinit_exit:
5387         DBEXIT(BCE_VERBOSE_RESET);
5388
5389         return (rc);
5390 }
5391
5392
5393 /****************************************************************************/
5394 /* Encapsulate an mbuf into the rx_bd chain.                                */
5395 /*                                                                          */
5396 /* Returns:                                                                 */
5397 /*   0 for success, positive value for failure.                             */
5398 /****************************************************************************/
5399 static int
5400 bce_get_rx_buf(struct bce_softc *sc, u16 prod, u16 chain_prod, u32 *prod_bseq)
5401 {
5402         bus_dma_segment_t segs[1];
5403         struct mbuf *m_new = NULL;
5404         struct rx_bd *rxbd;
5405         int nsegs, error, rc = 0;
5406 #ifdef BCE_DEBUG
5407         u16 debug_chain_prod = chain_prod;
5408 #endif
5409
5410         DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5411
5412         /* Make sure the inputs are valid. */
5413         DBRUNIF((chain_prod > MAX_RX_BD_ALLOC),
5414             BCE_PRINTF("%s(%d): RX producer out of range: "
5415             "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5416             chain_prod, (u16)MAX_RX_BD_ALLOC));
5417
5418         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5419             "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__,
5420             prod, chain_prod, *prod_bseq);
5421
5422         /* Update some debug statistic counters */
5423         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
5424             sc->rx_low_watermark = sc->free_rx_bd);
5425         DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
5426             sc->rx_empty_count++);
5427
5428         /* Simulate an mbuf allocation failure. */
5429         DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5430             sc->mbuf_alloc_failed_count++;
5431             sc->mbuf_alloc_failed_sim_count++;
5432             rc = ENOBUFS;
5433             goto bce_get_rx_buf_exit);
5434
5435         /* This is a new mbuf allocation. */
5436         if (bce_hdr_split == TRUE)
5437                 MGETHDR(m_new, M_NOWAIT, MT_DATA);
5438         else
5439                 m_new = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
5440                     sc->rx_bd_mbuf_alloc_size);
5441
5442         if (m_new == NULL) {
5443                 sc->mbuf_alloc_failed_count++;
5444                 rc = ENOBUFS;
5445                 goto bce_get_rx_buf_exit;
5446         }
5447
5448         DBRUN(sc->debug_rx_mbuf_alloc++);
5449
5450         /* Make sure we have a valid packet header. */
5451         M_ASSERTPKTHDR(m_new);
5452
5453         /* Initialize the mbuf size and pad if necessary for alignment. */
5454         m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size;
5455         m_adj(m_new, sc->rx_bd_mbuf_align_pad);
5456
5457         /* ToDo: Consider calling m_fragment() to test error handling. */
5458
5459         /* Map the mbuf cluster into device memory. */
5460         error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag,
5461             sc->rx_mbuf_map[chain_prod], m_new, segs, &nsegs, BUS_DMA_NOWAIT);
5462
5463         /* Handle any mapping errors. */
5464         if (error) {
5465                 BCE_PRINTF("%s(%d): Error mapping mbuf into RX "
5466                     "chain (%d)!\n", __FILE__, __LINE__, error);
5467
5468                 sc->dma_map_addr_rx_failed_count++;
5469                 m_freem(m_new);
5470
5471                 DBRUN(sc->debug_rx_mbuf_alloc--);
5472
5473                 rc = ENOBUFS;
5474                 goto bce_get_rx_buf_exit;
5475         }
5476
5477         /* All mbufs must map to a single segment. */
5478         KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",
5479             __FUNCTION__, nsegs));
5480
5481         /* Setup the rx_bd for the segment. */
5482         rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
5483
5484         rxbd->rx_bd_haddr_lo  = htole32(BCE_ADDR_LO(segs[0].ds_addr));
5485         rxbd->rx_bd_haddr_hi  = htole32(BCE_ADDR_HI(segs[0].ds_addr));
5486         rxbd->rx_bd_len       = htole32(segs[0].ds_len);
5487         rxbd->rx_bd_flags     = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5488         *prod_bseq += segs[0].ds_len;
5489
5490         /* Save the mbuf and update our counter. */
5491         sc->rx_mbuf_ptr[chain_prod] = m_new;
5492         sc->free_rx_bd -= nsegs;
5493
5494         DBRUNMSG(BCE_INSANE_RECV,
5495             bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs));
5496
5497         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5498             "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, prod,
5499             chain_prod, *prod_bseq);
5500
5501 bce_get_rx_buf_exit:
5502         DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5503
5504         return(rc);
5505 }
5506
5507
5508 /****************************************************************************/
5509 /* Encapsulate an mbuf cluster into the page chain.                         */
5510 /*                                                                          */
5511 /* Returns:                                                                 */
5512 /*   0 for success, positive value for failure.                             */
5513 /****************************************************************************/
5514 static int
5515 bce_get_pg_buf(struct bce_softc *sc, u16 prod, u16 prod_idx)
5516 {
5517         bus_dma_segment_t segs[1];
5518         struct mbuf *m_new = NULL;
5519         struct rx_bd *pgbd;
5520         int error, nsegs, rc = 0;
5521 #ifdef BCE_DEBUG
5522         u16 debug_prod_idx = prod_idx;
5523 #endif
5524
5525         DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5526
5527         /* Make sure the inputs are valid. */
5528         DBRUNIF((prod_idx > MAX_PG_BD_ALLOC),
5529             BCE_PRINTF("%s(%d): page producer out of range: "
5530             "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5531             prod_idx, (u16)MAX_PG_BD_ALLOC));
5532
5533         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5534             "chain_prod = 0x%04X\n", __FUNCTION__, prod, prod_idx);
5535
5536         /* Update counters if we've hit a new low or run out of pages. */
5537         DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark),
5538             sc->pg_low_watermark = sc->free_pg_bd);
5539         DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++);
5540
5541         /* Simulate an mbuf allocation failure. */
5542         DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5543             sc->mbuf_alloc_failed_count++;
5544             sc->mbuf_alloc_failed_sim_count++;
5545             rc = ENOBUFS;
5546             goto bce_get_pg_buf_exit);
5547
5548         /* This is a new mbuf allocation. */
5549         m_new = m_getcl(M_NOWAIT, MT_DATA, 0);
5550         if (m_new == NULL) {
5551                 sc->mbuf_alloc_failed_count++;
5552                 rc = ENOBUFS;
5553                 goto bce_get_pg_buf_exit;
5554         }
5555
5556         DBRUN(sc->debug_pg_mbuf_alloc++);
5557
5558         m_new->m_len = MCLBYTES;
5559
5560         /* ToDo: Consider calling m_fragment() to test error handling. */
5561
5562         /* Map the mbuf cluster into device memory. */
5563         error = bus_dmamap_load_mbuf_sg(sc->pg_mbuf_tag,
5564             sc->pg_mbuf_map[prod_idx], m_new, segs, &nsegs, BUS_DMA_NOWAIT);
5565
5566         /* Handle any mapping errors. */
5567         if (error) {
5568                 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n",
5569                     __FILE__, __LINE__);
5570
5571                 m_freem(m_new);
5572                 DBRUN(sc->debug_pg_mbuf_alloc--);
5573
5574                 rc = ENOBUFS;
5575                 goto bce_get_pg_buf_exit;
5576         }
5577
5578         /* All mbufs must map to a single segment. */
5579         KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",
5580             __FUNCTION__, nsegs));
5581
5582         /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */
5583
5584         /*
5585          * The page chain uses the same rx_bd data structure
5586          * as the receive chain but doesn't require a byte sequence (bseq).
5587          */
5588         pgbd = &sc->pg_bd_chain[PG_PAGE(prod_idx)][PG_IDX(prod_idx)];
5589
5590         pgbd->rx_bd_haddr_lo  = htole32(BCE_ADDR_LO(segs[0].ds_addr));
5591         pgbd->rx_bd_haddr_hi  = htole32(BCE_ADDR_HI(segs[0].ds_addr));
5592         pgbd->rx_bd_len       = htole32(MCLBYTES);
5593         pgbd->rx_bd_flags     = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5594
5595         /* Save the mbuf and update our counter. */
5596         sc->pg_mbuf_ptr[prod_idx] = m_new;
5597         sc->free_pg_bd--;
5598
5599         DBRUNMSG(BCE_INSANE_RECV,
5600             bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1));
5601
5602         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5603             "prod_idx = 0x%04X\n", __FUNCTION__, prod, prod_idx);
5604
5605 bce_get_pg_buf_exit:
5606         DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5607
5608         return(rc);
5609 }
5610
5611
5612 /****************************************************************************/
5613 /* Initialize the TX context memory.                                        */
5614 /*                                                                          */
5615 /* Returns:                                                                 */
5616 /*   Nothing                                                                */
5617 /****************************************************************************/
5618 static void
5619 bce_init_tx_context(struct bce_softc *sc)
5620 {
5621         u32 val;
5622
5623         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5624
5625         /* Initialize the context ID for an L2 TX chain. */
5626         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5627                 /* Set the CID type to support an L2 connection. */
5628                 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI |
5629                     BCE_L2CTX_TX_TYPE_SIZE_L2_XI;
5630                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
5631                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16);
5632                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5633                     BCE_L2CTX_TX_CMD_TYPE_XI, val);
5634
5635                 /* Point the hardware to the first page in the chain. */
5636                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5637                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5638                     BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
5639                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5640                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5641                     BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
5642         } else {
5643                 /* Set the CID type to support an L2 connection. */
5644                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
5645                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
5646                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
5647                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
5648
5649                 /* Point the hardware to the first page in the chain. */
5650                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5651                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5652                     BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
5653                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5654                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5655                     BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
5656         }
5657
5658         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5659 }
5660
5661
5662 /****************************************************************************/
5663 /* Allocate memory and initialize the TX data structures.                   */
5664 /*                                                                          */
5665 /* Returns:                                                                 */
5666 /*   0 for success, positive value for failure.                             */
5667 /****************************************************************************/
5668 static int
5669 bce_init_tx_chain(struct bce_softc *sc)
5670 {
5671         struct tx_bd *txbd;
5672         int i, rc = 0;
5673
5674         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5675
5676         /* Set the initial TX producer/consumer indices. */
5677         sc->tx_prod        = 0;
5678         sc->tx_cons        = 0;
5679         sc->tx_prod_bseq   = 0;
5680         sc->used_tx_bd     = 0;
5681         sc->max_tx_bd      = USABLE_TX_BD_ALLOC;
5682         DBRUN(sc->tx_hi_watermark = 0);
5683         DBRUN(sc->tx_full_count = 0);
5684
5685         /*
5686          * The NetXtreme II supports a linked-list structre called
5687          * a Buffer Descriptor Chain (or BD chain).  A BD chain
5688          * consists of a series of 1 or more chain pages, each of which
5689          * consists of a fixed number of BD entries.
5690          * The last BD entry on each page is a pointer to the next page
5691          * in the chain, and the last pointer in the BD chain
5692          * points back to the beginning of the chain.
5693          */
5694
5695         /* Set the TX next pointer chain entries. */
5696         for (i = 0; i < sc->tx_pages; i++) {
5697                 int j;
5698
5699                 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
5700
5701                 /* Check if we've reached the last page. */
5702                 if (i == (sc->tx_pages - 1))
5703                         j = 0;
5704                 else
5705                         j = i + 1;
5706
5707                 txbd->tx_bd_haddr_hi =
5708                     htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
5709                 txbd->tx_bd_haddr_lo =
5710                     htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
5711         }
5712
5713         bce_init_tx_context(sc);
5714
5715         DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC));
5716         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5717
5718         return(rc);
5719 }
5720
5721
5722 /****************************************************************************/
5723 /* Free memory and clear the TX data structures.                            */
5724 /*                                                                          */
5725 /* Returns:                                                                 */
5726 /*   Nothing.                                                               */
5727 /****************************************************************************/
5728 static void
5729 bce_free_tx_chain(struct bce_softc *sc)
5730 {
5731         int i;
5732
5733         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5734
5735         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
5736         for (i = 0; i < MAX_TX_BD_AVAIL; i++) {
5737                 if (sc->tx_mbuf_ptr[i] != NULL) {
5738                         if (sc->tx_mbuf_map[i] != NULL)
5739                                 bus_dmamap_sync(sc->tx_mbuf_tag,
5740                                     sc->tx_mbuf_map[i],
5741                                     BUS_DMASYNC_POSTWRITE);
5742                         m_freem(sc->tx_mbuf_ptr[i]);
5743                         sc->tx_mbuf_ptr[i] = NULL;
5744                         DBRUN(sc->debug_tx_mbuf_alloc--);
5745                 }
5746         }
5747
5748         /* Clear each TX chain page. */
5749         for (i = 0; i < sc->tx_pages; i++)
5750                 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
5751
5752         sc->used_tx_bd = 0;
5753
5754         /* Check if we lost any mbufs in the process. */
5755         DBRUNIF((sc->debug_tx_mbuf_alloc),
5756             BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs "
5757             "from tx chain!\n", __FILE__, __LINE__,
5758             sc->debug_tx_mbuf_alloc));
5759
5760         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5761 }
5762
5763
5764 /****************************************************************************/
5765 /* Initialize the RX context memory.                                        */
5766 /*                                                                          */
5767 /* Returns:                                                                 */
5768 /*   Nothing                                                                */
5769 /****************************************************************************/
5770 static void
5771 bce_init_rx_context(struct bce_softc *sc)
5772 {
5773         u32 val;
5774
5775         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5776
5777         /* Init the type, size, and BD cache levels for the RX context. */
5778         val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
5779             BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 |
5780             (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT);
5781
5782         /*
5783          * Set the level for generating pause frames
5784          * when the number of available rx_bd's gets
5785          * too low (the low watermark) and the level
5786          * when pause frames can be stopped (the high
5787          * watermark).
5788          */
5789         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5790                 u32 lo_water, hi_water;
5791
5792                 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) {
5793                         lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
5794                 } else {
5795                         lo_water = 0;
5796                 }
5797
5798                 if (lo_water >= USABLE_RX_BD_ALLOC) {
5799                         lo_water = 0;
5800                 }
5801
5802                 hi_water = USABLE_RX_BD_ALLOC / 4;
5803
5804                 if (hi_water <= lo_water) {
5805                         lo_water = 0;
5806                 }
5807
5808                 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
5809                 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
5810
5811                 if (hi_water > 0xf)
5812                         hi_water = 0xf;
5813                 else if (hi_water == 0)
5814                         lo_water = 0;
5815
5816                 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) |
5817                     (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
5818         }
5819
5820         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
5821
5822         /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
5823         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5824                 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
5825                 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
5826         }
5827
5828         /* Point the hardware to the first page in the chain. */
5829         val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
5830         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
5831         val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
5832         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
5833
5834         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5835 }
5836
5837
5838 /****************************************************************************/
5839 /* Allocate memory and initialize the RX data structures.                   */
5840 /*                                                                          */
5841 /* Returns:                                                                 */
5842 /*   0 for success, positive value for failure.                             */
5843 /****************************************************************************/
5844 static int
5845 bce_init_rx_chain(struct bce_softc *sc)
5846 {
5847         struct rx_bd *rxbd;
5848         int i, rc = 0;
5849
5850         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5851             BCE_VERBOSE_CTX);
5852
5853         /* Initialize the RX producer and consumer indices. */
5854         sc->rx_prod        = 0;
5855         sc->rx_cons        = 0;
5856         sc->rx_prod_bseq   = 0;
5857         sc->free_rx_bd     = USABLE_RX_BD_ALLOC;
5858         sc->max_rx_bd      = USABLE_RX_BD_ALLOC;
5859
5860         /* Initialize the RX next pointer chain entries. */
5861         for (i = 0; i < sc->rx_pages; i++) {
5862                 int j;
5863
5864                 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
5865
5866                 /* Check if we've reached the last page. */
5867                 if (i == (sc->rx_pages - 1))
5868                         j = 0;
5869                 else
5870                         j = i + 1;
5871
5872                 /* Setup the chain page pointers. */
5873                 rxbd->rx_bd_haddr_hi =
5874                     htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
5875                 rxbd->rx_bd_haddr_lo =
5876                     htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
5877         }
5878
5879         /* Fill up the RX chain. */
5880         bce_fill_rx_chain(sc);
5881
5882         DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC);
5883         DBRUN(sc->rx_empty_count = 0);
5884         for (i = 0; i < sc->rx_pages; i++) {
5885                 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i],
5886                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
5887         }
5888
5889         bce_init_rx_context(sc);
5890
5891         DBRUNMSG(BCE_EXTREME_RECV,
5892             bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC));
5893         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5894             BCE_VERBOSE_CTX);
5895
5896         /* ToDo: Are there possible failure modes here? */
5897
5898         return(rc);
5899 }
5900
5901
5902 /****************************************************************************/
5903 /* Add mbufs to the RX chain until its full or an mbuf allocation error     */
5904 /* occurs.                                                                  */
5905 /*                                                                          */
5906 /* Returns:                                                                 */
5907 /*   Nothing                                                                */
5908 /****************************************************************************/
5909 static void
5910 bce_fill_rx_chain(struct bce_softc *sc)
5911 {
5912         u16 prod, prod_idx;
5913         u32 prod_bseq;
5914
5915         DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5916             BCE_VERBOSE_CTX);
5917
5918         /* Get the RX chain producer indices. */
5919         prod      = sc->rx_prod;
5920         prod_bseq = sc->rx_prod_bseq;
5921
5922         /* Keep filling the RX chain until it's full. */
5923         while (sc->free_rx_bd > 0) {
5924                 prod_idx = RX_CHAIN_IDX(prod);
5925                 if (bce_get_rx_buf(sc, prod, prod_idx, &prod_bseq)) {
5926                         /* Bail out if we can't add an mbuf to the chain. */
5927                         break;
5928                 }
5929                 prod = NEXT_RX_BD(prod);
5930         }
5931
5932         /* Save the RX chain producer indices. */
5933         sc->rx_prod      = prod;
5934         sc->rx_prod_bseq = prod_bseq;
5935
5936         /* We should never end up pointing to a next page pointer. */
5937         DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
5938             BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n",
5939             __FUNCTION__, rx_prod));
5940
5941         /* Write the mailbox and tell the chip about the waiting rx_bd's. */
5942         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX, prod);
5943         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ, prod_bseq);
5944
5945         DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5946             BCE_VERBOSE_CTX);
5947 }
5948
5949
5950 /****************************************************************************/
5951 /* Free memory and clear the RX data structures.                            */
5952 /*                                                                          */
5953 /* Returns:                                                                 */
5954 /*   Nothing.                                                               */
5955 /****************************************************************************/
5956 static void
5957 bce_free_rx_chain(struct bce_softc *sc)
5958 {
5959         int i;
5960
5961         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5962
5963         /* Free any mbufs still in the RX mbuf chain. */
5964         for (i = 0; i < MAX_RX_BD_AVAIL; i++) {
5965                 if (sc->rx_mbuf_ptr[i] != NULL) {
5966                         if (sc->rx_mbuf_map[i] != NULL)
5967                                 bus_dmamap_sync(sc->rx_mbuf_tag,
5968                                     sc->rx_mbuf_map[i],
5969                                     BUS_DMASYNC_POSTREAD);
5970                         m_freem(sc->rx_mbuf_ptr[i]);
5971                         sc->rx_mbuf_ptr[i] = NULL;
5972                         DBRUN(sc->debug_rx_mbuf_alloc--);
5973                 }
5974         }
5975
5976         /* Clear each RX chain page. */
5977         for (i = 0; i < sc->rx_pages; i++)
5978                 if (sc->rx_bd_chain[i] != NULL)
5979                         bzero((char *)sc->rx_bd_chain[i],
5980                             BCE_RX_CHAIN_PAGE_SZ);
5981
5982         sc->free_rx_bd = sc->max_rx_bd;
5983
5984         /* Check if we lost any mbufs in the process. */
5985         DBRUNIF((sc->debug_rx_mbuf_alloc),
5986             BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n",
5987             __FUNCTION__, sc->debug_rx_mbuf_alloc));
5988
5989         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5990 }
5991
5992
5993 /****************************************************************************/
5994 /* Allocate memory and initialize the page data structures.                 */
5995 /* Assumes that bce_init_rx_chain() has not already been called.            */
5996 /*                                                                          */
5997 /* Returns:                                                                 */
5998 /*   0 for success, positive value for failure.                             */
5999 /****************************************************************************/
6000 static int
6001 bce_init_pg_chain(struct bce_softc *sc)
6002 {
6003         struct rx_bd *pgbd;
6004         int i, rc = 0;
6005         u32 val;
6006
6007         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
6008                 BCE_VERBOSE_CTX);
6009
6010         /* Initialize the page producer and consumer indices. */
6011         sc->pg_prod        = 0;
6012         sc->pg_cons        = 0;
6013         sc->free_pg_bd     = USABLE_PG_BD_ALLOC;
6014         sc->max_pg_bd      = USABLE_PG_BD_ALLOC;
6015         DBRUN(sc->pg_low_watermark = sc->max_pg_bd);
6016         DBRUN(sc->pg_empty_count = 0);
6017
6018         /* Initialize the page next pointer chain entries. */
6019         for (i = 0; i < sc->pg_pages; i++) {
6020                 int j;
6021
6022                 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE];
6023
6024                 /* Check if we've reached the last page. */
6025                 if (i == (sc->pg_pages - 1))
6026                         j = 0;
6027                 else
6028                         j = i + 1;
6029
6030                 /* Setup the chain page pointers. */
6031                 pgbd->rx_bd_haddr_hi =
6032                     htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j]));
6033                 pgbd->rx_bd_haddr_lo =
6034                     htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j]));
6035         }
6036
6037         /* Setup the MQ BIN mapping for host_pg_bidx. */
6038         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
6039                 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT);
6040
6041         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0);
6042
6043         /* Configure the rx_bd and page chain mbuf cluster size. */
6044         val = (sc->rx_bd_mbuf_data_len << 16) | MCLBYTES;
6045         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val);
6046
6047         /* Configure the context reserved for jumbo support. */
6048         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY,
6049                 BCE_L2CTX_RX_RBDC_JUMBO_KEY);
6050
6051         /* Point the hardware to the first page in the page chain. */
6052         val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]);
6053         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val);
6054         val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]);
6055         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val);
6056
6057         /* Fill up the page chain. */
6058         bce_fill_pg_chain(sc);
6059
6060         for (i = 0; i < sc->pg_pages; i++) {
6061                 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i],
6062                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
6063         }
6064
6065         DBRUNMSG(BCE_EXTREME_RECV,
6066             bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC));
6067         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
6068                 BCE_VERBOSE_CTX);
6069         return(rc);
6070 }
6071
6072
6073 /****************************************************************************/
6074 /* Add mbufs to the page chain until its full or an mbuf allocation error   */
6075 /* occurs.                                                                  */
6076 /*                                                                          */
6077 /* Returns:                                                                 */
6078 /*   Nothing                                                                */
6079 /****************************************************************************/
6080 static void
6081 bce_fill_pg_chain(struct bce_softc *sc)
6082 {
6083         u16 prod, prod_idx;
6084
6085         DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
6086             BCE_VERBOSE_CTX);
6087
6088         /* Get the page chain prodcuer index. */
6089         prod = sc->pg_prod;
6090
6091         /* Keep filling the page chain until it's full. */
6092         while (sc->free_pg_bd > 0) {
6093                 prod_idx = PG_CHAIN_IDX(prod);
6094                 if (bce_get_pg_buf(sc, prod, prod_idx)) {
6095                         /* Bail out if we can't add an mbuf to the chain. */
6096                         break;
6097                 }
6098                 prod = NEXT_PG_BD(prod);
6099         }
6100
6101         /* Save the page chain producer index. */
6102         sc->pg_prod = prod;
6103
6104         DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
6105             BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n",
6106             __FUNCTION__, pg_prod));
6107
6108         /*
6109          * Write the mailbox and tell the chip about
6110          * the new rx_bd's in the page chain.
6111          */
6112         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_PG_BDIDX,
6113             prod);
6114
6115         DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
6116             BCE_VERBOSE_CTX);
6117 }
6118
6119
6120 /****************************************************************************/
6121 /* Free memory and clear the RX data structures.                            */
6122 /*                                                                          */
6123 /* Returns:                                                                 */
6124 /*   Nothing.                                                               */
6125 /****************************************************************************/
6126 static void
6127 bce_free_pg_chain(struct bce_softc *sc)
6128 {
6129         int i;
6130
6131         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
6132
6133         /* Free any mbufs still in the mbuf page chain. */
6134         for (i = 0; i < MAX_PG_BD_AVAIL; i++) {
6135                 if (sc->pg_mbuf_ptr[i] != NULL) {
6136                         if (sc->pg_mbuf_map[i] != NULL)
6137                                 bus_dmamap_sync(sc->pg_mbuf_tag,
6138                                     sc->pg_mbuf_map[i],
6139                                     BUS_DMASYNC_POSTREAD);
6140                         m_freem(sc->pg_mbuf_ptr[i]);
6141                         sc->pg_mbuf_ptr[i] = NULL;
6142                         DBRUN(sc->debug_pg_mbuf_alloc--);
6143                 }
6144         }
6145
6146         /* Clear each page chain pages. */
6147         for (i = 0; i < sc->pg_pages; i++)
6148                 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ);
6149
6150         sc->free_pg_bd = sc->max_pg_bd;
6151
6152         /* Check if we lost any mbufs in the process. */
6153         DBRUNIF((sc->debug_pg_mbuf_alloc),
6154             BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n",
6155             __FUNCTION__, sc->debug_pg_mbuf_alloc));
6156
6157         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
6158 }
6159
6160
6161 static u32
6162 bce_get_rphy_link(struct bce_softc *sc)
6163 {
6164         u32 advertise, link;
6165         int fdpx;
6166
6167         advertise = 0;
6168         fdpx = 0;
6169         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0)
6170                 link = bce_shmem_rd(sc, BCE_RPHY_SERDES_LINK);
6171         else
6172                 link = bce_shmem_rd(sc, BCE_RPHY_COPPER_LINK);
6173         if (link & BCE_NETLINK_ANEG_ENB)
6174                 advertise |= BCE_NETLINK_ANEG_ENB;
6175         if (link & BCE_NETLINK_SPEED_10HALF)
6176                 advertise |= BCE_NETLINK_SPEED_10HALF;
6177         if (link & BCE_NETLINK_SPEED_10FULL) {
6178                 advertise |= BCE_NETLINK_SPEED_10FULL;
6179                 fdpx++;
6180         }
6181         if (link & BCE_NETLINK_SPEED_100HALF)
6182                 advertise |= BCE_NETLINK_SPEED_100HALF;
6183         if (link & BCE_NETLINK_SPEED_100FULL) {
6184                 advertise |= BCE_NETLINK_SPEED_100FULL;
6185                 fdpx++;
6186         }
6187         if (link & BCE_NETLINK_SPEED_1000HALF)
6188                 advertise |= BCE_NETLINK_SPEED_1000HALF;
6189         if (link & BCE_NETLINK_SPEED_1000FULL) {
6190                 advertise |= BCE_NETLINK_SPEED_1000FULL;
6191                 fdpx++;
6192         }
6193         if (link & BCE_NETLINK_SPEED_2500HALF)
6194                 advertise |= BCE_NETLINK_SPEED_2500HALF;
6195         if (link & BCE_NETLINK_SPEED_2500FULL) {
6196                 advertise |= BCE_NETLINK_SPEED_2500FULL;
6197                 fdpx++;
6198         }
6199         if (fdpx)
6200                 advertise |= BCE_NETLINK_FC_PAUSE_SYM |
6201                     BCE_NETLINK_FC_PAUSE_ASYM;
6202         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6203                 advertise |= BCE_NETLINK_PHY_APP_REMOTE |
6204                     BCE_NETLINK_ETH_AT_WIRESPEED;
6205
6206         return (advertise);
6207 }
6208
6209
6210 /****************************************************************************/
6211 /* Set media options.                                                       */
6212 /*                                                                          */
6213 /* Returns:                                                                 */
6214 /*   0 for success, positive value for failure.                             */
6215 /****************************************************************************/
6216 static int
6217 bce_ifmedia_upd(struct ifnet *ifp)
6218 {
6219         struct bce_softc *sc = ifp->if_softc;
6220         int error;
6221
6222         DBENTER(BCE_VERBOSE);
6223
6224         BCE_LOCK(sc);
6225         error = bce_ifmedia_upd_locked(ifp);
6226         BCE_UNLOCK(sc);
6227
6228         DBEXIT(BCE_VERBOSE);
6229         return (error);
6230 }
6231
6232
6233 /****************************************************************************/
6234 /* Set media options.                                                       */
6235 /*                                                                          */
6236 /* Returns:                                                                 */
6237 /*   Nothing.                                                               */
6238 /****************************************************************************/
6239 static int
6240 bce_ifmedia_upd_locked(struct ifnet *ifp)
6241 {
6242         struct bce_softc *sc = ifp->if_softc;
6243         struct mii_data *mii;
6244         struct mii_softc *miisc;
6245         struct ifmedia *ifm;
6246         u32 link;
6247         int error, fdx;
6248
6249         DBENTER(BCE_VERBOSE_PHY);
6250
6251         error = 0;
6252         BCE_LOCK_ASSERT(sc);
6253
6254         sc->bce_link_up = FALSE;
6255         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6256                 ifm = &sc->bce_ifmedia;
6257                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
6258                         return (EINVAL);
6259                 link = 0;
6260                 fdx = IFM_OPTIONS(ifm->ifm_media) & IFM_FDX;
6261                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
6262                 case IFM_AUTO:
6263                         /*
6264                          * Check advertised link of remote PHY by reading
6265                          * BCE_RPHY_SERDES_LINK or BCE_RPHY_COPPER_LINK.
6266                          * Always use the same link type of remote PHY.
6267                          */
6268                         link = bce_get_rphy_link(sc);
6269                         break;
6270                 case IFM_2500_SX:
6271                         if ((sc->bce_phy_flags &
6272                             (BCE_PHY_REMOTE_PORT_FIBER_FLAG |
6273                             BCE_PHY_2_5G_CAPABLE_FLAG)) == 0)
6274                                 return (EINVAL);
6275                         /*
6276                          * XXX
6277                          * Have to enable forced 2.5Gbps configuration.
6278                          */
6279                         if (fdx != 0)
6280                                 link |= BCE_NETLINK_SPEED_2500FULL;
6281                         else
6282                                 link |= BCE_NETLINK_SPEED_2500HALF;
6283                         break;
6284                 case IFM_1000_SX:
6285                         if ((sc->bce_phy_flags &
6286                             BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6287                                 return (EINVAL);
6288                         /*
6289                          * XXX
6290                          * Have to disable 2.5Gbps configuration.
6291                          */
6292                         if (fdx != 0)
6293                                 link = BCE_NETLINK_SPEED_1000FULL;
6294                         else
6295                                 link = BCE_NETLINK_SPEED_1000HALF;
6296                         break;
6297                 case IFM_1000_T:
6298                         if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6299                                 return (EINVAL);
6300                         if (fdx != 0)
6301                                 link = BCE_NETLINK_SPEED_1000FULL;
6302                         else
6303                                 link = BCE_NETLINK_SPEED_1000HALF;
6304                         break;
6305                 case IFM_100_TX:
6306                         if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6307                                 return (EINVAL);
6308                         if (fdx != 0)
6309                                 link = BCE_NETLINK_SPEED_100FULL;
6310                         else
6311                                 link = BCE_NETLINK_SPEED_100HALF;
6312                         break;
6313                 case IFM_10_T:
6314                         if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6315                                 return (EINVAL);
6316                         if (fdx != 0)
6317                                 link = BCE_NETLINK_SPEED_10FULL;
6318                         else
6319                                 link = BCE_NETLINK_SPEED_10HALF;
6320                         break;
6321                 default:
6322                         return (EINVAL);
6323                 }
6324                 if (IFM_SUBTYPE(ifm->ifm_media) != IFM_AUTO) {
6325                         /*
6326                          * XXX
6327                          * Advertise pause capability for full-duplex media.
6328                          */
6329                         if (fdx != 0)
6330                                 link |= BCE_NETLINK_FC_PAUSE_SYM |
6331                                     BCE_NETLINK_FC_PAUSE_ASYM;
6332                         if ((sc->bce_phy_flags &
6333                             BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6334                                 link |= BCE_NETLINK_PHY_APP_REMOTE |
6335                                     BCE_NETLINK_ETH_AT_WIRESPEED;
6336                 }
6337
6338                 bce_shmem_wr(sc, BCE_MB_ARGS_0, link);
6339                 error = bce_fw_sync(sc, BCE_DRV_MSG_CODE_CMD_SET_LINK);
6340         } else {
6341                 mii = device_get_softc(sc->bce_miibus);
6342
6343                 /* Make sure the MII bus has been enumerated. */
6344                 if (mii) {
6345                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
6346                                 PHY_RESET(miisc);
6347                         error = mii_mediachg(mii);
6348                 }
6349         }
6350
6351         DBEXIT(BCE_VERBOSE_PHY);
6352         return (error);
6353 }
6354
6355
6356 static void
6357 bce_ifmedia_sts_rphy(struct bce_softc *sc, struct ifmediareq *ifmr)
6358 {
6359         struct ifnet *ifp;
6360         u32 link;
6361
6362         ifp = sc->bce_ifp;
6363         BCE_LOCK_ASSERT(sc);
6364
6365         ifmr->ifm_status = IFM_AVALID;
6366         ifmr->ifm_active = IFM_ETHER;
6367         link = bce_shmem_rd(sc, BCE_LINK_STATUS);
6368         /* XXX Handle heart beat status? */
6369         if ((link & BCE_LINK_STATUS_LINK_UP) != 0)
6370                 ifmr->ifm_status |= IFM_ACTIVE;
6371         else {
6372                 ifmr->ifm_active |= IFM_NONE;
6373                 ifp->if_baudrate = 0;
6374                 return;
6375         }
6376         switch (link & BCE_LINK_STATUS_SPEED_MASK) {
6377         case BCE_LINK_STATUS_10HALF:
6378                 ifmr->ifm_active |= IFM_10_T | IFM_HDX;
6379                 ifp->if_baudrate = IF_Mbps(10UL);
6380                 break;
6381         case BCE_LINK_STATUS_10FULL:
6382                 ifmr->ifm_active |= IFM_10_T | IFM_FDX;
6383                 ifp->if_baudrate = IF_Mbps(10UL);
6384                 break;
6385         case BCE_LINK_STATUS_100HALF:
6386                 ifmr->ifm_active |= IFM_100_TX | IFM_HDX;
6387                 ifp->if_baudrate = IF_Mbps(100UL);
6388                 break;
6389         case BCE_LINK_STATUS_100FULL:
6390                 ifmr->ifm_active |= IFM_100_TX | IFM_FDX;
6391                 ifp->if_baudrate = IF_Mbps(100UL);
6392                 break;
6393         case BCE_LINK_STATUS_1000HALF:
6394                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6395                         ifmr->ifm_active |= IFM_1000_T | IFM_HDX;
6396                 else
6397                         ifmr->ifm_active |= IFM_1000_SX | IFM_HDX;
6398                 ifp->if_baudrate = IF_Mbps(1000UL);
6399                 break;
6400         case BCE_LINK_STATUS_1000FULL:
6401                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6402                         ifmr->ifm_active |= IFM_1000_T | IFM_FDX;
6403                 else
6404                         ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
6405                 ifp->if_baudrate = IF_Mbps(1000UL);
6406                 break;
6407         case BCE_LINK_STATUS_2500HALF:
6408                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6409                         ifmr->ifm_active |= IFM_NONE;
6410                         return;
6411                 } else
6412                         ifmr->ifm_active |= IFM_2500_SX | IFM_HDX;
6413                 ifp->if_baudrate = IF_Mbps(2500UL);
6414                 break;
6415         case BCE_LINK_STATUS_2500FULL:
6416                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6417                         ifmr->ifm_active |= IFM_NONE;
6418                         return;
6419                 } else
6420                         ifmr->ifm_active |= IFM_2500_SX | IFM_FDX;
6421                 ifp->if_baudrate = IF_Mbps(2500UL);
6422                 break;
6423         default:
6424                 ifmr->ifm_active |= IFM_NONE;
6425                 return;
6426         }
6427
6428         if ((link & BCE_LINK_STATUS_RX_FC_ENABLED) != 0)
6429                 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
6430         if ((link & BCE_LINK_STATUS_TX_FC_ENABLED) != 0)
6431                 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
6432 }
6433
6434
6435 /****************************************************************************/
6436 /* Reports current media status.                                            */
6437 /*                                                                          */
6438 /* Returns:                                                                 */
6439 /*   Nothing.                                                               */
6440 /****************************************************************************/
6441 static void
6442 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
6443 {
6444         struct bce_softc *sc = ifp->if_softc;
6445         struct mii_data *mii;
6446
6447         DBENTER(BCE_VERBOSE_PHY);
6448
6449         BCE_LOCK(sc);
6450
6451         if ((ifp->if_flags & IFF_UP) == 0) {
6452                 BCE_UNLOCK(sc);
6453                 return;
6454         }
6455
6456         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
6457                 bce_ifmedia_sts_rphy(sc, ifmr);
6458         else {
6459                 mii = device_get_softc(sc->bce_miibus);
6460                 mii_pollstat(mii);
6461                 ifmr->ifm_active = mii->mii_media_active;
6462                 ifmr->ifm_status = mii->mii_media_status;
6463         }
6464
6465         BCE_UNLOCK(sc);
6466
6467         DBEXIT(BCE_VERBOSE_PHY);
6468 }
6469
6470
6471 /****************************************************************************/
6472 /* Handles PHY generated interrupt events.                                  */
6473 /*                                                                          */
6474 /* Returns:                                                                 */
6475 /*   Nothing.                                                               */
6476 /****************************************************************************/
6477 static void
6478 bce_phy_intr(struct bce_softc *sc)
6479 {
6480         u32 new_link_state, old_link_state;
6481
6482         DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
6483
6484         DBRUN(sc->phy_interrupts++);
6485
6486         new_link_state = sc->status_block->status_attn_bits &
6487             STATUS_ATTN_BITS_LINK_STATE;
6488         old_link_state = sc->status_block->status_attn_bits_ack &
6489             STATUS_ATTN_BITS_LINK_STATE;
6490
6491         /* Handle any changes if the link state has changed. */
6492         if (new_link_state != old_link_state) {
6493
6494                 /* Update the status_attn_bits_ack field. */
6495                 if (new_link_state) {
6496                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
6497                             STATUS_ATTN_BITS_LINK_STATE);
6498                         DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n",
6499                             __FUNCTION__);
6500                 } else {
6501                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
6502                             STATUS_ATTN_BITS_LINK_STATE);
6503                         DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n",
6504                             __FUNCTION__);
6505                 }
6506
6507                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6508                         if (new_link_state) {
6509                                 if (bootverbose)
6510                                         if_printf(sc->bce_ifp, "link UP\n");
6511                                 if_link_state_change(sc->bce_ifp,
6512                                     LINK_STATE_UP);
6513                         } else {
6514                                 if (bootverbose)
6515                                         if_printf(sc->bce_ifp, "link DOWN\n");
6516                                 if_link_state_change(sc->bce_ifp,
6517                                     LINK_STATE_DOWN);
6518                         }
6519                 }
6520                 /*
6521                  * Assume link is down and allow
6522                  * tick routine to update the state
6523                  * based on the actual media state.
6524                  */
6525                 sc->bce_link_up = FALSE;
6526                 callout_stop(&sc->bce_tick_callout);
6527                 bce_tick(sc);
6528         }
6529
6530         /* Acknowledge the link change interrupt. */
6531         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
6532
6533         DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
6534 }
6535
6536
6537 /****************************************************************************/
6538 /* Reads the receive consumer value from the status block (skipping over    */
6539 /* chain page pointer if necessary).                                        */
6540 /*                                                                          */
6541 /* Returns:                                                                 */
6542 /*   hw_cons                                                                */
6543 /****************************************************************************/
6544 static inline u16
6545 bce_get_hw_rx_cons(struct bce_softc *sc)
6546 {
6547         u16 hw_cons;
6548
6549         rmb();
6550         hw_cons = sc->status_block->status_rx_quick_consumer_index0;
6551         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
6552                 hw_cons++;
6553
6554         return hw_cons;
6555 }
6556
6557 /****************************************************************************/
6558 /* Handles received frame interrupt events.                                 */
6559 /*                                                                          */
6560 /* Returns:                                                                 */
6561 /*   Nothing.                                                               */
6562 /****************************************************************************/
6563 static void
6564 bce_rx_intr(struct bce_softc *sc)
6565 {
6566         struct ifnet *ifp = sc->bce_ifp;
6567         struct l2_fhdr *l2fhdr;
6568         struct ether_vlan_header *vh;
6569         unsigned int pkt_len;
6570         u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons;
6571         u32 status;
6572         unsigned int rem_len;
6573         u16 sw_pg_cons, sw_pg_cons_idx;
6574
6575         DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6576         DBRUN(sc->interrupts_rx++);
6577         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, "
6578             "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6579             __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6580
6581         /* Prepare the RX chain pages to be accessed by the host CPU. */
6582         for (int i = 0; i < sc->rx_pages; i++)
6583                 bus_dmamap_sync(sc->rx_bd_chain_tag,
6584                     sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
6585
6586         /* Prepare the page chain pages to be accessed by the host CPU. */
6587         if (bce_hdr_split == TRUE) {
6588                 for (int i = 0; i < sc->pg_pages; i++)
6589                         bus_dmamap_sync(sc->pg_bd_chain_tag,
6590                             sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
6591         }
6592
6593         /* Get the hardware's view of the RX consumer index. */
6594         hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6595
6596         /* Get working copies of the driver's view of the consumer indices. */
6597         sw_rx_cons = sc->rx_cons;
6598         sw_pg_cons = sc->pg_cons;
6599
6600         /* Update some debug statistics counters */
6601         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
6602             sc->rx_low_watermark = sc->free_rx_bd);
6603         DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
6604             sc->rx_empty_count++);
6605
6606         /* Scan through the receive chain as long as there is work to do */
6607         /* ToDo: Consider setting a limit on the number of packets processed. */
6608         rmb();
6609         while (sw_rx_cons != hw_rx_cons) {
6610                 struct mbuf *m0;
6611
6612                 /* Convert the producer/consumer indices to an actual rx_bd index. */
6613                 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons);
6614
6615                 /* Unmap the mbuf from DMA space. */
6616                 bus_dmamap_sync(sc->rx_mbuf_tag,
6617                     sc->rx_mbuf_map[sw_rx_cons_idx],
6618                     BUS_DMASYNC_POSTREAD);
6619                 bus_dmamap_unload(sc->rx_mbuf_tag,
6620                     sc->rx_mbuf_map[sw_rx_cons_idx]);
6621
6622                 /* Remove the mbuf from the RX chain. */
6623                 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx];
6624                 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL;
6625                 DBRUN(sc->debug_rx_mbuf_alloc--);
6626                 sc->free_rx_bd++;
6627
6628                 /*
6629                  * Frames received on the NetXteme II are prepended
6630                  * with an l2_fhdr structure which provides status
6631                  * information about the received frame (including
6632                  * VLAN tags and checksum info).  The frames are
6633                  * also automatically adjusted to word align the IP
6634                  * header (i.e. two null bytes are inserted before
6635                  * the Ethernet header).  As a result the data
6636                  * DMA'd by the controller into the mbuf looks
6637                  * like this:
6638                  *
6639                  * +---------+-----+---------------------+-----+
6640                  * | l2_fhdr | pad | packet data         | FCS |
6641                  * +---------+-----+---------------------+-----+
6642                  *
6643                  * The l2_fhdr needs to be checked and skipped and
6644                  * the FCS needs to be stripped before sending the
6645                  * packet up the stack.
6646                  */
6647                 l2fhdr  = mtod(m0, struct l2_fhdr *);
6648
6649                 /* Get the packet data + FCS length and the status. */
6650                 pkt_len = l2fhdr->l2_fhdr_pkt_len;
6651                 status  = l2fhdr->l2_fhdr_status;
6652
6653                 /*
6654                  * Skip over the l2_fhdr and pad, resulting in the
6655                  * following data in the mbuf:
6656                  * +---------------------+-----+
6657                  * | packet data         | FCS |
6658                  * +---------------------+-----+
6659                  */
6660                 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN);
6661
6662                 /*
6663                  * When split header mode is used, an ethernet frame
6664                  * may be split across the receive chain and the
6665                  * page chain. If that occurs an mbuf cluster must be
6666                  * reassembled from the individual mbuf pieces.
6667                  */
6668                 if (bce_hdr_split == TRUE) {
6669                         /*
6670                          * Check whether the received frame fits in a single
6671                          * mbuf or not (i.e. packet data + FCS <=
6672                          * sc->rx_bd_mbuf_data_len bytes).
6673                          */
6674                         if (pkt_len > m0->m_len) {
6675                                 /*
6676                                  * The received frame is larger than a single mbuf.
6677                                  * If the frame was a TCP frame then only the TCP
6678                                  * header is placed in the mbuf, the remaining
6679                                  * payload (including FCS) is placed in the page
6680                                  * chain, the SPLIT flag is set, and the header
6681                                  * length is placed in the IP checksum field.
6682                                  * If the frame is not a TCP frame then the mbuf
6683                                  * is filled and the remaining bytes are placed
6684                                  * in the page chain.
6685                                  */
6686
6687                                 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large "
6688                                         "packet.\n", __FUNCTION__);
6689                                 DBRUN(sc->split_header_frames_rcvd++);
6690
6691                                 /*
6692                                  * When the page chain is enabled and the TCP
6693                                  * header has been split from the TCP payload,
6694                                  * the ip_xsum structure will reflect the length
6695                                  * of the TCP header, not the IP checksum.  Set
6696                                  * the packet length of the mbuf accordingly.
6697                                  */
6698                                 if (status & L2_FHDR_STATUS_SPLIT) {
6699                                         m0->m_len = l2fhdr->l2_fhdr_ip_xsum;
6700                                         DBRUN(sc->split_header_tcp_frames_rcvd++);
6701                                 }
6702
6703                                 rem_len = pkt_len - m0->m_len;
6704
6705                                 /* Pull mbufs off the page chain for any remaining data. */
6706                                 while (rem_len > 0) {
6707                                         struct mbuf *m_pg;
6708
6709                                         sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons);
6710
6711                                         /* Remove the mbuf from the page chain. */
6712                                         m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx];
6713                                         sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL;
6714                                         DBRUN(sc->debug_pg_mbuf_alloc--);
6715                                         sc->free_pg_bd++;
6716
6717                                         /* Unmap the page chain mbuf from DMA space. */
6718                                         bus_dmamap_sync(sc->pg_mbuf_tag,
6719                                                 sc->pg_mbuf_map[sw_pg_cons_idx],
6720                                                 BUS_DMASYNC_POSTREAD);
6721                                         bus_dmamap_unload(sc->pg_mbuf_tag,
6722                                                 sc->pg_mbuf_map[sw_pg_cons_idx]);
6723
6724                                         /* Adjust the mbuf length. */
6725                                         if (rem_len < m_pg->m_len) {
6726                                                 /* The mbuf chain is complete. */
6727                                                 m_pg->m_len = rem_len;
6728                                                 rem_len = 0;
6729                                         } else {
6730                                                 /* More packet data is waiting. */
6731                                                 rem_len -= m_pg->m_len;
6732                                         }
6733
6734                                         /* Concatenate the mbuf cluster to the mbuf. */
6735                                         m_cat(m0, m_pg);
6736
6737                                         sw_pg_cons = NEXT_PG_BD(sw_pg_cons);
6738                                 }
6739
6740                                 /* Set the total packet length. */
6741                                 m0->m_pkthdr.len = pkt_len;
6742
6743                         } else {
6744                                 /*
6745                                  * The received packet is small and fits in a
6746                                  * single mbuf (i.e. the l2_fhdr + pad + packet +
6747                                  * FCS <= MHLEN).  In other words, the packet is
6748                                  * 154 bytes or less in size.
6749                                  */
6750
6751                                 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small "
6752                                         "packet.\n", __FUNCTION__);
6753
6754                                 /* Set the total packet length. */
6755                                 m0->m_pkthdr.len = m0->m_len = pkt_len;
6756                         }
6757                 } else
6758                         /* Set the total packet length. */
6759                         m0->m_pkthdr.len = m0->m_len = pkt_len;
6760
6761                 /* Remove the trailing Ethernet FCS. */
6762                 m_adj(m0, -ETHER_CRC_LEN);
6763
6764                 /* Check that the resulting mbuf chain is valid. */
6765                 DBRUN(m_sanity(m0, FALSE));
6766                 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) |
6767                     (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)),
6768                     BCE_PRINTF("Invalid Ethernet frame size!\n");
6769                     m_print(m0, 128));
6770
6771                 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control),
6772                     sc->l2fhdr_error_sim_count++;
6773                     status = status | L2_FHDR_ERRORS_PHY_DECODE);
6774
6775                 /* Check the received frame for errors. */
6776                 if (status & (L2_FHDR_ERRORS_BAD_CRC |
6777                     L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT |
6778                     L2_FHDR_ERRORS_TOO_SHORT  | L2_FHDR_ERRORS_GIANT_FRAME)) {
6779
6780                         /* Log the error and release the mbuf. */
6781                         ifp->if_ierrors++;
6782                         sc->l2fhdr_error_count++;
6783
6784                         m_freem(m0);
6785                         m0 = NULL;
6786                         goto bce_rx_intr_next_rx;
6787                 }
6788
6789                 /* Send the packet to the appropriate interface. */
6790                 m0->m_pkthdr.rcvif = ifp;
6791
6792                 /* Assume no hardware checksum. */
6793                 m0->m_pkthdr.csum_flags = 0;
6794
6795                 /* Validate the checksum if offload enabled. */
6796                 if (ifp->if_capenable & IFCAP_RXCSUM) {
6797                         /* Check for an IP datagram. */
6798                         if (!(status & L2_FHDR_STATUS_SPLIT) &&
6799                             (status & L2_FHDR_STATUS_IP_DATAGRAM)) {
6800                                 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
6801                                 DBRUN(sc->csum_offload_ip++);
6802                                 /* Check if the IP checksum is valid. */
6803                                 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0)
6804                                         m0->m_pkthdr.csum_flags |=
6805                                             CSUM_IP_VALID;
6806                         }
6807
6808                         /* Check for a valid TCP/UDP frame. */
6809                         if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
6810                             L2_FHDR_STATUS_UDP_DATAGRAM)) {
6811
6812                                 /* Check for a good TCP/UDP checksum. */
6813                                 if ((status & (L2_FHDR_ERRORS_TCP_XSUM |
6814                                     L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
6815                                         DBRUN(sc->csum_offload_tcp_udp++);
6816                                         m0->m_pkthdr.csum_data =
6817                                             l2fhdr->l2_fhdr_tcp_udp_xsum;
6818                                         m0->m_pkthdr.csum_flags |=
6819                                             (CSUM_DATA_VALID
6820                                             | CSUM_PSEUDO_HDR);
6821                                 }
6822                         }
6823                 }
6824
6825                 /* Attach the VLAN tag. */
6826                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
6827                     !(sc->rx_mode & BCE_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
6828                         DBRUN(sc->vlan_tagged_frames_rcvd++);
6829                         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
6830                                 DBRUN(sc->vlan_tagged_frames_stripped++);
6831 #if __FreeBSD_version < 700000
6832                                 VLAN_INPUT_TAG(ifp, m0,
6833                                     l2fhdr->l2_fhdr_vlan_tag, continue);
6834 #else
6835                                 m0->m_pkthdr.ether_vtag =
6836                                     l2fhdr->l2_fhdr_vlan_tag;
6837                                 m0->m_flags |= M_VLANTAG;
6838 #endif
6839                         } else {
6840                                 /*
6841                                  * bce(4) controllers can't disable VLAN
6842                                  * tag stripping if management firmware
6843                                  * (ASF/IPMI/UMP) is running. So we always
6844                                  * strip VLAN tag and manually reconstruct
6845                                  * the VLAN frame by appending stripped
6846                                  * VLAN tag in driver if VLAN tag stripping
6847                                  * was disabled.
6848                                  *
6849                                  * TODO: LLC SNAP handling.
6850                                  */
6851                                 bcopy(mtod(m0, uint8_t *),
6852                                     mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN,
6853                                     ETHER_ADDR_LEN * 2);
6854                                 m0->m_data -= ETHER_VLAN_ENCAP_LEN;
6855                                 vh = mtod(m0, struct ether_vlan_header *);
6856                                 vh->evl_encap_proto = htons(ETHERTYPE_VLAN);
6857                                 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag);
6858                                 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN;
6859                                 m0->m_len += ETHER_VLAN_ENCAP_LEN;
6860                         }
6861                 }
6862
6863                 /* Increment received packet statistics. */
6864                 ifp->if_ipackets++;
6865
6866 bce_rx_intr_next_rx:
6867                 sw_rx_cons = NEXT_RX_BD(sw_rx_cons);
6868
6869                 /* If we have a packet, pass it up the stack */
6870                 if (m0) {
6871                         /* Make sure we don't lose our place when we release the lock. */
6872                         sc->rx_cons = sw_rx_cons;
6873                         sc->pg_cons = sw_pg_cons;
6874
6875                         BCE_UNLOCK(sc);
6876                         (*ifp->if_input)(ifp, m0);
6877                         BCE_LOCK(sc);
6878
6879                         /* Recover our place. */
6880                         sw_rx_cons = sc->rx_cons;
6881                         sw_pg_cons = sc->pg_cons;
6882                 }
6883
6884                 /* Refresh hw_cons to see if there's new work */
6885                 if (sw_rx_cons == hw_rx_cons)
6886                         hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6887         }
6888
6889         /* No new packets.  Refill the page chain. */
6890         if (bce_hdr_split == TRUE) {
6891                 sc->pg_cons = sw_pg_cons;
6892                 bce_fill_pg_chain(sc);
6893         }
6894
6895         /* No new packets.  Refill the RX chain. */
6896         sc->rx_cons = sw_rx_cons;
6897         bce_fill_rx_chain(sc);
6898
6899         /* Prepare the page chain pages to be accessed by the NIC. */
6900         for (int i = 0; i < sc->rx_pages; i++)
6901                 bus_dmamap_sync(sc->rx_bd_chain_tag,
6902                     sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6903
6904         if (bce_hdr_split == TRUE) {
6905                 for (int i = 0; i < sc->pg_pages; i++)
6906                         bus_dmamap_sync(sc->pg_bd_chain_tag,
6907                             sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6908         }
6909
6910         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, "
6911             "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6912             __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6913         DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6914 }
6915
6916
6917 /****************************************************************************/
6918 /* Reads the transmit consumer value from the status block (skipping over   */
6919 /* chain page pointer if necessary).                                        */
6920 /*                                                                          */
6921 /* Returns:                                                                 */
6922 /*   hw_cons                                                                */
6923 /****************************************************************************/
6924 static inline u16
6925 bce_get_hw_tx_cons(struct bce_softc *sc)
6926 {
6927         u16 hw_cons;
6928
6929         mb();
6930         hw_cons = sc->status_block->status_tx_quick_consumer_index0;
6931         if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
6932                 hw_cons++;
6933
6934         return hw_cons;
6935 }
6936
6937
6938 /****************************************************************************/
6939 /* Handles transmit completion interrupt events.                            */
6940 /*                                                                          */
6941 /* Returns:                                                                 */
6942 /*   Nothing.                                                               */
6943 /****************************************************************************/
6944 static void
6945 bce_tx_intr(struct bce_softc *sc)
6946 {
6947         struct ifnet *ifp = sc->bce_ifp;
6948         u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
6949
6950         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
6951         DBRUN(sc->interrupts_tx++);
6952         DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, "
6953             "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
6954             __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
6955
6956         BCE_LOCK_ASSERT(sc);
6957
6958         /* Get the hardware's view of the TX consumer index. */
6959         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6960         sw_tx_cons = sc->tx_cons;
6961
6962         /* Prevent speculative reads of the status block. */
6963         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6964             BUS_SPACE_BARRIER_READ);
6965
6966         /* Cycle through any completed TX chain page entries. */
6967         while (sw_tx_cons != hw_tx_cons) {
6968 #ifdef BCE_DEBUG
6969                 struct tx_bd *txbd = NULL;
6970 #endif
6971                 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
6972
6973                 DBPRINT(sc, BCE_INFO_SEND,
6974                     "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
6975                     "sw_tx_chain_cons = 0x%04X\n",
6976                     __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
6977
6978                 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC),
6979                     BCE_PRINTF("%s(%d): TX chain consumer out of range! "
6980                     " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons,
6981                     (int) MAX_TX_BD_ALLOC);
6982                     bce_breakpoint(sc));
6983
6984                 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
6985                     [TX_IDX(sw_tx_chain_cons)]);
6986
6987                 DBRUNIF((txbd == NULL),
6988                     BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n",
6989                     __FILE__, __LINE__, sw_tx_chain_cons);
6990                     bce_breakpoint(sc));
6991
6992                 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__);
6993                     bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
6994
6995                 /*
6996                  * Free the associated mbuf. Remember
6997                  * that only the last tx_bd of a packet
6998                  * has an mbuf pointer and DMA map.
6999                  */
7000                 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
7001
7002                         /* Validate that this is the last tx_bd. */
7003                         DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
7004                             BCE_PRINTF("%s(%d): tx_bd END flag not set but "
7005                             "txmbuf == NULL!\n", __FILE__, __LINE__);
7006                             bce_breakpoint(sc));
7007
7008                         DBRUNMSG(BCE_INFO_SEND,
7009                             BCE_PRINTF("%s(): Unloading map/freeing mbuf "
7010                             "from tx_bd[0x%04X]\n", __FUNCTION__,
7011                             sw_tx_chain_cons));
7012
7013                         /* Unmap the mbuf. */
7014                         bus_dmamap_unload(sc->tx_mbuf_tag,
7015                             sc->tx_mbuf_map[sw_tx_chain_cons]);
7016
7017                         /* Free the mbuf. */
7018                         m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
7019                         sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
7020                         DBRUN(sc->debug_tx_mbuf_alloc--);
7021
7022                         ifp->if_opackets++;
7023                 }
7024
7025                 sc->used_tx_bd--;
7026                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
7027
7028                 /* Refresh hw_cons to see if there's new work. */
7029                 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
7030
7031                 /* Prevent speculative reads of the status block. */
7032                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
7033                     BUS_SPACE_BARRIER_READ);
7034         }
7035
7036         /* Clear the TX timeout timer. */
7037         sc->watchdog_timer = 0;
7038
7039         /* Clear the tx hardware queue full flag. */
7040         if (sc->used_tx_bd < sc->max_tx_bd) {
7041                 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE),
7042                     DBPRINT(sc, BCE_INFO_SEND,
7043                     "%s(): Open TX chain! %d/%d (used/total)\n",
7044                     __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd));
7045                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
7046         }
7047
7048         sc->tx_cons = sw_tx_cons;
7049
7050         DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, "
7051             "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
7052             __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
7053         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
7054 }
7055
7056
7057 /****************************************************************************/
7058 /* Disables interrupt generation.                                           */
7059 /*                                                                          */
7060 /* Returns:                                                                 */
7061 /*   Nothing.                                                               */
7062 /****************************************************************************/
7063 static void
7064 bce_disable_intr(struct bce_softc *sc)
7065 {
7066         DBENTER(BCE_VERBOSE_INTR);
7067
7068         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
7069         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
7070
7071         DBEXIT(BCE_VERBOSE_INTR);
7072 }
7073
7074
7075 /****************************************************************************/
7076 /* Enables interrupt generation.                                            */
7077 /*                                                                          */
7078 /* Returns:                                                                 */
7079 /*   Nothing.                                                               */
7080 /****************************************************************************/
7081 static void
7082 bce_enable_intr(struct bce_softc *sc, int coal_now)
7083 {
7084         DBENTER(BCE_VERBOSE_INTR);
7085
7086         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7087             BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
7088             BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
7089
7090         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7091             BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
7092
7093         /* Force an immediate interrupt (whether there is new data or not). */
7094         if (coal_now)
7095                 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
7096
7097         DBEXIT(BCE_VERBOSE_INTR);
7098 }
7099
7100
7101 /****************************************************************************/
7102 /* Handles controller initialization.                                       */
7103 /*                                                                          */
7104 /* Returns:                                                                 */
7105 /*   Nothing.                                                               */
7106 /****************************************************************************/
7107 static void
7108 bce_init_locked(struct bce_softc *sc)
7109 {
7110         struct ifnet *ifp;
7111         u32 ether_mtu = 0;
7112
7113         DBENTER(BCE_VERBOSE_RESET);
7114
7115         BCE_LOCK_ASSERT(sc);
7116
7117         ifp = sc->bce_ifp;
7118
7119         /* Check if the driver is still running and bail out if it is. */
7120         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
7121                 goto bce_init_locked_exit;
7122
7123         bce_stop(sc);
7124
7125         if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
7126                 BCE_PRINTF("%s(%d): Controller reset failed!\n",
7127                     __FILE__, __LINE__);
7128                 goto bce_init_locked_exit;
7129         }
7130
7131         if (bce_chipinit(sc)) {
7132                 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
7133                     __FILE__, __LINE__);
7134                 goto bce_init_locked_exit;
7135         }
7136
7137         if (bce_blockinit(sc)) {
7138                 BCE_PRINTF("%s(%d): Block initialization failed!\n",
7139                     __FILE__, __LINE__);
7140                 goto bce_init_locked_exit;
7141         }
7142
7143         /* Load our MAC address. */
7144         bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN);
7145         bce_set_mac_addr(sc);
7146
7147         if (bce_hdr_split == FALSE)
7148                 bce_get_rx_buffer_sizes(sc, ifp->if_mtu);
7149         /*
7150          * Calculate and program the hardware Ethernet MTU
7151          * size. Be generous on the receive if we have room
7152          * and allowed by the user.
7153          */
7154         if (bce_strict_rx_mtu == TRUE)
7155                 ether_mtu = ifp->if_mtu;
7156         else {
7157                 if (bce_hdr_split == TRUE) {
7158                         if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len + MCLBYTES)
7159                                 ether_mtu = sc->rx_bd_mbuf_data_len +
7160                                     MCLBYTES;
7161                         else
7162                                 ether_mtu = ifp->if_mtu;
7163                 } else {
7164                         if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len)
7165                                 ether_mtu = sc->rx_bd_mbuf_data_len;
7166                         else
7167                                 ether_mtu = ifp->if_mtu;
7168                 }
7169         }
7170
7171         ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
7172
7173         DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n",
7174             __FUNCTION__, ether_mtu);
7175
7176         /* Program the mtu, enabling jumbo frame support if necessary. */
7177         if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN))
7178                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
7179                     min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
7180                     BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
7181         else
7182                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
7183
7184         /* Program appropriate promiscuous/multicast filtering. */
7185         bce_set_rx_mode(sc);
7186
7187         if (bce_hdr_split == TRUE) {
7188                 /* Init page buffer descriptor chain. */
7189                 bce_init_pg_chain(sc);
7190         }
7191
7192         /* Init RX buffer descriptor chain. */
7193         bce_init_rx_chain(sc);
7194
7195         /* Init TX buffer descriptor chain. */
7196         bce_init_tx_chain(sc);
7197
7198         /* Enable host interrupts. */
7199         bce_enable_intr(sc, 1);
7200
7201         bce_ifmedia_upd_locked(ifp);
7202
7203         /* Let the OS know the driver is up and running. */
7204         ifp->if_drv_flags |= IFF_DRV_RUNNING;
7205         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
7206
7207         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
7208
7209 bce_init_locked_exit:
7210         DBEXIT(BCE_VERBOSE_RESET);
7211 }
7212
7213
7214 /****************************************************************************/
7215 /* Initialize the controller just enough so that any management firmware    */
7216 /* running on the device will continue to operate correctly.                */
7217 /*                                                                          */
7218 /* Returns:                                                                 */
7219 /*   Nothing.                                                               */
7220 /****************************************************************************/
7221 static void
7222 bce_mgmt_init_locked(struct bce_softc *sc)
7223 {
7224         struct ifnet *ifp;
7225
7226         DBENTER(BCE_VERBOSE_RESET);
7227
7228         BCE_LOCK_ASSERT(sc);
7229
7230         /* Bail out if management firmware is not running. */
7231         if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) {
7232                 DBPRINT(sc, BCE_VERBOSE_SPECIAL,
7233                     "No management firmware running...\n");
7234                 goto bce_mgmt_init_locked_exit;
7235         }
7236
7237         ifp = sc->bce_ifp;
7238
7239         /* Enable all critical blocks in the MAC. */
7240         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
7241         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
7242         DELAY(20);
7243
7244         bce_ifmedia_upd_locked(ifp);
7245
7246 bce_mgmt_init_locked_exit:
7247         DBEXIT(BCE_VERBOSE_RESET);
7248 }
7249
7250
7251 /****************************************************************************/
7252 /* Handles controller initialization when called from an unlocked routine.  */
7253 /*                                                                          */
7254 /* Returns:                                                                 */
7255 /*   Nothing.                                                               */
7256 /****************************************************************************/
7257 static void
7258 bce_init(void *xsc)
7259 {
7260         struct bce_softc *sc = xsc;
7261
7262         DBENTER(BCE_VERBOSE_RESET);
7263
7264         BCE_LOCK(sc);
7265         bce_init_locked(sc);
7266         BCE_UNLOCK(sc);
7267
7268         DBEXIT(BCE_VERBOSE_RESET);
7269 }
7270
7271
7272 /****************************************************************************/
7273 /* Modifies an mbuf for TSO on the hardware.                                */
7274 /*                                                                          */
7275 /* Returns:                                                                 */
7276 /*   Pointer to a modified mbuf.                                            */
7277 /****************************************************************************/
7278 static struct mbuf *
7279 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags)
7280 {
7281         struct mbuf *m;
7282         struct ether_header *eh;
7283         struct ip *ip;
7284         struct tcphdr *th;
7285         u16 etype;
7286         int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0;
7287
7288         DBRUN(sc->tso_frames_requested++);
7289
7290         /* Controller may modify mbuf chains. */
7291         if (M_WRITABLE(*m_head) == 0) {
7292                 m = m_dup(*m_head, M_NOWAIT);
7293                 m_freem(*m_head);
7294                 if (m == NULL) {
7295                         sc->mbuf_alloc_failed_count++;
7296                         *m_head = NULL;
7297                         return (NULL);
7298                 }
7299                 *m_head = m;
7300         }
7301
7302         /*
7303          * For TSO the controller needs two pieces of info,
7304          * the MSS and the IP+TCP options length.
7305          */
7306         m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip));
7307         if (m == NULL) {
7308                 *m_head = NULL;
7309                 return (NULL);
7310         }
7311         eh = mtod(m, struct ether_header *);
7312         etype = ntohs(eh->ether_type);
7313
7314         /* Check for supported TSO Ethernet types (only IPv4 for now) */
7315         switch (etype) {
7316         case ETHERTYPE_IP:
7317                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7318                 /* TSO only supported for TCP protocol. */
7319                 if (ip->ip_p != IPPROTO_TCP) {
7320                         BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n",
7321                             __FILE__, __LINE__);
7322                         m_freem(*m_head);
7323                         *m_head = NULL;
7324                         return (NULL);
7325                 }
7326
7327                 /* Get IP header length in bytes (min 20) */
7328                 ip_hlen = ip->ip_hl << 2;
7329                 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen +
7330                     sizeof(struct tcphdr));
7331                 if (m == NULL) {
7332                         *m_head = NULL;
7333                         return (NULL);
7334                 }
7335
7336                 /* Get the TCP header length in bytes (min 20) */
7337                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7338                 th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
7339                 tcp_hlen = (th->th_off << 2);
7340
7341                 /* Make sure all IP/TCP options live in the same buffer. */
7342                 m = m_pullup(*m_head,  sizeof(struct ether_header)+ ip_hlen +
7343                     tcp_hlen);
7344                 if (m == NULL) {
7345                         *m_head = NULL;
7346                         return (NULL);
7347                 }
7348
7349                 /* Clear IP header length and checksum, will be calc'd by h/w. */
7350                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7351                 ip_len = ip->ip_len;
7352                 ip->ip_len = 0;
7353                 ip->ip_sum = 0;
7354                 break;
7355         case ETHERTYPE_IPV6:
7356                 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n",
7357                     __FILE__, __LINE__);
7358                 m_freem(*m_head);
7359                 *m_head = NULL;
7360                 return (NULL);
7361                 /* NOT REACHED */
7362         default:
7363                 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n",
7364                     __FILE__, __LINE__);
7365                 m_freem(*m_head);
7366                 *m_head = NULL;
7367                 return (NULL);
7368         }
7369
7370         hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen;
7371
7372         DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, "
7373             "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n",
7374             __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen,
7375             tcp_hlen, ip_len);
7376
7377         /* Set the LSO flag in the TX BD */
7378         *flags |= TX_BD_FLAGS_SW_LSO;
7379
7380         /* Set the length of IP + TCP options (in 32 bit words) */
7381         *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) -
7382             sizeof(struct tcphdr)) >> 2) << 8);
7383
7384         DBRUN(sc->tso_frames_completed++);
7385         return (*m_head);
7386 }
7387
7388
7389 /****************************************************************************/
7390 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
7391 /* memory visible to the controller.                                        */
7392 /*                                                                          */
7393 /* Returns:                                                                 */
7394 /*   0 for success, positive value for failure.                             */
7395 /* Modified:                                                                */
7396 /*   m_head: May be set to NULL if MBUF is excessively fragmented.          */
7397 /****************************************************************************/
7398 static int
7399 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head)
7400 {
7401         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
7402         bus_dmamap_t map;
7403         struct tx_bd *txbd = NULL;
7404         struct mbuf *m0;
7405         u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0;
7406         u32 prod_bseq;
7407
7408 #ifdef BCE_DEBUG
7409         u16 debug_prod;
7410 #endif
7411
7412         int i, error, nsegs, rc = 0;
7413
7414         DBENTER(BCE_VERBOSE_SEND);
7415
7416         /* Make sure we have room in the TX chain. */
7417         if (sc->used_tx_bd >= sc->max_tx_bd)
7418                 goto bce_tx_encap_exit;
7419
7420         /* Transfer any checksum offload flags to the bd. */
7421         m0 = *m_head;
7422         if (m0->m_pkthdr.csum_flags) {
7423                 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
7424                         m0 = bce_tso_setup(sc, m_head, &flags);
7425                         if (m0 == NULL) {
7426                                 DBRUN(sc->tso_frames_failed++);
7427                                 goto bce_tx_encap_exit;
7428                         }
7429                         mss = htole16(m0->m_pkthdr.tso_segsz);
7430                 } else {
7431                         if (m0->m_pkthdr.csum_flags & CSUM_IP)
7432                                 flags |= TX_BD_FLAGS_IP_CKSUM;
7433                         if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
7434                                 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
7435                 }
7436         }
7437
7438         /* Transfer any VLAN tags to the bd. */
7439         if (m0->m_flags & M_VLANTAG) {
7440                 flags |= TX_BD_FLAGS_VLAN_TAG;
7441                 vlan_tag = m0->m_pkthdr.ether_vtag;
7442         }
7443
7444         /* Map the mbuf into DMAable memory. */
7445         prod = sc->tx_prod;
7446         chain_prod = TX_CHAIN_IDX(prod);
7447         map = sc->tx_mbuf_map[chain_prod];
7448
7449         /* Map the mbuf into our DMA address space. */
7450         error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
7451             segs, &nsegs, BUS_DMA_NOWAIT);
7452
7453         /* Check if the DMA mapping was successful */
7454         if (error == EFBIG) {
7455                 sc->mbuf_frag_count++;
7456
7457                 /* Try to defrag the mbuf. */
7458                 m0 = m_collapse(*m_head, M_NOWAIT, BCE_MAX_SEGMENTS);
7459                 if (m0 == NULL) {
7460                         /* Defrag was unsuccessful */
7461                         m_freem(*m_head);
7462                         *m_head = NULL;
7463                         sc->mbuf_alloc_failed_count++;
7464                         rc = ENOBUFS;
7465                         goto bce_tx_encap_exit;
7466                 }
7467
7468                 /* Defrag was successful, try mapping again */
7469                 *m_head = m0;
7470                 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag,
7471                     map, m0, segs, &nsegs, BUS_DMA_NOWAIT);
7472
7473                 /* Still getting an error after a defrag. */
7474                 if (error == ENOMEM) {
7475                         /* Insufficient DMA buffers available. */
7476                         sc->dma_map_addr_tx_failed_count++;
7477                         rc = error;
7478                         goto bce_tx_encap_exit;
7479                 } else if (error != 0) {
7480                         /* Release it and return an error. */
7481                         BCE_PRINTF("%s(%d): Unknown error mapping mbuf into "
7482                             "TX chain!\n", __FILE__, __LINE__);
7483                         m_freem(m0);
7484                         *m_head = NULL;
7485                         sc->dma_map_addr_tx_failed_count++;
7486                         rc = ENOBUFS;
7487                         goto bce_tx_encap_exit;
7488                 }
7489         } else if (error == ENOMEM) {
7490                 /* Insufficient DMA buffers available. */
7491                 sc->dma_map_addr_tx_failed_count++;
7492                 rc = error;
7493                 goto bce_tx_encap_exit;
7494         } else if (error != 0) {
7495                 m_freem(m0);
7496                 *m_head = NULL;
7497                 sc->dma_map_addr_tx_failed_count++;
7498                 rc = error;
7499                 goto bce_tx_encap_exit;
7500         }
7501
7502         /* Make sure there's room in the chain */
7503         if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) {
7504                 bus_dmamap_unload(sc->tx_mbuf_tag, map);
7505                 rc = ENOBUFS;
7506                 goto bce_tx_encap_exit;
7507         }
7508
7509         /* prod points to an empty tx_bd at this point. */
7510         prod_bseq  = sc->tx_prod_bseq;
7511
7512 #ifdef BCE_DEBUG
7513         debug_prod = chain_prod;
7514 #endif
7515
7516         DBPRINT(sc, BCE_INFO_SEND,
7517             "%s(start): prod = 0x%04X, chain_prod = 0x%04X, "
7518             "prod_bseq = 0x%08X\n",
7519             __FUNCTION__, prod, chain_prod, prod_bseq);
7520
7521         /*
7522          * Cycle through each mbuf segment that makes up
7523          * the outgoing frame, gathering the mapping info
7524          * for that segment and creating a tx_bd for
7525          * the mbuf.
7526          */
7527         for (i = 0; i < nsegs ; i++) {
7528
7529                 chain_prod = TX_CHAIN_IDX(prod);
7530                 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)]
7531                     [TX_IDX(chain_prod)];
7532
7533                 txbd->tx_bd_haddr_lo =
7534                     htole32(BCE_ADDR_LO(segs[i].ds_addr));
7535                 txbd->tx_bd_haddr_hi =
7536                     htole32(BCE_ADDR_HI(segs[i].ds_addr));
7537                 txbd->tx_bd_mss_nbytes = htole32(mss << 16) |
7538                     htole16(segs[i].ds_len);
7539                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
7540                 txbd->tx_bd_flags = htole16(flags);
7541                 prod_bseq += segs[i].ds_len;
7542                 if (i == 0)
7543                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
7544                 prod = NEXT_TX_BD(prod);
7545         }
7546
7547         /* Set the END flag on the last TX buffer descriptor. */
7548         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
7549
7550         DBRUNMSG(BCE_EXTREME_SEND,
7551             bce_dump_tx_chain(sc, debug_prod, nsegs));
7552
7553         /*
7554          * Ensure that the mbuf pointer for this transmission
7555          * is placed at the array index of the last
7556          * descriptor in this chain.  This is done
7557          * because a single map is used for all
7558          * segments of the mbuf and we don't want to
7559          * unload the map before all of the segments
7560          * have been freed.
7561          */
7562         sc->tx_mbuf_ptr[chain_prod] = m0;
7563         sc->used_tx_bd += nsegs;
7564
7565         /* Update some debug statistic counters */
7566         DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
7567             sc->tx_hi_watermark = sc->used_tx_bd);
7568         DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
7569         DBRUNIF(sc->debug_tx_mbuf_alloc++);
7570
7571         DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1));
7572
7573         /* prod points to the next free tx_bd at this point. */
7574         sc->tx_prod = prod;
7575         sc->tx_prod_bseq = prod_bseq;
7576
7577         /* Tell the chip about the waiting TX frames. */
7578         REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) +
7579             BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod);
7580         REG_WR(sc, MB_GET_CID_ADDR(TX_CID) +
7581             BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq);
7582
7583 bce_tx_encap_exit:
7584         DBEXIT(BCE_VERBOSE_SEND);
7585         return(rc);
7586 }
7587
7588
7589 /****************************************************************************/
7590 /* Main transmit routine when called from another routine with a lock.      */
7591 /*                                                                          */
7592 /* Returns:                                                                 */
7593 /*   Nothing.                                                               */
7594 /****************************************************************************/
7595 static void
7596 bce_start_locked(struct ifnet *ifp)
7597 {
7598         struct bce_softc *sc = ifp->if_softc;
7599         struct mbuf *m_head = NULL;
7600         int count = 0;
7601         u16 tx_prod, tx_chain_prod;
7602
7603         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7604
7605         BCE_LOCK_ASSERT(sc);
7606
7607         /* prod points to the next free tx_bd. */
7608         tx_prod = sc->tx_prod;
7609         tx_chain_prod = TX_CHAIN_IDX(tx_prod);
7610
7611         DBPRINT(sc, BCE_INFO_SEND,
7612             "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
7613             "tx_prod_bseq = 0x%08X\n",
7614             __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq);
7615
7616         /* If there's no link or the transmit queue is empty then just exit. */
7617         if (sc->bce_link_up == FALSE) {
7618                 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n",
7619                     __FUNCTION__);
7620                 goto bce_start_locked_exit;
7621         }
7622
7623         if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
7624                 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n",
7625                     __FUNCTION__);
7626                 goto bce_start_locked_exit;
7627         }
7628
7629         /*
7630          * Keep adding entries while there is space in the ring.
7631          */
7632         while (sc->used_tx_bd < sc->max_tx_bd) {
7633
7634                 /* Check for any frames to send. */
7635                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
7636
7637                 /* Stop when the transmit queue is empty. */
7638                 if (m_head == NULL)
7639                         break;
7640
7641                 /*
7642                  * Pack the data into the transmit ring. If we
7643                  * don't have room, place the mbuf back at the
7644                  * head of the queue and set the OACTIVE flag
7645                  * to wait for the NIC to drain the chain.
7646                  */
7647                 if (bce_tx_encap(sc, &m_head)) {
7648                         if (m_head != NULL)
7649                                 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
7650                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
7651                         DBPRINT(sc, BCE_INFO_SEND,
7652                             "TX chain is closed for business! Total "
7653                             "tx_bd used = %d\n", sc->used_tx_bd);
7654                         break;
7655                 }
7656
7657                 count++;
7658
7659                 /* Send a copy of the frame to any BPF listeners. */
7660                 ETHER_BPF_MTAP(ifp, m_head);
7661         }
7662
7663         /* Exit if no packets were dequeued. */
7664         if (count == 0) {
7665                 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were "
7666                     "dequeued\n", __FUNCTION__);
7667                 goto bce_start_locked_exit;
7668         }
7669
7670         DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into "
7671             "send queue.\n", __FUNCTION__, count);
7672
7673         /* Set the tx timeout. */
7674         sc->watchdog_timer = BCE_TX_TIMEOUT;
7675
7676         DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID));
7677         DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc));
7678
7679 bce_start_locked_exit:
7680         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7681 }
7682
7683
7684 /****************************************************************************/
7685 /* Main transmit routine when called from another routine without a lock.   */
7686 /*                                                                          */
7687 /* Returns:                                                                 */
7688 /*   Nothing.                                                               */
7689 /****************************************************************************/
7690 static void
7691 bce_start(struct ifnet *ifp)
7692 {
7693         struct bce_softc *sc = ifp->if_softc;
7694
7695         DBENTER(BCE_VERBOSE_SEND);
7696
7697         BCE_LOCK(sc);
7698         bce_start_locked(ifp);
7699         BCE_UNLOCK(sc);
7700
7701         DBEXIT(BCE_VERBOSE_SEND);
7702 }
7703
7704
7705 /****************************************************************************/
7706 /* Handles any IOCTL calls from the operating system.                       */
7707 /*                                                                          */
7708 /* Returns:                                                                 */
7709 /*   0 for success, positive value for failure.                             */
7710 /****************************************************************************/
7711 static int
7712 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
7713 {
7714         struct bce_softc *sc = ifp->if_softc;
7715         struct ifreq *ifr = (struct ifreq *) data;
7716         struct mii_data *mii;
7717         int mask, error = 0;
7718
7719         DBENTER(BCE_VERBOSE_MISC);
7720
7721         switch(command) {
7722
7723         /* Set the interface MTU. */
7724         case SIOCSIFMTU:
7725                 /* Check that the MTU setting is supported. */
7726                 if ((ifr->ifr_mtu < BCE_MIN_MTU) ||
7727                         (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) {
7728                         error = EINVAL;
7729                         break;
7730                 }
7731
7732                 DBPRINT(sc, BCE_INFO_MISC,
7733                     "SIOCSIFMTU: Changing MTU from %d to %d\n",
7734                     (int) ifp->if_mtu, (int) ifr->ifr_mtu);
7735
7736                 BCE_LOCK(sc);
7737                 ifp->if_mtu = ifr->ifr_mtu;
7738                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7739                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
7740                         bce_init_locked(sc);
7741                 }
7742                 BCE_UNLOCK(sc);
7743                 break;
7744
7745         /* Set interface flags. */
7746         case SIOCSIFFLAGS:
7747                 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n");
7748
7749                 BCE_LOCK(sc);
7750
7751                 /* Check if the interface is up. */
7752                 if (ifp->if_flags & IFF_UP) {
7753                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7754                                 /* Change promiscuous/multicast flags as necessary. */
7755                                 bce_set_rx_mode(sc);
7756                         } else {
7757                                 /* Start the HW */
7758                                 bce_init_locked(sc);
7759                         }
7760                 } else {
7761                         /* The interface is down, check if driver is running. */
7762                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7763                                 bce_stop(sc);
7764
7765                                 /* If MFW is running, restart the controller a bit. */
7766                                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
7767                                         bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
7768                                         bce_chipinit(sc);
7769                                         bce_mgmt_init_locked(sc);
7770                                 }
7771                         }
7772                 }
7773
7774                 BCE_UNLOCK(sc);
7775                 break;
7776
7777         /* Add/Delete multicast address */
7778         case SIOCADDMULTI:
7779         case SIOCDELMULTI:
7780                 DBPRINT(sc, BCE_VERBOSE_MISC,
7781                     "Received SIOCADDMULTI/SIOCDELMULTI\n");
7782
7783                 BCE_LOCK(sc);
7784                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
7785                         bce_set_rx_mode(sc);
7786                 BCE_UNLOCK(sc);
7787
7788                 break;
7789
7790         /* Set/Get Interface media */
7791         case SIOCSIFMEDIA:
7792         case SIOCGIFMEDIA:
7793                 DBPRINT(sc, BCE_VERBOSE_MISC,
7794                     "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n");
7795                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
7796                         error = ifmedia_ioctl(ifp, ifr, &sc->bce_ifmedia,
7797                             command);
7798                 else {
7799                         mii = device_get_softc(sc->bce_miibus);
7800                         error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
7801                             command);
7802                 }
7803                 break;
7804
7805         /* Set interface capability */
7806         case SIOCSIFCAP:
7807                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
7808                 DBPRINT(sc, BCE_INFO_MISC,
7809                     "Received SIOCSIFCAP = 0x%08X\n", (u32) mask);
7810
7811                 /* Toggle the TX checksum capabilities enable flag. */
7812                 if (mask & IFCAP_TXCSUM &&
7813                     ifp->if_capabilities & IFCAP_TXCSUM) {
7814                         ifp->if_capenable ^= IFCAP_TXCSUM;
7815                         if (IFCAP_TXCSUM & ifp->if_capenable)
7816                                 ifp->if_hwassist |= BCE_IF_HWASSIST;
7817                         else
7818                                 ifp->if_hwassist &= ~BCE_IF_HWASSIST;
7819                 }
7820
7821                 /* Toggle the RX checksum capabilities enable flag. */
7822                 if (mask & IFCAP_RXCSUM &&
7823                     ifp->if_capabilities & IFCAP_RXCSUM)
7824                         ifp->if_capenable ^= IFCAP_RXCSUM;
7825
7826                 /* Toggle the TSO capabilities enable flag. */
7827                 if (bce_tso_enable && (mask & IFCAP_TSO4) &&
7828                     ifp->if_capabilities & IFCAP_TSO4) {
7829                         ifp->if_capenable ^= IFCAP_TSO4;
7830                         if (IFCAP_TSO4 & ifp->if_capenable)
7831                                 ifp->if_hwassist |= CSUM_TSO;
7832                         else
7833                                 ifp->if_hwassist &= ~CSUM_TSO;
7834                 }
7835
7836                 if (mask & IFCAP_VLAN_HWCSUM &&
7837                     ifp->if_capabilities & IFCAP_VLAN_HWCSUM)
7838                         ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
7839
7840                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
7841                     (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
7842                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
7843                 /*
7844                  * Don't actually disable VLAN tag stripping as
7845                  * management firmware (ASF/IPMI/UMP) requires the
7846                  * feature. If VLAN tag stripping is disabled driver
7847                  * will manually reconstruct the VLAN frame by
7848                  * appending stripped VLAN tag.
7849                  */
7850                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
7851                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) {
7852                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
7853                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
7854                             == 0)
7855                                 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
7856                 }
7857                 VLAN_CAPABILITIES(ifp);
7858                 break;
7859         default:
7860                 /* We don't know how to handle the IOCTL, pass it on. */
7861                 error = ether_ioctl(ifp, command, data);
7862                 break;
7863         }
7864
7865         DBEXIT(BCE_VERBOSE_MISC);
7866         return(error);
7867 }
7868
7869
7870 /****************************************************************************/
7871 /* Transmit timeout handler.                                                */
7872 /*                                                                          */
7873 /* Returns:                                                                 */
7874 /*   Nothing.                                                               */
7875 /****************************************************************************/
7876 static void
7877 bce_watchdog(struct bce_softc *sc)
7878 {
7879         uint32_t status;
7880
7881         DBENTER(BCE_EXTREME_SEND);
7882
7883         BCE_LOCK_ASSERT(sc);
7884
7885         status = 0;
7886         /* If the watchdog timer hasn't expired then just exit. */
7887         if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
7888                 goto bce_watchdog_exit;
7889
7890         status = REG_RD(sc, BCE_EMAC_RX_STATUS);
7891         /* If pause frames are active then don't reset the hardware. */
7892         if ((sc->bce_flags & BCE_USING_RX_FLOW_CONTROL) != 0) {
7893                 if ((status & BCE_EMAC_RX_STATUS_FFED) != 0) {
7894                         /*
7895                          * If link partner has us in XOFF state then wait for
7896                          * the condition to clear.
7897                          */
7898                         sc->watchdog_timer = BCE_TX_TIMEOUT;
7899                         goto bce_watchdog_exit;
7900                 } else if ((status & BCE_EMAC_RX_STATUS_FF_RECEIVED) != 0 &&
7901                         (status & BCE_EMAC_RX_STATUS_N_RECEIVED) != 0) {
7902                         /*
7903                          * If we're not currently XOFF'ed but have recently
7904                          * been XOFF'd/XON'd then assume that's delaying TX
7905                          * this time around.
7906                          */
7907                         sc->watchdog_timer = BCE_TX_TIMEOUT;
7908                         goto bce_watchdog_exit;
7909                 }
7910                 /*
7911                  * Any other condition is unexpected and the controller
7912                  * should be reset.
7913                  */
7914         }
7915
7916         BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n",
7917             __FILE__, __LINE__);
7918
7919         DBRUNMSG(BCE_INFO,
7920             bce_dump_driver_state(sc);
7921             bce_dump_status_block(sc);
7922             bce_dump_stats_block(sc);
7923             bce_dump_ftqs(sc);
7924             bce_dump_txp_state(sc, 0);
7925             bce_dump_rxp_state(sc, 0);
7926             bce_dump_tpat_state(sc, 0);
7927             bce_dump_cp_state(sc, 0);
7928             bce_dump_com_state(sc, 0));
7929
7930         DBRUN(bce_breakpoint(sc));
7931
7932         sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
7933
7934         bce_init_locked(sc);
7935         sc->bce_ifp->if_oerrors++;
7936
7937 bce_watchdog_exit:
7938         REG_WR(sc, BCE_EMAC_RX_STATUS, status);
7939         DBEXIT(BCE_EXTREME_SEND);
7940 }
7941
7942
7943 /*
7944  * Interrupt handler.
7945  */
7946 /****************************************************************************/
7947 /* Main interrupt entry point.  Verifies that the controller generated the  */
7948 /* interrupt and then calls a separate routine for handle the various       */
7949 /* interrupt causes (PHY, TX, RX).                                          */
7950 /*                                                                          */
7951 /* Returns:                                                                 */
7952 /*   Nothing.                                                               */
7953 /****************************************************************************/
7954 static void
7955 bce_intr(void *xsc)
7956 {
7957         struct bce_softc *sc;
7958         struct ifnet *ifp;
7959         u32 status_attn_bits;
7960         u16 hw_rx_cons, hw_tx_cons;
7961
7962         sc = xsc;
7963         ifp = sc->bce_ifp;
7964
7965         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
7966         DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
7967         DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc));
7968
7969         BCE_LOCK(sc);
7970
7971         DBRUN(sc->interrupts_generated++);
7972
7973         /* Synchnorize before we read from interface's status block */
7974         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
7975
7976         /*
7977          * If the hardware status block index matches the last value read
7978          * by the driver and we haven't asserted our interrupt then there's
7979          * nothing to do.  This may only happen in case of INTx due to the
7980          * interrupt arriving at the CPU before the status block is updated.
7981          */
7982         if ((sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) == 0 &&
7983             sc->status_block->status_idx == sc->last_status_idx &&
7984             (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
7985              BCE_PCICFG_MISC_STATUS_INTA_VALUE)) {
7986                 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n",
7987                     __FUNCTION__);
7988                 goto bce_intr_exit;
7989         }
7990
7991         /* Ack the interrupt and stop others from occuring. */
7992         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7993             BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
7994             BCE_PCICFG_INT_ACK_CMD_MASK_INT);
7995
7996         /* Check if the hardware has finished any work. */
7997         hw_rx_cons = bce_get_hw_rx_cons(sc);
7998         hw_tx_cons = bce_get_hw_tx_cons(sc);
7999
8000         /* Keep processing data as long as there is work to do. */
8001         for (;;) {
8002
8003                 status_attn_bits = sc->status_block->status_attn_bits;
8004
8005                 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control),
8006                     BCE_PRINTF("Simulating unexpected status attention "
8007                     "bit set.");
8008                     sc->unexpected_attention_sim_count++;
8009                     status_attn_bits = status_attn_bits |
8010                     STATUS_ATTN_BITS_PARITY_ERROR);
8011
8012                 /* Was it a link change interrupt? */
8013                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
8014                     (sc->status_block->status_attn_bits_ack &
8015                      STATUS_ATTN_BITS_LINK_STATE)) {
8016                         bce_phy_intr(sc);
8017
8018                         /* Clear transient updates during link state change. */
8019                         REG_WR(sc, BCE_HC_COMMAND, sc->hc_command |
8020                             BCE_HC_COMMAND_COAL_NOW_WO_INT);
8021                         REG_RD(sc, BCE_HC_COMMAND);
8022                 }
8023
8024                 /* If any other attention is asserted, the chip is toast. */
8025                 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
8026                     (sc->status_block->status_attn_bits_ack &
8027                     ~STATUS_ATTN_BITS_LINK_STATE))) {
8028
8029                         sc->unexpected_attention_count++;
8030
8031                         BCE_PRINTF("%s(%d): Fatal attention detected: "
8032                             "0x%08X\n", __FILE__, __LINE__,
8033                             sc->status_block->status_attn_bits);
8034
8035                         DBRUNMSG(BCE_FATAL,
8036                             if (unexpected_attention_sim_control == 0)
8037                                 bce_breakpoint(sc));
8038
8039                         bce_init_locked(sc);
8040                         goto bce_intr_exit;
8041                 }
8042
8043                 /* Check for any completed RX frames. */
8044                 if (hw_rx_cons != sc->hw_rx_cons)
8045                         bce_rx_intr(sc);
8046
8047                 /* Check for any completed TX frames. */
8048                 if (hw_tx_cons != sc->hw_tx_cons)
8049                         bce_tx_intr(sc);
8050
8051                 /* Save status block index value for the next interrupt. */
8052                 sc->last_status_idx = sc->status_block->status_idx;
8053
8054                 /*
8055                  * Prevent speculative reads from getting
8056                  * ahead of the status block.
8057                  */
8058                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
8059                     BUS_SPACE_BARRIER_READ);
8060
8061                 /*
8062                  * If there's no work left then exit the
8063                  * interrupt service routine.
8064                  */
8065                 hw_rx_cons = bce_get_hw_rx_cons(sc);
8066                 hw_tx_cons = bce_get_hw_tx_cons(sc);
8067
8068                 if ((hw_rx_cons == sc->hw_rx_cons) &&
8069                     (hw_tx_cons == sc->hw_tx_cons))
8070                         break;
8071         }
8072
8073         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREREAD);
8074
8075         /* Re-enable interrupts. */
8076         bce_enable_intr(sc, 0);
8077
8078         /* Handle any frames that arrived while handling the interrupt. */
8079         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
8080             !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
8081                 bce_start_locked(ifp);
8082
8083 bce_intr_exit:
8084         BCE_UNLOCK(sc);
8085
8086         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
8087 }
8088
8089
8090 /****************************************************************************/
8091 /* Programs the various packet receive modes (broadcast and multicast).     */
8092 /*                                                                          */
8093 /* Returns:                                                                 */
8094 /*   Nothing.                                                               */
8095 /****************************************************************************/
8096 static void
8097 bce_set_rx_mode(struct bce_softc *sc)
8098 {
8099         struct ifnet *ifp;
8100         struct ifmultiaddr *ifma;
8101         u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
8102         u32 rx_mode, sort_mode;
8103         int h, i;
8104
8105         DBENTER(BCE_VERBOSE_MISC);
8106
8107         BCE_LOCK_ASSERT(sc);
8108
8109         ifp = sc->bce_ifp;
8110
8111         /* Initialize receive mode default settings. */
8112         rx_mode   = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
8113             BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
8114         sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
8115
8116         /*
8117          * ASF/IPMI/UMP firmware requires that VLAN tag stripping
8118          * be enbled.
8119          */
8120         if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
8121             (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)))
8122                 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
8123
8124         /*
8125          * Check for promiscuous, all multicast, or selected
8126          * multicast address filtering.
8127          */
8128         if (ifp->if_flags & IFF_PROMISC) {
8129                 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n");
8130
8131                 /* Enable promiscuous mode. */
8132                 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
8133                 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
8134         } else if (ifp->if_flags & IFF_ALLMULTI) {
8135                 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n");
8136
8137                 /* Enable all multicast addresses. */
8138                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
8139                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
8140                             0xffffffff);
8141                 }
8142                 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
8143         } else {
8144                 /* Accept one or more multicast(s). */
8145                 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n");
8146
8147                 if_maddr_rlock(ifp);
8148                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
8149                         if (ifma->ifma_addr->sa_family != AF_LINK)
8150                                 continue;
8151                         h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
8152                             ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF;
8153                             hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
8154                 }
8155                 if_maddr_runlock(ifp);
8156
8157                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++)
8158                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]);
8159
8160                 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
8161         }
8162
8163         /* Only make changes if the recive mode has actually changed. */
8164         if (rx_mode != sc->rx_mode) {
8165                 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: "
8166                     "0x%08X\n", rx_mode);
8167
8168                 sc->rx_mode = rx_mode;
8169                 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
8170         }
8171
8172         /* Disable and clear the exisitng sort before enabling a new sort. */
8173         REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
8174         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
8175         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
8176
8177         DBEXIT(BCE_VERBOSE_MISC);
8178 }
8179
8180
8181 /****************************************************************************/
8182 /* Called periodically to updates statistics from the controllers           */
8183 /* statistics block.                                                        */
8184 /*                                                                          */
8185 /* Returns:                                                                 */
8186 /*   Nothing.                                                               */
8187 /****************************************************************************/
8188 static void
8189 bce_stats_update(struct bce_softc *sc)
8190 {
8191         struct ifnet *ifp;
8192         struct statistics_block *stats;
8193
8194         DBENTER(BCE_EXTREME_MISC);
8195
8196         ifp = sc->bce_ifp;
8197
8198         bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD);
8199
8200         stats = (struct statistics_block *) sc->stats_block;
8201
8202         /*
8203          * Certain controllers don't report
8204          * carrier sense errors correctly.
8205          * See errata E11_5708CA0_1165.
8206          */
8207         if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
8208             !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0))
8209                 ifp->if_oerrors +=
8210                     (u_long) stats->stat_Dot3StatsCarrierSenseErrors;
8211
8212         /*
8213          * Update the sysctl statistics from the
8214          * hardware statistics.
8215          */
8216         sc->stat_IfHCInOctets =
8217             ((u64) stats->stat_IfHCInOctets_hi << 32) +
8218              (u64) stats->stat_IfHCInOctets_lo;
8219
8220         sc->stat_IfHCInBadOctets =
8221             ((u64) stats->stat_IfHCInBadOctets_hi << 32) +
8222              (u64) stats->stat_IfHCInBadOctets_lo;
8223
8224         sc->stat_IfHCOutOctets =
8225             ((u64) stats->stat_IfHCOutOctets_hi << 32) +
8226              (u64) stats->stat_IfHCOutOctets_lo;
8227
8228         sc->stat_IfHCOutBadOctets =
8229             ((u64) stats->stat_IfHCOutBadOctets_hi << 32) +
8230              (u64) stats->stat_IfHCOutBadOctets_lo;
8231
8232         sc->stat_IfHCInUcastPkts =
8233             ((u64) stats->stat_IfHCInUcastPkts_hi << 32) +
8234              (u64) stats->stat_IfHCInUcastPkts_lo;
8235
8236         sc->stat_IfHCInMulticastPkts =
8237             ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) +
8238              (u64) stats->stat_IfHCInMulticastPkts_lo;
8239
8240         sc->stat_IfHCInBroadcastPkts =
8241             ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) +
8242              (u64) stats->stat_IfHCInBroadcastPkts_lo;
8243
8244         sc->stat_IfHCOutUcastPkts =
8245             ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) +
8246              (u64) stats->stat_IfHCOutUcastPkts_lo;
8247
8248         sc->stat_IfHCOutMulticastPkts =
8249             ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) +
8250              (u64) stats->stat_IfHCOutMulticastPkts_lo;
8251
8252         sc->stat_IfHCOutBroadcastPkts =
8253             ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) +
8254              (u64) stats->stat_IfHCOutBroadcastPkts_lo;
8255
8256         /* ToDo: Preserve counters beyond 32 bits? */
8257         /* ToDo: Read the statistics from auto-clear regs? */
8258
8259         sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
8260             stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
8261
8262         sc->stat_Dot3StatsCarrierSenseErrors =
8263             stats->stat_Dot3StatsCarrierSenseErrors;
8264
8265         sc->stat_Dot3StatsFCSErrors =
8266             stats->stat_Dot3StatsFCSErrors;
8267
8268         sc->stat_Dot3StatsAlignmentErrors =
8269             stats->stat_Dot3StatsAlignmentErrors;
8270
8271         sc->stat_Dot3StatsSingleCollisionFrames =
8272             stats->stat_Dot3StatsSingleCollisionFrames;
8273
8274         sc->stat_Dot3StatsMultipleCollisionFrames =
8275             stats->stat_Dot3StatsMultipleCollisionFrames;
8276
8277         sc->stat_Dot3StatsDeferredTransmissions =
8278             stats->stat_Dot3StatsDeferredTransmissions;
8279
8280         sc->stat_Dot3StatsExcessiveCollisions =
8281             stats->stat_Dot3StatsExcessiveCollisions;
8282
8283         sc->stat_Dot3StatsLateCollisions =
8284             stats->stat_Dot3StatsLateCollisions;
8285
8286         sc->stat_EtherStatsCollisions =
8287             stats->stat_EtherStatsCollisions;
8288
8289         sc->stat_EtherStatsFragments =
8290             stats->stat_EtherStatsFragments;
8291
8292         sc->stat_EtherStatsJabbers =
8293             stats->stat_EtherStatsJabbers;
8294
8295         sc->stat_EtherStatsUndersizePkts =
8296             stats->stat_EtherStatsUndersizePkts;
8297
8298         sc->stat_EtherStatsOversizePkts =
8299              stats->stat_EtherStatsOversizePkts;
8300
8301         sc->stat_EtherStatsPktsRx64Octets =
8302             stats->stat_EtherStatsPktsRx64Octets;
8303
8304         sc->stat_EtherStatsPktsRx65Octetsto127Octets =
8305             stats->stat_EtherStatsPktsRx65Octetsto127Octets;
8306
8307         sc->stat_EtherStatsPktsRx128Octetsto255Octets =
8308             stats->stat_EtherStatsPktsRx128Octetsto255Octets;
8309
8310         sc->stat_EtherStatsPktsRx256Octetsto511Octets =
8311             stats->stat_EtherStatsPktsRx256Octetsto511Octets;
8312
8313         sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
8314             stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
8315
8316         sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
8317             stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
8318
8319         sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
8320             stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
8321
8322         sc->stat_EtherStatsPktsTx64Octets =
8323             stats->stat_EtherStatsPktsTx64Octets;
8324
8325         sc->stat_EtherStatsPktsTx65Octetsto127Octets =
8326             stats->stat_EtherStatsPktsTx65Octetsto127Octets;
8327
8328         sc->stat_EtherStatsPktsTx128Octetsto255Octets =
8329             stats->stat_EtherStatsPktsTx128Octetsto255Octets;
8330
8331         sc->stat_EtherStatsPktsTx256Octetsto511Octets =
8332             stats->stat_EtherStatsPktsTx256Octetsto511Octets;
8333
8334         sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
8335             stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
8336
8337         sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
8338             stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
8339
8340         sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
8341             stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
8342
8343         sc->stat_XonPauseFramesReceived =
8344             stats->stat_XonPauseFramesReceived;
8345
8346         sc->stat_XoffPauseFramesReceived =
8347             stats->stat_XoffPauseFramesReceived;
8348
8349         sc->stat_OutXonSent =
8350             stats->stat_OutXonSent;
8351
8352         sc->stat_OutXoffSent =
8353             stats->stat_OutXoffSent;
8354
8355         sc->stat_FlowControlDone =
8356             stats->stat_FlowControlDone;
8357
8358         sc->stat_MacControlFramesReceived =
8359             stats->stat_MacControlFramesReceived;
8360
8361         sc->stat_XoffStateEntered =
8362             stats->stat_XoffStateEntered;
8363
8364         sc->stat_IfInFramesL2FilterDiscards =
8365             stats->stat_IfInFramesL2FilterDiscards;
8366
8367         sc->stat_IfInRuleCheckerDiscards =
8368             stats->stat_IfInRuleCheckerDiscards;
8369
8370         sc->stat_IfInFTQDiscards =
8371             stats->stat_IfInFTQDiscards;
8372
8373         sc->stat_IfInMBUFDiscards =
8374             stats->stat_IfInMBUFDiscards;
8375
8376         sc->stat_IfInRuleCheckerP4Hit =
8377             stats->stat_IfInRuleCheckerP4Hit;
8378
8379         sc->stat_CatchupInRuleCheckerDiscards =
8380             stats->stat_CatchupInRuleCheckerDiscards;
8381
8382         sc->stat_CatchupInFTQDiscards =
8383             stats->stat_CatchupInFTQDiscards;
8384
8385         sc->stat_CatchupInMBUFDiscards =
8386             stats->stat_CatchupInMBUFDiscards;
8387
8388         sc->stat_CatchupInRuleCheckerP4Hit =
8389             stats->stat_CatchupInRuleCheckerP4Hit;
8390
8391         sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
8392
8393         /*
8394          * Update the interface statistics from the
8395          * hardware statistics.
8396          */
8397         ifp->if_collisions =
8398             (u_long) sc->stat_EtherStatsCollisions;
8399
8400         /* ToDo: This method loses soft errors. */
8401         ifp->if_ierrors =
8402             (u_long) sc->stat_EtherStatsUndersizePkts +
8403             (u_long) sc->stat_EtherStatsOversizePkts +
8404             (u_long) sc->stat_IfInMBUFDiscards +
8405             (u_long) sc->stat_Dot3StatsAlignmentErrors +
8406             (u_long) sc->stat_Dot3StatsFCSErrors +
8407             (u_long) sc->stat_IfInRuleCheckerDiscards +
8408             (u_long) sc->stat_IfInFTQDiscards +
8409             (u_long) sc->com_no_buffers;
8410
8411         /* ToDo: This method loses soft errors. */
8412         ifp->if_oerrors =
8413             (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
8414             (u_long) sc->stat_Dot3StatsExcessiveCollisions +
8415             (u_long) sc->stat_Dot3StatsLateCollisions;
8416
8417         /* ToDo: Add additional statistics? */
8418
8419         DBEXIT(BCE_EXTREME_MISC);
8420 }
8421
8422
8423 /****************************************************************************/
8424 /* Periodic function to notify the bootcode that the driver is still        */
8425 /* present.                                                                 */
8426 /*                                                                          */
8427 /* Returns:                                                                 */
8428 /*   Nothing.                                                               */
8429 /****************************************************************************/
8430 static void
8431 bce_pulse(void *xsc)
8432 {
8433         struct bce_softc *sc = xsc;
8434         u32 msg;
8435
8436         DBENTER(BCE_EXTREME_MISC);
8437
8438         BCE_LOCK_ASSERT(sc);
8439
8440         /* Tell the firmware that the driver is still running. */
8441         msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq;
8442         bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
8443
8444         /* Update the bootcode condition. */
8445         sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
8446
8447         /* Report whether the bootcode still knows the driver is running. */
8448         if (bce_verbose || bootverbose) {
8449                 if (sc->bce_drv_cardiac_arrest == FALSE) {
8450                         if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
8451                                 sc->bce_drv_cardiac_arrest = TRUE;
8452                                 BCE_PRINTF("%s(): Warning: bootcode "
8453                                     "thinks driver is absent! "
8454                                     "(bc_state = 0x%08X)\n",
8455                                     __FUNCTION__, sc->bc_state);
8456                         }
8457                 } else {
8458                         /*
8459                          * Not supported by all bootcode versions.
8460                          * (v5.0.11+ and v5.2.1+)  Older bootcode
8461                          * will require the driver to reset the
8462                          * controller to clear this condition.
8463                          */
8464                         if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
8465                                 sc->bce_drv_cardiac_arrest = FALSE;
8466                                 BCE_PRINTF("%s(): Bootcode found the "
8467                                     "driver pulse! (bc_state = 0x%08X)\n",
8468                                     __FUNCTION__, sc->bc_state);
8469                         }
8470                 }
8471         }
8472
8473
8474         /* Schedule the next pulse. */
8475         callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
8476
8477         DBEXIT(BCE_EXTREME_MISC);
8478 }
8479
8480
8481 /****************************************************************************/
8482 /* Periodic function to perform maintenance tasks.                          */
8483 /*                                                                          */
8484 /* Returns:                                                                 */
8485 /*   Nothing.                                                               */
8486 /****************************************************************************/
8487 static void
8488 bce_tick(void *xsc)
8489 {
8490         struct bce_softc *sc = xsc;
8491         struct mii_data *mii;
8492         struct ifnet *ifp;
8493         struct ifmediareq ifmr;
8494
8495         ifp = sc->bce_ifp;
8496
8497         DBENTER(BCE_EXTREME_MISC);
8498
8499         BCE_LOCK_ASSERT(sc);
8500
8501         /* Schedule the next tick. */
8502         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
8503
8504         /* Update the statistics from the hardware statistics block. */
8505         bce_stats_update(sc);
8506
8507         /* Ensure page and RX chains get refilled in low-memory situations. */
8508         if (bce_hdr_split == TRUE)
8509                 bce_fill_pg_chain(sc);
8510         bce_fill_rx_chain(sc);
8511
8512         /* Check that chip hasn't hung. */
8513         bce_watchdog(sc);
8514
8515         /* If link is up already up then we're done. */
8516         if (sc->bce_link_up == TRUE)
8517                 goto bce_tick_exit;
8518
8519         /* Link is down.  Check what the PHY's doing. */
8520         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
8521                 bzero(&ifmr, sizeof(ifmr));
8522                 bce_ifmedia_sts_rphy(sc, &ifmr);
8523                 if ((ifmr.ifm_status & (IFM_ACTIVE | IFM_AVALID)) ==
8524                     (IFM_ACTIVE | IFM_AVALID)) {
8525                         sc->bce_link_up = TRUE;
8526                         bce_miibus_statchg(sc->bce_dev);
8527                 }
8528         } else {
8529                 mii = device_get_softc(sc->bce_miibus);
8530                 mii_tick(mii);
8531                 /* Check if the link has come up. */
8532                 if ((mii->mii_media_status & IFM_ACTIVE) &&
8533                     (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) {
8534                         DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n",
8535                             __FUNCTION__);
8536                         sc->bce_link_up = TRUE;
8537                         if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
8538                             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX ||
8539                             IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) &&
8540                             (bce_verbose || bootverbose))
8541                                 BCE_PRINTF("Gigabit link up!\n");
8542                 }
8543
8544         }
8545         if (sc->bce_link_up == TRUE) {
8546                 /* Now that link is up, handle any outstanding TX traffic. */
8547                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
8548                         DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found "
8549                             "pending TX traffic.\n", __FUNCTION__);
8550                         bce_start_locked(ifp);
8551                 }
8552         }
8553
8554 bce_tick_exit:
8555         DBEXIT(BCE_EXTREME_MISC);
8556 }
8557
8558 static void
8559 bce_fw_cap_init(struct bce_softc *sc)
8560 {
8561         u32 ack, cap, link;
8562
8563         ack = 0;
8564         cap = bce_shmem_rd(sc, BCE_FW_CAP_MB);
8565         if ((cap & BCE_FW_CAP_SIGNATURE_MAGIC_MASK) !=
8566             BCE_FW_CAP_SIGNATURE_MAGIC)
8567                 return;
8568         if ((cap & (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) ==
8569             (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN))
8570                 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC |
8571                     BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN;
8572         if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 &&
8573             (cap & BCE_FW_CAP_REMOTE_PHY_CAP) != 0) {
8574                 sc->bce_phy_flags &= ~BCE_PHY_REMOTE_PORT_FIBER_FLAG;
8575                 sc->bce_phy_flags |= BCE_PHY_REMOTE_CAP_FLAG;
8576                 link = bce_shmem_rd(sc, BCE_LINK_STATUS);
8577                 if ((link & BCE_LINK_STATUS_SERDES_LINK) != 0)
8578                         sc->bce_phy_flags |= BCE_PHY_REMOTE_PORT_FIBER_FLAG;
8579                 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC |
8580                     BCE_FW_CAP_REMOTE_PHY_CAP;
8581         }
8582
8583         if (ack != 0)
8584                 bce_shmem_wr(sc, BCE_DRV_ACK_CAP_MB, ack);
8585 }
8586
8587
8588 #ifdef BCE_DEBUG
8589 /****************************************************************************/
8590 /* Allows the driver state to be dumped through the sysctl interface.       */
8591 /*                                                                          */
8592 /* Returns:                                                                 */
8593 /*   0 for success, positive value for failure.                             */
8594 /****************************************************************************/
8595 static int
8596 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
8597 {
8598         int error;
8599         int result;
8600         struct bce_softc *sc;
8601
8602         result = -1;
8603         error = sysctl_handle_int(oidp, &result, 0, req);
8604
8605         if (error || !req->newptr)
8606                 return (error);
8607
8608         if (result == 1) {
8609                 sc = (struct bce_softc *)arg1;
8610                 bce_dump_driver_state(sc);
8611         }
8612
8613         return error;
8614 }
8615
8616
8617 /****************************************************************************/
8618 /* Allows the hardware state to be dumped through the sysctl interface.     */
8619 /*                                                                          */
8620 /* Returns:                                                                 */
8621 /*   0 for success, positive value for failure.                             */
8622 /****************************************************************************/
8623 static int
8624 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
8625 {
8626         int error;
8627         int result;
8628         struct bce_softc *sc;
8629
8630         result = -1;
8631         error = sysctl_handle_int(oidp, &result, 0, req);
8632
8633         if (error || !req->newptr)
8634                 return (error);
8635
8636         if (result == 1) {
8637                 sc = (struct bce_softc *)arg1;
8638                 bce_dump_hw_state(sc);
8639         }
8640
8641         return error;
8642 }
8643
8644
8645 /****************************************************************************/
8646 /* Allows the status block to be dumped through the sysctl interface.       */
8647 /*                                                                          */
8648 /* Returns:                                                                 */
8649 /*   0 for success, positive value for failure.                             */
8650 /****************************************************************************/
8651 static int
8652 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS)
8653 {
8654         int error;
8655         int result;
8656         struct bce_softc *sc;
8657
8658         result = -1;
8659         error = sysctl_handle_int(oidp, &result, 0, req);
8660
8661         if (error || !req->newptr)
8662                 return (error);
8663
8664         if (result == 1) {
8665                 sc = (struct bce_softc *)arg1;
8666                 bce_dump_status_block(sc);
8667         }
8668
8669         return error;
8670 }
8671
8672
8673 /****************************************************************************/
8674 /* Allows the stats block to be dumped through the sysctl interface.        */
8675 /*                                                                          */
8676 /* Returns:                                                                 */
8677 /*   0 for success, positive value for failure.                             */
8678 /****************************************************************************/
8679 static int
8680 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS)
8681 {
8682         int error;
8683         int result;
8684         struct bce_softc *sc;
8685
8686         result = -1;
8687         error = sysctl_handle_int(oidp, &result, 0, req);
8688
8689         if (error || !req->newptr)
8690                 return (error);
8691
8692         if (result == 1) {
8693                 sc = (struct bce_softc *)arg1;
8694                 bce_dump_stats_block(sc);
8695         }
8696
8697         return error;
8698 }
8699
8700
8701 /****************************************************************************/
8702 /* Allows the stat counters to be cleared without unloading/reloading the   */
8703 /* driver.                                                                  */
8704 /*                                                                          */
8705 /* Returns:                                                                 */
8706 /*   0 for success, positive value for failure.                             */
8707 /****************************************************************************/
8708 static int
8709 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS)
8710 {
8711         int error;
8712         int result;
8713         struct bce_softc *sc;
8714
8715         result = -1;
8716         error = sysctl_handle_int(oidp, &result, 0, req);
8717
8718         if (error || !req->newptr)
8719                 return (error);
8720
8721         if (result == 1) {
8722                 sc = (struct bce_softc *)arg1;
8723                 struct statistics_block *stats;
8724
8725                 stats = (struct statistics_block *) sc->stats_block;
8726                 bzero(stats, sizeof(struct statistics_block));
8727                 bus_dmamap_sync(sc->stats_tag, sc->stats_map,
8728                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
8729
8730                 /* Clear the internal H/W statistics counters. */
8731                 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
8732
8733                 /* Reset the driver maintained statistics. */
8734                 sc->interrupts_rx =
8735                     sc->interrupts_tx = 0;
8736                 sc->tso_frames_requested =
8737                     sc->tso_frames_completed =
8738                     sc->tso_frames_failed = 0;
8739                 sc->rx_empty_count =
8740                     sc->tx_full_count = 0;
8741                 sc->rx_low_watermark = USABLE_RX_BD_ALLOC;
8742                 sc->tx_hi_watermark = 0;
8743                 sc->l2fhdr_error_count =
8744                     sc->l2fhdr_error_sim_count = 0;
8745                 sc->mbuf_alloc_failed_count =
8746                     sc->mbuf_alloc_failed_sim_count = 0;
8747                 sc->dma_map_addr_rx_failed_count =
8748                     sc->dma_map_addr_tx_failed_count = 0;
8749                 sc->mbuf_frag_count = 0;
8750                 sc->csum_offload_tcp_udp =
8751                     sc->csum_offload_ip = 0;
8752                 sc->vlan_tagged_frames_rcvd =
8753                     sc->vlan_tagged_frames_stripped = 0;
8754                 sc->split_header_frames_rcvd =
8755                     sc->split_header_tcp_frames_rcvd = 0;
8756
8757                 /* Clear firmware maintained statistics. */
8758                 REG_WR_IND(sc, 0x120084, 0);
8759         }
8760
8761         return error;
8762 }
8763
8764
8765 /****************************************************************************/
8766 /* Allows the shared memory contents to be dumped through the sysctl  .     */
8767 /* interface.                                                               */
8768 /*                                                                          */
8769 /* Returns:                                                                 */
8770 /*   0 for success, positive value for failure.                             */
8771 /****************************************************************************/
8772 static int
8773 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS)
8774 {
8775         int error;
8776         int result;
8777         struct bce_softc *sc;
8778
8779         result = -1;
8780         error = sysctl_handle_int(oidp, &result, 0, req);
8781
8782         if (error || !req->newptr)
8783                 return (error);
8784
8785         if (result == 1) {
8786                 sc = (struct bce_softc *)arg1;
8787                 bce_dump_shmem_state(sc);
8788         }
8789
8790         return error;
8791 }
8792
8793
8794 /****************************************************************************/
8795 /* Allows the bootcode state to be dumped through the sysctl interface.     */
8796 /*                                                                          */
8797 /* Returns:                                                                 */
8798 /*   0 for success, positive value for failure.                             */
8799 /****************************************************************************/
8800 static int
8801 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS)
8802 {
8803         int error;
8804         int result;
8805         struct bce_softc *sc;
8806
8807         result = -1;
8808         error = sysctl_handle_int(oidp, &result, 0, req);
8809
8810         if (error || !req->newptr)
8811                 return (error);
8812
8813         if (result == 1) {
8814                 sc = (struct bce_softc *)arg1;
8815                 bce_dump_bc_state(sc);
8816         }
8817
8818         return error;
8819 }
8820
8821
8822 /****************************************************************************/
8823 /* Provides a sysctl interface to allow dumping the RX BD chain.            */
8824 /*                                                                          */
8825 /* Returns:                                                                 */
8826 /*   0 for success, positive value for failure.                             */
8827 /****************************************************************************/
8828 static int
8829 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS)
8830 {
8831         int error;
8832         int result;
8833         struct bce_softc *sc;
8834
8835         result = -1;
8836         error = sysctl_handle_int(oidp, &result, 0, req);
8837
8838         if (error || !req->newptr)
8839                 return (error);
8840
8841         if (result == 1) {
8842                 sc = (struct bce_softc *)arg1;
8843                 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC);
8844         }
8845
8846         return error;
8847 }
8848
8849
8850 /****************************************************************************/
8851 /* Provides a sysctl interface to allow dumping the RX MBUF chain.          */
8852 /*                                                                          */
8853 /* Returns:                                                                 */
8854 /*   0 for success, positive value for failure.                             */
8855 /****************************************************************************/
8856 static int
8857 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS)
8858 {
8859         int error;
8860         int result;
8861         struct bce_softc *sc;
8862
8863         result = -1;
8864         error = sysctl_handle_int(oidp, &result, 0, req);
8865
8866         if (error || !req->newptr)
8867                 return (error);
8868
8869         if (result == 1) {
8870                 sc = (struct bce_softc *)arg1;
8871                 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC);
8872         }
8873
8874         return error;
8875 }
8876
8877
8878 /****************************************************************************/
8879 /* Provides a sysctl interface to allow dumping the TX chain.               */
8880 /*                                                                          */
8881 /* Returns:                                                                 */
8882 /*   0 for success, positive value for failure.                             */
8883 /****************************************************************************/
8884 static int
8885 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
8886 {
8887         int error;
8888         int result;
8889         struct bce_softc *sc;
8890
8891         result = -1;
8892         error = sysctl_handle_int(oidp, &result, 0, req);
8893
8894         if (error || !req->newptr)
8895                 return (error);
8896
8897         if (result == 1) {
8898                 sc = (struct bce_softc *)arg1;
8899                 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC);
8900         }
8901
8902         return error;
8903 }
8904
8905
8906 /****************************************************************************/
8907 /* Provides a sysctl interface to allow dumping the page chain.             */
8908 /*                                                                          */
8909 /* Returns:                                                                 */
8910 /*   0 for success, positive value for failure.                             */
8911 /****************************************************************************/
8912 static int
8913 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS)
8914 {
8915         int error;
8916         int result;
8917         struct bce_softc *sc;
8918
8919         result = -1;
8920         error = sysctl_handle_int(oidp, &result, 0, req);
8921
8922         if (error || !req->newptr)
8923                 return (error);
8924
8925         if (result == 1) {
8926                 sc = (struct bce_softc *)arg1;
8927                 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC);
8928         }
8929
8930         return error;
8931 }
8932
8933 /****************************************************************************/
8934 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in  */
8935 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
8936 /*                                                                          */
8937 /* Returns:                                                                 */
8938 /*   0 for success, positive value for failure.                             */
8939 /****************************************************************************/
8940 static int
8941 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS)
8942 {
8943         struct bce_softc *sc = (struct bce_softc *)arg1;
8944         int error;
8945         u32 result;
8946         u32 val[1];
8947         u8 *data = (u8 *) val;
8948
8949         result = -1;
8950         error = sysctl_handle_int(oidp, &result, 0, req);
8951         if (error || (req->newptr == NULL))
8952                 return (error);
8953
8954         error = bce_nvram_read(sc, result, data, 4);
8955
8956         BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0]));
8957
8958         return (error);
8959 }
8960
8961
8962 /****************************************************************************/
8963 /* Provides a sysctl interface to allow reading arbitrary registers in the  */
8964 /* device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                            */
8965 /*                                                                          */
8966 /* Returns:                                                                 */
8967 /*   0 for success, positive value for failure.                             */
8968 /****************************************************************************/
8969 static int
8970 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
8971 {
8972         struct bce_softc *sc = (struct bce_softc *)arg1;
8973         int error;
8974         u32 val, result;
8975
8976         result = -1;
8977         error = sysctl_handle_int(oidp, &result, 0, req);
8978         if (error || (req->newptr == NULL))
8979                 return (error);
8980
8981         /* Make sure the register is accessible. */
8982         if (result < 0x8000) {
8983                 val = REG_RD(sc, result);
8984                 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8985         } else if (result < 0x0280000) {
8986                 val = REG_RD_IND(sc, result);
8987                 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8988         }
8989
8990         return (error);
8991 }
8992
8993
8994 /****************************************************************************/
8995 /* Provides a sysctl interface to allow reading arbitrary PHY registers in  */
8996 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
8997 /*                                                                          */
8998 /* Returns:                                                                 */
8999 /*   0 for success, positive value for failure.                             */
9000 /****************************************************************************/
9001 static int
9002 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
9003 {
9004         struct bce_softc *sc;
9005         device_t dev;
9006         int error, result;
9007         u16 val;
9008
9009         result = -1;
9010         error = sysctl_handle_int(oidp, &result, 0, req);
9011         if (error || (req->newptr == NULL))
9012                 return (error);
9013
9014         /* Make sure the register is accessible. */
9015         if (result < 0x20) {
9016                 sc = (struct bce_softc *)arg1;
9017                 dev = sc->bce_dev;
9018                 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
9019                 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val);
9020         }
9021         return (error);
9022 }
9023
9024
9025 /****************************************************************************/
9026 /* Provides a sysctl interface for dumping the nvram contents.              */
9027 /* DO NOT ENABLE ON PRODUCTION SYSTEMS!                                     */
9028 /*                                                                          */
9029 /* Returns:                                                                 */
9030 /*   0 for success, positive errno for failure.                             */
9031 /****************************************************************************/
9032 static int
9033 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS)
9034 {
9035         struct bce_softc *sc = (struct bce_softc *)arg1;
9036         int error, i;
9037
9038         if (sc->nvram_buf == NULL)
9039                 sc->nvram_buf = malloc(sc->bce_flash_size,
9040                                     M_TEMP, M_ZERO | M_WAITOK);
9041
9042         error = 0;
9043         if (req->oldlen == sc->bce_flash_size) {
9044                 for (i = 0; i < sc->bce_flash_size && error == 0; i++)
9045                         error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1);
9046         }
9047
9048         if (error == 0)
9049                 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size);
9050
9051         return error;
9052 }
9053
9054 #ifdef BCE_NVRAM_WRITE_SUPPORT
9055 /****************************************************************************/
9056 /* Provides a sysctl interface for writing to nvram.                        */
9057 /* DO NOT ENABLE ON PRODUCTION SYSTEMS!                                     */
9058 /*                                                                          */
9059 /* Returns:                                                                 */
9060 /*   0 for success, positive errno for failure.                             */
9061 /****************************************************************************/
9062 static int
9063 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS)
9064 {
9065         struct bce_softc *sc = (struct bce_softc *)arg1;
9066         int error;
9067
9068         if (sc->nvram_buf == NULL)
9069                 sc->nvram_buf = malloc(sc->bce_flash_size,
9070                                     M_TEMP, M_ZERO | M_WAITOK);
9071         else
9072                 bzero(sc->nvram_buf, sc->bce_flash_size);
9073
9074         error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size);
9075         if (error == 0)
9076                 return (error);
9077
9078         if (req->newlen == sc->bce_flash_size)
9079                 error = bce_nvram_write(sc, 0, sc->nvram_buf,
9080                             sc->bce_flash_size);
9081
9082
9083         return error;
9084 }
9085 #endif
9086
9087
9088 /****************************************************************************/
9089 /* Provides a sysctl interface to allow reading a CID.                      */
9090 /*                                                                          */
9091 /* Returns:                                                                 */
9092 /*   0 for success, positive value for failure.                             */
9093 /****************************************************************************/
9094 static int
9095 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS)
9096 {
9097         struct bce_softc *sc;
9098         int error, result;
9099
9100         result = -1;
9101         error = sysctl_handle_int(oidp, &result, 0, req);
9102         if (error || (req->newptr == NULL))
9103                 return (error);
9104
9105         /* Make sure the register is accessible. */
9106         if (result <= TX_CID) {
9107                 sc = (struct bce_softc *)arg1;
9108                 bce_dump_ctx(sc, result);
9109         }
9110
9111         return (error);
9112 }
9113
9114
9115 /****************************************************************************/
9116 /* Provides a sysctl interface to forcing the driver to dump state and      */
9117 /* enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                */
9118 /*                                                                          */
9119 /* Returns:                                                                 */
9120 /*   0 for success, positive value for failure.                             */
9121 /****************************************************************************/
9122 static int
9123 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
9124 {
9125         int error;
9126         int result;
9127         struct bce_softc *sc;
9128
9129         result = -1;
9130         error = sysctl_handle_int(oidp, &result, 0, req);
9131
9132         if (error || !req->newptr)
9133                 return (error);
9134
9135         if (result == 1) {
9136                 sc = (struct bce_softc *)arg1;
9137                 bce_breakpoint(sc);
9138         }
9139
9140         return error;
9141 }
9142 #endif
9143
9144 /****************************************************************************/
9145 /* Adds any sysctl parameters for tuning or debugging purposes.             */
9146 /*                                                                          */
9147 /* Returns:                                                                 */
9148 /*   0 for success, positive value for failure.                             */
9149 /****************************************************************************/
9150 static void
9151 bce_add_sysctls(struct bce_softc *sc)
9152 {
9153         struct sysctl_ctx_list *ctx;
9154         struct sysctl_oid_list *children;
9155
9156         DBENTER(BCE_VERBOSE_MISC);
9157
9158         ctx = device_get_sysctl_ctx(sc->bce_dev);
9159         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev));
9160
9161 #ifdef BCE_DEBUG
9162         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9163             "l2fhdr_error_sim_control",
9164             CTLFLAG_RW, &l2fhdr_error_sim_control,
9165             0, "Debug control to force l2fhdr errors");
9166
9167         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9168             "l2fhdr_error_sim_count",
9169             CTLFLAG_RD, &sc->l2fhdr_error_sim_count,
9170             0, "Number of simulated l2_fhdr errors");
9171 #endif
9172
9173         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9174             "l2fhdr_error_count",
9175             CTLFLAG_RD, &sc->l2fhdr_error_count,
9176             0, "Number of l2_fhdr errors");
9177
9178 #ifdef BCE_DEBUG
9179         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9180             "mbuf_alloc_failed_sim_control",
9181             CTLFLAG_RW, &mbuf_alloc_failed_sim_control,
9182             0, "Debug control to force mbuf allocation failures");
9183
9184         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9185             "mbuf_alloc_failed_sim_count",
9186             CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count,
9187             0, "Number of simulated mbuf cluster allocation failures");
9188 #endif
9189
9190         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9191             "mbuf_alloc_failed_count",
9192             CTLFLAG_RD, &sc->mbuf_alloc_failed_count,
9193             0, "Number of mbuf allocation failures");
9194
9195         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9196             "mbuf_frag_count",
9197             CTLFLAG_RD, &sc->mbuf_frag_count,
9198             0, "Number of fragmented mbufs");
9199
9200 #ifdef BCE_DEBUG
9201         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9202             "dma_map_addr_failed_sim_control",
9203             CTLFLAG_RW, &dma_map_addr_failed_sim_control,
9204             0, "Debug control to force DMA mapping failures");
9205
9206         /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */
9207         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9208             "dma_map_addr_failed_sim_count",
9209             CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count,
9210             0, "Number of simulated DMA mapping failures");
9211
9212 #endif
9213
9214         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9215             "dma_map_addr_rx_failed_count",
9216             CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count,
9217             0, "Number of RX DMA mapping failures");
9218
9219         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9220             "dma_map_addr_tx_failed_count",
9221             CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count,
9222             0, "Number of TX DMA mapping failures");
9223
9224 #ifdef BCE_DEBUG
9225         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9226             "unexpected_attention_sim_control",
9227             CTLFLAG_RW, &unexpected_attention_sim_control,
9228             0, "Debug control to simulate unexpected attentions");
9229
9230         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9231             "unexpected_attention_sim_count",
9232             CTLFLAG_RW, &sc->unexpected_attention_sim_count,
9233             0, "Number of simulated unexpected attentions");
9234 #endif
9235
9236         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9237             "unexpected_attention_count",
9238             CTLFLAG_RW, &sc->unexpected_attention_count,
9239             0, "Number of unexpected attentions");
9240
9241 #ifdef BCE_DEBUG
9242         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9243             "debug_bootcode_running_failure",
9244             CTLFLAG_RW, &bootcode_running_failure_sim_control,
9245             0, "Debug control to force bootcode running failures");
9246
9247         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9248             "rx_low_watermark",
9249             CTLFLAG_RD, &sc->rx_low_watermark,
9250             0, "Lowest level of free rx_bd's");
9251
9252         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9253             "rx_empty_count",
9254             CTLFLAG_RD, &sc->rx_empty_count,
9255             "Number of times the RX chain was empty");
9256
9257         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9258             "tx_hi_watermark",
9259             CTLFLAG_RD, &sc->tx_hi_watermark,
9260             0, "Highest level of used tx_bd's");
9261
9262         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9263             "tx_full_count",
9264             CTLFLAG_RD, &sc->tx_full_count,
9265             "Number of times the TX chain was full");
9266
9267         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9268             "tso_frames_requested",
9269             CTLFLAG_RD, &sc->tso_frames_requested,
9270             "Number of TSO frames requested");
9271
9272         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9273             "tso_frames_completed",
9274             CTLFLAG_RD, &sc->tso_frames_completed,
9275             "Number of TSO frames completed");
9276
9277         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9278             "tso_frames_failed",
9279             CTLFLAG_RD, &sc->tso_frames_failed,
9280             "Number of TSO frames failed");
9281
9282         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9283             "csum_offload_ip",
9284             CTLFLAG_RD, &sc->csum_offload_ip,
9285             "Number of IP checksum offload frames");
9286
9287         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9288             "csum_offload_tcp_udp",
9289             CTLFLAG_RD, &sc->csum_offload_tcp_udp,
9290             "Number of TCP/UDP checksum offload frames");
9291
9292         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9293             "vlan_tagged_frames_rcvd",
9294             CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd,
9295             "Number of VLAN tagged frames received");
9296
9297         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9298             "vlan_tagged_frames_stripped",
9299             CTLFLAG_RD, &sc->vlan_tagged_frames_stripped,
9300             "Number of VLAN tagged frames stripped");
9301
9302         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9303             "interrupts_rx",
9304             CTLFLAG_RD, &sc->interrupts_rx,
9305             "Number of RX interrupts");
9306
9307         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9308             "interrupts_tx",
9309             CTLFLAG_RD, &sc->interrupts_tx,
9310             "Number of TX interrupts");
9311
9312         if (bce_hdr_split == TRUE) {
9313                 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9314                     "split_header_frames_rcvd",
9315                     CTLFLAG_RD, &sc->split_header_frames_rcvd,
9316                     "Number of split header frames received");
9317
9318                 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9319                     "split_header_tcp_frames_rcvd",
9320                     CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd,
9321                     "Number of split header TCP frames received");
9322         }
9323
9324         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9325             "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD,
9326             (void *)sc, 0,
9327             bce_sysctl_nvram_dump, "S", "");
9328
9329 #ifdef BCE_NVRAM_WRITE_SUPPORT
9330         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9331             "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR,
9332             (void *)sc, 0,
9333             bce_sysctl_nvram_write, "S", "");
9334 #endif
9335 #endif /* BCE_DEBUG */
9336
9337         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9338             "stat_IfHcInOctets",
9339             CTLFLAG_RD, &sc->stat_IfHCInOctets,
9340             "Bytes received");
9341
9342         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9343             "stat_IfHCInBadOctets",
9344             CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
9345             "Bad bytes received");
9346
9347         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9348             "stat_IfHCOutOctets",
9349             CTLFLAG_RD, &sc->stat_IfHCOutOctets,
9350             "Bytes sent");
9351
9352         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9353             "stat_IfHCOutBadOctets",
9354             CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
9355             "Bad bytes sent");
9356
9357         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9358             "stat_IfHCInUcastPkts",
9359             CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
9360             "Unicast packets received");
9361
9362         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9363             "stat_IfHCInMulticastPkts",
9364             CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
9365             "Multicast packets received");
9366
9367         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9368             "stat_IfHCInBroadcastPkts",
9369             CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
9370             "Broadcast packets received");
9371
9372         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9373             "stat_IfHCOutUcastPkts",
9374             CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
9375             "Unicast packets sent");
9376
9377         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9378             "stat_IfHCOutMulticastPkts",
9379             CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
9380             "Multicast packets sent");
9381
9382         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9383             "stat_IfHCOutBroadcastPkts",
9384             CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
9385             "Broadcast packets sent");
9386
9387         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9388             "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
9389             CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
9390             0, "Internal MAC transmit errors");
9391
9392         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9393             "stat_Dot3StatsCarrierSenseErrors",
9394             CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
9395             0, "Carrier sense errors");
9396
9397         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9398             "stat_Dot3StatsFCSErrors",
9399             CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
9400             0, "Frame check sequence errors");
9401
9402         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9403             "stat_Dot3StatsAlignmentErrors",
9404             CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
9405             0, "Alignment errors");
9406
9407         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9408             "stat_Dot3StatsSingleCollisionFrames",
9409             CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
9410             0, "Single Collision Frames");
9411
9412         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9413             "stat_Dot3StatsMultipleCollisionFrames",
9414             CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
9415             0, "Multiple Collision Frames");
9416
9417         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9418             "stat_Dot3StatsDeferredTransmissions",
9419             CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
9420             0, "Deferred Transmissions");
9421
9422         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9423             "stat_Dot3StatsExcessiveCollisions",
9424             CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
9425             0, "Excessive Collisions");
9426
9427         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9428             "stat_Dot3StatsLateCollisions",
9429             CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
9430             0, "Late Collisions");
9431
9432         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9433             "stat_EtherStatsCollisions",
9434             CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
9435             0, "Collisions");
9436
9437         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9438             "stat_EtherStatsFragments",
9439             CTLFLAG_RD, &sc->stat_EtherStatsFragments,
9440             0, "Fragments");
9441
9442         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9443             "stat_EtherStatsJabbers",
9444             CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
9445             0, "Jabbers");
9446
9447         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9448             "stat_EtherStatsUndersizePkts",
9449             CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
9450             0, "Undersize packets");
9451
9452         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9453             "stat_EtherStatsOversizePkts",
9454             CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts,
9455             0, "stat_EtherStatsOversizePkts");
9456
9457         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9458             "stat_EtherStatsPktsRx64Octets",
9459             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
9460             0, "Bytes received in 64 byte packets");
9461
9462         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9463             "stat_EtherStatsPktsRx65Octetsto127Octets",
9464             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
9465             0, "Bytes received in 65 to 127 byte packets");
9466
9467         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9468             "stat_EtherStatsPktsRx128Octetsto255Octets",
9469             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
9470             0, "Bytes received in 128 to 255 byte packets");
9471
9472         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9473             "stat_EtherStatsPktsRx256Octetsto511Octets",
9474             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
9475             0, "Bytes received in 256 to 511 byte packets");
9476
9477         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9478             "stat_EtherStatsPktsRx512Octetsto1023Octets",
9479             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
9480             0, "Bytes received in 512 to 1023 byte packets");
9481
9482         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9483             "stat_EtherStatsPktsRx1024Octetsto1522Octets",
9484             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
9485             0, "Bytes received in 1024 t0 1522 byte packets");
9486
9487         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9488             "stat_EtherStatsPktsRx1523Octetsto9022Octets",
9489             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
9490             0, "Bytes received in 1523 to 9022 byte packets");
9491
9492         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9493             "stat_EtherStatsPktsTx64Octets",
9494             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
9495             0, "Bytes sent in 64 byte packets");
9496
9497         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9498             "stat_EtherStatsPktsTx65Octetsto127Octets",
9499             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
9500             0, "Bytes sent in 65 to 127 byte packets");
9501
9502         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9503             "stat_EtherStatsPktsTx128Octetsto255Octets",
9504             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
9505             0, "Bytes sent in 128 to 255 byte packets");
9506
9507         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9508             "stat_EtherStatsPktsTx256Octetsto511Octets",
9509             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
9510             0, "Bytes sent in 256 to 511 byte packets");
9511
9512         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9513             "stat_EtherStatsPktsTx512Octetsto1023Octets",
9514             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
9515             0, "Bytes sent in 512 to 1023 byte packets");
9516
9517         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9518             "stat_EtherStatsPktsTx1024Octetsto1522Octets",
9519             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
9520             0, "Bytes sent in 1024 to 1522 byte packets");
9521
9522         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9523             "stat_EtherStatsPktsTx1523Octetsto9022Octets",
9524             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
9525             0, "Bytes sent in 1523 to 9022 byte packets");
9526
9527         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9528             "stat_XonPauseFramesReceived",
9529             CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
9530             0, "XON pause frames receved");
9531
9532         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9533             "stat_XoffPauseFramesReceived",
9534             CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
9535             0, "XOFF pause frames received");
9536
9537         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9538             "stat_OutXonSent",
9539             CTLFLAG_RD, &sc->stat_OutXonSent,
9540             0, "XON pause frames sent");
9541
9542         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9543             "stat_OutXoffSent",
9544             CTLFLAG_RD, &sc->stat_OutXoffSent,
9545             0, "XOFF pause frames sent");
9546
9547         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9548             "stat_FlowControlDone",
9549             CTLFLAG_RD, &sc->stat_FlowControlDone,
9550             0, "Flow control done");
9551
9552         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9553             "stat_MacControlFramesReceived",
9554             CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
9555             0, "MAC control frames received");
9556
9557         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9558             "stat_XoffStateEntered",
9559             CTLFLAG_RD, &sc->stat_XoffStateEntered,
9560             0, "XOFF state entered");
9561
9562         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9563             "stat_IfInFramesL2FilterDiscards",
9564             CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
9565             0, "Received L2 packets discarded");
9566
9567         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9568             "stat_IfInRuleCheckerDiscards",
9569             CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
9570             0, "Received packets discarded by rule");
9571
9572         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9573             "stat_IfInFTQDiscards",
9574             CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
9575             0, "Received packet FTQ discards");
9576
9577         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9578             "stat_IfInMBUFDiscards",
9579             CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
9580             0, "Received packets discarded due to lack "
9581             "of controller buffer memory");
9582
9583         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9584             "stat_IfInRuleCheckerP4Hit",
9585             CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
9586             0, "Received packets rule checker hits");
9587
9588         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9589             "stat_CatchupInRuleCheckerDiscards",
9590             CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
9591             0, "Received packets discarded in Catchup path");
9592
9593         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9594             "stat_CatchupInFTQDiscards",
9595             CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
9596             0, "Received packets discarded in FTQ in Catchup path");
9597
9598         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9599             "stat_CatchupInMBUFDiscards",
9600             CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
9601             0, "Received packets discarded in controller "
9602             "buffer memory in Catchup path");
9603
9604         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9605             "stat_CatchupInRuleCheckerP4Hit",
9606             CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
9607             0, "Received packets rule checker hits in Catchup path");
9608
9609         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9610             "com_no_buffers",
9611             CTLFLAG_RD, &sc->com_no_buffers,
9612             0, "Valid packets received but no RX buffers available");
9613
9614 #ifdef BCE_DEBUG
9615         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9616             "driver_state", CTLTYPE_INT | CTLFLAG_RW,
9617             (void *)sc, 0,
9618             bce_sysctl_driver_state, "I", "Drive state information");
9619
9620         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9621             "hw_state", CTLTYPE_INT | CTLFLAG_RW,
9622             (void *)sc, 0,
9623             bce_sysctl_hw_state, "I", "Hardware state information");
9624
9625         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9626             "status_block", CTLTYPE_INT | CTLFLAG_RW,
9627             (void *)sc, 0,
9628             bce_sysctl_status_block, "I", "Dump status block");
9629
9630         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9631             "stats_block", CTLTYPE_INT | CTLFLAG_RW,
9632             (void *)sc, 0,
9633             bce_sysctl_stats_block, "I", "Dump statistics block");
9634
9635         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9636             "stats_clear", CTLTYPE_INT | CTLFLAG_RW,
9637             (void *)sc, 0,
9638             bce_sysctl_stats_clear, "I", "Clear statistics block");
9639
9640         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9641             "shmem_state", CTLTYPE_INT | CTLFLAG_RW,
9642             (void *)sc, 0,
9643             bce_sysctl_shmem_state, "I", "Shared memory state information");
9644
9645         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9646             "bc_state", CTLTYPE_INT | CTLFLAG_RW,
9647             (void *)sc, 0,
9648             bce_sysctl_bc_state, "I", "Bootcode state information");
9649
9650         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9651             "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW,
9652             (void *)sc, 0,
9653             bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain");
9654
9655         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9656             "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW,
9657             (void *)sc, 0,
9658             bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain");
9659
9660         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9661             "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
9662             (void *)sc, 0,
9663             bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
9664
9665         if (bce_hdr_split == TRUE) {
9666                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9667                     "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW,
9668                     (void *)sc, 0,
9669                     bce_sysctl_dump_pg_chain, "I", "Dump page chain");
9670         }
9671
9672         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9673             "dump_ctx", CTLTYPE_INT | CTLFLAG_RW,
9674             (void *)sc, 0,
9675             bce_sysctl_dump_ctx, "I", "Dump context memory");
9676
9677         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9678             "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
9679             (void *)sc, 0,
9680             bce_sysctl_breakpoint, "I", "Driver breakpoint");
9681
9682         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9683             "reg_read", CTLTYPE_INT | CTLFLAG_RW,
9684             (void *)sc, 0,
9685             bce_sysctl_reg_read, "I", "Register read");
9686
9687         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9688             "nvram_read", CTLTYPE_INT | CTLFLAG_RW,
9689             (void *)sc, 0,
9690             bce_sysctl_nvram_read, "I", "NVRAM read");
9691
9692         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9693             "phy_read", CTLTYPE_INT | CTLFLAG_RW,
9694             (void *)sc, 0,
9695             bce_sysctl_phy_read, "I", "PHY register read");
9696
9697 #endif
9698
9699         DBEXIT(BCE_VERBOSE_MISC);
9700 }
9701
9702
9703 /****************************************************************************/
9704 /* BCE Debug Routines                                                       */
9705 /****************************************************************************/
9706 #ifdef BCE_DEBUG
9707
9708 /****************************************************************************/
9709 /* Freezes the controller to allow for a cohesive state dump.               */
9710 /*                                                                          */
9711 /* Returns:                                                                 */
9712 /*   Nothing.                                                               */
9713 /****************************************************************************/
9714 static __attribute__ ((noinline)) void
9715 bce_freeze_controller(struct bce_softc *sc)
9716 {
9717         u32 val;
9718         val = REG_RD(sc, BCE_MISC_COMMAND);
9719         val |= BCE_MISC_COMMAND_DISABLE_ALL;
9720         REG_WR(sc, BCE_MISC_COMMAND, val);
9721 }
9722
9723
9724 /****************************************************************************/
9725 /* Unfreezes the controller after a freeze operation.  This may not always  */
9726 /* work and the controller will require a reset!                            */
9727 /*                                                                          */
9728 /* Returns:                                                                 */
9729 /*   Nothing.                                                               */
9730 /****************************************************************************/
9731 static __attribute__ ((noinline)) void
9732 bce_unfreeze_controller(struct bce_softc *sc)
9733 {
9734         u32 val;
9735         val = REG_RD(sc, BCE_MISC_COMMAND);
9736         val |= BCE_MISC_COMMAND_ENABLE_ALL;
9737         REG_WR(sc, BCE_MISC_COMMAND, val);
9738 }
9739
9740
9741 /****************************************************************************/
9742 /* Prints out Ethernet frame information from an mbuf.                      */
9743 /*                                                                          */
9744 /* Partially decode an Ethernet frame to look at some important headers.    */
9745 /*                                                                          */
9746 /* Returns:                                                                 */
9747 /*   Nothing.                                                               */
9748 /****************************************************************************/
9749 static __attribute__ ((noinline)) void
9750 bce_dump_enet(struct bce_softc *sc, struct mbuf *m)
9751 {
9752         struct ether_vlan_header *eh;
9753         u16 etype;
9754         int ehlen;
9755         struct ip *ip;
9756         struct tcphdr *th;
9757         struct udphdr *uh;
9758         struct arphdr *ah;
9759
9760         BCE_PRINTF(
9761             "-----------------------------"
9762             " Frame Decode "
9763             "-----------------------------\n");
9764
9765         eh = mtod(m, struct ether_vlan_header *);
9766
9767         /* Handle VLAN encapsulation if present. */
9768         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
9769                 etype = ntohs(eh->evl_proto);
9770                 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
9771         } else {
9772                 etype = ntohs(eh->evl_encap_proto);
9773                 ehlen = ETHER_HDR_LEN;
9774         }
9775
9776         /* ToDo: Add VLAN output. */
9777         BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n",
9778             eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen);
9779
9780         switch (etype) {
9781         case ETHERTYPE_IP:
9782                 ip = (struct ip *)(m->m_data + ehlen);
9783                 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, "
9784                     "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n",
9785                     ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr),
9786                     ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum));
9787
9788                 switch (ip->ip_p) {
9789                 case IPPROTO_TCP:
9790                         th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9791                         BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = "
9792                             "%d bytes, flags = 0x%b, csum = 0x%04X\n",
9793                             ntohs(th->th_dport), ntohs(th->th_sport),
9794                             (th->th_off << 2), th->th_flags,
9795                             "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST"
9796                             "\02SYN\01FIN", ntohs(th->th_sum));
9797                         break;
9798                 case IPPROTO_UDP:
9799                         uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9800                         BCE_PRINTF("-udp: dest = %d, src = %d, len = %d "
9801                             "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport),
9802                             ntohs(uh->uh_sport), ntohs(uh->uh_ulen),
9803                             ntohs(uh->uh_sum));
9804                         break;
9805                 case IPPROTO_ICMP:
9806                         BCE_PRINTF("icmp:\n");
9807                         break;
9808                 default:
9809                         BCE_PRINTF("----: Other IP protocol.\n");
9810                         }
9811                 break;
9812         case ETHERTYPE_IPV6:
9813                 BCE_PRINTF("ipv6: No decode supported.\n");
9814                 break;
9815         case ETHERTYPE_ARP:
9816                 BCE_PRINTF("-arp: ");
9817                 ah = (struct arphdr *) (m->m_data + ehlen);
9818                 switch (ntohs(ah->ar_op)) {
9819                 case ARPOP_REVREQUEST:
9820                         printf("reverse ARP request\n");
9821                         break;
9822                 case ARPOP_REVREPLY:
9823                         printf("reverse ARP reply\n");
9824                         break;
9825                 case ARPOP_REQUEST:
9826                         printf("ARP request\n");
9827                         break;
9828                 case ARPOP_REPLY:
9829                         printf("ARP reply\n");
9830                         break;
9831                 default:
9832                         printf("other ARP operation\n");
9833                 }
9834                 break;
9835         default:
9836                 BCE_PRINTF("----: Other protocol.\n");
9837         }
9838
9839         BCE_PRINTF(
9840                 "-----------------------------"
9841                 "--------------"
9842                 "-----------------------------\n");
9843 }
9844
9845
9846 /****************************************************************************/
9847 /* Prints out information about an mbuf.                                    */
9848 /*                                                                          */
9849 /* Returns:                                                                 */
9850 /*   Nothing.                                                               */
9851 /****************************************************************************/
9852 static __attribute__ ((noinline)) void
9853 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
9854 {
9855         struct mbuf *mp = m;
9856
9857         if (m == NULL) {
9858                 BCE_PRINTF("mbuf: null pointer\n");
9859                 return;
9860         }
9861
9862         while (mp) {
9863                 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, "
9864                     "m_data = %p\n", mp, mp->m_len, mp->m_flags,
9865                     "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data);
9866
9867                 if (mp->m_flags & M_PKTHDR) {
9868                         BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, "
9869                             "csum_flags = %b\n", mp->m_pkthdr.len,
9870                             mp->m_flags, M_FLAG_PRINTF,
9871                             mp->m_pkthdr.csum_flags,
9872                             "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP"
9873                             "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED"
9874                             "\12CSUM_IP_VALID\13CSUM_DATA_VALID"
9875                             "\14CSUM_PSEUDO_HDR");
9876                 }
9877
9878                 if (mp->m_flags & M_EXT) {
9879                         BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ",
9880                             mp->m_ext.ext_buf, mp->m_ext.ext_size);
9881                         switch (mp->m_ext.ext_type) {
9882                         case EXT_CLUSTER:
9883                                 printf("EXT_CLUSTER\n"); break;
9884                         case EXT_SFBUF:
9885                                 printf("EXT_SFBUF\n"); break;
9886                         case EXT_JUMBO9:
9887                                 printf("EXT_JUMBO9\n"); break;
9888                         case EXT_JUMBO16:
9889                                 printf("EXT_JUMBO16\n"); break;
9890                         case EXT_PACKET:
9891                                 printf("EXT_PACKET\n"); break;
9892                         case EXT_MBUF:
9893                                 printf("EXT_MBUF\n"); break;
9894                         case EXT_NET_DRV:
9895                                 printf("EXT_NET_DRV\n"); break;
9896                         case EXT_MOD_TYPE:
9897                                 printf("EXT_MDD_TYPE\n"); break;
9898                         case EXT_DISPOSABLE:
9899                                 printf("EXT_DISPOSABLE\n"); break;
9900                         case EXT_EXTREF:
9901                                 printf("EXT_EXTREF\n"); break;
9902                         default:
9903                                 printf("UNKNOWN\n");
9904                         }
9905                 }
9906
9907                 mp = mp->m_next;
9908         }
9909 }
9910
9911
9912 /****************************************************************************/
9913 /* Prints out the mbufs in the TX mbuf chain.                               */
9914 /*                                                                          */
9915 /* Returns:                                                                 */
9916 /*   Nothing.                                                               */
9917 /****************************************************************************/
9918 static __attribute__ ((noinline)) void
9919 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9920 {
9921         struct mbuf *m;
9922
9923         BCE_PRINTF(
9924                 "----------------------------"
9925                 "  tx mbuf data  "
9926                 "----------------------------\n");
9927
9928         for (int i = 0; i < count; i++) {
9929                 m = sc->tx_mbuf_ptr[chain_prod];
9930                 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod);
9931                 bce_dump_mbuf(sc, m);
9932                 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
9933         }
9934
9935         BCE_PRINTF(
9936                 "----------------------------"
9937                 "----------------"
9938                 "----------------------------\n");
9939 }
9940
9941
9942 /****************************************************************************/
9943 /* Prints out the mbufs in the RX mbuf chain.                               */
9944 /*                                                                          */
9945 /* Returns:                                                                 */
9946 /*   Nothing.                                                               */
9947 /****************************************************************************/
9948 static __attribute__ ((noinline)) void
9949 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9950 {
9951         struct mbuf *m;
9952
9953         BCE_PRINTF(
9954                 "----------------------------"
9955                 "  rx mbuf data  "
9956                 "----------------------------\n");
9957
9958         for (int i = 0; i < count; i++) {
9959                 m = sc->rx_mbuf_ptr[chain_prod];
9960                 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod);
9961                 bce_dump_mbuf(sc, m);
9962                 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
9963         }
9964
9965
9966         BCE_PRINTF(
9967                 "----------------------------"
9968                 "----------------"
9969                 "----------------------------\n");
9970 }
9971
9972
9973 /****************************************************************************/
9974 /* Prints out the mbufs in the mbuf page chain.                             */
9975 /*                                                                          */
9976 /* Returns:                                                                 */
9977 /*   Nothing.                                                               */
9978 /****************************************************************************/
9979 static __attribute__ ((noinline)) void
9980 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9981 {
9982         struct mbuf *m;
9983
9984         BCE_PRINTF(
9985                 "----------------------------"
9986                 "  pg mbuf data  "
9987                 "----------------------------\n");
9988
9989         for (int i = 0; i < count; i++) {
9990                 m = sc->pg_mbuf_ptr[chain_prod];
9991                 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod);
9992                 bce_dump_mbuf(sc, m);
9993                 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod));
9994         }
9995
9996
9997         BCE_PRINTF(
9998                 "----------------------------"
9999                 "----------------"
10000                 "----------------------------\n");
10001 }
10002
10003
10004 /****************************************************************************/
10005 /* Prints out a tx_bd structure.                                            */
10006 /*                                                                          */
10007 /* Returns:                                                                 */
10008 /*   Nothing.                                                               */
10009 /****************************************************************************/
10010 static __attribute__ ((noinline)) void
10011 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
10012 {
10013         int i = 0;
10014
10015         if (idx > MAX_TX_BD_ALLOC)
10016                 /* Index out of range. */
10017                 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
10018         else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
10019                 /* TX Chain page pointer. */
10020                 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
10021                     "pointer\n", idx, txbd->tx_bd_haddr_hi,
10022                     txbd->tx_bd_haddr_lo);
10023         else {
10024                 /* Normal tx_bd entry. */
10025                 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
10026                     "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = "
10027                     "0x%04X (", idx, txbd->tx_bd_haddr_hi,
10028                     txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes,
10029                     txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
10030
10031                 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) {
10032                         if (i>0)
10033                                 printf("|");
10034                         printf("CONN_FAULT");
10035                         i++;
10036                 }
10037
10038                 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) {
10039                         if (i>0)
10040                                 printf("|");
10041                         printf("TCP_UDP_CKSUM");
10042                         i++;
10043                 }
10044
10045                 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) {
10046                         if (i>0)
10047                                 printf("|");
10048                         printf("IP_CKSUM");
10049                         i++;
10050                 }
10051
10052                 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) {
10053                         if (i>0)
10054                                 printf("|");
10055                         printf("VLAN");
10056                         i++;
10057                 }
10058
10059                 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) {
10060                         if (i>0)
10061                                 printf("|");
10062                         printf("COAL_NOW");
10063                         i++;
10064                 }
10065
10066                 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) {
10067                         if (i>0)
10068                                 printf("|");
10069                         printf("DONT_GEN_CRC");
10070                         i++;
10071                 }
10072
10073                 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) {
10074                         if (i>0)
10075                                 printf("|");
10076                         printf("START");
10077                         i++;
10078                 }
10079
10080                 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) {
10081                         if (i>0)
10082                                 printf("|");
10083                         printf("END");
10084                         i++;
10085                 }
10086
10087                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) {
10088                         if (i>0)
10089                                 printf("|");
10090                         printf("LSO");
10091                         i++;
10092                 }
10093
10094                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) {
10095                         if (i>0)
10096                                 printf("|");
10097                         printf("SW_OPTION=%d", ((txbd->tx_bd_flags &
10098                             TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++;
10099                 }
10100
10101                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) {
10102                         if (i>0)
10103                                 printf("|");
10104                         printf("SW_FLAGS");
10105                         i++;
10106                 }
10107
10108                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) {
10109                         if (i>0)
10110                                 printf("|");
10111                         printf("SNAP)");
10112                 } else {
10113                         printf(")\n");
10114                 }
10115         }
10116 }
10117
10118
10119 /****************************************************************************/
10120 /* Prints out a rx_bd structure.                                            */
10121 /*                                                                          */
10122 /* Returns:                                                                 */
10123 /*   Nothing.                                                               */
10124 /****************************************************************************/
10125 static __attribute__ ((noinline)) void
10126 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
10127 {
10128         if (idx > MAX_RX_BD_ALLOC)
10129                 /* Index out of range. */
10130                 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
10131         else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
10132                 /* RX Chain page pointer. */
10133                 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
10134                     "pointer\n", idx, rxbd->rx_bd_haddr_hi,
10135                     rxbd->rx_bd_haddr_lo);
10136         else
10137                 /* Normal rx_bd entry. */
10138                 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = "
10139                     "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi,
10140                     rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len,
10141                     rxbd->rx_bd_flags);
10142 }
10143
10144
10145 /****************************************************************************/
10146 /* Prints out a rx_bd structure in the page chain.                          */
10147 /*                                                                          */
10148 /* Returns:                                                                 */
10149 /*   Nothing.                                                               */
10150 /****************************************************************************/
10151 static __attribute__ ((noinline)) void
10152 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd)
10153 {
10154         if (idx > MAX_PG_BD_ALLOC)
10155                 /* Index out of range. */
10156                 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx);
10157         else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE)
10158                 /* Page Chain page pointer. */
10159                 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n",
10160                         idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo);
10161         else
10162                 /* Normal rx_bd entry. */
10163                 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, "
10164                         "flags = 0x%08X\n", idx,
10165                         pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo,
10166                         pgbd->rx_bd_len, pgbd->rx_bd_flags);
10167 }
10168
10169
10170 /****************************************************************************/
10171 /* Prints out a l2_fhdr structure.                                          */
10172 /*                                                                          */
10173 /* Returns:                                                                 */
10174 /*   Nothing.                                                               */
10175 /****************************************************************************/
10176 static __attribute__ ((noinline)) void
10177 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
10178 {
10179         BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, "
10180                 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, "
10181                 "tcp_udp_xsum = 0x%04X\n", idx,
10182                 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB,
10183                 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
10184                 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
10185 }
10186
10187
10188 /****************************************************************************/
10189 /* Prints out context memory info.  (Only useful for CID 0 to 16.)          */
10190 /*                                                                          */
10191 /* Returns:                                                                 */
10192 /*   Nothing.                                                               */
10193 /****************************************************************************/
10194 static __attribute__ ((noinline)) void
10195 bce_dump_ctx(struct bce_softc *sc, u16 cid)
10196 {
10197         if (cid > TX_CID) {
10198                 BCE_PRINTF(" Unknown CID\n");
10199                 return;
10200         }
10201
10202         BCE_PRINTF(
10203             "----------------------------"
10204             "    CTX Data    "
10205             "----------------------------\n");
10206
10207         BCE_PRINTF("     0x%04X - (CID) Context ID\n", cid);
10208
10209         if (cid == RX_CID) {
10210                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx "
10211                    "producer index\n",
10212                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX));
10213                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host "
10214                     "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
10215                     BCE_L2CTX_RX_HOST_BSEQ));
10216                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n",
10217                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ));
10218                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer "
10219                     "descriptor address\n",
10220                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI));
10221                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer "
10222                     "descriptor address\n",
10223                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO));
10224                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer "
10225                     "index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10226                     BCE_L2CTX_RX_NX_BDIDX));
10227                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page "
10228                     "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10229                     BCE_L2CTX_RX_HOST_PG_BDIDX));
10230                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page "
10231                     "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid),
10232                     BCE_L2CTX_RX_PG_BUF_SIZE));
10233                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page "
10234                     "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
10235                     BCE_L2CTX_RX_NX_PG_BDHADDR_HI));
10236                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page "
10237                     "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
10238                     BCE_L2CTX_RX_NX_PG_BDHADDR_LO));
10239                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page "
10240                     "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10241                     BCE_L2CTX_RX_NX_PG_BDIDX));
10242         } else if (cid == TX_CID) {
10243                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
10244                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n",
10245                             CTX_RD(sc, GET_CID_ADDR(cid),
10246                             BCE_L2CTX_TX_TYPE_XI));
10247                         BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx "
10248                             "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid),
10249                             BCE_L2CTX_TX_CMD_TYPE_XI));
10250                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) "
10251                             "h/w buffer descriptor address\n",
10252                             CTX_RD(sc, GET_CID_ADDR(cid),
10253                             BCE_L2CTX_TX_TBDR_BHADDR_HI_XI));
10254                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) "
10255                             "h/w buffer descriptor address\n",
10256                             CTX_RD(sc, GET_CID_ADDR(cid),
10257                             BCE_L2CTX_TX_TBDR_BHADDR_LO_XI));
10258                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) "
10259                             "host producer index\n",
10260                             CTX_RD(sc, GET_CID_ADDR(cid),
10261                             BCE_L2CTX_TX_HOST_BIDX_XI));
10262                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) "
10263                             "host byte sequence\n",
10264                             CTX_RD(sc, GET_CID_ADDR(cid),
10265                             BCE_L2CTX_TX_HOST_BSEQ_XI));
10266                 } else {
10267                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n",
10268                             CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE));
10269                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n",
10270                             CTX_RD(sc, GET_CID_ADDR(cid),
10271                             BCE_L2CTX_TX_CMD_TYPE));
10272                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) "
10273                             "h/w buffer descriptor address\n",
10274                             CTX_RD(sc, GET_CID_ADDR(cid),
10275                             BCE_L2CTX_TX_TBDR_BHADDR_HI));
10276                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) "
10277                             "h/w buffer descriptor address\n",
10278                             CTX_RD(sc, GET_CID_ADDR(cid),
10279                             BCE_L2CTX_TX_TBDR_BHADDR_LO));
10280                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host "
10281                             "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10282                             BCE_L2CTX_TX_HOST_BIDX));
10283                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte "
10284                             "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
10285                             BCE_L2CTX_TX_HOST_BSEQ));
10286                 }
10287         }
10288
10289         BCE_PRINTF(
10290            "----------------------------"
10291            "    Raw CTX     "
10292            "----------------------------\n");
10293
10294         for (int i = 0x0; i < 0x300; i += 0x10) {
10295                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
10296                    CTX_RD(sc, GET_CID_ADDR(cid), i),
10297                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4),
10298                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8),
10299                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc));
10300         }
10301
10302
10303         BCE_PRINTF(
10304            "----------------------------"
10305            "----------------"
10306            "----------------------------\n");
10307 }
10308
10309
10310 /****************************************************************************/
10311 /* Prints out the FTQ data.                                                 */
10312 /*                                                                          */
10313 /* Returns:                                                                */
10314 /*   Nothing.                                                               */
10315 /****************************************************************************/
10316 static __attribute__ ((noinline)) void
10317 bce_dump_ftqs(struct bce_softc *sc)
10318 {
10319         u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val;
10320
10321         BCE_PRINTF(
10322             "----------------------------"
10323             "    FTQ Data    "
10324             "----------------------------\n");
10325
10326         BCE_PRINTF("   FTQ    Command    Control   Depth_Now  "
10327             "Max_Depth  Valid_Cnt \n");
10328         BCE_PRINTF(" ------- ---------- ---------- ---------- "
10329             "---------- ----------\n");
10330
10331         /* Setup the generic statistic counters for the FTQ valid count. */
10332         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) |
10333             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT  << 16) |
10334             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT   <<  8) |
10335             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT);
10336         REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10337
10338         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT  << 24) |
10339             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT  << 16) |
10340             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT <<  8) |
10341             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT);
10342         REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val);
10343
10344         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT  << 24) |
10345             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT  << 16) |
10346             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT   <<  8) |
10347             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT);
10348         REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val);
10349
10350         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT   << 24) |
10351             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT  << 16) |
10352             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT  <<  8) |
10353             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT);
10354         REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val);
10355
10356         /* Input queue to the Receive Lookup state machine */
10357         cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD);
10358         ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL);
10359         cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22;
10360         max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12;
10361         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
10362         BCE_PRINTF(" RLUP    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10363             cmd, ctl, cur_depth, max_depth, valid_cnt);
10364
10365         /* Input queue to the Receive Processor */
10366         cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD);
10367         ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL);
10368         cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22;
10369         max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12;
10370         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
10371         BCE_PRINTF(" RXP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10372             cmd, ctl, cur_depth, max_depth, valid_cnt);
10373
10374         /* Input queue to the Recevie Processor */
10375         cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD);
10376         ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL);
10377         cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22;
10378         max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12;
10379         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
10380         BCE_PRINTF(" RXPC    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10381             cmd, ctl, cur_depth, max_depth, valid_cnt);
10382
10383         /* Input queue to the Receive Virtual to Physical state machine */
10384         cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD);
10385         ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL);
10386         cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22;
10387         max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12;
10388         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
10389         BCE_PRINTF(" RV2PP   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10390             cmd, ctl, cur_depth, max_depth, valid_cnt);
10391
10392         /* Input queue to the Recevie Virtual to Physical state machine */
10393         cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD);
10394         ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL);
10395         cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22;
10396         max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12;
10397         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4);
10398         BCE_PRINTF(" RV2PM   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10399             cmd, ctl, cur_depth, max_depth, valid_cnt);
10400
10401         /* Input queue to the Receive Virtual to Physical state machine */
10402         cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD);
10403         ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL);
10404         cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22;
10405         max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12;
10406         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5);
10407         BCE_PRINTF(" RV2PT   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10408             cmd, ctl, cur_depth, max_depth, valid_cnt);
10409
10410         /* Input queue to the Receive DMA state machine */
10411         cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD);
10412         ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL);
10413         cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22;
10414         max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12;
10415         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6);
10416         BCE_PRINTF(" RDMA    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10417             cmd, ctl, cur_depth, max_depth, valid_cnt);
10418
10419         /* Input queue to the Transmit Scheduler state machine */
10420         cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD);
10421         ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL);
10422         cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22;
10423         max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12;
10424         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7);
10425         BCE_PRINTF(" TSCH    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10426             cmd, ctl, cur_depth, max_depth, valid_cnt);
10427
10428         /* Input queue to the Transmit Buffer Descriptor state machine */
10429         cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD);
10430         ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL);
10431         cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22;
10432         max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12;
10433         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8);
10434         BCE_PRINTF(" TBDR    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10435             cmd, ctl, cur_depth, max_depth, valid_cnt);
10436
10437         /* Input queue to the Transmit Processor */
10438         cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD);
10439         ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL);
10440         cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22;
10441         max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12;
10442         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9);
10443         BCE_PRINTF(" TXP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10444             cmd, ctl, cur_depth, max_depth, valid_cnt);
10445
10446         /* Input queue to the Transmit DMA state machine */
10447         cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD);
10448         ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL);
10449         cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22;
10450         max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12;
10451         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10);
10452         BCE_PRINTF(" TDMA    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10453             cmd, ctl, cur_depth, max_depth, valid_cnt);
10454
10455         /* Input queue to the Transmit Patch-Up Processor */
10456         cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD);
10457         ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL);
10458         cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22;
10459         max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12;
10460         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11);
10461         BCE_PRINTF(" TPAT    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10462             cmd, ctl, cur_depth, max_depth, valid_cnt);
10463
10464         /* Input queue to the Transmit Assembler state machine */
10465         cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD);
10466         ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL);
10467         cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22;
10468         max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12;
10469         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12);
10470         BCE_PRINTF(" TAS     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10471             cmd, ctl, cur_depth, max_depth, valid_cnt);
10472
10473         /* Input queue to the Completion Processor */
10474         cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD);
10475         ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL);
10476         cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22;
10477         max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12;
10478         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13);
10479         BCE_PRINTF(" COMX    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10480             cmd, ctl, cur_depth, max_depth, valid_cnt);
10481
10482         /* Input queue to the Completion Processor */
10483         cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD);
10484         ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL);
10485         cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22;
10486         max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12;
10487         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14);
10488         BCE_PRINTF(" COMT    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10489             cmd, ctl, cur_depth, max_depth, valid_cnt);
10490
10491         /* Input queue to the Completion Processor */
10492         cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD);
10493         ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL);
10494         cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22;
10495         max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12;
10496         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15);
10497         BCE_PRINTF(" COMX    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10498             cmd, ctl, cur_depth, max_depth, valid_cnt);
10499
10500         /* Setup the generic statistic counters for the FTQ valid count. */
10501         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT  << 16) |
10502             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT  <<  8) |
10503             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT);
10504
10505         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
10506                 val = val |
10507                     (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI <<
10508                      24);
10509         REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10510
10511         /* Input queue to the Management Control Processor */
10512         cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD);
10513         ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL);
10514         cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22;
10515         max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12;
10516         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
10517         BCE_PRINTF(" MCP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10518             cmd, ctl, cur_depth, max_depth, valid_cnt);
10519
10520         /* Input queue to the Command Processor */
10521         cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD);
10522         ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL);
10523         cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22;
10524         max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12;
10525         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
10526         BCE_PRINTF(" CP      0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10527             cmd, ctl, cur_depth, max_depth, valid_cnt);
10528
10529         /* Input queue to the Completion Scheduler state machine */
10530         cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD);
10531         ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL);
10532         cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22;
10533         max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12;
10534         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
10535         BCE_PRINTF(" CS      0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10536             cmd, ctl, cur_depth, max_depth, valid_cnt);
10537
10538         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
10539                 /* Input queue to the RV2P Command Scheduler */
10540                 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD);
10541                 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL);
10542                 cur_depth = (ctl & 0xFFC00000) >> 22;
10543                 max_depth = (ctl & 0x003FF000) >> 12;
10544                 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
10545                 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10546                     cmd, ctl, cur_depth, max_depth, valid_cnt);
10547         }
10548
10549         BCE_PRINTF(
10550             "----------------------------"
10551             "----------------"
10552             "----------------------------\n");
10553 }
10554
10555
10556 /****************************************************************************/
10557 /* Prints out the TX chain.                                                 */
10558 /*                                                                          */
10559 /* Returns:                                                                 */
10560 /*   Nothing.                                                               */
10561 /****************************************************************************/
10562 static __attribute__ ((noinline)) void
10563 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count)
10564 {
10565         struct tx_bd *txbd;
10566
10567         /* First some info about the tx_bd chain structure. */
10568         BCE_PRINTF(
10569             "----------------------------"
10570             "  tx_bd  chain  "
10571             "----------------------------\n");
10572
10573         BCE_PRINTF("page size      = 0x%08X, tx chain pages        = 0x%08X\n",
10574             (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages);
10575         BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n",
10576             (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE);
10577         BCE_PRINTF("total tx_bd    = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC);
10578
10579         BCE_PRINTF(
10580             "----------------------------"
10581             "   tx_bd data   "
10582             "----------------------------\n");
10583
10584         /* Now print out a decoded list of TX buffer descriptors. */
10585         for (int i = 0; i < count; i++) {
10586                 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
10587                 bce_dump_txbd(sc, tx_prod, txbd);
10588                 tx_prod++;
10589         }
10590
10591         BCE_PRINTF(
10592             "----------------------------"
10593             "----------------"
10594             "----------------------------\n");
10595 }
10596
10597
10598 /****************************************************************************/
10599 /* Prints out the RX chain.                                                 */
10600 /*                                                                          */
10601 /* Returns:                                                                 */
10602 /*   Nothing.                                                               */
10603 /****************************************************************************/
10604 static __attribute__ ((noinline)) void
10605 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count)
10606 {
10607         struct rx_bd *rxbd;
10608
10609         /* First some info about the rx_bd chain structure. */
10610         BCE_PRINTF(
10611             "----------------------------"
10612             "  rx_bd  chain  "
10613             "----------------------------\n");
10614
10615         BCE_PRINTF("page size      = 0x%08X, rx chain pages        = 0x%08X\n",
10616             (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages);
10617
10618         BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
10619             (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE);
10620
10621         BCE_PRINTF("total rx_bd    = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC);
10622
10623         BCE_PRINTF(
10624             "----------------------------"
10625             "   rx_bd data   "
10626             "----------------------------\n");
10627
10628         /* Now print out the rx_bd's themselves. */
10629         for (int i = 0; i < count; i++) {
10630                 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
10631                 bce_dump_rxbd(sc, rx_prod, rxbd);
10632                 rx_prod = RX_CHAIN_IDX(rx_prod + 1);
10633         }
10634
10635         BCE_PRINTF(
10636             "----------------------------"
10637             "----------------"
10638             "----------------------------\n");
10639 }
10640
10641
10642 /****************************************************************************/
10643 /* Prints out the page chain.                                               */
10644 /*                                                                          */
10645 /* Returns:                                                                 */
10646 /*   Nothing.                                                               */
10647 /****************************************************************************/
10648 static __attribute__ ((noinline)) void
10649 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count)
10650 {
10651         struct rx_bd *pgbd;
10652
10653         /* First some info about the page chain structure. */
10654         BCE_PRINTF(
10655             "----------------------------"
10656             "   page chain   "
10657             "----------------------------\n");
10658
10659         BCE_PRINTF("page size      = 0x%08X, pg chain pages        = 0x%08X\n",
10660             (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages);
10661
10662         BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
10663             (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE);
10664
10665         BCE_PRINTF("total pg_bd             = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC);
10666
10667         BCE_PRINTF(
10668             "----------------------------"
10669             "   page data    "
10670             "----------------------------\n");
10671
10672         /* Now print out the rx_bd's themselves. */
10673         for (int i = 0; i < count; i++) {
10674                 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)];
10675                 bce_dump_pgbd(sc, pg_prod, pgbd);
10676                 pg_prod = PG_CHAIN_IDX(pg_prod + 1);
10677         }
10678
10679         BCE_PRINTF(
10680             "----------------------------"
10681             "----------------"
10682             "----------------------------\n");
10683 }
10684
10685
10686 #define BCE_PRINT_RX_CONS(arg)                                          \
10687 if (sblk->status_rx_quick_consumer_index##arg)                          \
10688         BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n",      \
10689             sblk->status_rx_quick_consumer_index##arg, (u16)            \
10690             RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg),    \
10691             arg);
10692
10693
10694 #define BCE_PRINT_TX_CONS(arg)                                          \
10695 if (sblk->status_tx_quick_consumer_index##arg)                          \
10696         BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n",      \
10697             sblk->status_tx_quick_consumer_index##arg, (u16)            \
10698             TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg),    \
10699             arg);
10700
10701 /****************************************************************************/
10702 /* Prints out the status block from host memory.                            */
10703 /*                                                                          */
10704 /* Returns:                                                                 */
10705 /*   Nothing.                                                               */
10706 /****************************************************************************/
10707 static __attribute__ ((noinline)) void
10708 bce_dump_status_block(struct bce_softc *sc)
10709 {
10710         struct status_block *sblk;
10711
10712         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
10713
10714         sblk = sc->status_block;
10715
10716         BCE_PRINTF(
10717             "----------------------------"
10718             "  Status Block  "
10719             "----------------------------\n");
10720
10721         /* Theses indices are used for normal L2 drivers. */
10722         BCE_PRINTF("    0x%08X - attn_bits\n",
10723             sblk->status_attn_bits);
10724
10725         BCE_PRINTF("    0x%08X - attn_bits_ack\n",
10726             sblk->status_attn_bits_ack);
10727
10728         BCE_PRINT_RX_CONS(0);
10729         BCE_PRINT_TX_CONS(0)
10730
10731         BCE_PRINTF("        0x%04X - status_idx\n", sblk->status_idx);
10732
10733         /* Theses indices are not used for normal L2 drivers. */
10734         BCE_PRINT_RX_CONS(1);   BCE_PRINT_RX_CONS(2);   BCE_PRINT_RX_CONS(3);
10735         BCE_PRINT_RX_CONS(4);   BCE_PRINT_RX_CONS(5);   BCE_PRINT_RX_CONS(6);
10736         BCE_PRINT_RX_CONS(7);   BCE_PRINT_RX_CONS(8);   BCE_PRINT_RX_CONS(9);
10737         BCE_PRINT_RX_CONS(10);  BCE_PRINT_RX_CONS(11);  BCE_PRINT_RX_CONS(12);
10738         BCE_PRINT_RX_CONS(13);  BCE_PRINT_RX_CONS(14);  BCE_PRINT_RX_CONS(15);
10739
10740         BCE_PRINT_TX_CONS(1);   BCE_PRINT_TX_CONS(2);   BCE_PRINT_TX_CONS(3);
10741
10742         if (sblk->status_completion_producer_index ||
10743             sblk->status_cmd_consumer_index)
10744                 BCE_PRINTF("com_prod  = 0x%08X, cmd_cons      = 0x%08X\n",
10745                     sblk->status_completion_producer_index,
10746                     sblk->status_cmd_consumer_index);
10747
10748         BCE_PRINTF(
10749             "----------------------------"
10750             "----------------"
10751             "----------------------------\n");
10752 }
10753
10754
10755 #define BCE_PRINT_64BIT_STAT(arg)                               \
10756 if (sblk->arg##_lo || sblk->arg##_hi)                           \
10757         BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi,        \
10758             sblk->arg##_lo, #arg);
10759
10760 #define BCE_PRINT_32BIT_STAT(arg)                               \
10761 if (sblk->arg)                                                  \
10762         BCE_PRINTF("         0x%08X : %s\n",                    \
10763             sblk->arg, #arg);
10764
10765 /****************************************************************************/
10766 /* Prints out the statistics block from host memory.                        */
10767 /*                                                                          */
10768 /* Returns:                                                                 */
10769 /*   Nothing.                                                               */
10770 /****************************************************************************/
10771 static __attribute__ ((noinline)) void
10772 bce_dump_stats_block(struct bce_softc *sc)
10773 {
10774         struct statistics_block *sblk;
10775
10776         bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD);
10777
10778         sblk = sc->stats_block;
10779
10780         BCE_PRINTF(
10781             "---------------"
10782             " Stats Block  (All Stats Not Shown Are 0) "
10783             "---------------\n");
10784
10785         BCE_PRINT_64BIT_STAT(stat_IfHCInOctets);
10786         BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets);
10787         BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets);
10788         BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets);
10789         BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts);
10790         BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts);
10791         BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts);
10792         BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts);
10793         BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts);
10794         BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts);
10795         BCE_PRINT_32BIT_STAT(
10796             stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
10797         BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors);
10798         BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors);
10799         BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors);
10800         BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames);
10801         BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames);
10802         BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions);
10803         BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions);
10804         BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions);
10805         BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions);
10806         BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments);
10807         BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers);
10808         BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts);
10809         BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts);
10810         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets);
10811         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets);
10812         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets);
10813         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets);
10814         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets);
10815         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets);
10816         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets);
10817         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets);
10818         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets);
10819         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets);
10820         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets);
10821         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets);
10822         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets);
10823         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets);
10824         BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived);
10825         BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived);
10826         BCE_PRINT_32BIT_STAT(stat_OutXonSent);
10827         BCE_PRINT_32BIT_STAT(stat_OutXoffSent);
10828         BCE_PRINT_32BIT_STAT(stat_FlowControlDone);
10829         BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived);
10830         BCE_PRINT_32BIT_STAT(stat_XoffStateEntered);
10831         BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards);
10832         BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards);
10833         BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards);
10834         BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards);
10835         BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit);
10836         BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards);
10837         BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards);
10838         BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards);
10839         BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit);
10840
10841         BCE_PRINTF(
10842             "----------------------------"
10843             "----------------"
10844             "----------------------------\n");
10845 }
10846
10847
10848 /****************************************************************************/
10849 /* Prints out a summary of the driver state.                                */
10850 /*                                                                          */
10851 /* Returns:                                                                 */
10852 /*   Nothing.                                                               */
10853 /****************************************************************************/
10854 static __attribute__ ((noinline)) void
10855 bce_dump_driver_state(struct bce_softc *sc)
10856 {
10857         u32 val_hi, val_lo;
10858
10859         BCE_PRINTF(
10860             "-----------------------------"
10861             " Driver State "
10862             "-----------------------------\n");
10863
10864         val_hi = BCE_ADDR_HI(sc);
10865         val_lo = BCE_ADDR_LO(sc);
10866         BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual "
10867             "address\n", val_hi, val_lo);
10868
10869         val_hi = BCE_ADDR_HI(sc->bce_vhandle);
10870         val_lo = BCE_ADDR_LO(sc->bce_vhandle);
10871         BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual "
10872             "address\n", val_hi, val_lo);
10873
10874         val_hi = BCE_ADDR_HI(sc->status_block);
10875         val_lo = BCE_ADDR_LO(sc->status_block);
10876         BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block "
10877             "virtual address\n",        val_hi, val_lo);
10878
10879         val_hi = BCE_ADDR_HI(sc->stats_block);
10880         val_lo = BCE_ADDR_LO(sc->stats_block);
10881         BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block "
10882             "virtual address\n", val_hi, val_lo);
10883
10884         val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
10885         val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
10886         BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
10887             "virtual adddress\n", val_hi, val_lo);
10888
10889         val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
10890         val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
10891         BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
10892             "virtual address\n", val_hi, val_lo);
10893
10894         if (bce_hdr_split == TRUE) {
10895                 val_hi = BCE_ADDR_HI(sc->pg_bd_chain);
10896                 val_lo = BCE_ADDR_LO(sc->pg_bd_chain);
10897                 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain "
10898                     "virtual address\n", val_hi, val_lo);
10899         }
10900
10901         val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
10902         val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
10903         BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
10904             "virtual address\n",        val_hi, val_lo);
10905
10906         val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
10907         val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
10908         BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
10909             "virtual address\n", val_hi, val_lo);
10910
10911         if (bce_hdr_split == TRUE) {
10912                 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr);
10913                 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr);
10914                 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain "
10915                     "virtual address\n", val_hi, val_lo);
10916         }
10917
10918         BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) "
10919             "h/w intrs\n",
10920             (long long unsigned int) sc->interrupts_generated);
10921
10922         BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) "
10923             "rx interrupts handled\n",
10924             (long long unsigned int) sc->interrupts_rx);
10925
10926         BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) "
10927             "tx interrupts handled\n",
10928             (long long unsigned int) sc->interrupts_tx);
10929
10930         BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) "
10931             "phy interrupts handled\n",
10932             (long long unsigned int) sc->phy_interrupts);
10933
10934         BCE_PRINTF("         0x%08X - (sc->last_status_idx) "
10935             "status block index\n", sc->last_status_idx);
10936
10937         BCE_PRINTF("     0x%04X(0x%04X) - (sc->tx_prod) tx producer "
10938             "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod));
10939
10940         BCE_PRINTF("     0x%04X(0x%04X) - (sc->tx_cons) tx consumer "
10941             "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons));
10942
10943         BCE_PRINTF("         0x%08X - (sc->tx_prod_bseq) tx producer "
10944             "byte seq index\n", sc->tx_prod_bseq);
10945
10946         BCE_PRINTF("         0x%08X - (sc->debug_tx_mbuf_alloc) tx "
10947             "mbufs allocated\n", sc->debug_tx_mbuf_alloc);
10948
10949         BCE_PRINTF("         0x%08X - (sc->used_tx_bd) used "
10950             "tx_bd's\n", sc->used_tx_bd);
10951
10952         BCE_PRINTF("      0x%04X/0x%04X - (sc->tx_hi_watermark)/"
10953             "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd);
10954
10955         BCE_PRINTF("     0x%04X(0x%04X) - (sc->rx_prod) rx producer "
10956             "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod));
10957
10958         BCE_PRINTF("     0x%04X(0x%04X) - (sc->rx_cons) rx consumer "
10959             "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons));
10960
10961         BCE_PRINTF("         0x%08X - (sc->rx_prod_bseq) rx producer "
10962             "byte seq index\n", sc->rx_prod_bseq);
10963
10964         BCE_PRINTF("      0x%04X/0x%04X - (sc->rx_low_watermark)/"
10965                    "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd);
10966
10967         BCE_PRINTF("         0x%08X - (sc->debug_rx_mbuf_alloc) rx "
10968             "mbufs allocated\n", sc->debug_rx_mbuf_alloc);
10969
10970         BCE_PRINTF("         0x%08X - (sc->free_rx_bd) free "
10971             "rx_bd's\n", sc->free_rx_bd);
10972
10973         if (bce_hdr_split == TRUE) {
10974                 BCE_PRINTF("     0x%04X(0x%04X) - (sc->pg_prod) page producer "
10975                     "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod));
10976
10977                 BCE_PRINTF("     0x%04X(0x%04X) - (sc->pg_cons) page consumer "
10978                     "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons));
10979
10980                 BCE_PRINTF("         0x%08X - (sc->debug_pg_mbuf_alloc) page "
10981                     "mbufs allocated\n", sc->debug_pg_mbuf_alloc);
10982         }
10983
10984         BCE_PRINTF("         0x%08X - (sc->free_pg_bd) free page "
10985             "rx_bd's\n", sc->free_pg_bd);
10986
10987         BCE_PRINTF("      0x%04X/0x%04X - (sc->pg_low_watermark)/"
10988             "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd);
10989
10990         BCE_PRINTF("         0x%08X - (sc->mbuf_alloc_failed_count) "
10991             "mbuf alloc failures\n", sc->mbuf_alloc_failed_count);
10992
10993         BCE_PRINTF("         0x%08X - (sc->bce_flags) "
10994             "bce mac flags\n", sc->bce_flags);
10995
10996         BCE_PRINTF("         0x%08X - (sc->bce_phy_flags) "
10997             "bce phy flags\n", sc->bce_phy_flags);
10998
10999         BCE_PRINTF(
11000             "----------------------------"
11001             "----------------"
11002             "----------------------------\n");
11003 }
11004
11005
11006 /****************************************************************************/
11007 /* Prints out the hardware state through a summary of important register,   */
11008 /* followed by a complete register dump.                                    */
11009 /*                                                                          */
11010 /* Returns:                                                                 */
11011 /*   Nothing.                                                               */
11012 /****************************************************************************/
11013 static __attribute__ ((noinline)) void
11014 bce_dump_hw_state(struct bce_softc *sc)
11015 {
11016         u32 val;
11017
11018         BCE_PRINTF(
11019             "----------------------------"
11020             " Hardware State "
11021             "----------------------------\n");
11022
11023         BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
11024
11025         val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
11026         BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n",
11027             val, BCE_MISC_ENABLE_STATUS_BITS);
11028
11029         val = REG_RD(sc, BCE_DMA_STATUS);
11030         BCE_PRINTF("0x%08X - (0x%06X) dma_status\n",
11031             val, BCE_DMA_STATUS);
11032
11033         val = REG_RD(sc, BCE_CTX_STATUS);
11034         BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n",
11035             val, BCE_CTX_STATUS);
11036
11037         val = REG_RD(sc, BCE_EMAC_STATUS);
11038         BCE_PRINTF("0x%08X - (0x%06X) emac_status\n",
11039             val, BCE_EMAC_STATUS);
11040
11041         val = REG_RD(sc, BCE_RPM_STATUS);
11042         BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n",
11043             val, BCE_RPM_STATUS);
11044
11045         /* ToDo: Create a #define for this constant. */
11046         val = REG_RD(sc, 0x2004);
11047         BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n",
11048             val, 0x2004);
11049
11050         val = REG_RD(sc, BCE_RV2P_STATUS);
11051         BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n",
11052             val, BCE_RV2P_STATUS);
11053
11054         /* ToDo: Create a #define for this constant. */
11055         val = REG_RD(sc, 0x2c04);
11056         BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n",
11057             val, 0x2c04);
11058
11059         val = REG_RD(sc, BCE_TBDR_STATUS);
11060         BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n",
11061             val, BCE_TBDR_STATUS);
11062
11063         val = REG_RD(sc, BCE_TDMA_STATUS);
11064         BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n",
11065             val, BCE_TDMA_STATUS);
11066
11067         val = REG_RD(sc, BCE_HC_STATUS);
11068         BCE_PRINTF("0x%08X - (0x%06X) hc_status\n",
11069             val, BCE_HC_STATUS);
11070
11071         val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
11072         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
11073             val, BCE_TXP_CPU_STATE);
11074
11075         val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11076         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
11077             val, BCE_TPAT_CPU_STATE);
11078
11079         val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11080         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
11081             val, BCE_RXP_CPU_STATE);
11082
11083         val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11084         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
11085             val, BCE_COM_CPU_STATE);
11086
11087         val = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
11088         BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n",
11089             val, BCE_MCP_CPU_STATE);
11090
11091         val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11092         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
11093             val, BCE_CP_CPU_STATE);
11094
11095         BCE_PRINTF(
11096             "----------------------------"
11097             "----------------"
11098             "----------------------------\n");
11099
11100         BCE_PRINTF(
11101             "----------------------------"
11102             " Register  Dump "
11103             "----------------------------\n");
11104
11105         for (int i = 0x400; i < 0x8000; i += 0x10) {
11106                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11107                     i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
11108                     REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
11109         }
11110
11111         BCE_PRINTF(
11112             "----------------------------"
11113             "----------------"
11114             "----------------------------\n");
11115 }
11116
11117
11118 /****************************************************************************/
11119 /* Prints out the contentst of shared memory which is used for host driver  */
11120 /* to bootcode firmware communication.                                      */
11121 /*                                                                          */
11122 /* Returns:                                                                 */
11123 /*   Nothing.                                                               */
11124 /****************************************************************************/
11125 static __attribute__ ((noinline)) void
11126 bce_dump_shmem_state(struct bce_softc *sc)
11127 {
11128         BCE_PRINTF(
11129             "----------------------------"
11130             " Hardware State "
11131             "----------------------------\n");
11132
11133         BCE_PRINTF("0x%08X - Shared memory base address\n",
11134             sc->bce_shmem_base);
11135         BCE_PRINTF("%s - bootcode version\n",
11136             sc->bce_bc_ver);
11137
11138         BCE_PRINTF(
11139             "----------------------------"
11140             "   Shared Mem   "
11141             "----------------------------\n");
11142
11143         for (int i = 0x0; i < 0x200; i += 0x10) {
11144                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11145                     i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4),
11146                     bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC));
11147         }
11148
11149         BCE_PRINTF(
11150             "----------------------------"
11151             "----------------"
11152             "----------------------------\n");
11153 }
11154
11155
11156 /****************************************************************************/
11157 /* Prints out the mailbox queue registers.                                  */
11158 /*                                                                          */
11159 /* Returns:                                                                 */
11160 /*   Nothing.                                                               */
11161 /****************************************************************************/
11162 static __attribute__ ((noinline)) void
11163 bce_dump_mq_regs(struct bce_softc *sc)
11164 {
11165         BCE_PRINTF(
11166             "----------------------------"
11167             "    MQ Regs     "
11168             "----------------------------\n");
11169
11170         BCE_PRINTF(
11171             "----------------------------"
11172             "----------------"
11173             "----------------------------\n");
11174
11175         for (int i = 0x3c00; i < 0x4000; i += 0x10) {
11176                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11177                     i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
11178                     REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
11179         }
11180
11181         BCE_PRINTF(
11182             "----------------------------"
11183             "----------------"
11184             "----------------------------\n");
11185 }
11186
11187
11188 /****************************************************************************/
11189 /* Prints out the bootcode state.                                           */
11190 /*                                                                          */
11191 /* Returns:                                                                 */
11192 /*   Nothing.                                                               */
11193 /****************************************************************************/
11194 static __attribute__ ((noinline)) void
11195 bce_dump_bc_state(struct bce_softc *sc)
11196 {
11197         u32 val;
11198
11199         BCE_PRINTF(
11200             "----------------------------"
11201             " Bootcode State "
11202             "----------------------------\n");
11203
11204         BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
11205
11206         val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE);
11207         BCE_PRINTF("0x%08X - (0x%06X) reset_type\n",
11208             val, BCE_BC_RESET_TYPE);
11209
11210         val = bce_shmem_rd(sc, BCE_BC_STATE);
11211         BCE_PRINTF("0x%08X - (0x%06X) state\n",
11212             val, BCE_BC_STATE);
11213
11214         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
11215         BCE_PRINTF("0x%08X - (0x%06X) condition\n",
11216             val, BCE_BC_STATE_CONDITION);
11217
11218         val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD);
11219         BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n",
11220             val, BCE_BC_STATE_DEBUG_CMD);
11221
11222         BCE_PRINTF(
11223             "----------------------------"
11224             "----------------"
11225             "----------------------------\n");
11226 }
11227
11228
11229 /****************************************************************************/
11230 /* Prints out the TXP processor state.                                      */
11231 /*                                                                          */
11232 /* Returns:                                                                 */
11233 /*   Nothing.                                                               */
11234 /****************************************************************************/
11235 static __attribute__ ((noinline)) void
11236 bce_dump_txp_state(struct bce_softc *sc, int regs)
11237 {
11238         u32 val;
11239         u32 fw_version[3];
11240
11241         BCE_PRINTF(
11242             "----------------------------"
11243             "   TXP  State   "
11244             "----------------------------\n");
11245
11246         for (int i = 0; i < 3; i++)
11247                 fw_version[i] = htonl(REG_RD_IND(sc,
11248                     (BCE_TXP_SCRATCH + 0x10 + i * 4)));
11249         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11250
11251         val = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
11252         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n",
11253             val, BCE_TXP_CPU_MODE);
11254
11255         val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
11256         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
11257             val, BCE_TXP_CPU_STATE);
11258
11259         val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
11260         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n",
11261             val, BCE_TXP_CPU_EVENT_MASK);
11262
11263         if (regs) {
11264                 BCE_PRINTF(
11265                     "----------------------------"
11266                     " Register  Dump "
11267                     "----------------------------\n");
11268
11269                 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
11270                         /* Skip the big blank spaces */
11271                         if (i < 0x454000 && i > 0x5ffff)
11272                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11273                                     "0x%08X 0x%08X\n", i,
11274                                     REG_RD_IND(sc, i),
11275                                     REG_RD_IND(sc, i + 0x4),
11276                                     REG_RD_IND(sc, i + 0x8),
11277                                     REG_RD_IND(sc, i + 0xC));
11278                 }
11279         }
11280
11281         BCE_PRINTF(
11282             "----------------------------"
11283             "----------------"
11284             "----------------------------\n");
11285 }
11286
11287
11288 /****************************************************************************/
11289 /* Prints out the RXP processor state.                                      */
11290 /*                                                                          */
11291 /* Returns:                                                                 */
11292 /*   Nothing.                                                               */
11293 /****************************************************************************/
11294 static __attribute__ ((noinline)) void
11295 bce_dump_rxp_state(struct bce_softc *sc, int regs)
11296 {
11297         u32 val;
11298         u32 fw_version[3];
11299
11300         BCE_PRINTF(
11301             "----------------------------"
11302             "   RXP  State   "
11303             "----------------------------\n");
11304
11305         for (int i = 0; i < 3; i++)
11306                 fw_version[i] = htonl(REG_RD_IND(sc,
11307                     (BCE_RXP_SCRATCH + 0x10 + i * 4)));
11308
11309         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11310
11311         val = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
11312         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n",
11313             val, BCE_RXP_CPU_MODE);
11314
11315         val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11316         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
11317             val, BCE_RXP_CPU_STATE);
11318
11319         val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
11320         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n",
11321             val, BCE_RXP_CPU_EVENT_MASK);
11322
11323         if (regs) {
11324                 BCE_PRINTF(
11325                     "----------------------------"
11326                     " Register  Dump "
11327                     "----------------------------\n");
11328
11329                 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
11330                         /* Skip the big blank sapces */
11331                         if (i < 0xc5400 && i > 0xdffff)
11332                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11333                                     "0x%08X 0x%08X\n", i,
11334                                     REG_RD_IND(sc, i),
11335                                     REG_RD_IND(sc, i + 0x4),
11336                                     REG_RD_IND(sc, i + 0x8),
11337                                     REG_RD_IND(sc, i + 0xC));
11338                 }
11339         }
11340
11341         BCE_PRINTF(
11342             "----------------------------"
11343             "----------------"
11344             "----------------------------\n");
11345 }
11346
11347
11348 /****************************************************************************/
11349 /* Prints out the TPAT processor state.                                     */
11350 /*                                                                          */
11351 /* Returns:                                                                 */
11352 /*   Nothing.                                                               */
11353 /****************************************************************************/
11354 static __attribute__ ((noinline)) void
11355 bce_dump_tpat_state(struct bce_softc *sc, int regs)
11356 {
11357         u32 val;
11358         u32 fw_version[3];
11359
11360         BCE_PRINTF(
11361             "----------------------------"
11362             "   TPAT State   "
11363             "----------------------------\n");
11364
11365         for (int i = 0; i < 3; i++)
11366                 fw_version[i] = htonl(REG_RD_IND(sc,
11367                     (BCE_TPAT_SCRATCH + 0x410 + i * 4)));
11368
11369         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11370
11371         val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
11372         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n",
11373             val, BCE_TPAT_CPU_MODE);
11374
11375         val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11376         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
11377             val, BCE_TPAT_CPU_STATE);
11378
11379         val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
11380         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n",
11381             val, BCE_TPAT_CPU_EVENT_MASK);
11382
11383         if (regs) {
11384                 BCE_PRINTF(
11385                     "----------------------------"
11386                     " Register  Dump "
11387                     "----------------------------\n");
11388
11389                 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
11390                         /* Skip the big blank spaces */
11391                         if (i < 0x854000 && i > 0x9ffff)
11392                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11393                                     "0x%08X 0x%08X\n", i,
11394                                     REG_RD_IND(sc, i),
11395                                     REG_RD_IND(sc, i + 0x4),
11396                                     REG_RD_IND(sc, i + 0x8),
11397                                     REG_RD_IND(sc, i + 0xC));
11398                 }
11399         }
11400
11401         BCE_PRINTF(
11402                 "----------------------------"
11403                 "----------------"
11404                 "----------------------------\n");
11405 }
11406
11407
11408 /****************************************************************************/
11409 /* Prints out the Command Procesor (CP) state.                              */
11410 /*                                                                          */
11411 /* Returns:                                                                 */
11412 /*   Nothing.                                                               */
11413 /****************************************************************************/
11414 static __attribute__ ((noinline)) void
11415 bce_dump_cp_state(struct bce_softc *sc, int regs)
11416 {
11417         u32 val;
11418         u32 fw_version[3];
11419
11420         BCE_PRINTF(
11421             "----------------------------"
11422             "    CP State    "
11423             "----------------------------\n");
11424
11425         for (int i = 0; i < 3; i++)
11426                 fw_version[i] = htonl(REG_RD_IND(sc,
11427                     (BCE_CP_SCRATCH + 0x10 + i * 4)));
11428
11429         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11430
11431         val = REG_RD_IND(sc, BCE_CP_CPU_MODE);
11432         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n",
11433             val, BCE_CP_CPU_MODE);
11434
11435         val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11436         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
11437             val, BCE_CP_CPU_STATE);
11438
11439         val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK);
11440         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val,
11441             BCE_CP_CPU_EVENT_MASK);
11442
11443         if (regs) {
11444                 BCE_PRINTF(
11445                     "----------------------------"
11446                     " Register  Dump "
11447                     "----------------------------\n");
11448
11449                 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) {
11450                         /* Skip the big blank spaces */
11451                         if (i < 0x185400 && i > 0x19ffff)
11452                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11453                                     "0x%08X 0x%08X\n", i,
11454                                     REG_RD_IND(sc, i),
11455                                     REG_RD_IND(sc, i + 0x4),
11456                                     REG_RD_IND(sc, i + 0x8),
11457                                     REG_RD_IND(sc, i + 0xC));
11458                 }
11459         }
11460
11461         BCE_PRINTF(
11462             "----------------------------"
11463             "----------------"
11464             "----------------------------\n");
11465 }
11466
11467
11468 /****************************************************************************/
11469 /* Prints out the Completion Procesor (COM) state.                          */
11470 /*                                                                          */
11471 /* Returns:                                                                 */
11472 /*   Nothing.                                                               */
11473 /****************************************************************************/
11474 static __attribute__ ((noinline)) void
11475 bce_dump_com_state(struct bce_softc *sc, int regs)
11476 {
11477         u32 val;
11478         u32 fw_version[4];
11479
11480         BCE_PRINTF(
11481             "----------------------------"
11482             "   COM State    "
11483             "----------------------------\n");
11484
11485         for (int i = 0; i < 3; i++)
11486                 fw_version[i] = htonl(REG_RD_IND(sc,
11487                     (BCE_COM_SCRATCH + 0x10 + i * 4)));
11488
11489         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11490
11491         val = REG_RD_IND(sc, BCE_COM_CPU_MODE);
11492         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n",
11493             val, BCE_COM_CPU_MODE);
11494
11495         val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11496         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
11497             val, BCE_COM_CPU_STATE);
11498
11499         val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK);
11500         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val,
11501             BCE_COM_CPU_EVENT_MASK);
11502
11503         if (regs) {
11504                 BCE_PRINTF(
11505                     "----------------------------"
11506                     " Register  Dump "
11507                     "----------------------------\n");
11508
11509                 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) {
11510                         BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11511                             "0x%08X 0x%08X\n", i,
11512                             REG_RD_IND(sc, i),
11513                             REG_RD_IND(sc, i + 0x4),
11514                             REG_RD_IND(sc, i + 0x8),
11515                             REG_RD_IND(sc, i + 0xC));
11516                 }
11517         }
11518
11519         BCE_PRINTF(
11520                 "----------------------------"
11521                 "----------------"
11522                 "----------------------------\n");
11523 }
11524
11525
11526 /****************************************************************************/
11527 /* Prints out the Receive Virtual 2 Physical (RV2P) state.                  */
11528 /*                                                                          */
11529 /* Returns:                                                                 */
11530 /*   Nothing.                                                               */
11531 /****************************************************************************/
11532 static __attribute__ ((noinline)) void
11533 bce_dump_rv2p_state(struct bce_softc *sc)
11534 {
11535         u32 val, pc1, pc2, fw_ver_high, fw_ver_low;
11536
11537         BCE_PRINTF(
11538             "----------------------------"
11539             "   RV2P State   "
11540             "----------------------------\n");
11541
11542         /* Stall the RV2P processors. */
11543         val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11544         val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2;
11545         REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
11546
11547         /* Read the firmware version. */
11548         val = 0x00000001;
11549         REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
11550         fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
11551         fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
11552             BCE_RV2P_INSTR_HIGH_HIGH;
11553         BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n",
11554             fw_ver_high, fw_ver_low);
11555
11556         val = 0x00000001;
11557         REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
11558         fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
11559         fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
11560             BCE_RV2P_INSTR_HIGH_HIGH;
11561         BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n",
11562             fw_ver_high, fw_ver_low);
11563
11564         /* Resume the RV2P processors. */
11565         val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11566         val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2);
11567         REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
11568
11569         /* Fetch the program counter value. */
11570         val = 0x68007800;
11571         REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
11572         val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11573         pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
11574         pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
11575         BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1);
11576         BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2);
11577
11578         /* Fetch the program counter value again to see if it is advancing. */
11579         val = 0x68007800;
11580         REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
11581         val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11582         pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
11583         pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
11584         BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1);
11585         BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2);
11586
11587         BCE_PRINTF(
11588             "----------------------------"
11589             "----------------"
11590             "----------------------------\n");
11591 }
11592
11593
11594 /****************************************************************************/
11595 /* Prints out the driver state and then enters the debugger.                */
11596 /*                                                                          */
11597 /* Returns:                                                                 */
11598 /*   Nothing.                                                               */
11599 /****************************************************************************/
11600 static __attribute__ ((noinline)) void
11601 bce_breakpoint(struct bce_softc *sc)
11602 {
11603
11604         /*
11605          * Unreachable code to silence compiler warnings
11606          * about unused functions.
11607          */
11608         if (0) {
11609                 bce_freeze_controller(sc);
11610                 bce_unfreeze_controller(sc);
11611                 bce_dump_enet(sc, NULL);
11612                 bce_dump_txbd(sc, 0, NULL);
11613                 bce_dump_rxbd(sc, 0, NULL);
11614                 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC);
11615                 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC);
11616                 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC);
11617                 bce_dump_l2fhdr(sc, 0, NULL);
11618                 bce_dump_ctx(sc, RX_CID);
11619                 bce_dump_ftqs(sc);
11620                 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC);
11621                 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC);
11622                 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC);
11623                 bce_dump_status_block(sc);
11624                 bce_dump_stats_block(sc);
11625                 bce_dump_driver_state(sc);
11626                 bce_dump_hw_state(sc);
11627                 bce_dump_bc_state(sc);
11628                 bce_dump_txp_state(sc, 0);
11629                 bce_dump_rxp_state(sc, 0);
11630                 bce_dump_tpat_state(sc, 0);
11631                 bce_dump_cp_state(sc, 0);
11632                 bce_dump_com_state(sc, 0);
11633                 bce_dump_rv2p_state(sc);
11634                 bce_dump_pgbd(sc, 0, NULL);
11635         }
11636
11637         bce_dump_status_block(sc);
11638         bce_dump_driver_state(sc);
11639
11640         /* Call the debugger. */
11641         breakpoint();
11642 }
11643 #endif