2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2006-2014 QLogic Corporation
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
33 * The following controllers are supported by this driver:
43 * The following controllers are not supported by this driver:
44 * BCM5706C A0, A1 (pre-production)
45 * BCM5706S A0, A1 (pre-production)
46 * BCM5708C A0, B0 (pre-production)
47 * BCM5708S A0, B0 (pre-production)
48 * BCM5709C A0 B0, B1, B2 (pre-production)
49 * BCM5709S A0, B0, B1, B2 (pre-production)
54 #include <sys/param.h>
55 #include <sys/endian.h>
56 #include <sys/systm.h>
57 #include <sys/sockio.h>
60 #include <sys/malloc.h>
61 #include <sys/mutex.h>
62 #include <sys/kernel.h>
63 #include <sys/module.h>
64 #include <sys/socket.h>
65 #include <sys/sysctl.h>
66 #include <sys/queue.h>
69 #include <net/ethernet.h>
71 #include <net/if_var.h>
72 #include <net/if_arp.h>
73 #include <net/if_dl.h>
74 #include <net/if_media.h>
76 #include <net/if_types.h>
77 #include <net/if_vlan_var.h>
79 #include <netinet/in_systm.h>
80 #include <netinet/in.h>
81 #include <netinet/if_ether.h>
82 #include <netinet/ip.h>
83 #include <netinet/ip6.h>
84 #include <netinet/tcp.h>
85 #include <netinet/udp.h>
87 #include <machine/bus.h>
88 #include <machine/resource.h>
92 #include <dev/mii/mii.h>
93 #include <dev/mii/miivar.h>
95 #include <dev/mii/brgphyreg.h>
97 #include <dev/pci/pcireg.h>
98 #include <dev/pci/pcivar.h>
100 #include "miibus_if.h"
102 #include <dev/bce/if_bcereg.h>
103 #include <dev/bce/if_bcefw.h>
105 /****************************************************************************/
106 /* BCE Debug Options */
107 /****************************************************************************/
109 u32 bce_debug = BCE_WARN;
112 /* 1 = 1 in 2,147,483,648 */
113 /* 256 = 1 in 8,388,608 */
114 /* 2048 = 1 in 1,048,576 */
115 /* 65536 = 1 in 32,768 */
116 /* 1048576 = 1 in 2,048 */
117 /* 268435456 = 1 in 8 */
118 /* 536870912 = 1 in 4 */
119 /* 1073741824 = 1 in 2 */
121 /* Controls how often the l2_fhdr frame error check will fail. */
122 int l2fhdr_error_sim_control = 0;
124 /* Controls how often the unexpected attention check will fail. */
125 int unexpected_attention_sim_control = 0;
127 /* Controls how often to simulate an mbuf allocation failure. */
128 int mbuf_alloc_failed_sim_control = 0;
130 /* Controls how often to simulate a DMA mapping failure. */
131 int dma_map_addr_failed_sim_control = 0;
133 /* Controls how often to simulate a bootcode failure. */
134 int bootcode_running_failure_sim_control = 0;
137 /****************************************************************************/
138 /* PCI Device ID Table */
140 /* Used by bce_probe() to identify the devices supported by this driver. */
141 /****************************************************************************/
142 #define BCE_DEVDESC_MAX 64
144 static const struct bce_type bce_devs[] = {
145 /* BCM5706C Controllers and OEM boards. */
146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101,
147 "HP NC370T Multifunction Gigabit Server Adapter" },
148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106,
149 "HP NC370i Multifunction Gigabit Server Adapter" },
150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070,
151 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709,
153 "HP NC371i Multifunction Gigabit Server Adapter" },
154 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID,
155 "QLogic NetXtreme II BCM5706 1000Base-T" },
157 /* BCM5706S controllers and OEM boards. */
158 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
159 "HP NC370F Multifunction Gigabit Server Adapter" },
160 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID,
161 "QLogic NetXtreme II BCM5706 1000Base-SX" },
163 /* BCM5708C controllers and OEM boards. */
164 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037,
165 "HP NC373T PCIe Multifunction Gig Server Adapter" },
166 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038,
167 "HP NC373i Multifunction Gigabit Server Adapter" },
168 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045,
169 "HP NC374m PCIe Multifunction Adapter" },
170 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID,
171 "QLogic NetXtreme II BCM5708 1000Base-T" },
173 /* BCM5708S controllers and OEM boards. */
174 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706,
175 "HP NC373m Multifunction Gigabit Server Adapter" },
176 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b,
177 "HP NC373i Multifunction Gigabit Server Adapter" },
178 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d,
179 "HP NC373F PCIe Multifunc Giga Server Adapter" },
180 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID,
181 "QLogic NetXtreme II BCM5708 1000Base-SX" },
183 /* BCM5709C controllers and OEM boards. */
184 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055,
185 "HP NC382i DP Multifunction Gigabit Server Adapter" },
186 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059,
187 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
188 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID,
189 "QLogic NetXtreme II BCM5709 1000Base-T" },
191 /* BCM5709S controllers and OEM boards. */
192 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d,
193 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
194 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056,
195 "HP NC382i DP Multifunction Gigabit Server Adapter" },
196 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID,
197 "QLogic NetXtreme II BCM5709 1000Base-SX" },
199 /* BCM5716 controllers and OEM boards. */
200 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID,
201 "QLogic NetXtreme II BCM5716 1000Base-T" },
207 /****************************************************************************/
208 /* Supported Flash NVRAM device data. */
209 /****************************************************************************/
210 static const struct flash_spec flash_table[] =
212 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
213 #define NONBUFFERED_FLAGS (BCE_NV_WREN)
216 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
217 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
218 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
220 /* Expansion entry 0001 */
221 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
222 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
223 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
225 /* Saifun SA25F010 (non-buffered flash) */
226 /* strap, cfg1, & write1 need updates */
227 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
228 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
229 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
230 "Non-buffered flash (128kB)"},
231 /* Saifun SA25F020 (non-buffered flash) */
232 /* strap, cfg1, & write1 need updates */
233 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
234 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
235 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
236 "Non-buffered flash (256kB)"},
237 /* Expansion entry 0100 */
238 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
239 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
240 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
242 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
243 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
244 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
245 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
246 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
247 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
248 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
249 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
250 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
251 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
252 /* Saifun SA25F005 (non-buffered flash) */
253 /* strap, cfg1, & write1 need updates */
254 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
255 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
256 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
257 "Non-buffered flash (64kB)"},
259 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
260 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
261 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
263 /* Expansion entry 1001 */
264 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
265 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
266 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
268 /* Expansion entry 1010 */
269 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
270 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
271 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
273 /* ATMEL AT45DB011B (buffered flash) */
274 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
275 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
276 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
277 "Buffered flash (128kB)"},
278 /* Expansion entry 1100 */
279 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
280 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
281 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
283 /* Expansion entry 1101 */
284 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
285 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
286 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
288 /* Ateml Expansion entry 1110 */
289 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
290 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
291 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
292 "Entry 1110 (Atmel)"},
293 /* ATMEL AT45DB021B (buffered flash) */
294 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
295 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
296 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
297 "Buffered flash (256kB)"},
301 * The BCM5709 controllers transparently handle the
302 * differences between Atmel 264 byte pages and all
303 * flash devices which use 256 byte pages, so no
304 * logical-to-physical mapping is required in the
307 static const struct flash_spec flash_5709 = {
308 .flags = BCE_NV_BUFFERED,
309 .page_bits = BCM5709_FLASH_PAGE_BITS,
310 .page_size = BCM5709_FLASH_PAGE_SIZE,
311 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
312 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2,
313 .name = "5709/5716 buffered flash (256kB)",
317 /****************************************************************************/
318 /* FreeBSD device entry points. */
319 /****************************************************************************/
320 static int bce_probe (device_t);
321 static int bce_attach (device_t);
322 static int bce_detach (device_t);
323 static int bce_shutdown (device_t);
326 /****************************************************************************/
327 /* BCE Debug Data Structure Dump Routines */
328 /****************************************************************************/
330 static u32 bce_reg_rd (struct bce_softc *, u32);
331 static void bce_reg_wr (struct bce_softc *, u32, u32);
332 static void bce_reg_wr16 (struct bce_softc *, u32, u16);
333 static u32 bce_ctx_rd (struct bce_softc *, u32, u32);
334 static void bce_dump_enet (struct bce_softc *, struct mbuf *);
335 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *);
336 static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int);
337 static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int);
338 static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int);
339 static void bce_dump_txbd (struct bce_softc *,
340 int, struct tx_bd *);
341 static void bce_dump_rxbd (struct bce_softc *,
342 int, struct rx_bd *);
343 static void bce_dump_pgbd (struct bce_softc *,
344 int, struct rx_bd *);
345 static void bce_dump_l2fhdr (struct bce_softc *,
346 int, struct l2_fhdr *);
347 static void bce_dump_ctx (struct bce_softc *, u16);
348 static void bce_dump_ftqs (struct bce_softc *);
349 static void bce_dump_tx_chain (struct bce_softc *, u16, int);
350 static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int);
351 static void bce_dump_pg_chain (struct bce_softc *, u16, int);
352 static void bce_dump_status_block (struct bce_softc *);
353 static void bce_dump_stats_block (struct bce_softc *);
354 static void bce_dump_driver_state (struct bce_softc *);
355 static void bce_dump_hw_state (struct bce_softc *);
356 static void bce_dump_shmem_state (struct bce_softc *);
357 static void bce_dump_mq_regs (struct bce_softc *);
358 static void bce_dump_bc_state (struct bce_softc *);
359 static void bce_dump_txp_state (struct bce_softc *, int);
360 static void bce_dump_rxp_state (struct bce_softc *, int);
361 static void bce_dump_tpat_state (struct bce_softc *, int);
362 static void bce_dump_cp_state (struct bce_softc *, int);
363 static void bce_dump_com_state (struct bce_softc *, int);
364 static void bce_dump_rv2p_state (struct bce_softc *);
365 static void bce_breakpoint (struct bce_softc *);
366 #endif /*BCE_DEBUG */
369 /****************************************************************************/
370 /* BCE Register/Memory Access Routines */
371 /****************************************************************************/
372 static u32 bce_reg_rd_ind (struct bce_softc *, u32);
373 static void bce_reg_wr_ind (struct bce_softc *, u32, u32);
374 static void bce_shmem_wr (struct bce_softc *, u32, u32);
375 static u32 bce_shmem_rd (struct bce_softc *, u32);
376 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32);
377 static int bce_miibus_read_reg (device_t, int, int);
378 static int bce_miibus_write_reg (device_t, int, int, int);
379 static void bce_miibus_statchg (device_t);
382 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS);
383 #ifdef BCE_NVRAM_WRITE_SUPPORT
384 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS);
388 /****************************************************************************/
389 /* BCE NVRAM Access Routines */
390 /****************************************************************************/
391 static int bce_acquire_nvram_lock (struct bce_softc *);
392 static int bce_release_nvram_lock (struct bce_softc *);
393 static void bce_enable_nvram_access(struct bce_softc *);
394 static void bce_disable_nvram_access(struct bce_softc *);
395 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32);
396 static int bce_init_nvram (struct bce_softc *);
397 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int);
398 static int bce_nvram_test (struct bce_softc *);
399 #ifdef BCE_NVRAM_WRITE_SUPPORT
400 static int bce_enable_nvram_write (struct bce_softc *);
401 static void bce_disable_nvram_write(struct bce_softc *);
402 static int bce_nvram_erase_page (struct bce_softc *, u32);
403 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32);
404 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int);
407 /****************************************************************************/
409 /****************************************************************************/
410 static void bce_get_rx_buffer_sizes(struct bce_softc *, int);
411 static void bce_get_media (struct bce_softc *);
412 static void bce_init_media (struct bce_softc *);
413 static u32 bce_get_rphy_link (struct bce_softc *);
414 static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int);
415 static int bce_dma_alloc (device_t);
416 static void bce_dma_free (struct bce_softc *);
417 static void bce_release_resources (struct bce_softc *);
419 /****************************************************************************/
420 /* BCE Firmware Synchronization and Load */
421 /****************************************************************************/
422 static void bce_fw_cap_init (struct bce_softc *);
423 static int bce_fw_sync (struct bce_softc *, u32);
424 static void bce_load_rv2p_fw (struct bce_softc *, const u32 *, u32,
426 static void bce_load_cpu_fw (struct bce_softc *,
427 struct cpu_reg *, struct fw_info *);
428 static void bce_start_cpu (struct bce_softc *, struct cpu_reg *);
429 static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *);
430 static void bce_start_rxp_cpu (struct bce_softc *);
431 static void bce_init_rxp_cpu (struct bce_softc *);
432 static void bce_init_txp_cpu (struct bce_softc *);
433 static void bce_init_tpat_cpu (struct bce_softc *);
434 static void bce_init_cp_cpu (struct bce_softc *);
435 static void bce_init_com_cpu (struct bce_softc *);
436 static void bce_init_cpus (struct bce_softc *);
438 static void bce_print_adapter_info (struct bce_softc *);
439 static void bce_probe_pci_caps (device_t, struct bce_softc *);
440 static void bce_stop (struct bce_softc *);
441 static int bce_reset (struct bce_softc *, u32);
442 static int bce_chipinit (struct bce_softc *);
443 static int bce_blockinit (struct bce_softc *);
445 static int bce_init_tx_chain (struct bce_softc *);
446 static void bce_free_tx_chain (struct bce_softc *);
448 static int bce_get_rx_buf (struct bce_softc *, u16, u16, u32 *);
449 static int bce_init_rx_chain (struct bce_softc *);
450 static void bce_fill_rx_chain (struct bce_softc *);
451 static void bce_free_rx_chain (struct bce_softc *);
453 static int bce_get_pg_buf (struct bce_softc *, u16, u16);
454 static int bce_init_pg_chain (struct bce_softc *);
455 static void bce_fill_pg_chain (struct bce_softc *);
456 static void bce_free_pg_chain (struct bce_softc *);
458 static struct mbuf *bce_tso_setup (struct bce_softc *,
459 struct mbuf **, u16 *);
460 static int bce_tx_encap (struct bce_softc *, struct mbuf **);
461 static void bce_start_locked (struct ifnet *);
462 static void bce_start (struct ifnet *);
463 static int bce_ioctl (struct ifnet *, u_long, caddr_t);
464 static uint64_t bce_get_counter (struct ifnet *, ift_counter);
465 static void bce_watchdog (struct bce_softc *);
466 static int bce_ifmedia_upd (struct ifnet *);
467 static int bce_ifmedia_upd_locked (struct ifnet *);
468 static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *);
469 static void bce_ifmedia_sts_rphy (struct bce_softc *, struct ifmediareq *);
470 static void bce_init_locked (struct bce_softc *);
471 static void bce_init (void *);
472 static void bce_mgmt_init_locked (struct bce_softc *sc);
474 static int bce_init_ctx (struct bce_softc *);
475 static void bce_get_mac_addr (struct bce_softc *);
476 static void bce_set_mac_addr (struct bce_softc *);
477 static void bce_phy_intr (struct bce_softc *);
478 static inline u16 bce_get_hw_rx_cons (struct bce_softc *);
479 static void bce_rx_intr (struct bce_softc *);
480 static void bce_tx_intr (struct bce_softc *);
481 static void bce_disable_intr (struct bce_softc *);
482 static void bce_enable_intr (struct bce_softc *, int);
484 static void bce_intr (void *);
485 static void bce_set_rx_mode (struct bce_softc *);
486 static void bce_stats_update (struct bce_softc *);
487 static void bce_tick (void *);
488 static void bce_pulse (void *);
489 static void bce_add_sysctls (struct bce_softc *);
492 /****************************************************************************/
493 /* FreeBSD device dispatch table. */
494 /****************************************************************************/
495 static device_method_t bce_methods[] = {
496 /* Device interface (device_if.h) */
497 DEVMETHOD(device_probe, bce_probe),
498 DEVMETHOD(device_attach, bce_attach),
499 DEVMETHOD(device_detach, bce_detach),
500 DEVMETHOD(device_shutdown, bce_shutdown),
501 /* Supported by device interface but not used here. */
502 /* DEVMETHOD(device_identify, bce_identify), */
503 /* DEVMETHOD(device_suspend, bce_suspend), */
504 /* DEVMETHOD(device_resume, bce_resume), */
505 /* DEVMETHOD(device_quiesce, bce_quiesce), */
507 /* MII interface (miibus_if.h) */
508 DEVMETHOD(miibus_readreg, bce_miibus_read_reg),
509 DEVMETHOD(miibus_writereg, bce_miibus_write_reg),
510 DEVMETHOD(miibus_statchg, bce_miibus_statchg),
511 /* Supported by MII interface but not used here. */
512 /* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */
513 /* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */
518 static driver_t bce_driver = {
521 sizeof(struct bce_softc)
524 static devclass_t bce_devclass;
526 MODULE_DEPEND(bce, pci, 1, 1, 1);
527 MODULE_DEPEND(bce, ether, 1, 1, 1);
528 MODULE_DEPEND(bce, miibus, 1, 1, 1);
530 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, NULL, NULL);
531 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
532 MODULE_PNP_INFO("U16:vendor;U16:device;U16:#;U16:#;D:#", pci, bce,
533 bce_devs, nitems(bce_devs) - 1);
535 /****************************************************************************/
536 /* Tunable device values */
537 /****************************************************************************/
538 static SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters");
540 /* Allowable values are TRUE or FALSE */
541 static int bce_verbose = TRUE;
542 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0,
543 "Verbose output enable/disable");
545 /* Allowable values are TRUE or FALSE */
546 static int bce_tso_enable = TRUE;
547 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0,
548 "TSO Enable/Disable");
550 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
551 /* ToDo: Add MSI-X support. */
552 static int bce_msi_enable = 1;
553 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0,
554 "MSI-X|MSI|INTx selector");
556 /* Allowable values are 1, 2, 4, 8. */
557 static int bce_rx_pages = DEFAULT_RX_PAGES;
558 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0,
559 "Receive buffer descriptor pages (1 page = 255 buffer descriptors)");
561 /* Allowable values are 1, 2, 4, 8. */
562 static int bce_tx_pages = DEFAULT_TX_PAGES;
563 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0,
564 "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)");
566 /* Allowable values are TRUE or FALSE. */
567 static int bce_hdr_split = TRUE;
568 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0,
569 "Frame header/payload splitting Enable/Disable");
571 /* Allowable values are TRUE or FALSE. */
572 static int bce_strict_rx_mtu = FALSE;
573 SYSCTL_UINT(_hw_bce, OID_AUTO, strict_rx_mtu, CTLFLAG_RDTUN,
574 &bce_strict_rx_mtu, 0,
575 "Enable/Disable strict RX frame size checking");
577 /* Allowable values are 0 ... 100 */
579 /* Generate 1 interrupt for every transmit completion. */
580 static int bce_tx_quick_cons_trip_int = 1;
582 /* Generate 1 interrupt for every 20 transmit completions. */
583 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT;
585 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN,
586 &bce_tx_quick_cons_trip_int, 0,
587 "Transmit BD trip point during interrupts");
589 /* Allowable values are 0 ... 100 */
590 /* Generate 1 interrupt for every transmit completion. */
592 static int bce_tx_quick_cons_trip = 1;
594 /* Generate 1 interrupt for every 20 transmit completions. */
595 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
597 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN,
598 &bce_tx_quick_cons_trip, 0,
599 "Transmit BD trip point");
601 /* Allowable values are 0 ... 100 */
603 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
604 static int bce_tx_ticks_int = 0;
606 /* Generate an interrupt if 80us have elapsed since the last TX completion. */
607 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT;
609 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN,
610 &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt");
612 /* Allowable values are 0 ... 100 */
614 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
615 static int bce_tx_ticks = 0;
617 /* Generate an interrupt if 80us have elapsed since the last TX completion. */
618 static int bce_tx_ticks = DEFAULT_TX_TICKS;
620 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN,
621 &bce_tx_ticks, 0, "Transmit ticks count");
623 /* Allowable values are 1 ... 100 */
625 /* Generate 1 interrupt for every received frame. */
626 static int bce_rx_quick_cons_trip_int = 1;
628 /* Generate 1 interrupt for every 6 received frames. */
629 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT;
631 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN,
632 &bce_rx_quick_cons_trip_int, 0,
633 "Receive BD trip point duirng interrupts");
635 /* Allowable values are 1 ... 100 */
637 /* Generate 1 interrupt for every received frame. */
638 static int bce_rx_quick_cons_trip = 1;
640 /* Generate 1 interrupt for every 6 received frames. */
641 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP;
643 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN,
644 &bce_rx_quick_cons_trip, 0,
645 "Receive BD trip point");
647 /* Allowable values are 0 ... 100 */
649 /* Generate an int. if 0us have elapsed since the last received frame. */
650 static int bce_rx_ticks_int = 0;
652 /* Generate an int. if 18us have elapsed since the last received frame. */
653 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT;
655 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN,
656 &bce_rx_ticks_int, 0, "Receive ticks count during interrupt");
658 /* Allowable values are 0 ... 100 */
660 /* Generate an int. if 0us have elapsed since the last received frame. */
661 static int bce_rx_ticks = 0;
663 /* Generate an int. if 18us have elapsed since the last received frame. */
664 static int bce_rx_ticks = DEFAULT_RX_TICKS;
666 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN,
667 &bce_rx_ticks, 0, "Receive ticks count");
670 /****************************************************************************/
671 /* Device probe function. */
673 /* Compares the device to the driver's list of supported devices and */
674 /* reports back to the OS whether this is the right driver for the device. */
677 /* BUS_PROBE_DEFAULT on success, positive value on failure. */
678 /****************************************************************************/
680 bce_probe(device_t dev)
682 const struct bce_type *t;
683 struct bce_softc *sc;
685 u16 vid = 0, did = 0, svid = 0, sdid = 0;
689 sc = device_get_softc(dev);
690 sc->bce_unit = device_get_unit(dev);
693 /* Get the data for the device to be probed. */
694 vid = pci_get_vendor(dev);
695 did = pci_get_device(dev);
696 svid = pci_get_subvendor(dev);
697 sdid = pci_get_subdevice(dev);
699 DBPRINT(sc, BCE_EXTREME_LOAD,
700 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
701 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
703 /* Look through the list of known devices for a match. */
704 while(t->bce_name != NULL) {
706 if ((vid == t->bce_vid) && (did == t->bce_did) &&
707 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) &&
708 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) {
710 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
715 /* Print out the device identity. */
716 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
717 t->bce_name, (((pci_read_config(dev,
718 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'),
719 (pci_read_config(dev, PCIR_REVID, 4) & 0xf));
721 device_set_desc_copy(dev, descbuf);
722 free(descbuf, M_TEMP);
723 return(BUS_PROBE_DEFAULT);
732 /****************************************************************************/
733 /* PCI Capabilities Probe Function. */
735 /* Walks the PCI capabiites list for the device to find what features are */
740 /****************************************************************************/
742 bce_print_adapter_info(struct bce_softc *sc)
746 DBENTER(BCE_VERBOSE_LOAD);
748 if (bce_verbose || bootverbose) {
749 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid);
750 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >>
751 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
755 if (sc->bce_flags & BCE_PCIE_FLAG) {
756 printf("Bus (PCIe x%d, ", sc->link_width);
757 switch (sc->link_speed) {
758 case 1: printf("2.5Gbps); "); break;
759 case 2: printf("5Gbps); "); break;
760 default: printf("Unknown link speed); ");
763 printf("Bus (PCI%s, %s, %dMHz); ",
764 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
765 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ?
766 "32-bit" : "64-bit"), sc->bus_speed_mhz);
769 /* Firmware version and device features. */
770 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (",
771 sc->bce_bc_ver, sc->rx_pages, sc->tx_pages,
772 (bce_hdr_split == TRUE ? sc->pg_pages: 0));
774 if (bce_hdr_split == TRUE) {
779 if (sc->bce_flags & BCE_USING_MSI_FLAG) {
780 if (i > 0) printf("|");
784 if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
785 if (i > 0) printf("|");
786 printf("MSI-X"); i++;
789 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
790 if (i > 0) printf("|");
794 if (sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) {
795 if (i > 0) printf("|");
796 printf("Remote PHY(%s)",
797 sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG ?
798 "FIBER" : "TP"); i++;
801 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
802 if (i > 0) printf("|");
803 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver);
808 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n",
809 sc->bce_rx_quick_cons_trip_int,
810 sc->bce_rx_quick_cons_trip,
811 sc->bce_rx_ticks_int,
813 sc->bce_tx_quick_cons_trip_int,
814 sc->bce_tx_quick_cons_trip,
815 sc->bce_tx_ticks_int,
820 DBEXIT(BCE_VERBOSE_LOAD);
824 /****************************************************************************/
825 /* PCI Capabilities Probe Function. */
827 /* Walks the PCI capabiites list for the device to find what features are */
832 /****************************************************************************/
834 bce_probe_pci_caps(device_t dev, struct bce_softc *sc)
838 DBENTER(BCE_VERBOSE_LOAD);
840 /* Check if PCI-X capability is enabled. */
841 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) {
843 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
846 /* Check if PCIe capability is enabled. */
847 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
849 u16 link_status = pci_read_config(dev, reg + 0x12, 2);
850 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = "
851 "0x%08X\n", link_status);
852 sc->link_speed = link_status & 0xf;
853 sc->link_width = (link_status >> 4) & 0x3f;
854 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
855 sc->bce_flags |= BCE_PCIE_FLAG;
859 /* Check if MSI capability is enabled. */
860 if (pci_find_cap(dev, PCIY_MSI, ®) == 0) {
862 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG;
865 /* Check if MSI-X capability is enabled. */
866 if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) {
868 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG;
871 DBEXIT(BCE_VERBOSE_LOAD);
875 /****************************************************************************/
876 /* Load and validate user tunable settings. */
880 /****************************************************************************/
882 bce_set_tunables(struct bce_softc *sc)
884 /* Set sysctl values for RX page count. */
885 switch (bce_rx_pages) {
893 sc->rx_pages = bce_rx_pages;
896 sc->rx_pages = DEFAULT_RX_PAGES;
897 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
898 "hw.bce.rx_pages! Setting default of %d.\n",
899 __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES);
902 /* ToDo: Consider allowing user setting for pg_pages. */
903 sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES);
905 /* Set sysctl values for TX page count. */
906 switch (bce_tx_pages) {
914 sc->tx_pages = bce_tx_pages;
917 sc->tx_pages = DEFAULT_TX_PAGES;
918 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
919 "hw.bce.tx_pages! Setting default of %d.\n",
920 __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES);
924 * Validate the TX trip point (i.e. the number of
925 * TX completions before a status block update is
926 * generated and an interrupt is asserted.
928 if (bce_tx_quick_cons_trip_int <= 100) {
929 sc->bce_tx_quick_cons_trip_int =
930 bce_tx_quick_cons_trip_int;
932 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
933 "hw.bce.tx_quick_cons_trip_int! Setting default of %d.\n",
934 __FILE__, __LINE__, bce_tx_quick_cons_trip_int,
935 DEFAULT_TX_QUICK_CONS_TRIP_INT);
936 sc->bce_tx_quick_cons_trip_int =
937 DEFAULT_TX_QUICK_CONS_TRIP_INT;
940 if (bce_tx_quick_cons_trip <= 100) {
941 sc->bce_tx_quick_cons_trip =
942 bce_tx_quick_cons_trip;
944 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
945 "hw.bce.tx_quick_cons_trip! Setting default of %d.\n",
946 __FILE__, __LINE__, bce_tx_quick_cons_trip,
947 DEFAULT_TX_QUICK_CONS_TRIP);
948 sc->bce_tx_quick_cons_trip =
949 DEFAULT_TX_QUICK_CONS_TRIP;
953 * Validate the TX ticks count (i.e. the maximum amount
954 * of time to wait after the last TX completion has
955 * occurred before a status block update is generated
956 * and an interrupt is asserted.
958 if (bce_tx_ticks_int <= 100) {
959 sc->bce_tx_ticks_int =
962 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
963 "hw.bce.tx_ticks_int! Setting default of %d.\n",
964 __FILE__, __LINE__, bce_tx_ticks_int,
965 DEFAULT_TX_TICKS_INT);
966 sc->bce_tx_ticks_int =
967 DEFAULT_TX_TICKS_INT;
970 if (bce_tx_ticks <= 100) {
974 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
975 "hw.bce.tx_ticks! Setting default of %d.\n",
976 __FILE__, __LINE__, bce_tx_ticks,
983 * Validate the RX trip point (i.e. the number of
984 * RX frames received before a status block update is
985 * generated and an interrupt is asserted.
987 if (bce_rx_quick_cons_trip_int <= 100) {
988 sc->bce_rx_quick_cons_trip_int =
989 bce_rx_quick_cons_trip_int;
991 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
992 "hw.bce.rx_quick_cons_trip_int! Setting default of %d.\n",
993 __FILE__, __LINE__, bce_rx_quick_cons_trip_int,
994 DEFAULT_RX_QUICK_CONS_TRIP_INT);
995 sc->bce_rx_quick_cons_trip_int =
996 DEFAULT_RX_QUICK_CONS_TRIP_INT;
999 if (bce_rx_quick_cons_trip <= 100) {
1000 sc->bce_rx_quick_cons_trip =
1001 bce_rx_quick_cons_trip;
1003 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
1004 "hw.bce.rx_quick_cons_trip! Setting default of %d.\n",
1005 __FILE__, __LINE__, bce_rx_quick_cons_trip,
1006 DEFAULT_RX_QUICK_CONS_TRIP);
1007 sc->bce_rx_quick_cons_trip =
1008 DEFAULT_RX_QUICK_CONS_TRIP;
1012 * Validate the RX ticks count (i.e. the maximum amount
1013 * of time to wait after the last RX frame has been
1014 * received before a status block update is generated
1015 * and an interrupt is asserted.
1017 if (bce_rx_ticks_int <= 100) {
1018 sc->bce_rx_ticks_int = bce_rx_ticks_int;
1020 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
1021 "hw.bce.rx_ticks_int! Setting default of %d.\n",
1022 __FILE__, __LINE__, bce_rx_ticks_int,
1023 DEFAULT_RX_TICKS_INT);
1024 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT;
1027 if (bce_rx_ticks <= 100) {
1028 sc->bce_rx_ticks = bce_rx_ticks;
1030 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
1031 "hw.bce.rx_ticks! Setting default of %d.\n",
1032 __FILE__, __LINE__, bce_rx_ticks,
1034 sc->bce_rx_ticks = DEFAULT_RX_TICKS;
1037 /* Disabling both RX ticks and RX trips will prevent interrupts. */
1038 if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) {
1039 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and "
1040 "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n",
1041 __FILE__, __LINE__);
1042 sc->bce_rx_ticks = DEFAULT_RX_TICKS;
1043 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP;
1046 /* Disabling both TX ticks and TX trips will prevent interrupts. */
1047 if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) {
1048 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and "
1049 "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n",
1050 __FILE__, __LINE__);
1051 sc->bce_tx_ticks = DEFAULT_TX_TICKS;
1052 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
1057 /****************************************************************************/
1058 /* Device attach function. */
1060 /* Allocates device resources, performs secondary chip identification, */
1061 /* resets and initializes the hardware, and initializes driver instance */
1065 /* 0 on success, positive value on failure. */
1066 /****************************************************************************/
1068 bce_attach(device_t dev)
1070 struct bce_softc *sc;
1073 int count, error, rc = 0, rid;
1075 sc = device_get_softc(dev);
1078 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1080 sc->bce_unit = device_get_unit(dev);
1082 /* Set initial device and PHY flags */
1084 sc->bce_phy_flags = 0;
1086 bce_set_tunables(sc);
1088 pci_enable_busmaster(dev);
1090 /* Allocate PCI memory resources. */
1092 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1095 if (sc->bce_res_mem == NULL) {
1096 BCE_PRINTF("%s(%d): PCI memory allocation failed\n",
1097 __FILE__, __LINE__);
1099 goto bce_attach_fail;
1102 /* Get various resource handles. */
1103 sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
1104 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
1105 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem);
1107 bce_probe_pci_caps(dev, sc);
1112 /* Try allocating MSI-X interrupts. */
1113 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) &&
1114 (bce_msi_enable >= 2) &&
1115 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1116 &rid, RF_ACTIVE)) != NULL)) {
1118 msi_needed = count = 1;
1120 if (((error = pci_alloc_msix(dev, &count)) != 0) ||
1121 (count != msi_needed)) {
1122 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d,"
1123 "Received = %d, error = %d\n", __FILE__, __LINE__,
1124 msi_needed, count, error);
1126 pci_release_msi(dev);
1127 bus_release_resource(dev, SYS_RES_MEMORY, rid,
1129 sc->bce_res_irq = NULL;
1131 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n",
1133 sc->bce_flags |= BCE_USING_MSIX_FLAG;
1138 /* Try allocating a MSI interrupt. */
1139 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) &&
1140 (bce_msi_enable >= 1) && (count == 0)) {
1142 if ((error = pci_alloc_msi(dev, &count)) != 0) {
1143 BCE_PRINTF("%s(%d): MSI allocation failed! "
1144 "error = %d\n", __FILE__, __LINE__, error);
1146 pci_release_msi(dev);
1148 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI "
1149 "interrupt.\n", __FUNCTION__);
1150 sc->bce_flags |= BCE_USING_MSI_FLAG;
1151 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
1152 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG;
1157 /* Try allocating a legacy interrupt. */
1159 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n",
1164 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1165 &rid, RF_ACTIVE | (count != 0 ? 0 : RF_SHAREABLE));
1167 /* Report any IRQ allocation errors. */
1168 if (sc->bce_res_irq == NULL) {
1169 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n",
1170 __FILE__, __LINE__);
1172 goto bce_attach_fail;
1175 /* Initialize mutex for the current device instance. */
1176 BCE_LOCK_INIT(sc, device_get_nameunit(dev));
1179 * Configure byte swap and enable indirect register access.
1180 * Rely on CPU to do target byte swapping on big endian systems.
1181 * Access to registers outside of PCI configurtion space are not
1182 * valid until this is done.
1184 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
1185 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
1186 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
1188 /* Save ASIC revsion info. */
1189 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID);
1191 /* Weed out any non-production controller revisions. */
1192 switch(BCE_CHIP_ID(sc)) {
1193 case BCE_CHIP_ID_5706_A0:
1194 case BCE_CHIP_ID_5706_A1:
1195 case BCE_CHIP_ID_5708_A0:
1196 case BCE_CHIP_ID_5708_B0:
1197 case BCE_CHIP_ID_5709_A0:
1198 case BCE_CHIP_ID_5709_B0:
1199 case BCE_CHIP_ID_5709_B1:
1200 case BCE_CHIP_ID_5709_B2:
1201 BCE_PRINTF("%s(%d): Unsupported controller "
1202 "revision (%c%d)!\n", __FILE__, __LINE__,
1203 (((pci_read_config(dev, PCIR_REVID, 4) &
1204 0xf0) >> 4) + 'A'), (pci_read_config(dev,
1205 PCIR_REVID, 4) & 0xf));
1207 goto bce_attach_fail;
1211 * The embedded PCIe to PCI-X bridge (EPB)
1212 * in the 5708 cannot address memory above
1213 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
1215 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
1216 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR;
1218 sc->max_bus_addr = BUS_SPACE_MAXADDR;
1221 * Find the base address for shared memory access.
1222 * Newer versions of bootcode use a signature and offset
1223 * while older versions use a fixed address.
1225 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
1226 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG)
1227 /* Multi-port devices use different offsets in shared memory. */
1228 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 +
1229 (pci_get_function(sc->bce_dev) << 2));
1231 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
1233 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n",
1234 __FUNCTION__, sc->bce_shmem_base);
1236 /* Fetch the bootcode revision. */
1237 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
1238 for (int i = 0, j = 0; i < 3; i++) {
1241 num = (u8) (val >> (24 - (i * 8)));
1242 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
1243 if (num >= k || !skip0 || k == 1) {
1244 sc->bce_bc_ver[j++] = (num / k) + '0';
1250 sc->bce_bc_ver[j++] = '.';
1253 /* Check if any management firwmare is enabled. */
1254 val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
1255 if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
1256 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
1258 /* Allow time for firmware to enter the running state. */
1259 for (int i = 0; i < 30; i++) {
1260 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
1261 if (val & BCE_CONDITION_MFW_RUN_MASK)
1266 /* Check if management firmware is running. */
1267 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
1268 val &= BCE_CONDITION_MFW_RUN_MASK;
1269 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) &&
1270 (val != BCE_CONDITION_MFW_RUN_NONE)) {
1271 u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
1274 /* Read the management firmware version string. */
1275 for (int j = 0; j < 3; j++) {
1276 val = bce_reg_rd_ind(sc, addr + j * 4);
1278 memcpy(&sc->bce_mfw_ver[i], &val, 4);
1282 /* May cause firmware synchronization timeouts. */
1283 BCE_PRINTF("%s(%d): Management firmware enabled "
1284 "but not running!\n", __FILE__, __LINE__);
1285 strcpy(sc->bce_mfw_ver, "NOT RUNNING!");
1287 /* ToDo: Any action the driver should take? */
1291 /* Get PCI bus information (speed and type). */
1292 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
1293 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
1296 sc->bce_flags |= BCE_PCIX_FLAG;
1298 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS);
1300 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
1302 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
1303 sc->bus_speed_mhz = 133;
1306 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
1307 sc->bus_speed_mhz = 100;
1310 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
1311 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
1312 sc->bus_speed_mhz = 66;
1315 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
1316 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
1317 sc->bus_speed_mhz = 50;
1320 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
1321 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
1322 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
1323 sc->bus_speed_mhz = 33;
1327 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
1328 sc->bus_speed_mhz = 66;
1330 sc->bus_speed_mhz = 33;
1333 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
1334 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
1336 /* Find the media type for the adapter. */
1339 /* Reset controller and announce to bootcode that driver is present. */
1340 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
1341 BCE_PRINTF("%s(%d): Controller reset failed!\n",
1342 __FILE__, __LINE__);
1344 goto bce_attach_fail;
1347 /* Initialize the controller. */
1348 if (bce_chipinit(sc)) {
1349 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
1350 __FILE__, __LINE__);
1352 goto bce_attach_fail;
1355 /* Perform NVRAM test. */
1356 if (bce_nvram_test(sc)) {
1357 BCE_PRINTF("%s(%d): NVRAM test failed!\n",
1358 __FILE__, __LINE__);
1360 goto bce_attach_fail;
1363 /* Fetch the permanent Ethernet MAC address. */
1364 bce_get_mac_addr(sc);
1366 /* Update statistics once every second. */
1367 sc->bce_stats_ticks = 1000000 & 0xffff00;
1369 /* Store data needed by PHY driver for backplane applications */
1370 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
1371 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG);
1373 /* Allocate DMA memory resources. */
1374 if (bce_dma_alloc(dev)) {
1375 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n",
1376 __FILE__, __LINE__);
1378 goto bce_attach_fail;
1381 /* Allocate an ifnet structure. */
1382 ifp = sc->bce_ifp = if_alloc(IFT_ETHER);
1384 BCE_PRINTF("%s(%d): Interface allocation failed!\n",
1385 __FILE__, __LINE__);
1387 goto bce_attach_fail;
1390 /* Initialize the ifnet interface. */
1392 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1393 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1394 ifp->if_ioctl = bce_ioctl;
1395 ifp->if_start = bce_start;
1396 ifp->if_get_counter = bce_get_counter;
1397 ifp->if_init = bce_init;
1398 ifp->if_mtu = ETHERMTU;
1400 if (bce_tso_enable) {
1401 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO;
1402 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 |
1405 ifp->if_hwassist = BCE_IF_HWASSIST;
1406 ifp->if_capabilities = BCE_IF_CAPABILITIES;
1409 #if __FreeBSD_version >= 800505
1411 * Introducing IFCAP_LINKSTATE didn't bump __FreeBSD_version
1412 * so it's approximate value.
1414 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1415 ifp->if_capabilities |= IFCAP_LINKSTATE;
1418 ifp->if_capenable = ifp->if_capabilities;
1421 * Assume standard mbuf sizes for buffer allocation.
1422 * This may change later if the MTU size is set to
1423 * something other than 1500.
1425 bce_get_rx_buffer_sizes(sc,
1426 (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN));
1428 /* Recalculate our buffer allocation sizes. */
1429 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC;
1430 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
1431 IFQ_SET_READY(&ifp->if_snd);
1433 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1434 ifp->if_baudrate = IF_Mbps(2500ULL);
1436 ifp->if_baudrate = IF_Mbps(1000);
1438 /* Handle any special PHY initialization for SerDes PHYs. */
1441 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
1442 ifmedia_init(&sc->bce_ifmedia, IFM_IMASK, bce_ifmedia_upd,
1445 * We can't manually override remote PHY's link and assume
1446 * PHY port configuration(Fiber or TP) is not changed after
1447 * device attach. This may not be correct though.
1449 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) {
1450 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
1451 ifmedia_add(&sc->bce_ifmedia,
1452 IFM_ETHER | IFM_2500_SX, 0, NULL);
1453 ifmedia_add(&sc->bce_ifmedia,
1454 IFM_ETHER | IFM_2500_SX | IFM_FDX, 0, NULL);
1456 ifmedia_add(&sc->bce_ifmedia,
1457 IFM_ETHER | IFM_1000_SX, 0, NULL);
1458 ifmedia_add(&sc->bce_ifmedia,
1459 IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL);
1461 ifmedia_add(&sc->bce_ifmedia,
1462 IFM_ETHER | IFM_10_T, 0, NULL);
1463 ifmedia_add(&sc->bce_ifmedia,
1464 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
1465 ifmedia_add(&sc->bce_ifmedia,
1466 IFM_ETHER | IFM_100_TX, 0, NULL);
1467 ifmedia_add(&sc->bce_ifmedia,
1468 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
1469 ifmedia_add(&sc->bce_ifmedia,
1470 IFM_ETHER | IFM_1000_T, 0, NULL);
1471 ifmedia_add(&sc->bce_ifmedia,
1472 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1474 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
1475 ifmedia_set(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO);
1476 sc->bce_ifmedia.ifm_media = sc->bce_ifmedia.ifm_cur->ifm_media;
1478 /* MII child bus by attaching the PHY. */
1479 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd,
1480 bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr,
1481 MII_OFFSET_ANY, MIIF_DOPAUSE);
1483 BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__,
1485 goto bce_attach_fail;
1489 /* Attach to the Ethernet interface list. */
1490 ether_ifattach(ifp, sc->eaddr);
1492 #if __FreeBSD_version < 500000
1493 callout_init(&sc->bce_tick_callout);
1494 callout_init(&sc->bce_pulse_callout);
1496 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0);
1497 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0);
1500 /* Hookup IRQ last. */
1501 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE,
1502 NULL, bce_intr, sc, &sc->bce_intrhand);
1505 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n",
1506 __FILE__, __LINE__);
1508 goto bce_attach_exit;
1512 * At this point we've acquired all the resources
1513 * we need to run so there's no turning back, we're
1514 * cleared for launch.
1517 /* Print some important debugging info. */
1518 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc));
1520 /* Add the supported sysctls to the kernel. */
1521 bce_add_sysctls(sc);
1526 * The chip reset earlier notified the bootcode that
1527 * a driver is present. We now need to start our pulse
1528 * routine so that the bootcode is reminded that we're
1533 bce_mgmt_init_locked(sc);
1536 /* Finally, print some useful adapter info */
1537 bce_print_adapter_info(sc);
1538 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n",
1541 goto bce_attach_exit;
1544 bce_release_resources(sc);
1548 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1554 /****************************************************************************/
1555 /* Device detach function. */
1557 /* Stops the controller, resets the controller, and releases resources. */
1560 /* 0 on success, positive value on failure. */
1561 /****************************************************************************/
1563 bce_detach(device_t dev)
1565 struct bce_softc *sc = device_get_softc(dev);
1569 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1573 /* Stop and reset the controller. */
1576 /* Stop the pulse so the bootcode can go to driver absent state. */
1577 callout_stop(&sc->bce_pulse_callout);
1580 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1581 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1583 msg = BCE_DRV_MSG_CODE_UNLOAD;
1588 ether_ifdetach(ifp);
1590 /* If we have a child device on the MII bus remove it too. */
1591 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1592 ifmedia_removeall(&sc->bce_ifmedia);
1594 bus_generic_detach(dev);
1595 device_delete_child(dev, sc->bce_miibus);
1598 /* Release all remaining resources. */
1599 bce_release_resources(sc);
1601 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1607 /****************************************************************************/
1608 /* Device shutdown function. */
1610 /* Stops and resets the controller. */
1613 /* 0 on success, positive value on failure. */
1614 /****************************************************************************/
1616 bce_shutdown(device_t dev)
1618 struct bce_softc *sc = device_get_softc(dev);
1621 DBENTER(BCE_VERBOSE);
1625 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1626 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1628 msg = BCE_DRV_MSG_CODE_UNLOAD;
1632 DBEXIT(BCE_VERBOSE);
1639 /****************************************************************************/
1640 /* Register read. */
1643 /* The value of the register. */
1644 /****************************************************************************/
1646 bce_reg_rd(struct bce_softc *sc, u32 offset)
1648 u32 val = REG_RD(sc, offset);
1649 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1650 __FUNCTION__, offset, val);
1655 /****************************************************************************/
1656 /* Register write (16 bit). */
1660 /****************************************************************************/
1662 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val)
1664 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n",
1665 __FUNCTION__, offset, val);
1666 REG_WR16(sc, offset, val);
1670 /****************************************************************************/
1671 /* Register write. */
1675 /****************************************************************************/
1677 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val)
1679 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1680 __FUNCTION__, offset, val);
1681 REG_WR(sc, offset, val);
1685 /****************************************************************************/
1686 /* Indirect register read. */
1688 /* Reads NetXtreme II registers using an index/data register pair in PCI */
1689 /* configuration space. Using this mechanism avoids issues with posted */
1690 /* reads but is much slower than memory-mapped I/O. */
1693 /* The value of the register. */
1694 /****************************************************************************/
1696 bce_reg_rd_ind(struct bce_softc *sc, u32 offset)
1701 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1705 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1706 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1707 __FUNCTION__, offset, val);
1711 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1716 /****************************************************************************/
1717 /* Indirect register write. */
1719 /* Writes NetXtreme II registers using an index/data register pair in PCI */
1720 /* configuration space. Using this mechanism avoids issues with posted */
1721 /* writes but is muchh slower than memory-mapped I/O. */
1725 /****************************************************************************/
1727 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val)
1732 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1733 __FUNCTION__, offset, val);
1735 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1736 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1740 /****************************************************************************/
1741 /* Shared memory write. */
1743 /* Writes NetXtreme II shared memory region. */
1747 /****************************************************************************/
1749 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val)
1751 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to "
1752 "0x%08X\n", __FUNCTION__, val, offset);
1754 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1758 /****************************************************************************/
1759 /* Shared memory read. */
1761 /* Reads NetXtreme II shared memory region. */
1764 /* The 32 bit value read. */
1765 /****************************************************************************/
1767 bce_shmem_rd(struct bce_softc *sc, u32 offset)
1769 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1771 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from "
1772 "0x%08X\n", __FUNCTION__, val, offset);
1779 /****************************************************************************/
1780 /* Context memory read. */
1782 /* The NetXtreme II controller uses context memory to track connection */
1783 /* information for L2 and higher network protocols. */
1786 /* The requested 32 bit value of context memory. */
1787 /****************************************************************************/
1789 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset)
1791 u32 idx, offset, retry_cnt = 5, val;
1793 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 ||
1794 cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID "
1795 "address: 0x%08X.\n", __FUNCTION__, cid_addr));
1797 offset = ctx_offset + cid_addr;
1799 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1801 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ));
1803 for (idx = 0; idx < retry_cnt; idx++) {
1804 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1805 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0)
1810 if (val & BCE_CTX_CTX_CTRL_READ_REQ)
1811 BCE_PRINTF("%s(%d); Unable to read CTX memory: "
1812 "cid_addr = 0x%08X, offset = 0x%08X!\n",
1813 __FILE__, __LINE__, cid_addr, ctx_offset);
1815 val = REG_RD(sc, BCE_CTX_CTX_DATA);
1817 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1818 val = REG_RD(sc, BCE_CTX_DATA);
1821 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1822 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val);
1829 /****************************************************************************/
1830 /* Context memory write. */
1832 /* The NetXtreme II controller uses context memory to track connection */
1833 /* information for L2 and higher network protocols. */
1837 /****************************************************************************/
1839 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val)
1841 u32 idx, offset = ctx_offset + cid_addr;
1842 u32 val, retry_cnt = 5;
1844 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1845 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val);
1847 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK),
1848 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n",
1849 __FUNCTION__, cid_addr));
1851 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1853 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1854 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1856 for (idx = 0; idx < retry_cnt; idx++) {
1857 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1858 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1863 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ)
1864 BCE_PRINTF("%s(%d); Unable to write CTX memory: "
1865 "cid_addr = 0x%08X, offset = 0x%08X!\n",
1866 __FILE__, __LINE__, cid_addr, ctx_offset);
1869 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1870 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1875 /****************************************************************************/
1876 /* PHY register read. */
1878 /* Implements register reads on the MII bus. */
1881 /* The value of the register. */
1882 /****************************************************************************/
1884 bce_miibus_read_reg(device_t dev, int phy, int reg)
1886 struct bce_softc *sc;
1890 sc = device_get_softc(dev);
1893 * The 5709S PHY is an IEEE Clause 45 PHY
1894 * with special mappings to work with IEEE
1895 * Clause 22 register accesses.
1897 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1898 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1902 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1903 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1904 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1906 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1907 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1913 val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1914 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1915 BCE_EMAC_MDIO_COMM_START_BUSY;
1916 REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1918 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1921 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1922 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1925 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1926 val &= BCE_EMAC_MDIO_COMM_DATA;
1932 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1933 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, "
1934 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg);
1937 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1941 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1942 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1943 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1945 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1946 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1951 DB_PRINT_PHY_REG(reg, val);
1952 return (val & 0xffff);
1956 /****************************************************************************/
1957 /* PHY register write. */
1959 /* Implements register writes on the MII bus. */
1962 /* The value of the register. */
1963 /****************************************************************************/
1965 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1967 struct bce_softc *sc;
1971 sc = device_get_softc(dev);
1973 DB_PRINT_PHY_REG(reg, val);
1976 * The 5709S PHY is an IEEE Clause 45 PHY
1977 * with special mappings to work with IEEE
1978 * Clause 22 register accesses.
1980 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1981 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1985 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1986 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1987 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1989 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1990 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1995 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1996 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1997 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1998 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
2000 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
2003 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
2004 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
2010 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
2011 BCE_PRINTF("%s(%d): PHY write timeout!\n",
2012 __FILE__, __LINE__);
2014 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
2015 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
2016 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
2018 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
2019 REG_RD(sc, BCE_EMAC_MDIO_MODE);
2028 /****************************************************************************/
2029 /* MII bus status change. */
2031 /* Called by the MII bus driver when the PHY establishes link to set the */
2032 /* MAC interface registers. */
2036 /****************************************************************************/
2038 bce_miibus_statchg(device_t dev)
2040 struct bce_softc *sc;
2041 struct mii_data *mii;
2042 struct ifmediareq ifmr;
2043 int media_active, media_status, val;
2045 sc = device_get_softc(dev);
2047 DBENTER(BCE_VERBOSE_PHY);
2049 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
2050 bzero(&ifmr, sizeof(ifmr));
2051 bce_ifmedia_sts_rphy(sc, &ifmr);
2052 media_active = ifmr.ifm_active;
2053 media_status = ifmr.ifm_status;
2055 mii = device_get_softc(sc->bce_miibus);
2056 media_active = mii->mii_media_active;
2057 media_status = mii->mii_media_status;
2060 /* Ignore invalid media status. */
2061 if ((media_status & (IFM_ACTIVE | IFM_AVALID)) !=
2062 (IFM_ACTIVE | IFM_AVALID))
2063 goto bce_miibus_statchg_exit;
2065 val = REG_RD(sc, BCE_EMAC_MODE);
2066 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX |
2067 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK |
2070 /* Set MII or GMII interface based on the PHY speed. */
2071 switch (IFM_SUBTYPE(media_active)) {
2073 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2074 DBPRINT(sc, BCE_INFO_PHY,
2075 "Enabling 10Mb interface.\n");
2076 val |= BCE_EMAC_MODE_PORT_MII_10;
2081 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n");
2082 val |= BCE_EMAC_MODE_PORT_MII;
2085 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n");
2086 val |= BCE_EMAC_MODE_25G;
2090 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n");
2091 val |= BCE_EMAC_MODE_PORT_GMII;
2094 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling "
2095 "default GMII interface.\n");
2096 val |= BCE_EMAC_MODE_PORT_GMII;
2099 /* Set half or full duplex based on PHY settings. */
2100 if ((IFM_OPTIONS(media_active) & IFM_FDX) == 0) {
2101 DBPRINT(sc, BCE_INFO_PHY,
2102 "Setting Half-Duplex interface.\n");
2103 val |= BCE_EMAC_MODE_HALF_DUPLEX;
2105 DBPRINT(sc, BCE_INFO_PHY,
2106 "Setting Full-Duplex interface.\n");
2108 REG_WR(sc, BCE_EMAC_MODE, val);
2110 if ((IFM_OPTIONS(media_active) & IFM_ETH_RXPAUSE) != 0) {
2111 DBPRINT(sc, BCE_INFO_PHY,
2112 "%s(): Enabling RX flow control.\n", __FUNCTION__);
2113 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
2114 sc->bce_flags |= BCE_USING_RX_FLOW_CONTROL;
2116 DBPRINT(sc, BCE_INFO_PHY,
2117 "%s(): Disabling RX flow control.\n", __FUNCTION__);
2118 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
2119 sc->bce_flags &= ~BCE_USING_RX_FLOW_CONTROL;
2122 if ((IFM_OPTIONS(media_active) & IFM_ETH_TXPAUSE) != 0) {
2123 DBPRINT(sc, BCE_INFO_PHY,
2124 "%s(): Enabling TX flow control.\n", __FUNCTION__);
2125 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
2126 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL;
2128 DBPRINT(sc, BCE_INFO_PHY,
2129 "%s(): Disabling TX flow control.\n", __FUNCTION__);
2130 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
2131 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL;
2134 /* ToDo: Update watermarks in bce_init_rx_context(). */
2136 bce_miibus_statchg_exit:
2137 DBEXIT(BCE_VERBOSE_PHY);
2141 /****************************************************************************/
2142 /* Acquire NVRAM lock. */
2144 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */
2145 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
2146 /* for use by the driver. */
2149 /* 0 on success, positive value on failure. */
2150 /****************************************************************************/
2152 bce_acquire_nvram_lock(struct bce_softc *sc)
2157 DBENTER(BCE_VERBOSE_NVRAM);
2159 /* Request access to the flash interface. */
2160 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
2161 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2162 val = REG_RD(sc, BCE_NVM_SW_ARB);
2163 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
2169 if (j >= NVRAM_TIMEOUT_COUNT) {
2170 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
2174 DBEXIT(BCE_VERBOSE_NVRAM);
2179 /****************************************************************************/
2180 /* Release NVRAM lock. */
2182 /* When the caller is finished accessing NVRAM the lock must be released. */
2183 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
2184 /* for use by the driver. */
2187 /* 0 on success, positive value on failure. */
2188 /****************************************************************************/
2190 bce_release_nvram_lock(struct bce_softc *sc)
2195 DBENTER(BCE_VERBOSE_NVRAM);
2198 * Relinquish nvram interface.
2200 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
2202 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2203 val = REG_RD(sc, BCE_NVM_SW_ARB);
2204 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
2210 if (j >= NVRAM_TIMEOUT_COUNT) {
2211 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n");
2215 DBEXIT(BCE_VERBOSE_NVRAM);
2220 #ifdef BCE_NVRAM_WRITE_SUPPORT
2221 /****************************************************************************/
2222 /* Enable NVRAM write access. */
2224 /* Before writing to NVRAM the caller must enable NVRAM writes. */
2227 /* 0 on success, positive value on failure. */
2228 /****************************************************************************/
2230 bce_enable_nvram_write(struct bce_softc *sc)
2235 DBENTER(BCE_VERBOSE_NVRAM);
2237 val = REG_RD(sc, BCE_MISC_CFG);
2238 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);
2240 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2243 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2244 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT);
2246 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2249 val = REG_RD(sc, BCE_NVM_COMMAND);
2250 if (val & BCE_NVM_COMMAND_DONE)
2254 if (j >= NVRAM_TIMEOUT_COUNT) {
2255 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n");
2260 DBENTER(BCE_VERBOSE_NVRAM);
2265 /****************************************************************************/
2266 /* Disable NVRAM write access. */
2268 /* When the caller is finished writing to NVRAM write access must be */
2273 /****************************************************************************/
2275 bce_disable_nvram_write(struct bce_softc *sc)
2279 DBENTER(BCE_VERBOSE_NVRAM);
2281 val = REG_RD(sc, BCE_MISC_CFG);
2282 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);
2284 DBEXIT(BCE_VERBOSE_NVRAM);
2290 /****************************************************************************/
2291 /* Enable NVRAM access. */
2293 /* Before accessing NVRAM for read or write operations the caller must */
2294 /* enabled NVRAM access. */
2298 /****************************************************************************/
2300 bce_enable_nvram_access(struct bce_softc *sc)
2304 DBENTER(BCE_VERBOSE_NVRAM);
2306 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
2307 /* Enable both bits, even on read. */
2308 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val |
2309 BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
2311 DBEXIT(BCE_VERBOSE_NVRAM);
2315 /****************************************************************************/
2316 /* Disable NVRAM access. */
2318 /* When the caller is finished accessing NVRAM access must be disabled. */
2322 /****************************************************************************/
2324 bce_disable_nvram_access(struct bce_softc *sc)
2328 DBENTER(BCE_VERBOSE_NVRAM);
2330 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
2332 /* Disable both bits, even after read. */
2333 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val &
2334 ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
2336 DBEXIT(BCE_VERBOSE_NVRAM);
2340 #ifdef BCE_NVRAM_WRITE_SUPPORT
2341 /****************************************************************************/
2342 /* Erase NVRAM page before writing. */
2344 /* Non-buffered flash parts require that a page be erased before it is */
2348 /* 0 on success, positive value on failure. */
2349 /****************************************************************************/
2351 bce_nvram_erase_page(struct bce_softc *sc, u32 offset)
2356 DBENTER(BCE_VERBOSE_NVRAM);
2358 /* Buffered flash doesn't require an erase. */
2359 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED)
2360 goto bce_nvram_erase_page_exit;
2362 /* Build an erase command. */
2363 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR |
2364 BCE_NVM_COMMAND_DOIT;
2367 * Clear the DONE bit separately, set the NVRAM address to erase,
2368 * and issue the erase command.
2370 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2371 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2372 REG_WR(sc, BCE_NVM_COMMAND, cmd);
2374 /* Wait for completion. */
2375 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2380 val = REG_RD(sc, BCE_NVM_COMMAND);
2381 if (val & BCE_NVM_COMMAND_DONE)
2385 if (j >= NVRAM_TIMEOUT_COUNT) {
2386 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n");
2390 bce_nvram_erase_page_exit:
2391 DBEXIT(BCE_VERBOSE_NVRAM);
2394 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2397 /****************************************************************************/
2398 /* Read a dword (32 bits) from NVRAM. */
2400 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */
2401 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */
2404 /* 0 on success and the 32 bit value read, positive value on failure. */
2405 /****************************************************************************/
2407 bce_nvram_read_dword(struct bce_softc *sc,
2408 u32 offset, u8 *ret_val, u32 cmd_flags)
2413 DBENTER(BCE_EXTREME_NVRAM);
2415 /* Build the command word. */
2416 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
2418 /* Calculate the offset for buffered flash if translation is used. */
2419 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2420 offset = ((offset / sc->bce_flash_info->page_size) <<
2421 sc->bce_flash_info->page_bits) +
2422 (offset % sc->bce_flash_info->page_size);
2426 * Clear the DONE bit separately, set the address to read,
2427 * and issue the read.
2429 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2430 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2431 REG_WR(sc, BCE_NVM_COMMAND, cmd);
2433 /* Wait for completion. */
2434 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
2439 val = REG_RD(sc, BCE_NVM_COMMAND);
2440 if (val & BCE_NVM_COMMAND_DONE) {
2441 val = REG_RD(sc, BCE_NVM_READ);
2443 val = bce_be32toh(val);
2444 memcpy(ret_val, &val, 4);
2449 /* Check for errors. */
2450 if (i >= NVRAM_TIMEOUT_COUNT) {
2451 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at "
2452 "offset 0x%08X!\n", __FILE__, __LINE__, offset);
2456 DBEXIT(BCE_EXTREME_NVRAM);
2461 #ifdef BCE_NVRAM_WRITE_SUPPORT
2462 /****************************************************************************/
2463 /* Write a dword (32 bits) to NVRAM. */
2465 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */
2466 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */
2467 /* enabled NVRAM write access. */
2470 /* 0 on success, positive value on failure. */
2471 /****************************************************************************/
2473 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val,
2479 DBENTER(BCE_VERBOSE_NVRAM);
2481 /* Build the command word. */
2482 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags;
2484 /* Calculate the offset for buffered flash if translation is used. */
2485 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2486 offset = ((offset / sc->bce_flash_info->page_size) <<
2487 sc->bce_flash_info->page_bits) +
2488 (offset % sc->bce_flash_info->page_size);
2492 * Clear the DONE bit separately, convert NVRAM data to big-endian,
2493 * set the NVRAM address to write, and issue the write command
2495 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2496 memcpy(&val32, val, 4);
2497 val32 = htobe32(val32);
2498 REG_WR(sc, BCE_NVM_WRITE, val32);
2499 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2500 REG_WR(sc, BCE_NVM_COMMAND, cmd);
2502 /* Wait for completion. */
2503 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2506 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE)
2509 if (j >= NVRAM_TIMEOUT_COUNT) {
2510 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at "
2511 "offset 0x%08X\n", __FILE__, __LINE__, offset);
2515 DBEXIT(BCE_VERBOSE_NVRAM);
2518 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2521 /****************************************************************************/
2522 /* Initialize NVRAM access. */
2524 /* Identify the NVRAM device in use and prepare the NVRAM interface to */
2525 /* access that device. */
2528 /* 0 on success, positive value on failure. */
2529 /****************************************************************************/
2531 bce_init_nvram(struct bce_softc *sc)
2534 int j, entry_count, rc = 0;
2535 const struct flash_spec *flash;
2537 DBENTER(BCE_VERBOSE_NVRAM);
2539 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
2540 sc->bce_flash_info = &flash_5709;
2541 goto bce_init_nvram_get_flash_size;
2544 /* Determine the selected interface. */
2545 val = REG_RD(sc, BCE_NVM_CFG1);
2547 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2550 * Flash reconfiguration is required to support additional
2551 * NVRAM devices not directly supported in hardware.
2552 * Check if the flash interface was reconfigured
2556 if (val & 0x40000000) {
2557 /* Flash interface reconfigured by bootcode. */
2559 DBPRINT(sc,BCE_INFO_LOAD,
2560 "bce_init_nvram(): Flash WAS reconfigured.\n");
2562 for (j = 0, flash = &flash_table[0]; j < entry_count;
2564 if ((val & FLASH_BACKUP_STRAP_MASK) ==
2565 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2566 sc->bce_flash_info = flash;
2571 /* Flash interface not yet reconfigured. */
2574 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n",
2577 if (val & (1 << 23))
2578 mask = FLASH_BACKUP_STRAP_MASK;
2580 mask = FLASH_STRAP_MASK;
2582 /* Look for the matching NVRAM device configuration data. */
2583 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) {
2585 /* Check if the device matches any of the known devices. */
2586 if ((val & mask) == (flash->strapping & mask)) {
2587 /* Found a device match. */
2588 sc->bce_flash_info = flash;
2590 /* Request access to the flash interface. */
2591 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2594 /* Reconfigure the flash interface. */
2595 bce_enable_nvram_access(sc);
2596 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
2597 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
2598 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
2599 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
2600 bce_disable_nvram_access(sc);
2601 bce_release_nvram_lock(sc);
2608 /* Check if a matching device was found. */
2609 if (j == entry_count) {
2610 sc->bce_flash_info = NULL;
2611 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n",
2612 __FILE__, __LINE__);
2613 DBEXIT(BCE_VERBOSE_NVRAM);
2617 bce_init_nvram_get_flash_size:
2618 /* Write the flash config data to the shared memory interface. */
2619 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2);
2620 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
2622 sc->bce_flash_size = val;
2624 sc->bce_flash_size = sc->bce_flash_info->total_size;
2626 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n",
2627 __FUNCTION__, sc->bce_flash_info->name,
2628 sc->bce_flash_info->total_size);
2630 DBEXIT(BCE_VERBOSE_NVRAM);
2635 /****************************************************************************/
2636 /* Read an arbitrary range of data from NVRAM. */
2638 /* Prepares the NVRAM interface for access and reads the requested data */
2639 /* into the supplied buffer. */
2642 /* 0 on success and the data read, positive value on failure. */
2643 /****************************************************************************/
2645 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf,
2649 u32 cmd_flags, offset32, len32, extra;
2651 DBENTER(BCE_VERBOSE_NVRAM);
2654 goto bce_nvram_read_exit;
2656 /* Request access to the flash interface. */
2657 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2658 goto bce_nvram_read_exit;
2660 /* Enable access to flash interface */
2661 bce_enable_nvram_access(sc);
2674 pre_len = 4 - (offset & 3);
2676 if (pre_len >= len32) {
2678 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
2681 cmd_flags = BCE_NVM_COMMAND_FIRST;
2684 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2689 memcpy(ret_buf, buf + (offset & 3), pre_len);
2697 extra = 4 - (len32 & 3);
2698 len32 = (len32 + 4) & ~3;
2705 cmd_flags = BCE_NVM_COMMAND_LAST;
2707 cmd_flags = BCE_NVM_COMMAND_FIRST |
2708 BCE_NVM_COMMAND_LAST;
2710 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2712 memcpy(ret_buf, buf, 4 - extra);
2714 else if (len32 > 0) {
2717 /* Read the first word. */
2721 cmd_flags = BCE_NVM_COMMAND_FIRST;
2723 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
2725 /* Advance to the next dword. */
2730 while (len32 > 4 && rc == 0) {
2731 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
2733 /* Advance to the next dword. */
2740 goto bce_nvram_read_locked_exit;
2742 cmd_flags = BCE_NVM_COMMAND_LAST;
2743 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2745 memcpy(ret_buf, buf, 4 - extra);
2748 bce_nvram_read_locked_exit:
2749 /* Disable access to flash interface and release the lock. */
2750 bce_disable_nvram_access(sc);
2751 bce_release_nvram_lock(sc);
2753 bce_nvram_read_exit:
2754 DBEXIT(BCE_VERBOSE_NVRAM);
2759 #ifdef BCE_NVRAM_WRITE_SUPPORT
2760 /****************************************************************************/
2761 /* Write an arbitrary range of data from NVRAM. */
2763 /* Prepares the NVRAM interface for write access and writes the requested */
2764 /* data from the supplied buffer. The caller is responsible for */
2765 /* calculating any appropriate CRCs. */
2768 /* 0 on success, positive value on failure. */
2769 /****************************************************************************/
2771 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf,
2774 u32 written, offset32, len32;
2775 u8 *buf, start[4], end[4];
2777 int align_start, align_end;
2779 DBENTER(BCE_VERBOSE_NVRAM);
2784 align_start = align_end = 0;
2786 if ((align_start = (offset32 & 3))) {
2788 len32 += align_start;
2789 if ((rc = bce_nvram_read(sc, offset32, start, 4)))
2790 goto bce_nvram_write_exit;
2794 if ((len32 > 4) || !align_start) {
2795 align_end = 4 - (len32 & 3);
2797 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4,
2799 goto bce_nvram_write_exit;
2804 if (align_start || align_end) {
2805 buf = malloc(len32, M_DEVBUF, M_NOWAIT);
2808 goto bce_nvram_write_exit;
2812 memcpy(buf, start, 4);
2816 memcpy(buf + len32 - 4, end, 4);
2818 memcpy(buf + align_start, data_buf, buf_size);
2822 while ((written < len32) && (rc == 0)) {
2823 u32 page_start, page_end, data_start, data_end;
2824 u32 addr, cmd_flags;
2826 u8 flash_buffer[264];
2828 /* Find the page_start addr */
2829 page_start = offset32 + written;
2830 page_start -= (page_start % sc->bce_flash_info->page_size);
2831 /* Find the page_end addr */
2832 page_end = page_start + sc->bce_flash_info->page_size;
2833 /* Find the data_start addr */
2834 data_start = (written == 0) ? offset32 : page_start;
2835 /* Find the data_end addr */
2836 data_end = (page_end > offset32 + len32) ?
2837 (offset32 + len32) : page_end;
2839 /* Request access to the flash interface. */
2840 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2841 goto bce_nvram_write_exit;
2843 /* Enable access to flash interface */
2844 bce_enable_nvram_access(sc);
2846 cmd_flags = BCE_NVM_COMMAND_FIRST;
2847 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2850 /* Read the whole page into the buffer
2851 * (non-buffer flash only) */
2852 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) {
2853 if (j == (sc->bce_flash_info->page_size - 4)) {
2854 cmd_flags |= BCE_NVM_COMMAND_LAST;
2856 rc = bce_nvram_read_dword(sc,
2862 goto bce_nvram_write_locked_exit;
2868 /* Enable writes to flash interface (unlock write-protect) */
2869 if ((rc = bce_enable_nvram_write(sc)) != 0)
2870 goto bce_nvram_write_locked_exit;
2872 /* Erase the page */
2873 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0)
2874 goto bce_nvram_write_locked_exit;
2876 /* Re-enable the write again for the actual write */
2877 bce_enable_nvram_write(sc);
2879 /* Loop to write back the buffer data from page_start to
2882 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2883 for (addr = page_start; addr < data_start;
2884 addr += 4, i += 4) {
2886 rc = bce_nvram_write_dword(sc, addr,
2887 &flash_buffer[i], cmd_flags);
2890 goto bce_nvram_write_locked_exit;
2896 /* Loop to write the new data from data_start to data_end */
2897 for (addr = data_start; addr < data_end; addr += 4, i++) {
2898 if ((addr == page_end - 4) ||
2899 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) &&
2900 (addr == data_end - 4))) {
2902 cmd_flags |= BCE_NVM_COMMAND_LAST;
2904 rc = bce_nvram_write_dword(sc, addr, buf,
2908 goto bce_nvram_write_locked_exit;
2914 /* Loop to write back the buffer data from data_end
2916 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2917 for (addr = data_end; addr < page_end;
2918 addr += 4, i += 4) {
2920 if (addr == page_end-4) {
2921 cmd_flags = BCE_NVM_COMMAND_LAST;
2923 rc = bce_nvram_write_dword(sc, addr,
2924 &flash_buffer[i], cmd_flags);
2927 goto bce_nvram_write_locked_exit;
2933 /* Disable writes to flash interface (lock write-protect) */
2934 bce_disable_nvram_write(sc);
2936 /* Disable access to flash interface */
2937 bce_disable_nvram_access(sc);
2938 bce_release_nvram_lock(sc);
2940 /* Increment written */
2941 written += data_end - data_start;
2944 goto bce_nvram_write_exit;
2946 bce_nvram_write_locked_exit:
2947 bce_disable_nvram_write(sc);
2948 bce_disable_nvram_access(sc);
2949 bce_release_nvram_lock(sc);
2951 bce_nvram_write_exit:
2952 if (align_start || align_end)
2953 free(buf, M_DEVBUF);
2955 DBEXIT(BCE_VERBOSE_NVRAM);
2958 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2961 /****************************************************************************/
2962 /* Verifies that NVRAM is accessible and contains valid data. */
2964 /* Reads the configuration data from NVRAM and verifies that the CRC is */
2968 /* 0 on success, positive value on failure. */
2969 /****************************************************************************/
2971 bce_nvram_test(struct bce_softc *sc)
2973 u32 buf[BCE_NVRAM_SIZE / 4];
2974 u8 *data = (u8 *) buf;
2978 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
2981 * Check that the device NVRAM is valid by reading
2982 * the magic value at offset 0.
2984 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) {
2985 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n",
2986 __FILE__, __LINE__);
2987 goto bce_nvram_test_exit;
2991 * Verify that offset 0 of the NVRAM contains
2992 * a valid magic number.
2994 magic = bce_be32toh(buf[0]);
2995 if (magic != BCE_NVRAM_MAGIC) {
2997 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! "
2998 "Expected: 0x%08X, Found: 0x%08X\n",
2999 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic);
3000 goto bce_nvram_test_exit;
3004 * Verify that the device NVRAM includes valid
3005 * configuration data.
3007 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) {
3008 BCE_PRINTF("%s(%d): Unable to read manufacturing "
3009 "Information from NVRAM!\n", __FILE__, __LINE__);
3010 goto bce_nvram_test_exit;
3013 csum = ether_crc32_le(data, 0x100);
3014 if (csum != BCE_CRC32_RESIDUAL) {
3016 BCE_PRINTF("%s(%d): Invalid manufacturing information "
3017 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n",
3018 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum);
3019 goto bce_nvram_test_exit;
3022 csum = ether_crc32_le(data + 0x100, 0x100);
3023 if (csum != BCE_CRC32_RESIDUAL) {
3025 BCE_PRINTF("%s(%d): Invalid feature configuration "
3026 "information NVRAM CRC! Expected: 0x%08X, "
3027 "Found: 08%08X\n", __FILE__, __LINE__,
3028 BCE_CRC32_RESIDUAL, csum);
3031 bce_nvram_test_exit:
3032 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
3037 /****************************************************************************/
3038 /* Calculates the size of the buffers to allocate based on the MTU. */
3042 /****************************************************************************/
3044 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu)
3046 DBENTER(BCE_VERBOSE_LOAD);
3048 /* Use a single allocation type when header splitting enabled. */
3049 if (bce_hdr_split == TRUE) {
3050 sc->rx_bd_mbuf_alloc_size = MHLEN;
3051 /* Make sure offset is 16 byte aligned for hardware. */
3052 sc->rx_bd_mbuf_align_pad =
3053 roundup2(MSIZE - MHLEN, 16) - (MSIZE - MHLEN);
3054 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
3055 sc->rx_bd_mbuf_align_pad;
3057 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
3058 ETHER_CRC_LEN) > MCLBYTES) {
3059 /* Setup for jumbo RX buffer allocations. */
3060 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES;
3061 sc->rx_bd_mbuf_align_pad =
3062 roundup2(MJUM9BYTES, 16) - MJUM9BYTES;
3063 sc->rx_bd_mbuf_data_len =
3064 sc->rx_bd_mbuf_alloc_size -
3065 sc->rx_bd_mbuf_align_pad;
3067 /* Setup for standard RX buffer allocations. */
3068 sc->rx_bd_mbuf_alloc_size = MCLBYTES;
3069 sc->rx_bd_mbuf_align_pad =
3070 roundup2(MCLBYTES, 16) - MCLBYTES;
3071 sc->rx_bd_mbuf_data_len =
3072 sc->rx_bd_mbuf_alloc_size -
3073 sc->rx_bd_mbuf_align_pad;
3077 // DBPRINT(sc, BCE_INFO_LOAD,
3078 DBPRINT(sc, BCE_WARN,
3079 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, "
3080 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__,
3081 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len,
3082 sc->rx_bd_mbuf_align_pad);
3084 DBEXIT(BCE_VERBOSE_LOAD);
3087 /****************************************************************************/
3088 /* Identifies the current media type of the controller and sets the PHY */
3093 /****************************************************************************/
3095 bce_get_media(struct bce_softc *sc)
3099 DBENTER(BCE_VERBOSE_PHY);
3101 /* Assume PHY address for copper controllers. */
3102 sc->bce_phy_addr = 1;
3104 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3105 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
3106 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
3110 * The BCM5709S is software configurable
3111 * for Copper or SerDes operation.
3113 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
3114 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
3116 goto bce_get_media_exit;
3117 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
3118 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
3119 "for dual media.\n");
3120 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3121 goto bce_get_media_exit;
3124 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
3126 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
3129 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
3131 if (pci_get_function(sc->bce_dev) == 0) {
3136 DBPRINT(sc, BCE_INFO_LOAD,
3137 "BCM5709 s/w configured for SerDes.\n");
3138 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3141 DBPRINT(sc, BCE_INFO_LOAD,
3142 "BCM5709 s/w configured for Copper.\n");
3150 DBPRINT(sc, BCE_INFO_LOAD,
3151 "BCM5709 s/w configured for SerDes.\n");
3152 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3155 DBPRINT(sc, BCE_INFO_LOAD,
3156 "BCM5709 s/w configured for Copper.\n");
3161 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT)
3162 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3164 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
3166 sc->bce_flags |= BCE_NO_WOL_FLAG;
3168 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
3169 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG;
3171 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
3172 /* 5708S/09S/16S use a separate PHY for SerDes. */
3173 sc->bce_phy_addr = 2;
3175 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
3176 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) {
3177 sc->bce_phy_flags |=
3178 BCE_PHY_2_5G_CAPABLE_FLAG;
3179 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb "
3180 "capable adapter\n");
3183 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
3184 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708))
3185 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
3188 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY),
3189 "Using PHY address %d.\n", sc->bce_phy_addr);
3191 DBEXIT(BCE_VERBOSE_PHY);
3195 /****************************************************************************/
3196 /* Performs PHY initialization required before MII drivers access the */
3201 /****************************************************************************/
3203 bce_init_media(struct bce_softc *sc)
3205 if ((sc->bce_phy_flags & (BCE_PHY_IEEE_CLAUSE_45_FLAG |
3206 BCE_PHY_REMOTE_CAP_FLAG)) == BCE_PHY_IEEE_CLAUSE_45_FLAG) {
3208 * Configure 5709S/5716S PHYs to use traditional IEEE
3209 * Clause 22 method. Otherwise we have no way to attach
3210 * the PHY in mii(4) layer. PHY specific configuration
3211 * is done in mii layer.
3214 /* Select auto-negotiation MMD of the PHY. */
3215 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3216 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT);
3217 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3218 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD);
3220 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */
3221 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3222 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
3227 /****************************************************************************/
3228 /* Free any DMA memory owned by the driver. */
3230 /* Scans through each data structre that requires DMA memory and frees */
3231 /* the memory if allocated. */
3235 /****************************************************************************/
3237 bce_dma_free(struct bce_softc *sc)
3241 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
3243 /* Free, unmap, and destroy the status block. */
3244 if (sc->status_block_paddr != 0) {
3248 sc->status_block_paddr = 0;
3251 if (sc->status_block != NULL) {
3256 sc->status_block = NULL;
3259 if (sc->status_tag != NULL) {
3260 bus_dma_tag_destroy(sc->status_tag);
3261 sc->status_tag = NULL;
3265 /* Free, unmap, and destroy the statistics block. */
3266 if (sc->stats_block_paddr != 0) {
3270 sc->stats_block_paddr = 0;
3273 if (sc->stats_block != NULL) {
3278 sc->stats_block = NULL;
3281 if (sc->stats_tag != NULL) {
3282 bus_dma_tag_destroy(sc->stats_tag);
3283 sc->stats_tag = NULL;
3287 /* Free, unmap and destroy all context memory pages. */
3288 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3289 for (i = 0; i < sc->ctx_pages; i++ ) {
3290 if (sc->ctx_paddr[i] != 0) {
3294 sc->ctx_paddr[i] = 0;
3297 if (sc->ctx_block[i] != NULL) {
3302 sc->ctx_block[i] = NULL;
3306 /* Destroy the context memory tag. */
3307 if (sc->ctx_tag != NULL) {
3308 bus_dma_tag_destroy(sc->ctx_tag);
3314 /* Free, unmap and destroy all TX buffer descriptor chain pages. */
3315 for (i = 0; i < sc->tx_pages; i++ ) {
3316 if (sc->tx_bd_chain_paddr[i] != 0) {
3318 sc->tx_bd_chain_tag,
3319 sc->tx_bd_chain_map[i]);
3320 sc->tx_bd_chain_paddr[i] = 0;
3323 if (sc->tx_bd_chain[i] != NULL) {
3325 sc->tx_bd_chain_tag,
3327 sc->tx_bd_chain_map[i]);
3328 sc->tx_bd_chain[i] = NULL;
3332 /* Destroy the TX buffer descriptor tag. */
3333 if (sc->tx_bd_chain_tag != NULL) {
3334 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
3335 sc->tx_bd_chain_tag = NULL;
3339 /* Free, unmap and destroy all RX buffer descriptor chain pages. */
3340 for (i = 0; i < sc->rx_pages; i++ ) {
3341 if (sc->rx_bd_chain_paddr[i] != 0) {
3343 sc->rx_bd_chain_tag,
3344 sc->rx_bd_chain_map[i]);
3345 sc->rx_bd_chain_paddr[i] = 0;
3348 if (sc->rx_bd_chain[i] != NULL) {
3350 sc->rx_bd_chain_tag,
3352 sc->rx_bd_chain_map[i]);
3353 sc->rx_bd_chain[i] = NULL;
3357 /* Destroy the RX buffer descriptor tag. */
3358 if (sc->rx_bd_chain_tag != NULL) {
3359 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
3360 sc->rx_bd_chain_tag = NULL;
3364 /* Free, unmap and destroy all page buffer descriptor chain pages. */
3365 if (bce_hdr_split == TRUE) {
3366 for (i = 0; i < sc->pg_pages; i++ ) {
3367 if (sc->pg_bd_chain_paddr[i] != 0) {
3369 sc->pg_bd_chain_tag,
3370 sc->pg_bd_chain_map[i]);
3371 sc->pg_bd_chain_paddr[i] = 0;
3374 if (sc->pg_bd_chain[i] != NULL) {
3376 sc->pg_bd_chain_tag,
3378 sc->pg_bd_chain_map[i]);
3379 sc->pg_bd_chain[i] = NULL;
3383 /* Destroy the page buffer descriptor tag. */
3384 if (sc->pg_bd_chain_tag != NULL) {
3385 bus_dma_tag_destroy(sc->pg_bd_chain_tag);
3386 sc->pg_bd_chain_tag = NULL;
3391 /* Unload and destroy the TX mbuf maps. */
3392 for (i = 0; i < MAX_TX_BD_AVAIL; i++) {
3393 if (sc->tx_mbuf_map[i] != NULL) {
3394 bus_dmamap_unload(sc->tx_mbuf_tag,
3395 sc->tx_mbuf_map[i]);
3396 bus_dmamap_destroy(sc->tx_mbuf_tag,
3397 sc->tx_mbuf_map[i]);
3398 sc->tx_mbuf_map[i] = NULL;
3402 /* Destroy the TX mbuf tag. */
3403 if (sc->tx_mbuf_tag != NULL) {
3404 bus_dma_tag_destroy(sc->tx_mbuf_tag);
3405 sc->tx_mbuf_tag = NULL;
3408 /* Unload and destroy the RX mbuf maps. */
3409 for (i = 0; i < MAX_RX_BD_AVAIL; i++) {
3410 if (sc->rx_mbuf_map[i] != NULL) {
3411 bus_dmamap_unload(sc->rx_mbuf_tag,
3412 sc->rx_mbuf_map[i]);
3413 bus_dmamap_destroy(sc->rx_mbuf_tag,
3414 sc->rx_mbuf_map[i]);
3415 sc->rx_mbuf_map[i] = NULL;
3419 /* Destroy the RX mbuf tag. */
3420 if (sc->rx_mbuf_tag != NULL) {
3421 bus_dma_tag_destroy(sc->rx_mbuf_tag);
3422 sc->rx_mbuf_tag = NULL;
3425 /* Unload and destroy the page mbuf maps. */
3426 if (bce_hdr_split == TRUE) {
3427 for (i = 0; i < MAX_PG_BD_AVAIL; i++) {
3428 if (sc->pg_mbuf_map[i] != NULL) {
3429 bus_dmamap_unload(sc->pg_mbuf_tag,
3430 sc->pg_mbuf_map[i]);
3431 bus_dmamap_destroy(sc->pg_mbuf_tag,
3432 sc->pg_mbuf_map[i]);
3433 sc->pg_mbuf_map[i] = NULL;
3437 /* Destroy the page mbuf tag. */
3438 if (sc->pg_mbuf_tag != NULL) {
3439 bus_dma_tag_destroy(sc->pg_mbuf_tag);
3440 sc->pg_mbuf_tag = NULL;
3444 /* Destroy the parent tag */
3445 if (sc->parent_tag != NULL) {
3446 bus_dma_tag_destroy(sc->parent_tag);
3447 sc->parent_tag = NULL;
3450 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
3454 /****************************************************************************/
3455 /* Get DMA memory from the OS. */
3457 /* Validates that the OS has provided DMA buffers in response to a */
3458 /* bus_dmamap_load() call and saves the physical address of those buffers. */
3459 /* When the callback is used the OS will return 0 for the mapping function */
3460 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */
3461 /* failures back to the caller. */
3465 /****************************************************************************/
3467 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3469 bus_addr_t *busaddr = arg;
3471 KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!",
3472 __FUNCTION__, nseg));
3473 /* Simulate a mapping failure. */
3474 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control),
3477 /* ToDo: How to increment debug sim_count variable here? */
3479 /* Check for an error and signal the caller that an error occurred. */
3483 *busaddr = segs->ds_addr;
3488 /****************************************************************************/
3489 /* Allocate any DMA memory needed by the driver. */
3491 /* Allocates DMA memory needed for the various global structures needed by */
3494 /* Memory alignment requirements: */
3495 /* +-----------------+----------+----------+----------+----------+ */
3496 /* | | 5706 | 5708 | 5709 | 5716 | */
3497 /* +-----------------+----------+----------+----------+----------+ */
3498 /* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
3499 /* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
3500 /* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */
3501 /* |PG Buffers | none | none | none | none | */
3502 /* |TX Buffers | none | none | none | none | */
3503 /* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */
3504 /* |Context Memory | | | | | */
3505 /* +-----------------+----------+----------+----------+----------+ */
3507 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */
3510 /* 0 for success, positive value for failure. */
3511 /****************************************************************************/
3513 bce_dma_alloc(device_t dev)
3515 struct bce_softc *sc;
3516 int i, error, rc = 0;
3517 bus_size_t max_size, max_seg_size;
3520 sc = device_get_softc(dev);
3522 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3525 * Allocate the parent bus DMA tag appropriate for PCI.
3527 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY,
3528 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3529 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
3531 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n",
3532 __FILE__, __LINE__);
3534 goto bce_dma_alloc_exit;
3538 * Create a DMA tag for the status block, allocate and clear the
3539 * memory, map the memory into DMA space, and fetch the physical
3540 * address of the block.
3542 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3543 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3544 NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ,
3545 0, NULL, NULL, &sc->status_tag)) {
3546 BCE_PRINTF("%s(%d): Could not allocate status block "
3547 "DMA tag!\n", __FILE__, __LINE__);
3549 goto bce_dma_alloc_exit;
3552 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block,
3553 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3555 BCE_PRINTF("%s(%d): Could not allocate status block "
3556 "DMA memory!\n", __FILE__, __LINE__);
3558 goto bce_dma_alloc_exit;
3561 error = bus_dmamap_load(sc->status_tag, sc->status_map,
3562 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr,
3563 &sc->status_block_paddr, BUS_DMA_NOWAIT);
3565 if (error || sc->status_block_paddr == 0) {
3566 BCE_PRINTF("%s(%d): Could not map status block "
3567 "DMA memory!\n", __FILE__, __LINE__);
3569 goto bce_dma_alloc_exit;
3572 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n",
3573 __FUNCTION__, (uintmax_t) sc->status_block_paddr);
3576 * Create a DMA tag for the statistics block, allocate and clear the
3577 * memory, map the memory into DMA space, and fetch the physical
3578 * address of the block.
3580 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3581 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3582 NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ,
3583 0, NULL, NULL, &sc->stats_tag)) {
3584 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3585 "DMA tag!\n", __FILE__, __LINE__);
3587 goto bce_dma_alloc_exit;
3590 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block,
3591 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) {
3592 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3593 "DMA memory!\n", __FILE__, __LINE__);
3595 goto bce_dma_alloc_exit;
3598 error = bus_dmamap_load(sc->stats_tag, sc->stats_map,
3599 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr,
3600 &sc->stats_block_paddr, BUS_DMA_NOWAIT);
3602 if (error || sc->stats_block_paddr == 0) {
3603 BCE_PRINTF("%s(%d): Could not map statistics block "
3604 "DMA memory!\n", __FILE__, __LINE__);
3606 goto bce_dma_alloc_exit;
3609 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n",
3610 __FUNCTION__, (uintmax_t) sc->stats_block_paddr);
3612 /* BCM5709 uses host memory as cache for context memory. */
3613 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3614 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
3615 if (sc->ctx_pages == 0)
3618 DBRUNIF((sc->ctx_pages > 512),
3619 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n",
3620 __FILE__, __LINE__, sc->ctx_pages));
3623 * Create a DMA tag for the context pages,
3624 * allocate and clear the memory, map the
3625 * memory into DMA space, and fetch the
3626 * physical address of the block.
3628 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3629 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3630 NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
3631 0, NULL, NULL, &sc->ctx_tag)) {
3632 BCE_PRINTF("%s(%d): Could not allocate CTX "
3633 "DMA tag!\n", __FILE__, __LINE__);
3635 goto bce_dma_alloc_exit;
3638 for (i = 0; i < sc->ctx_pages; i++) {
3640 if(bus_dmamem_alloc(sc->ctx_tag,
3641 (void **)&sc->ctx_block[i],
3642 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3644 BCE_PRINTF("%s(%d): Could not allocate CTX "
3645 "DMA memory!\n", __FILE__, __LINE__);
3647 goto bce_dma_alloc_exit;
3650 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
3651 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr,
3652 &sc->ctx_paddr[i], BUS_DMA_NOWAIT);
3654 if (error || sc->ctx_paddr[i] == 0) {
3655 BCE_PRINTF("%s(%d): Could not map CTX "
3656 "DMA memory!\n", __FILE__, __LINE__);
3658 goto bce_dma_alloc_exit;
3661 DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] "
3662 "= 0x%jX\n", __FUNCTION__, i,
3663 (uintmax_t) sc->ctx_paddr[i]);
3668 * Create a DMA tag for the TX buffer descriptor chain,
3669 * allocate and clear the memory, and fetch the
3670 * physical address of the block.
3672 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY,
3673 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3674 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0,
3675 NULL, NULL, &sc->tx_bd_chain_tag)) {
3676 BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3677 "chain DMA tag!\n", __FILE__, __LINE__);
3679 goto bce_dma_alloc_exit;
3682 for (i = 0; i < sc->tx_pages; i++) {
3684 if(bus_dmamem_alloc(sc->tx_bd_chain_tag,
3685 (void **)&sc->tx_bd_chain[i],
3686 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3687 &sc->tx_bd_chain_map[i])) {
3688 BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3689 "chain DMA memory!\n", __FILE__, __LINE__);
3691 goto bce_dma_alloc_exit;
3694 error = bus_dmamap_load(sc->tx_bd_chain_tag,
3695 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i],
3696 BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3697 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3699 if (error || sc->tx_bd_chain_paddr[i] == 0) {
3700 BCE_PRINTF("%s(%d): Could not map TX descriptor "
3701 "chain DMA memory!\n", __FILE__, __LINE__);
3703 goto bce_dma_alloc_exit;
3706 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = "
3707 "0x%jX\n", __FUNCTION__, i,
3708 (uintmax_t) sc->tx_bd_chain_paddr[i]);
3711 /* Check the required size before mapping to conserve resources. */
3712 if (bce_tso_enable) {
3713 max_size = BCE_TSO_MAX_SIZE;
3714 max_segments = BCE_MAX_SEGMENTS;
3715 max_seg_size = BCE_TSO_MAX_SEG_SIZE;
3717 max_size = MCLBYTES * BCE_MAX_SEGMENTS;
3718 max_segments = BCE_MAX_SEGMENTS;
3719 max_seg_size = MCLBYTES;
3722 /* Create a DMA tag for TX mbufs. */
3723 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3724 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size,
3725 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) {
3726 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n",
3727 __FILE__, __LINE__);
3729 goto bce_dma_alloc_exit;
3732 /* Create DMA maps for the TX mbufs clusters. */
3733 for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) {
3734 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT,
3735 &sc->tx_mbuf_map[i])) {
3736 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA "
3737 "map!\n", __FILE__, __LINE__);
3739 goto bce_dma_alloc_exit;
3744 * Create a DMA tag for the RX buffer descriptor chain,
3745 * allocate and clear the memory, and fetch the physical
3746 * address of the blocks.
3748 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3749 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR,
3750 sc->max_bus_addr, NULL, NULL,
3751 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
3752 0, NULL, NULL, &sc->rx_bd_chain_tag)) {
3753 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain "
3754 "DMA tag!\n", __FILE__, __LINE__);
3756 goto bce_dma_alloc_exit;
3759 for (i = 0; i < sc->rx_pages; i++) {
3761 if (bus_dmamem_alloc(sc->rx_bd_chain_tag,
3762 (void **)&sc->rx_bd_chain[i],
3763 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3764 &sc->rx_bd_chain_map[i])) {
3765 BCE_PRINTF("%s(%d): Could not allocate RX descriptor "
3766 "chain DMA memory!\n", __FILE__, __LINE__);
3768 goto bce_dma_alloc_exit;
3771 error = bus_dmamap_load(sc->rx_bd_chain_tag,
3772 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i],
3773 BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3774 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3776 if (error || sc->rx_bd_chain_paddr[i] == 0) {
3777 BCE_PRINTF("%s(%d): Could not map RX descriptor "
3778 "chain DMA memory!\n", __FILE__, __LINE__);
3780 goto bce_dma_alloc_exit;
3783 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = "
3784 "0x%jX\n", __FUNCTION__, i,
3785 (uintmax_t) sc->rx_bd_chain_paddr[i]);
3789 * Create a DMA tag for RX mbufs.
3791 if (bce_hdr_split == TRUE)
3792 max_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ?
3793 MCLBYTES : sc->rx_bd_mbuf_alloc_size);
3795 max_size = MJUM9BYTES;
3797 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag "
3798 "(max size = 0x%jX)\n", __FUNCTION__, (uintmax_t)max_size);
3800 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN,
3801 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3802 max_size, 1, max_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) {
3803 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n",
3804 __FILE__, __LINE__);
3806 goto bce_dma_alloc_exit;
3809 /* Create DMA maps for the RX mbuf clusters. */
3810 for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) {
3811 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT,
3812 &sc->rx_mbuf_map[i])) {
3813 BCE_PRINTF("%s(%d): Unable to create RX mbuf "
3814 "DMA map!\n", __FILE__, __LINE__);
3816 goto bce_dma_alloc_exit;
3820 if (bce_hdr_split == TRUE) {
3822 * Create a DMA tag for the page buffer descriptor chain,
3823 * allocate and clear the memory, and fetch the physical
3824 * address of the blocks.
3826 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3827 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr,
3828 NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ,
3829 0, NULL, NULL, &sc->pg_bd_chain_tag)) {
3830 BCE_PRINTF("%s(%d): Could not allocate page descriptor "
3831 "chain DMA tag!\n", __FILE__, __LINE__);
3833 goto bce_dma_alloc_exit;
3836 for (i = 0; i < sc->pg_pages; i++) {
3837 if (bus_dmamem_alloc(sc->pg_bd_chain_tag,
3838 (void **)&sc->pg_bd_chain[i],
3839 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3840 &sc->pg_bd_chain_map[i])) {
3841 BCE_PRINTF("%s(%d): Could not allocate page "
3842 "descriptor chain DMA memory!\n",
3843 __FILE__, __LINE__);
3845 goto bce_dma_alloc_exit;
3848 error = bus_dmamap_load(sc->pg_bd_chain_tag,
3849 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i],
3850 BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr,
3851 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3853 if (error || sc->pg_bd_chain_paddr[i] == 0) {
3854 BCE_PRINTF("%s(%d): Could not map page descriptor "
3855 "chain DMA memory!\n", __FILE__, __LINE__);
3857 goto bce_dma_alloc_exit;
3860 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = "
3861 "0x%jX\n", __FUNCTION__, i,
3862 (uintmax_t) sc->pg_bd_chain_paddr[i]);
3866 * Create a DMA tag for page mbufs.
3868 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3869 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
3870 1, MCLBYTES, 0, NULL, NULL, &sc->pg_mbuf_tag)) {
3871 BCE_PRINTF("%s(%d): Could not allocate page mbuf "
3872 "DMA tag!\n", __FILE__, __LINE__);
3874 goto bce_dma_alloc_exit;
3877 /* Create DMA maps for the page mbuf clusters. */
3878 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) {
3879 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT,
3880 &sc->pg_mbuf_map[i])) {
3881 BCE_PRINTF("%s(%d): Unable to create page mbuf "
3882 "DMA map!\n", __FILE__, __LINE__);
3884 goto bce_dma_alloc_exit;
3890 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3895 /****************************************************************************/
3896 /* Release all resources used by the driver. */
3898 /* Releases all resources acquired by the driver including interrupts, */
3899 /* interrupt handler, interfaces, mutexes, and DMA memory. */
3903 /****************************************************************************/
3905 bce_release_resources(struct bce_softc *sc)
3909 DBENTER(BCE_VERBOSE_RESET);
3915 if (sc->bce_intrhand != NULL) {
3916 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n");
3917 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
3920 if (sc->bce_res_irq != NULL) {
3921 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n");
3922 bus_release_resource(dev, SYS_RES_IRQ,
3923 rman_get_rid(sc->bce_res_irq), sc->bce_res_irq);
3926 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) {
3927 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n");
3928 pci_release_msi(dev);
3931 if (sc->bce_res_mem != NULL) {
3932 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n");
3933 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
3937 if (sc->bce_ifp != NULL) {
3938 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n");
3939 if_free(sc->bce_ifp);
3942 if (mtx_initialized(&sc->bce_mtx))
3943 BCE_LOCK_DESTROY(sc);
3945 DBEXIT(BCE_VERBOSE_RESET);
3949 /****************************************************************************/
3950 /* Firmware synchronization. */
3952 /* Before performing certain events such as a chip reset, synchronize with */
3953 /* the firmware first. */
3956 /* 0 for success, positive value for failure. */
3957 /****************************************************************************/
3959 bce_fw_sync(struct bce_softc *sc, u32 msg_data)
3964 DBENTER(BCE_VERBOSE_RESET);
3966 /* Don't waste any time if we've timed out before. */
3967 if (sc->bce_fw_timed_out == TRUE) {
3969 goto bce_fw_sync_exit;
3972 /* Increment the message sequence number. */
3973 sc->bce_fw_wr_seq++;
3974 msg_data |= sc->bce_fw_wr_seq;
3976 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = "
3977 "0x%08X\n", msg_data);
3979 /* Send the message to the bootcode driver mailbox. */
3980 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
3982 /* Wait for the bootcode to acknowledge the message. */
3983 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
3984 /* Check for a response in the bootcode firmware mailbox. */
3985 val = bce_shmem_rd(sc, BCE_FW_MB);
3986 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
3991 /* If we've timed out, tell bootcode that we've stopped waiting. */
3992 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) &&
3993 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) {
3995 BCE_PRINTF("%s(%d): Firmware synchronization timeout! "
3996 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data);
3998 msg_data &= ~BCE_DRV_MSG_CODE;
3999 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
4001 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
4003 sc->bce_fw_timed_out = TRUE;
4008 DBEXIT(BCE_VERBOSE_RESET);
4013 /****************************************************************************/
4014 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */
4018 /****************************************************************************/
4020 bce_load_rv2p_fw(struct bce_softc *sc, const u32 *rv2p_code,
4021 u32 rv2p_code_len, u32 rv2p_proc)
4026 DBENTER(BCE_VERBOSE_RESET);
4028 /* Set the page size used by RV2P. */
4029 if (rv2p_proc == RV2P_PROC2) {
4030 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE);
4033 for (i = 0; i < rv2p_code_len; i += 8) {
4034 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
4036 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
4039 if (rv2p_proc == RV2P_PROC1) {
4040 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
4041 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
4044 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
4045 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
4049 /* Reset the processor, un-stall is done later. */
4050 if (rv2p_proc == RV2P_PROC1) {
4051 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
4054 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
4057 DBEXIT(BCE_VERBOSE_RESET);
4061 /****************************************************************************/
4062 /* Load RISC processor firmware. */
4064 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */
4065 /* associated with a particular processor. */
4069 /****************************************************************************/
4071 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
4076 DBENTER(BCE_VERBOSE_RESET);
4078 bce_halt_cpu(sc, cpu_reg);
4080 /* Load the Text area. */
4081 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
4085 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
4086 REG_WR_IND(sc, offset, fw->text[j]);
4090 /* Load the Data area. */
4091 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
4095 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
4096 REG_WR_IND(sc, offset, fw->data[j]);
4100 /* Load the SBSS area. */
4101 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
4105 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
4106 REG_WR_IND(sc, offset, fw->sbss[j]);
4110 /* Load the BSS area. */
4111 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
4115 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
4116 REG_WR_IND(sc, offset, fw->bss[j]);
4120 /* Load the Read-Only area. */
4121 offset = cpu_reg->spad_base +
4122 (fw->rodata_addr - cpu_reg->mips_view_base);
4126 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
4127 REG_WR_IND(sc, offset, fw->rodata[j]);
4131 /* Clear the pre-fetch instruction and set the FW start address. */
4132 REG_WR_IND(sc, cpu_reg->inst, 0);
4133 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
4135 DBEXIT(BCE_VERBOSE_RESET);
4139 /****************************************************************************/
4140 /* Starts the RISC processor. */
4142 /* Assumes the CPU starting address has already been set. */
4146 /****************************************************************************/
4148 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4152 DBENTER(BCE_VERBOSE_RESET);
4154 /* Start the CPU. */
4155 val = REG_RD_IND(sc, cpu_reg->mode);
4156 val &= ~cpu_reg->mode_value_halt;
4157 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4158 REG_WR_IND(sc, cpu_reg->mode, val);
4160 DBEXIT(BCE_VERBOSE_RESET);
4164 /****************************************************************************/
4165 /* Halts the RISC processor. */
4169 /****************************************************************************/
4171 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4175 DBENTER(BCE_VERBOSE_RESET);
4178 val = REG_RD_IND(sc, cpu_reg->mode);
4179 val |= cpu_reg->mode_value_halt;
4180 REG_WR_IND(sc, cpu_reg->mode, val);
4181 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4183 DBEXIT(BCE_VERBOSE_RESET);
4187 /****************************************************************************/
4188 /* Initialize the RX CPU. */
4192 /****************************************************************************/
4194 bce_start_rxp_cpu(struct bce_softc *sc)
4196 struct cpu_reg cpu_reg;
4198 DBENTER(BCE_VERBOSE_RESET);
4200 cpu_reg.mode = BCE_RXP_CPU_MODE;
4201 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4202 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4203 cpu_reg.state = BCE_RXP_CPU_STATE;
4204 cpu_reg.state_value_clear = 0xffffff;
4205 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4206 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4207 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4208 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4209 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4210 cpu_reg.spad_base = BCE_RXP_SCRATCH;
4211 cpu_reg.mips_view_base = 0x8000000;
4213 DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n");
4214 bce_start_cpu(sc, &cpu_reg);
4216 DBEXIT(BCE_VERBOSE_RESET);
4220 /****************************************************************************/
4221 /* Initialize the RX CPU. */
4225 /****************************************************************************/
4227 bce_init_rxp_cpu(struct bce_softc *sc)
4229 struct cpu_reg cpu_reg;
4232 DBENTER(BCE_VERBOSE_RESET);
4234 cpu_reg.mode = BCE_RXP_CPU_MODE;
4235 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4236 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4237 cpu_reg.state = BCE_RXP_CPU_STATE;
4238 cpu_reg.state_value_clear = 0xffffff;
4239 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4240 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4241 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4242 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4243 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4244 cpu_reg.spad_base = BCE_RXP_SCRATCH;
4245 cpu_reg.mips_view_base = 0x8000000;
4247 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4248 fw.ver_major = bce_RXP_b09FwReleaseMajor;
4249 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
4250 fw.ver_fix = bce_RXP_b09FwReleaseFix;
4251 fw.start_addr = bce_RXP_b09FwStartAddr;
4253 fw.text_addr = bce_RXP_b09FwTextAddr;
4254 fw.text_len = bce_RXP_b09FwTextLen;
4256 fw.text = bce_RXP_b09FwText;
4258 fw.data_addr = bce_RXP_b09FwDataAddr;
4259 fw.data_len = bce_RXP_b09FwDataLen;
4261 fw.data = bce_RXP_b09FwData;
4263 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
4264 fw.sbss_len = bce_RXP_b09FwSbssLen;
4266 fw.sbss = bce_RXP_b09FwSbss;
4268 fw.bss_addr = bce_RXP_b09FwBssAddr;
4269 fw.bss_len = bce_RXP_b09FwBssLen;
4271 fw.bss = bce_RXP_b09FwBss;
4273 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
4274 fw.rodata_len = bce_RXP_b09FwRodataLen;
4275 fw.rodata_index = 0;
4276 fw.rodata = bce_RXP_b09FwRodata;
4278 fw.ver_major = bce_RXP_b06FwReleaseMajor;
4279 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
4280 fw.ver_fix = bce_RXP_b06FwReleaseFix;
4281 fw.start_addr = bce_RXP_b06FwStartAddr;
4283 fw.text_addr = bce_RXP_b06FwTextAddr;
4284 fw.text_len = bce_RXP_b06FwTextLen;
4286 fw.text = bce_RXP_b06FwText;
4288 fw.data_addr = bce_RXP_b06FwDataAddr;
4289 fw.data_len = bce_RXP_b06FwDataLen;
4291 fw.data = bce_RXP_b06FwData;
4293 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
4294 fw.sbss_len = bce_RXP_b06FwSbssLen;
4296 fw.sbss = bce_RXP_b06FwSbss;
4298 fw.bss_addr = bce_RXP_b06FwBssAddr;
4299 fw.bss_len = bce_RXP_b06FwBssLen;
4301 fw.bss = bce_RXP_b06FwBss;
4303 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
4304 fw.rodata_len = bce_RXP_b06FwRodataLen;
4305 fw.rodata_index = 0;
4306 fw.rodata = bce_RXP_b06FwRodata;
4309 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
4310 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4312 /* Delay RXP start until initialization is complete. */
4314 DBEXIT(BCE_VERBOSE_RESET);
4318 /****************************************************************************/
4319 /* Initialize the TX CPU. */
4323 /****************************************************************************/
4325 bce_init_txp_cpu(struct bce_softc *sc)
4327 struct cpu_reg cpu_reg;
4330 DBENTER(BCE_VERBOSE_RESET);
4332 cpu_reg.mode = BCE_TXP_CPU_MODE;
4333 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
4334 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
4335 cpu_reg.state = BCE_TXP_CPU_STATE;
4336 cpu_reg.state_value_clear = 0xffffff;
4337 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
4338 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
4339 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
4340 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
4341 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
4342 cpu_reg.spad_base = BCE_TXP_SCRATCH;
4343 cpu_reg.mips_view_base = 0x8000000;
4345 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4346 fw.ver_major = bce_TXP_b09FwReleaseMajor;
4347 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
4348 fw.ver_fix = bce_TXP_b09FwReleaseFix;
4349 fw.start_addr = bce_TXP_b09FwStartAddr;
4351 fw.text_addr = bce_TXP_b09FwTextAddr;
4352 fw.text_len = bce_TXP_b09FwTextLen;
4354 fw.text = bce_TXP_b09FwText;
4356 fw.data_addr = bce_TXP_b09FwDataAddr;
4357 fw.data_len = bce_TXP_b09FwDataLen;
4359 fw.data = bce_TXP_b09FwData;
4361 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
4362 fw.sbss_len = bce_TXP_b09FwSbssLen;
4364 fw.sbss = bce_TXP_b09FwSbss;
4366 fw.bss_addr = bce_TXP_b09FwBssAddr;
4367 fw.bss_len = bce_TXP_b09FwBssLen;
4369 fw.bss = bce_TXP_b09FwBss;
4371 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
4372 fw.rodata_len = bce_TXP_b09FwRodataLen;
4373 fw.rodata_index = 0;
4374 fw.rodata = bce_TXP_b09FwRodata;
4376 fw.ver_major = bce_TXP_b06FwReleaseMajor;
4377 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
4378 fw.ver_fix = bce_TXP_b06FwReleaseFix;
4379 fw.start_addr = bce_TXP_b06FwStartAddr;
4381 fw.text_addr = bce_TXP_b06FwTextAddr;
4382 fw.text_len = bce_TXP_b06FwTextLen;
4384 fw.text = bce_TXP_b06FwText;
4386 fw.data_addr = bce_TXP_b06FwDataAddr;
4387 fw.data_len = bce_TXP_b06FwDataLen;
4389 fw.data = bce_TXP_b06FwData;
4391 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
4392 fw.sbss_len = bce_TXP_b06FwSbssLen;
4394 fw.sbss = bce_TXP_b06FwSbss;
4396 fw.bss_addr = bce_TXP_b06FwBssAddr;
4397 fw.bss_len = bce_TXP_b06FwBssLen;
4399 fw.bss = bce_TXP_b06FwBss;
4401 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
4402 fw.rodata_len = bce_TXP_b06FwRodataLen;
4403 fw.rodata_index = 0;
4404 fw.rodata = bce_TXP_b06FwRodata;
4407 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
4408 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4409 bce_start_cpu(sc, &cpu_reg);
4411 DBEXIT(BCE_VERBOSE_RESET);
4415 /****************************************************************************/
4416 /* Initialize the TPAT CPU. */
4420 /****************************************************************************/
4422 bce_init_tpat_cpu(struct bce_softc *sc)
4424 struct cpu_reg cpu_reg;
4427 DBENTER(BCE_VERBOSE_RESET);
4429 cpu_reg.mode = BCE_TPAT_CPU_MODE;
4430 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
4431 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
4432 cpu_reg.state = BCE_TPAT_CPU_STATE;
4433 cpu_reg.state_value_clear = 0xffffff;
4434 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
4435 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
4436 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
4437 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
4438 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
4439 cpu_reg.spad_base = BCE_TPAT_SCRATCH;
4440 cpu_reg.mips_view_base = 0x8000000;
4442 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4443 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
4444 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
4445 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
4446 fw.start_addr = bce_TPAT_b09FwStartAddr;
4448 fw.text_addr = bce_TPAT_b09FwTextAddr;
4449 fw.text_len = bce_TPAT_b09FwTextLen;
4451 fw.text = bce_TPAT_b09FwText;
4453 fw.data_addr = bce_TPAT_b09FwDataAddr;
4454 fw.data_len = bce_TPAT_b09FwDataLen;
4456 fw.data = bce_TPAT_b09FwData;
4458 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
4459 fw.sbss_len = bce_TPAT_b09FwSbssLen;
4461 fw.sbss = bce_TPAT_b09FwSbss;
4463 fw.bss_addr = bce_TPAT_b09FwBssAddr;
4464 fw.bss_len = bce_TPAT_b09FwBssLen;
4466 fw.bss = bce_TPAT_b09FwBss;
4468 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
4469 fw.rodata_len = bce_TPAT_b09FwRodataLen;
4470 fw.rodata_index = 0;
4471 fw.rodata = bce_TPAT_b09FwRodata;
4473 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
4474 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
4475 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
4476 fw.start_addr = bce_TPAT_b06FwStartAddr;
4478 fw.text_addr = bce_TPAT_b06FwTextAddr;
4479 fw.text_len = bce_TPAT_b06FwTextLen;
4481 fw.text = bce_TPAT_b06FwText;
4483 fw.data_addr = bce_TPAT_b06FwDataAddr;
4484 fw.data_len = bce_TPAT_b06FwDataLen;
4486 fw.data = bce_TPAT_b06FwData;
4488 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
4489 fw.sbss_len = bce_TPAT_b06FwSbssLen;
4491 fw.sbss = bce_TPAT_b06FwSbss;
4493 fw.bss_addr = bce_TPAT_b06FwBssAddr;
4494 fw.bss_len = bce_TPAT_b06FwBssLen;
4496 fw.bss = bce_TPAT_b06FwBss;
4498 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
4499 fw.rodata_len = bce_TPAT_b06FwRodataLen;
4500 fw.rodata_index = 0;
4501 fw.rodata = bce_TPAT_b06FwRodata;
4504 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
4505 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4506 bce_start_cpu(sc, &cpu_reg);
4508 DBEXIT(BCE_VERBOSE_RESET);
4512 /****************************************************************************/
4513 /* Initialize the CP CPU. */
4517 /****************************************************************************/
4519 bce_init_cp_cpu(struct bce_softc *sc)
4521 struct cpu_reg cpu_reg;
4524 DBENTER(BCE_VERBOSE_RESET);
4526 cpu_reg.mode = BCE_CP_CPU_MODE;
4527 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
4528 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
4529 cpu_reg.state = BCE_CP_CPU_STATE;
4530 cpu_reg.state_value_clear = 0xffffff;
4531 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
4532 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
4533 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
4534 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
4535 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
4536 cpu_reg.spad_base = BCE_CP_SCRATCH;
4537 cpu_reg.mips_view_base = 0x8000000;
4539 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4540 fw.ver_major = bce_CP_b09FwReleaseMajor;
4541 fw.ver_minor = bce_CP_b09FwReleaseMinor;
4542 fw.ver_fix = bce_CP_b09FwReleaseFix;
4543 fw.start_addr = bce_CP_b09FwStartAddr;
4545 fw.text_addr = bce_CP_b09FwTextAddr;
4546 fw.text_len = bce_CP_b09FwTextLen;
4548 fw.text = bce_CP_b09FwText;
4550 fw.data_addr = bce_CP_b09FwDataAddr;
4551 fw.data_len = bce_CP_b09FwDataLen;
4553 fw.data = bce_CP_b09FwData;
4555 fw.sbss_addr = bce_CP_b09FwSbssAddr;
4556 fw.sbss_len = bce_CP_b09FwSbssLen;
4558 fw.sbss = bce_CP_b09FwSbss;
4560 fw.bss_addr = bce_CP_b09FwBssAddr;
4561 fw.bss_len = bce_CP_b09FwBssLen;
4563 fw.bss = bce_CP_b09FwBss;
4565 fw.rodata_addr = bce_CP_b09FwRodataAddr;
4566 fw.rodata_len = bce_CP_b09FwRodataLen;
4567 fw.rodata_index = 0;
4568 fw.rodata = bce_CP_b09FwRodata;
4570 fw.ver_major = bce_CP_b06FwReleaseMajor;
4571 fw.ver_minor = bce_CP_b06FwReleaseMinor;
4572 fw.ver_fix = bce_CP_b06FwReleaseFix;
4573 fw.start_addr = bce_CP_b06FwStartAddr;
4575 fw.text_addr = bce_CP_b06FwTextAddr;
4576 fw.text_len = bce_CP_b06FwTextLen;
4578 fw.text = bce_CP_b06FwText;
4580 fw.data_addr = bce_CP_b06FwDataAddr;
4581 fw.data_len = bce_CP_b06FwDataLen;
4583 fw.data = bce_CP_b06FwData;
4585 fw.sbss_addr = bce_CP_b06FwSbssAddr;
4586 fw.sbss_len = bce_CP_b06FwSbssLen;
4588 fw.sbss = bce_CP_b06FwSbss;
4590 fw.bss_addr = bce_CP_b06FwBssAddr;
4591 fw.bss_len = bce_CP_b06FwBssLen;
4593 fw.bss = bce_CP_b06FwBss;
4595 fw.rodata_addr = bce_CP_b06FwRodataAddr;
4596 fw.rodata_len = bce_CP_b06FwRodataLen;
4597 fw.rodata_index = 0;
4598 fw.rodata = bce_CP_b06FwRodata;
4601 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
4602 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4603 bce_start_cpu(sc, &cpu_reg);
4605 DBEXIT(BCE_VERBOSE_RESET);
4609 /****************************************************************************/
4610 /* Initialize the COM CPU. */
4614 /****************************************************************************/
4616 bce_init_com_cpu(struct bce_softc *sc)
4618 struct cpu_reg cpu_reg;
4621 DBENTER(BCE_VERBOSE_RESET);
4623 cpu_reg.mode = BCE_COM_CPU_MODE;
4624 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
4625 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
4626 cpu_reg.state = BCE_COM_CPU_STATE;
4627 cpu_reg.state_value_clear = 0xffffff;
4628 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
4629 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
4630 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
4631 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
4632 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
4633 cpu_reg.spad_base = BCE_COM_SCRATCH;
4634 cpu_reg.mips_view_base = 0x8000000;
4636 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4637 fw.ver_major = bce_COM_b09FwReleaseMajor;
4638 fw.ver_minor = bce_COM_b09FwReleaseMinor;
4639 fw.ver_fix = bce_COM_b09FwReleaseFix;
4640 fw.start_addr = bce_COM_b09FwStartAddr;
4642 fw.text_addr = bce_COM_b09FwTextAddr;
4643 fw.text_len = bce_COM_b09FwTextLen;
4645 fw.text = bce_COM_b09FwText;
4647 fw.data_addr = bce_COM_b09FwDataAddr;
4648 fw.data_len = bce_COM_b09FwDataLen;
4650 fw.data = bce_COM_b09FwData;
4652 fw.sbss_addr = bce_COM_b09FwSbssAddr;
4653 fw.sbss_len = bce_COM_b09FwSbssLen;
4655 fw.sbss = bce_COM_b09FwSbss;
4657 fw.bss_addr = bce_COM_b09FwBssAddr;
4658 fw.bss_len = bce_COM_b09FwBssLen;
4660 fw.bss = bce_COM_b09FwBss;
4662 fw.rodata_addr = bce_COM_b09FwRodataAddr;
4663 fw.rodata_len = bce_COM_b09FwRodataLen;
4664 fw.rodata_index = 0;
4665 fw.rodata = bce_COM_b09FwRodata;
4667 fw.ver_major = bce_COM_b06FwReleaseMajor;
4668 fw.ver_minor = bce_COM_b06FwReleaseMinor;
4669 fw.ver_fix = bce_COM_b06FwReleaseFix;
4670 fw.start_addr = bce_COM_b06FwStartAddr;
4672 fw.text_addr = bce_COM_b06FwTextAddr;
4673 fw.text_len = bce_COM_b06FwTextLen;
4675 fw.text = bce_COM_b06FwText;
4677 fw.data_addr = bce_COM_b06FwDataAddr;
4678 fw.data_len = bce_COM_b06FwDataLen;
4680 fw.data = bce_COM_b06FwData;
4682 fw.sbss_addr = bce_COM_b06FwSbssAddr;
4683 fw.sbss_len = bce_COM_b06FwSbssLen;
4685 fw.sbss = bce_COM_b06FwSbss;
4687 fw.bss_addr = bce_COM_b06FwBssAddr;
4688 fw.bss_len = bce_COM_b06FwBssLen;
4690 fw.bss = bce_COM_b06FwBss;
4692 fw.rodata_addr = bce_COM_b06FwRodataAddr;
4693 fw.rodata_len = bce_COM_b06FwRodataLen;
4694 fw.rodata_index = 0;
4695 fw.rodata = bce_COM_b06FwRodata;
4698 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
4699 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4700 bce_start_cpu(sc, &cpu_reg);
4702 DBEXIT(BCE_VERBOSE_RESET);
4706 /****************************************************************************/
4707 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */
4709 /* Loads the firmware for each CPU and starts the CPU. */
4713 /****************************************************************************/
4715 bce_init_cpus(struct bce_softc *sc)
4717 DBENTER(BCE_VERBOSE_RESET);
4719 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4721 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) {
4722 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
4723 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
4724 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
4725 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
4727 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
4728 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
4729 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
4730 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
4734 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
4735 sizeof(bce_rv2p_proc1), RV2P_PROC1);
4736 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
4737 sizeof(bce_rv2p_proc2), RV2P_PROC2);
4740 bce_init_rxp_cpu(sc);
4741 bce_init_txp_cpu(sc);
4742 bce_init_tpat_cpu(sc);
4743 bce_init_com_cpu(sc);
4744 bce_init_cp_cpu(sc);
4746 DBEXIT(BCE_VERBOSE_RESET);
4750 /****************************************************************************/
4751 /* Initialize context memory. */
4753 /* Clears the memory associated with each Context ID (CID). */
4757 /****************************************************************************/
4759 bce_init_ctx(struct bce_softc *sc)
4761 u32 offset, val, vcid_addr;
4762 int i, j, rc, retry_cnt;
4765 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4767 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4768 retry_cnt = CTX_INIT_RETRY_COUNT;
4770 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n");
4773 * BCM5709 context memory may be cached
4774 * in host memory so prepare the host memory
4777 val = BCE_CTX_COMMAND_ENABLED |
4778 BCE_CTX_COMMAND_MEM_INIT | (1 << 12);
4779 val |= (BCM_PAGE_BITS - 8) << 16;
4780 REG_WR(sc, BCE_CTX_COMMAND, val);
4782 /* Wait for mem init command to complete. */
4783 for (i = 0; i < retry_cnt; i++) {
4784 val = REG_RD(sc, BCE_CTX_COMMAND);
4785 if (!(val & BCE_CTX_COMMAND_MEM_INIT))
4789 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) {
4790 BCE_PRINTF("%s(): Context memory initialization failed!\n",
4796 for (i = 0; i < sc->ctx_pages; i++) {
4797 /* Set the physical address of the context memory. */
4798 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
4799 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
4800 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
4801 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
4802 BCE_ADDR_HI(sc->ctx_paddr[i]));
4803 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i |
4804 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
4806 /* Verify the context memory write was successful. */
4807 for (j = 0; j < retry_cnt; j++) {
4808 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
4810 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
4814 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) {
4815 BCE_PRINTF("%s(): Failed to initialize "
4816 "context page %d!\n", __FUNCTION__, i);
4823 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n");
4826 * For the 5706/5708, context memory is local to
4827 * the controller, so initialize the controller
4831 vcid_addr = GET_CID_ADDR(96);
4834 vcid_addr -= PHY_CTX_SIZE;
4836 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
4837 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4839 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
4840 CTX_WR(sc, 0x00, offset, 0);
4843 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
4844 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4849 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4854 /****************************************************************************/
4855 /* Fetch the permanent MAC address of the controller. */
4859 /****************************************************************************/
4861 bce_get_mac_addr(struct bce_softc *sc)
4863 u32 mac_lo = 0, mac_hi = 0;
4865 DBENTER(BCE_VERBOSE_RESET);
4868 * The NetXtreme II bootcode populates various NIC
4869 * power-on and runtime configuration items in a
4870 * shared memory area. The factory configured MAC
4871 * address is available from both NVRAM and the
4872 * shared memory area so we'll read the value from
4873 * shared memory for speed.
4876 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER);
4877 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
4879 if ((mac_lo == 0) && (mac_hi == 0)) {
4880 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n",
4881 __FILE__, __LINE__);
4883 sc->eaddr[0] = (u_char)(mac_hi >> 8);
4884 sc->eaddr[1] = (u_char)(mac_hi >> 0);
4885 sc->eaddr[2] = (u_char)(mac_lo >> 24);
4886 sc->eaddr[3] = (u_char)(mac_lo >> 16);
4887 sc->eaddr[4] = (u_char)(mac_lo >> 8);
4888 sc->eaddr[5] = (u_char)(mac_lo >> 0);
4891 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet "
4892 "address = %6D\n", sc->eaddr, ":");
4893 DBEXIT(BCE_VERBOSE_RESET);
4897 /****************************************************************************/
4898 /* Program the MAC address. */
4902 /****************************************************************************/
4904 bce_set_mac_addr(struct bce_softc *sc)
4907 u8 *mac_addr = sc->eaddr;
4909 /* ToDo: Add support for setting multiple MAC addresses. */
4911 DBENTER(BCE_VERBOSE_RESET);
4912 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = "
4913 "%6D\n", sc->eaddr, ":");
4915 val = (mac_addr[0] << 8) | mac_addr[1];
4917 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
4919 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
4920 (mac_addr[4] << 8) | mac_addr[5];
4922 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
4924 DBEXIT(BCE_VERBOSE_RESET);
4928 /****************************************************************************/
4929 /* Stop the controller. */
4933 /****************************************************************************/
4935 bce_stop(struct bce_softc *sc)
4939 DBENTER(BCE_VERBOSE_RESET);
4941 BCE_LOCK_ASSERT(sc);
4945 callout_stop(&sc->bce_tick_callout);
4947 /* Disable the transmit/receive blocks. */
4948 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
4949 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
4952 bce_disable_intr(sc);
4954 /* Free RX buffers. */
4955 if (bce_hdr_split == TRUE) {
4956 bce_free_pg_chain(sc);
4958 bce_free_rx_chain(sc);
4960 /* Free TX buffers. */
4961 bce_free_tx_chain(sc);
4963 sc->watchdog_timer = 0;
4965 sc->bce_link_up = FALSE;
4967 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4969 DBEXIT(BCE_VERBOSE_RESET);
4974 bce_reset(struct bce_softc *sc, u32 reset_code)
4976 u32 emac_mode_save, val;
4978 static const u32 emac_mode_mask = BCE_EMAC_MODE_PORT |
4979 BCE_EMAC_MODE_HALF_DUPLEX | BCE_EMAC_MODE_25G;
4981 DBENTER(BCE_VERBOSE_RESET);
4983 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n",
4984 __FUNCTION__, reset_code);
4987 * If ASF/IPMI is operational, then the EMAC Mode register already
4988 * contains appropriate values for the link settings that have
4989 * been auto-negotiated. Resetting the chip will clobber those
4990 * values. Save the important bits so we can restore them after
4993 emac_mode_save = REG_RD(sc, BCE_EMAC_MODE) & emac_mode_mask;
4995 /* Wait for pending PCI transactions to complete. */
4996 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
4997 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4998 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4999 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
5000 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
5001 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
5005 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5006 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
5007 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
5008 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
5011 /* Assume bootcode is running. */
5012 sc->bce_fw_timed_out = FALSE;
5013 sc->bce_drv_cardiac_arrest = FALSE;
5015 /* Give the firmware a chance to prepare for the reset. */
5016 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
5018 goto bce_reset_exit;
5020 /* Set a firmware reminder that this is a soft reset. */
5021 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC);
5023 /* Dummy read to force the chip to complete all current transactions. */
5024 val = REG_RD(sc, BCE_MISC_ID);
5027 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5028 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
5029 REG_RD(sc, BCE_MISC_COMMAND);
5032 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5033 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
5035 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
5037 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5038 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5039 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
5040 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
5042 /* Allow up to 30us for reset to complete. */
5043 for (i = 0; i < 10; i++) {
5044 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
5045 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5046 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
5052 /* Check that reset completed successfully. */
5053 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5054 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
5055 BCE_PRINTF("%s(%d): Reset failed!\n",
5056 __FILE__, __LINE__);
5058 goto bce_reset_exit;
5062 /* Make sure byte swapping is properly configured. */
5063 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
5064 if (val != 0x01020304) {
5065 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n",
5066 __FILE__, __LINE__);
5068 goto bce_reset_exit;
5071 /* Just completed a reset, assume that firmware is running again. */
5072 sc->bce_fw_timed_out = FALSE;
5073 sc->bce_drv_cardiac_arrest = FALSE;
5075 /* Wait for the firmware to finish its initialization. */
5076 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
5078 BCE_PRINTF("%s(%d): Firmware did not complete "
5079 "initialization!\n", __FILE__, __LINE__);
5080 /* Get firmware capabilities. */
5081 bce_fw_cap_init(sc);
5084 /* Restore EMAC Mode bits needed to keep ASF/IPMI running. */
5085 if (reset_code == BCE_DRV_MSG_CODE_RESET) {
5086 val = REG_RD(sc, BCE_EMAC_MODE);
5087 val = (val & ~emac_mode_mask) | emac_mode_save;
5088 REG_WR(sc, BCE_EMAC_MODE, val);
5091 DBEXIT(BCE_VERBOSE_RESET);
5097 bce_chipinit(struct bce_softc *sc)
5102 DBENTER(BCE_VERBOSE_RESET);
5104 bce_disable_intr(sc);
5107 * Initialize DMA byte/word swapping, configure the number of DMA
5108 * channels and PCI clock compensation delay.
5110 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
5111 BCE_DMA_CONFIG_DATA_WORD_SWAP |
5112 #if BYTE_ORDER == BIG_ENDIAN
5113 BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
5115 BCE_DMA_CONFIG_CNTL_WORD_SWAP |
5116 DMA_READ_CHANS << 12 |
5117 DMA_WRITE_CHANS << 16;
5119 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
5121 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133))
5122 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
5125 * This setting resolves a problem observed on certain Intel PCI
5126 * chipsets that cannot handle multiple outstanding DMA operations.
5127 * See errata E9_5706A1_65.
5129 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5130 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) &&
5131 !(sc->bce_flags & BCE_PCIX_FLAG))
5132 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
5134 REG_WR(sc, BCE_DMA_CONFIG, val);
5136 /* Enable the RX_V2P and Context state machines before access. */
5137 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5138 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
5139 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
5140 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
5142 /* Initialize context mapping and zero out the quick contexts. */
5143 if ((rc = bce_init_ctx(sc)) != 0)
5144 goto bce_chipinit_exit;
5146 /* Initialize the on-boards CPUs */
5149 /* Enable management frames (NC-SI) to flow to the MCP. */
5150 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5151 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
5152 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5155 /* Prepare NVRAM for access. */
5156 if ((rc = bce_init_nvram(sc)) != 0)
5157 goto bce_chipinit_exit;
5159 /* Set the kernel bypass block size */
5160 val = REG_RD(sc, BCE_MQ_CONFIG);
5161 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
5162 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
5164 /* Enable bins used on the 5709. */
5165 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5166 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
5167 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
5168 val |= BCE_MQ_CONFIG_HALT_DIS;
5171 REG_WR(sc, BCE_MQ_CONFIG, val);
5173 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
5174 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
5175 REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
5177 /* Set the page size and clear the RV2P processor stall bits. */
5178 val = (BCM_PAGE_BITS - 8) << 24;
5179 REG_WR(sc, BCE_RV2P_CONFIG, val);
5181 /* Configure page size. */
5182 val = REG_RD(sc, BCE_TBDR_CONFIG);
5183 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
5184 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
5185 REG_WR(sc, BCE_TBDR_CONFIG, val);
5187 /* Set the perfect match control register to default. */
5188 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
5191 DBEXIT(BCE_VERBOSE_RESET);
5197 /****************************************************************************/
5198 /* Initialize the controller in preparation to send/receive traffic. */
5201 /* 0 for success, positive value for failure. */
5202 /****************************************************************************/
5204 bce_blockinit(struct bce_softc *sc)
5209 DBENTER(BCE_VERBOSE_RESET);
5211 /* Load the hardware default MAC address. */
5212 bce_set_mac_addr(sc);
5214 /* Set the Ethernet backoff seed value */
5215 val = sc->eaddr[0] + (sc->eaddr[1] << 8) +
5216 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) +
5217 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
5218 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
5220 sc->last_status_idx = 0;
5221 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
5223 /* Set up link change interrupt generation. */
5224 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
5226 /* Program the physical address of the status block. */
5227 REG_WR(sc, BCE_HC_STATUS_ADDR_L,
5228 BCE_ADDR_LO(sc->status_block_paddr));
5229 REG_WR(sc, BCE_HC_STATUS_ADDR_H,
5230 BCE_ADDR_HI(sc->status_block_paddr));
5232 /* Program the physical address of the statistics block. */
5233 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
5234 BCE_ADDR_LO(sc->stats_block_paddr));
5235 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
5236 BCE_ADDR_HI(sc->stats_block_paddr));
5239 * Program various host coalescing parameters.
5240 * Trip points control how many BDs should be ready before generating
5241 * an interrupt while ticks control how long a BD can sit in the chain
5242 * before generating an interrupt.
5244 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5245 (sc->bce_tx_quick_cons_trip_int << 16) |
5246 sc->bce_tx_quick_cons_trip);
5247 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5248 (sc->bce_rx_quick_cons_trip_int << 16) |
5249 sc->bce_rx_quick_cons_trip);
5250 REG_WR(sc, BCE_HC_TX_TICKS,
5251 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
5252 REG_WR(sc, BCE_HC_RX_TICKS,
5253 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
5254 REG_WR(sc, BCE_HC_STATS_TICKS, sc->bce_stats_ticks & 0xffff00);
5255 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
5256 /* Not used for L2. */
5257 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 0);
5258 REG_WR(sc, BCE_HC_COM_TICKS, 0);
5259 REG_WR(sc, BCE_HC_CMD_TICKS, 0);
5261 /* Configure the Host Coalescing block. */
5262 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE |
5263 BCE_HC_CONFIG_COLLECT_STATS;
5266 /* ToDo: Add MSI-X support. */
5267 if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
5268 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) +
5271 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL);
5273 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE |
5274 BCE_HC_SB_CONFIG_1_ONE_SHOT);
5276 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF,
5277 (sc->tx_quick_cons_trip_int << 16) |
5278 sc->tx_quick_cons_trip);
5280 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF,
5281 (sc->tx_ticks_int << 16) | sc->tx_ticks);
5283 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
5287 * Tell the HC block to automatically set the
5288 * INT_MASK bit after an MSI/MSI-X interrupt
5289 * is generated so the driver doesn't have to.
5291 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG)
5292 val |= BCE_HC_CONFIG_ONE_SHOT;
5294 /* Set the MSI-X status blocks to 128 byte boundaries. */
5295 if (sc->bce_flags & BCE_USING_MSIX_FLAG)
5296 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
5299 REG_WR(sc, BCE_HC_CONFIG, val);
5301 /* Clear the internal statistics counters. */
5302 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
5304 /* Verify that bootcode is running. */
5305 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
5307 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control),
5308 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n",
5309 __FILE__, __LINE__);
5312 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5313 BCE_DEV_INFO_SIGNATURE_MAGIC) {
5314 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, "
5315 "Expected: 08%08X\n", __FILE__, __LINE__,
5316 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK),
5317 BCE_DEV_INFO_SIGNATURE_MAGIC);
5319 goto bce_blockinit_exit;
5323 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5324 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
5325 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
5326 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
5329 /* Allow bootcode to apply additional fixes before enabling MAC. */
5330 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 |
5331 BCE_DRV_MSG_CODE_RESET);
5333 /* Enable link state change interrupt generation. */
5334 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
5336 /* Enable the RXP. */
5337 bce_start_rxp_cpu(sc);
5339 /* Disable management frames (NC-SI) from flowing to the MCP. */
5340 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5341 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
5342 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
5343 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5346 /* Enable all remaining blocks in the MAC. */
5347 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
5348 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5349 BCE_MISC_ENABLE_DEFAULT_XI);
5351 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5352 BCE_MISC_ENABLE_DEFAULT);
5354 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
5357 /* Save the current host coalescing block settings. */
5358 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
5361 DBEXIT(BCE_VERBOSE_RESET);
5367 /****************************************************************************/
5368 /* Encapsulate an mbuf into the rx_bd chain. */
5371 /* 0 for success, positive value for failure. */
5372 /****************************************************************************/
5374 bce_get_rx_buf(struct bce_softc *sc, u16 prod, u16 chain_prod, u32 *prod_bseq)
5376 bus_dma_segment_t segs[1];
5377 struct mbuf *m_new = NULL;
5379 int nsegs, error, rc = 0;
5381 u16 debug_chain_prod = chain_prod;
5384 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5386 /* Make sure the inputs are valid. */
5387 DBRUNIF((chain_prod > MAX_RX_BD_ALLOC),
5388 BCE_PRINTF("%s(%d): RX producer out of range: "
5389 "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5390 chain_prod, (u16)MAX_RX_BD_ALLOC));
5392 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5393 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__,
5394 prod, chain_prod, *prod_bseq);
5396 /* Update some debug statistic counters */
5397 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
5398 sc->rx_low_watermark = sc->free_rx_bd);
5399 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
5400 sc->rx_empty_count++);
5402 /* Simulate an mbuf allocation failure. */
5403 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5404 sc->mbuf_alloc_failed_count++;
5405 sc->mbuf_alloc_failed_sim_count++;
5407 goto bce_get_rx_buf_exit);
5409 /* This is a new mbuf allocation. */
5410 if (bce_hdr_split == TRUE)
5411 MGETHDR(m_new, M_NOWAIT, MT_DATA);
5413 m_new = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
5414 sc->rx_bd_mbuf_alloc_size);
5416 if (m_new == NULL) {
5417 sc->mbuf_alloc_failed_count++;
5419 goto bce_get_rx_buf_exit;
5422 DBRUN(sc->debug_rx_mbuf_alloc++);
5424 /* Make sure we have a valid packet header. */
5425 M_ASSERTPKTHDR(m_new);
5427 /* Initialize the mbuf size and pad if necessary for alignment. */
5428 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size;
5429 m_adj(m_new, sc->rx_bd_mbuf_align_pad);
5431 /* ToDo: Consider calling m_fragment() to test error handling. */
5433 /* Map the mbuf cluster into device memory. */
5434 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag,
5435 sc->rx_mbuf_map[chain_prod], m_new, segs, &nsegs, BUS_DMA_NOWAIT);
5437 /* Handle any mapping errors. */
5439 BCE_PRINTF("%s(%d): Error mapping mbuf into RX "
5440 "chain (%d)!\n", __FILE__, __LINE__, error);
5442 sc->dma_map_addr_rx_failed_count++;
5445 DBRUN(sc->debug_rx_mbuf_alloc--);
5448 goto bce_get_rx_buf_exit;
5451 /* All mbufs must map to a single segment. */
5452 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",
5453 __FUNCTION__, nsegs));
5455 /* Setup the rx_bd for the segment. */
5456 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
5458 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr));
5459 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr));
5460 rxbd->rx_bd_len = htole32(segs[0].ds_len);
5461 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5462 *prod_bseq += segs[0].ds_len;
5464 /* Save the mbuf and update our counter. */
5465 sc->rx_mbuf_ptr[chain_prod] = m_new;
5466 sc->free_rx_bd -= nsegs;
5468 DBRUNMSG(BCE_INSANE_RECV,
5469 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs));
5471 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5472 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, prod,
5473 chain_prod, *prod_bseq);
5475 bce_get_rx_buf_exit:
5476 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5482 /****************************************************************************/
5483 /* Encapsulate an mbuf cluster into the page chain. */
5486 /* 0 for success, positive value for failure. */
5487 /****************************************************************************/
5489 bce_get_pg_buf(struct bce_softc *sc, u16 prod, u16 prod_idx)
5491 bus_dma_segment_t segs[1];
5492 struct mbuf *m_new = NULL;
5494 int error, nsegs, rc = 0;
5496 u16 debug_prod_idx = prod_idx;
5499 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5501 /* Make sure the inputs are valid. */
5502 DBRUNIF((prod_idx > MAX_PG_BD_ALLOC),
5503 BCE_PRINTF("%s(%d): page producer out of range: "
5504 "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5505 prod_idx, (u16)MAX_PG_BD_ALLOC));
5507 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5508 "chain_prod = 0x%04X\n", __FUNCTION__, prod, prod_idx);
5510 /* Update counters if we've hit a new low or run out of pages. */
5511 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark),
5512 sc->pg_low_watermark = sc->free_pg_bd);
5513 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++);
5515 /* Simulate an mbuf allocation failure. */
5516 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5517 sc->mbuf_alloc_failed_count++;
5518 sc->mbuf_alloc_failed_sim_count++;
5520 goto bce_get_pg_buf_exit);
5522 /* This is a new mbuf allocation. */
5523 m_new = m_getcl(M_NOWAIT, MT_DATA, 0);
5524 if (m_new == NULL) {
5525 sc->mbuf_alloc_failed_count++;
5527 goto bce_get_pg_buf_exit;
5530 DBRUN(sc->debug_pg_mbuf_alloc++);
5532 m_new->m_len = MCLBYTES;
5534 /* ToDo: Consider calling m_fragment() to test error handling. */
5536 /* Map the mbuf cluster into device memory. */
5537 error = bus_dmamap_load_mbuf_sg(sc->pg_mbuf_tag,
5538 sc->pg_mbuf_map[prod_idx], m_new, segs, &nsegs, BUS_DMA_NOWAIT);
5540 /* Handle any mapping errors. */
5542 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n",
5543 __FILE__, __LINE__);
5546 DBRUN(sc->debug_pg_mbuf_alloc--);
5549 goto bce_get_pg_buf_exit;
5552 /* All mbufs must map to a single segment. */
5553 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",
5554 __FUNCTION__, nsegs));
5556 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */
5559 * The page chain uses the same rx_bd data structure
5560 * as the receive chain but doesn't require a byte sequence (bseq).
5562 pgbd = &sc->pg_bd_chain[PG_PAGE(prod_idx)][PG_IDX(prod_idx)];
5564 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr));
5565 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr));
5566 pgbd->rx_bd_len = htole32(MCLBYTES);
5567 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5569 /* Save the mbuf and update our counter. */
5570 sc->pg_mbuf_ptr[prod_idx] = m_new;
5573 DBRUNMSG(BCE_INSANE_RECV,
5574 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1));
5576 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5577 "prod_idx = 0x%04X\n", __FUNCTION__, prod, prod_idx);
5579 bce_get_pg_buf_exit:
5580 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5586 /****************************************************************************/
5587 /* Initialize the TX context memory. */
5591 /****************************************************************************/
5593 bce_init_tx_context(struct bce_softc *sc)
5597 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5599 /* Initialize the context ID for an L2 TX chain. */
5600 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5601 /* Set the CID type to support an L2 connection. */
5602 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI |
5603 BCE_L2CTX_TX_TYPE_SIZE_L2_XI;
5604 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
5605 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16);
5606 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5607 BCE_L2CTX_TX_CMD_TYPE_XI, val);
5609 /* Point the hardware to the first page in the chain. */
5610 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5611 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5612 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
5613 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5614 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5615 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
5617 /* Set the CID type to support an L2 connection. */
5618 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
5619 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
5620 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
5621 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
5623 /* Point the hardware to the first page in the chain. */
5624 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5625 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5626 BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
5627 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5628 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5629 BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
5632 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5636 /****************************************************************************/
5637 /* Allocate memory and initialize the TX data structures. */
5640 /* 0 for success, positive value for failure. */
5641 /****************************************************************************/
5643 bce_init_tx_chain(struct bce_softc *sc)
5648 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5650 /* Set the initial TX producer/consumer indices. */
5653 sc->tx_prod_bseq = 0;
5655 sc->max_tx_bd = USABLE_TX_BD_ALLOC;
5656 DBRUN(sc->tx_hi_watermark = 0);
5657 DBRUN(sc->tx_full_count = 0);
5660 * The NetXtreme II supports a linked-list structre called
5661 * a Buffer Descriptor Chain (or BD chain). A BD chain
5662 * consists of a series of 1 or more chain pages, each of which
5663 * consists of a fixed number of BD entries.
5664 * The last BD entry on each page is a pointer to the next page
5665 * in the chain, and the last pointer in the BD chain
5666 * points back to the beginning of the chain.
5669 /* Set the TX next pointer chain entries. */
5670 for (i = 0; i < sc->tx_pages; i++) {
5673 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
5675 /* Check if we've reached the last page. */
5676 if (i == (sc->tx_pages - 1))
5681 txbd->tx_bd_haddr_hi =
5682 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
5683 txbd->tx_bd_haddr_lo =
5684 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
5687 bce_init_tx_context(sc);
5689 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC));
5690 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5696 /****************************************************************************/
5697 /* Free memory and clear the TX data structures. */
5701 /****************************************************************************/
5703 bce_free_tx_chain(struct bce_softc *sc)
5707 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5709 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
5710 for (i = 0; i < MAX_TX_BD_AVAIL; i++) {
5711 if (sc->tx_mbuf_ptr[i] != NULL) {
5712 if (sc->tx_mbuf_map[i] != NULL)
5713 bus_dmamap_sync(sc->tx_mbuf_tag,
5715 BUS_DMASYNC_POSTWRITE);
5716 m_freem(sc->tx_mbuf_ptr[i]);
5717 sc->tx_mbuf_ptr[i] = NULL;
5718 DBRUN(sc->debug_tx_mbuf_alloc--);
5722 /* Clear each TX chain page. */
5723 for (i = 0; i < sc->tx_pages; i++)
5724 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
5728 /* Check if we lost any mbufs in the process. */
5729 DBRUNIF((sc->debug_tx_mbuf_alloc),
5730 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs "
5731 "from tx chain!\n", __FILE__, __LINE__,
5732 sc->debug_tx_mbuf_alloc));
5734 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5738 /****************************************************************************/
5739 /* Initialize the RX context memory. */
5743 /****************************************************************************/
5745 bce_init_rx_context(struct bce_softc *sc)
5749 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5751 /* Init the type, size, and BD cache levels for the RX context. */
5752 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
5753 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 |
5754 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT);
5757 * Set the level for generating pause frames
5758 * when the number of available rx_bd's gets
5759 * too low (the low watermark) and the level
5760 * when pause frames can be stopped (the high
5763 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5764 u32 lo_water, hi_water;
5766 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) {
5767 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
5772 if (lo_water >= USABLE_RX_BD_ALLOC) {
5776 hi_water = USABLE_RX_BD_ALLOC / 4;
5778 if (hi_water <= lo_water) {
5782 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
5783 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
5787 else if (hi_water == 0)
5790 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) |
5791 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
5794 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
5796 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
5797 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5798 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
5799 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
5802 /* Point the hardware to the first page in the chain. */
5803 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
5804 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
5805 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
5806 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
5808 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5812 /****************************************************************************/
5813 /* Allocate memory and initialize the RX data structures. */
5816 /* 0 for success, positive value for failure. */
5817 /****************************************************************************/
5819 bce_init_rx_chain(struct bce_softc *sc)
5824 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5827 /* Initialize the RX producer and consumer indices. */
5830 sc->rx_prod_bseq = 0;
5831 sc->free_rx_bd = USABLE_RX_BD_ALLOC;
5832 sc->max_rx_bd = USABLE_RX_BD_ALLOC;
5834 /* Initialize the RX next pointer chain entries. */
5835 for (i = 0; i < sc->rx_pages; i++) {
5838 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
5840 /* Check if we've reached the last page. */
5841 if (i == (sc->rx_pages - 1))
5846 /* Setup the chain page pointers. */
5847 rxbd->rx_bd_haddr_hi =
5848 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
5849 rxbd->rx_bd_haddr_lo =
5850 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
5853 /* Fill up the RX chain. */
5854 bce_fill_rx_chain(sc);
5856 DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC);
5857 DBRUN(sc->rx_empty_count = 0);
5858 for (i = 0; i < sc->rx_pages; i++) {
5859 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i],
5860 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
5863 bce_init_rx_context(sc);
5865 DBRUNMSG(BCE_EXTREME_RECV,
5866 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC));
5867 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5870 /* ToDo: Are there possible failure modes here? */
5876 /****************************************************************************/
5877 /* Add mbufs to the RX chain until its full or an mbuf allocation error */
5882 /****************************************************************************/
5884 bce_fill_rx_chain(struct bce_softc *sc)
5889 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5892 /* Get the RX chain producer indices. */
5894 prod_bseq = sc->rx_prod_bseq;
5896 /* Keep filling the RX chain until it's full. */
5897 while (sc->free_rx_bd > 0) {
5898 prod_idx = RX_CHAIN_IDX(prod);
5899 if (bce_get_rx_buf(sc, prod, prod_idx, &prod_bseq)) {
5900 /* Bail out if we can't add an mbuf to the chain. */
5903 prod = NEXT_RX_BD(prod);
5906 /* Save the RX chain producer indices. */
5908 sc->rx_prod_bseq = prod_bseq;
5910 /* We should never end up pointing to a next page pointer. */
5911 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
5912 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n",
5913 __FUNCTION__, rx_prod));
5915 /* Write the mailbox and tell the chip about the waiting rx_bd's. */
5916 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX, prod);
5917 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ, prod_bseq);
5919 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5924 /****************************************************************************/
5925 /* Free memory and clear the RX data structures. */
5929 /****************************************************************************/
5931 bce_free_rx_chain(struct bce_softc *sc)
5935 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5937 /* Free any mbufs still in the RX mbuf chain. */
5938 for (i = 0; i < MAX_RX_BD_AVAIL; i++) {
5939 if (sc->rx_mbuf_ptr[i] != NULL) {
5940 if (sc->rx_mbuf_map[i] != NULL)
5941 bus_dmamap_sync(sc->rx_mbuf_tag,
5943 BUS_DMASYNC_POSTREAD);
5944 m_freem(sc->rx_mbuf_ptr[i]);
5945 sc->rx_mbuf_ptr[i] = NULL;
5946 DBRUN(sc->debug_rx_mbuf_alloc--);
5950 /* Clear each RX chain page. */
5951 for (i = 0; i < sc->rx_pages; i++)
5952 if (sc->rx_bd_chain[i] != NULL)
5953 bzero((char *)sc->rx_bd_chain[i],
5954 BCE_RX_CHAIN_PAGE_SZ);
5956 sc->free_rx_bd = sc->max_rx_bd;
5958 /* Check if we lost any mbufs in the process. */
5959 DBRUNIF((sc->debug_rx_mbuf_alloc),
5960 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n",
5961 __FUNCTION__, sc->debug_rx_mbuf_alloc));
5963 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5967 /****************************************************************************/
5968 /* Allocate memory and initialize the page data structures. */
5969 /* Assumes that bce_init_rx_chain() has not already been called. */
5972 /* 0 for success, positive value for failure. */
5973 /****************************************************************************/
5975 bce_init_pg_chain(struct bce_softc *sc)
5981 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5984 /* Initialize the page producer and consumer indices. */
5987 sc->free_pg_bd = USABLE_PG_BD_ALLOC;
5988 sc->max_pg_bd = USABLE_PG_BD_ALLOC;
5989 DBRUN(sc->pg_low_watermark = sc->max_pg_bd);
5990 DBRUN(sc->pg_empty_count = 0);
5992 /* Initialize the page next pointer chain entries. */
5993 for (i = 0; i < sc->pg_pages; i++) {
5996 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE];
5998 /* Check if we've reached the last page. */
5999 if (i == (sc->pg_pages - 1))
6004 /* Setup the chain page pointers. */
6005 pgbd->rx_bd_haddr_hi =
6006 htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j]));
6007 pgbd->rx_bd_haddr_lo =
6008 htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j]));
6011 /* Setup the MQ BIN mapping for host_pg_bidx. */
6012 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
6013 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT);
6015 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0);
6017 /* Configure the rx_bd and page chain mbuf cluster size. */
6018 val = (sc->rx_bd_mbuf_data_len << 16) | MCLBYTES;
6019 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val);
6021 /* Configure the context reserved for jumbo support. */
6022 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY,
6023 BCE_L2CTX_RX_RBDC_JUMBO_KEY);
6025 /* Point the hardware to the first page in the page chain. */
6026 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]);
6027 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val);
6028 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]);
6029 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val);
6031 /* Fill up the page chain. */
6032 bce_fill_pg_chain(sc);
6034 for (i = 0; i < sc->pg_pages; i++) {
6035 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i],
6036 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
6039 DBRUNMSG(BCE_EXTREME_RECV,
6040 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC));
6041 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
6047 /****************************************************************************/
6048 /* Add mbufs to the page chain until its full or an mbuf allocation error */
6053 /****************************************************************************/
6055 bce_fill_pg_chain(struct bce_softc *sc)
6059 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
6062 /* Get the page chain prodcuer index. */
6065 /* Keep filling the page chain until it's full. */
6066 while (sc->free_pg_bd > 0) {
6067 prod_idx = PG_CHAIN_IDX(prod);
6068 if (bce_get_pg_buf(sc, prod, prod_idx)) {
6069 /* Bail out if we can't add an mbuf to the chain. */
6072 prod = NEXT_PG_BD(prod);
6075 /* Save the page chain producer index. */
6078 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
6079 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n",
6080 __FUNCTION__, pg_prod));
6083 * Write the mailbox and tell the chip about
6084 * the new rx_bd's in the page chain.
6086 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_PG_BDIDX,
6089 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
6094 /****************************************************************************/
6095 /* Free memory and clear the RX data structures. */
6099 /****************************************************************************/
6101 bce_free_pg_chain(struct bce_softc *sc)
6105 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
6107 /* Free any mbufs still in the mbuf page chain. */
6108 for (i = 0; i < MAX_PG_BD_AVAIL; i++) {
6109 if (sc->pg_mbuf_ptr[i] != NULL) {
6110 if (sc->pg_mbuf_map[i] != NULL)
6111 bus_dmamap_sync(sc->pg_mbuf_tag,
6113 BUS_DMASYNC_POSTREAD);
6114 m_freem(sc->pg_mbuf_ptr[i]);
6115 sc->pg_mbuf_ptr[i] = NULL;
6116 DBRUN(sc->debug_pg_mbuf_alloc--);
6120 /* Clear each page chain pages. */
6121 for (i = 0; i < sc->pg_pages; i++)
6122 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ);
6124 sc->free_pg_bd = sc->max_pg_bd;
6126 /* Check if we lost any mbufs in the process. */
6127 DBRUNIF((sc->debug_pg_mbuf_alloc),
6128 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n",
6129 __FUNCTION__, sc->debug_pg_mbuf_alloc));
6131 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
6136 bce_get_rphy_link(struct bce_softc *sc)
6138 u32 advertise, link;
6143 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0)
6144 link = bce_shmem_rd(sc, BCE_RPHY_SERDES_LINK);
6146 link = bce_shmem_rd(sc, BCE_RPHY_COPPER_LINK);
6147 if (link & BCE_NETLINK_ANEG_ENB)
6148 advertise |= BCE_NETLINK_ANEG_ENB;
6149 if (link & BCE_NETLINK_SPEED_10HALF)
6150 advertise |= BCE_NETLINK_SPEED_10HALF;
6151 if (link & BCE_NETLINK_SPEED_10FULL) {
6152 advertise |= BCE_NETLINK_SPEED_10FULL;
6155 if (link & BCE_NETLINK_SPEED_100HALF)
6156 advertise |= BCE_NETLINK_SPEED_100HALF;
6157 if (link & BCE_NETLINK_SPEED_100FULL) {
6158 advertise |= BCE_NETLINK_SPEED_100FULL;
6161 if (link & BCE_NETLINK_SPEED_1000HALF)
6162 advertise |= BCE_NETLINK_SPEED_1000HALF;
6163 if (link & BCE_NETLINK_SPEED_1000FULL) {
6164 advertise |= BCE_NETLINK_SPEED_1000FULL;
6167 if (link & BCE_NETLINK_SPEED_2500HALF)
6168 advertise |= BCE_NETLINK_SPEED_2500HALF;
6169 if (link & BCE_NETLINK_SPEED_2500FULL) {
6170 advertise |= BCE_NETLINK_SPEED_2500FULL;
6174 advertise |= BCE_NETLINK_FC_PAUSE_SYM |
6175 BCE_NETLINK_FC_PAUSE_ASYM;
6176 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6177 advertise |= BCE_NETLINK_PHY_APP_REMOTE |
6178 BCE_NETLINK_ETH_AT_WIRESPEED;
6184 /****************************************************************************/
6185 /* Set media options. */
6188 /* 0 for success, positive value for failure. */
6189 /****************************************************************************/
6191 bce_ifmedia_upd(struct ifnet *ifp)
6193 struct bce_softc *sc = ifp->if_softc;
6196 DBENTER(BCE_VERBOSE);
6199 error = bce_ifmedia_upd_locked(ifp);
6202 DBEXIT(BCE_VERBOSE);
6207 /****************************************************************************/
6208 /* Set media options. */
6212 /****************************************************************************/
6214 bce_ifmedia_upd_locked(struct ifnet *ifp)
6216 struct bce_softc *sc = ifp->if_softc;
6217 struct mii_data *mii;
6218 struct mii_softc *miisc;
6219 struct ifmedia *ifm;
6223 DBENTER(BCE_VERBOSE_PHY);
6226 BCE_LOCK_ASSERT(sc);
6228 sc->bce_link_up = FALSE;
6229 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6230 ifm = &sc->bce_ifmedia;
6231 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
6234 fdx = IFM_OPTIONS(ifm->ifm_media) & IFM_FDX;
6235 switch(IFM_SUBTYPE(ifm->ifm_media)) {
6238 * Check advertised link of remote PHY by reading
6239 * BCE_RPHY_SERDES_LINK or BCE_RPHY_COPPER_LINK.
6240 * Always use the same link type of remote PHY.
6242 link = bce_get_rphy_link(sc);
6245 if ((sc->bce_phy_flags &
6246 (BCE_PHY_REMOTE_PORT_FIBER_FLAG |
6247 BCE_PHY_2_5G_CAPABLE_FLAG)) == 0)
6251 * Have to enable forced 2.5Gbps configuration.
6254 link |= BCE_NETLINK_SPEED_2500FULL;
6256 link |= BCE_NETLINK_SPEED_2500HALF;
6259 if ((sc->bce_phy_flags &
6260 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6264 * Have to disable 2.5Gbps configuration.
6267 link = BCE_NETLINK_SPEED_1000FULL;
6269 link = BCE_NETLINK_SPEED_1000HALF;
6272 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6275 link = BCE_NETLINK_SPEED_1000FULL;
6277 link = BCE_NETLINK_SPEED_1000HALF;
6280 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6283 link = BCE_NETLINK_SPEED_100FULL;
6285 link = BCE_NETLINK_SPEED_100HALF;
6288 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6291 link = BCE_NETLINK_SPEED_10FULL;
6293 link = BCE_NETLINK_SPEED_10HALF;
6298 if (IFM_SUBTYPE(ifm->ifm_media) != IFM_AUTO) {
6301 * Advertise pause capability for full-duplex media.
6304 link |= BCE_NETLINK_FC_PAUSE_SYM |
6305 BCE_NETLINK_FC_PAUSE_ASYM;
6306 if ((sc->bce_phy_flags &
6307 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6308 link |= BCE_NETLINK_PHY_APP_REMOTE |
6309 BCE_NETLINK_ETH_AT_WIRESPEED;
6312 bce_shmem_wr(sc, BCE_MB_ARGS_0, link);
6313 error = bce_fw_sync(sc, BCE_DRV_MSG_CODE_CMD_SET_LINK);
6315 mii = device_get_softc(sc->bce_miibus);
6317 /* Make sure the MII bus has been enumerated. */
6319 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
6321 error = mii_mediachg(mii);
6325 DBEXIT(BCE_VERBOSE_PHY);
6331 bce_ifmedia_sts_rphy(struct bce_softc *sc, struct ifmediareq *ifmr)
6337 BCE_LOCK_ASSERT(sc);
6339 ifmr->ifm_status = IFM_AVALID;
6340 ifmr->ifm_active = IFM_ETHER;
6341 link = bce_shmem_rd(sc, BCE_LINK_STATUS);
6342 /* XXX Handle heart beat status? */
6343 if ((link & BCE_LINK_STATUS_LINK_UP) != 0)
6344 ifmr->ifm_status |= IFM_ACTIVE;
6346 ifmr->ifm_active |= IFM_NONE;
6347 ifp->if_baudrate = 0;
6350 switch (link & BCE_LINK_STATUS_SPEED_MASK) {
6351 case BCE_LINK_STATUS_10HALF:
6352 ifmr->ifm_active |= IFM_10_T | IFM_HDX;
6353 ifp->if_baudrate = IF_Mbps(10UL);
6355 case BCE_LINK_STATUS_10FULL:
6356 ifmr->ifm_active |= IFM_10_T | IFM_FDX;
6357 ifp->if_baudrate = IF_Mbps(10UL);
6359 case BCE_LINK_STATUS_100HALF:
6360 ifmr->ifm_active |= IFM_100_TX | IFM_HDX;
6361 ifp->if_baudrate = IF_Mbps(100UL);
6363 case BCE_LINK_STATUS_100FULL:
6364 ifmr->ifm_active |= IFM_100_TX | IFM_FDX;
6365 ifp->if_baudrate = IF_Mbps(100UL);
6367 case BCE_LINK_STATUS_1000HALF:
6368 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6369 ifmr->ifm_active |= IFM_1000_T | IFM_HDX;
6371 ifmr->ifm_active |= IFM_1000_SX | IFM_HDX;
6372 ifp->if_baudrate = IF_Mbps(1000UL);
6374 case BCE_LINK_STATUS_1000FULL:
6375 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6376 ifmr->ifm_active |= IFM_1000_T | IFM_FDX;
6378 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
6379 ifp->if_baudrate = IF_Mbps(1000UL);
6381 case BCE_LINK_STATUS_2500HALF:
6382 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6383 ifmr->ifm_active |= IFM_NONE;
6386 ifmr->ifm_active |= IFM_2500_SX | IFM_HDX;
6387 ifp->if_baudrate = IF_Mbps(2500UL);
6389 case BCE_LINK_STATUS_2500FULL:
6390 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6391 ifmr->ifm_active |= IFM_NONE;
6394 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX;
6395 ifp->if_baudrate = IF_Mbps(2500UL);
6398 ifmr->ifm_active |= IFM_NONE;
6402 if ((link & BCE_LINK_STATUS_RX_FC_ENABLED) != 0)
6403 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
6404 if ((link & BCE_LINK_STATUS_TX_FC_ENABLED) != 0)
6405 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
6409 /****************************************************************************/
6410 /* Reports current media status. */
6414 /****************************************************************************/
6416 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
6418 struct bce_softc *sc = ifp->if_softc;
6419 struct mii_data *mii;
6421 DBENTER(BCE_VERBOSE_PHY);
6425 if ((ifp->if_flags & IFF_UP) == 0) {
6430 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
6431 bce_ifmedia_sts_rphy(sc, ifmr);
6433 mii = device_get_softc(sc->bce_miibus);
6435 ifmr->ifm_active = mii->mii_media_active;
6436 ifmr->ifm_status = mii->mii_media_status;
6441 DBEXIT(BCE_VERBOSE_PHY);
6445 /****************************************************************************/
6446 /* Handles PHY generated interrupt events. */
6450 /****************************************************************************/
6452 bce_phy_intr(struct bce_softc *sc)
6454 u32 new_link_state, old_link_state;
6456 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
6458 DBRUN(sc->phy_interrupts++);
6460 new_link_state = sc->status_block->status_attn_bits &
6461 STATUS_ATTN_BITS_LINK_STATE;
6462 old_link_state = sc->status_block->status_attn_bits_ack &
6463 STATUS_ATTN_BITS_LINK_STATE;
6465 /* Handle any changes if the link state has changed. */
6466 if (new_link_state != old_link_state) {
6468 /* Update the status_attn_bits_ack field. */
6469 if (new_link_state) {
6470 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
6471 STATUS_ATTN_BITS_LINK_STATE);
6472 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n",
6475 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
6476 STATUS_ATTN_BITS_LINK_STATE);
6477 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n",
6481 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6482 if (new_link_state) {
6484 if_printf(sc->bce_ifp, "link UP\n");
6485 if_link_state_change(sc->bce_ifp,
6489 if_printf(sc->bce_ifp, "link DOWN\n");
6490 if_link_state_change(sc->bce_ifp,
6495 * Assume link is down and allow
6496 * tick routine to update the state
6497 * based on the actual media state.
6499 sc->bce_link_up = FALSE;
6500 callout_stop(&sc->bce_tick_callout);
6504 /* Acknowledge the link change interrupt. */
6505 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
6507 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
6511 /****************************************************************************/
6512 /* Reads the receive consumer value from the status block (skipping over */
6513 /* chain page pointer if necessary). */
6517 /****************************************************************************/
6519 bce_get_hw_rx_cons(struct bce_softc *sc)
6524 hw_cons = sc->status_block->status_rx_quick_consumer_index0;
6525 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
6531 /****************************************************************************/
6532 /* Handles received frame interrupt events. */
6536 /****************************************************************************/
6538 bce_rx_intr(struct bce_softc *sc)
6540 struct ifnet *ifp = sc->bce_ifp;
6541 struct l2_fhdr *l2fhdr;
6542 struct ether_vlan_header *vh;
6543 unsigned int pkt_len;
6544 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons;
6546 unsigned int rem_len;
6547 u16 sw_pg_cons, sw_pg_cons_idx;
6549 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6550 DBRUN(sc->interrupts_rx++);
6551 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, "
6552 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6553 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6555 /* Prepare the RX chain pages to be accessed by the host CPU. */
6556 for (int i = 0; i < sc->rx_pages; i++)
6557 bus_dmamap_sync(sc->rx_bd_chain_tag,
6558 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
6560 /* Prepare the page chain pages to be accessed by the host CPU. */
6561 if (bce_hdr_split == TRUE) {
6562 for (int i = 0; i < sc->pg_pages; i++)
6563 bus_dmamap_sync(sc->pg_bd_chain_tag,
6564 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
6567 /* Get the hardware's view of the RX consumer index. */
6568 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6570 /* Get working copies of the driver's view of the consumer indices. */
6571 sw_rx_cons = sc->rx_cons;
6572 sw_pg_cons = sc->pg_cons;
6574 /* Update some debug statistics counters */
6575 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
6576 sc->rx_low_watermark = sc->free_rx_bd);
6577 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
6578 sc->rx_empty_count++);
6580 /* Scan through the receive chain as long as there is work to do */
6581 /* ToDo: Consider setting a limit on the number of packets processed. */
6583 while (sw_rx_cons != hw_rx_cons) {
6586 /* Convert the producer/consumer indices to an actual rx_bd index. */
6587 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons);
6589 /* Unmap the mbuf from DMA space. */
6590 bus_dmamap_sync(sc->rx_mbuf_tag,
6591 sc->rx_mbuf_map[sw_rx_cons_idx],
6592 BUS_DMASYNC_POSTREAD);
6593 bus_dmamap_unload(sc->rx_mbuf_tag,
6594 sc->rx_mbuf_map[sw_rx_cons_idx]);
6596 /* Remove the mbuf from the RX chain. */
6597 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx];
6598 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL;
6599 DBRUN(sc->debug_rx_mbuf_alloc--);
6603 * Frames received on the NetXteme II are prepended
6604 * with an l2_fhdr structure which provides status
6605 * information about the received frame (including
6606 * VLAN tags and checksum info). The frames are
6607 * also automatically adjusted to word align the IP
6608 * header (i.e. two null bytes are inserted before
6609 * the Ethernet header). As a result the data
6610 * DMA'd by the controller into the mbuf looks
6613 * +---------+-----+---------------------+-----+
6614 * | l2_fhdr | pad | packet data | FCS |
6615 * +---------+-----+---------------------+-----+
6617 * The l2_fhdr needs to be checked and skipped and
6618 * the FCS needs to be stripped before sending the
6619 * packet up the stack.
6621 l2fhdr = mtod(m0, struct l2_fhdr *);
6623 /* Get the packet data + FCS length and the status. */
6624 pkt_len = l2fhdr->l2_fhdr_pkt_len;
6625 status = l2fhdr->l2_fhdr_status;
6628 * Skip over the l2_fhdr and pad, resulting in the
6629 * following data in the mbuf:
6630 * +---------------------+-----+
6631 * | packet data | FCS |
6632 * +---------------------+-----+
6634 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN);
6637 * When split header mode is used, an ethernet frame
6638 * may be split across the receive chain and the
6639 * page chain. If that occurs an mbuf cluster must be
6640 * reassembled from the individual mbuf pieces.
6642 if (bce_hdr_split == TRUE) {
6644 * Check whether the received frame fits in a single
6645 * mbuf or not (i.e. packet data + FCS <=
6646 * sc->rx_bd_mbuf_data_len bytes).
6648 if (pkt_len > m0->m_len) {
6650 * The received frame is larger than a single mbuf.
6651 * If the frame was a TCP frame then only the TCP
6652 * header is placed in the mbuf, the remaining
6653 * payload (including FCS) is placed in the page
6654 * chain, the SPLIT flag is set, and the header
6655 * length is placed in the IP checksum field.
6656 * If the frame is not a TCP frame then the mbuf
6657 * is filled and the remaining bytes are placed
6658 * in the page chain.
6661 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large "
6662 "packet.\n", __FUNCTION__);
6663 DBRUN(sc->split_header_frames_rcvd++);
6666 * When the page chain is enabled and the TCP
6667 * header has been split from the TCP payload,
6668 * the ip_xsum structure will reflect the length
6669 * of the TCP header, not the IP checksum. Set
6670 * the packet length of the mbuf accordingly.
6672 if (status & L2_FHDR_STATUS_SPLIT) {
6673 m0->m_len = l2fhdr->l2_fhdr_ip_xsum;
6674 DBRUN(sc->split_header_tcp_frames_rcvd++);
6677 rem_len = pkt_len - m0->m_len;
6679 /* Pull mbufs off the page chain for any remaining data. */
6680 while (rem_len > 0) {
6683 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons);
6685 /* Remove the mbuf from the page chain. */
6686 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx];
6687 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL;
6688 DBRUN(sc->debug_pg_mbuf_alloc--);
6691 /* Unmap the page chain mbuf from DMA space. */
6692 bus_dmamap_sync(sc->pg_mbuf_tag,
6693 sc->pg_mbuf_map[sw_pg_cons_idx],
6694 BUS_DMASYNC_POSTREAD);
6695 bus_dmamap_unload(sc->pg_mbuf_tag,
6696 sc->pg_mbuf_map[sw_pg_cons_idx]);
6698 /* Adjust the mbuf length. */
6699 if (rem_len < m_pg->m_len) {
6700 /* The mbuf chain is complete. */
6701 m_pg->m_len = rem_len;
6704 /* More packet data is waiting. */
6705 rem_len -= m_pg->m_len;
6708 /* Concatenate the mbuf cluster to the mbuf. */
6711 sw_pg_cons = NEXT_PG_BD(sw_pg_cons);
6714 /* Set the total packet length. */
6715 m0->m_pkthdr.len = pkt_len;
6719 * The received packet is small and fits in a
6720 * single mbuf (i.e. the l2_fhdr + pad + packet +
6721 * FCS <= MHLEN). In other words, the packet is
6722 * 154 bytes or less in size.
6725 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small "
6726 "packet.\n", __FUNCTION__);
6728 /* Set the total packet length. */
6729 m0->m_pkthdr.len = m0->m_len = pkt_len;
6732 /* Set the total packet length. */
6733 m0->m_pkthdr.len = m0->m_len = pkt_len;
6735 /* Remove the trailing Ethernet FCS. */
6736 m_adj(m0, -ETHER_CRC_LEN);
6738 /* Check that the resulting mbuf chain is valid. */
6739 DBRUN(m_sanity(m0, FALSE));
6740 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) |
6741 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)),
6742 BCE_PRINTF("Invalid Ethernet frame size!\n");
6745 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control),
6746 sc->l2fhdr_error_sim_count++;
6747 status = status | L2_FHDR_ERRORS_PHY_DECODE);
6749 /* Check the received frame for errors. */
6750 if (status & (L2_FHDR_ERRORS_BAD_CRC |
6751 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT |
6752 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) {
6754 /* Log the error and release the mbuf. */
6755 sc->l2fhdr_error_count++;
6758 goto bce_rx_intr_next_rx;
6761 /* Send the packet to the appropriate interface. */
6762 m0->m_pkthdr.rcvif = ifp;
6764 /* Assume no hardware checksum. */
6765 m0->m_pkthdr.csum_flags = 0;
6767 /* Validate the checksum if offload enabled. */
6768 if (ifp->if_capenable & IFCAP_RXCSUM) {
6769 /* Check for an IP datagram. */
6770 if (!(status & L2_FHDR_STATUS_SPLIT) &&
6771 (status & L2_FHDR_STATUS_IP_DATAGRAM)) {
6772 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
6773 DBRUN(sc->csum_offload_ip++);
6774 /* Check if the IP checksum is valid. */
6775 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0)
6776 m0->m_pkthdr.csum_flags |=
6780 /* Check for a valid TCP/UDP frame. */
6781 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
6782 L2_FHDR_STATUS_UDP_DATAGRAM)) {
6784 /* Check for a good TCP/UDP checksum. */
6785 if ((status & (L2_FHDR_ERRORS_TCP_XSUM |
6786 L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
6787 DBRUN(sc->csum_offload_tcp_udp++);
6788 m0->m_pkthdr.csum_data =
6789 l2fhdr->l2_fhdr_tcp_udp_xsum;
6790 m0->m_pkthdr.csum_flags |=
6797 /* Attach the VLAN tag. */
6798 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
6799 !(sc->rx_mode & BCE_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
6800 DBRUN(sc->vlan_tagged_frames_rcvd++);
6801 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
6802 DBRUN(sc->vlan_tagged_frames_stripped++);
6803 #if __FreeBSD_version < 700000
6804 VLAN_INPUT_TAG(ifp, m0,
6805 l2fhdr->l2_fhdr_vlan_tag, continue);
6807 m0->m_pkthdr.ether_vtag =
6808 l2fhdr->l2_fhdr_vlan_tag;
6809 m0->m_flags |= M_VLANTAG;
6813 * bce(4) controllers can't disable VLAN
6814 * tag stripping if management firmware
6815 * (ASF/IPMI/UMP) is running. So we always
6816 * strip VLAN tag and manually reconstruct
6817 * the VLAN frame by appending stripped
6818 * VLAN tag in driver if VLAN tag stripping
6821 * TODO: LLC SNAP handling.
6823 bcopy(mtod(m0, uint8_t *),
6824 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN,
6825 ETHER_ADDR_LEN * 2);
6826 m0->m_data -= ETHER_VLAN_ENCAP_LEN;
6827 vh = mtod(m0, struct ether_vlan_header *);
6828 vh->evl_encap_proto = htons(ETHERTYPE_VLAN);
6829 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag);
6830 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN;
6831 m0->m_len += ETHER_VLAN_ENCAP_LEN;
6835 /* Increment received packet statistics. */
6836 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
6838 bce_rx_intr_next_rx:
6839 sw_rx_cons = NEXT_RX_BD(sw_rx_cons);
6841 /* If we have a packet, pass it up the stack */
6843 /* Make sure we don't lose our place when we release the lock. */
6844 sc->rx_cons = sw_rx_cons;
6845 sc->pg_cons = sw_pg_cons;
6848 (*ifp->if_input)(ifp, m0);
6851 /* Recover our place. */
6852 sw_rx_cons = sc->rx_cons;
6853 sw_pg_cons = sc->pg_cons;
6856 /* Refresh hw_cons to see if there's new work */
6857 if (sw_rx_cons == hw_rx_cons)
6858 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6861 /* No new packets. Refill the page chain. */
6862 if (bce_hdr_split == TRUE) {
6863 sc->pg_cons = sw_pg_cons;
6864 bce_fill_pg_chain(sc);
6867 /* No new packets. Refill the RX chain. */
6868 sc->rx_cons = sw_rx_cons;
6869 bce_fill_rx_chain(sc);
6871 /* Prepare the page chain pages to be accessed by the NIC. */
6872 for (int i = 0; i < sc->rx_pages; i++)
6873 bus_dmamap_sync(sc->rx_bd_chain_tag,
6874 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6876 if (bce_hdr_split == TRUE) {
6877 for (int i = 0; i < sc->pg_pages; i++)
6878 bus_dmamap_sync(sc->pg_bd_chain_tag,
6879 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6882 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, "
6883 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6884 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6885 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6889 /****************************************************************************/
6890 /* Reads the transmit consumer value from the status block (skipping over */
6891 /* chain page pointer if necessary). */
6895 /****************************************************************************/
6897 bce_get_hw_tx_cons(struct bce_softc *sc)
6902 hw_cons = sc->status_block->status_tx_quick_consumer_index0;
6903 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
6910 /****************************************************************************/
6911 /* Handles transmit completion interrupt events. */
6915 /****************************************************************************/
6917 bce_tx_intr(struct bce_softc *sc)
6919 struct ifnet *ifp = sc->bce_ifp;
6920 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
6922 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
6923 DBRUN(sc->interrupts_tx++);
6924 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, "
6925 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
6926 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
6928 BCE_LOCK_ASSERT(sc);
6930 /* Get the hardware's view of the TX consumer index. */
6931 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6932 sw_tx_cons = sc->tx_cons;
6934 /* Prevent speculative reads of the status block. */
6935 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6936 BUS_SPACE_BARRIER_READ);
6938 /* Cycle through any completed TX chain page entries. */
6939 while (sw_tx_cons != hw_tx_cons) {
6941 struct tx_bd *txbd = NULL;
6943 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
6945 DBPRINT(sc, BCE_INFO_SEND,
6946 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
6947 "sw_tx_chain_cons = 0x%04X\n",
6948 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
6950 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC),
6951 BCE_PRINTF("%s(%d): TX chain consumer out of range! "
6952 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons,
6953 (int) MAX_TX_BD_ALLOC);
6954 bce_breakpoint(sc));
6956 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
6957 [TX_IDX(sw_tx_chain_cons)]);
6959 DBRUNIF((txbd == NULL),
6960 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n",
6961 __FILE__, __LINE__, sw_tx_chain_cons);
6962 bce_breakpoint(sc));
6964 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__);
6965 bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
6968 * Free the associated mbuf. Remember
6969 * that only the last tx_bd of a packet
6970 * has an mbuf pointer and DMA map.
6972 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
6974 /* Validate that this is the last tx_bd. */
6975 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
6976 BCE_PRINTF("%s(%d): tx_bd END flag not set but "
6977 "txmbuf == NULL!\n", __FILE__, __LINE__);
6978 bce_breakpoint(sc));
6980 DBRUNMSG(BCE_INFO_SEND,
6981 BCE_PRINTF("%s(): Unloading map/freeing mbuf "
6982 "from tx_bd[0x%04X]\n", __FUNCTION__,
6985 /* Unmap the mbuf. */
6986 bus_dmamap_unload(sc->tx_mbuf_tag,
6987 sc->tx_mbuf_map[sw_tx_chain_cons]);
6989 /* Free the mbuf. */
6990 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
6991 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
6992 DBRUN(sc->debug_tx_mbuf_alloc--);
6994 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
6998 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
7000 /* Refresh hw_cons to see if there's new work. */
7001 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
7003 /* Prevent speculative reads of the status block. */
7004 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
7005 BUS_SPACE_BARRIER_READ);
7008 /* Clear the TX timeout timer. */
7009 sc->watchdog_timer = 0;
7011 /* Clear the tx hardware queue full flag. */
7012 if (sc->used_tx_bd < sc->max_tx_bd) {
7013 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE),
7014 DBPRINT(sc, BCE_INFO_SEND,
7015 "%s(): Open TX chain! %d/%d (used/total)\n",
7016 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd));
7017 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
7020 sc->tx_cons = sw_tx_cons;
7022 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, "
7023 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
7024 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
7025 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
7029 /****************************************************************************/
7030 /* Disables interrupt generation. */
7034 /****************************************************************************/
7036 bce_disable_intr(struct bce_softc *sc)
7038 DBENTER(BCE_VERBOSE_INTR);
7040 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
7041 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
7043 DBEXIT(BCE_VERBOSE_INTR);
7047 /****************************************************************************/
7048 /* Enables interrupt generation. */
7052 /****************************************************************************/
7054 bce_enable_intr(struct bce_softc *sc, int coal_now)
7056 DBENTER(BCE_VERBOSE_INTR);
7058 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7059 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
7060 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
7062 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7063 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
7065 /* Force an immediate interrupt (whether there is new data or not). */
7067 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
7069 DBEXIT(BCE_VERBOSE_INTR);
7073 /****************************************************************************/
7074 /* Handles controller initialization. */
7078 /****************************************************************************/
7080 bce_init_locked(struct bce_softc *sc)
7085 DBENTER(BCE_VERBOSE_RESET);
7087 BCE_LOCK_ASSERT(sc);
7091 /* Check if the driver is still running and bail out if it is. */
7092 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
7093 goto bce_init_locked_exit;
7097 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
7098 BCE_PRINTF("%s(%d): Controller reset failed!\n",
7099 __FILE__, __LINE__);
7100 goto bce_init_locked_exit;
7103 if (bce_chipinit(sc)) {
7104 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
7105 __FILE__, __LINE__);
7106 goto bce_init_locked_exit;
7109 if (bce_blockinit(sc)) {
7110 BCE_PRINTF("%s(%d): Block initialization failed!\n",
7111 __FILE__, __LINE__);
7112 goto bce_init_locked_exit;
7115 /* Load our MAC address. */
7116 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN);
7117 bce_set_mac_addr(sc);
7119 if (bce_hdr_split == FALSE)
7120 bce_get_rx_buffer_sizes(sc, ifp->if_mtu);
7122 * Calculate and program the hardware Ethernet MTU
7123 * size. Be generous on the receive if we have room
7124 * and allowed by the user.
7126 if (bce_strict_rx_mtu == TRUE)
7127 ether_mtu = ifp->if_mtu;
7129 if (bce_hdr_split == TRUE) {
7130 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len + MCLBYTES)
7131 ether_mtu = sc->rx_bd_mbuf_data_len +
7134 ether_mtu = ifp->if_mtu;
7136 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len)
7137 ether_mtu = sc->rx_bd_mbuf_data_len;
7139 ether_mtu = ifp->if_mtu;
7143 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
7145 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n",
7146 __FUNCTION__, ether_mtu);
7148 /* Program the mtu, enabling jumbo frame support if necessary. */
7149 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN))
7150 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
7151 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
7152 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
7154 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
7156 /* Program appropriate promiscuous/multicast filtering. */
7157 bce_set_rx_mode(sc);
7159 if (bce_hdr_split == TRUE) {
7160 /* Init page buffer descriptor chain. */
7161 bce_init_pg_chain(sc);
7164 /* Init RX buffer descriptor chain. */
7165 bce_init_rx_chain(sc);
7167 /* Init TX buffer descriptor chain. */
7168 bce_init_tx_chain(sc);
7170 /* Enable host interrupts. */
7171 bce_enable_intr(sc, 1);
7173 bce_ifmedia_upd_locked(ifp);
7175 /* Let the OS know the driver is up and running. */
7176 ifp->if_drv_flags |= IFF_DRV_RUNNING;
7177 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
7179 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
7181 bce_init_locked_exit:
7182 DBEXIT(BCE_VERBOSE_RESET);
7186 /****************************************************************************/
7187 /* Initialize the controller just enough so that any management firmware */
7188 /* running on the device will continue to operate correctly. */
7192 /****************************************************************************/
7194 bce_mgmt_init_locked(struct bce_softc *sc)
7198 DBENTER(BCE_VERBOSE_RESET);
7200 BCE_LOCK_ASSERT(sc);
7202 /* Bail out if management firmware is not running. */
7203 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) {
7204 DBPRINT(sc, BCE_VERBOSE_SPECIAL,
7205 "No management firmware running...\n");
7206 goto bce_mgmt_init_locked_exit;
7211 /* Enable all critical blocks in the MAC. */
7212 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
7213 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
7216 bce_ifmedia_upd_locked(ifp);
7218 bce_mgmt_init_locked_exit:
7219 DBEXIT(BCE_VERBOSE_RESET);
7223 /****************************************************************************/
7224 /* Handles controller initialization when called from an unlocked routine. */
7228 /****************************************************************************/
7232 struct bce_softc *sc = xsc;
7234 DBENTER(BCE_VERBOSE_RESET);
7237 bce_init_locked(sc);
7240 DBEXIT(BCE_VERBOSE_RESET);
7244 /****************************************************************************/
7245 /* Modifies an mbuf for TSO on the hardware. */
7248 /* Pointer to a modified mbuf. */
7249 /****************************************************************************/
7250 static struct mbuf *
7251 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags)
7254 struct ether_header *eh;
7258 int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0;
7260 DBRUN(sc->tso_frames_requested++);
7262 /* Controller may modify mbuf chains. */
7263 if (M_WRITABLE(*m_head) == 0) {
7264 m = m_dup(*m_head, M_NOWAIT);
7267 sc->mbuf_alloc_failed_count++;
7275 * For TSO the controller needs two pieces of info,
7276 * the MSS and the IP+TCP options length.
7278 m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip));
7283 eh = mtod(m, struct ether_header *);
7284 etype = ntohs(eh->ether_type);
7286 /* Check for supported TSO Ethernet types (only IPv4 for now) */
7289 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7290 /* TSO only supported for TCP protocol. */
7291 if (ip->ip_p != IPPROTO_TCP) {
7292 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n",
7293 __FILE__, __LINE__);
7299 /* Get IP header length in bytes (min 20) */
7300 ip_hlen = ip->ip_hl << 2;
7301 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen +
7302 sizeof(struct tcphdr));
7308 /* Get the TCP header length in bytes (min 20) */
7309 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7310 th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
7311 tcp_hlen = (th->th_off << 2);
7313 /* Make sure all IP/TCP options live in the same buffer. */
7314 m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen +
7321 /* Clear IP header length and checksum, will be calc'd by h/w. */
7322 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7323 ip_len = ip->ip_len;
7327 case ETHERTYPE_IPV6:
7328 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n",
7329 __FILE__, __LINE__);
7335 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n",
7336 __FILE__, __LINE__);
7342 hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen;
7344 DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, "
7345 "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n",
7346 __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen,
7349 /* Set the LSO flag in the TX BD */
7350 *flags |= TX_BD_FLAGS_SW_LSO;
7352 /* Set the length of IP + TCP options (in 32 bit words) */
7353 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) -
7354 sizeof(struct tcphdr)) >> 2) << 8);
7356 DBRUN(sc->tso_frames_completed++);
7361 /****************************************************************************/
7362 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
7363 /* memory visible to the controller. */
7366 /* 0 for success, positive value for failure. */
7368 /* m_head: May be set to NULL if MBUF is excessively fragmented. */
7369 /****************************************************************************/
7371 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head)
7373 bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
7375 struct tx_bd *txbd = NULL;
7377 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0;
7384 int i, error, nsegs, rc = 0;
7386 DBENTER(BCE_VERBOSE_SEND);
7388 /* Make sure we have room in the TX chain. */
7389 if (sc->used_tx_bd >= sc->max_tx_bd)
7390 goto bce_tx_encap_exit;
7392 /* Transfer any checksum offload flags to the bd. */
7394 if (m0->m_pkthdr.csum_flags) {
7395 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
7396 m0 = bce_tso_setup(sc, m_head, &flags);
7398 DBRUN(sc->tso_frames_failed++);
7399 goto bce_tx_encap_exit;
7401 mss = htole16(m0->m_pkthdr.tso_segsz);
7403 if (m0->m_pkthdr.csum_flags & CSUM_IP)
7404 flags |= TX_BD_FLAGS_IP_CKSUM;
7405 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
7406 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
7410 /* Transfer any VLAN tags to the bd. */
7411 if (m0->m_flags & M_VLANTAG) {
7412 flags |= TX_BD_FLAGS_VLAN_TAG;
7413 vlan_tag = m0->m_pkthdr.ether_vtag;
7416 /* Map the mbuf into DMAable memory. */
7418 chain_prod = TX_CHAIN_IDX(prod);
7419 map = sc->tx_mbuf_map[chain_prod];
7421 /* Map the mbuf into our DMA address space. */
7422 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
7423 segs, &nsegs, BUS_DMA_NOWAIT);
7425 /* Check if the DMA mapping was successful */
7426 if (error == EFBIG) {
7427 sc->mbuf_frag_count++;
7429 /* Try to defrag the mbuf. */
7430 m0 = m_collapse(*m_head, M_NOWAIT, BCE_MAX_SEGMENTS);
7432 /* Defrag was unsuccessful */
7435 sc->mbuf_alloc_failed_count++;
7437 goto bce_tx_encap_exit;
7440 /* Defrag was successful, try mapping again */
7442 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag,
7443 map, m0, segs, &nsegs, BUS_DMA_NOWAIT);
7445 /* Still getting an error after a defrag. */
7446 if (error == ENOMEM) {
7447 /* Insufficient DMA buffers available. */
7448 sc->dma_map_addr_tx_failed_count++;
7450 goto bce_tx_encap_exit;
7451 } else if (error != 0) {
7452 /* Release it and return an error. */
7453 BCE_PRINTF("%s(%d): Unknown error mapping mbuf into "
7454 "TX chain!\n", __FILE__, __LINE__);
7457 sc->dma_map_addr_tx_failed_count++;
7459 goto bce_tx_encap_exit;
7461 } else if (error == ENOMEM) {
7462 /* Insufficient DMA buffers available. */
7463 sc->dma_map_addr_tx_failed_count++;
7465 goto bce_tx_encap_exit;
7466 } else if (error != 0) {
7469 sc->dma_map_addr_tx_failed_count++;
7471 goto bce_tx_encap_exit;
7474 /* Make sure there's room in the chain */
7475 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) {
7476 bus_dmamap_unload(sc->tx_mbuf_tag, map);
7478 goto bce_tx_encap_exit;
7481 /* prod points to an empty tx_bd at this point. */
7482 prod_bseq = sc->tx_prod_bseq;
7485 debug_prod = chain_prod;
7488 DBPRINT(sc, BCE_INFO_SEND,
7489 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, "
7490 "prod_bseq = 0x%08X\n",
7491 __FUNCTION__, prod, chain_prod, prod_bseq);
7494 * Cycle through each mbuf segment that makes up
7495 * the outgoing frame, gathering the mapping info
7496 * for that segment and creating a tx_bd for
7499 for (i = 0; i < nsegs ; i++) {
7501 chain_prod = TX_CHAIN_IDX(prod);
7502 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)]
7503 [TX_IDX(chain_prod)];
7505 txbd->tx_bd_haddr_lo =
7506 htole32(BCE_ADDR_LO(segs[i].ds_addr));
7507 txbd->tx_bd_haddr_hi =
7508 htole32(BCE_ADDR_HI(segs[i].ds_addr));
7509 txbd->tx_bd_mss_nbytes = htole32(mss << 16) |
7510 htole16(segs[i].ds_len);
7511 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
7512 txbd->tx_bd_flags = htole16(flags);
7513 prod_bseq += segs[i].ds_len;
7515 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
7516 prod = NEXT_TX_BD(prod);
7519 /* Set the END flag on the last TX buffer descriptor. */
7520 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
7522 DBRUNMSG(BCE_EXTREME_SEND,
7523 bce_dump_tx_chain(sc, debug_prod, nsegs));
7526 * Ensure that the mbuf pointer for this transmission
7527 * is placed at the array index of the last
7528 * descriptor in this chain. This is done
7529 * because a single map is used for all
7530 * segments of the mbuf and we don't want to
7531 * unload the map before all of the segments
7534 sc->tx_mbuf_ptr[chain_prod] = m0;
7535 sc->used_tx_bd += nsegs;
7537 /* Update some debug statistic counters */
7538 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
7539 sc->tx_hi_watermark = sc->used_tx_bd);
7540 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
7541 DBRUNIF(sc->debug_tx_mbuf_alloc++);
7543 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1));
7545 /* prod points to the next free tx_bd at this point. */
7547 sc->tx_prod_bseq = prod_bseq;
7549 /* Tell the chip about the waiting TX frames. */
7550 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) +
7551 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod);
7552 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) +
7553 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq);
7556 DBEXIT(BCE_VERBOSE_SEND);
7561 /****************************************************************************/
7562 /* Main transmit routine when called from another routine with a lock. */
7566 /****************************************************************************/
7568 bce_start_locked(struct ifnet *ifp)
7570 struct bce_softc *sc = ifp->if_softc;
7571 struct mbuf *m_head = NULL;
7573 u16 tx_prod, tx_chain_prod;
7575 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7577 BCE_LOCK_ASSERT(sc);
7579 /* prod points to the next free tx_bd. */
7580 tx_prod = sc->tx_prod;
7581 tx_chain_prod = TX_CHAIN_IDX(tx_prod);
7583 DBPRINT(sc, BCE_INFO_SEND,
7584 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
7585 "tx_prod_bseq = 0x%08X\n",
7586 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq);
7588 /* If there's no link or the transmit queue is empty then just exit. */
7589 if (sc->bce_link_up == FALSE) {
7590 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n",
7592 goto bce_start_locked_exit;
7595 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
7596 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n",
7598 goto bce_start_locked_exit;
7602 * Keep adding entries while there is space in the ring.
7604 while (sc->used_tx_bd < sc->max_tx_bd) {
7606 /* Check for any frames to send. */
7607 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
7609 /* Stop when the transmit queue is empty. */
7614 * Pack the data into the transmit ring. If we
7615 * don't have room, place the mbuf back at the
7616 * head of the queue and set the OACTIVE flag
7617 * to wait for the NIC to drain the chain.
7619 if (bce_tx_encap(sc, &m_head)) {
7621 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
7622 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
7623 DBPRINT(sc, BCE_INFO_SEND,
7624 "TX chain is closed for business! Total "
7625 "tx_bd used = %d\n", sc->used_tx_bd);
7631 /* Send a copy of the frame to any BPF listeners. */
7632 ETHER_BPF_MTAP(ifp, m_head);
7635 /* Exit if no packets were dequeued. */
7637 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were "
7638 "dequeued\n", __FUNCTION__);
7639 goto bce_start_locked_exit;
7642 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into "
7643 "send queue.\n", __FUNCTION__, count);
7645 /* Set the tx timeout. */
7646 sc->watchdog_timer = BCE_TX_TIMEOUT;
7648 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID));
7649 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc));
7651 bce_start_locked_exit:
7652 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7656 /****************************************************************************/
7657 /* Main transmit routine when called from another routine without a lock. */
7661 /****************************************************************************/
7663 bce_start(struct ifnet *ifp)
7665 struct bce_softc *sc = ifp->if_softc;
7667 DBENTER(BCE_VERBOSE_SEND);
7670 bce_start_locked(ifp);
7673 DBEXIT(BCE_VERBOSE_SEND);
7677 /****************************************************************************/
7678 /* Handles any IOCTL calls from the operating system. */
7681 /* 0 for success, positive value for failure. */
7682 /****************************************************************************/
7684 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
7686 struct bce_softc *sc = ifp->if_softc;
7687 struct ifreq *ifr = (struct ifreq *) data;
7688 struct mii_data *mii;
7689 int mask, error = 0;
7691 DBENTER(BCE_VERBOSE_MISC);
7695 /* Set the interface MTU. */
7697 /* Check that the MTU setting is supported. */
7698 if ((ifr->ifr_mtu < BCE_MIN_MTU) ||
7699 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) {
7704 DBPRINT(sc, BCE_INFO_MISC,
7705 "SIOCSIFMTU: Changing MTU from %d to %d\n",
7706 (int) ifp->if_mtu, (int) ifr->ifr_mtu);
7709 ifp->if_mtu = ifr->ifr_mtu;
7710 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7711 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
7712 bce_init_locked(sc);
7717 /* Set interface flags. */
7719 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n");
7723 /* Check if the interface is up. */
7724 if (ifp->if_flags & IFF_UP) {
7725 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7726 /* Change promiscuous/multicast flags as necessary. */
7727 bce_set_rx_mode(sc);
7730 bce_init_locked(sc);
7733 /* The interface is down, check if driver is running. */
7734 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7737 /* If MFW is running, restart the controller a bit. */
7738 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
7739 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
7741 bce_mgmt_init_locked(sc);
7749 /* Add/Delete multicast address */
7752 DBPRINT(sc, BCE_VERBOSE_MISC,
7753 "Received SIOCADDMULTI/SIOCDELMULTI\n");
7756 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
7757 bce_set_rx_mode(sc);
7762 /* Set/Get Interface media */
7765 DBPRINT(sc, BCE_VERBOSE_MISC,
7766 "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n");
7767 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
7768 error = ifmedia_ioctl(ifp, ifr, &sc->bce_ifmedia,
7771 mii = device_get_softc(sc->bce_miibus);
7772 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
7777 /* Set interface capability */
7779 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
7780 DBPRINT(sc, BCE_INFO_MISC,
7781 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask);
7783 /* Toggle the TX checksum capabilities enable flag. */
7784 if (mask & IFCAP_TXCSUM &&
7785 ifp->if_capabilities & IFCAP_TXCSUM) {
7786 ifp->if_capenable ^= IFCAP_TXCSUM;
7787 if (IFCAP_TXCSUM & ifp->if_capenable)
7788 ifp->if_hwassist |= BCE_IF_HWASSIST;
7790 ifp->if_hwassist &= ~BCE_IF_HWASSIST;
7793 /* Toggle the RX checksum capabilities enable flag. */
7794 if (mask & IFCAP_RXCSUM &&
7795 ifp->if_capabilities & IFCAP_RXCSUM)
7796 ifp->if_capenable ^= IFCAP_RXCSUM;
7798 /* Toggle the TSO capabilities enable flag. */
7799 if (bce_tso_enable && (mask & IFCAP_TSO4) &&
7800 ifp->if_capabilities & IFCAP_TSO4) {
7801 ifp->if_capenable ^= IFCAP_TSO4;
7802 if (IFCAP_TSO4 & ifp->if_capenable)
7803 ifp->if_hwassist |= CSUM_TSO;
7805 ifp->if_hwassist &= ~CSUM_TSO;
7808 if (mask & IFCAP_VLAN_HWCSUM &&
7809 ifp->if_capabilities & IFCAP_VLAN_HWCSUM)
7810 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
7812 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
7813 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
7814 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
7816 * Don't actually disable VLAN tag stripping as
7817 * management firmware (ASF/IPMI/UMP) requires the
7818 * feature. If VLAN tag stripping is disabled driver
7819 * will manually reconstruct the VLAN frame by
7820 * appending stripped VLAN tag.
7822 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
7823 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) {
7824 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
7825 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
7827 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
7829 VLAN_CAPABILITIES(ifp);
7832 /* We don't know how to handle the IOCTL, pass it on. */
7833 error = ether_ioctl(ifp, command, data);
7837 DBEXIT(BCE_VERBOSE_MISC);
7842 /****************************************************************************/
7843 /* Transmit timeout handler. */
7847 /****************************************************************************/
7849 bce_watchdog(struct bce_softc *sc)
7853 DBENTER(BCE_EXTREME_SEND);
7855 BCE_LOCK_ASSERT(sc);
7858 /* If the watchdog timer hasn't expired then just exit. */
7859 if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
7860 goto bce_watchdog_exit;
7862 status = REG_RD(sc, BCE_EMAC_RX_STATUS);
7863 /* If pause frames are active then don't reset the hardware. */
7864 if ((sc->bce_flags & BCE_USING_RX_FLOW_CONTROL) != 0) {
7865 if ((status & BCE_EMAC_RX_STATUS_FFED) != 0) {
7867 * If link partner has us in XOFF state then wait for
7868 * the condition to clear.
7870 sc->watchdog_timer = BCE_TX_TIMEOUT;
7871 goto bce_watchdog_exit;
7872 } else if ((status & BCE_EMAC_RX_STATUS_FF_RECEIVED) != 0 &&
7873 (status & BCE_EMAC_RX_STATUS_N_RECEIVED) != 0) {
7875 * If we're not currently XOFF'ed but have recently
7876 * been XOFF'd/XON'd then assume that's delaying TX
7879 sc->watchdog_timer = BCE_TX_TIMEOUT;
7880 goto bce_watchdog_exit;
7883 * Any other condition is unexpected and the controller
7888 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n",
7889 __FILE__, __LINE__);
7892 bce_dump_driver_state(sc);
7893 bce_dump_status_block(sc);
7894 bce_dump_stats_block(sc);
7896 bce_dump_txp_state(sc, 0);
7897 bce_dump_rxp_state(sc, 0);
7898 bce_dump_tpat_state(sc, 0);
7899 bce_dump_cp_state(sc, 0);
7900 bce_dump_com_state(sc, 0));
7902 DBRUN(bce_breakpoint(sc));
7904 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
7906 bce_init_locked(sc);
7907 sc->watchdog_timeouts++;
7910 REG_WR(sc, BCE_EMAC_RX_STATUS, status);
7911 DBEXIT(BCE_EXTREME_SEND);
7916 * Interrupt handler.
7918 /****************************************************************************/
7919 /* Main interrupt entry point. Verifies that the controller generated the */
7920 /* interrupt and then calls a separate routine for handle the various */
7921 /* interrupt causes (PHY, TX, RX). */
7925 /****************************************************************************/
7929 struct bce_softc *sc;
7931 u32 status_attn_bits;
7932 u16 hw_rx_cons, hw_tx_cons;
7937 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
7938 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
7939 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc));
7943 DBRUN(sc->interrupts_generated++);
7945 /* Synchnorize before we read from interface's status block */
7946 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
7949 * If the hardware status block index matches the last value read
7950 * by the driver and we haven't asserted our interrupt then there's
7951 * nothing to do. This may only happen in case of INTx due to the
7952 * interrupt arriving at the CPU before the status block is updated.
7954 if ((sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) == 0 &&
7955 sc->status_block->status_idx == sc->last_status_idx &&
7956 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
7957 BCE_PCICFG_MISC_STATUS_INTA_VALUE)) {
7958 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n",
7963 /* Ack the interrupt and stop others from occurring. */
7964 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7965 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
7966 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
7968 /* Check if the hardware has finished any work. */
7969 hw_rx_cons = bce_get_hw_rx_cons(sc);
7970 hw_tx_cons = bce_get_hw_tx_cons(sc);
7972 /* Keep processing data as long as there is work to do. */
7975 status_attn_bits = sc->status_block->status_attn_bits;
7977 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control),
7978 BCE_PRINTF("Simulating unexpected status attention "
7980 sc->unexpected_attention_sim_count++;
7981 status_attn_bits = status_attn_bits |
7982 STATUS_ATTN_BITS_PARITY_ERROR);
7984 /* Was it a link change interrupt? */
7985 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
7986 (sc->status_block->status_attn_bits_ack &
7987 STATUS_ATTN_BITS_LINK_STATE)) {
7990 /* Clear transient updates during link state change. */
7991 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command |
7992 BCE_HC_COMMAND_COAL_NOW_WO_INT);
7993 REG_RD(sc, BCE_HC_COMMAND);
7996 /* If any other attention is asserted, the chip is toast. */
7997 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
7998 (sc->status_block->status_attn_bits_ack &
7999 ~STATUS_ATTN_BITS_LINK_STATE))) {
8001 sc->unexpected_attention_count++;
8003 BCE_PRINTF("%s(%d): Fatal attention detected: "
8004 "0x%08X\n", __FILE__, __LINE__,
8005 sc->status_block->status_attn_bits);
8008 if (unexpected_attention_sim_control == 0)
8009 bce_breakpoint(sc));
8011 bce_init_locked(sc);
8015 /* Check for any completed RX frames. */
8016 if (hw_rx_cons != sc->hw_rx_cons)
8019 /* Check for any completed TX frames. */
8020 if (hw_tx_cons != sc->hw_tx_cons)
8023 /* Save status block index value for the next interrupt. */
8024 sc->last_status_idx = sc->status_block->status_idx;
8027 * Prevent speculative reads from getting
8028 * ahead of the status block.
8030 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
8031 BUS_SPACE_BARRIER_READ);
8034 * If there's no work left then exit the
8035 * interrupt service routine.
8037 hw_rx_cons = bce_get_hw_rx_cons(sc);
8038 hw_tx_cons = bce_get_hw_tx_cons(sc);
8040 if ((hw_rx_cons == sc->hw_rx_cons) &&
8041 (hw_tx_cons == sc->hw_tx_cons))
8045 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREREAD);
8047 /* Re-enable interrupts. */
8048 bce_enable_intr(sc, 0);
8050 /* Handle any frames that arrived while handling the interrupt. */
8051 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
8052 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
8053 bce_start_locked(ifp);
8058 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
8062 /****************************************************************************/
8063 /* Programs the various packet receive modes (broadcast and multicast). */
8067 /****************************************************************************/
8069 bce_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
8074 h = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0xFF;
8075 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
8081 bce_set_rx_mode(struct bce_softc *sc)
8084 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
8085 u32 rx_mode, sort_mode;
8088 DBENTER(BCE_VERBOSE_MISC);
8090 BCE_LOCK_ASSERT(sc);
8094 /* Initialize receive mode default settings. */
8095 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
8096 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
8097 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
8100 * ASF/IPMI/UMP firmware requires that VLAN tag stripping
8103 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
8104 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)))
8105 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
8108 * Check for promiscuous, all multicast, or selected
8109 * multicast address filtering.
8111 if (ifp->if_flags & IFF_PROMISC) {
8112 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n");
8114 /* Enable promiscuous mode. */
8115 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
8116 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
8117 } else if (ifp->if_flags & IFF_ALLMULTI) {
8118 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n");
8120 /* Enable all multicast addresses. */
8121 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
8122 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
8125 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
8127 /* Accept one or more multicast(s). */
8128 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n");
8129 if_foreach_llmaddr(ifp, bce_hash_maddr, hashes);
8131 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++)
8132 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]);
8134 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
8137 /* Only make changes if the recive mode has actually changed. */
8138 if (rx_mode != sc->rx_mode) {
8139 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: "
8140 "0x%08X\n", rx_mode);
8142 sc->rx_mode = rx_mode;
8143 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
8146 /* Disable and clear the exisitng sort before enabling a new sort. */
8147 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
8148 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
8149 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
8151 DBEXIT(BCE_VERBOSE_MISC);
8155 /****************************************************************************/
8156 /* Called periodically to updates statistics from the controllers */
8157 /* statistics block. */
8161 /****************************************************************************/
8163 bce_stats_update(struct bce_softc *sc)
8165 struct statistics_block *stats;
8167 DBENTER(BCE_EXTREME_MISC);
8169 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD);
8171 stats = (struct statistics_block *) sc->stats_block;
8174 * Update the sysctl statistics from the
8175 * hardware statistics.
8177 sc->stat_IfHCInOctets =
8178 ((u64) stats->stat_IfHCInOctets_hi << 32) +
8179 (u64) stats->stat_IfHCInOctets_lo;
8181 sc->stat_IfHCInBadOctets =
8182 ((u64) stats->stat_IfHCInBadOctets_hi << 32) +
8183 (u64) stats->stat_IfHCInBadOctets_lo;
8185 sc->stat_IfHCOutOctets =
8186 ((u64) stats->stat_IfHCOutOctets_hi << 32) +
8187 (u64) stats->stat_IfHCOutOctets_lo;
8189 sc->stat_IfHCOutBadOctets =
8190 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) +
8191 (u64) stats->stat_IfHCOutBadOctets_lo;
8193 sc->stat_IfHCInUcastPkts =
8194 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) +
8195 (u64) stats->stat_IfHCInUcastPkts_lo;
8197 sc->stat_IfHCInMulticastPkts =
8198 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) +
8199 (u64) stats->stat_IfHCInMulticastPkts_lo;
8201 sc->stat_IfHCInBroadcastPkts =
8202 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) +
8203 (u64) stats->stat_IfHCInBroadcastPkts_lo;
8205 sc->stat_IfHCOutUcastPkts =
8206 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) +
8207 (u64) stats->stat_IfHCOutUcastPkts_lo;
8209 sc->stat_IfHCOutMulticastPkts =
8210 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) +
8211 (u64) stats->stat_IfHCOutMulticastPkts_lo;
8213 sc->stat_IfHCOutBroadcastPkts =
8214 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) +
8215 (u64) stats->stat_IfHCOutBroadcastPkts_lo;
8217 /* ToDo: Preserve counters beyond 32 bits? */
8218 /* ToDo: Read the statistics from auto-clear regs? */
8220 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
8221 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
8223 sc->stat_Dot3StatsCarrierSenseErrors =
8224 stats->stat_Dot3StatsCarrierSenseErrors;
8226 sc->stat_Dot3StatsFCSErrors =
8227 stats->stat_Dot3StatsFCSErrors;
8229 sc->stat_Dot3StatsAlignmentErrors =
8230 stats->stat_Dot3StatsAlignmentErrors;
8232 sc->stat_Dot3StatsSingleCollisionFrames =
8233 stats->stat_Dot3StatsSingleCollisionFrames;
8235 sc->stat_Dot3StatsMultipleCollisionFrames =
8236 stats->stat_Dot3StatsMultipleCollisionFrames;
8238 sc->stat_Dot3StatsDeferredTransmissions =
8239 stats->stat_Dot3StatsDeferredTransmissions;
8241 sc->stat_Dot3StatsExcessiveCollisions =
8242 stats->stat_Dot3StatsExcessiveCollisions;
8244 sc->stat_Dot3StatsLateCollisions =
8245 stats->stat_Dot3StatsLateCollisions;
8247 sc->stat_EtherStatsCollisions =
8248 stats->stat_EtherStatsCollisions;
8250 sc->stat_EtherStatsFragments =
8251 stats->stat_EtherStatsFragments;
8253 sc->stat_EtherStatsJabbers =
8254 stats->stat_EtherStatsJabbers;
8256 sc->stat_EtherStatsUndersizePkts =
8257 stats->stat_EtherStatsUndersizePkts;
8259 sc->stat_EtherStatsOversizePkts =
8260 stats->stat_EtherStatsOversizePkts;
8262 sc->stat_EtherStatsPktsRx64Octets =
8263 stats->stat_EtherStatsPktsRx64Octets;
8265 sc->stat_EtherStatsPktsRx65Octetsto127Octets =
8266 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
8268 sc->stat_EtherStatsPktsRx128Octetsto255Octets =
8269 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
8271 sc->stat_EtherStatsPktsRx256Octetsto511Octets =
8272 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
8274 sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
8275 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
8277 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
8278 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
8280 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
8281 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
8283 sc->stat_EtherStatsPktsTx64Octets =
8284 stats->stat_EtherStatsPktsTx64Octets;
8286 sc->stat_EtherStatsPktsTx65Octetsto127Octets =
8287 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
8289 sc->stat_EtherStatsPktsTx128Octetsto255Octets =
8290 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
8292 sc->stat_EtherStatsPktsTx256Octetsto511Octets =
8293 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
8295 sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
8296 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
8298 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
8299 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
8301 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
8302 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
8304 sc->stat_XonPauseFramesReceived =
8305 stats->stat_XonPauseFramesReceived;
8307 sc->stat_XoffPauseFramesReceived =
8308 stats->stat_XoffPauseFramesReceived;
8310 sc->stat_OutXonSent =
8311 stats->stat_OutXonSent;
8313 sc->stat_OutXoffSent =
8314 stats->stat_OutXoffSent;
8316 sc->stat_FlowControlDone =
8317 stats->stat_FlowControlDone;
8319 sc->stat_MacControlFramesReceived =
8320 stats->stat_MacControlFramesReceived;
8322 sc->stat_XoffStateEntered =
8323 stats->stat_XoffStateEntered;
8325 sc->stat_IfInFramesL2FilterDiscards =
8326 stats->stat_IfInFramesL2FilterDiscards;
8328 sc->stat_IfInRuleCheckerDiscards =
8329 stats->stat_IfInRuleCheckerDiscards;
8331 sc->stat_IfInFTQDiscards =
8332 stats->stat_IfInFTQDiscards;
8334 sc->stat_IfInMBUFDiscards =
8335 stats->stat_IfInMBUFDiscards;
8337 sc->stat_IfInRuleCheckerP4Hit =
8338 stats->stat_IfInRuleCheckerP4Hit;
8340 sc->stat_CatchupInRuleCheckerDiscards =
8341 stats->stat_CatchupInRuleCheckerDiscards;
8343 sc->stat_CatchupInFTQDiscards =
8344 stats->stat_CatchupInFTQDiscards;
8346 sc->stat_CatchupInMBUFDiscards =
8347 stats->stat_CatchupInMBUFDiscards;
8349 sc->stat_CatchupInRuleCheckerP4Hit =
8350 stats->stat_CatchupInRuleCheckerP4Hit;
8352 sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
8354 /* ToDo: Add additional statistics? */
8356 DBEXIT(BCE_EXTREME_MISC);
8360 bce_get_counter(struct ifnet *ifp, ift_counter cnt)
8362 struct bce_softc *sc;
8365 sc = if_getsoftc(ifp);
8368 case IFCOUNTER_COLLISIONS:
8369 return (sc->stat_EtherStatsCollisions);
8370 case IFCOUNTER_IERRORS:
8371 return (sc->stat_EtherStatsUndersizePkts +
8372 sc->stat_EtherStatsOversizePkts +
8373 sc->stat_IfInMBUFDiscards +
8374 sc->stat_Dot3StatsAlignmentErrors +
8375 sc->stat_Dot3StatsFCSErrors +
8376 sc->stat_IfInRuleCheckerDiscards +
8377 sc->stat_IfInFTQDiscards +
8378 sc->l2fhdr_error_count +
8379 sc->com_no_buffers);
8380 case IFCOUNTER_OERRORS:
8381 rv = sc->stat_Dot3StatsExcessiveCollisions +
8382 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
8383 sc->stat_Dot3StatsLateCollisions +
8384 sc->watchdog_timeouts;
8386 * Certain controllers don't report
8387 * carrier sense errors correctly.
8388 * See errata E11_5708CA0_1165.
8390 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
8391 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0))
8392 rv += sc->stat_Dot3StatsCarrierSenseErrors;
8395 return (if_get_counter_default(ifp, cnt));
8400 /****************************************************************************/
8401 /* Periodic function to notify the bootcode that the driver is still */
8406 /****************************************************************************/
8408 bce_pulse(void *xsc)
8410 struct bce_softc *sc = xsc;
8413 DBENTER(BCE_EXTREME_MISC);
8415 BCE_LOCK_ASSERT(sc);
8417 /* Tell the firmware that the driver is still running. */
8418 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq;
8419 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
8421 /* Update the bootcode condition. */
8422 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
8424 /* Report whether the bootcode still knows the driver is running. */
8425 if (bce_verbose || bootverbose) {
8426 if (sc->bce_drv_cardiac_arrest == FALSE) {
8427 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
8428 sc->bce_drv_cardiac_arrest = TRUE;
8429 BCE_PRINTF("%s(): Warning: bootcode "
8430 "thinks driver is absent! "
8431 "(bc_state = 0x%08X)\n",
8432 __FUNCTION__, sc->bc_state);
8436 * Not supported by all bootcode versions.
8437 * (v5.0.11+ and v5.2.1+) Older bootcode
8438 * will require the driver to reset the
8439 * controller to clear this condition.
8441 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
8442 sc->bce_drv_cardiac_arrest = FALSE;
8443 BCE_PRINTF("%s(): Bootcode found the "
8444 "driver pulse! (bc_state = 0x%08X)\n",
8445 __FUNCTION__, sc->bc_state);
8451 /* Schedule the next pulse. */
8452 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
8454 DBEXIT(BCE_EXTREME_MISC);
8458 /****************************************************************************/
8459 /* Periodic function to perform maintenance tasks. */
8463 /****************************************************************************/
8467 struct bce_softc *sc = xsc;
8468 struct mii_data *mii;
8470 struct ifmediareq ifmr;
8474 DBENTER(BCE_EXTREME_MISC);
8476 BCE_LOCK_ASSERT(sc);
8478 /* Schedule the next tick. */
8479 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
8481 /* Update the statistics from the hardware statistics block. */
8482 bce_stats_update(sc);
8484 /* Ensure page and RX chains get refilled in low-memory situations. */
8485 if (bce_hdr_split == TRUE)
8486 bce_fill_pg_chain(sc);
8487 bce_fill_rx_chain(sc);
8489 /* Check that chip hasn't hung. */
8492 /* If link is up already up then we're done. */
8493 if (sc->bce_link_up == TRUE)
8496 /* Link is down. Check what the PHY's doing. */
8497 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
8498 bzero(&ifmr, sizeof(ifmr));
8499 bce_ifmedia_sts_rphy(sc, &ifmr);
8500 if ((ifmr.ifm_status & (IFM_ACTIVE | IFM_AVALID)) ==
8501 (IFM_ACTIVE | IFM_AVALID)) {
8502 sc->bce_link_up = TRUE;
8503 bce_miibus_statchg(sc->bce_dev);
8506 mii = device_get_softc(sc->bce_miibus);
8508 /* Check if the link has come up. */
8509 if ((mii->mii_media_status & IFM_ACTIVE) &&
8510 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) {
8511 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n",
8513 sc->bce_link_up = TRUE;
8514 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
8515 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX ||
8516 IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) &&
8517 (bce_verbose || bootverbose))
8518 BCE_PRINTF("Gigabit link up!\n");
8522 if (sc->bce_link_up == TRUE) {
8523 /* Now that link is up, handle any outstanding TX traffic. */
8524 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
8525 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found "
8526 "pending TX traffic.\n", __FUNCTION__);
8527 bce_start_locked(ifp);
8532 DBEXIT(BCE_EXTREME_MISC);
8536 bce_fw_cap_init(struct bce_softc *sc)
8541 cap = bce_shmem_rd(sc, BCE_FW_CAP_MB);
8542 if ((cap & BCE_FW_CAP_SIGNATURE_MAGIC_MASK) !=
8543 BCE_FW_CAP_SIGNATURE_MAGIC)
8545 if ((cap & (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) ==
8546 (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN))
8547 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC |
8548 BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN;
8549 if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 &&
8550 (cap & BCE_FW_CAP_REMOTE_PHY_CAP) != 0) {
8551 sc->bce_phy_flags &= ~BCE_PHY_REMOTE_PORT_FIBER_FLAG;
8552 sc->bce_phy_flags |= BCE_PHY_REMOTE_CAP_FLAG;
8553 link = bce_shmem_rd(sc, BCE_LINK_STATUS);
8554 if ((link & BCE_LINK_STATUS_SERDES_LINK) != 0)
8555 sc->bce_phy_flags |= BCE_PHY_REMOTE_PORT_FIBER_FLAG;
8556 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC |
8557 BCE_FW_CAP_REMOTE_PHY_CAP;
8561 bce_shmem_wr(sc, BCE_DRV_ACK_CAP_MB, ack);
8566 /****************************************************************************/
8567 /* Allows the driver state to be dumped through the sysctl interface. */
8570 /* 0 for success, positive value for failure. */
8571 /****************************************************************************/
8573 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
8577 struct bce_softc *sc;
8580 error = sysctl_handle_int(oidp, &result, 0, req);
8582 if (error || !req->newptr)
8586 sc = (struct bce_softc *)arg1;
8587 bce_dump_driver_state(sc);
8594 /****************************************************************************/
8595 /* Allows the hardware state to be dumped through the sysctl interface. */
8598 /* 0 for success, positive value for failure. */
8599 /****************************************************************************/
8601 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
8605 struct bce_softc *sc;
8608 error = sysctl_handle_int(oidp, &result, 0, req);
8610 if (error || !req->newptr)
8614 sc = (struct bce_softc *)arg1;
8615 bce_dump_hw_state(sc);
8622 /****************************************************************************/
8623 /* Allows the status block to be dumped through the sysctl interface. */
8626 /* 0 for success, positive value for failure. */
8627 /****************************************************************************/
8629 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS)
8633 struct bce_softc *sc;
8636 error = sysctl_handle_int(oidp, &result, 0, req);
8638 if (error || !req->newptr)
8642 sc = (struct bce_softc *)arg1;
8643 bce_dump_status_block(sc);
8650 /****************************************************************************/
8651 /* Allows the stats block to be dumped through the sysctl interface. */
8654 /* 0 for success, positive value for failure. */
8655 /****************************************************************************/
8657 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS)
8661 struct bce_softc *sc;
8664 error = sysctl_handle_int(oidp, &result, 0, req);
8666 if (error || !req->newptr)
8670 sc = (struct bce_softc *)arg1;
8671 bce_dump_stats_block(sc);
8678 /****************************************************************************/
8679 /* Allows the stat counters to be cleared without unloading/reloading the */
8683 /* 0 for success, positive value for failure. */
8684 /****************************************************************************/
8686 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS)
8690 struct bce_softc *sc;
8693 error = sysctl_handle_int(oidp, &result, 0, req);
8695 if (error || !req->newptr)
8699 sc = (struct bce_softc *)arg1;
8700 struct statistics_block *stats;
8702 stats = (struct statistics_block *) sc->stats_block;
8703 bzero(stats, sizeof(struct statistics_block));
8704 bus_dmamap_sync(sc->stats_tag, sc->stats_map,
8705 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
8707 /* Clear the internal H/W statistics counters. */
8708 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
8710 /* Reset the driver maintained statistics. */
8712 sc->interrupts_tx = 0;
8713 sc->tso_frames_requested =
8714 sc->tso_frames_completed =
8715 sc->tso_frames_failed = 0;
8716 sc->rx_empty_count =
8717 sc->tx_full_count = 0;
8718 sc->rx_low_watermark = USABLE_RX_BD_ALLOC;
8719 sc->tx_hi_watermark = 0;
8720 sc->l2fhdr_error_count =
8721 sc->l2fhdr_error_sim_count = 0;
8722 sc->mbuf_alloc_failed_count =
8723 sc->mbuf_alloc_failed_sim_count = 0;
8724 sc->dma_map_addr_rx_failed_count =
8725 sc->dma_map_addr_tx_failed_count = 0;
8726 sc->mbuf_frag_count = 0;
8727 sc->csum_offload_tcp_udp =
8728 sc->csum_offload_ip = 0;
8729 sc->vlan_tagged_frames_rcvd =
8730 sc->vlan_tagged_frames_stripped = 0;
8731 sc->split_header_frames_rcvd =
8732 sc->split_header_tcp_frames_rcvd = 0;
8734 /* Clear firmware maintained statistics. */
8735 REG_WR_IND(sc, 0x120084, 0);
8742 /****************************************************************************/
8743 /* Allows the shared memory contents to be dumped through the sysctl . */
8747 /* 0 for success, positive value for failure. */
8748 /****************************************************************************/
8750 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS)
8754 struct bce_softc *sc;
8757 error = sysctl_handle_int(oidp, &result, 0, req);
8759 if (error || !req->newptr)
8763 sc = (struct bce_softc *)arg1;
8764 bce_dump_shmem_state(sc);
8771 /****************************************************************************/
8772 /* Allows the bootcode state to be dumped through the sysctl interface. */
8775 /* 0 for success, positive value for failure. */
8776 /****************************************************************************/
8778 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS)
8782 struct bce_softc *sc;
8785 error = sysctl_handle_int(oidp, &result, 0, req);
8787 if (error || !req->newptr)
8791 sc = (struct bce_softc *)arg1;
8792 bce_dump_bc_state(sc);
8799 /****************************************************************************/
8800 /* Provides a sysctl interface to allow dumping the RX BD chain. */
8803 /* 0 for success, positive value for failure. */
8804 /****************************************************************************/
8806 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS)
8810 struct bce_softc *sc;
8813 error = sysctl_handle_int(oidp, &result, 0, req);
8815 if (error || !req->newptr)
8819 sc = (struct bce_softc *)arg1;
8820 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC);
8827 /****************************************************************************/
8828 /* Provides a sysctl interface to allow dumping the RX MBUF chain. */
8831 /* 0 for success, positive value for failure. */
8832 /****************************************************************************/
8834 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS)
8838 struct bce_softc *sc;
8841 error = sysctl_handle_int(oidp, &result, 0, req);
8843 if (error || !req->newptr)
8847 sc = (struct bce_softc *)arg1;
8848 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC);
8855 /****************************************************************************/
8856 /* Provides a sysctl interface to allow dumping the TX chain. */
8859 /* 0 for success, positive value for failure. */
8860 /****************************************************************************/
8862 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
8866 struct bce_softc *sc;
8869 error = sysctl_handle_int(oidp, &result, 0, req);
8871 if (error || !req->newptr)
8875 sc = (struct bce_softc *)arg1;
8876 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC);
8883 /****************************************************************************/
8884 /* Provides a sysctl interface to allow dumping the page chain. */
8887 /* 0 for success, positive value for failure. */
8888 /****************************************************************************/
8890 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS)
8894 struct bce_softc *sc;
8897 error = sysctl_handle_int(oidp, &result, 0, req);
8899 if (error || !req->newptr)
8903 sc = (struct bce_softc *)arg1;
8904 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC);
8910 /****************************************************************************/
8911 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */
8912 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
8915 /* 0 for success, positive value for failure. */
8916 /****************************************************************************/
8918 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS)
8920 struct bce_softc *sc = (struct bce_softc *)arg1;
8924 u8 *data = (u8 *) val;
8927 error = sysctl_handle_int(oidp, &result, 0, req);
8928 if (error || (req->newptr == NULL))
8931 error = bce_nvram_read(sc, result, data, 4);
8933 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0]));
8939 /****************************************************************************/
8940 /* Provides a sysctl interface to allow reading arbitrary registers in the */
8941 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
8944 /* 0 for success, positive value for failure. */
8945 /****************************************************************************/
8947 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
8949 struct bce_softc *sc = (struct bce_softc *)arg1;
8954 error = sysctl_handle_int(oidp, &result, 0, req);
8955 if (error || (req->newptr == NULL))
8958 /* Make sure the register is accessible. */
8959 if (result < 0x8000) {
8960 val = REG_RD(sc, result);
8961 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8962 } else if (result < 0x0280000) {
8963 val = REG_RD_IND(sc, result);
8964 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8971 /****************************************************************************/
8972 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */
8973 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
8976 /* 0 for success, positive value for failure. */
8977 /****************************************************************************/
8979 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
8981 struct bce_softc *sc;
8987 error = sysctl_handle_int(oidp, &result, 0, req);
8988 if (error || (req->newptr == NULL))
8991 /* Make sure the register is accessible. */
8992 if (result < 0x20) {
8993 sc = (struct bce_softc *)arg1;
8995 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
8996 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val);
9002 /****************************************************************************/
9003 /* Provides a sysctl interface for dumping the nvram contents. */
9004 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */
9007 /* 0 for success, positive errno for failure. */
9008 /****************************************************************************/
9010 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS)
9012 struct bce_softc *sc = (struct bce_softc *)arg1;
9015 if (sc->nvram_buf == NULL)
9016 sc->nvram_buf = malloc(sc->bce_flash_size,
9017 M_TEMP, M_ZERO | M_WAITOK);
9020 if (req->oldlen == sc->bce_flash_size) {
9021 for (i = 0; i < sc->bce_flash_size && error == 0; i++)
9022 error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1);
9026 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size);
9031 #ifdef BCE_NVRAM_WRITE_SUPPORT
9032 /****************************************************************************/
9033 /* Provides a sysctl interface for writing to nvram. */
9034 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */
9037 /* 0 for success, positive errno for failure. */
9038 /****************************************************************************/
9040 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS)
9042 struct bce_softc *sc = (struct bce_softc *)arg1;
9045 if (sc->nvram_buf == NULL)
9046 sc->nvram_buf = malloc(sc->bce_flash_size,
9047 M_TEMP, M_ZERO | M_WAITOK);
9049 bzero(sc->nvram_buf, sc->bce_flash_size);
9051 error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size);
9055 if (req->newlen == sc->bce_flash_size)
9056 error = bce_nvram_write(sc, 0, sc->nvram_buf,
9057 sc->bce_flash_size);
9065 /****************************************************************************/
9066 /* Provides a sysctl interface to allow reading a CID. */
9069 /* 0 for success, positive value for failure. */
9070 /****************************************************************************/
9072 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS)
9074 struct bce_softc *sc;
9078 error = sysctl_handle_int(oidp, &result, 0, req);
9079 if (error || (req->newptr == NULL))
9082 /* Make sure the register is accessible. */
9083 if (result <= TX_CID) {
9084 sc = (struct bce_softc *)arg1;
9085 bce_dump_ctx(sc, result);
9092 /****************************************************************************/
9093 /* Provides a sysctl interface to forcing the driver to dump state and */
9094 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
9097 /* 0 for success, positive value for failure. */
9098 /****************************************************************************/
9100 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
9104 struct bce_softc *sc;
9107 error = sysctl_handle_int(oidp, &result, 0, req);
9109 if (error || !req->newptr)
9113 sc = (struct bce_softc *)arg1;
9121 /****************************************************************************/
9122 /* Adds any sysctl parameters for tuning or debugging purposes. */
9125 /* 0 for success, positive value for failure. */
9126 /****************************************************************************/
9128 bce_add_sysctls(struct bce_softc *sc)
9130 struct sysctl_ctx_list *ctx;
9131 struct sysctl_oid_list *children;
9133 DBENTER(BCE_VERBOSE_MISC);
9135 ctx = device_get_sysctl_ctx(sc->bce_dev);
9136 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev));
9139 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9140 "l2fhdr_error_sim_control",
9141 CTLFLAG_RW, &l2fhdr_error_sim_control,
9142 0, "Debug control to force l2fhdr errors");
9144 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9145 "l2fhdr_error_sim_count",
9146 CTLFLAG_RD, &sc->l2fhdr_error_sim_count,
9147 0, "Number of simulated l2_fhdr errors");
9150 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9151 "l2fhdr_error_count",
9152 CTLFLAG_RD, &sc->l2fhdr_error_count,
9153 0, "Number of l2_fhdr errors");
9156 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9157 "mbuf_alloc_failed_sim_control",
9158 CTLFLAG_RW, &mbuf_alloc_failed_sim_control,
9159 0, "Debug control to force mbuf allocation failures");
9161 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9162 "mbuf_alloc_failed_sim_count",
9163 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count,
9164 0, "Number of simulated mbuf cluster allocation failures");
9167 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9168 "mbuf_alloc_failed_count",
9169 CTLFLAG_RD, &sc->mbuf_alloc_failed_count,
9170 0, "Number of mbuf allocation failures");
9172 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9174 CTLFLAG_RD, &sc->mbuf_frag_count,
9175 0, "Number of fragmented mbufs");
9178 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9179 "dma_map_addr_failed_sim_control",
9180 CTLFLAG_RW, &dma_map_addr_failed_sim_control,
9181 0, "Debug control to force DMA mapping failures");
9183 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */
9184 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9185 "dma_map_addr_failed_sim_count",
9186 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count,
9187 0, "Number of simulated DMA mapping failures");
9191 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9192 "dma_map_addr_rx_failed_count",
9193 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count,
9194 0, "Number of RX DMA mapping failures");
9196 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9197 "dma_map_addr_tx_failed_count",
9198 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count,
9199 0, "Number of TX DMA mapping failures");
9202 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9203 "unexpected_attention_sim_control",
9204 CTLFLAG_RW, &unexpected_attention_sim_control,
9205 0, "Debug control to simulate unexpected attentions");
9207 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9208 "unexpected_attention_sim_count",
9209 CTLFLAG_RW, &sc->unexpected_attention_sim_count,
9210 0, "Number of simulated unexpected attentions");
9213 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9214 "unexpected_attention_count",
9215 CTLFLAG_RW, &sc->unexpected_attention_count,
9216 0, "Number of unexpected attentions");
9219 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9220 "debug_bootcode_running_failure",
9221 CTLFLAG_RW, &bootcode_running_failure_sim_control,
9222 0, "Debug control to force bootcode running failures");
9224 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9226 CTLFLAG_RD, &sc->rx_low_watermark,
9227 0, "Lowest level of free rx_bd's");
9229 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9231 CTLFLAG_RD, &sc->rx_empty_count,
9232 "Number of times the RX chain was empty");
9234 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9236 CTLFLAG_RD, &sc->tx_hi_watermark,
9237 0, "Highest level of used tx_bd's");
9239 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9241 CTLFLAG_RD, &sc->tx_full_count,
9242 "Number of times the TX chain was full");
9244 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9245 "tso_frames_requested",
9246 CTLFLAG_RD, &sc->tso_frames_requested,
9247 "Number of TSO frames requested");
9249 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9250 "tso_frames_completed",
9251 CTLFLAG_RD, &sc->tso_frames_completed,
9252 "Number of TSO frames completed");
9254 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9255 "tso_frames_failed",
9256 CTLFLAG_RD, &sc->tso_frames_failed,
9257 "Number of TSO frames failed");
9259 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9261 CTLFLAG_RD, &sc->csum_offload_ip,
9262 "Number of IP checksum offload frames");
9264 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9265 "csum_offload_tcp_udp",
9266 CTLFLAG_RD, &sc->csum_offload_tcp_udp,
9267 "Number of TCP/UDP checksum offload frames");
9269 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9270 "vlan_tagged_frames_rcvd",
9271 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd,
9272 "Number of VLAN tagged frames received");
9274 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9275 "vlan_tagged_frames_stripped",
9276 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped,
9277 "Number of VLAN tagged frames stripped");
9279 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9281 CTLFLAG_RD, &sc->interrupts_rx,
9282 "Number of RX interrupts");
9284 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9286 CTLFLAG_RD, &sc->interrupts_tx,
9287 "Number of TX interrupts");
9289 if (bce_hdr_split == TRUE) {
9290 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9291 "split_header_frames_rcvd",
9292 CTLFLAG_RD, &sc->split_header_frames_rcvd,
9293 "Number of split header frames received");
9295 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9296 "split_header_tcp_frames_rcvd",
9297 CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd,
9298 "Number of split header TCP frames received");
9301 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9302 "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD,
9304 bce_sysctl_nvram_dump, "S", "");
9306 #ifdef BCE_NVRAM_WRITE_SUPPORT
9307 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9308 "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR,
9310 bce_sysctl_nvram_write, "S", "");
9312 #endif /* BCE_DEBUG */
9314 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9315 "stat_IfHcInOctets",
9316 CTLFLAG_RD, &sc->stat_IfHCInOctets,
9319 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9320 "stat_IfHCInBadOctets",
9321 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
9322 "Bad bytes received");
9324 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9325 "stat_IfHCOutOctets",
9326 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
9329 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9330 "stat_IfHCOutBadOctets",
9331 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
9334 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9335 "stat_IfHCInUcastPkts",
9336 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
9337 "Unicast packets received");
9339 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9340 "stat_IfHCInMulticastPkts",
9341 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
9342 "Multicast packets received");
9344 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9345 "stat_IfHCInBroadcastPkts",
9346 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
9347 "Broadcast packets received");
9349 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9350 "stat_IfHCOutUcastPkts",
9351 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
9352 "Unicast packets sent");
9354 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9355 "stat_IfHCOutMulticastPkts",
9356 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
9357 "Multicast packets sent");
9359 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9360 "stat_IfHCOutBroadcastPkts",
9361 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
9362 "Broadcast packets sent");
9364 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9365 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
9366 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
9367 0, "Internal MAC transmit errors");
9369 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9370 "stat_Dot3StatsCarrierSenseErrors",
9371 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
9372 0, "Carrier sense errors");
9374 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9375 "stat_Dot3StatsFCSErrors",
9376 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
9377 0, "Frame check sequence errors");
9379 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9380 "stat_Dot3StatsAlignmentErrors",
9381 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
9382 0, "Alignment errors");
9384 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9385 "stat_Dot3StatsSingleCollisionFrames",
9386 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
9387 0, "Single Collision Frames");
9389 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9390 "stat_Dot3StatsMultipleCollisionFrames",
9391 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
9392 0, "Multiple Collision Frames");
9394 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9395 "stat_Dot3StatsDeferredTransmissions",
9396 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
9397 0, "Deferred Transmissions");
9399 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9400 "stat_Dot3StatsExcessiveCollisions",
9401 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
9402 0, "Excessive Collisions");
9404 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9405 "stat_Dot3StatsLateCollisions",
9406 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
9407 0, "Late Collisions");
9409 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9410 "stat_EtherStatsCollisions",
9411 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
9414 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9415 "stat_EtherStatsFragments",
9416 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
9419 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9420 "stat_EtherStatsJabbers",
9421 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
9424 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9425 "stat_EtherStatsUndersizePkts",
9426 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
9427 0, "Undersize packets");
9429 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9430 "stat_EtherStatsOversizePkts",
9431 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts,
9432 0, "stat_EtherStatsOversizePkts");
9434 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9435 "stat_EtherStatsPktsRx64Octets",
9436 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
9437 0, "Bytes received in 64 byte packets");
9439 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9440 "stat_EtherStatsPktsRx65Octetsto127Octets",
9441 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
9442 0, "Bytes received in 65 to 127 byte packets");
9444 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9445 "stat_EtherStatsPktsRx128Octetsto255Octets",
9446 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
9447 0, "Bytes received in 128 to 255 byte packets");
9449 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9450 "stat_EtherStatsPktsRx256Octetsto511Octets",
9451 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
9452 0, "Bytes received in 256 to 511 byte packets");
9454 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9455 "stat_EtherStatsPktsRx512Octetsto1023Octets",
9456 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
9457 0, "Bytes received in 512 to 1023 byte packets");
9459 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9460 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
9461 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
9462 0, "Bytes received in 1024 t0 1522 byte packets");
9464 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9465 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
9466 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
9467 0, "Bytes received in 1523 to 9022 byte packets");
9469 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9470 "stat_EtherStatsPktsTx64Octets",
9471 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
9472 0, "Bytes sent in 64 byte packets");
9474 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9475 "stat_EtherStatsPktsTx65Octetsto127Octets",
9476 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
9477 0, "Bytes sent in 65 to 127 byte packets");
9479 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9480 "stat_EtherStatsPktsTx128Octetsto255Octets",
9481 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
9482 0, "Bytes sent in 128 to 255 byte packets");
9484 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9485 "stat_EtherStatsPktsTx256Octetsto511Octets",
9486 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
9487 0, "Bytes sent in 256 to 511 byte packets");
9489 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9490 "stat_EtherStatsPktsTx512Octetsto1023Octets",
9491 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
9492 0, "Bytes sent in 512 to 1023 byte packets");
9494 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9495 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
9496 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
9497 0, "Bytes sent in 1024 to 1522 byte packets");
9499 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9500 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
9501 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
9502 0, "Bytes sent in 1523 to 9022 byte packets");
9504 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9505 "stat_XonPauseFramesReceived",
9506 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
9507 0, "XON pause frames receved");
9509 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9510 "stat_XoffPauseFramesReceived",
9511 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
9512 0, "XOFF pause frames received");
9514 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9516 CTLFLAG_RD, &sc->stat_OutXonSent,
9517 0, "XON pause frames sent");
9519 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9521 CTLFLAG_RD, &sc->stat_OutXoffSent,
9522 0, "XOFF pause frames sent");
9524 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9525 "stat_FlowControlDone",
9526 CTLFLAG_RD, &sc->stat_FlowControlDone,
9527 0, "Flow control done");
9529 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9530 "stat_MacControlFramesReceived",
9531 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
9532 0, "MAC control frames received");
9534 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9535 "stat_XoffStateEntered",
9536 CTLFLAG_RD, &sc->stat_XoffStateEntered,
9537 0, "XOFF state entered");
9539 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9540 "stat_IfInFramesL2FilterDiscards",
9541 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
9542 0, "Received L2 packets discarded");
9544 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9545 "stat_IfInRuleCheckerDiscards",
9546 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
9547 0, "Received packets discarded by rule");
9549 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9550 "stat_IfInFTQDiscards",
9551 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
9552 0, "Received packet FTQ discards");
9554 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9555 "stat_IfInMBUFDiscards",
9556 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
9557 0, "Received packets discarded due to lack "
9558 "of controller buffer memory");
9560 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9561 "stat_IfInRuleCheckerP4Hit",
9562 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
9563 0, "Received packets rule checker hits");
9565 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9566 "stat_CatchupInRuleCheckerDiscards",
9567 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
9568 0, "Received packets discarded in Catchup path");
9570 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9571 "stat_CatchupInFTQDiscards",
9572 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
9573 0, "Received packets discarded in FTQ in Catchup path");
9575 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9576 "stat_CatchupInMBUFDiscards",
9577 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
9578 0, "Received packets discarded in controller "
9579 "buffer memory in Catchup path");
9581 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9582 "stat_CatchupInRuleCheckerP4Hit",
9583 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
9584 0, "Received packets rule checker hits in Catchup path");
9586 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9588 CTLFLAG_RD, &sc->com_no_buffers,
9589 0, "Valid packets received but no RX buffers available");
9592 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9593 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
9595 bce_sysctl_driver_state, "I", "Drive state information");
9597 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9598 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
9600 bce_sysctl_hw_state, "I", "Hardware state information");
9602 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9603 "status_block", CTLTYPE_INT | CTLFLAG_RW,
9605 bce_sysctl_status_block, "I", "Dump status block");
9607 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9608 "stats_block", CTLTYPE_INT | CTLFLAG_RW,
9610 bce_sysctl_stats_block, "I", "Dump statistics block");
9612 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9613 "stats_clear", CTLTYPE_INT | CTLFLAG_RW,
9615 bce_sysctl_stats_clear, "I", "Clear statistics block");
9617 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9618 "shmem_state", CTLTYPE_INT | CTLFLAG_RW,
9620 bce_sysctl_shmem_state, "I", "Shared memory state information");
9622 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9623 "bc_state", CTLTYPE_INT | CTLFLAG_RW,
9625 bce_sysctl_bc_state, "I", "Bootcode state information");
9627 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9628 "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW,
9630 bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain");
9632 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9633 "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW,
9635 bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain");
9637 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9638 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
9640 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
9642 if (bce_hdr_split == TRUE) {
9643 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9644 "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW,
9646 bce_sysctl_dump_pg_chain, "I", "Dump page chain");
9649 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9650 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW,
9652 bce_sysctl_dump_ctx, "I", "Dump context memory");
9654 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9655 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
9657 bce_sysctl_breakpoint, "I", "Driver breakpoint");
9659 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9660 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
9662 bce_sysctl_reg_read, "I", "Register read");
9664 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9665 "nvram_read", CTLTYPE_INT | CTLFLAG_RW,
9667 bce_sysctl_nvram_read, "I", "NVRAM read");
9669 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9670 "phy_read", CTLTYPE_INT | CTLFLAG_RW,
9672 bce_sysctl_phy_read, "I", "PHY register read");
9676 DBEXIT(BCE_VERBOSE_MISC);
9680 /****************************************************************************/
9681 /* BCE Debug Routines */
9682 /****************************************************************************/
9685 /****************************************************************************/
9686 /* Freezes the controller to allow for a cohesive state dump. */
9690 /****************************************************************************/
9691 static __attribute__ ((noinline)) void
9692 bce_freeze_controller(struct bce_softc *sc)
9695 val = REG_RD(sc, BCE_MISC_COMMAND);
9696 val |= BCE_MISC_COMMAND_DISABLE_ALL;
9697 REG_WR(sc, BCE_MISC_COMMAND, val);
9701 /****************************************************************************/
9702 /* Unfreezes the controller after a freeze operation. This may not always */
9703 /* work and the controller will require a reset! */
9707 /****************************************************************************/
9708 static __attribute__ ((noinline)) void
9709 bce_unfreeze_controller(struct bce_softc *sc)
9712 val = REG_RD(sc, BCE_MISC_COMMAND);
9713 val |= BCE_MISC_COMMAND_ENABLE_ALL;
9714 REG_WR(sc, BCE_MISC_COMMAND, val);
9718 /****************************************************************************/
9719 /* Prints out Ethernet frame information from an mbuf. */
9721 /* Partially decode an Ethernet frame to look at some important headers. */
9725 /****************************************************************************/
9726 static __attribute__ ((noinline)) void
9727 bce_dump_enet(struct bce_softc *sc, struct mbuf *m)
9729 struct ether_vlan_header *eh;
9738 "-----------------------------"
9740 "-----------------------------\n");
9742 eh = mtod(m, struct ether_vlan_header *);
9744 /* Handle VLAN encapsulation if present. */
9745 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
9746 etype = ntohs(eh->evl_proto);
9747 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
9749 etype = ntohs(eh->evl_encap_proto);
9750 ehlen = ETHER_HDR_LEN;
9753 /* ToDo: Add VLAN output. */
9754 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n",
9755 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen);
9759 ip = (struct ip *)(m->m_data + ehlen);
9760 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, "
9761 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n",
9762 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr),
9763 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum));
9767 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9768 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = "
9769 "%d bytes, flags = 0x%b, csum = 0x%04X\n",
9770 ntohs(th->th_dport), ntohs(th->th_sport),
9771 (th->th_off << 2), th->th_flags,
9772 "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST"
9773 "\02SYN\01FIN", ntohs(th->th_sum));
9776 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9777 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d "
9778 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport),
9779 ntohs(uh->uh_sport), ntohs(uh->uh_ulen),
9783 BCE_PRINTF("icmp:\n");
9786 BCE_PRINTF("----: Other IP protocol.\n");
9789 case ETHERTYPE_IPV6:
9790 BCE_PRINTF("ipv6: No decode supported.\n");
9793 BCE_PRINTF("-arp: ");
9794 ah = (struct arphdr *) (m->m_data + ehlen);
9795 switch (ntohs(ah->ar_op)) {
9796 case ARPOP_REVREQUEST:
9797 printf("reverse ARP request\n");
9799 case ARPOP_REVREPLY:
9800 printf("reverse ARP reply\n");
9803 printf("ARP request\n");
9806 printf("ARP reply\n");
9809 printf("other ARP operation\n");
9813 BCE_PRINTF("----: Other protocol.\n");
9817 "-----------------------------"
9819 "-----------------------------\n");
9823 /****************************************************************************/
9824 /* Prints out information about an mbuf. */
9828 /****************************************************************************/
9829 static __attribute__ ((noinline)) void
9830 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
9832 struct mbuf *mp = m;
9835 BCE_PRINTF("mbuf: null pointer\n");
9840 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, "
9841 "m_data = %p\n", mp, mp->m_len, mp->m_flags,
9842 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data);
9844 if (mp->m_flags & M_PKTHDR) {
9845 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, "
9846 "csum_flags = %b\n", mp->m_pkthdr.len,
9847 mp->m_flags, M_FLAG_PRINTF,
9848 mp->m_pkthdr.csum_flags, CSUM_BITS);
9851 if (mp->m_flags & M_EXT) {
9852 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ",
9853 mp->m_ext.ext_buf, mp->m_ext.ext_size);
9854 switch (mp->m_ext.ext_type) {
9856 printf("EXT_CLUSTER\n"); break;
9858 printf("EXT_SFBUF\n"); break;
9860 printf("EXT_JUMBO9\n"); break;
9862 printf("EXT_JUMBO16\n"); break;
9864 printf("EXT_PACKET\n"); break;
9866 printf("EXT_MBUF\n"); break;
9868 printf("EXT_NET_DRV\n"); break;
9870 printf("EXT_MDD_TYPE\n"); break;
9871 case EXT_DISPOSABLE:
9872 printf("EXT_DISPOSABLE\n"); break;
9874 printf("EXT_EXTREF\n"); break;
9876 printf("UNKNOWN\n");
9885 /****************************************************************************/
9886 /* Prints out the mbufs in the TX mbuf chain. */
9890 /****************************************************************************/
9891 static __attribute__ ((noinline)) void
9892 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9897 "----------------------------"
9899 "----------------------------\n");
9901 for (int i = 0; i < count; i++) {
9902 m = sc->tx_mbuf_ptr[chain_prod];
9903 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod);
9904 bce_dump_mbuf(sc, m);
9905 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
9909 "----------------------------"
9911 "----------------------------\n");
9915 /****************************************************************************/
9916 /* Prints out the mbufs in the RX mbuf chain. */
9920 /****************************************************************************/
9921 static __attribute__ ((noinline)) void
9922 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9927 "----------------------------"
9929 "----------------------------\n");
9931 for (int i = 0; i < count; i++) {
9932 m = sc->rx_mbuf_ptr[chain_prod];
9933 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod);
9934 bce_dump_mbuf(sc, m);
9935 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
9940 "----------------------------"
9942 "----------------------------\n");
9946 /****************************************************************************/
9947 /* Prints out the mbufs in the mbuf page chain. */
9951 /****************************************************************************/
9952 static __attribute__ ((noinline)) void
9953 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9958 "----------------------------"
9960 "----------------------------\n");
9962 for (int i = 0; i < count; i++) {
9963 m = sc->pg_mbuf_ptr[chain_prod];
9964 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod);
9965 bce_dump_mbuf(sc, m);
9966 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod));
9971 "----------------------------"
9973 "----------------------------\n");
9977 /****************************************************************************/
9978 /* Prints out a tx_bd structure. */
9982 /****************************************************************************/
9983 static __attribute__ ((noinline)) void
9984 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
9988 if (idx > MAX_TX_BD_ALLOC)
9989 /* Index out of range. */
9990 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
9991 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
9992 /* TX Chain page pointer. */
9993 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
9994 "pointer\n", idx, txbd->tx_bd_haddr_hi,
9995 txbd->tx_bd_haddr_lo);
9997 /* Normal tx_bd entry. */
9998 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
9999 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = "
10000 "0x%04X (", idx, txbd->tx_bd_haddr_hi,
10001 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes,
10002 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
10004 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) {
10007 printf("CONN_FAULT");
10011 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) {
10014 printf("TCP_UDP_CKSUM");
10018 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) {
10021 printf("IP_CKSUM");
10025 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) {
10032 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) {
10035 printf("COAL_NOW");
10039 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) {
10042 printf("DONT_GEN_CRC");
10046 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) {
10053 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) {
10060 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) {
10067 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) {
10070 printf("SW_OPTION=%d", ((txbd->tx_bd_flags &
10071 TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++;
10074 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) {
10077 printf("SW_FLAGS");
10081 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) {
10092 /****************************************************************************/
10093 /* Prints out a rx_bd structure. */
10097 /****************************************************************************/
10098 static __attribute__ ((noinline)) void
10099 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
10101 if (idx > MAX_RX_BD_ALLOC)
10102 /* Index out of range. */
10103 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
10104 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
10105 /* RX Chain page pointer. */
10106 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
10107 "pointer\n", idx, rxbd->rx_bd_haddr_hi,
10108 rxbd->rx_bd_haddr_lo);
10110 /* Normal rx_bd entry. */
10111 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = "
10112 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi,
10113 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len,
10114 rxbd->rx_bd_flags);
10118 /****************************************************************************/
10119 /* Prints out a rx_bd structure in the page chain. */
10123 /****************************************************************************/
10124 static __attribute__ ((noinline)) void
10125 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd)
10127 if (idx > MAX_PG_BD_ALLOC)
10128 /* Index out of range. */
10129 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx);
10130 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE)
10131 /* Page Chain page pointer. */
10132 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n",
10133 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo);
10135 /* Normal rx_bd entry. */
10136 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, "
10137 "flags = 0x%08X\n", idx,
10138 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo,
10139 pgbd->rx_bd_len, pgbd->rx_bd_flags);
10143 /****************************************************************************/
10144 /* Prints out a l2_fhdr structure. */
10148 /****************************************************************************/
10149 static __attribute__ ((noinline)) void
10150 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
10152 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, "
10153 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, "
10154 "tcp_udp_xsum = 0x%04X\n", idx,
10155 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB,
10156 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
10157 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
10161 /****************************************************************************/
10162 /* Prints out context memory info. (Only useful for CID 0 to 16.) */
10166 /****************************************************************************/
10167 static __attribute__ ((noinline)) void
10168 bce_dump_ctx(struct bce_softc *sc, u16 cid)
10170 if (cid > TX_CID) {
10171 BCE_PRINTF(" Unknown CID\n");
10176 "----------------------------"
10178 "----------------------------\n");
10180 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid);
10182 if (cid == RX_CID) {
10183 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx "
10184 "producer index\n",
10185 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX));
10186 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host "
10187 "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
10188 BCE_L2CTX_RX_HOST_BSEQ));
10189 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n",
10190 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ));
10191 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer "
10192 "descriptor address\n",
10193 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI));
10194 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer "
10195 "descriptor address\n",
10196 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO));
10197 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer "
10198 "index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10199 BCE_L2CTX_RX_NX_BDIDX));
10200 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page "
10201 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10202 BCE_L2CTX_RX_HOST_PG_BDIDX));
10203 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page "
10204 "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid),
10205 BCE_L2CTX_RX_PG_BUF_SIZE));
10206 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page "
10207 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
10208 BCE_L2CTX_RX_NX_PG_BDHADDR_HI));
10209 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page "
10210 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
10211 BCE_L2CTX_RX_NX_PG_BDHADDR_LO));
10212 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page "
10213 "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10214 BCE_L2CTX_RX_NX_PG_BDIDX));
10215 } else if (cid == TX_CID) {
10216 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
10217 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n",
10218 CTX_RD(sc, GET_CID_ADDR(cid),
10219 BCE_L2CTX_TX_TYPE_XI));
10220 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx "
10221 "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid),
10222 BCE_L2CTX_TX_CMD_TYPE_XI));
10223 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) "
10224 "h/w buffer descriptor address\n",
10225 CTX_RD(sc, GET_CID_ADDR(cid),
10226 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI));
10227 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) "
10228 "h/w buffer descriptor address\n",
10229 CTX_RD(sc, GET_CID_ADDR(cid),
10230 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI));
10231 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) "
10232 "host producer index\n",
10233 CTX_RD(sc, GET_CID_ADDR(cid),
10234 BCE_L2CTX_TX_HOST_BIDX_XI));
10235 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) "
10236 "host byte sequence\n",
10237 CTX_RD(sc, GET_CID_ADDR(cid),
10238 BCE_L2CTX_TX_HOST_BSEQ_XI));
10240 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n",
10241 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE));
10242 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n",
10243 CTX_RD(sc, GET_CID_ADDR(cid),
10244 BCE_L2CTX_TX_CMD_TYPE));
10245 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) "
10246 "h/w buffer descriptor address\n",
10247 CTX_RD(sc, GET_CID_ADDR(cid),
10248 BCE_L2CTX_TX_TBDR_BHADDR_HI));
10249 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) "
10250 "h/w buffer descriptor address\n",
10251 CTX_RD(sc, GET_CID_ADDR(cid),
10252 BCE_L2CTX_TX_TBDR_BHADDR_LO));
10253 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host "
10254 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10255 BCE_L2CTX_TX_HOST_BIDX));
10256 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte "
10257 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
10258 BCE_L2CTX_TX_HOST_BSEQ));
10263 "----------------------------"
10265 "----------------------------\n");
10267 for (int i = 0x0; i < 0x300; i += 0x10) {
10268 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
10269 CTX_RD(sc, GET_CID_ADDR(cid), i),
10270 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4),
10271 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8),
10272 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc));
10277 "----------------------------"
10279 "----------------------------\n");
10283 /****************************************************************************/
10284 /* Prints out the FTQ data. */
10288 /****************************************************************************/
10289 static __attribute__ ((noinline)) void
10290 bce_dump_ftqs(struct bce_softc *sc)
10292 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val;
10295 "----------------------------"
10297 "----------------------------\n");
10299 BCE_PRINTF(" FTQ Command Control Depth_Now "
10300 "Max_Depth Valid_Cnt \n");
10301 BCE_PRINTF(" ------- ---------- ---------- ---------- "
10302 "---------- ----------\n");
10304 /* Setup the generic statistic counters for the FTQ valid count. */
10305 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) |
10306 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) |
10307 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) |
10308 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT);
10309 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10311 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) |
10312 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) |
10313 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) |
10314 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT);
10315 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val);
10317 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) |
10318 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) |
10319 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) |
10320 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT);
10321 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val);
10323 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) |
10324 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) |
10325 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) |
10326 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT);
10327 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val);
10329 /* Input queue to the Receive Lookup state machine */
10330 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD);
10331 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL);
10332 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22;
10333 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12;
10334 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
10335 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10336 cmd, ctl, cur_depth, max_depth, valid_cnt);
10338 /* Input queue to the Receive Processor */
10339 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD);
10340 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL);
10341 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22;
10342 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12;
10343 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
10344 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10345 cmd, ctl, cur_depth, max_depth, valid_cnt);
10347 /* Input queue to the Recevie Processor */
10348 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD);
10349 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL);
10350 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22;
10351 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12;
10352 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
10353 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10354 cmd, ctl, cur_depth, max_depth, valid_cnt);
10356 /* Input queue to the Receive Virtual to Physical state machine */
10357 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD);
10358 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL);
10359 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22;
10360 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12;
10361 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
10362 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10363 cmd, ctl, cur_depth, max_depth, valid_cnt);
10365 /* Input queue to the Recevie Virtual to Physical state machine */
10366 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD);
10367 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL);
10368 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22;
10369 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12;
10370 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4);
10371 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10372 cmd, ctl, cur_depth, max_depth, valid_cnt);
10374 /* Input queue to the Receive Virtual to Physical state machine */
10375 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD);
10376 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL);
10377 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22;
10378 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12;
10379 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5);
10380 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10381 cmd, ctl, cur_depth, max_depth, valid_cnt);
10383 /* Input queue to the Receive DMA state machine */
10384 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD);
10385 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL);
10386 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22;
10387 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12;
10388 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6);
10389 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10390 cmd, ctl, cur_depth, max_depth, valid_cnt);
10392 /* Input queue to the Transmit Scheduler state machine */
10393 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD);
10394 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL);
10395 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22;
10396 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12;
10397 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7);
10398 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10399 cmd, ctl, cur_depth, max_depth, valid_cnt);
10401 /* Input queue to the Transmit Buffer Descriptor state machine */
10402 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD);
10403 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL);
10404 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22;
10405 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12;
10406 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8);
10407 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10408 cmd, ctl, cur_depth, max_depth, valid_cnt);
10410 /* Input queue to the Transmit Processor */
10411 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD);
10412 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL);
10413 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22;
10414 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12;
10415 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9);
10416 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10417 cmd, ctl, cur_depth, max_depth, valid_cnt);
10419 /* Input queue to the Transmit DMA state machine */
10420 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD);
10421 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL);
10422 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22;
10423 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12;
10424 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10);
10425 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10426 cmd, ctl, cur_depth, max_depth, valid_cnt);
10428 /* Input queue to the Transmit Patch-Up Processor */
10429 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD);
10430 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL);
10431 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22;
10432 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12;
10433 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11);
10434 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10435 cmd, ctl, cur_depth, max_depth, valid_cnt);
10437 /* Input queue to the Transmit Assembler state machine */
10438 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD);
10439 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL);
10440 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22;
10441 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12;
10442 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12);
10443 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10444 cmd, ctl, cur_depth, max_depth, valid_cnt);
10446 /* Input queue to the Completion Processor */
10447 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD);
10448 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL);
10449 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22;
10450 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12;
10451 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13);
10452 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10453 cmd, ctl, cur_depth, max_depth, valid_cnt);
10455 /* Input queue to the Completion Processor */
10456 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD);
10457 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL);
10458 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22;
10459 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12;
10460 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14);
10461 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10462 cmd, ctl, cur_depth, max_depth, valid_cnt);
10464 /* Input queue to the Completion Processor */
10465 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD);
10466 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL);
10467 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22;
10468 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12;
10469 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15);
10470 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10471 cmd, ctl, cur_depth, max_depth, valid_cnt);
10473 /* Setup the generic statistic counters for the FTQ valid count. */
10474 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) |
10475 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) |
10476 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT);
10478 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
10480 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI <<
10482 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10484 /* Input queue to the Management Control Processor */
10485 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD);
10486 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL);
10487 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22;
10488 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12;
10489 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
10490 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10491 cmd, ctl, cur_depth, max_depth, valid_cnt);
10493 /* Input queue to the Command Processor */
10494 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD);
10495 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL);
10496 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22;
10497 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12;
10498 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
10499 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10500 cmd, ctl, cur_depth, max_depth, valid_cnt);
10502 /* Input queue to the Completion Scheduler state machine */
10503 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD);
10504 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL);
10505 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22;
10506 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12;
10507 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
10508 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10509 cmd, ctl, cur_depth, max_depth, valid_cnt);
10511 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
10512 /* Input queue to the RV2P Command Scheduler */
10513 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD);
10514 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL);
10515 cur_depth = (ctl & 0xFFC00000) >> 22;
10516 max_depth = (ctl & 0x003FF000) >> 12;
10517 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
10518 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10519 cmd, ctl, cur_depth, max_depth, valid_cnt);
10523 "----------------------------"
10525 "----------------------------\n");
10529 /****************************************************************************/
10530 /* Prints out the TX chain. */
10534 /****************************************************************************/
10535 static __attribute__ ((noinline)) void
10536 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count)
10538 struct tx_bd *txbd;
10540 /* First some info about the tx_bd chain structure. */
10542 "----------------------------"
10544 "----------------------------\n");
10546 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n",
10547 (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages);
10548 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n",
10549 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE);
10550 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC);
10553 "----------------------------"
10555 "----------------------------\n");
10557 /* Now print out a decoded list of TX buffer descriptors. */
10558 for (int i = 0; i < count; i++) {
10559 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
10560 bce_dump_txbd(sc, tx_prod, txbd);
10565 "----------------------------"
10567 "----------------------------\n");
10571 /****************************************************************************/
10572 /* Prints out the RX chain. */
10576 /****************************************************************************/
10577 static __attribute__ ((noinline)) void
10578 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count)
10580 struct rx_bd *rxbd;
10582 /* First some info about the rx_bd chain structure. */
10584 "----------------------------"
10586 "----------------------------\n");
10588 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n",
10589 (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages);
10591 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
10592 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE);
10594 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC);
10597 "----------------------------"
10599 "----------------------------\n");
10601 /* Now print out the rx_bd's themselves. */
10602 for (int i = 0; i < count; i++) {
10603 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
10604 bce_dump_rxbd(sc, rx_prod, rxbd);
10605 rx_prod = RX_CHAIN_IDX(rx_prod + 1);
10609 "----------------------------"
10611 "----------------------------\n");
10615 /****************************************************************************/
10616 /* Prints out the page chain. */
10620 /****************************************************************************/
10621 static __attribute__ ((noinline)) void
10622 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count)
10624 struct rx_bd *pgbd;
10626 /* First some info about the page chain structure. */
10628 "----------------------------"
10630 "----------------------------\n");
10632 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n",
10633 (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages);
10635 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
10636 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE);
10638 BCE_PRINTF("total pg_bd = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC);
10641 "----------------------------"
10643 "----------------------------\n");
10645 /* Now print out the rx_bd's themselves. */
10646 for (int i = 0; i < count; i++) {
10647 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)];
10648 bce_dump_pgbd(sc, pg_prod, pgbd);
10649 pg_prod = PG_CHAIN_IDX(pg_prod + 1);
10653 "----------------------------"
10655 "----------------------------\n");
10659 #define BCE_PRINT_RX_CONS(arg) \
10660 if (sblk->status_rx_quick_consumer_index##arg) \
10661 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \
10662 sblk->status_rx_quick_consumer_index##arg, (u16) \
10663 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \
10667 #define BCE_PRINT_TX_CONS(arg) \
10668 if (sblk->status_tx_quick_consumer_index##arg) \
10669 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \
10670 sblk->status_tx_quick_consumer_index##arg, (u16) \
10671 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \
10674 /****************************************************************************/
10675 /* Prints out the status block from host memory. */
10679 /****************************************************************************/
10680 static __attribute__ ((noinline)) void
10681 bce_dump_status_block(struct bce_softc *sc)
10683 struct status_block *sblk;
10685 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
10687 sblk = sc->status_block;
10690 "----------------------------"
10692 "----------------------------\n");
10694 /* Theses indices are used for normal L2 drivers. */
10695 BCE_PRINTF(" 0x%08X - attn_bits\n",
10696 sblk->status_attn_bits);
10698 BCE_PRINTF(" 0x%08X - attn_bits_ack\n",
10699 sblk->status_attn_bits_ack);
10701 BCE_PRINT_RX_CONS(0);
10702 BCE_PRINT_TX_CONS(0)
10704 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx);
10706 /* Theses indices are not used for normal L2 drivers. */
10707 BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3);
10708 BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6);
10709 BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9);
10710 BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12);
10711 BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15);
10713 BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3);
10715 if (sblk->status_completion_producer_index ||
10716 sblk->status_cmd_consumer_index)
10717 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n",
10718 sblk->status_completion_producer_index,
10719 sblk->status_cmd_consumer_index);
10722 "----------------------------"
10724 "----------------------------\n");
10728 #define BCE_PRINT_64BIT_STAT(arg) \
10729 if (sblk->arg##_lo || sblk->arg##_hi) \
10730 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \
10731 sblk->arg##_lo, #arg);
10733 #define BCE_PRINT_32BIT_STAT(arg) \
10735 BCE_PRINTF(" 0x%08X : %s\n", \
10738 /****************************************************************************/
10739 /* Prints out the statistics block from host memory. */
10743 /****************************************************************************/
10744 static __attribute__ ((noinline)) void
10745 bce_dump_stats_block(struct bce_softc *sc)
10747 struct statistics_block *sblk;
10749 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD);
10751 sblk = sc->stats_block;
10755 " Stats Block (All Stats Not Shown Are 0) "
10756 "---------------\n");
10758 BCE_PRINT_64BIT_STAT(stat_IfHCInOctets);
10759 BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets);
10760 BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets);
10761 BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets);
10762 BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts);
10763 BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts);
10764 BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts);
10765 BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts);
10766 BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts);
10767 BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts);
10768 BCE_PRINT_32BIT_STAT(
10769 stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
10770 BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors);
10771 BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors);
10772 BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors);
10773 BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames);
10774 BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames);
10775 BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions);
10776 BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions);
10777 BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions);
10778 BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions);
10779 BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments);
10780 BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers);
10781 BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts);
10782 BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts);
10783 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets);
10784 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets);
10785 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets);
10786 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets);
10787 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets);
10788 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets);
10789 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets);
10790 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets);
10791 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets);
10792 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets);
10793 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets);
10794 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets);
10795 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets);
10796 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets);
10797 BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived);
10798 BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived);
10799 BCE_PRINT_32BIT_STAT(stat_OutXonSent);
10800 BCE_PRINT_32BIT_STAT(stat_OutXoffSent);
10801 BCE_PRINT_32BIT_STAT(stat_FlowControlDone);
10802 BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived);
10803 BCE_PRINT_32BIT_STAT(stat_XoffStateEntered);
10804 BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards);
10805 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards);
10806 BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards);
10807 BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards);
10808 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit);
10809 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards);
10810 BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards);
10811 BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards);
10812 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit);
10815 "----------------------------"
10817 "----------------------------\n");
10821 /****************************************************************************/
10822 /* Prints out a summary of the driver state. */
10826 /****************************************************************************/
10827 static __attribute__ ((noinline)) void
10828 bce_dump_driver_state(struct bce_softc *sc)
10830 u32 val_hi, val_lo;
10833 "-----------------------------"
10835 "-----------------------------\n");
10837 val_hi = BCE_ADDR_HI(sc);
10838 val_lo = BCE_ADDR_LO(sc);
10839 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual "
10840 "address\n", val_hi, val_lo);
10842 val_hi = BCE_ADDR_HI(sc->bce_vhandle);
10843 val_lo = BCE_ADDR_LO(sc->bce_vhandle);
10844 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual "
10845 "address\n", val_hi, val_lo);
10847 val_hi = BCE_ADDR_HI(sc->status_block);
10848 val_lo = BCE_ADDR_LO(sc->status_block);
10849 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block "
10850 "virtual address\n", val_hi, val_lo);
10852 val_hi = BCE_ADDR_HI(sc->stats_block);
10853 val_lo = BCE_ADDR_LO(sc->stats_block);
10854 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block "
10855 "virtual address\n", val_hi, val_lo);
10857 val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
10858 val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
10859 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
10860 "virtual adddress\n", val_hi, val_lo);
10862 val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
10863 val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
10864 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
10865 "virtual address\n", val_hi, val_lo);
10867 if (bce_hdr_split == TRUE) {
10868 val_hi = BCE_ADDR_HI(sc->pg_bd_chain);
10869 val_lo = BCE_ADDR_LO(sc->pg_bd_chain);
10870 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain "
10871 "virtual address\n", val_hi, val_lo);
10874 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
10875 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
10876 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
10877 "virtual address\n", val_hi, val_lo);
10879 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
10880 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
10881 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
10882 "virtual address\n", val_hi, val_lo);
10884 if (bce_hdr_split == TRUE) {
10885 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr);
10886 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr);
10887 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain "
10888 "virtual address\n", val_hi, val_lo);
10891 BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) "
10893 (long long unsigned int) sc->interrupts_generated);
10895 BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) "
10896 "rx interrupts handled\n",
10897 (long long unsigned int) sc->interrupts_rx);
10899 BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) "
10900 "tx interrupts handled\n",
10901 (long long unsigned int) sc->interrupts_tx);
10903 BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) "
10904 "phy interrupts handled\n",
10905 (long long unsigned int) sc->phy_interrupts);
10907 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) "
10908 "status block index\n", sc->last_status_idx);
10910 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer "
10911 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod));
10913 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer "
10914 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons));
10916 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer "
10917 "byte seq index\n", sc->tx_prod_bseq);
10919 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx "
10920 "mbufs allocated\n", sc->debug_tx_mbuf_alloc);
10922 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used "
10923 "tx_bd's\n", sc->used_tx_bd);
10925 BCE_PRINTF(" 0x%04X/0x%04X - (sc->tx_hi_watermark)/"
10926 "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd);
10928 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer "
10929 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod));
10931 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer "
10932 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons));
10934 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer "
10935 "byte seq index\n", sc->rx_prod_bseq);
10937 BCE_PRINTF(" 0x%04X/0x%04X - (sc->rx_low_watermark)/"
10938 "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd);
10940 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx "
10941 "mbufs allocated\n", sc->debug_rx_mbuf_alloc);
10943 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free "
10944 "rx_bd's\n", sc->free_rx_bd);
10946 if (bce_hdr_split == TRUE) {
10947 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer "
10948 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod));
10950 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer "
10951 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons));
10953 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page "
10954 "mbufs allocated\n", sc->debug_pg_mbuf_alloc);
10957 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page "
10958 "rx_bd's\n", sc->free_pg_bd);
10960 BCE_PRINTF(" 0x%04X/0x%04X - (sc->pg_low_watermark)/"
10961 "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd);
10963 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) "
10964 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count);
10966 BCE_PRINTF(" 0x%08X - (sc->bce_flags) "
10967 "bce mac flags\n", sc->bce_flags);
10969 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) "
10970 "bce phy flags\n", sc->bce_phy_flags);
10973 "----------------------------"
10975 "----------------------------\n");
10979 /****************************************************************************/
10980 /* Prints out the hardware state through a summary of important register, */
10981 /* followed by a complete register dump. */
10985 /****************************************************************************/
10986 static __attribute__ ((noinline)) void
10987 bce_dump_hw_state(struct bce_softc *sc)
10992 "----------------------------"
10994 "----------------------------\n");
10996 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
10998 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
10999 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n",
11000 val, BCE_MISC_ENABLE_STATUS_BITS);
11002 val = REG_RD(sc, BCE_DMA_STATUS);
11003 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n",
11004 val, BCE_DMA_STATUS);
11006 val = REG_RD(sc, BCE_CTX_STATUS);
11007 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n",
11008 val, BCE_CTX_STATUS);
11010 val = REG_RD(sc, BCE_EMAC_STATUS);
11011 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n",
11012 val, BCE_EMAC_STATUS);
11014 val = REG_RD(sc, BCE_RPM_STATUS);
11015 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n",
11016 val, BCE_RPM_STATUS);
11018 /* ToDo: Create a #define for this constant. */
11019 val = REG_RD(sc, 0x2004);
11020 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n",
11023 val = REG_RD(sc, BCE_RV2P_STATUS);
11024 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n",
11025 val, BCE_RV2P_STATUS);
11027 /* ToDo: Create a #define for this constant. */
11028 val = REG_RD(sc, 0x2c04);
11029 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n",
11032 val = REG_RD(sc, BCE_TBDR_STATUS);
11033 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n",
11034 val, BCE_TBDR_STATUS);
11036 val = REG_RD(sc, BCE_TDMA_STATUS);
11037 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n",
11038 val, BCE_TDMA_STATUS);
11040 val = REG_RD(sc, BCE_HC_STATUS);
11041 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n",
11042 val, BCE_HC_STATUS);
11044 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
11045 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
11046 val, BCE_TXP_CPU_STATE);
11048 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11049 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
11050 val, BCE_TPAT_CPU_STATE);
11052 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11053 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
11054 val, BCE_RXP_CPU_STATE);
11056 val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11057 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
11058 val, BCE_COM_CPU_STATE);
11060 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
11061 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n",
11062 val, BCE_MCP_CPU_STATE);
11064 val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11065 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
11066 val, BCE_CP_CPU_STATE);
11069 "----------------------------"
11071 "----------------------------\n");
11074 "----------------------------"
11076 "----------------------------\n");
11078 for (int i = 0x400; i < 0x8000; i += 0x10) {
11079 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11080 i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
11081 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
11085 "----------------------------"
11087 "----------------------------\n");
11091 /****************************************************************************/
11092 /* Prints out the contentst of shared memory which is used for host driver */
11093 /* to bootcode firmware communication. */
11097 /****************************************************************************/
11098 static __attribute__ ((noinline)) void
11099 bce_dump_shmem_state(struct bce_softc *sc)
11102 "----------------------------"
11104 "----------------------------\n");
11106 BCE_PRINTF("0x%08X - Shared memory base address\n",
11107 sc->bce_shmem_base);
11108 BCE_PRINTF("%s - bootcode version\n",
11112 "----------------------------"
11114 "----------------------------\n");
11116 for (int i = 0x0; i < 0x200; i += 0x10) {
11117 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11118 i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4),
11119 bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC));
11123 "----------------------------"
11125 "----------------------------\n");
11129 /****************************************************************************/
11130 /* Prints out the mailbox queue registers. */
11134 /****************************************************************************/
11135 static __attribute__ ((noinline)) void
11136 bce_dump_mq_regs(struct bce_softc *sc)
11139 "----------------------------"
11141 "----------------------------\n");
11144 "----------------------------"
11146 "----------------------------\n");
11148 for (int i = 0x3c00; i < 0x4000; i += 0x10) {
11149 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11150 i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
11151 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
11155 "----------------------------"
11157 "----------------------------\n");
11161 /****************************************************************************/
11162 /* Prints out the bootcode state. */
11166 /****************************************************************************/
11167 static __attribute__ ((noinline)) void
11168 bce_dump_bc_state(struct bce_softc *sc)
11173 "----------------------------"
11175 "----------------------------\n");
11177 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
11179 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE);
11180 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n",
11181 val, BCE_BC_RESET_TYPE);
11183 val = bce_shmem_rd(sc, BCE_BC_STATE);
11184 BCE_PRINTF("0x%08X - (0x%06X) state\n",
11185 val, BCE_BC_STATE);
11187 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
11188 BCE_PRINTF("0x%08X - (0x%06X) condition\n",
11189 val, BCE_BC_STATE_CONDITION);
11191 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD);
11192 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n",
11193 val, BCE_BC_STATE_DEBUG_CMD);
11196 "----------------------------"
11198 "----------------------------\n");
11202 /****************************************************************************/
11203 /* Prints out the TXP processor state. */
11207 /****************************************************************************/
11208 static __attribute__ ((noinline)) void
11209 bce_dump_txp_state(struct bce_softc *sc, int regs)
11215 "----------------------------"
11217 "----------------------------\n");
11219 for (int i = 0; i < 3; i++)
11220 fw_version[i] = htonl(REG_RD_IND(sc,
11221 (BCE_TXP_SCRATCH + 0x10 + i * 4)));
11222 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11224 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
11225 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n",
11226 val, BCE_TXP_CPU_MODE);
11228 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
11229 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
11230 val, BCE_TXP_CPU_STATE);
11232 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
11233 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n",
11234 val, BCE_TXP_CPU_EVENT_MASK);
11238 "----------------------------"
11240 "----------------------------\n");
11242 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
11243 /* Skip the big blank spaces */
11244 if (i < 0x454000 && i > 0x5ffff)
11245 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11246 "0x%08X 0x%08X\n", i,
11248 REG_RD_IND(sc, i + 0x4),
11249 REG_RD_IND(sc, i + 0x8),
11250 REG_RD_IND(sc, i + 0xC));
11255 "----------------------------"
11257 "----------------------------\n");
11261 /****************************************************************************/
11262 /* Prints out the RXP processor state. */
11266 /****************************************************************************/
11267 static __attribute__ ((noinline)) void
11268 bce_dump_rxp_state(struct bce_softc *sc, int regs)
11274 "----------------------------"
11276 "----------------------------\n");
11278 for (int i = 0; i < 3; i++)
11279 fw_version[i] = htonl(REG_RD_IND(sc,
11280 (BCE_RXP_SCRATCH + 0x10 + i * 4)));
11282 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11284 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
11285 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n",
11286 val, BCE_RXP_CPU_MODE);
11288 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11289 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
11290 val, BCE_RXP_CPU_STATE);
11292 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
11293 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n",
11294 val, BCE_RXP_CPU_EVENT_MASK);
11298 "----------------------------"
11300 "----------------------------\n");
11302 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
11303 /* Skip the big blank sapces */
11304 if (i < 0xc5400 && i > 0xdffff)
11305 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11306 "0x%08X 0x%08X\n", i,
11308 REG_RD_IND(sc, i + 0x4),
11309 REG_RD_IND(sc, i + 0x8),
11310 REG_RD_IND(sc, i + 0xC));
11315 "----------------------------"
11317 "----------------------------\n");
11321 /****************************************************************************/
11322 /* Prints out the TPAT processor state. */
11326 /****************************************************************************/
11327 static __attribute__ ((noinline)) void
11328 bce_dump_tpat_state(struct bce_softc *sc, int regs)
11334 "----------------------------"
11336 "----------------------------\n");
11338 for (int i = 0; i < 3; i++)
11339 fw_version[i] = htonl(REG_RD_IND(sc,
11340 (BCE_TPAT_SCRATCH + 0x410 + i * 4)));
11342 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11344 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
11345 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n",
11346 val, BCE_TPAT_CPU_MODE);
11348 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11349 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
11350 val, BCE_TPAT_CPU_STATE);
11352 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
11353 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n",
11354 val, BCE_TPAT_CPU_EVENT_MASK);
11358 "----------------------------"
11360 "----------------------------\n");
11362 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
11363 /* Skip the big blank spaces */
11364 if (i < 0x854000 && i > 0x9ffff)
11365 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11366 "0x%08X 0x%08X\n", i,
11368 REG_RD_IND(sc, i + 0x4),
11369 REG_RD_IND(sc, i + 0x8),
11370 REG_RD_IND(sc, i + 0xC));
11375 "----------------------------"
11377 "----------------------------\n");
11381 /****************************************************************************/
11382 /* Prints out the Command Procesor (CP) state. */
11386 /****************************************************************************/
11387 static __attribute__ ((noinline)) void
11388 bce_dump_cp_state(struct bce_softc *sc, int regs)
11394 "----------------------------"
11396 "----------------------------\n");
11398 for (int i = 0; i < 3; i++)
11399 fw_version[i] = htonl(REG_RD_IND(sc,
11400 (BCE_CP_SCRATCH + 0x10 + i * 4)));
11402 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11404 val = REG_RD_IND(sc, BCE_CP_CPU_MODE);
11405 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n",
11406 val, BCE_CP_CPU_MODE);
11408 val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11409 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
11410 val, BCE_CP_CPU_STATE);
11412 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK);
11413 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val,
11414 BCE_CP_CPU_EVENT_MASK);
11418 "----------------------------"
11420 "----------------------------\n");
11422 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) {
11423 /* Skip the big blank spaces */
11424 if (i < 0x185400 && i > 0x19ffff)
11425 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11426 "0x%08X 0x%08X\n", i,
11428 REG_RD_IND(sc, i + 0x4),
11429 REG_RD_IND(sc, i + 0x8),
11430 REG_RD_IND(sc, i + 0xC));
11435 "----------------------------"
11437 "----------------------------\n");
11441 /****************************************************************************/
11442 /* Prints out the Completion Procesor (COM) state. */
11446 /****************************************************************************/
11447 static __attribute__ ((noinline)) void
11448 bce_dump_com_state(struct bce_softc *sc, int regs)
11454 "----------------------------"
11456 "----------------------------\n");
11458 for (int i = 0; i < 3; i++)
11459 fw_version[i] = htonl(REG_RD_IND(sc,
11460 (BCE_COM_SCRATCH + 0x10 + i * 4)));
11462 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11464 val = REG_RD_IND(sc, BCE_COM_CPU_MODE);
11465 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n",
11466 val, BCE_COM_CPU_MODE);
11468 val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11469 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
11470 val, BCE_COM_CPU_STATE);
11472 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK);
11473 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val,
11474 BCE_COM_CPU_EVENT_MASK);
11478 "----------------------------"
11480 "----------------------------\n");
11482 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) {
11483 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11484 "0x%08X 0x%08X\n", i,
11486 REG_RD_IND(sc, i + 0x4),
11487 REG_RD_IND(sc, i + 0x8),
11488 REG_RD_IND(sc, i + 0xC));
11493 "----------------------------"
11495 "----------------------------\n");
11499 /****************************************************************************/
11500 /* Prints out the Receive Virtual 2 Physical (RV2P) state. */
11504 /****************************************************************************/
11505 static __attribute__ ((noinline)) void
11506 bce_dump_rv2p_state(struct bce_softc *sc)
11508 u32 val, pc1, pc2, fw_ver_high, fw_ver_low;
11511 "----------------------------"
11513 "----------------------------\n");
11515 /* Stall the RV2P processors. */
11516 val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11517 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2;
11518 REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
11520 /* Read the firmware version. */
11522 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
11523 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
11524 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
11525 BCE_RV2P_INSTR_HIGH_HIGH;
11526 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n",
11527 fw_ver_high, fw_ver_low);
11530 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
11531 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
11532 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
11533 BCE_RV2P_INSTR_HIGH_HIGH;
11534 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n",
11535 fw_ver_high, fw_ver_low);
11537 /* Resume the RV2P processors. */
11538 val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11539 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2);
11540 REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
11542 /* Fetch the program counter value. */
11544 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
11545 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11546 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
11547 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
11548 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1);
11549 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2);
11551 /* Fetch the program counter value again to see if it is advancing. */
11553 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
11554 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11555 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
11556 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
11557 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1);
11558 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2);
11561 "----------------------------"
11563 "----------------------------\n");
11567 /****************************************************************************/
11568 /* Prints out the driver state and then enters the debugger. */
11572 /****************************************************************************/
11573 static __attribute__ ((noinline)) void
11574 bce_breakpoint(struct bce_softc *sc)
11578 * Unreachable code to silence compiler warnings
11579 * about unused functions.
11582 bce_freeze_controller(sc);
11583 bce_unfreeze_controller(sc);
11584 bce_dump_enet(sc, NULL);
11585 bce_dump_txbd(sc, 0, NULL);
11586 bce_dump_rxbd(sc, 0, NULL);
11587 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC);
11588 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC);
11589 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC);
11590 bce_dump_l2fhdr(sc, 0, NULL);
11591 bce_dump_ctx(sc, RX_CID);
11593 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC);
11594 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC);
11595 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC);
11596 bce_dump_status_block(sc);
11597 bce_dump_stats_block(sc);
11598 bce_dump_driver_state(sc);
11599 bce_dump_hw_state(sc);
11600 bce_dump_bc_state(sc);
11601 bce_dump_txp_state(sc, 0);
11602 bce_dump_rxp_state(sc, 0);
11603 bce_dump_tpat_state(sc, 0);
11604 bce_dump_cp_state(sc, 0);
11605 bce_dump_com_state(sc, 0);
11606 bce_dump_rv2p_state(sc);
11607 bce_dump_pgbd(sc, 0, NULL);
11610 bce_dump_status_block(sc);
11611 bce_dump_driver_state(sc);
11613 /* Call the debugger. */