sys/dev/bce/if_bcereg.h

   1 /*-
   2  * Copyright (c) 2006 Broadcom Corporation
   3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
  14  *    may be used to endorse or promote products derived from this software
  15  *    without specific prior written consent.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  18  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  21  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  22  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  25  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  27  * THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * $FreeBSD$
  30  */
  31
  32 #ifndef _BCE_H_DEFINED
  33 #define _BCE_H_DEFINED
  34
  35 #ifdef HAVE_KERNEL_OPTION_HEADERS
  36 #include "opt_device_polling.h"
  37 #endif
  38
  39 #include <sys/param.h>
  40 #include <sys/endian.h>
  41 #include <sys/systm.h>
  42 #include <sys/sockio.h>
  43 #include <sys/mbuf.h>
  44 #include <sys/malloc.h>
  45 #include <sys/kernel.h>
  46 #include <sys/module.h>
  47 #include <sys/socket.h>
  48 #include <sys/sysctl.h>
  49 #include <sys/queue.h>
  50
  51 #include <net/if.h>
  52 #include <net/if_arp.h>
  53 #include <net/ethernet.h>
  54 #include <net/if_dl.h>
  55 #include <net/if_media.h>
  56
  57 #include <net/bpf.h>
  58
  59 #include <net/if_types.h>
  60 #include <net/if_vlan_var.h>
  61
  62 #include <netinet/in_systm.h>
  63 #include <netinet/in.h>
  64 #include <netinet/ip.h>
  65
  66 #include <machine/clock.h>      /* for DELAY */
  67 #include <machine/bus.h>
  68 #include <machine/resource.h>
  69 #include <sys/bus.h>
  70 #include <sys/rman.h>
  71
  72 #include <dev/mii/mii.h>
  73 #include <dev/mii/miivar.h>
  74 #include "miidevs.h"
  75 #include <dev/mii/brgphyreg.h>
  76
  77 #include <dev/pci/pcireg.h>
  78 #include <dev/pci/pcivar.h>
  79
  80 #include "miibus_if.h"
  81
  82 /****************************************************************************/
  83 /* Conversion to FreeBSD type definitions.                                  */
  84 /****************************************************************************/
  85 #define u64 uint64_t
  86 #define u32     uint32_t
  87 #define u16     uint16_t
  88 #define u8      uint8_t
  89
  90 #if BYTE_ORDER == BIG_ENDIAN
  91 #define __BIG_ENDIAN 1
  92 #undef  __LITTLE_ENDIAN
  93 #else
  94 #undef  __BIG_ENDIAN
  95 #define __LITTLE_ENDIAN 1
  96 #endif
  97
  98 /****************************************************************************/
  99 /* Debugging macros and definitions.                                        */
 100 /****************************************************************************/
 101 #define BCE_CP_LOAD                     0x00000001
 102 #define BCE_CP_SEND                             0x00000002
 103 #define BCE_CP_RECV                             0x00000004
 104 #define BCE_CP_INTR                             0x00000008
 105 #define BCE_CP_UNLOAD                   0x00000010
 106 #define BCE_CP_RESET                    0x00000020
 107 #define BCE_CP_ALL                              0x00FFFFFF
 108
 109 #define BCE_CP_MASK                             0x00FFFFFF
 110
 111 #define BCE_LEVEL_FATAL                 0x00000000
 112 #define BCE_LEVEL_WARN                  0x01000000
 113 #define BCE_LEVEL_INFO                  0x02000000
 114 #define BCE_LEVEL_VERBOSE               0x03000000
 115 #define BCE_LEVEL_EXCESSIVE             0x04000000
 116
 117 #define BCE_LEVEL_MASK                  0xFF000000
 118
 119 #define BCE_WARN_LOAD                   (BCE_CP_LOAD | BCE_LEVEL_WARN)
 120 #define BCE_INFO_LOAD                   (BCE_CP_LOAD | BCE_LEVEL_INFO)
 121 #define BCE_VERBOSE_LOAD                (BCE_CP_LOAD | BCE_LEVEL_VERBOSE)
 122 #define BCE_EXCESSIVE_LOAD              (BCE_CP_LOAD | BCE_LEVEL_EXCESSIVE)
 123
 124 #define BCE_WARN_SEND                   (BCE_CP_SEND | BCE_LEVEL_WARN)
 125 #define BCE_INFO_SEND                   (BCE_CP_SEND | BCE_LEVEL_INFO)
 126 #define BCE_VERBOSE_SEND                (BCE_CP_SEND | BCE_LEVEL_VERBOSE)
 127 #define BCE_EXCESSIVE_SEND              (BCE_CP_SEND | BCE_LEVEL_EXCESSIVE)
 128
 129 #define BCE_WARN_RECV                   (BCE_CP_RECV | BCE_LEVEL_WARN)
 130 #define BCE_INFO_RECV                   (BCE_CP_RECV | BCE_LEVEL_INFO)
 131 #define BCE_VERBOSE_RECV                (BCE_CP_RECV | BCE_LEVEL_VERBOSE)
 132 #define BCE_EXCESSIVE_RECV              (BCE_CP_RECV | BCE_LEVEL_EXCESSIVE)
 133
 134 #define BCE_WARN_INTR                   (BCE_CP_INTR | BCE_LEVEL_WARN)
 135 #define BCE_INFO_INTR                   (BCE_CP_INTR | BCE_LEVEL_INFO)
 136 #define BCE_VERBOSE_INTR                (BCE_CP_INTR | BCE_LEVEL_VERBOSE)
 137 #define BCE_EXCESSIVE_INTR              (BCE_CP_INTR | BCE_LEVEL_EXCESSIVE)
 138
 139 #define BCE_WARN_UNLOAD                 (BCE_CP_UNLOAD | BCE_LEVEL_WARN)
 140 #define BCE_INFO_UNLOAD                 (BCE_CP_UNLOAD | BCE_LEVEL_INFO)
 141 #define BCE_VERBOSE_UNLOAD              (BCE_CP_UNLOAD | BCE_LEVEL_VERBOSE)
 142 #define BCE_EXCESSIVE_UNLOAD    (BCE_CP_UNLOAD | BCE_LEVEL_EXCESSIVE)
 143
 144 #define BCE_WARN_RESET                  (BCE_CP_RESET | BCE_LEVEL_WARN)
 145 #define BCE_INFO_RESET                  (BCE_CP_RESET | BCE_LEVEL_INFO)
 146 #define BCE_VERBOSE_RESET               (BCE_CP_RESET | BCE_LEVEL_VERBOSE)
 147 #define BCE_EXCESSIVE_RESET             (BCE_CP_RESET | BCE_LEVEL_EXCESSIVE)
 148
 149 #define BCE_FATAL                               (BCE_CP_ALL | BCE_LEVEL_FATAL)
 150 #define BCE_WARN                                (BCE_CP_ALL | BCE_LEVEL_WARN)
 151 #define BCE_INFO                                (BCE_CP_ALL | BCE_LEVEL_INFO)
 152 #define BCE_VERBOSE                             (BCE_CP_ALL | BCE_LEVEL_VERBOSE)
 153 #define BCE_EXCESSIVE                   (BCE_CP_ALL | BCE_LEVEL_EXCESSIVE)
 154
 155 #define BCE_CODE_PATH(cp)               ((cp & BCE_CP_MASK) & bce_debug)
 156 #define BCE_MSG_LEVEL(lv)               ((lv & BCE_LEVEL_MASK) <= (bce_debug & BCE_LEVEL_MASK))
 157 #define BCE_LOG_MSG(m)                  (BCE_CODE_PATH(m) && BCE_MSG_LEVEL(m))
 158
 159 #ifdef BCE_DEBUG
 160
 161 /* Print a message based on the logging level and code path. */
 162 #define DBPRINT(sc, level, format, args...)                                     \
 163         if (BCE_LOG_MSG(level)) {                                                       \
 164                 device_printf(sc->bce_dev, format, ## args);                                            \
 165         }
 166
 167 /* Runs a particular command based on the logging level and code path. */
 168 #define DBRUN(m, args...) \
 169         if (BCE_LOG_MSG(m)) { \
 170                 args; \
 171         }
 172
 173 /* Runs a particular command based on the logging level. */
 174 #define DBRUNLV(level, args...) \
 175         if (BCE_MSG_LEVEL(level)) { \
 176                 args; \
 177         }
 178
 179 /* Runs a particular command based on the code path. */
 180 #define DBRUNCP(cp, args...) \
 181         if (BCE_CODE_PATH(cp)) { \
 182                 args; \
 183         }
 184
 185 /* Runs a particular command based on a condition. */
 186 #define DBRUNIF(cond, args...) \
 187         if (cond) { \
 188                 args; \
 189         }
 190
 191 /* Needed for random() function which is only used in debugging. */
 192 #include <sys/random.h>
 193
 194 /* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */
 195 #define DB_RANDOMFALSE(defects)        (random() > defects)
 196 #define DB_OR_RANDOMFALSE(defects)  || (random() > defects)
 197 #define DB_AND_RANDOMFALSE(defects) && (random() > ddfects)
 198
 199 /* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */
 200 #define DB_RANDOMTRUE(defects)         (random() < defects)
 201 #define DB_OR_RANDOMTRUE(defects)   || (random() < defects)
 202 #define DB_AND_RANDOMTRUE(defects)  && (random() < defects)
 203
 204 #else
 205
 206 #define DBPRINT(level, format, args...)
 207 #define DBRUN(m, args...)
 208 #define DBRUNLV(level, args...)
 209 #define DBRUNCP(cp, args...)
 210 #define DBRUNIF(cond, args...)
 211 #define DB_RANDOMFALSE(defects)
 212 #define DB_OR_RANDOMFALSE(percent)
 213 #define DB_AND_RANDOMFALSE(percent)
 214 #define DB_RANDOMTRUE(defects)
 215 #define DB_OR_RANDOMTRUE(percent)
 216 #define DB_AND_RANDOMTRUE(percent)
 217
 218 #endif /* BCE_DEBUG */
 219
 220
 221 /****************************************************************************/
 222 /* Device identification definitions.                                       */
 223 /****************************************************************************/
 224 #define BRCM_VENDORID                           0x14E4
 225 #define BRCM_DEVICEID_BCM5706           0x164A
 226 #define BRCM_DEVICEID_BCM5706S          0x16AA
 227 #define BRCM_DEVICEID_BCM5708           0x164C
 228 #define BRCM_DEVICEID_BCM5708S          0x16AC
 229
 230 #define HP_VENDORID                                     0x103C
 231
 232 #define PCI_ANY_ID                                      (u_int16_t) (~0U)
 233
 234 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
 235
 236 #define BCE_CHIP_NUM(sc)                        (((sc)->bce_chipid) & 0xffff0000)
 237 #define BCE_CHIP_NUM_5706                       0x57060000
 238 #define BCE_CHIP_NUM_5708                       0x57080000
 239
 240 #define BCE_CHIP_REV(sc)                        (((sc)->bce_chipid) & 0x0000f000)
 241 #define BCE_CHIP_REV_Ax                         0x00000000
 242 #define BCE_CHIP_REV_Bx                         0x00001000
 243 #define BCE_CHIP_REV_Cx                         0x00002000
 244
 245 #define BCE_CHIP_METAL(sc)                      (((sc)->bce_chipid) & 0x00000ff0)
 246 #define BCE_CHIP_BOND(bp)                       (((sc)->bce_chipid) & 0x0000000f)
 247
 248 #define BCE_CHIP_ID(sc)                         (((sc)->bce_chipid) & 0xfffffff0)
 249 #define BCE_CHIP_ID_5706_A0                     0x57060000
 250 #define BCE_CHIP_ID_5706_A1                     0x57060010
 251 #define BCE_CHIP_ID_5706_A2                     0x57060020
 252 #define BCE_CHIP_ID_5708_A0                     0x57080000
 253 #define BCE_CHIP_ID_5708_B0                     0x57081000
 254 #define BCE_CHIP_ID_5708_B1                     0x57081010
 255
 256 #define BCE_CHIP_BOND_ID(sc)            (((sc)->bce_chipid) & 0xf)
 257
 258 /* A serdes chip will have the first bit of the bond id set. */
 259 #define BCE_CHIP_BOND_ID_SERDES_BIT             0x01
 260
 261
 262 /* shorthand one */
 263 #define BCE_ASICREV(x)                  ((x) >> 28)
 264 #define BCE_ASICREV_BCM5700             0x06
 265
 266 /* chip revisions */
 267 #define BCE_CHIPREV(x)                  ((x) >> 24)
 268 #define BCE_CHIPREV_5700_AX             0x70
 269 #define BCE_CHIPREV_5700_BX             0x71
 270 #define BCE_CHIPREV_5700_CX             0x72
 271 #define BCE_CHIPREV_5701_AX             0x00
 272
 273 struct bce_type {
 274         u_int16_t               bce_vid;
 275         u_int16_t               bce_did;
 276         u_int16_t               bce_svid;
 277         u_int16_t               bce_sdid;
 278         char                    *bce_name;
 279 };
 280
 281 /****************************************************************************/
 282 /* Byte order conversions.                                                  */
 283 /****************************************************************************/
 284 #if __FreeBSD_version >= 500000
 285 #define bce_htobe16(x) htobe16(x)
 286 #define bce_htobe32(x) htobe32(x)
 287 #define bce_htobe64(x) htobe64(x)
 288 #define bce_htole16(x) htole16(x)
 289 #define bce_htole32(x) htole32(x)
 290 #define bce_htole64(x) htole64(x)
 291
 292 #define bce_be16toh(x) be16toh(x)
 293 #define bce_be32toh(x) be32toh(x)
 294 #define bce_be64toh(x) be64toh(x)
 295 #define bce_le16toh(x) le16toh(x)
 296 #define bce_le32toh(x) le32toh(x)
 297 #define bce_le64toh(x) le64toh(x)
 298 #else
 299 #define bce_htobe16(x) (x)
 300 #define bce_htobe32(x) (x)
 301 #define bce_htobe64(x) (x)
 302 #define bce_htole16(x) (x)
 303 #define bce_htole32(x) (x)
 304 #define bce_htole64(x) (x)
 305
 306 #define bce_be16toh(x) (x)
 307 #define bce_be32toh(x) (x)
 308 #define bce_be64toh(x) (x)
 309 #define bce_le16toh(x) (x)
 310 #define bce_le32toh(x) (x)
 311 #define bce_le64toh(x) (x)
 312 #endif
 313
 314
 315 /****************************************************************************/
 316 /* NVRAM Access                                                             */
 317 /****************************************************************************/
 318
 319 /* Buffered flash (Atmel: AT45DB011B) specific information */
 320 #define SEEPROM_PAGE_BITS                               2
 321 #define SEEPROM_PHY_PAGE_SIZE                   (1 << SEEPROM_PAGE_BITS)
 322 #define SEEPROM_BYTE_ADDR_MASK                  (SEEPROM_PHY_PAGE_SIZE-1)
 323 #define SEEPROM_PAGE_SIZE                               4
 324 #define SEEPROM_TOTAL_SIZE                              65536
 325
 326 #define BUFFERED_FLASH_PAGE_BITS                9
 327 #define BUFFERED_FLASH_PHY_PAGE_SIZE    (1 << BUFFERED_FLASH_PAGE_BITS)
 328 #define BUFFERED_FLASH_BYTE_ADDR_MASK   (BUFFERED_FLASH_PHY_PAGE_SIZE-1)
 329 #define BUFFERED_FLASH_PAGE_SIZE                264
 330 #define BUFFERED_FLASH_TOTAL_SIZE               0x21000
 331
 332 #define SAIFUN_FLASH_PAGE_BITS                  8
 333 #define SAIFUN_FLASH_PHY_PAGE_SIZE              (1 << SAIFUN_FLASH_PAGE_BITS)
 334 #define SAIFUN_FLASH_BYTE_ADDR_MASK             (SAIFUN_FLASH_PHY_PAGE_SIZE-1)
 335 #define SAIFUN_FLASH_PAGE_SIZE                  256
 336 #define SAIFUN_FLASH_BASE_TOTAL_SIZE    65536
 337
 338 #define ST_MICRO_FLASH_PAGE_BITS                8
 339 #define ST_MICRO_FLASH_PHY_PAGE_SIZE    (1 << ST_MICRO_FLASH_PAGE_BITS)
 340 #define ST_MICRO_FLASH_BYTE_ADDR_MASK   (ST_MICRO_FLASH_PHY_PAGE_SIZE-1)
 341 #define ST_MICRO_FLASH_PAGE_SIZE                256
 342 #define ST_MICRO_FLASH_BASE_TOTAL_SIZE  65536
 343
 344 #define NVRAM_TIMEOUT_COUNT                             30000
 345 #define BCE_FLASHDESC_MAX                               64
 346
 347 #define FLASH_STRAP_MASK                                (BCE_NVM_CFG1_FLASH_MODE | \
 348                                                                                  BCE_NVM_CFG1_BUFFER_MODE  | \
 349                                                                                  BCE_NVM_CFG1_PROTECT_MODE | \
 350                                                                                  BCE_NVM_CFG1_FLASH_SIZE)
 351
 352 #define FLASH_BACKUP_STRAP_MASK                 (0xf << 26)
 353
 354 struct flash_spec {
 355         u32 strapping;
 356         u32 config1;
 357         u32 config2;
 358         u32 config3;
 359         u32 write1;
 360         u32 buffered;
 361         u32 page_bits;
 362         u32 page_size;
 363         u32 addr_mask;
 364         u32 total_size;
 365         u8  *name;
 366 };
 367
 368
 369 /****************************************************************************/
 370 /* Shared Memory layout                                                     */
 371 /* The BCE bootcode will initialize this data area with port configurtion   */
 372 /* information which can be accessed by the driver.                         */
 373 /****************************************************************************/
 374
 375 /*
 376  * This value (in milliseconds) determines the frequency of the driver
 377  * issuing the PULSE message code.  The firmware monitors this periodic
 378  * pulse to determine when to switch to an OS-absent mode.
 379  */
 380 #define DRV_PULSE_PERIOD_MS                 250
 381
 382 /*
 383  * This value (in milliseconds) determines how long the driver should
 384  * wait for an acknowledgement from the firmware before timing out.  Once
 385  * the firmware has timed out, the driver will assume there is no firmware
 386  * running and there won't be any firmware-driver synchronization during a
 387  * driver reset.
 388  */
 389 #define FW_ACK_TIME_OUT_MS                  100
 390
 391
 392 #define BCE_DRV_RESET_SIGNATURE                         0x00000000
 393 #define BCE_DRV_RESET_SIGNATURE_MAGIC           0x4841564b /* HAVK */
 394
 395 #define BCE_DRV_MB                                                      0x00000004
 396 #define BCE_DRV_MSG_CODE                                        0xff000000
 397 #define BCE_DRV_MSG_CODE_RESET                          0x01000000
 398 #define BCE_DRV_MSG_CODE_UNLOAD                         0x02000000
 399 #define BCE_DRV_MSG_CODE_SHUTDOWN                       0x03000000
 400 #define BCE_DRV_MSG_CODE_SUSPEND_WOL            0x04000000
 401 #define BCE_DRV_MSG_CODE_FW_TIMEOUT                     0x05000000
 402 #define BCE_DRV_MSG_CODE_PULSE                          0x06000000
 403 #define BCE_DRV_MSG_CODE_DIAG                           0x07000000
 404 #define BCE_DRV_MSG_CODE_SUSPEND_NO_WOL         0x09000000
 405
 406 #define BCE_DRV_MSG_DATA                                        0x00ff0000
 407 #define BCE_DRV_MSG_DATA_WAIT0                          0x00010000
 408 #define BCE_DRV_MSG_DATA_WAIT1                          0x00020000
 409 #define BCE_DRV_MSG_DATA_WAIT2                          0x00030000
 410 #define BCE_DRV_MSG_DATA_WAIT3                          0x00040000
 411
 412 #define BCE_DRV_MSG_SEQ                                         0x0000ffff
 413
 414 #define BCE_FW_MB                               0x00000008
 415 #define BCE_FW_MSG_ACK                           0x0000ffff
 416 #define BCE_FW_MSG_STATUS_MASK                   0x00ff0000
 417 #define BCE_FW_MSG_STATUS_OK                     0x00000000
 418 #define BCE_FW_MSG_STATUS_FAILURE                0x00ff0000
 419
 420 #define BCE_LINK_STATUS                 0x0000000c
 421 #define BCE_LINK_STATUS_INIT_VALUE               0xffffffff
 422 #define BCE_LINK_STATUS_LINK_UP          0x1
 423 #define BCE_LINK_STATUS_LINK_DOWN                0x0
 424 #define BCE_LINK_STATUS_SPEED_MASK               0x1e
 425 #define BCE_LINK_STATUS_AN_INCOMPLETE            (0<<1)
 426 #define BCE_LINK_STATUS_10HALF                   (1<<1)
 427 #define BCE_LINK_STATUS_10FULL                   (2<<1)
 428 #define BCE_LINK_STATUS_100HALF          (3<<1)
 429 #define BCE_LINK_STATUS_100BASE_T4               (4<<1)
 430 #define BCE_LINK_STATUS_100FULL          (5<<1)
 431 #define BCE_LINK_STATUS_1000HALF                 (6<<1)
 432 #define BCE_LINK_STATUS_1000FULL                 (7<<1)
 433 #define BCE_LINK_STATUS_2500HALF                 (8<<1)
 434 #define BCE_LINK_STATUS_2500FULL                 (9<<1)
 435 #define BCE_LINK_STATUS_AN_ENABLED               (1<<5)
 436 #define BCE_LINK_STATUS_AN_COMPLETE              (1<<6)
 437 #define BCE_LINK_STATUS_PARALLEL_DET             (1<<7)
 438 #define BCE_LINK_STATUS_RESERVED                 (1<<8)
 439 #define BCE_LINK_STATUS_PARTNER_AD_1000FULL      (1<<9)
 440 #define BCE_LINK_STATUS_PARTNER_AD_1000HALF      (1<<10)
 441 #define BCE_LINK_STATUS_PARTNER_AD_100BT4        (1<<11)
 442 #define BCE_LINK_STATUS_PARTNER_AD_100FULL       (1<<12)
 443 #define BCE_LINK_STATUS_PARTNER_AD_100HALF       (1<<13)
 444 #define BCE_LINK_STATUS_PARTNER_AD_10FULL        (1<<14)
 445 #define BCE_LINK_STATUS_PARTNER_AD_10HALF        (1<<15)
 446 #define BCE_LINK_STATUS_TX_FC_ENABLED            (1<<16)
 447 #define BCE_LINK_STATUS_RX_FC_ENABLED            (1<<17)
 448 #define BCE_LINK_STATUS_PARTNER_SYM_PAUSE_CAP    (1<<18)
 449 #define BCE_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP   (1<<19)
 450 #define BCE_LINK_STATUS_SERDES_LINK              (1<<20)
 451 #define BCE_LINK_STATUS_PARTNER_AD_2500FULL      (1<<21)
 452 #define BCE_LINK_STATUS_PARTNER_AD_2500HALF      (1<<22)
 453
 454 #define BCE_DRV_PULSE_MB                        0x00000010
 455 #define BCE_DRV_PULSE_SEQ_MASK                   0x00007fff
 456
 457 /* Indicate to the firmware not to go into the
 458  * OS absent when it is not getting driver pulse.
 459  * This is used for debugging. */
 460 #define BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE         0x00080000
 461
 462 #define BCE_DEV_INFO_SIGNATURE                  0x00000020
 463 #define BCE_DEV_INFO_SIGNATURE_MAGIC             0x44564900
 464 #define BCE_DEV_INFO_SIGNATURE_MAGIC_MASK        0xffffff00
 465 #define BCE_DEV_INFO_FEATURE_CFG_VALID           0x01
 466 #define BCE_DEV_INFO_SECONDARY_PORT              0x80
 467 #define BCE_DEV_INFO_DRV_ALWAYS_ALIVE            0x40
 468
 469 #define BCE_SHARED_HW_CFG_PART_NUM              0x00000024
 470
 471 #define BCE_SHARED_HW_CFG_POWER_DISSIPATED      0x00000034
 472 #define BCE_SHARED_HW_CFG_POWER_STATE_D3_MASK    0xff000000
 473 #define BCE_SHARED_HW_CFG_POWER_STATE_D2_MASK    0xff0000
 474 #define BCE_SHARED_HW_CFG_POWER_STATE_D1_MASK    0xff00
 475 #define BCE_SHARED_HW_CFG_POWER_STATE_D0_MASK    0xff
 476
 477 #define BCE_SHARED_HW_CFG_POWER_CONSUMED        0x00000038
 478 #define BCE_SHARED_HW_CFG_CONFIG                0x0000003c
 479 #define BCE_SHARED_HW_CFG_DESIGN_NIC             0
 480 #define BCE_SHARED_HW_CFG_DESIGN_LOM             0x1
 481 #define BCE_SHARED_HW_CFG_PHY_COPPER             0
 482 #define BCE_SHARED_HW_CFG_PHY_FIBER              0x2
 483 #define BCE_SHARED_HW_CFG_PHY_2_5G               0x20
 484 #define BCE_SHARED_HW_CFG_PHY_BACKPLANE  0x40
 485 #define BCE_SHARED_HW_CFG_LED_MODE_SHIFT_BITS    8
 486 #define BCE_SHARED_HW_CFG_LED_MODE_MASK  0x300
 487 #define BCE_SHARED_HW_CFG_LED_MODE_MAC           0
 488 #define BCE_SHARED_HW_CFG_LED_MODE_GPHY1         0x100
 489 #define BCE_SHARED_HW_CFG_LED_MODE_GPHY2         0x200
 490
 491 #define BCE_SHARED_HW_CFG_CONFIG2               0x00000040
 492 #define BCE_SHARED_HW_CFG2_NVM_SIZE_MASK         0x00fff000
 493
 494 #define BCE_DEV_INFO_BC_REV                     0x0000004c
 495
 496 #define BCE_PORT_HW_CFG_MAC_UPPER               0x00000050
 497 #define BCE_PORT_HW_CFG_UPPERMAC_MASK            0xffff
 498
 499 #define BCE_PORT_HW_CFG_MAC_LOWER               0x00000054
 500 #define BCE_PORT_HW_CFG_CONFIG                  0x00000058
 501 #define BCE_PORT_HW_CFG_CFG_TXCTL3_MASK  0x0000ffff
 502 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_MASK       0x001f0000
 503 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_AN         0x00000000
 504 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_1G         0x00030000
 505 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_2_5G       0x00040000
 506
 507 #define BCE_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068
 508 #define BCE_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c
 509 #define BCE_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070
 510 #define BCE_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074
 511 #define BCE_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078
 512 #define BCE_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c
 513
 514 #define BCE_DEV_INFO_PER_PORT_HW_CONFIG2        0x000000b4
 515
 516 #define BCE_DEV_INFO_FORMAT_REV         0x000000c4
 517 #define BCE_DEV_INFO_FORMAT_REV_MASK             0xff000000
 518 #define BCE_DEV_INFO_FORMAT_REV_ID               ('A' << 24)
 519
 520 #define BCE_SHARED_FEATURE                      0x000000c8
 521 #define BCE_SHARED_FEATURE_MASK          0xffffffff
 522
 523 #define BCE_PORT_FEATURE                        0x000000d8
 524 #define BCE_PORT2_FEATURE                       0x00000014c
 525 #define BCE_PORT_FEATURE_WOL_ENABLED             0x01000000
 526 #define BCE_PORT_FEATURE_MBA_ENABLED             0x02000000
 527 #define BCE_PORT_FEATURE_ASF_ENABLED             0x04000000
 528 #define BCE_PORT_FEATURE_IMD_ENABLED             0x08000000
 529 #define BCE_PORT_FEATURE_BAR1_SIZE_MASK  0xf
 530 #define BCE_PORT_FEATURE_BAR1_SIZE_DISABLED      0x0
 531 #define BCE_PORT_FEATURE_BAR1_SIZE_64K           0x1
 532 #define BCE_PORT_FEATURE_BAR1_SIZE_128K  0x2
 533 #define BCE_PORT_FEATURE_BAR1_SIZE_256K  0x3
 534 #define BCE_PORT_FEATURE_BAR1_SIZE_512K  0x4
 535 #define BCE_PORT_FEATURE_BAR1_SIZE_1M            0x5
 536 #define BCE_PORT_FEATURE_BAR1_SIZE_2M            0x6
 537 #define BCE_PORT_FEATURE_BAR1_SIZE_4M            0x7
 538 #define BCE_PORT_FEATURE_BAR1_SIZE_8M            0x8
 539 #define BCE_PORT_FEATURE_BAR1_SIZE_16M           0x9
 540 #define BCE_PORT_FEATURE_BAR1_SIZE_32M           0xa
 541 #define BCE_PORT_FEATURE_BAR1_SIZE_64M           0xb
 542 #define BCE_PORT_FEATURE_BAR1_SIZE_128M  0xc
 543 #define BCE_PORT_FEATURE_BAR1_SIZE_256M  0xd
 544 #define BCE_PORT_FEATURE_BAR1_SIZE_512M  0xe
 545 #define BCE_PORT_FEATURE_BAR1_SIZE_1G            0xf
 546
 547 #define BCE_PORT_FEATURE_WOL                    0xdc
 548 #define BCE_PORT2_FEATURE_WOL                   0x150
 549 #define BCE_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS  4
 550 #define BCE_PORT_FEATURE_WOL_DEFAULT_MASK        0x30
 551 #define BCE_PORT_FEATURE_WOL_DEFAULT_DISABLE     0
 552 #define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC       0x10
 553 #define BCE_PORT_FEATURE_WOL_DEFAULT_ACPI        0x20
 554 #define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI      0x30
 555 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_MASK     0xf
 556 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG  0
 557 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_10HALF   1
 558 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_10FULL   2
 559 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3
 560 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4
 561 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000HALF         5
 562 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000FULL         6
 563 #define BCE_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000      0x40
 564 #define BCE_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400
 565 #define BCE_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP     0x800
 566
 567 #define BCE_PORT_FEATURE_MBA                    0xe0
 568 #define BCE_PORT2_FEATURE_MBA                   0x154
 569 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS  0
 570 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK        0x3
 571 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE         0
 572 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL         1
 573 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP       2
 574 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS       2
 575 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_MASK     0x3c
 576 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG  0
 577 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_10HALF   0x4
 578 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_10FULL   0x8
 579 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_100HALF  0xc
 580 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_100FULL  0x10
 581 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000HALF         0x14
 582 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000FULL         0x18
 583 #define BCE_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE         0x40
 584 #define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_S       0
 585 #define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_B       0x80
 586 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS     8
 587 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK   0xff00
 588 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED       0
 589 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K     0x100
 590 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K     0x200
 591 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K     0x300
 592 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K     0x400
 593 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K    0x500
 594 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K    0x600
 595 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K    0x700
 596 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K   0x800
 597 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K   0x900
 598 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K   0xa00
 599 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M     0xb00
 600 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M     0xc00
 601 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M     0xd00
 602 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M     0xe00
 603 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M    0xf00
 604 #define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS      16
 605 #define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK    0xf0000
 606 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS   20
 607 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK         0x300000
 608 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO         0
 609 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS  0x100000
 610 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H       0x200000
 611 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H       0x300000
 612
 613 #define BCE_PORT_FEATURE_IMD                    0xe4
 614 #define BCE_PORT2_FEATURE_IMD                   0x158
 615 #define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT       0
 616 #define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE        1
 617
 618 #define BCE_PORT_FEATURE_VLAN                   0xe8
 619 #define BCE_PORT2_FEATURE_VLAN                  0x15c
 620 #define BCE_PORT_FEATURE_MBA_VLAN_TAG_MASK       0xffff
 621 #define BCE_PORT_FEATURE_MBA_VLAN_ENABLE         0x10000
 622
 623 #define BCE_BC_STATE_RESET_TYPE         0x000001c0
 624 #define BCE_BC_STATE_RESET_TYPE_SIG              0x00005254
 625 #define BCE_BC_STATE_RESET_TYPE_SIG_MASK         0x0000ffff
 626 #define BCE_BC_STATE_RESET_TYPE_NONE     (BCE_BC_STATE_RESET_TYPE_SIG | \
 627                                           0x00010000)
 628 #define BCE_BC_STATE_RESET_TYPE_PCI      (BCE_BC_STATE_RESET_TYPE_SIG | \
 629                                           0x00020000)
 630 #define BCE_BC_STATE_RESET_TYPE_VAUX     (BCE_BC_STATE_RESET_TYPE_SIG | \
 631                                           0x00030000)
 632 #define BCE_BC_STATE_RESET_TYPE_DRV_MASK         DRV_MSG_CODE
 633 #define BCE_BC_STATE_RESET_TYPE_DRV_RESET (BCE_BC_STATE_RESET_TYPE_SIG | \
 634                                             DRV_MSG_CODE_RESET)
 635 #define BCE_BC_STATE_RESET_TYPE_DRV_UNLOAD (BCE_BC_STATE_RESET_TYPE_SIG | \
 636                                              DRV_MSG_CODE_UNLOAD)
 637 #define BCE_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BCE_BC_STATE_RESET_TYPE_SIG | \
 638                                                DRV_MSG_CODE_SHUTDOWN)
 639 #define BCE_BC_STATE_RESET_TYPE_DRV_WOL (BCE_BC_STATE_RESET_TYPE_SIG | \
 640                                           DRV_MSG_CODE_WOL)
 641 #define BCE_BC_STATE_RESET_TYPE_DRV_DIAG (BCE_BC_STATE_RESET_TYPE_SIG | \
 642                                            DRV_MSG_CODE_DIAG)
 643 #define BCE_BC_STATE_RESET_TYPE_VALUE(msg) (BCE_BC_STATE_RESET_TYPE_SIG | \
 644                                              (msg))
 645
 646 #define BCE_BC_STATE                            0x000001c4
 647 #define BCE_BC_STATE_ERR_MASK                    0x0000ff00
 648 #define BCE_BC_STATE_SIGN                        0x42530000
 649 #define BCE_BC_STATE_SIGN_MASK                   0xffff0000
 650 #define BCE_BC_STATE_BC1_START                   (BCE_BC_STATE_SIGN | 0x1)
 651 #define BCE_BC_STATE_GET_NVM_CFG1                (BCE_BC_STATE_SIGN | 0x2)
 652 #define BCE_BC_STATE_PROG_BAR                    (BCE_BC_STATE_SIGN | 0x3)
 653 #define BCE_BC_STATE_INIT_VID                    (BCE_BC_STATE_SIGN | 0x4)
 654 #define BCE_BC_STATE_GET_NVM_CFG2                (BCE_BC_STATE_SIGN | 0x5)
 655 #define BCE_BC_STATE_APPLY_WKARND                (BCE_BC_STATE_SIGN | 0x6)
 656 #define BCE_BC_STATE_LOAD_BC2                    (BCE_BC_STATE_SIGN | 0x7)
 657 #define BCE_BC_STATE_GOING_BC2                   (BCE_BC_STATE_SIGN | 0x8)
 658 #define BCE_BC_STATE_GOING_DIAG          (BCE_BC_STATE_SIGN | 0x9)
 659 #define BCE_BC_STATE_RT_FINAL_INIT               (BCE_BC_STATE_SIGN | 0x81)
 660 #define BCE_BC_STATE_RT_WKARND                   (BCE_BC_STATE_SIGN | 0x82)
 661 #define BCE_BC_STATE_RT_DRV_PULSE                (BCE_BC_STATE_SIGN | 0x83)
 662 #define BCE_BC_STATE_RT_FIOEVTS          (BCE_BC_STATE_SIGN | 0x84)
 663 #define BCE_BC_STATE_RT_DRV_CMD          (BCE_BC_STATE_SIGN | 0x85)
 664 #define BCE_BC_STATE_RT_LOW_POWER                (BCE_BC_STATE_SIGN | 0x86)
 665 #define BCE_BC_STATE_RT_SET_WOL          (BCE_BC_STATE_SIGN | 0x87)
 666 #define BCE_BC_STATE_RT_OTHER_FW                 (BCE_BC_STATE_SIGN | 0x88)
 667 #define BCE_BC_STATE_RT_GOING_D3                 (BCE_BC_STATE_SIGN | 0x89)
 668 #define BCE_BC_STATE_ERR_BAD_VERSION             (BCE_BC_STATE_SIGN | 0x0100)
 669 #define BCE_BC_STATE_ERR_BAD_BC2_CRC             (BCE_BC_STATE_SIGN | 0x0200)
 670 #define BCE_BC_STATE_ERR_BC1_LOOP                (BCE_BC_STATE_SIGN | 0x0300)
 671 #define BCE_BC_STATE_ERR_UNKNOWN_CMD             (BCE_BC_STATE_SIGN | 0x0400)
 672 #define BCE_BC_STATE_ERR_DRV_DEAD                (BCE_BC_STATE_SIGN | 0x0500)
 673 #define BCE_BC_STATE_ERR_NO_RXP          (BCE_BC_STATE_SIGN | 0x0600)
 674 #define BCE_BC_STATE_ERR_TOO_MANY_RBUF           (BCE_BC_STATE_SIGN | 0x0700)
 675
 676 #define BCE_BC_STATE_DEBUG_CMD                  0x1dc
 677 #define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE        0x42440000
 678 #define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK   0xffff0000
 679 #define BCE_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK    0xffff
 680 #define BCE_BC_STATE_BC_DBG_CMD_LOOP_INFINITE    0xffff
 681
 682 #define HOST_VIEW_SHMEM_BASE                    0x167c00
 683
 684 /*
 685  * PCI registers defined in the PCI 2.2 spec.
 686  */
 687 #define BCE_PCI_PCIX_CMD                0x42
 688
 689
 690 /****************************************************************************/
 691 /* Convenience definitions.                                                 */
 692 /****************************************************************************/
 693 #define BCE_PRINTF(sc, fmt, args...)    device_printf(sc->bce_dev, fmt, ##args)
 694
 695 #define BCE_LOCK_INIT(_sc, _name)       mtx_init(&(_sc)->bce_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
 696 #define BCE_LOCK(_sc)                           mtx_lock(&(_sc)->bce_mtx)
 697 #define BCE_LOCK_ASSERT(_sc)            mtx_assert(&(_sc)->bce_mtx, MA_OWNED)
 698 #define BCE_UNLOCK(_sc)                         mtx_unlock(&(_sc)->bce_mtx)
 699 #define BCE_LOCK_DESTROY(_sc)           mtx_destroy(&(_sc)->bce_mtx)
 700
 701 #define REG_WR(sc, reg, val)            bus_space_write_4(sc->bce_btag, sc->bce_bhandle, reg, val)
 702 #define REG_WR16(sc, reg, val)          bus_space_write_2(sc->bce_btag, sc->bce_bhandle, reg, val)
 703 #define REG_RD(sc, reg)                         bus_space_read_4(sc->bce_btag, sc->bce_bhandle, reg)
 704 #define REG_RD_IND(sc, offset)          bce_reg_rd_ind(sc, offset)
 705 #define REG_WR_IND(sc, offset, val)     bce_reg_wr_ind(sc, offset, val)
 706 #define CTX_WR(sc, cid_addr, offset, val)       bce_ctx_wr(sc, cid_addr, offset, val)
 707 #define BCE_SETBIT(sc, reg, x)          REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))
 708 #define BCE_CLRBIT(sc, reg, x)          REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))
 709 #define PCI_SETBIT(dev, reg, x, s)      pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
 710 #define PCI_CLRBIT(dev, reg, x, s)      pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
 711
 712 #define BCE_STATS(x)                    (u_long) stats->stat_ ## x ## _lo
 713 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
 714 #define BCE_ADDR_LO(y)                  ((u64) (y) & 0xFFFFFFFF)
 715 #define BCE_ADDR_HI(y)                  ((u64) (y) >> 32)
 716 #else
 717 #define BCE_ADDR_LO(y)                  ((u32)y)
 718 #define BCE_ADDR_HI(y)                  (0)
 719 #endif
 720
 721
 722 /*
 723  * The following data structures are generated from RTL code.
 724  * Do not modify any values below this line.
 725  */
 726
 727 /****************************************************************************/
 728 /* Do not modify any of the following data structures, they are generated   */
 729 /* from RTL code.                                                           */
 730 /*                                                                          */
 731 /* Begin machine generated definitions.                                     */
 732 /****************************************************************************/
 733
 734 /*
 735  *  tx_bd definition
 736  */
 737 struct tx_bd {
 738         u32 tx_bd_haddr_hi;
 739         u32 tx_bd_haddr_lo;
 740         u32 tx_bd_mss_nbytes;
 741         u32 tx_bd_vlan_tag_flags;
 742                 #define TX_BD_FLAGS_CONN_FAULT          (1<<0)
 743                 #define TX_BD_FLAGS_TCP_UDP_CKSUM       (1<<1)
 744                 #define TX_BD_FLAGS_IP_CKSUM            (1<<2)
 745                 #define TX_BD_FLAGS_VLAN_TAG            (1<<3)
 746                 #define TX_BD_FLAGS_COAL_NOW            (1<<4)
 747                 #define TX_BD_FLAGS_DONT_GEN_CRC        (1<<5)
 748                 #define TX_BD_FLAGS_END                 (1<<6)
 749                 #define TX_BD_FLAGS_START               (1<<7)
 750                 #define TX_BD_FLAGS_SW_OPTION_WORD      (0x1f<<8)
 751                 #define TX_BD_FLAGS_SW_FLAGS            (1<<13)
 752                 #define TX_BD_FLAGS_SW_SNAP             (1<<14)
 753                 #define TX_BD_FLAGS_SW_LSO              (1<<15)
 754
 755 };
 756
 757
 758 /*
 759  *  rx_bd definition
 760  */
 761 struct rx_bd {
 762         u32 rx_bd_haddr_hi;
 763         u32 rx_bd_haddr_lo;
 764         u32 rx_bd_len;
 765         u32 rx_bd_flags;
 766                 #define RX_BD_FLAGS_NOPUSH              (1<<0)
 767                 #define RX_BD_FLAGS_DUMMY               (1<<1)
 768                 #define RX_BD_FLAGS_END                 (1<<2)
 769                 #define RX_BD_FLAGS_START               (1<<3)
 770
 771 };
 772
 773
 774 /*
 775  *  status_block definition
 776  */
 777 struct status_block {
 778         u32 status_attn_bits;
 779                 #define STATUS_ATTN_BITS_LINK_STATE             (1L<<0)
 780                 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT     (1L<<1)
 781                 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT       (1L<<2)
 782                 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT      (1L<<3)
 783                 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT     (1L<<4)
 784                 #define STATUS_ATTN_BITS_TX_DMA_ABORT           (1L<<5)
 785                 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT       (1L<<6)
 786                 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT     (1L<<7)
 787                 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT    (1L<<8)
 788                 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT        (1L<<9)
 789                 #define STATUS_ATTN_BITS_RX_MBUF_ABORT          (1L<<10)
 790                 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT        (1L<<11)
 791                 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT     (1L<<12)
 792                 #define STATUS_ATTN_BITS_RX_V2P_ABORT           (1L<<13)
 793                 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT      (1L<<14)
 794                 #define STATUS_ATTN_BITS_RX_DMA_ABORT           (1L<<15)
 795                 #define STATUS_ATTN_BITS_COMPLETION_ABORT       (1L<<16)
 796                 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT    (1L<<17)
 797                 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT    (1L<<18)
 798                 #define STATUS_ATTN_BITS_CONTEXT_ABORT          (1L<<19)
 799                 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT    (1L<<20)
 800                 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT    (1L<<21)
 801                 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT   (1L<<22)
 802                 #define STATUS_ATTN_BITS_MAC_ABORT              (1L<<23)
 803                 #define STATUS_ATTN_BITS_TIMER_ABORT            (1L<<24)
 804                 #define STATUS_ATTN_BITS_DMAE_ABORT             (1L<<25)
 805                 #define STATUS_ATTN_BITS_FLSH_ABORT             (1L<<26)
 806                 #define STATUS_ATTN_BITS_GRC_ABORT              (1L<<27)
 807                 #define STATUS_ATTN_BITS_PARITY_ERROR           (1L<<31)
 808
 809         u32 status_attn_bits_ack;
 810 #if defined(__BIG_ENDIAN)
 811         u16 status_tx_quick_consumer_index0;
 812         u16 status_tx_quick_consumer_index1;
 813         u16 status_tx_quick_consumer_index2;
 814         u16 status_tx_quick_consumer_index3;
 815         u16 status_rx_quick_consumer_index0;
 816         u16 status_rx_quick_consumer_index1;
 817         u16 status_rx_quick_consumer_index2;
 818         u16 status_rx_quick_consumer_index3;
 819         u16 status_rx_quick_consumer_index4;
 820         u16 status_rx_quick_consumer_index5;
 821         u16 status_rx_quick_consumer_index6;
 822         u16 status_rx_quick_consumer_index7;
 823         u16 status_rx_quick_consumer_index8;
 824         u16 status_rx_quick_consumer_index9;
 825         u16 status_rx_quick_consumer_index10;
 826         u16 status_rx_quick_consumer_index11;
 827         u16 status_rx_quick_consumer_index12;
 828         u16 status_rx_quick_consumer_index13;
 829         u16 status_rx_quick_consumer_index14;
 830         u16 status_rx_quick_consumer_index15;
 831         u16 status_completion_producer_index;
 832         u16 status_cmd_consumer_index;
 833         u16 status_idx;
 834         u16 status_unused;
 835 #elif defined(__LITTLE_ENDIAN)
 836         u16 status_tx_quick_consumer_index1;
 837         u16 status_tx_quick_consumer_index0;
 838         u16 status_tx_quick_consumer_index3;
 839         u16 status_tx_quick_consumer_index2;
 840         u16 status_rx_quick_consumer_index1;
 841         u16 status_rx_quick_consumer_index0;
 842         u16 status_rx_quick_consumer_index3;
 843         u16 status_rx_quick_consumer_index2;
 844         u16 status_rx_quick_consumer_index5;
 845         u16 status_rx_quick_consumer_index4;
 846         u16 status_rx_quick_consumer_index7;
 847         u16 status_rx_quick_consumer_index6;
 848         u16 status_rx_quick_consumer_index9;
 849         u16 status_rx_quick_consumer_index8;
 850         u16 status_rx_quick_consumer_index11;
 851         u16 status_rx_quick_consumer_index10;
 852         u16 status_rx_quick_consumer_index13;
 853         u16 status_rx_quick_consumer_index12;
 854         u16 status_rx_quick_consumer_index15;
 855         u16 status_rx_quick_consumer_index14;
 856         u16 status_cmd_consumer_index;
 857         u16 status_completion_producer_index;
 858         u16 status_unused;
 859         u16 status_idx;
 860 #endif
 861 };
 862
 863
 864 /*
 865  *  statistics_block definition
 866  */
 867 struct statistics_block {
 868         u32 stat_IfHCInOctets_hi;
 869         u32 stat_IfHCInOctets_lo;
 870         u32 stat_IfHCInBadOctets_hi;
 871         u32 stat_IfHCInBadOctets_lo;
 872         u32 stat_IfHCOutOctets_hi;
 873         u32 stat_IfHCOutOctets_lo;
 874         u32 stat_IfHCOutBadOctets_hi;
 875         u32 stat_IfHCOutBadOctets_lo;
 876         u32 stat_IfHCInUcastPkts_hi;
 877         u32 stat_IfHCInUcastPkts_lo;
 878         u32 stat_IfHCInMulticastPkts_hi;
 879         u32 stat_IfHCInMulticastPkts_lo;
 880         u32 stat_IfHCInBroadcastPkts_hi;
 881         u32 stat_IfHCInBroadcastPkts_lo;
 882         u32 stat_IfHCOutUcastPkts_hi;
 883         u32 stat_IfHCOutUcastPkts_lo;
 884         u32 stat_IfHCOutMulticastPkts_hi;
 885         u32 stat_IfHCOutMulticastPkts_lo;
 886         u32 stat_IfHCOutBroadcastPkts_hi;
 887         u32 stat_IfHCOutBroadcastPkts_lo;
 888         u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
 889         u32 stat_Dot3StatsCarrierSenseErrors;
 890         u32 stat_Dot3StatsFCSErrors;
 891         u32 stat_Dot3StatsAlignmentErrors;
 892         u32 stat_Dot3StatsSingleCollisionFrames;
 893         u32 stat_Dot3StatsMultipleCollisionFrames;
 894         u32 stat_Dot3StatsDeferredTransmissions;
 895         u32 stat_Dot3StatsExcessiveCollisions;
 896         u32 stat_Dot3StatsLateCollisions;
 897         u32 stat_EtherStatsCollisions;
 898         u32 stat_EtherStatsFragments;
 899         u32 stat_EtherStatsJabbers;
 900         u32 stat_EtherStatsUndersizePkts;
 901         u32 stat_EtherStatsOverrsizePkts;
 902         u32 stat_EtherStatsPktsRx64Octets;
 903         u32 stat_EtherStatsPktsRx65Octetsto127Octets;
 904         u32 stat_EtherStatsPktsRx128Octetsto255Octets;
 905         u32 stat_EtherStatsPktsRx256Octetsto511Octets;
 906         u32 stat_EtherStatsPktsRx512Octetsto1023Octets;
 907         u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;
 908         u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;
 909         u32 stat_EtherStatsPktsTx64Octets;
 910         u32 stat_EtherStatsPktsTx65Octetsto127Octets;
 911         u32 stat_EtherStatsPktsTx128Octetsto255Octets;
 912         u32 stat_EtherStatsPktsTx256Octetsto511Octets;
 913         u32 stat_EtherStatsPktsTx512Octetsto1023Octets;
 914         u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;
 915         u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;
 916         u32 stat_XonPauseFramesReceived;
 917         u32 stat_XoffPauseFramesReceived;
 918         u32 stat_OutXonSent;
 919         u32 stat_OutXoffSent;
 920         u32 stat_FlowControlDone;
 921         u32 stat_MacControlFramesReceived;
 922         u32 stat_XoffStateEntered;
 923         u32 stat_IfInFramesL2FilterDiscards;
 924         u32 stat_IfInRuleCheckerDiscards;
 925         u32 stat_IfInFTQDiscards;
 926         u32 stat_IfInMBUFDiscards;
 927         u32 stat_IfInRuleCheckerP4Hit;
 928         u32 stat_CatchupInRuleCheckerDiscards;
 929         u32 stat_CatchupInFTQDiscards;
 930         u32 stat_CatchupInMBUFDiscards;
 931         u32 stat_CatchupInRuleCheckerP4Hit;
 932         u32 stat_GenStat00;
 933         u32 stat_GenStat01;
 934         u32 stat_GenStat02;
 935         u32 stat_GenStat03;
 936         u32 stat_GenStat04;
 937         u32 stat_GenStat05;
 938         u32 stat_GenStat06;
 939         u32 stat_GenStat07;
 940         u32 stat_GenStat08;
 941         u32 stat_GenStat09;
 942         u32 stat_GenStat10;
 943         u32 stat_GenStat11;
 944         u32 stat_GenStat12;
 945         u32 stat_GenStat13;
 946         u32 stat_GenStat14;
 947         u32 stat_GenStat15;
 948 };
 949
 950
 951 /*
 952  *  l2_fhdr definition
 953  */
 954 struct l2_fhdr {
 955         u32 l2_fhdr_status;
 956                 #define L2_FHDR_STATUS_RULE_CLASS       (0x7<<0)
 957                 #define L2_FHDR_STATUS_RULE_P2          (1<<3)
 958                 #define L2_FHDR_STATUS_RULE_P3          (1<<4)
 959                 #define L2_FHDR_STATUS_RULE_P4          (1<<5)
 960                 #define L2_FHDR_STATUS_L2_VLAN_TAG      (1<<6)
 961                 #define L2_FHDR_STATUS_L2_LLC_SNAP      (1<<7)
 962                 #define L2_FHDR_STATUS_RSS_HASH         (1<<8)
 963                 #define L2_FHDR_STATUS_IP_DATAGRAM      (1<<13)
 964                 #define L2_FHDR_STATUS_TCP_SEGMENT      (1<<14)
 965                 #define L2_FHDR_STATUS_UDP_DATAGRAM     (1<<15)
 966
 967                 #define L2_FHDR_ERRORS_BAD_CRC          (1<<17)
 968                 #define L2_FHDR_ERRORS_PHY_DECODE       (1<<18)
 969                 #define L2_FHDR_ERRORS_ALIGNMENT        (1<<19)
 970                 #define L2_FHDR_ERRORS_TOO_SHORT        (1<<20)
 971                 #define L2_FHDR_ERRORS_GIANT_FRAME      (1<<21)
 972                 #define L2_FHDR_ERRORS_TCP_XSUM         (1<<28)
 973                 #define L2_FHDR_ERRORS_UDP_XSUM         (1<<31)
 974
 975         u32 l2_fhdr_hash;
 976 #if defined(__BIG_ENDIAN)
 977         u16 l2_fhdr_pkt_len;
 978         u16 l2_fhdr_vlan_tag;
 979         u16 l2_fhdr_ip_xsum;
 980         u16 l2_fhdr_tcp_udp_xsum;
 981 #elif defined(__LITTLE_ENDIAN)
 982         u16 l2_fhdr_vlan_tag;
 983         u16 l2_fhdr_pkt_len;
 984         u16 l2_fhdr_tcp_udp_xsum;
 985         u16 l2_fhdr_ip_xsum;
 986 #endif
 987 };
 988
 989
 990 /*
 991  *  l2_context definition
 992  */
 993 #define BCE_L2CTX_TYPE                                  0x00000000
 994 #define BCE_L2CTX_TYPE_SIZE_L2                           ((0xc0/0x20)<<16)
 995 #define BCE_L2CTX_TYPE_TYPE                              (0xf<<28)
 996 #define BCE_L2CTX_TYPE_TYPE_EMPTY                        (0<<28)
 997 #define BCE_L2CTX_TYPE_TYPE_L2                           (1<<28)
 998
 999 #define BCE_L2CTX_TX_HOST_BIDX                          0x00000088
1000 #define BCE_L2CTX_EST_NBD                               0x00000088
1001 #define BCE_L2CTX_CMD_TYPE                              0x00000088
1002 #define BCE_L2CTX_CMD_TYPE_TYPE                  (0xf<<24)
1003 #define BCE_L2CTX_CMD_TYPE_TYPE_L2                       (0<<24)
1004 #define BCE_L2CTX_CMD_TYPE_TYPE_TCP                      (1<<24)
1005
1006 #define BCE_L2CTX_TX_HOST_BSEQ                          0x00000090
1007 #define BCE_L2CTX_TSCH_BSEQ                             0x00000094
1008 #define BCE_L2CTX_TBDR_BSEQ                             0x00000098
1009 #define BCE_L2CTX_TBDR_BOFF                             0x0000009c
1010 #define BCE_L2CTX_TBDR_BIDX                             0x0000009c
1011 #define BCE_L2CTX_TBDR_BHADDR_HI                        0x000000a0
1012 #define BCE_L2CTX_TBDR_BHADDR_LO                        0x000000a4
1013 #define BCE_L2CTX_TXP_BOFF                              0x000000a8
1014 #define BCE_L2CTX_TXP_BIDX                              0x000000a8
1015 #define BCE_L2CTX_TXP_BSEQ                              0x000000ac
1016
1017
1018 /*
1019  *  l2_bd_chain_context definition
1020  */
1021 #define BCE_L2CTX_BD_PRE_READ                           0x00000000
1022 #define BCE_L2CTX_CTX_SIZE                              0x00000000
1023 #define BCE_L2CTX_CTX_TYPE                              0x00000000
1024 #define BCE_L2CTX_CTX_TYPE_SIZE_L2                       ((0x20/20)<<16)
1025 #define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE               (0xf<<28)
1026 #define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED     (0<<28)
1027 #define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE         (1<<28)
1028
1029 #define BCE_L2CTX_HOST_BDIDX                            0x00000004
1030 #define BCE_L2CTX_HOST_BSEQ                             0x00000008
1031 #define BCE_L2CTX_NX_BSEQ                               0x0000000c
1032 #define BCE_L2CTX_NX_BDHADDR_HI                 0x00000010
1033 #define BCE_L2CTX_NX_BDHADDR_LO                 0x00000014
1034 #define BCE_L2CTX_NX_BDIDX                              0x00000018
1035
1036
1037 /*
1038  *  pci_config_l definition
1039  *  offset: 0000
1040  */
1041 #define BCE_PCICFG_MISC_CONFIG                                                  0x00000068
1042 #define BCE_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP                 (1L<<2)
1043 #define BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP       (1L<<3)
1044 #define BCE_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA             (1L<<5)
1045 #define BCE_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP      (1L<<6)
1046 #define BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA            (1L<<7)
1047 #define BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ              (1L<<8)
1048 #define BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY              (1L<<9)
1049 #define BCE_PCICFG_MISC_CONFIG_ASIC_METAL_REV            (0xffL<<16)
1050 #define BCE_PCICFG_MISC_CONFIG_ASIC_BASE_REV             (0xfL<<24)
1051 #define BCE_PCICFG_MISC_CONFIG_ASIC_ID                   (0xfL<<28)
1052 #define BCE_PCICFG_MISC_CONFIG_ASIC_REV                  (0xffffL<<16)
1053
1054 #define BCE_PCICFG_MISC_STATUS                          0x0000006c
1055 #define BCE_PCICFG_MISC_STATUS_INTA_VALUE                (1L<<0)
1056 #define BCE_PCICFG_MISC_STATUS_32BIT_DET                 (1L<<1)
1057 #define BCE_PCICFG_MISC_STATUS_M66EN                     (1L<<2)
1058 #define BCE_PCICFG_MISC_STATUS_PCIX_DET          (1L<<3)
1059 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED                (0x3L<<4)
1060 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_66             (0L<<4)
1061 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_100            (1L<<4)
1062 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_133            (2L<<4)
1063 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE       (3L<<4)
1064
1065 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS               0x00000070
1066 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET        (0xfL<<0)
1067 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ  (0L<<0)
1068 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ  (1L<<0)
1069 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ  (2L<<0)
1070 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ  (3L<<0)
1071 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ  (4L<<0)
1072 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ  (5L<<0)
1073 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ  (6L<<0)
1074 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ         (7L<<0)
1075 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW    (0xfL<<0)
1076 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE       (1L<<6)
1077 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT   (1L<<7)
1078 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC       (0x7L<<8)
1079 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF         (0L<<8)
1080 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12    (1L<<8)
1081 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6     (2L<<8)
1082 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62    (4L<<8)
1083 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD      (1L<<11)
1084 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED     (0xfL<<12)
1085 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100         (0L<<12)
1086 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80  (1L<<12)
1087 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50  (2L<<12)
1088 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40  (4L<<12)
1089 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25  (8L<<12)
1090 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP      (1L<<16)
1091 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP   (1L<<17)
1092 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18    (1L<<18)
1093 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET    (1L<<19)
1094 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED       (0xfffL<<20)
1095
1096 #define BCE_PCICFG_REG_WINDOW_ADDRESS                   0x00000078
1097 #define BCE_PCICFG_REG_WINDOW                           0x00000080
1098 #define BCE_PCICFG_INT_ACK_CMD                          0x00000084
1099 #define BCE_PCICFG_INT_ACK_CMD_INDEX                     (0xffffL<<0)
1100 #define BCE_PCICFG_INT_ACK_CMD_INDEX_VALID               (1L<<16)
1101 #define BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM  (1L<<17)
1102 #define BCE_PCICFG_INT_ACK_CMD_MASK_INT          (1L<<18)
1103
1104 #define BCE_PCICFG_STATUS_BIT_SET_CMD                   0x00000088
1105 #define BCE_PCICFG_STATUS_BIT_CLEAR_CMD         0x0000008c
1106 #define BCE_PCICFG_MAILBOX_QUEUE_ADDR                   0x00000090
1107 #define BCE_PCICFG_MAILBOX_QUEUE_DATA                   0x00000094
1108
1109
1110 /*
1111  *  pci_reg definition
1112  *  offset: 0x400
1113  */
1114 #define BCE_PCI_GRC_WINDOW_ADDR                 0x00000400
1115 #define BCE_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE        (0x3ffffL<<8)
1116
1117 #define BCE_PCI_CONFIG_1                                0x00000404
1118 #define BCE_PCI_CONFIG_1_READ_BOUNDARY                   (0x7L<<8)
1119 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_OFF               (0L<<8)
1120 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_16                (1L<<8)
1121 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_32                (2L<<8)
1122 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_64                (3L<<8)
1123 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_128               (4L<<8)
1124 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_256               (5L<<8)
1125 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_512               (6L<<8)
1126 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_1024              (7L<<8)
1127 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY          (0x7L<<11)
1128 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_OFF              (0L<<11)
1129 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_16               (1L<<11)
1130 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_32               (2L<<11)
1131 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_64               (3L<<11)
1132 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_128              (4L<<11)
1133 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_256              (5L<<11)
1134 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_512              (6L<<11)
1135 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_1024             (7L<<11)
1136
1137 #define BCE_PCI_CONFIG_2                                0x00000408
1138 #define BCE_PCI_CONFIG_2_BAR1_SIZE                       (0xfL<<0)
1139 #define BCE_PCI_CONFIG_2_BAR1_SIZE_DISABLED              (0L<<0)
1140 #define BCE_PCI_CONFIG_2_BAR1_SIZE_64K                   (1L<<0)
1141 #define BCE_PCI_CONFIG_2_BAR1_SIZE_128K          (2L<<0)
1142 #define BCE_PCI_CONFIG_2_BAR1_SIZE_256K          (3L<<0)
1143 #define BCE_PCI_CONFIG_2_BAR1_SIZE_512K          (4L<<0)
1144 #define BCE_PCI_CONFIG_2_BAR1_SIZE_1M                    (5L<<0)
1145 #define BCE_PCI_CONFIG_2_BAR1_SIZE_2M                    (6L<<0)
1146 #define BCE_PCI_CONFIG_2_BAR1_SIZE_4M                    (7L<<0)
1147 #define BCE_PCI_CONFIG_2_BAR1_SIZE_8M                    (8L<<0)
1148 #define BCE_PCI_CONFIG_2_BAR1_SIZE_16M                   (9L<<0)
1149 #define BCE_PCI_CONFIG_2_BAR1_SIZE_32M                   (10L<<0)
1150 #define BCE_PCI_CONFIG_2_BAR1_SIZE_64M                   (11L<<0)
1151 #define BCE_PCI_CONFIG_2_BAR1_SIZE_128M          (12L<<0)
1152 #define BCE_PCI_CONFIG_2_BAR1_SIZE_256M          (13L<<0)
1153 #define BCE_PCI_CONFIG_2_BAR1_SIZE_512M          (14L<<0)
1154 #define BCE_PCI_CONFIG_2_BAR1_SIZE_1G                    (15L<<0)
1155 #define BCE_PCI_CONFIG_2_BAR1_64ENA                      (1L<<4)
1156 #define BCE_PCI_CONFIG_2_EXP_ROM_RETRY                   (1L<<5)
1157 #define BCE_PCI_CONFIG_2_CFG_CYCLE_RETRY                 (1L<<6)
1158 #define BCE_PCI_CONFIG_2_FIRST_CFG_DONE          (1L<<7)
1159 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE                    (0xffL<<8)
1160 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED           (0L<<8)
1161 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1K                 (1L<<8)
1162 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2K                 (2L<<8)
1163 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4K                 (3L<<8)
1164 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8K                 (4L<<8)
1165 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16K                (5L<<8)
1166 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_32K                (6L<<8)
1167 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_64K                (7L<<8)
1168 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_128K               (8L<<8)
1169 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_256K               (9L<<8)
1170 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_512K               (10L<<8)
1171 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1M                 (11L<<8)
1172 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2M                 (12L<<8)
1173 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4M                 (13L<<8)
1174 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8M                 (14L<<8)
1175 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16M                (15L<<8)
1176 #define BCE_PCI_CONFIG_2_MAX_SPLIT_LIMIT                 (0x1fL<<16)
1177 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT          (0x3L<<21)
1178 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_512              (0L<<21)
1179 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_1K               (1L<<21)
1180 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_2K               (2L<<21)
1181 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_4K               (3L<<21)
1182 #define BCE_PCI_CONFIG_2_FORCE_32_BIT_MSTR               (1L<<23)
1183 #define BCE_PCI_CONFIG_2_FORCE_32_BIT_TGT                (1L<<24)
1184 #define BCE_PCI_CONFIG_2_KEEP_REQ_ASSERT                 (1L<<25)
1185
1186 #define BCE_PCI_CONFIG_3                                0x0000040c
1187 #define BCE_PCI_CONFIG_3_STICKY_BYTE                     (0xffL<<0)
1188 #define BCE_PCI_CONFIG_3_FORCE_PME                       (1L<<24)
1189 #define BCE_PCI_CONFIG_3_PME_STATUS                      (1L<<25)
1190 #define BCE_PCI_CONFIG_3_PME_ENABLE                      (1L<<26)
1191 #define BCE_PCI_CONFIG_3_PM_STATE                        (0x3L<<27)
1192 #define BCE_PCI_CONFIG_3_VAUX_PRESET                     (1L<<30)
1193 #define BCE_PCI_CONFIG_3_PCI_POWER                       (1L<<31)
1194
1195 #define BCE_PCI_PM_DATA_A                               0x00000410
1196 #define BCE_PCI_PM_DATA_A_PM_DATA_0_PRG          (0xffL<<0)
1197 #define BCE_PCI_PM_DATA_A_PM_DATA_1_PRG          (0xffL<<8)
1198 #define BCE_PCI_PM_DATA_A_PM_DATA_2_PRG          (0xffL<<16)
1199 #define BCE_PCI_PM_DATA_A_PM_DATA_3_PRG          (0xffL<<24)
1200
1201 #define BCE_PCI_PM_DATA_B                               0x00000414
1202 #define BCE_PCI_PM_DATA_B_PM_DATA_4_PRG          (0xffL<<0)
1203 #define BCE_PCI_PM_DATA_B_PM_DATA_5_PRG          (0xffL<<8)
1204 #define BCE_PCI_PM_DATA_B_PM_DATA_6_PRG          (0xffL<<16)
1205 #define BCE_PCI_PM_DATA_B_PM_DATA_7_PRG          (0xffL<<24)
1206
1207 #define BCE_PCI_SWAP_DIAG0                              0x00000418
1208 #define BCE_PCI_SWAP_DIAG1                              0x0000041c
1209 #define BCE_PCI_EXP_ROM_ADDR                            0x00000420
1210 #define BCE_PCI_EXP_ROM_ADDR_ADDRESS                     (0x3fffffL<<2)
1211 #define BCE_PCI_EXP_ROM_ADDR_REQ                         (1L<<31)
1212
1213 #define BCE_PCI_EXP_ROM_DATA                            0x00000424
1214 #define BCE_PCI_VPD_INTF                                0x00000428
1215 #define BCE_PCI_VPD_INTF_INTF_REQ                        (1L<<0)
1216
1217 #define BCE_PCI_VPD_ADDR_FLAG                           0x0000042c
1218 #define BCE_PCI_VPD_ADDR_FLAG_ADDRESS                    (0x1fff<<2)
1219 #define BCE_PCI_VPD_ADDR_FLAG_WR                         (1<<15)
1220
1221 #define BCE_PCI_VPD_DATA                                0x00000430
1222 #define BCE_PCI_ID_VAL1                         0x00000434
1223 #define BCE_PCI_ID_VAL1_DEVICE_ID                        (0xffffL<<0)
1224 #define BCE_PCI_ID_VAL1_VENDOR_ID                        (0xffffL<<16)
1225
1226 #define BCE_PCI_ID_VAL2                         0x00000438
1227 #define BCE_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID              (0xffffL<<0)
1228 #define BCE_PCI_ID_VAL2_SUBSYSTEM_ID                     (0xffffL<<16)
1229
1230 #define BCE_PCI_ID_VAL3                         0x0000043c
1231 #define BCE_PCI_ID_VAL3_CLASS_CODE                       (0xffffffL<<0)
1232 #define BCE_PCI_ID_VAL3_REVISION_ID                      (0xffL<<24)
1233
1234 #define BCE_PCI_ID_VAL4                         0x00000440
1235 #define BCE_PCI_ID_VAL4_CAP_ENA                  (0xfL<<0)
1236 #define BCE_PCI_ID_VAL4_CAP_ENA_0                        (0L<<0)
1237 #define BCE_PCI_ID_VAL4_CAP_ENA_1                        (1L<<0)
1238 #define BCE_PCI_ID_VAL4_CAP_ENA_2                        (2L<<0)
1239 #define BCE_PCI_ID_VAL4_CAP_ENA_3                        (3L<<0)
1240 #define BCE_PCI_ID_VAL4_CAP_ENA_4                        (4L<<0)
1241 #define BCE_PCI_ID_VAL4_CAP_ENA_5                        (5L<<0)
1242 #define BCE_PCI_ID_VAL4_CAP_ENA_6                        (6L<<0)
1243 #define BCE_PCI_ID_VAL4_CAP_ENA_7                        (7L<<0)
1244 #define BCE_PCI_ID_VAL4_CAP_ENA_8                        (8L<<0)
1245 #define BCE_PCI_ID_VAL4_CAP_ENA_9                        (9L<<0)
1246 #define BCE_PCI_ID_VAL4_CAP_ENA_10                       (10L<<0)
1247 #define BCE_PCI_ID_VAL4_CAP_ENA_11                       (11L<<0)
1248 #define BCE_PCI_ID_VAL4_CAP_ENA_12                       (12L<<0)
1249 #define BCE_PCI_ID_VAL4_CAP_ENA_13                       (13L<<0)
1250 #define BCE_PCI_ID_VAL4_CAP_ENA_14                       (14L<<0)
1251 #define BCE_PCI_ID_VAL4_CAP_ENA_15                       (15L<<0)
1252 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG                     (0x3L<<6)
1253 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_0                   (0L<<6)
1254 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_1                   (1L<<6)
1255 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_2                   (2L<<6)
1256 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_3                   (3L<<6)
1257 #define BCE_PCI_ID_VAL4_MSI_LIMIT                        (0x7L<<9)
1258 #define BCE_PCI_ID_VAL4_MSI_ADVERTIZE                    (0x7L<<12)
1259 #define BCE_PCI_ID_VAL4_MSI_ENABLE                       (1L<<15)
1260 #define BCE_PCI_ID_VAL4_MAX_64_ADVERTIZE                 (1L<<16)
1261 #define BCE_PCI_ID_VAL4_MAX_133_ADVERTIZE                (1L<<17)
1262 #define BCE_PCI_ID_VAL4_MAX_MEM_READ_SIZE                (0x3L<<21)
1263 #define BCE_PCI_ID_VAL4_MAX_SPLIT_SIZE                   (0x7L<<23)
1264 #define BCE_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE              (0x7L<<26)
1265
1266 #define BCE_PCI_ID_VAL5                         0x00000444
1267 #define BCE_PCI_ID_VAL5_D1_SUPPORT                       (1L<<0)
1268 #define BCE_PCI_ID_VAL5_D2_SUPPORT                       (1L<<1)
1269 #define BCE_PCI_ID_VAL5_PME_IN_D0                        (1L<<2)
1270 #define BCE_PCI_ID_VAL5_PME_IN_D1                        (1L<<3)
1271 #define BCE_PCI_ID_VAL5_PME_IN_D2                        (1L<<4)
1272 #define BCE_PCI_ID_VAL5_PME_IN_D3_HOT                    (1L<<5)
1273
1274 #define BCE_PCI_PCIX_EXTENDED_STATUS                    0x00000448
1275 #define BCE_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP            (1L<<8)
1276 #define BCE_PCI_PCIX_EXTENDED_STATUS_LONG_BURST  (1L<<9)
1277 #define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS        (0xfL<<16)
1278 #define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX  (0xffL<<24)
1279
1280 #define BCE_PCI_ID_VAL6                         0x0000044c
1281 #define BCE_PCI_ID_VAL6_MAX_LAT                  (0xffL<<0)
1282 #define BCE_PCI_ID_VAL6_MIN_GNT                  (0xffL<<8)
1283 #define BCE_PCI_ID_VAL6_BIST                             (0xffL<<16)
1284
1285 #define BCE_PCI_MSI_DATA                                0x00000450
1286 #define BCE_PCI_MSI_DATA_PCI_MSI_DATA                    (0xffffL<<0)
1287
1288 #define BCE_PCI_MSI_ADDR_H                              0x00000454
1289 #define BCE_PCI_MSI_ADDR_L                              0x00000458
1290
1291
1292 /*
1293  *  misc_reg definition
1294  *  offset: 0x800
1295  */
1296 #define BCE_MISC_COMMAND                                0x00000800
1297 #define BCE_MISC_COMMAND_ENABLE_ALL                      (1L<<0)
1298 #define BCE_MISC_COMMAND_DISABLE_ALL                     (1L<<1)
1299 #define BCE_MISC_COMMAND_CORE_RESET                      (1L<<4)
1300 #define BCE_MISC_COMMAND_HARD_RESET                      (1L<<5)
1301 #define BCE_MISC_COMMAND_PAR_ERROR                       (1L<<8)
1302 #define BCE_MISC_COMMAND_PAR_ERR_RAM                     (0x7fL<<16)
1303
1304 #define BCE_MISC_CFG                                    0x00000804
1305 #define BCE_MISC_CFG_PCI_GRC_TMOUT                       (1L<<0)
1306 #define BCE_MISC_CFG_NVM_WR_EN                           (0x3L<<1)
1307 #define BCE_MISC_CFG_NVM_WR_EN_PROTECT                   (0L<<1)
1308 #define BCE_MISC_CFG_NVM_WR_EN_PCI                       (1L<<1)
1309 #define BCE_MISC_CFG_NVM_WR_EN_ALLOW                     (2L<<1)
1310 #define BCE_MISC_CFG_NVM_WR_EN_ALLOW2                    (3L<<1)
1311 #define BCE_MISC_CFG_BIST_EN                             (1L<<3)
1312 #define BCE_MISC_CFG_CK25_OUT_ALT_SRC                    (1L<<4)
1313 #define BCE_MISC_CFG_BYPASS_BSCAN                        (1L<<5)
1314 #define BCE_MISC_CFG_BYPASS_EJTAG                        (1L<<6)
1315 #define BCE_MISC_CFG_CLK_CTL_OVERRIDE                    (1L<<7)
1316 #define BCE_MISC_CFG_LEDMODE                             (0x3L<<8)
1317 #define BCE_MISC_CFG_LEDMODE_MAC                         (0L<<8)
1318 #define BCE_MISC_CFG_LEDMODE_GPHY1                       (1L<<8)
1319 #define BCE_MISC_CFG_LEDMODE_GPHY2                       (2L<<8)
1320
1321 #define BCE_MISC_ID                                     0x00000808
1322 #define BCE_MISC_ID_BOND_ID                              (0xfL<<0)
1323 #define BCE_MISC_ID_CHIP_METAL                           (0xffL<<4)
1324 #define BCE_MISC_ID_CHIP_REV                             (0xfL<<12)
1325 #define BCE_MISC_ID_CHIP_NUM                             (0xffffL<<16)
1326
1327 #define BCE_MISC_ENABLE_STATUS_BITS                     0x0000080c
1328 #define BCE_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE  (1L<<0)
1329 #define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE    (1L<<1)
1330 #define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE   (1L<<2)
1331 #define BCE_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE  (1L<<3)
1332 #define BCE_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE        (1L<<4)
1333 #define BCE_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE    (1L<<5)
1334 #define BCE_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE  (1L<<6)
1335 #define BCE_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE   (1L<<7)
1336 #define BCE_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE  (1L<<8)
1337 #define BCE_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE  (1L<<9)
1338 #define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE         (1L<<10)
1339 #define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE     (1L<<11)
1340 #define BCE_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE       (1L<<12)
1341 #define BCE_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE     (1L<<13)
1342 #define BCE_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE  (1L<<14)
1343 #define BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE        (1L<<15)
1344 #define BCE_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE   (1L<<16)
1345 #define BCE_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE        (1L<<17)
1346 #define BCE_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE    (1L<<18)
1347 #define BCE_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE         (1L<<19)
1348 #define BCE_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE         (1L<<20)
1349 #define BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE       (1L<<21)
1350 #define BCE_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE         (1L<<22)
1351 #define BCE_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE         (1L<<23)
1352 #define BCE_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE        (1L<<24)
1353 #define BCE_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE         (1L<<25)
1354 #define BCE_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE    (1L<<26)
1355 #define BCE_MISC_ENABLE_STATUS_BITS_UMP_ENABLE           (1L<<27)
1356
1357 #define BCE_MISC_ENABLE_SET_BITS                        0x00000810
1358 #define BCE_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE     (1L<<0)
1359 #define BCE_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE       (1L<<1)
1360 #define BCE_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE      (1L<<2)
1361 #define BCE_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE     (1L<<3)
1362 #define BCE_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE           (1L<<4)
1363 #define BCE_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE       (1L<<5)
1364 #define BCE_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE     (1L<<6)
1365 #define BCE_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE      (1L<<7)
1366 #define BCE_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE     (1L<<8)
1367 #define BCE_MISC_ENABLE_SET_BITS_EMAC_ENABLE             (1L<<9)
1368 #define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE    (1L<<10)
1369 #define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE        (1L<<11)
1370 #define BCE_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE  (1L<<12)
1371 #define BCE_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE        (1L<<13)
1372 #define BCE_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE     (1L<<14)
1373 #define BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE           (1L<<15)
1374 #define BCE_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE      (1L<<16)
1375 #define BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE           (1L<<17)
1376 #define BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE       (1L<<18)
1377 #define BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE    (1L<<19)
1378 #define BCE_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE    (1L<<20)
1379 #define BCE_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE  (1L<<21)
1380 #define BCE_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE    (1L<<22)
1381 #define BCE_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE    (1L<<23)
1382 #define BCE_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE   (1L<<24)
1383 #define BCE_MISC_ENABLE_SET_BITS_TIMER_ENABLE            (1L<<25)
1384 #define BCE_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE       (1L<<26)
1385 #define BCE_MISC_ENABLE_SET_BITS_UMP_ENABLE              (1L<<27)
1386
1387 #define BCE_MISC_ENABLE_CLR_BITS                        0x00000814
1388 #define BCE_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE     (1L<<0)
1389 #define BCE_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE       (1L<<1)
1390 #define BCE_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE      (1L<<2)
1391 #define BCE_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE     (1L<<3)
1392 #define BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE           (1L<<4)
1393 #define BCE_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE       (1L<<5)
1394 #define BCE_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE     (1L<<6)
1395 #define BCE_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE      (1L<<7)
1396 #define BCE_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE     (1L<<8)
1397 #define BCE_MISC_ENABLE_CLR_BITS_EMAC_ENABLE             (1L<<9)
1398 #define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE    (1L<<10)
1399 #define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE        (1L<<11)
1400 #define BCE_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE  (1L<<12)
1401 #define BCE_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE        (1L<<13)
1402 #define BCE_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE     (1L<<14)
1403 #define BCE_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE           (1L<<15)
1404 #define BCE_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE      (1L<<16)
1405 #define BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE           (1L<<17)
1406 #define BCE_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE       (1L<<18)
1407 #define BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE    (1L<<19)
1408 #define BCE_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE    (1L<<20)
1409 #define BCE_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE  (1L<<21)
1410 #define BCE_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE    (1L<<22)
1411 #define BCE_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE    (1L<<23)
1412 #define BCE_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE   (1L<<24)
1413 #define BCE_MISC_ENABLE_CLR_BITS_TIMER_ENABLE            (1L<<25)
1414 #define BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE       (1L<<26)
1415 #define BCE_MISC_ENABLE_CLR_BITS_UMP_ENABLE              (1L<<27)
1416
1417 #define BCE_MISC_CLOCK_CONTROL_BITS                     0x00000818
1418 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET      (0xfL<<0)
1419 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ        (0L<<0)
1420 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ        (1L<<0)
1421 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ        (2L<<0)
1422 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ        (3L<<0)
1423 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ        (4L<<0)
1424 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ        (5L<<0)
1425 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ        (6L<<0)
1426 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ       (7L<<0)
1427 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW  (0xfL<<0)
1428 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE     (1L<<6)
1429 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT         (1L<<7)
1430 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC     (0x7L<<8)
1431 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF       (0L<<8)
1432 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12  (1L<<8)
1433 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6   (2L<<8)
1434 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62  (4L<<8)
1435 #define BCE_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD            (1L<<11)
1436 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED   (0xfL<<12)
1437 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100       (0L<<12)
1438 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80        (1L<<12)
1439 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50        (2L<<12)
1440 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40        (4L<<12)
1441 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25        (8L<<12)
1442 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP    (1L<<16)
1443 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP         (1L<<17)
1444 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_18  (1L<<18)
1445 #define BCE_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET  (1L<<19)
1446 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED             (0xfffL<<20)
1447
1448 #define BCE_MISC_GPIO                                   0x0000081c
1449 #define BCE_MISC_GPIO_VALUE                              (0xffL<<0)
1450 #define BCE_MISC_GPIO_SET                                (0xffL<<8)
1451 #define BCE_MISC_GPIO_CLR                                (0xffL<<16)
1452 #define BCE_MISC_GPIO_FLOAT                              (0xffL<<24)
1453
1454 #define BCE_MISC_GPIO_INT                               0x00000820
1455 #define BCE_MISC_GPIO_INT_INT_STATE                      (0xfL<<0)
1456 #define BCE_MISC_GPIO_INT_OLD_VALUE                      (0xfL<<8)
1457 #define BCE_MISC_GPIO_INT_OLD_SET                        (0xfL<<16)
1458 #define BCE_MISC_GPIO_INT_OLD_CLR                        (0xfL<<24)
1459
1460 #define BCE_MISC_CONFIG_LFSR                            0x00000824
1461 #define BCE_MISC_CONFIG_LFSR_DIV                         (0xffffL<<0)
1462
1463 #define BCE_MISC_LFSR_MASK_BITS                 0x00000828
1464 #define BCE_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE      (1L<<0)
1465 #define BCE_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE        (1L<<1)
1466 #define BCE_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE       (1L<<2)
1467 #define BCE_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE      (1L<<3)
1468 #define BCE_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE            (1L<<4)
1469 #define BCE_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE        (1L<<5)
1470 #define BCE_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE      (1L<<6)
1471 #define BCE_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE       (1L<<7)
1472 #define BCE_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE      (1L<<8)
1473 #define BCE_MISC_LFSR_MASK_BITS_EMAC_ENABLE              (1L<<9)
1474 #define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE     (1L<<10)
1475 #define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE         (1L<<11)
1476 #define BCE_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE           (1L<<12)
1477 #define BCE_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE         (1L<<13)
1478 #define BCE_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE      (1L<<14)
1479 #define BCE_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE            (1L<<15)
1480 #define BCE_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE       (1L<<16)
1481 #define BCE_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE            (1L<<17)
1482 #define BCE_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE        (1L<<18)
1483 #define BCE_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE     (1L<<19)
1484 #define BCE_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE     (1L<<20)
1485 #define BCE_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE           (1L<<21)
1486 #define BCE_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE     (1L<<22)
1487 #define BCE_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE     (1L<<23)
1488 #define BCE_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE    (1L<<24)
1489 #define BCE_MISC_LFSR_MASK_BITS_TIMER_ENABLE             (1L<<25)
1490 #define BCE_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE        (1L<<26)
1491 #define BCE_MISC_LFSR_MASK_BITS_UMP_ENABLE               (1L<<27)
1492
1493 #define BCE_MISC_ARB_REQ0                               0x0000082c
1494 #define BCE_MISC_ARB_REQ1                               0x00000830
1495 #define BCE_MISC_ARB_REQ2                               0x00000834
1496 #define BCE_MISC_ARB_REQ3                               0x00000838
1497 #define BCE_MISC_ARB_REQ4                               0x0000083c
1498 #define BCE_MISC_ARB_FREE0                              0x00000840
1499 #define BCE_MISC_ARB_FREE1                              0x00000844
1500 #define BCE_MISC_ARB_FREE2                              0x00000848
1501 #define BCE_MISC_ARB_FREE3                              0x0000084c
1502 #define BCE_MISC_ARB_FREE4                              0x00000850
1503 #define BCE_MISC_ARB_REQ_STATUS0                        0x00000854
1504 #define BCE_MISC_ARB_REQ_STATUS1                        0x00000858
1505 #define BCE_MISC_ARB_REQ_STATUS2                        0x0000085c
1506 #define BCE_MISC_ARB_REQ_STATUS3                        0x00000860
1507 #define BCE_MISC_ARB_REQ_STATUS4                        0x00000864
1508 #define BCE_MISC_ARB_GNT0                               0x00000868
1509 #define BCE_MISC_ARB_GNT0_0                              (0x7L<<0)
1510 #define BCE_MISC_ARB_GNT0_1                              (0x7L<<4)
1511 #define BCE_MISC_ARB_GNT0_2                              (0x7L<<8)
1512 #define BCE_MISC_ARB_GNT0_3                              (0x7L<<12)
1513 #define BCE_MISC_ARB_GNT0_4                              (0x7L<<16)
1514 #define BCE_MISC_ARB_GNT0_5                              (0x7L<<20)
1515 #define BCE_MISC_ARB_GNT0_6                              (0x7L<<24)
1516 #define BCE_MISC_ARB_GNT0_7                              (0x7L<<28)
1517
1518 #define BCE_MISC_ARB_GNT1                               0x0000086c
1519 #define BCE_MISC_ARB_GNT1_8                              (0x7L<<0)
1520 #define BCE_MISC_ARB_GNT1_9                              (0x7L<<4)
1521 #define BCE_MISC_ARB_GNT1_10                             (0x7L<<8)
1522 #define BCE_MISC_ARB_GNT1_11                             (0x7L<<12)
1523 #define BCE_MISC_ARB_GNT1_12                             (0x7L<<16)
1524 #define BCE_MISC_ARB_GNT1_13                             (0x7L<<20)
1525 #define BCE_MISC_ARB_GNT1_14                             (0x7L<<24)
1526 #define BCE_MISC_ARB_GNT1_15                             (0x7L<<28)
1527
1528 #define BCE_MISC_ARB_GNT2                               0x00000870
1529 #define BCE_MISC_ARB_GNT2_16                             (0x7L<<0)
1530 #define BCE_MISC_ARB_GNT2_17                             (0x7L<<4)
1531 #define BCE_MISC_ARB_GNT2_18                             (0x7L<<8)
1532 #define BCE_MISC_ARB_GNT2_19                             (0x7L<<12)
1533 #define BCE_MISC_ARB_GNT2_20                             (0x7L<<16)
1534 #define BCE_MISC_ARB_GNT2_21                             (0x7L<<20)
1535 #define BCE_MISC_ARB_GNT2_22                             (0x7L<<24)
1536 #define BCE_MISC_ARB_GNT2_23                             (0x7L<<28)
1537
1538 #define BCE_MISC_ARB_GNT3                               0x00000874
1539 #define BCE_MISC_ARB_GNT3_24                             (0x7L<<0)
1540 #define BCE_MISC_ARB_GNT3_25                             (0x7L<<4)
1541 #define BCE_MISC_ARB_GNT3_26                             (0x7L<<8)
1542 #define BCE_MISC_ARB_GNT3_27                             (0x7L<<12)
1543 #define BCE_MISC_ARB_GNT3_28                             (0x7L<<16)
1544 #define BCE_MISC_ARB_GNT3_29                             (0x7L<<20)
1545 #define BCE_MISC_ARB_GNT3_30                             (0x7L<<24)
1546 #define BCE_MISC_ARB_GNT3_31                             (0x7L<<28)
1547
1548 #define BCE_MISC_PRBS_CONTROL                           0x00000878
1549 #define BCE_MISC_PRBS_CONTROL_EN                         (1L<<0)
1550 #define BCE_MISC_PRBS_CONTROL_RSTB                       (1L<<1)
1551 #define BCE_MISC_PRBS_CONTROL_INV                        (1L<<2)
1552 #define BCE_MISC_PRBS_CONTROL_ERR_CLR                    (1L<<3)
1553 #define BCE_MISC_PRBS_CONTROL_ORDER                      (0x3L<<4)
1554 #define BCE_MISC_PRBS_CONTROL_ORDER_7TH          (0L<<4)
1555 #define BCE_MISC_PRBS_CONTROL_ORDER_15TH                 (1L<<4)
1556 #define BCE_MISC_PRBS_CONTROL_ORDER_23RD                 (2L<<4)
1557 #define BCE_MISC_PRBS_CONTROL_ORDER_31ST                 (3L<<4)
1558
1559 #define BCE_MISC_PRBS_STATUS                            0x0000087c
1560 #define BCE_MISC_PRBS_STATUS_LOCK                        (1L<<0)
1561 #define BCE_MISC_PRBS_STATUS_STKY                        (1L<<1)
1562 #define BCE_MISC_PRBS_STATUS_ERRORS                      (0x3fffL<<2)
1563 #define BCE_MISC_PRBS_STATUS_STATE                       (0xfL<<16)
1564
1565 #define BCE_MISC_SM_ASF_CONTROL                 0x00000880
1566 #define BCE_MISC_SM_ASF_CONTROL_ASF_RST          (1L<<0)
1567 #define BCE_MISC_SM_ASF_CONTROL_TSC_EN                   (1L<<1)
1568 #define BCE_MISC_SM_ASF_CONTROL_WG_TO                    (1L<<2)
1569 #define BCE_MISC_SM_ASF_CONTROL_HB_TO                    (1L<<3)
1570 #define BCE_MISC_SM_ASF_CONTROL_PA_TO                    (1L<<4)
1571 #define BCE_MISC_SM_ASF_CONTROL_PL_TO                    (1L<<5)
1572 #define BCE_MISC_SM_ASF_CONTROL_RT_TO                    (1L<<6)
1573 #define BCE_MISC_SM_ASF_CONTROL_SMB_EVENT                (1L<<7)
1574 #define BCE_MISC_SM_ASF_CONTROL_RES                      (0xfL<<8)
1575 #define BCE_MISC_SM_ASF_CONTROL_SMB_EN                   (1L<<12)
1576 #define BCE_MISC_SM_ASF_CONTROL_SMB_BB_EN                (1L<<13)
1577 #define BCE_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT         (1L<<14)
1578 #define BCE_MISC_SM_ASF_CONTROL_SMB_AUTOREAD             (1L<<15)
1579 #define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1            (0x3fL<<16)
1580 #define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2            (0x3fL<<24)
1581 #define BCE_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0        (1L<<30)
1582 #define BCE_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN           (1L<<31)
1583
1584 #define BCE_MISC_SMB_IN                         0x00000884
1585 #define BCE_MISC_SMB_IN_DAT_IN                           (0xffL<<0)
1586 #define BCE_MISC_SMB_IN_RDY                              (1L<<8)
1587 #define BCE_MISC_SMB_IN_DONE                             (1L<<9)
1588 #define BCE_MISC_SMB_IN_FIRSTBYTE                        (1L<<10)
1589 #define BCE_MISC_SMB_IN_STATUS                           (0x7L<<11)
1590 #define BCE_MISC_SMB_IN_STATUS_OK                        (0x0L<<11)
1591 #define BCE_MISC_SMB_IN_STATUS_PEC                       (0x1L<<11)
1592 #define BCE_MISC_SMB_IN_STATUS_OFLOW                     (0x2L<<11)
1593 #define BCE_MISC_SMB_IN_STATUS_STOP                      (0x3L<<11)
1594 #define BCE_MISC_SMB_IN_STATUS_TIMEOUT                   (0x4L<<11)
1595
1596 #define BCE_MISC_SMB_OUT                                0x00000888
1597 #define BCE_MISC_SMB_OUT_DAT_OUT                         (0xffL<<0)
1598 #define BCE_MISC_SMB_OUT_RDY                             (1L<<8)
1599 #define BCE_MISC_SMB_OUT_START                           (1L<<9)
1600 #define BCE_MISC_SMB_OUT_LAST                            (1L<<10)
1601 #define BCE_MISC_SMB_OUT_ACC_TYPE                        (1L<<11)
1602 #define BCE_MISC_SMB_OUT_ENB_PEC                         (1L<<12)
1603 #define BCE_MISC_SMB_OUT_GET_RX_LEN                      (1L<<13)
1604 #define BCE_MISC_SMB_OUT_SMB_READ_LEN                    (0x3fL<<14)
1605 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS          (0xfL<<20)
1606 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_OK               (0L<<20)
1607 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK       (1L<<20)
1608 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK         (9L<<20)
1609 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW            (2L<<20)
1610 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_STOP             (3L<<20)
1611 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT  (4L<<20)
1612 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST       (5L<<20)
1613 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST         (0xdL<<20)
1614 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK           (0x6L<<20)
1615 #define BCE_MISC_SMB_OUT_SMB_OUT_SLAVEMODE               (1L<<24)
1616 #define BCE_MISC_SMB_OUT_SMB_OUT_DAT_EN          (1L<<25)
1617 #define BCE_MISC_SMB_OUT_SMB_OUT_DAT_IN          (1L<<26)
1618 #define BCE_MISC_SMB_OUT_SMB_OUT_CLK_EN          (1L<<27)
1619 #define BCE_MISC_SMB_OUT_SMB_OUT_CLK_IN          (1L<<28)
1620
1621 #define BCE_MISC_SMB_WATCHDOG                           0x0000088c
1622 #define BCE_MISC_SMB_WATCHDOG_WATCHDOG                   (0xffffL<<0)
1623
1624 #define BCE_MISC_SMB_HEARTBEAT                          0x00000890
1625 #define BCE_MISC_SMB_HEARTBEAT_HEARTBEAT                 (0xffffL<<0)
1626
1627 #define BCE_MISC_SMB_POLL_ASF                           0x00000894
1628 #define BCE_MISC_SMB_POLL_ASF_POLL_ASF                   (0xffffL<<0)
1629
1630 #define BCE_MISC_SMB_POLL_LEGACY                        0x00000898
1631 #define BCE_MISC_SMB_POLL_LEGACY_POLL_LEGACY             (0xffffL<<0)
1632
1633 #define BCE_MISC_SMB_RETRAN                             0x0000089c
1634 #define BCE_MISC_SMB_RETRAN_RETRAN                       (0xffL<<0)
1635
1636 #define BCE_MISC_SMB_TIMESTAMP                          0x000008a0
1637 #define BCE_MISC_SMB_TIMESTAMP_TIMESTAMP                 (0xffffffffL<<0)
1638
1639 #define BCE_MISC_PERR_ENA0                              0x000008a4
1640 #define BCE_MISC_PERR_ENA0_COM_MISC_CTXC                 (1L<<0)
1641 #define BCE_MISC_PERR_ENA0_COM_MISC_REGF                 (1L<<1)
1642 #define BCE_MISC_PERR_ENA0_COM_MISC_SCPAD                (1L<<2)
1643 #define BCE_MISC_PERR_ENA0_CP_MISC_CTXC          (1L<<3)
1644 #define BCE_MISC_PERR_ENA0_CP_MISC_REGF          (1L<<4)
1645 #define BCE_MISC_PERR_ENA0_CP_MISC_SCPAD                 (1L<<5)
1646 #define BCE_MISC_PERR_ENA0_CS_MISC_TMEM          (1L<<6)
1647 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM0                (1L<<7)
1648 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM1                (1L<<8)
1649 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM2                (1L<<9)
1650 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM3                (1L<<10)
1651 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM4                (1L<<11)
1652 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM5                (1L<<12)
1653 #define BCE_MISC_PERR_ENA0_CTX_MISC_PGTBL                (1L<<13)
1654 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR0                 (1L<<14)
1655 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR1                 (1L<<15)
1656 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR2                 (1L<<16)
1657 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR3                 (1L<<17)
1658 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR4                 (1L<<18)
1659 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DW0                 (1L<<19)
1660 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DW1                 (1L<<20)
1661 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DW2                 (1L<<21)
1662 #define BCE_MISC_PERR_ENA0_HC_MISC_DMA                   (1L<<22)
1663 #define BCE_MISC_PERR_ENA0_MCP_MISC_REGF                 (1L<<23)
1664 #define BCE_MISC_PERR_ENA0_MCP_MISC_SCPAD                (1L<<24)
1665 #define BCE_MISC_PERR_ENA0_MQ_MISC_CTX                   (1L<<25)
1666 #define BCE_MISC_PERR_ENA0_RBDC_MISC                     (1L<<26)
1667 #define BCE_MISC_PERR_ENA0_RBUF_MISC_MB          (1L<<27)
1668 #define BCE_MISC_PERR_ENA0_RBUF_MISC_PTR                 (1L<<28)
1669 #define BCE_MISC_PERR_ENA0_RDE_MISC_RPC          (1L<<29)
1670 #define BCE_MISC_PERR_ENA0_RDE_MISC_RPM          (1L<<30)
1671 #define BCE_MISC_PERR_ENA0_RV2P_MISC_CB0REGS             (1L<<31)
1672
1673 #define BCE_MISC_PERR_ENA1                              0x000008a8
1674 #define BCE_MISC_PERR_ENA1_RV2P_MISC_CB1REGS             (1L<<0)
1675 #define BCE_MISC_PERR_ENA1_RV2P_MISC_P1IRAM              (1L<<1)
1676 #define BCE_MISC_PERR_ENA1_RV2P_MISC_P2IRAM              (1L<<2)
1677 #define BCE_MISC_PERR_ENA1_RXP_MISC_CTXC                 (1L<<3)
1678 #define BCE_MISC_PERR_ENA1_RXP_MISC_REGF                 (1L<<4)
1679 #define BCE_MISC_PERR_ENA1_RXP_MISC_SCPAD                (1L<<5)
1680 #define BCE_MISC_PERR_ENA1_RXP_MISC_RBUFC                (1L<<6)
1681 #define BCE_MISC_PERR_ENA1_TBDC_MISC                     (1L<<7)
1682 #define BCE_MISC_PERR_ENA1_TDMA_MISC                     (1L<<8)
1683 #define BCE_MISC_PERR_ENA1_THBUF_MISC_MB0                (1L<<9)
1684 #define BCE_MISC_PERR_ENA1_THBUF_MISC_MB1                (1L<<10)
1685 #define BCE_MISC_PERR_ENA1_TPAT_MISC_REGF                (1L<<11)
1686 #define BCE_MISC_PERR_ENA1_TPAT_MISC_SCPAD               (1L<<12)
1687 #define BCE_MISC_PERR_ENA1_TPBUF_MISC_MB                 (1L<<13)
1688 #define BCE_MISC_PERR_ENA1_TSCH_MISC_LR          (1L<<14)
1689 #define BCE_MISC_PERR_ENA1_TXP_MISC_CTXC                 (1L<<15)
1690 #define BCE_MISC_PERR_ENA1_TXP_MISC_REGF                 (1L<<16)
1691 #define BCE_MISC_PERR_ENA1_TXP_MISC_SCPAD                (1L<<17)
1692 #define BCE_MISC_PERR_ENA1_UMP_MISC_FIORX                (1L<<18)
1693 #define BCE_MISC_PERR_ENA1_UMP_MISC_FIOTX                (1L<<19)
1694 #define BCE_MISC_PERR_ENA1_UMP_MISC_RX                   (1L<<20)
1695 #define BCE_MISC_PERR_ENA1_UMP_MISC_TX                   (1L<<21)
1696 #define BCE_MISC_PERR_ENA1_RDMAQ_MISC                    (1L<<22)
1697 #define BCE_MISC_PERR_ENA1_CSQ_MISC                      (1L<<23)
1698 #define BCE_MISC_PERR_ENA1_CPQ_MISC                      (1L<<24)
1699 #define BCE_MISC_PERR_ENA1_MCPQ_MISC                     (1L<<25)
1700 #define BCE_MISC_PERR_ENA1_RV2PMQ_MISC                   (1L<<26)
1701 #define BCE_MISC_PERR_ENA1_RV2PPQ_MISC                   (1L<<27)
1702 #define BCE_MISC_PERR_ENA1_RV2PTQ_MISC                   (1L<<28)
1703 #define BCE_MISC_PERR_ENA1_RXPQ_MISC                     (1L<<29)
1704 #define BCE_MISC_PERR_ENA1_RXPCQ_MISC                    (1L<<30)
1705 #define BCE_MISC_PERR_ENA1_RLUPQ_MISC                    (1L<<31)
1706
1707 #define BCE_MISC_PERR_ENA2                              0x000008ac
1708 #define BCE_MISC_PERR_ENA2_COMQ_MISC                     (1L<<0)
1709 #define BCE_MISC_PERR_ENA2_COMXQ_MISC                    (1L<<1)
1710 #define BCE_MISC_PERR_ENA2_COMTQ_MISC                    (1L<<2)
1711 #define BCE_MISC_PERR_ENA2_TSCHQ_MISC                    (1L<<3)
1712 #define BCE_MISC_PERR_ENA2_TBDRQ_MISC                    (1L<<4)
1713 #define BCE_MISC_PERR_ENA2_TXPQ_MISC                     (1L<<5)
1714 #define BCE_MISC_PERR_ENA2_TDMAQ_MISC                    (1L<<6)
1715 #define BCE_MISC_PERR_ENA2_TPATQ_MISC                    (1L<<7)
1716 #define BCE_MISC_PERR_ENA2_TASQ_MISC                     (1L<<8)
1717
1718 #define BCE_MISC_DEBUG_VECTOR_SEL                       0x000008b0
1719 #define BCE_MISC_DEBUG_VECTOR_SEL_0                      (0xfffL<<0)
1720 #define BCE_MISC_DEBUG_VECTOR_SEL_1                      (0xfffL<<12)
1721
1722 #define BCE_MISC_VREG_CONTROL                           0x000008b4
1723 #define BCE_MISC_VREG_CONTROL_1_2                        (0xfL<<0)
1724 #define BCE_MISC_VREG_CONTROL_2_5                        (0xfL<<4)
1725
1726 #define BCE_MISC_FINAL_CLK_CTL_VAL                      0x000008b8
1727 #define BCE_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL        (0x3ffffffL<<6)
1728
1729 #define BCE_MISC_UNUSED0                                0x000008bc
1730
1731
1732 /*
1733  *  nvm_reg definition
1734  *  offset: 0x6400
1735  */
1736 #define BCE_NVM_COMMAND                         0x00006400
1737 #define BCE_NVM_COMMAND_RST                              (1L<<0)
1738 #define BCE_NVM_COMMAND_DONE                             (1L<<3)
1739 #define BCE_NVM_COMMAND_DOIT                             (1L<<4)
1740 #define BCE_NVM_COMMAND_WR                               (1L<<5)
1741 #define BCE_NVM_COMMAND_ERASE                            (1L<<6)
1742 #define BCE_NVM_COMMAND_FIRST                            (1L<<7)
1743 #define BCE_NVM_COMMAND_LAST                             (1L<<8)
1744 #define BCE_NVM_COMMAND_WREN                             (1L<<16)
1745 #define BCE_NVM_COMMAND_WRDI                             (1L<<17)
1746 #define BCE_NVM_COMMAND_EWSR                             (1L<<18)
1747 #define BCE_NVM_COMMAND_WRSR                             (1L<<19)
1748
1749 #define BCE_NVM_STATUS                                  0x00006404
1750 #define BCE_NVM_STATUS_PI_FSM_STATE                      (0xfL<<0)
1751 #define BCE_NVM_STATUS_EE_FSM_STATE                      (0xfL<<4)
1752 #define BCE_NVM_STATUS_EQ_FSM_STATE                      (0xfL<<8)
1753
1754 #define BCE_NVM_WRITE                                   0x00006408
1755 #define BCE_NVM_WRITE_NVM_WRITE_VALUE                    (0xffffffffL<<0)
1756 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG           (0L<<0)
1757 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_EECLK              (1L<<0)
1758 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_EEDATA             (2L<<0)
1759 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_SCLK               (4L<<0)
1760 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_CS_B               (8L<<0)
1761 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_SO                 (16L<<0)
1762 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_SI                 (32L<<0)
1763
1764 #define BCE_NVM_ADDR                                    0x0000640c
1765 #define BCE_NVM_ADDR_NVM_ADDR_VALUE                      (0xffffffL<<0)
1766 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG             (0L<<0)
1767 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_EECLK                (1L<<0)
1768 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_EEDATA               (2L<<0)
1769 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_SCLK                 (4L<<0)
1770 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_CS_B                 (8L<<0)
1771 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_SO                   (16L<<0)
1772 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_SI                   (32L<<0)
1773
1774 #define BCE_NVM_READ                                    0x00006410
1775 #define BCE_NVM_READ_NVM_READ_VALUE                      (0xffffffffL<<0)
1776 #define BCE_NVM_READ_NVM_READ_VALUE_BIT_BANG             (0L<<0)
1777 #define BCE_NVM_READ_NVM_READ_VALUE_EECLK                (1L<<0)
1778 #define BCE_NVM_READ_NVM_READ_VALUE_EEDATA               (2L<<0)
1779 #define BCE_NVM_READ_NVM_READ_VALUE_SCLK                 (4L<<0)
1780 #define BCE_NVM_READ_NVM_READ_VALUE_CS_B                 (8L<<0)
1781 #define BCE_NVM_READ_NVM_READ_VALUE_SO                   (16L<<0)
1782 #define BCE_NVM_READ_NVM_READ_VALUE_SI                   (32L<<0)
1783
1784 #define BCE_NVM_CFG1                                    0x00006414
1785 #define BCE_NVM_CFG1_FLASH_MODE                  (1L<<0)
1786 #define BCE_NVM_CFG1_BUFFER_MODE                         (1L<<1)
1787 #define BCE_NVM_CFG1_PASS_MODE                           (1L<<2)
1788 #define BCE_NVM_CFG1_BITBANG_MODE                        (1L<<3)
1789 #define BCE_NVM_CFG1_STATUS_BIT                  (0x7L<<4)
1790 #define BCE_NVM_CFG1_STATUS_BIT_FLASH_RDY                (0L<<4)
1791 #define BCE_NVM_CFG1_STATUS_BIT_BUFFER_RDY               (7L<<4)
1792 #define BCE_NVM_CFG1_SPI_CLK_DIV                         (0xfL<<7)
1793 #define BCE_NVM_CFG1_SEE_CLK_DIV                         (0x7ffL<<11)
1794 #define BCE_NVM_CFG1_PROTECT_MODE                        (1L<<24)
1795 #define BCE_NVM_CFG1_FLASH_SIZE                  (1L<<25)
1796 #define BCE_NVM_CFG1_COMPAT_BYPASSS                      (1L<<31)
1797
1798 #define BCE_NVM_CFG2                                    0x00006418
1799 #define BCE_NVM_CFG2_ERASE_CMD                           (0xffL<<0)
1800 #define BCE_NVM_CFG2_DUMMY                               (0xffL<<8)
1801 #define BCE_NVM_CFG2_STATUS_CMD                  (0xffL<<16)
1802
1803 #define BCE_NVM_CFG3                                    0x0000641c
1804 #define BCE_NVM_CFG3_BUFFER_RD_CMD                       (0xffL<<0)
1805 #define BCE_NVM_CFG3_WRITE_CMD                           (0xffL<<8)
1806 #define BCE_NVM_CFG3_BUFFER_WRITE_CMD                    (0xffL<<16)
1807 #define BCE_NVM_CFG3_READ_CMD                            (0xffL<<24)
1808
1809 #define BCE_NVM_SW_ARB                                  0x00006420
1810 #define BCE_NVM_SW_ARB_ARB_REQ_SET0                      (1L<<0)
1811 #define BCE_NVM_SW_ARB_ARB_REQ_SET1                      (1L<<1)
1812 #define BCE_NVM_SW_ARB_ARB_REQ_SET2                      (1L<<2)
1813 #define BCE_NVM_SW_ARB_ARB_REQ_SET3                      (1L<<3)
1814 #define BCE_NVM_SW_ARB_ARB_REQ_CLR0                      (1L<<4)
1815 #define BCE_NVM_SW_ARB_ARB_REQ_CLR1                      (1L<<5)
1816 #define BCE_NVM_SW_ARB_ARB_REQ_CLR2                      (1L<<6)
1817 #define BCE_NVM_SW_ARB_ARB_REQ_CLR3                      (1L<<7)
1818 #define BCE_NVM_SW_ARB_ARB_ARB0                  (1L<<8)
1819 #define BCE_NVM_SW_ARB_ARB_ARB1                  (1L<<9)
1820 #define BCE_NVM_SW_ARB_ARB_ARB2                  (1L<<10)
1821 #define BCE_NVM_SW_ARB_ARB_ARB3                  (1L<<11)
1822 #define BCE_NVM_SW_ARB_REQ0                              (1L<<12)
1823 #define BCE_NVM_SW_ARB_REQ1                              (1L<<13)
1824 #define BCE_NVM_SW_ARB_REQ2                              (1L<<14)
1825 #define BCE_NVM_SW_ARB_REQ3                              (1L<<15)
1826
1827 #define BCE_NVM_ACCESS_ENABLE                           0x00006424
1828 #define BCE_NVM_ACCESS_ENABLE_EN                         (1L<<0)
1829 #define BCE_NVM_ACCESS_ENABLE_WR_EN                      (1L<<1)
1830
1831 #define BCE_NVM_WRITE1                                  0x00006428
1832 #define BCE_NVM_WRITE1_WREN_CMD                  (0xffL<<0)
1833 #define BCE_NVM_WRITE1_WRDI_CMD                  (0xffL<<8)
1834 #define BCE_NVM_WRITE1_SR_DATA                           (0xffL<<16)
1835
1836
1837
1838 /*
1839  *  dma_reg definition
1840  *  offset: 0xc00
1841  */
1842 #define BCE_DMA_COMMAND                         0x00000c00
1843 #define BCE_DMA_COMMAND_ENABLE                           (1L<<0)
1844
1845 #define BCE_DMA_STATUS                                  0x00000c04
1846 #define BCE_DMA_STATUS_PAR_ERROR_STATE                   (1L<<0)
1847 #define BCE_DMA_STATUS_READ_TRANSFERS_STAT               (1L<<16)
1848 #define BCE_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT  (1L<<17)
1849 #define BCE_DMA_STATUS_BIG_READ_TRANSFERS_STAT           (1L<<18)
1850 #define BCE_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT      (1L<<19)
1851 #define BCE_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT    (1L<<20)
1852 #define BCE_DMA_STATUS_WRITE_TRANSFERS_STAT              (1L<<21)
1853 #define BCE_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT         (1L<<22)
1854 #define BCE_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT  (1L<<23)
1855 #define BCE_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT     (1L<<24)
1856 #define BCE_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT   (1L<<25)
1857
1858 #define BCE_DMA_CONFIG                                  0x00000c08
1859 #define BCE_DMA_CONFIG_DATA_BYTE_SWAP                    (1L<<0)
1860 #define BCE_DMA_CONFIG_DATA_WORD_SWAP                    (1L<<1)
1861 #define BCE_DMA_CONFIG_CNTL_BYTE_SWAP                    (1L<<4)
1862 #define BCE_DMA_CONFIG_CNTL_WORD_SWAP                    (1L<<5)
1863 #define BCE_DMA_CONFIG_ONE_DMA                           (1L<<6)
1864 #define BCE_DMA_CONFIG_CNTL_TWO_DMA                      (1L<<7)
1865 #define BCE_DMA_CONFIG_CNTL_FPGA_MODE                    (1L<<8)
1866 #define BCE_DMA_CONFIG_CNTL_PING_PONG_DMA                (1L<<10)
1867 #define BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY                 (1L<<11)
1868 #define BCE_DMA_CONFIG_NO_RCHANS_IN_USE          (0xfL<<12)
1869 #define BCE_DMA_CONFIG_NO_WCHANS_IN_USE          (0xfL<<16)
1870 #define BCE_DMA_CONFIG_PCI_CLK_CMP_BITS          (0x7L<<20)
1871 #define BCE_DMA_CONFIG_PCI_FAST_CLK_CMP          (1L<<23)
1872 #define BCE_DMA_CONFIG_BIG_SIZE                  (0xfL<<24)
1873 #define BCE_DMA_CONFIG_BIG_SIZE_NONE                     (0x0L<<24)
1874 #define BCE_DMA_CONFIG_BIG_SIZE_64                       (0x1L<<24)
1875 #define BCE_DMA_CONFIG_BIG_SIZE_128                      (0x2L<<24)
1876 #define BCE_DMA_CONFIG_BIG_SIZE_256                      (0x4L<<24)
1877 #define BCE_DMA_CONFIG_BIG_SIZE_512                      (0x8L<<24)
1878
1879 #define BCE_DMA_BLACKOUT                                0x00000c0c
1880 #define BCE_DMA_BLACKOUT_RD_RETRY_BLACKOUT               (0xffL<<0)
1881 #define BCE_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT           (0xffL<<8)
1882 #define BCE_DMA_BLACKOUT_WR_RETRY_BLACKOUT               (0xffL<<16)
1883
1884 #define BCE_DMA_RCHAN_STAT                              0x00000c30
1885 #define BCE_DMA_RCHAN_STAT_COMP_CODE_0                   (0x7L<<0)
1886 #define BCE_DMA_RCHAN_STAT_PAR_ERR_0                     (1L<<3)
1887 #define BCE_DMA_RCHAN_STAT_COMP_CODE_1                   (0x7L<<4)
1888 #define BCE_DMA_RCHAN_STAT_PAR_ERR_1                     (1L<<7)
1889 #define BCE_DMA_RCHAN_STAT_COMP_CODE_2                   (0x7L<<8)
1890 #define BCE_DMA_RCHAN_STAT_PAR_ERR_2                     (1L<<11)
1891 #define BCE_DMA_RCHAN_STAT_COMP_CODE_3                   (0x7L<<12)
1892 #define BCE_DMA_RCHAN_STAT_PAR_ERR_3                     (1L<<15)
1893 #define BCE_DMA_RCHAN_STAT_COMP_CODE_4                   (0x7L<<16)
1894 #define BCE_DMA_RCHAN_STAT_PAR_ERR_4                     (1L<<19)
1895 #define BCE_DMA_RCHAN_STAT_COMP_CODE_5                   (0x7L<<20)
1896 #define BCE_DMA_RCHAN_STAT_PAR_ERR_5                     (1L<<23)
1897 #define BCE_DMA_RCHAN_STAT_COMP_CODE_6                   (0x7L<<24)
1898 #define BCE_DMA_RCHAN_STAT_PAR_ERR_6                     (1L<<27)
1899 #define BCE_DMA_RCHAN_STAT_COMP_CODE_7                   (0x7L<<28)
1900 #define BCE_DMA_RCHAN_STAT_PAR_ERR_7                     (1L<<31)
1901
1902 #define BCE_DMA_WCHAN_STAT                              0x00000c34
1903 #define BCE_DMA_WCHAN_STAT_COMP_CODE_0                   (0x7L<<0)
1904 #define BCE_DMA_WCHAN_STAT_PAR_ERR_0                     (1L<<3)
1905 #define BCE_DMA_WCHAN_STAT_COMP_CODE_1                   (0x7L<<4)
1906 #define BCE_DMA_WCHAN_STAT_PAR_ERR_1                     (1L<<7)
1907 #define BCE_DMA_WCHAN_STAT_COMP_CODE_2                   (0x7L<<8)
1908 #define BCE_DMA_WCHAN_STAT_PAR_ERR_2                     (1L<<11)
1909 #define BCE_DMA_WCHAN_STAT_COMP_CODE_3                   (0x7L<<12)
1910 #define BCE_DMA_WCHAN_STAT_PAR_ERR_3                     (1L<<15)
1911 #define BCE_DMA_WCHAN_STAT_COMP_CODE_4                   (0x7L<<16)
1912 #define BCE_DMA_WCHAN_STAT_PAR_ERR_4                     (1L<<19)
1913 #define BCE_DMA_WCHAN_STAT_COMP_CODE_5                   (0x7L<<20)
1914 #define BCE_DMA_WCHAN_STAT_PAR_ERR_5                     (1L<<23)
1915 #define BCE_DMA_WCHAN_STAT_COMP_CODE_6                   (0x7L<<24)
1916 #define BCE_DMA_WCHAN_STAT_PAR_ERR_6                     (1L<<27)
1917 #define BCE_DMA_WCHAN_STAT_COMP_CODE_7                   (0x7L<<28)
1918 #define BCE_DMA_WCHAN_STAT_PAR_ERR_7                     (1L<<31)
1919
1920 #define BCE_DMA_RCHAN_ASSIGNMENT                        0x00000c38
1921 #define BCE_DMA_RCHAN_ASSIGNMENT_0                       (0xfL<<0)
1922 #define BCE_DMA_RCHAN_ASSIGNMENT_1                       (0xfL<<4)
1923 #define BCE_DMA_RCHAN_ASSIGNMENT_2                       (0xfL<<8)
1924 #define BCE_DMA_RCHAN_ASSIGNMENT_3                       (0xfL<<12)
1925 #define BCE_DMA_RCHAN_ASSIGNMENT_4                       (0xfL<<16)
1926 #define BCE_DMA_RCHAN_ASSIGNMENT_5                       (0xfL<<20)
1927 #define BCE_DMA_RCHAN_ASSIGNMENT_6                       (0xfL<<24)
1928 #define BCE_DMA_RCHAN_ASSIGNMENT_7                       (0xfL<<28)
1929
1930 #define BCE_DMA_WCHAN_ASSIGNMENT                        0x00000c3c
1931 #define BCE_DMA_WCHAN_ASSIGNMENT_0                       (0xfL<<0)
1932 #define BCE_DMA_WCHAN_ASSIGNMENT_1                       (0xfL<<4)
1933 #define BCE_DMA_WCHAN_ASSIGNMENT_2                       (0xfL<<8)
1934 #define BCE_DMA_WCHAN_ASSIGNMENT_3                       (0xfL<<12)
1935 #define BCE_DMA_WCHAN_ASSIGNMENT_4                       (0xfL<<16)
1936 #define BCE_DMA_WCHAN_ASSIGNMENT_5                       (0xfL<<20)
1937 #define BCE_DMA_WCHAN_ASSIGNMENT_6                       (0xfL<<24)
1938 #define BCE_DMA_WCHAN_ASSIGNMENT_7                       (0xfL<<28)
1939
1940 #define BCE_DMA_RCHAN_STAT_00                           0x00000c40
1941 #define BCE_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW    (0xffffffffL<<0)
1942
1943 #define BCE_DMA_RCHAN_STAT_01                           0x00000c44
1944 #define BCE_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH   (0xffffffffL<<0)
1945
1946 #define BCE_DMA_RCHAN_STAT_02                           0x00000c48
1947 #define BCE_DMA_RCHAN_STAT_02_LENGTH                     (0xffffL<<0)
1948 #define BCE_DMA_RCHAN_STAT_02_WORD_SWAP          (1L<<16)
1949 #define BCE_DMA_RCHAN_STAT_02_BYTE_SWAP          (1L<<17)
1950 #define BCE_DMA_RCHAN_STAT_02_PRIORITY_LVL               (1L<<18)
1951
1952 #define BCE_DMA_RCHAN_STAT_10                           0x00000c4c
1953 #define BCE_DMA_RCHAN_STAT_11                           0x00000c50
1954 #define BCE_DMA_RCHAN_STAT_12                           0x00000c54
1955 #define BCE_DMA_RCHAN_STAT_20                           0x00000c58
1956 #define BCE_DMA_RCHAN_STAT_21                           0x00000c5c
1957 #define BCE_DMA_RCHAN_STAT_22                           0x00000c60
1958 #define BCE_DMA_RCHAN_STAT_30                           0x00000c64
1959 #define BCE_DMA_RCHAN_STAT_31                           0x00000c68
1960 #define BCE_DMA_RCHAN_STAT_32                           0x00000c6c
1961 #define BCE_DMA_RCHAN_STAT_40                           0x00000c70
1962 #define BCE_DMA_RCHAN_STAT_41                           0x00000c74
1963 #define BCE_DMA_RCHAN_STAT_42                           0x00000c78
1964 #define BCE_DMA_RCHAN_STAT_50                           0x00000c7c
1965 #define BCE_DMA_RCHAN_STAT_51                           0x00000c80
1966 #define BCE_DMA_RCHAN_STAT_52                           0x00000c84
1967 #define BCE_DMA_RCHAN_STAT_60                           0x00000c88
1968 #define BCE_DMA_RCHAN_STAT_61                           0x00000c8c
1969 #define BCE_DMA_RCHAN_STAT_62                           0x00000c90
1970 #define BCE_DMA_RCHAN_STAT_70                           0x00000c94
1971 #define BCE_DMA_RCHAN_STAT_71                           0x00000c98
1972 #define BCE_DMA_RCHAN_STAT_72                           0x00000c9c
1973 #define BCE_DMA_WCHAN_STAT_00                           0x00000ca0
1974 #define BCE_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW    (0xffffffffL<<0)
1975
1976 #define BCE_DMA_WCHAN_STAT_01                           0x00000ca4
1977 #define BCE_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH   (0xffffffffL<<0)
1978
1979 #define BCE_DMA_WCHAN_STAT_02                           0x00000ca8
1980 #define BCE_DMA_WCHAN_STAT_02_LENGTH                     (0xffffL<<0)
1981 #define BCE_DMA_WCHAN_STAT_02_WORD_SWAP          (1L<<16)
1982 #define BCE_DMA_WCHAN_STAT_02_BYTE_SWAP          (1L<<17)
1983 #define BCE_DMA_WCHAN_STAT_02_PRIORITY_LVL               (1L<<18)
1984
1985 #define BCE_DMA_WCHAN_STAT_10                           0x00000cac
1986 #define BCE_DMA_WCHAN_STAT_11                           0x00000cb0
1987 #define BCE_DMA_WCHAN_STAT_12                           0x00000cb4
1988 #define BCE_DMA_WCHAN_STAT_20                           0x00000cb8
1989 #define BCE_DMA_WCHAN_STAT_21                           0x00000cbc
1990 #define BCE_DMA_WCHAN_STAT_22                           0x00000cc0
1991 #define BCE_DMA_WCHAN_STAT_30                           0x00000cc4
1992 #define BCE_DMA_WCHAN_STAT_31                           0x00000cc8
1993 #define BCE_DMA_WCHAN_STAT_32                           0x00000ccc
1994 #define BCE_DMA_WCHAN_STAT_40                           0x00000cd0
1995 #define BCE_DMA_WCHAN_STAT_41                           0x00000cd4
1996 #define BCE_DMA_WCHAN_STAT_42                           0x00000cd8
1997 #define BCE_DMA_WCHAN_STAT_50                           0x00000cdc
1998 #define BCE_DMA_WCHAN_STAT_51                           0x00000ce0
1999 #define BCE_DMA_WCHAN_STAT_52                           0x00000ce4
2000 #define BCE_DMA_WCHAN_STAT_60                           0x00000ce8
2001 #define BCE_DMA_WCHAN_STAT_61                           0x00000cec
2002 #define BCE_DMA_WCHAN_STAT_62                           0x00000cf0
2003 #define BCE_DMA_WCHAN_STAT_70                           0x00000cf4
2004 #define BCE_DMA_WCHAN_STAT_71                           0x00000cf8
2005 #define BCE_DMA_WCHAN_STAT_72                           0x00000cfc
2006 #define BCE_DMA_ARB_STAT_00                             0x00000d00
2007 #define BCE_DMA_ARB_STAT_00_MASTER                       (0xffffL<<0)
2008 #define BCE_DMA_ARB_STAT_00_MASTER_ENC                   (0xffL<<16)
2009 #define BCE_DMA_ARB_STAT_00_CUR_BINMSTR          (0xffL<<24)
2010
2011 #define BCE_DMA_ARB_STAT_01                             0x00000d04
2012 #define BCE_DMA_ARB_STAT_01_LPR_RPTR                     (0xfL<<0)
2013 #define BCE_DMA_ARB_STAT_01_LPR_WPTR                     (0xfL<<4)
2014 #define BCE_DMA_ARB_STAT_01_LPB_RPTR                     (0xfL<<8)
2015 #define BCE_DMA_ARB_STAT_01_LPB_WPTR                     (0xfL<<12)
2016 #define BCE_DMA_ARB_STAT_01_HPR_RPTR                     (0xfL<<16)
2017 #define BCE_DMA_ARB_STAT_01_HPR_WPTR                     (0xfL<<20)
2018 #define BCE_DMA_ARB_STAT_01_HPB_RPTR                     (0xfL<<24)
2019 #define BCE_DMA_ARB_STAT_01_HPB_WPTR                     (0xfL<<28)
2020
2021 #define BCE_DMA_FUSE_CTRL0_CMD                          0x00000f00
2022 #define BCE_DMA_FUSE_CTRL0_CMD_PWRUP_DONE                (1L<<0)
2023 #define BCE_DMA_FUSE_CTRL0_CMD_SHIFT_DONE                (1L<<1)
2024 #define BCE_DMA_FUSE_CTRL0_CMD_SHIFT                     (1L<<2)
2025 #define BCE_DMA_FUSE_CTRL0_CMD_LOAD                      (1L<<3)
2026 #define BCE_DMA_FUSE_CTRL0_CMD_SEL                       (0xfL<<8)
2027
2028 #define BCE_DMA_FUSE_CTRL0_DATA                 0x00000f04
2029 #define BCE_DMA_FUSE_CTRL1_CMD                          0x00000f08
2030 #define BCE_DMA_FUSE_CTRL1_CMD_PWRUP_DONE                (1L<<0)
2031 #define BCE_DMA_FUSE_CTRL1_CMD_SHIFT_DONE                (1L<<1)
2032 #define BCE_DMA_FUSE_CTRL1_CMD_SHIFT                     (1L<<2)
2033 #define BCE_DMA_FUSE_CTRL1_CMD_LOAD                      (1L<<3)
2034 #define BCE_DMA_FUSE_CTRL1_CMD_SEL                       (0xfL<<8)
2035
2036 #define BCE_DMA_FUSE_CTRL1_DATA                 0x00000f0c
2037 #define BCE_DMA_FUSE_CTRL2_CMD                          0x00000f10
2038 #define BCE_DMA_FUSE_CTRL2_CMD_PWRUP_DONE                (1L<<0)
2039 #define BCE_DMA_FUSE_CTRL2_CMD_SHIFT_DONE                (1L<<1)
2040 #define BCE_DMA_FUSE_CTRL2_CMD_SHIFT                     (1L<<2)
2041 #define BCE_DMA_FUSE_CTRL2_CMD_LOAD                      (1L<<3)
2042 #define BCE_DMA_FUSE_CTRL2_CMD_SEL                       (0xfL<<8)
2043
2044 #define BCE_DMA_FUSE_CTRL2_DATA                 0x00000f14
2045
2046
2047 /*
2048  *  context_reg definition
2049  *  offset: 0x1000
2050  */
2051 #define BCE_CTX_COMMAND                         0x00001000
2052 #define BCE_CTX_COMMAND_ENABLED                  (1L<<0)
2053
2054 #define BCE_CTX_STATUS                                  0x00001004
2055 #define BCE_CTX_STATUS_LOCK_WAIT                         (1L<<0)
2056 #define BCE_CTX_STATUS_READ_STAT                         (1L<<16)
2057 #define BCE_CTX_STATUS_WRITE_STAT                        (1L<<17)
2058 #define BCE_CTX_STATUS_ACC_STALL_STAT                    (1L<<18)
2059 #define BCE_CTX_STATUS_LOCK_STALL_STAT                   (1L<<19)
2060
2061 #define BCE_CTX_VIRT_ADDR                               0x00001008
2062 #define BCE_CTX_VIRT_ADDR_VIRT_ADDR                      (0x7fffL<<6)
2063
2064 #define BCE_CTX_PAGE_TBL                                0x0000100c
2065 #define BCE_CTX_PAGE_TBL_PAGE_TBL                        (0x3fffL<<6)
2066
2067 #define BCE_CTX_DATA_ADR                                0x00001010
2068 #define BCE_CTX_DATA_ADR_DATA_ADR                        (0x7ffffL<<2)
2069
2070 #define BCE_CTX_DATA                                    0x00001014
2071 #define BCE_CTX_LOCK                                    0x00001018
2072 #define BCE_CTX_LOCK_TYPE                                (0x7L<<0)
2073 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_VOID                 (0x0L<<0)
2074 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE             (0x7L<<0)
2075 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL             (0x1L<<0)
2076 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TX                   (0x2L<<0)
2077 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TIMER                (0x4L<<0)
2078 #define BCE_CTX_LOCK_CID_VALUE                           (0x3fffL<<7)
2079 #define BCE_CTX_LOCK_GRANTED                             (1L<<26)
2080 #define BCE_CTX_LOCK_MODE                                (0x7L<<27)
2081 #define BCE_CTX_LOCK_MODE_UNLOCK                         (0x0L<<27)
2082 #define BCE_CTX_LOCK_MODE_IMMEDIATE                      (0x1L<<27)
2083 #define BCE_CTX_LOCK_MODE_SURE                           (0x2L<<27)
2084 #define BCE_CTX_LOCK_STATUS                              (1L<<30)
2085 #define BCE_CTX_LOCK_REQ                                 (1L<<31)
2086
2087 #define BCE_CTX_ACCESS_STATUS                           0x00001040
2088 #define BCE_CTX_ACCESS_STATUS_MASTERENCODED              (0xfL<<0)
2089 #define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYSM             (0x3L<<10)
2090 #define BCE_CTX_ACCESS_STATUS_PAGETABLEINITSM            (0x3L<<12)
2091 #define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM         (0x3L<<14)
2092 #define BCE_CTX_ACCESS_STATUS_QUALIFIED_REQUEST  (0x7ffL<<17)
2093
2094 #define BCE_CTX_DBG_LOCK_STATUS                 0x00001044
2095 #define BCE_CTX_DBG_LOCK_STATUS_SM                       (0x3ffL<<0)
2096 #define BCE_CTX_DBG_LOCK_STATUS_MATCH                    (0x3ffL<<22)
2097
2098 #define BCE_CTX_CHNL_LOCK_STATUS_0                      0x00001080
2099 #define BCE_CTX_CHNL_LOCK_STATUS_0_CID                   (0x3fffL<<0)
2100 #define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE          (0x3L<<14)
2101 #define BCE_CTX_CHNL_LOCK_STATUS_0_MODE          (1L<<16)
2102
2103 #define BCE_CTX_CHNL_LOCK_STATUS_1                      0x00001084
2104 #define BCE_CTX_CHNL_LOCK_STATUS_2                      0x00001088
2105 #define BCE_CTX_CHNL_LOCK_STATUS_3                      0x0000108c
2106 #define BCE_CTX_CHNL_LOCK_STATUS_4                      0x00001090
2107 #define BCE_CTX_CHNL_LOCK_STATUS_5                      0x00001094
2108 #define BCE_CTX_CHNL_LOCK_STATUS_6                      0x00001098
2109 #define BCE_CTX_CHNL_LOCK_STATUS_7                      0x0000109c
2110 #define BCE_CTX_CHNL_LOCK_STATUS_8                      0x000010a0
2111
2112
2113 /*
2114  *  emac_reg definition
2115  *  offset: 0x1400
2116  */
2117 #define BCE_EMAC_MODE                                   0x00001400
2118 #define BCE_EMAC_MODE_RESET                              (1L<<0)
2119 #define BCE_EMAC_MODE_HALF_DUPLEX                        (1L<<1)
2120 #define BCE_EMAC_MODE_PORT                               (0x3L<<2)
2121 #define BCE_EMAC_MODE_PORT_NONE                  (0L<<2)
2122 #define BCE_EMAC_MODE_PORT_MII                           (1L<<2)
2123 #define BCE_EMAC_MODE_PORT_GMII                  (2L<<2)
2124 #define BCE_EMAC_MODE_PORT_MII_10                        (3L<<2)
2125 #define BCE_EMAC_MODE_MAC_LOOP                           (1L<<4)
2126 #define BCE_EMAC_MODE_25G                                (1L<<5)
2127 #define BCE_EMAC_MODE_TAGGED_MAC_CTL                     (1L<<7)
2128 #define BCE_EMAC_MODE_TX_BURST                           (1L<<8)
2129 #define BCE_EMAC_MODE_MAX_DEFER_DROP_ENA                 (1L<<9)
2130 #define BCE_EMAC_MODE_EXT_LINK_POL                       (1L<<10)
2131 #define BCE_EMAC_MODE_FORCE_LINK                         (1L<<11)
2132 #define BCE_EMAC_MODE_MPKT                               (1L<<18)
2133 #define BCE_EMAC_MODE_MPKT_RCVD                  (1L<<19)
2134 #define BCE_EMAC_MODE_ACPI_RCVD                  (1L<<20)
2135
2136 #define BCE_EMAC_STATUS                         0x00001404
2137 #define BCE_EMAC_STATUS_LINK                             (1L<<11)
2138 #define BCE_EMAC_STATUS_LINK_CHANGE                      (1L<<12)
2139 #define BCE_EMAC_STATUS_MI_COMPLETE                      (1L<<22)
2140 #define BCE_EMAC_STATUS_MI_INT                           (1L<<23)
2141 #define BCE_EMAC_STATUS_AP_ERROR                         (1L<<24)
2142 #define BCE_EMAC_STATUS_PARITY_ERROR_STATE               (1L<<31)
2143
2144 #define BCE_EMAC_ATTENTION_ENA                          0x00001408
2145 #define BCE_EMAC_ATTENTION_ENA_LINK                      (1L<<11)
2146 #define BCE_EMAC_ATTENTION_ENA_MI_COMPLETE               (1L<<22)
2147 #define BCE_EMAC_ATTENTION_ENA_MI_INT                    (1L<<23)
2148 #define BCE_EMAC_ATTENTION_ENA_AP_ERROR          (1L<<24)
2149
2150 #define BCE_EMAC_LED                                    0x0000140c
2151 #define BCE_EMAC_LED_OVERRIDE                            (1L<<0)
2152 #define BCE_EMAC_LED_1000MB_OVERRIDE                     (1L<<1)
2153 #define BCE_EMAC_LED_100MB_OVERRIDE                      (1L<<2)
2154 #define BCE_EMAC_LED_10MB_OVERRIDE                       (1L<<3)
2155 #define BCE_EMAC_LED_TRAFFIC_OVERRIDE                    (1L<<4)
2156 #define BCE_EMAC_LED_BLNK_TRAFFIC                        (1L<<5)
2157 #define BCE_EMAC_LED_TRAFFIC                             (1L<<6)
2158 #define BCE_EMAC_LED_1000MB                              (1L<<7)
2159 #define BCE_EMAC_LED_100MB                               (1L<<8)
2160 #define BCE_EMAC_LED_10MB                                (1L<<9)
2161 #define BCE_EMAC_LED_TRAFFIC_STAT                        (1L<<10)
2162 #define BCE_EMAC_LED_BLNK_RATE                           (0xfffL<<19)
2163 #define BCE_EMAC_LED_BLNK_RATE_ENA                       (1L<<31)
2164
2165 #define BCE_EMAC_MAC_MATCH0                             0x00001410
2166 #define BCE_EMAC_MAC_MATCH1                             0x00001414
2167 #define BCE_EMAC_MAC_MATCH2                             0x00001418
2168 #define BCE_EMAC_MAC_MATCH3                             0x0000141c
2169 #define BCE_EMAC_MAC_MATCH4                             0x00001420
2170 #define BCE_EMAC_MAC_MATCH5                             0x00001424
2171 #define BCE_EMAC_MAC_MATCH6                             0x00001428
2172 #define BCE_EMAC_MAC_MATCH7                             0x0000142c
2173 #define BCE_EMAC_MAC_MATCH8                             0x00001430
2174 #define BCE_EMAC_MAC_MATCH9                             0x00001434
2175 #define BCE_EMAC_MAC_MATCH10                            0x00001438
2176 #define BCE_EMAC_MAC_MATCH11                            0x0000143c
2177 #define BCE_EMAC_MAC_MATCH12                            0x00001440
2178 #define BCE_EMAC_MAC_MATCH13                            0x00001444
2179 #define BCE_EMAC_MAC_MATCH14                            0x00001448
2180 #define BCE_EMAC_MAC_MATCH15                            0x0000144c
2181 #define BCE_EMAC_MAC_MATCH16                            0x00001450
2182 #define BCE_EMAC_MAC_MATCH17                            0x00001454
2183 #define BCE_EMAC_MAC_MATCH18                            0x00001458
2184 #define BCE_EMAC_MAC_MATCH19                            0x0000145c
2185 #define BCE_EMAC_MAC_MATCH20                            0x00001460
2186 #define BCE_EMAC_MAC_MATCH21                            0x00001464
2187 #define BCE_EMAC_MAC_MATCH22                            0x00001468
2188 #define BCE_EMAC_MAC_MATCH23                            0x0000146c
2189 #define BCE_EMAC_MAC_MATCH24                            0x00001470
2190 #define BCE_EMAC_MAC_MATCH25                            0x00001474
2191 #define BCE_EMAC_MAC_MATCH26                            0x00001478
2192 #define BCE_EMAC_MAC_MATCH27                            0x0000147c
2193 #define BCE_EMAC_MAC_MATCH28                            0x00001480
2194 #define BCE_EMAC_MAC_MATCH29                            0x00001484
2195 #define BCE_EMAC_MAC_MATCH30                            0x00001488
2196 #define BCE_EMAC_MAC_MATCH31                            0x0000148c
2197 #define BCE_EMAC_BACKOFF_SEED                           0x00001498
2198 #define BCE_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED  (0x3ffL<<0)
2199
2200 #define BCE_EMAC_RX_MTU_SIZE                            0x0000149c
2201 #define BCE_EMAC_RX_MTU_SIZE_MTU_SIZE                    (0xffffL<<0)
2202 #define BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA                   (1L<<31)
2203
2204 #define BCE_EMAC_SERDES_CNTL                            0x000014a4
2205 #define BCE_EMAC_SERDES_CNTL_RXR                         (0x7L<<0)
2206 #define BCE_EMAC_SERDES_CNTL_RXG                         (0x3L<<3)
2207 #define BCE_EMAC_SERDES_CNTL_RXCKSEL                     (1L<<6)
2208 #define BCE_EMAC_SERDES_CNTL_TXBIAS                      (0x7L<<7)
2209 #define BCE_EMAC_SERDES_CNTL_BGMAX                       (1L<<10)
2210 #define BCE_EMAC_SERDES_CNTL_BGMIN                       (1L<<11)
2211 #define BCE_EMAC_SERDES_CNTL_TXMODE                      (1L<<12)
2212 #define BCE_EMAC_SERDES_CNTL_TXEDGE                      (1L<<13)
2213 #define BCE_EMAC_SERDES_CNTL_SERDES_MODE                 (1L<<14)
2214 #define BCE_EMAC_SERDES_CNTL_PLLTEST                     (1L<<15)
2215 #define BCE_EMAC_SERDES_CNTL_CDET_EN                     (1L<<16)
2216 #define BCE_EMAC_SERDES_CNTL_TBI_LBK                     (1L<<17)
2217 #define BCE_EMAC_SERDES_CNTL_REMOTE_LBK          (1L<<18)
2218 #define BCE_EMAC_SERDES_CNTL_REV_PHASE                   (1L<<19)
2219 #define BCE_EMAC_SERDES_CNTL_REGCTL12                    (0x3L<<20)
2220 #define BCE_EMAC_SERDES_CNTL_REGCTL25                    (0x3L<<22)
2221
2222 #define BCE_EMAC_SERDES_STATUS                          0x000014a8
2223 #define BCE_EMAC_SERDES_STATUS_RX_STAT                   (0xffL<<0)
2224 #define BCE_EMAC_SERDES_STATUS_COMMA_DET                 (1L<<8)
2225
2226 #define BCE_EMAC_MDIO_COMM                              0x000014ac
2227 #define BCE_EMAC_MDIO_COMM_DATA                  (0xffffL<<0)
2228 #define BCE_EMAC_MDIO_COMM_REG_ADDR                      (0x1fL<<16)
2229 #define BCE_EMAC_MDIO_COMM_PHY_ADDR                      (0x1fL<<21)
2230 #define BCE_EMAC_MDIO_COMM_COMMAND                       (0x3L<<26)
2231 #define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0           (0L<<26)
2232 #define BCE_EMAC_MDIO_COMM_COMMAND_WRITE                 (1L<<26)
2233 #define BCE_EMAC_MDIO_COMM_COMMAND_READ          (2L<<26)
2234 #define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3           (3L<<26)
2235 #define BCE_EMAC_MDIO_COMM_FAIL                  (1L<<28)
2236 #define BCE_EMAC_MDIO_COMM_START_BUSY                    (1L<<29)
2237 #define BCE_EMAC_MDIO_COMM_DISEXT                        (1L<<30)
2238
2239 #define BCE_EMAC_MDIO_STATUS                            0x000014b0
2240 #define BCE_EMAC_MDIO_STATUS_LINK                        (1L<<0)
2241 #define BCE_EMAC_MDIO_STATUS_10MB                        (1L<<1)
2242
2243 #define BCE_EMAC_MDIO_MODE                              0x000014b4
2244 #define BCE_EMAC_MDIO_MODE_SHORT_PREAMBLE                (1L<<1)
2245 #define BCE_EMAC_MDIO_MODE_AUTO_POLL                     (1L<<4)
2246 #define BCE_EMAC_MDIO_MODE_BIT_BANG                      (1L<<8)
2247 #define BCE_EMAC_MDIO_MODE_MDIO                  (1L<<9)
2248 #define BCE_EMAC_MDIO_MODE_MDIO_OE                       (1L<<10)
2249 #define BCE_EMAC_MDIO_MODE_MDC                           (1L<<11)
2250 #define BCE_EMAC_MDIO_MODE_MDINT                         (1L<<12)
2251 #define BCE_EMAC_MDIO_MODE_CLOCK_CNT                     (0x1fL<<16)
2252
2253 #define BCE_EMAC_MDIO_AUTO_STATUS                       0x000014b8
2254 #define BCE_EMAC_MDIO_AUTO_STATUS_AUTO_ERR               (1L<<0)
2255
2256 #define BCE_EMAC_TX_MODE                                0x000014bc
2257 #define BCE_EMAC_TX_MODE_RESET                           (1L<<0)
2258 #define BCE_EMAC_TX_MODE_EXT_PAUSE_EN                    (1L<<3)
2259 #define BCE_EMAC_TX_MODE_FLOW_EN                         (1L<<4)
2260 #define BCE_EMAC_TX_MODE_BIG_BACKOFF                     (1L<<5)
2261 #define BCE_EMAC_TX_MODE_LONG_PAUSE                      (1L<<6)
2262 #define BCE_EMAC_TX_MODE_LINK_AWARE                      (1L<<7)
2263
2264 #define BCE_EMAC_TX_STATUS                              0x000014c0
2265 #define BCE_EMAC_TX_STATUS_XOFFED                        (1L<<0)
2266 #define BCE_EMAC_TX_STATUS_XOFF_SENT                     (1L<<1)
2267 #define BCE_EMAC_TX_STATUS_XON_SENT                      (1L<<2)
2268 #define BCE_EMAC_TX_STATUS_LINK_UP                       (1L<<3)
2269 #define BCE_EMAC_TX_STATUS_UNDERRUN                      (1L<<4)
2270
2271 #define BCE_EMAC_TX_LENGTHS                             0x000014c4
2272 #define BCE_EMAC_TX_LENGTHS_SLOT                         (0xffL<<0)
2273 #define BCE_EMAC_TX_LENGTHS_IPG                  (0xfL<<8)
2274 #define BCE_EMAC_TX_LENGTHS_IPG_CRS                      (0x3L<<12)
2275
2276 #define BCE_EMAC_RX_MODE                                0x000014c8
2277 #define BCE_EMAC_RX_MODE_RESET                           (1L<<0)
2278 #define BCE_EMAC_RX_MODE_FLOW_EN                         (1L<<2)
2279 #define BCE_EMAC_RX_MODE_KEEP_MAC_CONTROL                (1L<<3)
2280 #define BCE_EMAC_RX_MODE_KEEP_PAUSE                      (1L<<4)
2281 #define BCE_EMAC_RX_MODE_ACCEPT_OVERSIZE                 (1L<<5)
2282 #define BCE_EMAC_RX_MODE_ACCEPT_RUNTS                    (1L<<6)
2283 #define BCE_EMAC_RX_MODE_LLC_CHK                         (1L<<7)
2284 #define BCE_EMAC_RX_MODE_PROMISCUOUS                     (1L<<8)
2285 #define BCE_EMAC_RX_MODE_NO_CRC_CHK                      (1L<<9)
2286 #define BCE_EMAC_RX_MODE_KEEP_VLAN_TAG                   (1L<<10)
2287 #define BCE_EMAC_RX_MODE_FILT_BROADCAST          (1L<<11)
2288 #define BCE_EMAC_RX_MODE_SORT_MODE                       (1L<<12)
2289
2290 #define BCE_EMAC_RX_STATUS                              0x000014cc
2291 #define BCE_EMAC_RX_STATUS_FFED                  (1L<<0)
2292 #define BCE_EMAC_RX_STATUS_FF_RECEIVED                   (1L<<1)
2293 #define BCE_EMAC_RX_STATUS_N_RECEIVED                    (1L<<2)
2294
2295 #define BCE_EMAC_MULTICAST_HASH0                        0x000014d0
2296 #define BCE_EMAC_MULTICAST_HASH1                        0x000014d4
2297 #define BCE_EMAC_MULTICAST_HASH2                        0x000014d8
2298 #define BCE_EMAC_MULTICAST_HASH3                        0x000014dc
2299 #define BCE_EMAC_MULTICAST_HASH4                        0x000014e0
2300 #define BCE_EMAC_MULTICAST_HASH5                        0x000014e4
2301 #define BCE_EMAC_MULTICAST_HASH6                        0x000014e8
2302 #define BCE_EMAC_MULTICAST_HASH7                        0x000014ec
2303 #define BCE_EMAC_RX_STAT_IFHCINOCTETS                   0x00001500
2304 #define BCE_EMAC_RX_STAT_IFHCINBADOCTETS                0x00001504
2305 #define BCE_EMAC_RX_STAT_ETHERSTATSFRAGMENTS            0x00001508
2306 #define BCE_EMAC_RX_STAT_IFHCINUCASTPKTS                0x0000150c
2307 #define BCE_EMAC_RX_STAT_IFHCINMULTICASTPKTS            0x00001510
2308 #define BCE_EMAC_RX_STAT_IFHCINBROADCASTPKTS            0x00001514
2309 #define BCE_EMAC_RX_STAT_DOT3STATSFCSERRORS             0x00001518
2310 #define BCE_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS       0x0000151c
2311 #define BCE_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS    0x00001520
2312 #define BCE_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524
2313 #define BCE_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED        0x00001528
2314 #define BCE_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED       0x0000152c
2315 #define BCE_EMAC_RX_STAT_XOFFSTATEENTERED               0x00001530
2316 #define BCE_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534
2317 #define BCE_EMAC_RX_STAT_ETHERSTATSJABBERS              0x00001538
2318 #define BCE_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS        0x0000153c
2319 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540
2320 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS      0x00001544
2321 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS     0x00001548
2322 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS     0x0000154c
2323 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS    0x00001550
2324 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS   0x00001554
2325 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS   0x00001558
2326 #define BCE_EMAC_RXMAC_DEBUG0                           0x0000155c
2327 #define BCE_EMAC_RXMAC_DEBUG1                           0x00001560
2328 #define BCE_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT       (1L<<0)
2329 #define BCE_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE           (1L<<1)
2330 #define BCE_EMAC_RXMAC_DEBUG1_BAD_CRC                    (1L<<2)
2331 #define BCE_EMAC_RXMAC_DEBUG1_RX_ERROR                   (1L<<3)
2332 #define BCE_EMAC_RXMAC_DEBUG1_ALIGN_ERROR                (1L<<4)
2333 #define BCE_EMAC_RXMAC_DEBUG1_LAST_DATA          (1L<<5)
2334 #define BCE_EMAC_RXMAC_DEBUG1_ODD_BYTE_START             (1L<<6)
2335 #define BCE_EMAC_RXMAC_DEBUG1_BYTE_COUNT                 (0xffffL<<7)
2336 #define BCE_EMAC_RXMAC_DEBUG1_SLOT_TIME          (0xffL<<23)
2337
2338 #define BCE_EMAC_RXMAC_DEBUG2                           0x00001564
2339 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE                   (0x7L<<0)
2340 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE              (0x0L<<0)
2341 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SFD               (0x1L<<0)
2342 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DATA              (0x2L<<0)
2343 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP             (0x3L<<0)
2344 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_EXT               (0x4L<<0)
2345 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DROP              (0x5L<<0)
2346 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP             (0x6L<<0)
2347 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_FC                (0x7L<<0)
2348 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE          (0xfL<<3)
2349 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE             (0x0L<<3)
2350 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0            (0x1L<<3)
2351 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1            (0x2L<<3)
2352 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2            (0x3L<<3)
2353 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3            (0x4L<<3)
2354 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT            (0x5L<<3)
2355 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT             (0x6L<<3)
2356 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS           (0x7L<<3)
2357 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST             (0x8L<<3)
2358 #define BCE_EMAC_RXMAC_DEBUG2_BYTE_IN                    (0xffL<<7)
2359 #define BCE_EMAC_RXMAC_DEBUG2_FALSEC                     (1L<<15)
2360 #define BCE_EMAC_RXMAC_DEBUG2_TAGGED                     (1L<<16)
2361 #define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE                (1L<<18)
2362 #define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE           (0L<<18)
2363 #define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED         (1L<<18)
2364 #define BCE_EMAC_RXMAC_DEBUG2_SE_COUNTER                 (0xfL<<19)
2365 #define BCE_EMAC_RXMAC_DEBUG2_QUANTA                     (0x1fL<<23)
2366
2367 #define BCE_EMAC_RXMAC_DEBUG3                           0x00001568
2368 #define BCE_EMAC_RXMAC_DEBUG3_PAUSE_CTR          (0xffffL<<0)
2369 #define BCE_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR              (0xffffL<<16)
2370
2371 #define BCE_EMAC_RXMAC_DEBUG4                           0x0000156c
2372 #define BCE_EMAC_RXMAC_DEBUG4_TYPE_FIELD                 (0xffffL<<0)
2373 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE                 (0x3fL<<16)
2374 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE            (0x0L<<16)
2375 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2           (0x1L<<16)
2376 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3           (0x2L<<16)
2377 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI             (0x3L<<16)
2378 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2           (0x7L<<16)
2379 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3           (0x5L<<16)
2380 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1            (0x6L<<16)
2381 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2            (0x7L<<16)
2382 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3            (0x8L<<16)
2383 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2             (0x9L<<16)
2384 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3             (0xaL<<16)
2385 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1  (0xeL<<16)
2386 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2  (0xfL<<16)
2387 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK  (0x10L<<16)
2388 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC              (0x11L<<16)
2389 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2             (0x12L<<16)
2390 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3             (0x13L<<16)
2391 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1            (0x14L<<16)
2392 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2            (0x15L<<16)
2393 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3            (0x16L<<16)
2394 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE           (0x17L<<16)
2395 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC              (0x18L<<16)
2396 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE           (0x19L<<16)
2397 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD             (0x1aL<<16)
2398 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC             (0x1bL<<16)
2399 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH           (0x1cL<<16)
2400 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF            (0x1dL<<16)
2401 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XON             (0x1eL<<16)
2402 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED  (0x1fL<<16)
2403 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED         (0x20L<<16)
2404 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE           (0x21L<<16)
2405 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL            (0x22L<<16)
2406 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1            (0x23L<<16)
2407 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2            (0x24L<<16)
2408 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3            (0x25L<<16)
2409 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE           (0x26L<<16)
2410 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE  (0x27L<<16)
2411 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL           (0x28L<<16)
2412 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE           (0x29L<<16)
2413 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP            (0x2aL<<16)
2414 #define BCE_EMAC_RXMAC_DEBUG4_DROP_PKT                   (1L<<22)
2415 #define BCE_EMAC_RXMAC_DEBUG4_SLOT_FILLED                (1L<<23)
2416 #define BCE_EMAC_RXMAC_DEBUG4_FALSE_CARRIER              (1L<<24)
2417 #define BCE_EMAC_RXMAC_DEBUG4_LAST_DATA          (1L<<25)
2418 #define BCE_EMAC_RXMAC_DEBUG4_sfd_FOUND          (1L<<26)
2419 #define BCE_EMAC_RXMAC_DEBUG4_ADVANCE                    (1L<<27)
2420 #define BCE_EMAC_RXMAC_DEBUG4_START                      (1L<<28)
2421
2422 #define BCE_EMAC_RXMAC_DEBUG5                           0x00001570
2423 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM                   (0x7L<<0)
2424 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE              (0L<<0)
2425 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF  (1L<<0)
2426 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT         (2L<<0)
2427 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC      (3L<<0)
2428 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE       (4L<<0)
2429 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL       (5L<<0)
2430 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT     (6L<<0)
2431 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1                 (0x7L<<4)
2432 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW             (0x0L<<4)
2433 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT            (0x1L<<4)
2434 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF            (0x2L<<4)
2435 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF            (0x3L<<4)
2436 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF             (0x4L<<4)
2437 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF           (0x6L<<4)
2438 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF           (0x7L<<4)
2439 #define BCE_EMAC_RXMAC_DEBUG5_EOF_DETECTED               (1L<<7)
2440 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF0                 (0x7L<<8)
2441 #define BCE_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL  (1L<<11)
2442 #define BCE_EMAC_RXMAC_DEBUG5_LOAD_CCODE                 (1L<<12)
2443 #define BCE_EMAC_RXMAC_DEBUG5_LOAD_DATA          (1L<<13)
2444 #define BCE_EMAC_RXMAC_DEBUG5_LOAD_STAT          (1L<<14)
2445 #define BCE_EMAC_RXMAC_DEBUG5_CLR_STAT                   (1L<<15)
2446 #define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE              (0x3L<<16)
2447 #define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT             (1L<<19)
2448 #define BCE_EMAC_RXMAC_DEBUG5_FMLEN                      (0xfffL<<20)
2449
2450 #define BCE_EMAC_RX_STAT_AC0                            0x00001580
2451 #define BCE_EMAC_RX_STAT_AC1                            0x00001584
2452 #define BCE_EMAC_RX_STAT_AC2                            0x00001588
2453 #define BCE_EMAC_RX_STAT_AC3                            0x0000158c
2454 #define BCE_EMAC_RX_STAT_AC4                            0x00001590
2455 #define BCE_EMAC_RX_STAT_AC5                            0x00001594
2456 #define BCE_EMAC_RX_STAT_AC6                            0x00001598
2457 #define BCE_EMAC_RX_STAT_AC7                            0x0000159c
2458 #define BCE_EMAC_RX_STAT_AC8                            0x000015a0
2459 #define BCE_EMAC_RX_STAT_AC9                            0x000015a4
2460 #define BCE_EMAC_RX_STAT_AC10                           0x000015a8
2461 #define BCE_EMAC_RX_STAT_AC11                           0x000015ac
2462 #define BCE_EMAC_RX_STAT_AC12                           0x000015b0
2463 #define BCE_EMAC_RX_STAT_AC13                           0x000015b4
2464 #define BCE_EMAC_RX_STAT_AC14                           0x000015b8
2465 #define BCE_EMAC_RX_STAT_AC15                           0x000015bc
2466 #define BCE_EMAC_RX_STAT_AC16                           0x000015c0
2467 #define BCE_EMAC_RX_STAT_AC17                           0x000015c4
2468 #define BCE_EMAC_RX_STAT_AC18                           0x000015c8
2469 #define BCE_EMAC_RX_STAT_AC19                           0x000015cc
2470 #define BCE_EMAC_RX_STAT_AC20                           0x000015d0
2471 #define BCE_EMAC_RX_STAT_AC21                           0x000015d4
2472 #define BCE_EMAC_RX_STAT_AC22                           0x000015d8
2473 #define BCE_EMAC_RXMAC_SUC_DBG_OVERRUNVEC               0x000015dc
2474 #define BCE_EMAC_TX_STAT_IFHCOUTOCTETS                  0x00001600
2475 #define BCE_EMAC_TX_STAT_IFHCOUTBADOCTETS               0x00001604
2476 #define BCE_EMAC_TX_STAT_ETHERSTATSCOLLISIONS           0x00001608
2477 #define BCE_EMAC_TX_STAT_OUTXONSENT                     0x0000160c
2478 #define BCE_EMAC_TX_STAT_OUTXOFFSENT                    0x00001610
2479 #define BCE_EMAC_TX_STAT_FLOWCONTROLDONE                0x00001614
2480 #define BCE_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618
2481 #define BCE_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES       0x0000161c
2482 #define BCE_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620
2483 #define BCE_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS   0x00001624
2484 #define BCE_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS        0x00001628
2485 #define BCE_EMAC_TX_STAT_IFHCOUTUCASTPKTS               0x0000162c
2486 #define BCE_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS           0x00001630
2487 #define BCE_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS           0x00001634
2488 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638
2489 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS      0x0000163c
2490 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS     0x00001640
2491 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS     0x00001644
2492 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS    0x00001648
2493 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS   0x0000164c
2494 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS   0x00001650
2495 #define BCE_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS     0x00001654
2496 #define BCE_EMAC_TXMAC_DEBUG0                           0x00001658
2497 #define BCE_EMAC_TXMAC_DEBUG1                           0x0000165c
2498 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE          (0xfL<<0)
2499 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE             (0x0L<<0)
2500 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_START0           (0x1L<<0)
2501 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0            (0x4L<<0)
2502 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1            (0x5L<<0)
2503 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2            (0x6L<<0)
2504 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3            (0x7L<<0)
2505 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0            (0x8L<<0)
2506 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1            (0x9L<<0)
2507 #define BCE_EMAC_TXMAC_DEBUG1_CRS_ENABLE                 (1L<<4)
2508 #define BCE_EMAC_TXMAC_DEBUG1_BAD_CRC                    (1L<<5)
2509 #define BCE_EMAC_TXMAC_DEBUG1_SE_COUNTER                 (0xfL<<6)
2510 #define BCE_EMAC_TXMAC_DEBUG1_SEND_PAUSE                 (1L<<10)
2511 #define BCE_EMAC_TXMAC_DEBUG1_LATE_COLLISION             (1L<<11)
2512 #define BCE_EMAC_TXMAC_DEBUG1_MAX_DEFER          (1L<<12)
2513 #define BCE_EMAC_TXMAC_DEBUG1_DEFERRED                   (1L<<13)
2514 #define BCE_EMAC_TXMAC_DEBUG1_ONE_BYTE                   (1L<<14)
2515 #define BCE_EMAC_TXMAC_DEBUG1_IPG_TIME                   (0xfL<<15)
2516 #define BCE_EMAC_TXMAC_DEBUG1_SLOT_TIME          (0xffL<<19)
2517
2518 #define BCE_EMAC_TXMAC_DEBUG2                           0x00001660
2519 #define BCE_EMAC_TXMAC_DEBUG2_BACK_OFF                   (0x3ffL<<0)
2520 #define BCE_EMAC_TXMAC_DEBUG2_BYTE_COUNT                 (0xffffL<<10)
2521 #define BCE_EMAC_TXMAC_DEBUG2_COL_COUNT          (0x1fL<<26)
2522 #define BCE_EMAC_TXMAC_DEBUG2_COL_BIT                    (1L<<31)
2523
2524 #define BCE_EMAC_TXMAC_DEBUG3                           0x00001664
2525 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE                   (0xfL<<0)
2526 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE              (0x0L<<0)
2527 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1              (0x1L<<0)
2528 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2              (0x2L<<0)
2529 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SFD               (0x3L<<0)
2530 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_DATA              (0x4L<<0)
2531 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1              (0x5L<<0)
2532 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2              (0x6L<<0)
2533 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EXT               (0x7L<<0)
2534 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATB             (0x8L<<0)
2535 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATG             (0x9L<<0)
2536 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_JAM               (0xaL<<0)
2537 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM              (0xbL<<0)
2538 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM              (0xcL<<0)
2539 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT             (0xdL<<0)
2540 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF           (0xeL<<0)
2541 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE                 (0x7L<<4)
2542 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE            (0x0L<<4)
2543 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT            (0x1L<<4)
2544 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI             (0x2L<<4)
2545 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_MC              (0x3L<<4)
2546 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2             (0x4L<<4)
2547 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3             (0x5L<<4)
2548 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC              (0x6L<<4)
2549 #define BCE_EMAC_TXMAC_DEBUG3_CRS_DONE                   (1L<<7)
2550 #define BCE_EMAC_TXMAC_DEBUG3_XOFF                       (1L<<8)
2551 #define BCE_EMAC_TXMAC_DEBUG3_SE_COUNTER                 (0xfL<<9)
2552 #define BCE_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER             (0x1fL<<13)
2553
2554 #define BCE_EMAC_TXMAC_DEBUG4                           0x00001668
2555 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER              (0xffffL<<0)
2556 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE                (0xfL<<16)
2557 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE           (0x0L<<16)
2558 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1           (0x2L<<16)
2559 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2           (0x3L<<16)
2560 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3           (0x6L<<16)
2561 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1           (0x7L<<16)
2562 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2           (0x5L<<16)
2563 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3           (0x4L<<16)
2564 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE           (0xcL<<16)
2565 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD            (0xeL<<16)
2566 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME           (0xaL<<16)
2567 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1           (0x8L<<16)
2568 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2           (0x9L<<16)
2569 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT           (0xdL<<16)
2570 #define BCE_EMAC_TXMAC_DEBUG4_STATS0_VALID               (1L<<20)
2571 #define BCE_EMAC_TXMAC_DEBUG4_APPEND_CRC                 (1L<<21)
2572 #define BCE_EMAC_TXMAC_DEBUG4_SLOT_FILLED                (1L<<22)
2573 #define BCE_EMAC_TXMAC_DEBUG4_MAX_DEFER          (1L<<23)
2574 #define BCE_EMAC_TXMAC_DEBUG4_SEND_EXTEND                (1L<<24)
2575 #define BCE_EMAC_TXMAC_DEBUG4_SEND_PADDING               (1L<<25)
2576 #define BCE_EMAC_TXMAC_DEBUG4_EOF_LOC                    (1L<<26)
2577 #define BCE_EMAC_TXMAC_DEBUG4_COLLIDING          (1L<<27)
2578 #define BCE_EMAC_TXMAC_DEBUG4_COL_IN                     (1L<<28)
2579 #define BCE_EMAC_TXMAC_DEBUG4_BURSTING                   (1L<<29)
2580 #define BCE_EMAC_TXMAC_DEBUG4_ADVANCE                    (1L<<30)
2581 #define BCE_EMAC_TXMAC_DEBUG4_GO                         (1L<<31)
2582
2583 #define BCE_EMAC_TX_STAT_AC0                            0x00001680
2584 #define BCE_EMAC_TX_STAT_AC1                            0x00001684
2585 #define BCE_EMAC_TX_STAT_AC2                            0x00001688
2586 #define BCE_EMAC_TX_STAT_AC3                            0x0000168c
2587 #define BCE_EMAC_TX_STAT_AC4                            0x00001690
2588 #define BCE_EMAC_TX_STAT_AC5                            0x00001694
2589 #define BCE_EMAC_TX_STAT_AC6                            0x00001698
2590 #define BCE_EMAC_TX_STAT_AC7                            0x0000169c
2591 #define BCE_EMAC_TX_STAT_AC8                            0x000016a0
2592 #define BCE_EMAC_TX_STAT_AC9                            0x000016a4
2593 #define BCE_EMAC_TX_STAT_AC10                           0x000016a8
2594 #define BCE_EMAC_TX_STAT_AC11                           0x000016ac
2595 #define BCE_EMAC_TX_STAT_AC12                           0x000016b0
2596 #define BCE_EMAC_TX_STAT_AC13                           0x000016b4
2597 #define BCE_EMAC_TX_STAT_AC14                           0x000016b8
2598 #define BCE_EMAC_TX_STAT_AC15                           0x000016bc
2599 #define BCE_EMAC_TX_STAT_AC16                           0x000016c0
2600 #define BCE_EMAC_TX_STAT_AC17                           0x000016c4
2601 #define BCE_EMAC_TX_STAT_AC18                           0x000016c8
2602 #define BCE_EMAC_TX_STAT_AC19                           0x000016cc
2603 #define BCE_EMAC_TX_STAT_AC20                           0x000016d0
2604 #define BCE_EMAC_TX_STAT_AC21                           0x000016d4
2605 #define BCE_EMAC_TXMAC_SUC_DBG_OVERRUNVEC               0x000016d8
2606
2607
2608 /*
2609  *  rpm_reg definition
2610  *  offset: 0x1800
2611  */
2612 #define BCE_RPM_COMMAND                         0x00001800
2613 #define BCE_RPM_COMMAND_ENABLED                  (1L<<0)
2614 #define BCE_RPM_COMMAND_OVERRUN_ABORT                    (1L<<4)
2615
2616 #define BCE_RPM_STATUS                                  0x00001804
2617 #define BCE_RPM_STATUS_MBUF_WAIT                         (1L<<0)
2618 #define BCE_RPM_STATUS_FREE_WAIT                         (1L<<1)
2619
2620 #define BCE_RPM_CONFIG                                  0x00001808
2621 #define BCE_RPM_CONFIG_NO_PSD_HDR_CKSUM          (1L<<0)
2622 #define BCE_RPM_CONFIG_ACPI_ENA                  (1L<<1)
2623 #define BCE_RPM_CONFIG_ACPI_KEEP                         (1L<<2)
2624 #define BCE_RPM_CONFIG_MP_KEEP                           (1L<<3)
2625 #define BCE_RPM_CONFIG_SORT_VECT_VAL                     (0xfL<<4)
2626 #define BCE_RPM_CONFIG_IGNORE_VLAN                       (1L<<31)
2627
2628 #define BCE_RPM_VLAN_MATCH0                             0x00001810
2629 #define BCE_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE         (0xfffL<<0)
2630
2631 #define BCE_RPM_VLAN_MATCH1                             0x00001814
2632 #define BCE_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE         (0xfffL<<0)
2633
2634 #define BCE_RPM_VLAN_MATCH2                             0x00001818
2635 #define BCE_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE         (0xfffL<<0)
2636
2637 #define BCE_RPM_VLAN_MATCH3                             0x0000181c
2638 #define BCE_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE         (0xfffL<<0)
2639
2640 #define BCE_RPM_SORT_USER0                              0x00001820
2641 #define BCE_RPM_SORT_USER0_PM_EN                         (0xffffL<<0)
2642 #define BCE_RPM_SORT_USER0_BC_EN                         (1L<<16)
2643 #define BCE_RPM_SORT_USER0_MC_EN                         (1L<<17)
2644 #define BCE_RPM_SORT_USER0_MC_HSH_EN                     (1L<<18)
2645 #define BCE_RPM_SORT_USER0_PROM_EN                       (1L<<19)
2646 #define BCE_RPM_SORT_USER0_VLAN_EN                       (0xfL<<20)
2647 #define BCE_RPM_SORT_USER0_PROM_VLAN                     (1L<<24)
2648 #define BCE_RPM_SORT_USER0_ENA                           (1L<<31)
2649
2650 #define BCE_RPM_SORT_USER1                              0x00001824
2651 #define BCE_RPM_SORT_USER1_PM_EN                         (0xffffL<<0)
2652 #define BCE_RPM_SORT_USER1_BC_EN                         (1L<<16)
2653 #define BCE_RPM_SORT_USER1_MC_EN                         (1L<<17)
2654 #define BCE_RPM_SORT_USER1_MC_HSH_EN                     (1L<<18)
2655 #define BCE_RPM_SORT_USER1_PROM_EN                       (1L<<19)
2656 #define BCE_RPM_SORT_USER1_VLAN_EN                       (0xfL<<20)
2657 #define BCE_RPM_SORT_USER1_PROM_VLAN                     (1L<<24)
2658 #define BCE_RPM_SORT_USER1_ENA                           (1L<<31)
2659
2660 #define BCE_RPM_SORT_USER2                              0x00001828
2661 #define BCE_RPM_SORT_USER2_PM_EN                         (0xffffL<<0)
2662 #define BCE_RPM_SORT_USER2_BC_EN                         (1L<<16)
2663 #define BCE_RPM_SORT_USER2_MC_EN                         (1L<<17)
2664 #define BCE_RPM_SORT_USER2_MC_HSH_EN                     (1L<<18)
2665 #define BCE_RPM_SORT_USER2_PROM_EN                       (1L<<19)
2666 #define BCE_RPM_SORT_USER2_VLAN_EN                       (0xfL<<20)
2667 #define BCE_RPM_SORT_USER2_PROM_VLAN                     (1L<<24)
2668 #define BCE_RPM_SORT_USER2_ENA                           (1L<<31)
2669
2670 #define BCE_RPM_SORT_USER3                              0x0000182c
2671 #define BCE_RPM_SORT_USER3_PM_EN                         (0xffffL<<0)
2672 #define BCE_RPM_SORT_USER3_BC_EN                         (1L<<16)
2673 #define BCE_RPM_SORT_USER3_MC_EN                         (1L<<17)
2674 #define BCE_RPM_SORT_USER3_MC_HSH_EN                     (1L<<18)
2675 #define BCE_RPM_SORT_USER3_PROM_EN                       (1L<<19)
2676 #define BCE_RPM_SORT_USER3_VLAN_EN                       (0xfL<<20)
2677 #define BCE_RPM_SORT_USER3_PROM_VLAN                     (1L<<24)
2678 #define BCE_RPM_SORT_USER3_ENA                           (1L<<31)
2679
2680 #define BCE_RPM_STAT_L2_FILTER_DISCARDS         0x00001840
2681 #define BCE_RPM_STAT_RULE_CHECKER_DISCARDS              0x00001844
2682 #define BCE_RPM_STAT_IFINFTQDISCARDS                    0x00001848
2683 #define BCE_RPM_STAT_IFINMBUFDISCARD                    0x0000184c
2684 #define BCE_RPM_STAT_RULE_CHECKER_P4_HIT                0x00001850
2685 #define BCE_RPM_STAT_AC0                                0x00001880
2686 #define BCE_RPM_STAT_AC1                                0x00001884
2687 #define BCE_RPM_STAT_AC2                                0x00001888
2688 #define BCE_RPM_STAT_AC3                                0x0000188c
2689 #define BCE_RPM_STAT_AC4                                0x00001890
2690 #define BCE_RPM_RC_CNTL_0                               0x00001900
2691 #define BCE_RPM_RC_CNTL_0_OFFSET                         (0xffL<<0)
2692 #define BCE_RPM_RC_CNTL_0_CLASS                  (0x7L<<8)
2693 #define BCE_RPM_RC_CNTL_0_PRIORITY                       (1L<<11)
2694 #define BCE_RPM_RC_CNTL_0_P4                             (1L<<12)
2695 #define BCE_RPM_RC_CNTL_0_HDR_TYPE                       (0x7L<<13)
2696 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_START                 (0L<<13)
2697 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_IP                    (1L<<13)
2698 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_TCP                   (2L<<13)
2699 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_UDP                   (3L<<13)
2700 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_DATA          (4L<<13)
2701 #define BCE_RPM_RC_CNTL_0_COMP                           (0x3L<<16)
2702 #define BCE_RPM_RC_CNTL_0_COMP_EQUAL                     (0L<<16)
2703 #define BCE_RPM_RC_CNTL_0_COMP_NEQUAL                    (1L<<16)
2704 #define BCE_RPM_RC_CNTL_0_COMP_GREATER                   (2L<<16)
2705 #define BCE_RPM_RC_CNTL_0_COMP_LESS                      (3L<<16)
2706 #define BCE_RPM_RC_CNTL_0_SBIT                           (1L<<19)
2707 #define BCE_RPM_RC_CNTL_0_CMDSEL                         (0xfL<<20)
2708 #define BCE_RPM_RC_CNTL_0_MAP                            (1L<<24)
2709 #define BCE_RPM_RC_CNTL_0_DISCARD                        (1L<<25)
2710 #define BCE_RPM_RC_CNTL_0_MASK                           (1L<<26)
2711 #define BCE_RPM_RC_CNTL_0_P1                             (1L<<27)
2712 #define BCE_RPM_RC_CNTL_0_P2                             (1L<<28)
2713 #define BCE_RPM_RC_CNTL_0_P3                             (1L<<29)
2714 #define BCE_RPM_RC_CNTL_0_NBIT                           (1L<<30)
2715
2716 #define BCE_RPM_RC_VALUE_MASK_0                 0x00001904
2717 #define BCE_RPM_RC_VALUE_MASK_0_VALUE                    (0xffffL<<0)
2718 #define BCE_RPM_RC_VALUE_MASK_0_MASK                     (0xffffL<<16)
2719
2720 #define BCE_RPM_RC_CNTL_1                               0x00001908
2721 #define BCE_RPM_RC_CNTL_1_A                              (0x3ffffL<<0)
2722 #define BCE_RPM_RC_CNTL_1_B                              (0xfffL<<19)
2723
2724 #define BCE_RPM_RC_VALUE_MASK_1                 0x0000190c
2725 #define BCE_RPM_RC_CNTL_2                               0x00001910
2726 #define BCE_RPM_RC_CNTL_2_A                              (0x3ffffL<<0)
2727 #define BCE_RPM_RC_CNTL_2_B                              (0xfffL<<19)
2728
2729 #define BCE_RPM_RC_VALUE_MASK_2                 0x00001914
2730 #define BCE_RPM_RC_CNTL_3                               0x00001918
2731 #define BCE_RPM_RC_CNTL_3_A                              (0x3ffffL<<0)
2732 #define BCE_RPM_RC_CNTL_3_B                              (0xfffL<<19)
2733
2734 #define BCE_RPM_RC_VALUE_MASK_3                 0x0000191c
2735 #define BCE_RPM_RC_CNTL_4                               0x00001920
2736 #define BCE_RPM_RC_CNTL_4_A                              (0x3ffffL<<0)
2737 #define BCE_RPM_RC_CNTL_4_B                              (0xfffL<<19)
2738
2739 #define BCE_RPM_RC_VALUE_MASK_4                 0x00001924
2740 #define BCE_RPM_RC_CNTL_5                               0x00001928
2741 #define BCE_RPM_RC_CNTL_5_A                              (0x3ffffL<<0)
2742 #define BCE_RPM_RC_CNTL_5_B                              (0xfffL<<19)
2743
2744 #define BCE_RPM_RC_VALUE_MASK_5                 0x0000192c
2745 #define BCE_RPM_RC_CNTL_6                               0x00001930
2746 #define BCE_RPM_RC_CNTL_6_A                              (0x3ffffL<<0)
2747 #define BCE_RPM_RC_CNTL_6_B                              (0xfffL<<19)
2748
2749 #define BCE_RPM_RC_VALUE_MASK_6                 0x00001934
2750 #define BCE_RPM_RC_CNTL_7                               0x00001938
2751 #define BCE_RPM_RC_CNTL_7_A                              (0x3ffffL<<0)
2752 #define BCE_RPM_RC_CNTL_7_B                              (0xfffL<<19)
2753
2754 #define BCE_RPM_RC_VALUE_MASK_7                 0x0000193c
2755 #define BCE_RPM_RC_CNTL_8                               0x00001940
2756 #define BCE_RPM_RC_CNTL_8_A                              (0x3ffffL<<0)
2757 #define BCE_RPM_RC_CNTL_8_B                              (0xfffL<<19)
2758
2759 #define BCE_RPM_RC_VALUE_MASK_8                 0x00001944
2760 #define BCE_RPM_RC_CNTL_9                               0x00001948
2761 #define BCE_RPM_RC_CNTL_9_A                              (0x3ffffL<<0)
2762 #define BCE_RPM_RC_CNTL_9_B                              (0xfffL<<19)
2763
2764 #define BCE_RPM_RC_VALUE_MASK_9                 0x0000194c
2765 #define BCE_RPM_RC_CNTL_10                              0x00001950
2766 #define BCE_RPM_RC_CNTL_10_A                             (0x3ffffL<<0)
2767 #define BCE_RPM_RC_CNTL_10_B                             (0xfffL<<19)
2768
2769 #define BCE_RPM_RC_VALUE_MASK_10                        0x00001954
2770 #define BCE_RPM_RC_CNTL_11                              0x00001958
2771 #define BCE_RPM_RC_CNTL_11_A                             (0x3ffffL<<0)
2772 #define BCE_RPM_RC_CNTL_11_B                             (0xfffL<<19)
2773
2774 #define BCE_RPM_RC_VALUE_MASK_11                        0x0000195c
2775 #define BCE_RPM_RC_CNTL_12                              0x00001960
2776 #define BCE_RPM_RC_CNTL_12_A                             (0x3ffffL<<0)
2777 #define BCE_RPM_RC_CNTL_12_B                             (0xfffL<<19)
2778
2779 #define BCE_RPM_RC_VALUE_MASK_12                        0x00001964
2780 #define BCE_RPM_RC_CNTL_13                              0x00001968
2781 #define BCE_RPM_RC_CNTL_13_A                             (0x3ffffL<<0)
2782 #define BCE_RPM_RC_CNTL_13_B                             (0xfffL<<19)
2783
2784 #define BCE_RPM_RC_VALUE_MASK_13                        0x0000196c
2785 #define BCE_RPM_RC_CNTL_14                              0x00001970
2786 #define BCE_RPM_RC_CNTL_14_A                             (0x3ffffL<<0)
2787 #define BCE_RPM_RC_CNTL_14_B                             (0xfffL<<19)
2788
2789 #define BCE_RPM_RC_VALUE_MASK_14                        0x00001974
2790 #define BCE_RPM_RC_CNTL_15                              0x00001978
2791 #define BCE_RPM_RC_CNTL_15_A                             (0x3ffffL<<0)
2792 #define BCE_RPM_RC_CNTL_15_B                             (0xfffL<<19)
2793
2794 #define BCE_RPM_RC_VALUE_MASK_15                        0x0000197c
2795 #define BCE_RPM_RC_CONFIG                               0x00001980
2796 #define BCE_RPM_RC_CONFIG_RULE_ENABLE                    (0xffffL<<0)
2797 #define BCE_RPM_RC_CONFIG_DEF_CLASS                      (0x7L<<24)
2798
2799 #define BCE_RPM_DEBUG0                                  0x00001984
2800 #define BCE_RPM_DEBUG0_FM_BCNT                           (0xffffL<<0)
2801 #define BCE_RPM_DEBUG0_T_DATA_OFST_VLD                   (1L<<16)
2802 #define BCE_RPM_DEBUG0_T_UDP_OFST_VLD                    (1L<<17)
2803 #define BCE_RPM_DEBUG0_T_TCP_OFST_VLD                    (1L<<18)
2804 #define BCE_RPM_DEBUG0_T_IP_OFST_VLD                     (1L<<19)
2805 #define BCE_RPM_DEBUG0_IP_MORE_FRGMT                     (1L<<20)
2806 #define BCE_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR               (1L<<21)
2807 #define BCE_RPM_DEBUG0_LLC_SNAP                  (1L<<22)
2808 #define BCE_RPM_DEBUG0_FM_STARTED                        (1L<<23)
2809 #define BCE_RPM_DEBUG0_DONE                              (1L<<24)
2810 #define BCE_RPM_DEBUG0_WAIT_4_DONE                       (1L<<25)
2811 #define BCE_RPM_DEBUG0_USE_TPBUF_CKSUM                   (1L<<26)
2812 #define BCE_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM               (1L<<27)
2813 #define BCE_RPM_DEBUG0_IGNORE_VLAN                       (1L<<28)
2814 #define BCE_RPM_DEBUG0_RP_ENA_ACTIVE                     (1L<<31)
2815
2816 #define BCE_RPM_DEBUG1                                  0x00001988
2817 #define BCE_RPM_DEBUG1_FSM_CUR_ST                        (0xffffL<<0)
2818 #define BCE_RPM_DEBUG1_FSM_CUR_ST_IDLE                   (0L<<0)
2819 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL           (1L<<0)
2820 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC         (2L<<0)
2821 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP            (4L<<0)
2822 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP            (8L<<0)
2823 #define BCE_RPM_DEBUG1_FSM_CUR_ST_IP_START               (16L<<0)
2824 #define BCE_RPM_DEBUG1_FSM_CUR_ST_IP                     (32L<<0)
2825 #define BCE_RPM_DEBUG1_FSM_CUR_ST_TCP                    (64L<<0)
2826 #define BCE_RPM_DEBUG1_FSM_CUR_ST_UDP                    (128L<<0)
2827 #define BCE_RPM_DEBUG1_FSM_CUR_ST_AH                     (256L<<0)
2828 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP                    (512L<<0)
2829 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD            (1024L<<0)
2830 #define BCE_RPM_DEBUG1_FSM_CUR_ST_DATA                   (2048L<<0)
2831 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY              (0x2000L<<0)
2832 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT           (0x4000L<<0)
2833 #define BCE_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT           (0x8000L<<0)
2834 #define BCE_RPM_DEBUG1_HDR_BCNT                  (0x7ffL<<16)
2835 #define BCE_RPM_DEBUG1_UNKNOWN_ETYPE_D                   (1L<<28)
2836 #define BCE_RPM_DEBUG1_VLAN_REMOVED_D2                   (1L<<29)
2837 #define BCE_RPM_DEBUG1_VLAN_REMOVED_D1                   (1L<<30)
2838 #define BCE_RPM_DEBUG1_EOF_0XTRA_WD                      (1L<<31)
2839
2840 #define BCE_RPM_DEBUG2                                  0x0000198c
2841 #define BCE_RPM_DEBUG2_CMD_HIT_VEC                       (0xffffL<<0)
2842 #define BCE_RPM_DEBUG2_IP_BCNT                           (0xffL<<16)
2843 #define BCE_RPM_DEBUG2_THIS_CMD_M4                       (1L<<24)
2844 #define BCE_RPM_DEBUG2_THIS_CMD_M3                       (1L<<25)
2845 #define BCE_RPM_DEBUG2_THIS_CMD_M2                       (1L<<26)
2846 #define BCE_RPM_DEBUG2_THIS_CMD_M1                       (1L<<27)
2847 #define BCE_RPM_DEBUG2_IPIPE_EMPTY                       (1L<<28)
2848 #define BCE_RPM_DEBUG2_FM_DISCARD                        (1L<<29)
2849 #define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D2                (1L<<30)
2850 #define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D1                (1L<<31)
2851
2852 #define BCE_RPM_DEBUG3                                  0x00001990
2853 #define BCE_RPM_DEBUG3_AVAIL_MBUF_PTR                    (0x1ffL<<0)
2854 #define BCE_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT              (1L<<9)
2855 #define BCE_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT              (1L<<10)
2856 #define BCE_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT               (1L<<11)
2857 #define BCE_RPM_DEBUG3_RDE_RBUF_FREE_REQ                 (1L<<12)
2858 #define BCE_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ                (1L<<13)
2859 #define BCE_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL                (1L<<14)
2860 #define BCE_RPM_DEBUG3_RBUF_RDE_SOF_DROP                 (1L<<15)
2861 #define BCE_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT                (0xfL<<16)
2862 #define BCE_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL              (1L<<21)
2863 #define BCE_RPM_DEBUG3_DROP_NXT_VLD                      (1L<<22)
2864 #define BCE_RPM_DEBUG3_DROP_NXT                  (1L<<23)
2865 #define BCE_RPM_DEBUG3_FTQ_FSM                           (0x3L<<24)
2866 #define BCE_RPM_DEBUG3_FTQ_FSM_IDLE                      (0x0L<<24)
2867 #define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_ACK          (0x1L<<24)
2868 #define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_FREE                 (0x2L<<24)
2869 #define BCE_RPM_DEBUG3_MBWRITE_FSM                       (0x3L<<26)
2870 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF              (0x0L<<26)
2871 #define BCE_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF              (0x1L<<26)
2872 #define BCE_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA              (0x2L<<26)
2873 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA             (0x3L<<26)
2874 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF              (0x4L<<26)
2875 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK           (0x5L<<26)
2876 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD     (0x6L<<26)
2877 #define BCE_RPM_DEBUG3_MBWRITE_FSM_DONE          (0x7L<<26)
2878 #define BCE_RPM_DEBUG3_MBFREE_FSM                        (1L<<29)
2879 #define BCE_RPM_DEBUG3_MBFREE_FSM_IDLE                   (0L<<29)
2880 #define BCE_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK               (1L<<29)
2881 #define BCE_RPM_DEBUG3_MBALLOC_FSM                       (1L<<30)
2882 #define BCE_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF               (0x0L<<30)
2883 #define BCE_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF              (0x1L<<30)
2884 #define BCE_RPM_DEBUG3_CCODE_EOF_ERROR                   (1L<<31)
2885
2886 #define BCE_RPM_DEBUG4                                  0x00001994
2887 #define BCE_RPM_DEBUG4_DFSM_MBUF_CLUSTER                 (0x1ffffffL<<0)
2888 #define BCE_RPM_DEBUG4_DFIFO_CUR_CCODE                   (0x7L<<25)
2889 #define BCE_RPM_DEBUG4_MBWRITE_FSM                       (0x7L<<28)
2890 #define BCE_RPM_DEBUG4_DFIFO_EMPTY                       (1L<<31)
2891
2892 #define BCE_RPM_DEBUG5                                  0x00001998
2893 #define BCE_RPM_DEBUG5_RDROP_WPTR                        (0x1fL<<0)
2894 #define BCE_RPM_DEBUG5_RDROP_ACPI_RPTR                   (0x1fL<<5)
2895 #define BCE_RPM_DEBUG5_RDROP_MC_RPTR                     (0x1fL<<10)
2896 #define BCE_RPM_DEBUG5_RDROP_RC_RPTR                     (0x1fL<<15)
2897 #define BCE_RPM_DEBUG5_RDROP_ACPI_EMPTY          (1L<<20)
2898 #define BCE_RPM_DEBUG5_RDROP_MC_EMPTY                    (1L<<21)
2899 #define BCE_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR   (1L<<22)
2900 #define BCE_RPM_DEBUG5_HOLDREG_WOL_DROP_INT              (1L<<23)
2901 #define BCE_RPM_DEBUG5_HOLDREG_DISCARD                   (1L<<24)
2902 #define BCE_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL             (1L<<25)
2903 #define BCE_RPM_DEBUG5_HOLDREG_MC_EMPTY          (1L<<26)
2904 #define BCE_RPM_DEBUG5_HOLDREG_RC_EMPTY          (1L<<27)
2905 #define BCE_RPM_DEBUG5_HOLDREG_FC_EMPTY          (1L<<28)
2906 #define BCE_RPM_DEBUG5_HOLDREG_ACPI_EMPTY                (1L<<29)
2907 #define BCE_RPM_DEBUG5_HOLDREG_FULL_T                    (1L<<30)
2908 #define BCE_RPM_DEBUG5_HOLDREG_RD                        (1L<<31)
2909
2910 #define BCE_RPM_DEBUG6                                  0x0000199c
2911 #define BCE_RPM_DEBUG6_ACPI_VEC                  (0xffffL<<0)
2912 #define BCE_RPM_DEBUG6_VEC                               (0xffffL<<16)
2913
2914 #define BCE_RPM_DEBUG7                                  0x000019a0
2915 #define BCE_RPM_DEBUG7_RPM_DBG7_LAST_CRC                 (0xffffffffL<<0)
2916
2917 #define BCE_RPM_DEBUG8                                  0x000019a4
2918 #define BCE_RPM_DEBUG8_PS_ACPI_FSM                       (0xfL<<0)
2919 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_IDLE          (0L<<0)
2920 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR           (1L<<0)
2921 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR           (2L<<0)
2922 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR           (3L<<0)
2923 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF        (4L<<0)
2924 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA               (5L<<0)
2925 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR               (6L<<0)
2926 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR               (7L<<0)
2927 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR               (8L<<0)
2928 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR               (9L<<0)
2929 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF            (10L<<0)
2930 #define BCE_RPM_DEBUG8_COMPARE_AT_W0                     (1L<<4)
2931 #define BCE_RPM_DEBUG8_COMPARE_AT_W3_DATA                (1L<<5)
2932 #define BCE_RPM_DEBUG8_COMPARE_AT_SOF_WAIT               (1L<<6)
2933 #define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W3                 (1L<<7)
2934 #define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W2                 (1L<<8)
2935 #define BCE_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES              (1L<<9)
2936 #define BCE_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES              (1L<<10)
2937 #define BCE_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES             (1L<<11)
2938 #define BCE_RPM_DEBUG8_EOF_DET                           (1L<<12)
2939 #define BCE_RPM_DEBUG8_SOF_DET                           (1L<<13)
2940 #define BCE_RPM_DEBUG8_WAIT_4_SOF                        (1L<<14)
2941 #define BCE_RPM_DEBUG8_ALL_DONE                  (1L<<15)
2942 #define BCE_RPM_DEBUG8_THBUF_ADDR                        (0x7fL<<16)
2943 #define BCE_RPM_DEBUG8_BYTE_CTR                  (0xffL<<24)
2944
2945 #define BCE_RPM_DEBUG9                                  0x000019a8
2946 #define BCE_RPM_DEBUG9_OUTFIFO_COUNT                     (0x7L<<0)
2947 #define BCE_RPM_DEBUG9_RDE_ACPI_RDY                      (1L<<3)
2948 #define BCE_RPM_DEBUG9_VLD_RD_ENTRY_CT                   (0x7L<<4)
2949 #define BCE_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED  (1L<<28)
2950 #define BCE_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED           (1L<<29)
2951 #define BCE_RPM_DEBUG9_ACPI_MATCH_INT                    (1L<<30)
2952 #define BCE_RPM_DEBUG9_ACPI_ENABLE_SYN                   (1L<<31)
2953
2954 #define BCE_RPM_ACPI_DBG_BUF_W00                        0x000019c0
2955 #define BCE_RPM_ACPI_DBG_BUF_W01                        0x000019c4
2956 #define BCE_RPM_ACPI_DBG_BUF_W02                        0x000019c8
2957 #define BCE_RPM_ACPI_DBG_BUF_W03                        0x000019cc
2958 #define BCE_RPM_ACPI_DBG_BUF_W10                        0x000019d0
2959 #define BCE_RPM_ACPI_DBG_BUF_W11                        0x000019d4
2960 #define BCE_RPM_ACPI_DBG_BUF_W12                        0x000019d8
2961 #define BCE_RPM_ACPI_DBG_BUF_W13                        0x000019dc
2962 #define BCE_RPM_ACPI_DBG_BUF_W20                        0x000019e0
2963 #define BCE_RPM_ACPI_DBG_BUF_W21                        0x000019e4
2964 #define BCE_RPM_ACPI_DBG_BUF_W22                        0x000019e8
2965 #define BCE_RPM_ACPI_DBG_BUF_W23                        0x000019ec
2966 #define BCE_RPM_ACPI_DBG_BUF_W30                        0x000019f0
2967 #define BCE_RPM_ACPI_DBG_BUF_W31                        0x000019f4
2968 #define BCE_RPM_ACPI_DBG_BUF_W32                        0x000019f8
2969 #define BCE_RPM_ACPI_DBG_BUF_W33                        0x000019fc
2970
2971
2972 /*
2973  *  rbuf_reg definition
2974  *  offset: 0x200000
2975  */
2976 #define BCE_RBUF_COMMAND                                0x00200000
2977 #define BCE_RBUF_COMMAND_ENABLED                         (1L<<0)
2978 #define BCE_RBUF_COMMAND_FREE_INIT                       (1L<<1)
2979 #define BCE_RBUF_COMMAND_RAM_INIT                        (1L<<2)
2980 #define BCE_RBUF_COMMAND_OVER_FREE                       (1L<<4)
2981 #define BCE_RBUF_COMMAND_ALLOC_REQ                       (1L<<5)
2982
2983 #define BCE_RBUF_STATUS1                                0x00200004
2984 #define BCE_RBUF_STATUS1_FREE_COUNT                      (0x3ffL<<0)
2985
2986 #define BCE_RBUF_STATUS2                                0x00200008
2987 #define BCE_RBUF_STATUS2_FREE_TAIL                       (0x3ffL<<0)
2988 #define BCE_RBUF_STATUS2_FREE_HEAD                       (0x3ffL<<16)
2989
2990 #define BCE_RBUF_CONFIG                         0x0020000c
2991 #define BCE_RBUF_CONFIG_XOFF_TRIP                        (0x3ffL<<0)
2992 #define BCE_RBUF_CONFIG_XON_TRIP                         (0x3ffL<<16)
2993
2994 #define BCE_RBUF_FW_BUF_ALLOC                           0x00200010
2995 #define BCE_RBUF_FW_BUF_ALLOC_VALUE                      (0x1ffL<<7)
2996
2997 #define BCE_RBUF_FW_BUF_FREE                            0x00200014
2998 #define BCE_RBUF_FW_BUF_FREE_COUNT                       (0x7fL<<0)
2999 #define BCE_RBUF_FW_BUF_FREE_TAIL                        (0x1ffL<<7)
3000 #define BCE_RBUF_FW_BUF_FREE_HEAD                        (0x1ffL<<16)
3001
3002 #define BCE_RBUF_FW_BUF_SEL                             0x00200018
3003 #define BCE_RBUF_FW_BUF_SEL_COUNT                        (0x7fL<<0)
3004 #define BCE_RBUF_FW_BUF_SEL_TAIL                         (0x1ffL<<7)
3005 #define BCE_RBUF_FW_BUF_SEL_HEAD                         (0x1ffL<<16)
3006
3007 #define BCE_RBUF_CONFIG2                                0x0020001c
3008 #define BCE_RBUF_CONFIG2_MAC_DROP_TRIP                   (0x3ffL<<0)
3009 #define BCE_RBUF_CONFIG2_MAC_KEEP_TRIP                   (0x3ffL<<16)
3010
3011 #define BCE_RBUF_CONFIG3                                0x00200020
3012 #define BCE_RBUF_CONFIG3_CU_DROP_TRIP                    (0x3ffL<<0)
3013 #define BCE_RBUF_CONFIG3_CU_KEEP_TRIP                    (0x3ffL<<16)
3014
3015 #define BCE_RBUF_PKT_DATA                               0x00208000
3016 #define BCE_RBUF_CLIST_DATA                             0x00210000
3017 #define BCE_RBUF_BUF_DATA                               0x00220000
3018
3019
3020 /*
3021  *  rv2p_reg definition
3022  *  offset: 0x2800
3023  */
3024 #define BCE_RV2P_COMMAND                                0x00002800
3025 #define BCE_RV2P_COMMAND_ENABLED                         (1L<<0)
3026 #define BCE_RV2P_COMMAND_PROC1_INTRPT                    (1L<<1)
3027 #define BCE_RV2P_COMMAND_PROC2_INTRPT                    (1L<<2)
3028 #define BCE_RV2P_COMMAND_ABORT0                  (1L<<4)
3029 #define BCE_RV2P_COMMAND_ABORT1                  (1L<<5)
3030 #define BCE_RV2P_COMMAND_ABORT2                  (1L<<6)
3031 #define BCE_RV2P_COMMAND_ABORT3                  (1L<<7)
3032 #define BCE_RV2P_COMMAND_ABORT4                  (1L<<8)
3033 #define BCE_RV2P_COMMAND_ABORT5                  (1L<<9)
3034 #define BCE_RV2P_COMMAND_PROC1_RESET                     (1L<<16)
3035 #define BCE_RV2P_COMMAND_PROC2_RESET                     (1L<<17)
3036 #define BCE_RV2P_COMMAND_CTXIF_RESET                     (1L<<18)
3037
3038 #define BCE_RV2P_STATUS                         0x00002804
3039 #define BCE_RV2P_STATUS_ALWAYS_0                         (1L<<0)
3040 #define BCE_RV2P_STATUS_RV2P_GEN_STAT0_CNT               (1L<<8)
3041 #define BCE_RV2P_STATUS_RV2P_GEN_STAT1_CNT               (1L<<9)
3042 #define BCE_RV2P_STATUS_RV2P_GEN_STAT2_CNT               (1L<<10)
3043 #define BCE_RV2P_STATUS_RV2P_GEN_STAT3_CNT               (1L<<11)
3044 #define BCE_RV2P_STATUS_RV2P_GEN_STAT4_CNT               (1L<<12)
3045 #define BCE_RV2P_STATUS_RV2P_GEN_STAT5_CNT               (1L<<13)
3046
3047 #define BCE_RV2P_CONFIG                         0x00002808
3048 #define BCE_RV2P_CONFIG_STALL_PROC1                      (1L<<0)
3049 #define BCE_RV2P_CONFIG_STALL_PROC2                      (1L<<1)
3050 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT0            (1L<<8)
3051 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT1            (1L<<9)
3052 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT2            (1L<<10)
3053 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT3            (1L<<11)
3054 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT4            (1L<<12)
3055 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT5            (1L<<13)
3056 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT0            (1L<<16)
3057 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT1            (1L<<17)
3058 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT2            (1L<<18)
3059 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT3            (1L<<19)
3060 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT4            (1L<<20)
3061 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT5            (1L<<21)
3062 #define BCE_RV2P_CONFIG_PAGE_SIZE                        (0xfL<<24)
3063 #define BCE_RV2P_CONFIG_PAGE_SIZE_256                    (0L<<24)
3064 #define BCE_RV2P_CONFIG_PAGE_SIZE_512                    (1L<<24)
3065 #define BCE_RV2P_CONFIG_PAGE_SIZE_1K                     (2L<<24)
3066 #define BCE_RV2P_CONFIG_PAGE_SIZE_2K                     (3L<<24)
3067 #define BCE_RV2P_CONFIG_PAGE_SIZE_4K                     (4L<<24)
3068 #define BCE_RV2P_CONFIG_PAGE_SIZE_8K                     (5L<<24)
3069 #define BCE_RV2P_CONFIG_PAGE_SIZE_16K                    (6L<<24)
3070 #define BCE_RV2P_CONFIG_PAGE_SIZE_32K                    (7L<<24)
3071 #define BCE_RV2P_CONFIG_PAGE_SIZE_64K                    (8L<<24)
3072 #define BCE_RV2P_CONFIG_PAGE_SIZE_128K                   (9L<<24)
3073 #define BCE_RV2P_CONFIG_PAGE_SIZE_256K                   (10L<<24)
3074 #define BCE_RV2P_CONFIG_PAGE_SIZE_512K                   (11L<<24)
3075 #define BCE_RV2P_CONFIG_PAGE_SIZE_1M                     (12L<<24)
3076
3077 #define BCE_RV2P_GEN_BFR_ADDR_0                 0x00002810
3078 #define BCE_RV2P_GEN_BFR_ADDR_0_VALUE                    (0xffffL<<16)
3079
3080 #define BCE_RV2P_GEN_BFR_ADDR_1                 0x00002814
3081 #define BCE_RV2P_GEN_BFR_ADDR_1_VALUE                    (0xffffL<<16)
3082
3083 #define BCE_RV2P_GEN_BFR_ADDR_2                 0x00002818
3084 #define BCE_RV2P_GEN_BFR_ADDR_2_VALUE                    (0xffffL<<16)
3085
3086 #define BCE_RV2P_GEN_BFR_ADDR_3                 0x0000281c
3087 #define BCE_RV2P_GEN_BFR_ADDR_3_VALUE                    (0xffffL<<16)
3088
3089 #define BCE_RV2P_INSTR_HIGH                             0x00002830
3090 #define BCE_RV2P_INSTR_HIGH_HIGH                         (0x1fL<<0)
3091
3092 #define BCE_RV2P_INSTR_LOW                              0x00002834
3093 #define BCE_RV2P_PROC1_ADDR_CMD                 0x00002838
3094 #define BCE_RV2P_PROC1_ADDR_CMD_ADD                      (0x3ffL<<0)
3095 #define BCE_RV2P_PROC1_ADDR_CMD_RDWR                     (1L<<31)
3096
3097 #define BCE_RV2P_PROC2_ADDR_CMD                 0x0000283c
3098 #define BCE_RV2P_PROC2_ADDR_CMD_ADD                      (0x3ffL<<0)
3099 #define BCE_RV2P_PROC2_ADDR_CMD_RDWR                     (1L<<31)
3100
3101 #define BCE_RV2P_PROC1_GRC_DEBUG                        0x00002840
3102 #define BCE_RV2P_PROC2_GRC_DEBUG                        0x00002844
3103 #define BCE_RV2P_GRC_PROC_DEBUG                 0x00002848
3104 #define BCE_RV2P_DEBUG_VECT_PEEK                        0x0000284c
3105 #define BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE                 (0x7ffL<<0)
3106 #define BCE_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN               (1L<<11)
3107 #define BCE_RV2P_DEBUG_VECT_PEEK_1_SEL                   (0xfL<<12)
3108 #define BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE                 (0x7ffL<<16)
3109 #define BCE_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN               (1L<<27)
3110 #define BCE_RV2P_DEBUG_VECT_PEEK_2_SEL                   (0xfL<<28)
3111
3112 #define BCE_RV2P_PFTQ_DATA                              0x00002b40
3113 #define BCE_RV2P_PFTQ_CMD                               0x00002b78
3114 #define BCE_RV2P_PFTQ_CMD_OFFSET                         (0x3ffL<<0)
3115 #define BCE_RV2P_PFTQ_CMD_WR_TOP                         (1L<<10)
3116 #define BCE_RV2P_PFTQ_CMD_WR_TOP_0                       (0L<<10)
3117 #define BCE_RV2P_PFTQ_CMD_WR_TOP_1                       (1L<<10)
3118 #define BCE_RV2P_PFTQ_CMD_SFT_RESET                      (1L<<25)
3119 #define BCE_RV2P_PFTQ_CMD_RD_DATA                        (1L<<26)
3120 #define BCE_RV2P_PFTQ_CMD_ADD_INTERVEN                   (1L<<27)
3121 #define BCE_RV2P_PFTQ_CMD_ADD_DATA                       (1L<<28)
3122 #define BCE_RV2P_PFTQ_CMD_INTERVENE_CLR          (1L<<29)
3123 #define BCE_RV2P_PFTQ_CMD_POP                            (1L<<30)
3124 #define BCE_RV2P_PFTQ_CMD_BUSY                           (1L<<31)
3125
3126 #define BCE_RV2P_PFTQ_CTL                               0x00002b7c
3127 #define BCE_RV2P_PFTQ_CTL_INTERVENE                      (1L<<0)
3128 #define BCE_RV2P_PFTQ_CTL_OVERFLOW                       (1L<<1)
3129 #define BCE_RV2P_PFTQ_CTL_FORCE_INTERVENE                (1L<<2)
3130 #define BCE_RV2P_PFTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
3131 #define BCE_RV2P_PFTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
3132
3133 #define BCE_RV2P_TFTQ_DATA                              0x00002b80
3134 #define BCE_RV2P_TFTQ_CMD                               0x00002bb8
3135 #define BCE_RV2P_TFTQ_CMD_OFFSET                         (0x3ffL<<0)
3136 #define BCE_RV2P_TFTQ_CMD_WR_TOP                         (1L<<10)
3137 #define BCE_RV2P_TFTQ_CMD_WR_TOP_0                       (0L<<10)
3138 #define BCE_RV2P_TFTQ_CMD_WR_TOP_1                       (1L<<10)
3139 #define BCE_RV2P_TFTQ_CMD_SFT_RESET                      (1L<<25)
3140 #define BCE_RV2P_TFTQ_CMD_RD_DATA                        (1L<<26)
3141 #define BCE_RV2P_TFTQ_CMD_ADD_INTERVEN                   (1L<<27)
3142 #define BCE_RV2P_TFTQ_CMD_ADD_DATA                       (1L<<28)
3143 #define BCE_RV2P_TFTQ_CMD_INTERVENE_CLR          (1L<<29)
3144 #define BCE_RV2P_TFTQ_CMD_POP                            (1L<<30)
3145 #define BCE_RV2P_TFTQ_CMD_BUSY                           (1L<<31)
3146
3147 #define BCE_RV2P_TFTQ_CTL                               0x00002bbc
3148 #define BCE_RV2P_TFTQ_CTL_INTERVENE                      (1L<<0)
3149 #define BCE_RV2P_TFTQ_CTL_OVERFLOW                       (1L<<1)
3150 #define BCE_RV2P_TFTQ_CTL_FORCE_INTERVENE                (1L<<2)
3151 #define BCE_RV2P_TFTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
3152 #define BCE_RV2P_TFTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
3153
3154 #define BCE_RV2P_MFTQ_DATA                              0x00002bc0
3155 #define BCE_RV2P_MFTQ_CMD                               0x00002bf8
3156 #define BCE_RV2P_MFTQ_CMD_OFFSET                         (0x3ffL<<0)
3157 #define BCE_RV2P_MFTQ_CMD_WR_TOP                         (1L<<10)
3158 #define BCE_RV2P_MFTQ_CMD_WR_TOP_0                       (0L<<10)
3159 #define BCE_RV2P_MFTQ_CMD_WR_TOP_1                       (1L<<10)
3160 #define BCE_RV2P_MFTQ_CMD_SFT_RESET                      (1L<<25)
3161 #define BCE_RV2P_MFTQ_CMD_RD_DATA                        (1L<<26)
3162 #define BCE_RV2P_MFTQ_CMD_ADD_INTERVEN                   (1L<<27)
3163 #define BCE_RV2P_MFTQ_CMD_ADD_DATA                       (1L<<28)
3164 #define BCE_RV2P_MFTQ_CMD_INTERVENE_CLR          (1L<<29)
3165 #define BCE_RV2P_MFTQ_CMD_POP                            (1L<<30)
3166 #define BCE_RV2P_MFTQ_CMD_BUSY                           (1L<<31)
3167
3168 #define BCE_RV2P_MFTQ_CTL                               0x00002bfc
3169 #define BCE_RV2P_MFTQ_CTL_INTERVENE                      (1L<<0)
3170 #define BCE_RV2P_MFTQ_CTL_OVERFLOW                       (1L<<1)
3171 #define BCE_RV2P_MFTQ_CTL_FORCE_INTERVENE                (1L<<2)
3172 #define BCE_RV2P_MFTQ_CTL_MAX_DEPTH                      (0x3ffL<<12)
3173 #define BCE_RV2P_MFTQ_CTL_CUR_DEPTH                      (0x3ffL<<22)
3174
3175
3176
3177 /*
3178  *  mq_reg definition
3179  *  offset: 0x3c00
3180  */
3181 #define BCE_MQ_COMMAND                                  0x00003c00
3182 #define BCE_MQ_COMMAND_ENABLED                           (1L<<0)
3183 #define BCE_MQ_COMMAND_OVERFLOW                  (1L<<4)
3184 #define BCE_MQ_COMMAND_WR_ERROR                  (1L<<5)
3185 #define BCE_MQ_COMMAND_RD_ERROR                  (1L<<6)
3186
3187 #define BCE_MQ_STATUS                                   0x00003c04
3188 #define BCE_MQ_STATUS_CTX_ACCESS_STAT                    (1L<<16)
3189 #define BCE_MQ_STATUS_CTX_ACCESS64_STAT          (1L<<17)
3190 #define BCE_MQ_STATUS_PCI_STALL_STAT                     (1L<<18)
3191
3192 #define BCE_MQ_CONFIG                                   0x00003c08
3193 #define BCE_MQ_CONFIG_TX_HIGH_PRI                        (1L<<0)
3194 #define BCE_MQ_CONFIG_HALT_DIS                           (1L<<1)
3195 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE                   (0x7L<<4)
3196 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256               (0L<<4)
3197 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_512               (1L<<4)
3198 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K                (2L<<4)
3199 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K                (3L<<4)
3200 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K                (4L<<4)
3201 #define BCE_MQ_CONFIG_MAX_DEPTH                  (0x7fL<<8)
3202 #define BCE_MQ_CONFIG_CUR_DEPTH                  (0x7fL<<20)
3203
3204 #define BCE_MQ_ENQUEUE1                         0x00003c0c
3205 #define BCE_MQ_ENQUEUE1_OFFSET                           (0x3fL<<2)
3206 #define BCE_MQ_ENQUEUE1_CID                              (0x3fffL<<8)
3207 #define BCE_MQ_ENQUEUE1_BYTE_MASK                        (0xfL<<24)
3208 #define BCE_MQ_ENQUEUE1_KNL_MODE                         (1L<<28)
3209
3210 #define BCE_MQ_ENQUEUE2                         0x00003c10
3211 #define BCE_MQ_BAD_WR_ADDR                              0x00003c14
3212 #define BCE_MQ_BAD_RD_ADDR                              0x00003c18
3213 #define BCE_MQ_KNL_BYP_WIND_START                       0x00003c1c
3214 #define BCE_MQ_KNL_BYP_WIND_START_VALUE          (0xfffffL<<12)
3215
3216 #define BCE_MQ_KNL_WIND_END                             0x00003c20
3217 #define BCE_MQ_KNL_WIND_END_VALUE                        (0xffffffL<<8)
3218
3219 #define BCE_MQ_KNL_WRITE_MASK1                          0x00003c24
3220 #define BCE_MQ_KNL_TX_MASK1                             0x00003c28
3221 #define BCE_MQ_KNL_CMD_MASK1                            0x00003c2c
3222 #define BCE_MQ_KNL_COND_ENQUEUE_MASK1                   0x00003c30
3223 #define BCE_MQ_KNL_RX_V2P_MASK1                 0x00003c34
3224 #define BCE_MQ_KNL_WRITE_MASK2                          0x00003c38
3225 #define BCE_MQ_KNL_TX_MASK2                             0x00003c3c
3226 #define BCE_MQ_KNL_CMD_MASK2                            0x00003c40
3227 #define BCE_MQ_KNL_COND_ENQUEUE_MASK2                   0x00003c44
3228 #define BCE_MQ_KNL_RX_V2P_MASK2                 0x00003c48
3229 #define BCE_MQ_KNL_BYP_WRITE_MASK1                      0x00003c4c
3230 #define BCE_MQ_KNL_BYP_TX_MASK1                 0x00003c50
3231 #define BCE_MQ_KNL_BYP_CMD_MASK1                        0x00003c54
3232 #define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK1               0x00003c58
3233 #define BCE_MQ_KNL_BYP_RX_V2P_MASK1                     0x00003c5c
3234 #define BCE_MQ_KNL_BYP_WRITE_MASK2                      0x00003c60
3235 #define BCE_MQ_KNL_BYP_TX_MASK2                 0x00003c64
3236 #define BCE_MQ_KNL_BYP_CMD_MASK2                        0x00003c68
3237 #define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK2               0x00003c6c
3238 #define BCE_MQ_KNL_BYP_RX_V2P_MASK2                     0x00003c70
3239 #define BCE_MQ_MEM_WR_ADDR                              0x00003c74
3240 #define BCE_MQ_MEM_WR_ADDR_VALUE                         (0x3fL<<0)
3241
3242 #define BCE_MQ_MEM_WR_DATA0                             0x00003c78
3243 #define BCE_MQ_MEM_WR_DATA0_VALUE                        (0xffffffffL<<0)
3244
3245 #define BCE_MQ_MEM_WR_DATA1                             0x00003c7c
3246 #define BCE_MQ_MEM_WR_DATA1_VALUE                        (0xffffffffL<<0)
3247
3248 #define BCE_MQ_MEM_WR_DATA2                             0x00003c80
3249 #define BCE_MQ_MEM_WR_DATA2_VALUE                        (0x3fffffffL<<0)
3250
3251 #define BCE_MQ_MEM_RD_ADDR                              0x00003c84
3252 #define BCE_MQ_MEM_RD_ADDR_VALUE                         (0x3fL<<0)
3253
3254 #define BCE_MQ_MEM_RD_DATA0                             0x00003c88
3255 #define BCE_MQ_MEM_RD_DATA0_VALUE                        (0xffffffffL<<0)
3256
3257 #define BCE_MQ_MEM_RD_DATA1                             0x00003c8c
3258 #define BCE_MQ_MEM_RD_DATA1_VALUE                        (0xffffffffL<<0)
3259
3260 #define BCE_MQ_MEM_RD_DATA2                             0x00003c90
3261 #define BCE_MQ_MEM_RD_DATA2_VALUE                        (0x3fffffffL<<0)
3262
3263
3264
3265 /*
3266  *  tbdr_reg definition
3267  *  offset: 0x5000
3268  */
3269 #define BCE_TBDR_COMMAND                                0x00005000
3270 #define BCE_TBDR_COMMAND_ENABLE                  (1L<<0)
3271 #define BCE_TBDR_COMMAND_SOFT_RST                        (1L<<1)
3272 #define BCE_TBDR_COMMAND_MSTR_ABORT                      (1L<<4)
3273
3274 #define BCE_TBDR_STATUS                         0x00005004
3275 #define BCE_TBDR_STATUS_DMA_WAIT                         (1L<<0)
3276 #define BCE_TBDR_STATUS_FTQ_WAIT                         (1L<<1)
3277 #define BCE_TBDR_STATUS_FIFO_OVERFLOW                    (1L<<2)
3278 #define BCE_TBDR_STATUS_FIFO_UNDERFLOW                   (1L<<3)
3279 #define BCE_TBDR_STATUS_SEARCHMISS_ERROR                 (1L<<4)
3280 #define BCE_TBDR_STATUS_FTQ_ENTRY_CNT                    (1L<<5)
3281 #define BCE_TBDR_STATUS_BURST_CNT                        (1L<<6)
3282
3283 #define BCE_TBDR_CONFIG                         0x00005008
3284 #define BCE_TBDR_CONFIG_MAX_BDS                  (0xffL<<0)
3285 #define BCE_TBDR_CONFIG_SWAP_MODE                        (1L<<8)
3286 #define BCE_TBDR_CONFIG_PRIORITY                         (1L<<9)
3287 #define BCE_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS             (1L<<10)
3288 #define BCE_TBDR_CONFIG_PAGE_SIZE                        (0xfL<<24)
3289 #define BCE_TBDR_CONFIG_PAGE_SIZE_256                    (0L<<24)
3290 #define BCE_TBDR_CONFIG_PAGE_SIZE_512                    (1L<<24)
3291 #define BCE_TBDR_CONFIG_PAGE_SIZE_1K                     (2L<<24)
3292 #define BCE_TBDR_CONFIG_PAGE_SIZE_2K                     (3L<<24)
3293 #define BCE_TBDR_CONFIG_PAGE_SIZE_4K                     (4L<<24)
3294 #define BCE_TBDR_CONFIG_PAGE_SIZE_8K                     (5L<<24)
3295 #define BCE_TBDR_CONFIG_PAGE_SIZE_16K                    (6L<<24)
3296 #define BCE_TBDR_CONFIG_PAGE_SIZE_32K                    (7L<<24)
3297 #define BCE_TBDR_CONFIG_PAGE_SIZE_64K                    (8L<<24)
3298 #define BCE_TBDR_CONFIG_PAGE_SIZE_128K                   (9L<<24)
3299 #define BCE_TBDR_CONFIG_PAGE_SIZE_256K                   (10L<<24)
3300 #define BCE_TBDR_CONFIG_PAGE_SIZE_512K                   (11L<<24)
3301 #define BCE_TBDR_CONFIG_PAGE_SIZE_1M                     (12L<<24)
3302
3303 #define BCE_TBDR_DEBUG_VECT_PEEK                        0x0000500c
3304 #define BCE_TBDR_DEBUG_VECT_PEEK_1_VALUE                 (0x7ffL<<0)
3305 #define BCE_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN               (1L<<11)
3306 #define BCE_TBDR_DEBUG_VECT_PEEK_1_SEL                   (0xfL<<12)
3307 #define BCE_TBDR_DEBUG_VECT_PEEK_2_VALUE                 (0x7ffL<<16)
3308 #define BCE_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN               (1L<<27)
3309 #define BCE_TBDR_DEBUG_VECT_PEEK_2_SEL                   (0xfL<<28)
3310
3311 #define BCE_TBDR_FTQ_DATA                               0x000053c0
3312 #define BCE_TBDR_FTQ_CMD                                0x000053f8
3313 #define BCE_TBDR_FTQ_CMD_OFFSET                  (0x3ffL<<0)
3314 #define BCE_TBDR_FTQ_CMD_WR_TOP                  (1L<<10)
3315 #define BCE_TBDR_FTQ_CMD_WR_TOP_0                        (0L<<10)
3316 #define BCE_TBDR_FTQ_CMD_WR_TOP_1                        (1L<<10)
3317 #define BCE_TBDR_FTQ_CMD_SFT_RESET                       (1L<<25)
3318 #define BCE_TBDR_FTQ_CMD_RD_DATA                         (1L<<26)
3319 #define BCE_TBDR_FTQ_CMD_ADD_INTERVEN                    (1L<<27)
3320 #define BCE_TBDR_FTQ_CMD_ADD_DATA                        (1L<<28)
3321 #define BCE_TBDR_FTQ_CMD_INTERVENE_CLR                   (1L<<29)
3322 #define BCE_TBDR_FTQ_CMD_POP                             (1L<<30)
3323 #define BCE_TBDR_FTQ_CMD_BUSY                            (1L<<31)
3324
3325 #define BCE_TBDR_FTQ_CTL                                0x000053fc
3326 #define BCE_TBDR_FTQ_CTL_INTERVENE                       (1L<<0)
3327 #define BCE_TBDR_FTQ_CTL_OVERFLOW                        (1L<<1)
3328 #define BCE_TBDR_FTQ_CTL_FORCE_INTERVENE                 (1L<<2)
3329 #define BCE_TBDR_FTQ_CTL_MAX_DEPTH                       (0x3ffL<<12)
3330 #define BCE_TBDR_FTQ_CTL_CUR_DEPTH                       (0x3ffL<<22)
3331
3332
3333
3334 /*
3335  *  tdma_reg definition
3336  *  offset: 0x5c00
3337  */
3338 #define BCE_TDMA_COMMAND                                0x00005c00
3339 #define BCE_TDMA_COMMAND_ENABLED                         (1L<<0)
3340 #define BCE_TDMA_COMMAND_MASTER_ABORT                    (1L<<4)
3341 #define BCE_TDMA_COMMAND_BAD_L2_LENGTH_ABORT             (1L<<7)
3342
3343 #define BCE_TDMA_STATUS                         0x00005c04
3344 #define BCE_TDMA_STATUS_DMA_WAIT                         (1L<<0)
3345 #define BCE_TDMA_STATUS_PAYLOAD_WAIT                     (1L<<1)
3346 #define BCE_TDMA_STATUS_PATCH_FTQ_WAIT                   (1L<<2)
3347 #define BCE_TDMA_STATUS_LOCK_WAIT                        (1L<<3)
3348 #define BCE_TDMA_STATUS_FTQ_ENTRY_CNT                    (1L<<16)
3349 #define BCE_TDMA_STATUS_BURST_CNT                        (1L<<17)
3350
3351 #define BCE_TDMA_CONFIG                         0x00005c08
3352 #define BCE_TDMA_CONFIG_ONE_DMA                  (1L<<0)
3353 #define BCE_TDMA_CONFIG_ONE_RECORD                       (1L<<1)
3354 #define BCE_TDMA_CONFIG_LIMIT_SZ                         (0xfL<<4)
3355 #define BCE_TDMA_CONFIG_LIMIT_SZ_64                      (0L<<4)
3356 #define BCE_TDMA_CONFIG_LIMIT_SZ_128                     (0x4L<<4)
3357 #define BCE_TDMA_CONFIG_LIMIT_SZ_256                     (0x6L<<4)
3358 #define BCE_TDMA_CONFIG_LIMIT_SZ_512                     (0x8L<<4)
3359 #define BCE_TDMA_CONFIG_LINE_SZ                  (0xfL<<8)
3360 #define BCE_TDMA_CONFIG_LINE_SZ_64                       (0L<<8)
3361 #define BCE_TDMA_CONFIG_LINE_SZ_128                      (4L<<8)
3362 #define BCE_TDMA_CONFIG_LINE_SZ_256                      (6L<<8)
3363 #define BCE_TDMA_CONFIG_LINE_SZ_512                      (8L<<8)
3364 #define BCE_TDMA_CONFIG_ALIGN_ENA                        (1L<<15)
3365 #define BCE_TDMA_CONFIG_CHK_L2_BD                        (1L<<16)
3366 #define BCE_TDMA_CONFIG_FIFO_CMP                         (0xfL<<20)
3367
3368 #define BCE_TDMA_PAYLOAD_PROD                           0x00005c0c
3369 #define BCE_TDMA_PAYLOAD_PROD_VALUE                      (0x1fffL<<3)
3370
3371 #define BCE_TDMA_DBG_WATCHDOG                           0x00005c10
3372 #define BCE_TDMA_DBG_TRIGGER                            0x00005c14
3373 #define BCE_TDMA_DMAD_FSM                               0x00005c80
3374 #define BCE_TDMA_DMAD_FSM_BD_INVLD                       (1L<<0)
3375 #define BCE_TDMA_DMAD_FSM_PUSH                           (0xfL<<4)
3376 #define BCE_TDMA_DMAD_FSM_ARB_TBDC                       (0x3L<<8)
3377 #define BCE_TDMA_DMAD_FSM_ARB_CTX                        (1L<<12)
3378 #define BCE_TDMA_DMAD_FSM_DR_INTF                        (1L<<16)
3379 #define BCE_TDMA_DMAD_FSM_DMAD                           (0x7L<<20)
3380 #define BCE_TDMA_DMAD_FSM_BD                             (0xfL<<24)
3381
3382 #define BCE_TDMA_DMAD_STATUS                            0x00005c84
3383 #define BCE_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY            (0x3L<<0)
3384 #define BCE_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY            (0x3L<<4)
3385 #define BCE_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY              (0x3L<<8)
3386 #define BCE_TDMA_DMAD_STATUS_IFTQ_ENUM                   (0xfL<<12)
3387
3388 #define BCE_TDMA_DR_INTF_FSM                            0x00005c88
3389 #define BCE_TDMA_DR_INTF_FSM_L2_COMP                     (0x3L<<0)
3390 #define BCE_TDMA_DR_INTF_FSM_TPATQ                       (0x7L<<4)
3391 #define BCE_TDMA_DR_INTF_FSM_TPBUF                       (0x3L<<8)
3392 #define BCE_TDMA_DR_INTF_FSM_DR_BUF                      (0x7L<<12)
3393 #define BCE_TDMA_DR_INTF_FSM_DMAD                        (0x7L<<16)
3394
3395 #define BCE_TDMA_DR_INTF_STATUS                 0x00005c8c
3396 #define BCE_TDMA_DR_INTF_STATUS_HOLE_PHASE               (0x7L<<0)
3397 #define BCE_TDMA_DR_INTF_STATUS_DATA_AVAIL               (0x3L<<4)
3398 #define BCE_TDMA_DR_INTF_STATUS_SHIFT_ADDR               (0x7L<<8)
3399 #define BCE_TDMA_DR_INTF_STATUS_NXT_PNTR                 (0xfL<<12)
3400 #define BCE_TDMA_DR_INTF_STATUS_BYTE_COUNT               (0x7L<<16)
3401
3402 #define BCE_TDMA_FTQ_DATA                               0x00005fc0
3403 #define BCE_TDMA_FTQ_CMD                                0x00005ff8
3404 #define BCE_TDMA_FTQ_CMD_OFFSET                  (0x3ffL<<0)
3405 #define BCE_TDMA_FTQ_CMD_WR_TOP                  (1L<<10)
3406 #define BCE_TDMA_FTQ_CMD_WR_TOP_0                        (0L<<10)
3407 #define BCE_TDMA_FTQ_CMD_WR_TOP_1                        (1L<<10)
3408 #define BCE_TDMA_FTQ_CMD_SFT_RESET                       (1L<<25)
3409 #define BCE_TDMA_FTQ_CMD_RD_DATA                         (1L<<26)
3410 #define BCE_TDMA_FTQ_CMD_ADD_INTERVEN                    (1L<<27)
3411 #define BCE_TDMA_FTQ_CMD_ADD_DATA                        (1L<<28)
3412 #define BCE_TDMA_FTQ_CMD_INTERVENE_CLR                   (1L<<29)
3413 #define BCE_TDMA_FTQ_CMD_POP                             (1L<<30)
3414 #define BCE_TDMA_FTQ_CMD_BUSY                            (1L<<31)
3415
3416 #define BCE_TDMA_FTQ_CTL                                0x00005ffc
3417 #define BCE_TDMA_FTQ_CTL_INTERVENE                       (1L<<0)
3418 #define BCE_TDMA_FTQ_CTL_OVERFLOW                        (1L<<1)
3419 #define BCE_TDMA_FTQ_CTL_FORCE_INTERVENE                 (1L<<2)
3420 #define BCE_TDMA_FTQ_CTL_MAX_DEPTH                       (0x3ffL<<12)
3421 #define BCE_TDMA_FTQ_CTL_CUR_DEPTH                       (0x3ffL<<22)
3422
3423
3424
3425 /*
3426  *  hc_reg definition
3427  *  offset: 0x6800
3428  */
3429 #define BCE_HC_COMMAND                                  0x00006800
3430 #define BCE_HC_COMMAND_ENABLE                            (1L<<0)
3431 #define BCE_HC_COMMAND_SKIP_ABORT                        (1L<<4)
3432 #define BCE_HC_COMMAND_COAL_NOW                  (1L<<16)
3433 #define BCE_HC_COMMAND_COAL_NOW_WO_INT                   (1L<<17)
3434 #define BCE_HC_COMMAND_STATS_NOW                         (1L<<18)
3435 #define BCE_HC_COMMAND_FORCE_INT                         (0x3L<<19)
3436 #define BCE_HC_COMMAND_FORCE_INT_NULL                    (0L<<19)
3437 #define BCE_HC_COMMAND_FORCE_INT_HIGH                    (1L<<19)
3438 #define BCE_HC_COMMAND_FORCE_INT_LOW                     (2L<<19)
3439 #define BCE_HC_COMMAND_FORCE_INT_FREE                    (3L<<19)
3440 #define BCE_HC_COMMAND_CLR_STAT_NOW                      (1L<<21)
3441
3442 #define BCE_HC_STATUS                                   0x00006804
3443 #define BCE_HC_STATUS_MASTER_ABORT                       (1L<<0)
3444 #define BCE_HC_STATUS_PARITY_ERROR_STATE                 (1L<<1)
3445 #define BCE_HC_STATUS_PCI_CLK_CNT_STAT                   (1L<<16)
3446 #define BCE_HC_STATUS_CORE_CLK_CNT_STAT          (1L<<17)
3447 #define BCE_HC_STATUS_NUM_STATUS_BLOCKS_STAT             (1L<<18)
3448 #define BCE_HC_STATUS_NUM_INT_GEN_STAT                   (1L<<19)
3449 #define BCE_HC_STATUS_NUM_INT_MBOX_WR_STAT               (1L<<20)
3450 #define BCE_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT        (1L<<23)
3451 #define BCE_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT        (1L<<24)
3452 #define BCE_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT    (1L<<25)
3453
3454 #define BCE_HC_CONFIG                                   0x00006808
3455 #define BCE_HC_CONFIG_COLLECT_STATS                      (1L<<0)
3456 #define BCE_HC_CONFIG_RX_TMR_MODE                        (1L<<1)
3457 #define BCE_HC_CONFIG_TX_TMR_MODE                        (1L<<2)
3458 #define BCE_HC_CONFIG_COM_TMR_MODE                       (1L<<3)
3459 #define BCE_HC_CONFIG_CMD_TMR_MODE                       (1L<<4)
3460 #define BCE_HC_CONFIG_STATISTIC_PRIORITY                 (1L<<5)
3461 #define BCE_HC_CONFIG_STATUS_PRIORITY                    (1L<<6)
3462 #define BCE_HC_CONFIG_STAT_MEM_ADDR                      (0xffL<<8)
3463
3464 #define BCE_HC_ATTN_BITS_ENABLE                 0x0000680c
3465 #define BCE_HC_STATUS_ADDR_L                            0x00006810
3466 #define BCE_HC_STATUS_ADDR_H                            0x00006814
3467 #define BCE_HC_STATISTICS_ADDR_L                        0x00006818
3468 #define BCE_HC_STATISTICS_ADDR_H                        0x0000681c
3469 #define BCE_HC_TX_QUICK_CONS_TRIP                       0x00006820
3470 #define BCE_HC_TX_QUICK_CONS_TRIP_VALUE          (0xffL<<0)
3471 #define BCE_HC_TX_QUICK_CONS_TRIP_INT                    (0xffL<<16)
3472
3473 #define BCE_HC_COMP_PROD_TRIP                           0x00006824
3474 #define BCE_HC_COMP_PROD_TRIP_VALUE                      (0xffL<<0)
3475 #define BCE_HC_COMP_PROD_TRIP_INT                        (0xffL<<16)
3476
3477 #define BCE_HC_RX_QUICK_CONS_TRIP                       0x00006828
3478 #define BCE_HC_RX_QUICK_CONS_TRIP_VALUE          (0xffL<<0)
3479 #define BCE_HC_RX_QUICK_CONS_TRIP_INT                    (0xffL<<16)
3480
3481 #define BCE_HC_RX_TICKS                         0x0000682c
3482 #define BCE_HC_RX_TICKS_VALUE                            (0x3ffL<<0)
3483 #define BCE_HC_RX_TICKS_INT                              (0x3ffL<<16)
3484
3485 #define BCE_HC_TX_TICKS                         0x00006830
3486 #define BCE_HC_TX_TICKS_VALUE                            (0x3ffL<<0)
3487 #define BCE_HC_TX_TICKS_INT                              (0x3ffL<<16)
3488
3489 #define BCE_HC_COM_TICKS                                0x00006834
3490 #define BCE_HC_COM_TICKS_VALUE                           (0x3ffL<<0)
3491 #define BCE_HC_COM_TICKS_INT                             (0x3ffL<<16)
3492
3493 #define BCE_HC_CMD_TICKS                                0x00006838
3494 #define BCE_HC_CMD_TICKS_VALUE                           (0x3ffL<<0)
3495 #define BCE_HC_CMD_TICKS_INT                             (0x3ffL<<16)
3496
3497 #define BCE_HC_PERIODIC_TICKS                           0x0000683c
3498 #define BCE_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS  (0xffffL<<0)
3499
3500 #define BCE_HC_STAT_COLLECT_TICKS                       0x00006840
3501 #define BCE_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS     (0xffL<<4)
3502
3503 #define BCE_HC_STATS_TICKS                              0x00006844
3504 #define BCE_HC_STATS_TICKS_HC_STAT_TICKS                 (0xffffL<<8)
3505
3506 #define BCE_HC_STAT_MEM_DATA                            0x0000684c
3507 #define BCE_HC_STAT_GEN_SEL_0                           0x00006850
3508 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0          (0x7fL<<0)
3509 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0        (0L<<0)
3510 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1        (1L<<0)
3511 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2        (2L<<0)
3512 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3        (3L<<0)
3513 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4        (4L<<0)
3514 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5        (5L<<0)
3515 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6        (6L<<0)
3516 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7        (7L<<0)
3517 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8        (8L<<0)
3518 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9        (9L<<0)
3519 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10       (10L<<0)
3520 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11       (11L<<0)
3521 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0        (12L<<0)
3522 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1        (13L<<0)
3523 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2        (14L<<0)
3524 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3        (15L<<0)
3525 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4        (16L<<0)
3526 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5        (17L<<0)
3527 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6        (18L<<0)
3528 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7        (19L<<0)
3529 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0        (20L<<0)
3530 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1        (21L<<0)
3531 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2        (22L<<0)
3532 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3        (23L<<0)
3533 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4        (24L<<0)
3534 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5        (25L<<0)
3535 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6        (26L<<0)
3536 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7        (27L<<0)
3537 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8        (28L<<0)
3538 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9        (29L<<0)
3539 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10       (30L<<0)
3540 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11       (31L<<0)
3541 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0       (32L<<0)
3542 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1       (33L<<0)
3543 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2       (34L<<0)
3544 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3       (35L<<0)
3545 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0         (36L<<0)
3546 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1         (37L<<0)
3547 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2         (38L<<0)
3548 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3         (39L<<0)
3549 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4         (40L<<0)
3550 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5         (41L<<0)
3551 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6         (42L<<0)
3552 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7         (43L<<0)
3553 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0        (44L<<0)
3554 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1        (45L<<0)
3555 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2        (46L<<0)
3556 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3        (47L<<0)
3557 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4        (48L<<0)
3558 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5        (49L<<0)
3559 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6        (50L<<0)
3560 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7        (51L<<0)
3561 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT      (52L<<0)
3562 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT     (53L<<0)
3563 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS     (54L<<0)
3564 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN   (55L<<0)
3565 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR       (56L<<0)
3566 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK        (59L<<0)
3567 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK        (60L<<0)
3568 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK    (61L<<0)
3569 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT     (62L<<0)
3570 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT    (63L<<0)
3571 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT     (64L<<0)
3572 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT    (65L<<0)
3573 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT  (66L<<0)
3574 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT   (67L<<0)
3575 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT  (68L<<0)
3576 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT         (69L<<0)
3577 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT         (70L<<0)
3578 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT         (71L<<0)
3579 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT  (72L<<0)
3580 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT  (73L<<0)
3581 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT  (74L<<0)
3582 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT   (75L<<0)
3583 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT  (76L<<0)
3584 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT  (77L<<0)
3585 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT   (78L<<0)
3586 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT    (79L<<0)
3587 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT    (80L<<0)
3588 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT  (81L<<0)
3589 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT  (82L<<0)
3590 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT   (83L<<0)
3591 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT   (84L<<0)
3592 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT  (85L<<0)
3593 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT     (86L<<0)
3594 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT      (87L<<0)
3595 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT         (88L<<0)
3596 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT       (89L<<0)
3597 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT         (90L<<0)
3598 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT    (91L<<0)
3599 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT     (92L<<0)
3600 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT        (93L<<0)
3601 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT      (94L<<0)
3602 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64     (95L<<0)
3603 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64     (96L<<0)
3604 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS       (97L<<0)
3605 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS      (98L<<0)
3606 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT      (99L<<0)
3607 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT    (100L<<0)
3608 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT       (101L<<0)
3609 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT       (102L<<0)
3610 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT   (103L<<0)
3611 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT       (104L<<0)
3612 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT   (105L<<0)
3613 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT       (106L<<0)
3614 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT   (107L<<0)
3615 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT   (108L<<0)
3616 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT        (109L<<0)
3617 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT     (110L<<0)
3618 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT     (111L<<0)
3619 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT     (112L<<0)
3620 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT     (113L<<0)
3621 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT     (114L<<0)
3622 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0       (115L<<0)
3623 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1       (116L<<0)
3624 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2       (117L<<0)
3625 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3       (118L<<0)
3626 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4       (119L<<0)
3627 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5       (120L<<0)
3628 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS  (121L<<0)
3629 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS  (122L<<0)
3630 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT   (127L<<0)
3631 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_1          (0x7fL<<8)
3632 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_2          (0x7fL<<16)
3633 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_3          (0x7fL<<24)
3634
3635 #define BCE_HC_STAT_GEN_SEL_1                           0x00006854
3636 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_4          (0x7fL<<0)
3637 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_5          (0x7fL<<8)
3638 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_6          (0x7fL<<16)
3639 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_7          (0x7fL<<24)
3640
3641 #define BCE_HC_STAT_GEN_SEL_2                           0x00006858
3642 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_8          (0x7fL<<0)
3643 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_9          (0x7fL<<8)
3644 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_10                 (0x7fL<<16)
3645 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_11                 (0x7fL<<24)
3646
3647 #define BCE_HC_STAT_GEN_SEL_3                           0x0000685c
3648 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_12                 (0x7fL<<0)
3649 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_13                 (0x7fL<<8)
3650 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_14                 (0x7fL<<16)
3651 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_15                 (0x7fL<<24)
3652
3653 #define BCE_HC_STAT_GEN_STAT0                           0x00006888
3654 #define BCE_HC_STAT_GEN_STAT1                           0x0000688c
3655 #define BCE_HC_STAT_GEN_STAT2                           0x00006890
3656 #define BCE_HC_STAT_GEN_STAT3                           0x00006894
3657 #define BCE_HC_STAT_GEN_STAT4                           0x00006898
3658 #define BCE_HC_STAT_GEN_STAT5                           0x0000689c
3659 #define BCE_HC_STAT_GEN_STAT6                           0x000068a0
3660 #define BCE_HC_STAT_GEN_STAT7                           0x000068a4
3661 #define BCE_HC_STAT_GEN_STAT8                           0x000068a8
3662 #define BCE_HC_STAT_GEN_STAT9                           0x000068ac
3663 #define BCE_HC_STAT_GEN_STAT10                          0x000068b0
3664 #define BCE_HC_STAT_GEN_STAT11                          0x000068b4
3665 #define BCE_HC_STAT_GEN_STAT12                          0x000068b8
3666 #define BCE_HC_STAT_GEN_STAT13                          0x000068bc
3667 #define BCE_HC_STAT_GEN_STAT14                          0x000068c0
3668 #define BCE_HC_STAT_GEN_STAT15                          0x000068c4
3669 #define BCE_HC_STAT_GEN_STAT_AC0                        0x000068c8
3670 #define BCE_HC_STAT_GEN_STAT_AC1                        0x000068cc
3671 #define BCE_HC_STAT_GEN_STAT_AC2                        0x000068d0
3672 #define BCE_HC_STAT_GEN_STAT_AC3                        0x000068d4
3673 #define BCE_HC_STAT_GEN_STAT_AC4                        0x000068d8
3674 #define BCE_HC_STAT_GEN_STAT_AC5                        0x000068dc
3675 #define BCE_HC_STAT_GEN_STAT_AC6                        0x000068e0
3676 #define BCE_HC_STAT_GEN_STAT_AC7                        0x000068e4
3677 #define BCE_HC_STAT_GEN_STAT_AC8                        0x000068e8
3678 #define BCE_HC_STAT_GEN_STAT_AC9                        0x000068ec
3679 #define BCE_HC_STAT_GEN_STAT_AC10                       0x000068f0
3680 #define BCE_HC_STAT_GEN_STAT_AC11                       0x000068f4
3681 #define BCE_HC_STAT_GEN_STAT_AC12                       0x000068f8
3682 #define BCE_HC_STAT_GEN_STAT_AC13                       0x000068fc
3683 #define BCE_HC_STAT_GEN_STAT_AC14                       0x00006900
3684 #define BCE_HC_STAT_GEN_STAT_AC15                       0x00006904
3685 #define BCE_HC_VIS                                      0x00006908
3686 #define BCE_HC_VIS_STAT_BUILD_STATE                      (0xfL<<0)
3687 #define BCE_HC_VIS_STAT_BUILD_STATE_IDLE                 (0L<<0)
3688 #define BCE_HC_VIS_STAT_BUILD_STATE_START                (1L<<0)
3689 #define BCE_HC_VIS_STAT_BUILD_STATE_REQUEST              (2L<<0)
3690 #define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE64             (3L<<0)
3691 #define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE32             (4L<<0)
3692 #define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE  (5L<<0)
3693 #define BCE_HC_VIS_STAT_BUILD_STATE_DMA          (6L<<0)
3694 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL  (7L<<0)
3695 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_LOW              (8L<<0)
3696 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_HIGH             (9L<<0)
3697 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_DATA             (10L<<0)
3698 #define BCE_HC_VIS_DMA_STAT_STATE                        (0xfL<<8)
3699 #define BCE_HC_VIS_DMA_STAT_STATE_IDLE                   (0L<<8)
3700 #define BCE_HC_VIS_DMA_STAT_STATE_STATUS_PARAM           (1L<<8)
3701 #define BCE_HC_VIS_DMA_STAT_STATE_STATUS_DMA             (2L<<8)
3702 #define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP             (3L<<8)
3703 #define BCE_HC_VIS_DMA_STAT_STATE_COMP                   (4L<<8)
3704 #define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM        (5L<<8)
3705 #define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA  (6L<<8)
3706 #define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1           (7L<<8)
3707 #define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2           (8L<<8)
3708 #define BCE_HC_VIS_DMA_STAT_STATE_WAIT                   (9L<<8)
3709 #define BCE_HC_VIS_DMA_STAT_STATE_ABORT          (15L<<8)
3710 #define BCE_HC_VIS_DMA_MSI_STATE                         (0x7L<<12)
3711 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE                (0x3L<<15)
3712 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE           (0L<<15)
3713 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT  (1L<<15)
3714 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_START  (2L<<15)
3715
3716 #define BCE_HC_VIS_1                                    0x0000690c
3717 #define BCE_HC_VIS_1_HW_INTACK_STATE                     (1L<<4)
3718 #define BCE_HC_VIS_1_HW_INTACK_STATE_IDLE                (0L<<4)
3719 #define BCE_HC_VIS_1_HW_INTACK_STATE_COUNT               (1L<<4)
3720 #define BCE_HC_VIS_1_SW_INTACK_STATE                     (1L<<5)
3721 #define BCE_HC_VIS_1_SW_INTACK_STATE_IDLE                (0L<<5)
3722 #define BCE_HC_VIS_1_SW_INTACK_STATE_COUNT               (1L<<5)
3723 #define BCE_HC_VIS_1_DURING_SW_INTACK_STATE              (1L<<6)
3724 #define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE         (0L<<6)
3725 #define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT        (1L<<6)
3726 #define BCE_HC_VIS_1_MAILBOX_COUNT_STATE                 (1L<<7)
3727 #define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE            (0L<<7)
3728 #define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT           (1L<<7)
3729 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE                    (0xfL<<17)
3730 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_IDLE               (0L<<17)
3731 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_DMA                (1L<<17)
3732 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE             (2L<<17)
3733 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN             (3L<<17)
3734 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_WAIT               (4L<<17)
3735 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE         (5L<<17)
3736 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN         (6L<<17)
3737 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT           (7L<<17)
3738 #define BCE_HC_VIS_1_RAM_WR_ARB_STATE                    (0x3L<<21)
3739 #define BCE_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL             (0L<<21)
3740 #define BCE_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR              (1L<<21)
3741 #define BCE_HC_VIS_1_INT_GEN_STATE                       (1L<<23)
3742 #define BCE_HC_VIS_1_INT_GEN_STATE_DLE                   (0L<<23)
3743 #define BCE_HC_VIS_1_INT_GEN_STATE_NTERRUPT              (1L<<23)
3744 #define BCE_HC_VIS_1_STAT_CHAN_ID                        (0x7L<<24)
3745 #define BCE_HC_VIS_1_INT_B                               (1L<<27)
3746
3747 #define BCE_HC_DEBUG_VECT_PEEK                          0x00006910
3748 #define BCE_HC_DEBUG_VECT_PEEK_1_VALUE                   (0x7ffL<<0)
3749 #define BCE_HC_DEBUG_VECT_PEEK_1_PEEK_EN                 (1L<<11)
3750 #define BCE_HC_DEBUG_VECT_PEEK_1_SEL                     (0xfL<<12)
3751 #define BCE_HC_DEBUG_VECT_PEEK_2_VALUE                   (0x7ffL<<16)
3752 #define BCE_HC_DEBUG_VECT_PEEK_2_PEEK_EN                 (1L<<27)
3753 #define BCE_HC_DEBUG_VECT_PEEK_2_SEL                     (0xfL<<28)
3754
3755
3756
3757 /*
3758  *  txp_reg definition
3759  *  offset: 0x40000
3760  */
3761 #define BCE_TXP_CPU_MODE                                0x00045000
3762 #define BCE_TXP_CPU_MODE_LOCAL_RST                       (1L<<0)
3763 #define BCE_TXP_CPU_MODE_STEP_ENA                        (1L<<1)
3764 #define BCE_TXP_CPU_MODE_PAGE_0_DATA_ENA                 (1L<<2)
3765 #define BCE_TXP_CPU_MODE_PAGE_0_INST_ENA                 (1L<<3)
3766 #define BCE_TXP_CPU_MODE_MSG_BIT1                        (1L<<6)
3767 #define BCE_TXP_CPU_MODE_INTERRUPT_ENA                   (1L<<7)
3768 #define BCE_TXP_CPU_MODE_SOFT_HALT                       (1L<<10)
3769 #define BCE_TXP_CPU_MODE_BAD_DATA_HALT_ENA               (1L<<11)
3770 #define BCE_TXP_CPU_MODE_BAD_INST_HALT_ENA               (1L<<12)
3771 #define BCE_TXP_CPU_MODE_FIO_ABORT_HALT_ENA              (1L<<13)
3772 #define BCE_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA         (1L<<15)
3773
3774 #define BCE_TXP_CPU_STATE                               0x00045004
3775 #define BCE_TXP_CPU_STATE_BREAKPOINT                     (1L<<0)
3776 #define BCE_TXP_CPU_STATE_BAD_INST_HALTED                (1L<<2)
3777 #define BCE_TXP_CPU_STATE_PAGE_0_DATA_HALTED             (1L<<3)
3778 #define BCE_TXP_CPU_STATE_PAGE_0_INST_HALTED             (1L<<4)
3779 #define BCE_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED           (1L<<5)
3780 #define BCE_TXP_CPU_STATE_BAD_pc_HALTED          (1L<<6)
3781 #define BCE_TXP_CPU_STATE_ALIGN_HALTED                   (1L<<7)
3782 #define BCE_TXP_CPU_STATE_FIO_ABORT_HALTED               (1L<<8)
3783 #define BCE_TXP_CPU_STATE_SOFT_HALTED                    (1L<<10)
3784 #define BCE_TXP_CPU_STATE_SPAD_UNDERFLOW                 (1L<<11)
3785 #define BCE_TXP_CPU_STATE_INTERRRUPT                     (1L<<12)
3786 #define BCE_TXP_CPU_STATE_DATA_ACCESS_STALL              (1L<<14)
3787 #define BCE_TXP_CPU_STATE_INST_FETCH_STALL               (1L<<15)
3788 #define BCE_TXP_CPU_STATE_BLOCKED_READ                   (1L<<31)
3789
3790 #define BCE_TXP_CPU_EVENT_MASK                          0x00045008
3791 #define BCE_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK           (1L<<0)
3792 #define BCE_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK      (1L<<2)
3793 #define BCE_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK   (1L<<3)
3794 #define BCE_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK   (1L<<4)
3795 #define BCE_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK         (1L<<5)
3796 #define BCE_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK        (1L<<6)
3797 #define BCE_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK         (1L<<7)
3798 #define BCE_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK            (1L<<8)
3799 #define BCE_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK  (1L<<10)
3800 #define BCE_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK       (1L<<11)
3801 #define BCE_TXP_CPU_EVENT_MASK_INTERRUPT_MASK            (1L<<12)
3802
3803 #define BCE_TXP_CPU_PROGRAM_COUNTER                     0x0004501c
3804 #define BCE_TXP_CPU_INSTRUCTION                 0x00045020
3805 #define BCE_TXP_CPU_DATA_ACCESS                 0x00045024
3806 #define BCE_TXP_CPU_INTERRUPT_ENABLE                    0x00045028
3807 #define BCE_TXP_CPU_INTERRUPT_VECTOR                    0x0004502c
3808 #define BCE_TXP_CPU_INTERRUPT_SAVED_PC                  0x00045030
3809 #define BCE_TXP_CPU_HW_BREAKPOINT                       0x00045034
3810 #define BCE_TXP_CPU_HW_BREAKPOINT_DISABLE                (1L<<0)
3811 #define BCE_TXP_CPU_HW_BREAKPOINT_ADDRESS                (0x3fffffffL<<2)
3812
3813 #define BCE_TXP_CPU_DEBUG_VECT_PEEK                     0x00045038
3814 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE              (0x7ffL<<0)
3815 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN            (1L<<11)
3816 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_SEL                (0xfL<<12)
3817 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE              (0x7ffL<<16)
3818 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN            (1L<<27)
3819 #define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_SEL                (0xfL<<28)
3820
3821 #define BCE_TXP_CPU_LAST_BRANCH_ADDR                    0x00045048
3822 #define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE                (1L<<1)
3823 #define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP           (0L<<1)
3824 #define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH         (1L<<1)
3825 #define BCE_TXP_CPU_LAST_BRANCH_ADDR_LBA                 (0x3fffffffL<<2)
3826
3827 #define BCE_TXP_CPU_REG_FILE                            0x00045200
3828 #define BCE_TXP_FTQ_DATA                                0x000453c0
3829 #define BCE_TXP_FTQ_CMD                         0x000453f8
3830 #define BCE_TXP_FTQ_CMD_OFFSET                           (0x3ffL<<0)
3831 #define BCE_TXP_FTQ_CMD_WR_TOP                           (1L<<10)
3832 #define BCE_TXP_FTQ_CMD_WR_TOP_0                         (0L<<10)
3833 #define BCE_TXP_FTQ_CMD_WR_TOP_1                         (1L<<10)
3834 #define BCE_TXP_FTQ_CMD_SFT_RESET                        (1L<<25)
3835 #define BCE_TXP_FTQ_CMD_RD_DATA                  (1L<<26)
3836 #define BCE_TXP_FTQ_CMD_ADD_INTERVEN                     (1L<<27)
3837 #define BCE_TXP_FTQ_CMD_ADD_DATA                         (1L<<28)
3838 #define BCE_TXP_FTQ_CMD_INTERVENE_CLR                    (1L<<29)
3839 #define BCE_TXP_FTQ_CMD_POP                              (1L<<30)
3840 #define BCE_TXP_FTQ_CMD_BUSY                             (1L<<31)
3841
3842 #define BCE_TXP_FTQ_CTL                         0x000453fc
3843 #define BCE_TXP_FTQ_CTL_INTERVENE                        (1L<<0)
3844 #define BCE_TXP_FTQ_CTL_OVERFLOW                         (1L<<1)
3845 #define BCE_TXP_FTQ_CTL_FORCE_INTERVENE          (1L<<2)
3846 #define BCE_TXP_FTQ_CTL_MAX_DEPTH                        (0x3ffL<<12)
3847 #define BCE_TXP_FTQ_CTL_CUR_DEPTH                        (0x3ffL<<22)
3848
3849 #define BCE_TXP_SCRATCH                         0x00060000
3850
3851
3852 /*
3853  *  tpat_reg definition
3854  *  offset: 0x80000
3855  */
3856 #define BCE_TPAT_CPU_MODE                               0x00085000
3857 #define BCE_TPAT_CPU_MODE_LOCAL_RST                      (1L<<0)
3858 #define BCE_TPAT_CPU_MODE_STEP_ENA                       (1L<<1)
3859 #define BCE_TPAT_CPU_MODE_PAGE_0_DATA_ENA                (1L<<2)
3860 #define BCE_TPAT_CPU_MODE_PAGE_0_INST_ENA                (1L<<3)
3861 #define BCE_TPAT_CPU_MODE_MSG_BIT1                       (1L<<6)
3862 #define BCE_TPAT_CPU_MODE_INTERRUPT_ENA          (1L<<7)
3863 #define BCE_TPAT_CPU_MODE_SOFT_HALT                      (1L<<10)
3864 #define BCE_TPAT_CPU_MODE_BAD_DATA_HALT_ENA              (1L<<11)
3865 #define BCE_TPAT_CPU_MODE_BAD_INST_HALT_ENA              (1L<<12)
3866 #define BCE_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA             (1L<<13)
3867 #define BCE_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA        (1L<<15)
3868
3869 #define BCE_TPAT_CPU_STATE                              0x00085004
3870 #define BCE_TPAT_CPU_STATE_BREAKPOINT                    (1L<<0)
3871 #define BCE_TPAT_CPU_STATE_BAD_INST_HALTED               (1L<<2)
3872 #define BCE_TPAT_CPU_STATE_PAGE_0_DATA_HALTED            (1L<<3)
3873 #define BCE_TPAT_CPU_STATE_PAGE_0_INST_HALTED            (1L<<4)
3874 #define BCE_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED  (1L<<5)
3875 #define BCE_TPAT_CPU_STATE_BAD_pc_HALTED                 (1L<<6)
3876 #define BCE_TPAT_CPU_STATE_ALIGN_HALTED          (1L<<7)
3877 #define BCE_TPAT_CPU_STATE_FIO_ABORT_HALTED              (1L<<8)
3878 #define BCE_TPAT_CPU_STATE_SOFT_HALTED                   (1L<<10)
3879 #define BCE_TPAT_CPU_STATE_SPAD_UNDERFLOW                (1L<<11)
3880 #define BCE_TPAT_CPU_STATE_INTERRRUPT                    (1L<<12)
3881 #define BCE_TPAT_CPU_STATE_DATA_ACCESS_STALL             (1L<<14)
3882 #define BCE_TPAT_CPU_STATE_INST_FETCH_STALL              (1L<<15)
3883 #define BCE_TPAT_CPU_STATE_BLOCKED_READ          (1L<<31)
3884
3885 #define BCE_TPAT_CPU_EVENT_MASK                 0x00085008
3886 #define BCE_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK  (1L<<0)
3887 #define BCE_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK     (1L<<2)
3888 #define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK  (1L<<3)
3889 #define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK  (1L<<4)
3890 #define BCE_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK        (1L<<5)
3891 #define BCE_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK       (1L<<6)
3892 #define BCE_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK        (1L<<7)
3893 #define BCE_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK           (1L<<8)
3894 #define BCE_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK         (1L<<10)
3895 #define BCE_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK      (1L<<11)
3896 #define BCE_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK           (1L<<12)
3897
3898 #define BCE_TPAT_CPU_PROGRAM_COUNTER                    0x0008501c
3899 #define BCE_TPAT_CPU_INSTRUCTION                        0x00085020
3900 #define BCE_TPAT_CPU_DATA_ACCESS                        0x00085024
3901 #define BCE_TPAT_CPU_INTERRUPT_ENABLE                   0x00085028
3902 #define BCE_TPAT_CPU_INTERRUPT_VECTOR                   0x0008502c
3903 #define BCE_TPAT_CPU_INTERRUPT_SAVED_PC         0x00085030
3904 #define BCE_TPAT_CPU_HW_BREAKPOINT                      0x00085034
3905 #define BCE_TPAT_CPU_HW_BREAKPOINT_DISABLE               (1L<<0)
3906 #define BCE_TPAT_CPU_HW_BREAKPOINT_ADDRESS               (0x3fffffffL<<2)
3907
3908 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK                    0x00085038
3909 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE             (0x7ffL<<0)
3910 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN           (1L<<11)
3911 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL               (0xfL<<12)
3912 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE             (0x7ffL<<16)
3913 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN           (1L<<27)
3914 #define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL               (0xfL<<28)
3915
3916 #define BCE_TPAT_CPU_LAST_BRANCH_ADDR                   0x00085048
3917 #define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE               (1L<<1)
3918 #define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP  (0L<<1)
3919 #define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH        (1L<<1)
3920 #define BCE_TPAT_CPU_LAST_BRANCH_ADDR_LBA                (0x3fffffffL<<2)
3921
3922 #define BCE_TPAT_CPU_REG_FILE                           0x00085200
3923 #define BCE_TPAT_FTQ_DATA                               0x000853c0
3924 #define BCE_TPAT_FTQ_CMD                                0x000853f8
3925 #define BCE_TPAT_FTQ_CMD_OFFSET                  (0x3ffL<<0)
3926 #define BCE_TPAT_FTQ_CMD_WR_TOP                  (1L<<10)
3927 #define BCE_TPAT_FTQ_CMD_WR_TOP_0                        (0L<<10)
3928 #define BCE_TPAT_FTQ_CMD_WR_TOP_1                        (1L<<10)
3929 #define BCE_TPAT_FTQ_CMD_SFT_RESET                       (1L<<25)
3930 #define BCE_TPAT_FTQ_CMD_RD_DATA                         (1L<<26)
3931 #define BCE_TPAT_FTQ_CMD_ADD_INTERVEN                    (1L<<27)
3932 #define BCE_TPAT_FTQ_CMD_ADD_DATA                        (1L<<28)
3933 #define BCE_TPAT_FTQ_CMD_INTERVENE_CLR                   (1L<<29)
3934 #define BCE_TPAT_FTQ_CMD_POP                             (1L<<30)
3935 #define BCE_TPAT_FTQ_CMD_BUSY                            (1L<<31)
3936
3937 #define BCE_TPAT_FTQ_CTL                                0x000853fc
3938 #define BCE_TPAT_FTQ_CTL_INTERVENE                       (1L<<0)
3939 #define BCE_TPAT_FTQ_CTL_OVERFLOW                        (1L<<1)
3940 #define BCE_TPAT_FTQ_CTL_FORCE_INTERVENE                 (1L<<2)
3941 #define BCE_TPAT_FTQ_CTL_MAX_DEPTH                       (0x3ffL<<12)
3942 #define BCE_TPAT_FTQ_CTL_CUR_DEPTH                       (0x3ffL<<22)
3943
3944 #define BCE_TPAT_SCRATCH                                0x000a0000
3945
3946
3947 /*
3948  *  rxp_reg definition
3949  *  offset: 0xc0000
3950  */
3951 #define BCE_RXP_CPU_MODE                                0x000c5000
3952 #define BCE_RXP_CPU_MODE_LOCAL_RST                       (1L<<0)
3953 #define BCE_RXP_CPU_MODE_STEP_ENA                        (1L<<1)
3954 #define BCE_RXP_CPU_MODE_PAGE_0_DATA_ENA                 (1L<<2)
3955 #define BCE_RXP_CPU_MODE_PAGE_0_INST_ENA                 (1L<<3)
3956 #define BCE_RXP_CPU_MODE_MSG_BIT1                        (1L<<6)
3957 #define BCE_RXP_CPU_MODE_INTERRUPT_ENA                   (1L<<7)
3958 #define BCE_RXP_CPU_MODE_SOFT_HALT                       (1L<<10)
3959 #define BCE_RXP_CPU_MODE_BAD_DATA_HALT_ENA               (1L<<11)
3960 #define BCE_RXP_CPU_MODE_BAD_INST_HALT_ENA               (1L<<12)
3961 #define BCE_RXP_CPU_MODE_FIO_ABORT_HALT_ENA              (1L<<13)
3962 #define BCE_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA         (1L<<15)
3963
3964 #define BCE_RXP_CPU_STATE                               0x000c5004
3965 #define BCE_RXP_CPU_STATE_BREAKPOINT                     (1L<<0)
3966 #define BCE_RXP_CPU_STATE_BAD_INST_HALTED                (1L<<2)
3967 #define BCE_RXP_CPU_STATE_PAGE_0_DATA_HALTED             (1L<<3)
3968 #define BCE_RXP_CPU_STATE_PAGE_0_INST_HALTED             (1L<<4)
3969 #define BCE_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED           (1L<<5)
3970 #define BCE_RXP_CPU_STATE_BAD_pc_HALTED          (1L<<6)
3971 #define BCE_RXP_CPU_STATE_ALIGN_HALTED                   (1L<<7)
3972 #define BCE_RXP_CPU_STATE_FIO_ABORT_HALTED               (1L<<8)
3973 #define BCE_RXP_CPU_STATE_SOFT_HALTED                    (1L<<10)
3974 #define BCE_RXP_CPU_STATE_SPAD_UNDERFLOW                 (1L<<11)
3975 #define BCE_RXP_CPU_STATE_INTERRRUPT                     (1L<<12)
3976 #define BCE_RXP_CPU_STATE_DATA_ACCESS_STALL              (1L<<14)
3977 #define BCE_RXP_CPU_STATE_INST_FETCH_STALL               (1L<<15)
3978 #define BCE_RXP_CPU_STATE_BLOCKED_READ                   (1L<<31)
3979
3980 #define BCE_RXP_CPU_EVENT_MASK                          0x000c5008
3981 #define BCE_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK           (1L<<0)
3982 #define BCE_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK      (1L<<2)
3983 #define BCE_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK   (1L<<3)
3984 #define BCE_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK   (1L<<4)
3985 #define BCE_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK         (1L<<5)
3986 #define BCE_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK        (1L<<6)
3987 #define BCE_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK         (1L<<7)
3988 #define BCE_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK            (1L<<8)
3989 #define BCE_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK  (1L<<10)
3990 #define BCE_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK       (1L<<11)
3991 #define BCE_RXP_CPU_EVENT_MASK_INTERRUPT_MASK            (1L<<12)
3992
3993 #define BCE_RXP_CPU_PROGRAM_COUNTER                     0x000c501c
3994 #define BCE_RXP_CPU_INSTRUCTION                 0x000c5020
3995 #define BCE_RXP_CPU_DATA_ACCESS                 0x000c5024
3996 #define BCE_RXP_CPU_INTERRUPT_ENABLE                    0x000c5028
3997 #define BCE_RXP_CPU_INTERRUPT_VECTOR                    0x000c502c
3998 #define BCE_RXP_CPU_INTERRUPT_SAVED_PC                  0x000c5030
3999 #define BCE_RXP_CPU_HW_BREAKPOINT                       0x000c5034
4000 #define BCE_RXP_CPU_HW_BREAKPOINT_DISABLE                (1L<<0)
4001 #define BCE_RXP_CPU_HW_BREAKPOINT_ADDRESS                (0x3fffffffL<<2)
4002
4003 #define BCE_RXP_CPU_DEBUG_VECT_PEEK                     0x000c5038
4004 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE              (0x7ffL<<0)
4005 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN            (1L<<11)
4006 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_SEL                (0xfL<<12)
4007 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE              (0x7ffL<<16)
4008 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN            (1L<<27)
4009 #define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_SEL                (0xfL<<28)
4010
4011 #define BCE_RXP_CPU_LAST_BRANCH_ADDR                    0x000c5048
4012 #define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE                (1L<<1)
4013 #define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP           (0L<<1)
4014 #define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH         (1L<<1)
4015 #define BCE_RXP_CPU_LAST_BRANCH_ADDR_LBA                 (0x3fffffffL<<2)
4016
4017 #define BCE_RXP_CPU_REG_FILE                            0x000c5200
4018 #define BCE_RXP_CFTQ_DATA                               0x000c5380
4019 #define BCE_RXP_CFTQ_CMD                                0x000c53b8
4020 #define BCE_RXP_CFTQ_CMD_OFFSET                  (0x3ffL<<0)
4021 #define BCE_RXP_CFTQ_CMD_WR_TOP                  (1L<<10)
4022 #define BCE_RXP_CFTQ_CMD_WR_TOP_0                        (0L<<10)
4023 #define BCE_RXP_CFTQ_CMD_WR_TOP_1                        (1L<<10)
4024 #define BCE_RXP_CFTQ_CMD_SFT_RESET                       (1L<<25)
4025 #define BCE_RXP_CFTQ_CMD_RD_DATA                         (1L<<26)
4026 #define BCE_RXP_CFTQ_CMD_ADD_INTERVEN                    (1L<<27)
4027 #define BCE_RXP_CFTQ_CMD_ADD_DATA                        (1L<<28)
4028 #define BCE_RXP_CFTQ_CMD_INTERVENE_CLR                   (1L<<29)
4029 #define BCE_RXP_CFTQ_CMD_POP                             (1L<<30)
4030 #define BCE_RXP_CFTQ_CMD_BUSY                            (1L<<31)
4031
4032 #define BCE_RXP_CFTQ_CTL                                0x000c53bc
4033 #define BCE_RXP_CFTQ_CTL_INTERVENE                       (1L<<0)
4034 #define BCE_RXP_CFTQ_CTL_OVERFLOW                        (1L<<1)
4035 #define BCE_RXP_CFTQ_CTL_FORCE_INTERVENE                 (1L<<2)
4036 #define BCE_RXP_CFTQ_CTL_MAX_DEPTH                       (0x3ffL<<12)
4037 #define BCE_RXP_CFTQ_CTL_CUR_DEPTH                       (0x3ffL<<22)
4038
4039 #define BCE_RXP_FTQ_DATA                                0x000c53c0
4040 #define BCE_RXP_FTQ_CMD                         0x000c53f8
4041 #define BCE_RXP_FTQ_CMD_OFFSET                           (0x3ffL<<0)
4042 #define BCE_RXP_FTQ_CMD_WR_TOP                           (1L<<10)
4043 #define BCE_RXP_FTQ_CMD_WR_TOP_0                         (0L<<10)
4044 #define BCE_RXP_FTQ_CMD_WR_TOP_1                         (1L<<10)
4045 #define BCE_RXP_FTQ_CMD_SFT_RESET                        (1L<<25)
4046 #define BCE_RXP_FTQ_CMD_RD_DATA                  (1L<<26)
4047 #define BCE_RXP_FTQ_CMD_ADD_INTERVEN                     (1L<<27)
4048 #define BCE_RXP_FTQ_CMD_ADD_DATA                         (1L<<28)
4049 #define BCE_RXP_FTQ_CMD_INTERVENE_CLR                    (1L<<29)
4050 #define BCE_RXP_FTQ_CMD_POP                              (1L<<30)
4051 #define BCE_RXP_FTQ_CMD_BUSY                             (1L<<31)
4052
4053 #define BCE_RXP_FTQ_CTL                         0x000c53fc
4054 #define BCE_RXP_FTQ_CTL_INTERVENE                        (1L<<0)
4055 #define BCE_RXP_FTQ_CTL_OVERFLOW                         (1L<<1)
4056 #define BCE_RXP_FTQ_CTL_FORCE_INTERVENE          (1L<<2)
4057 #define BCE_RXP_FTQ_CTL_MAX_DEPTH                        (0x3ffL<<12)
4058 #define BCE_RXP_FTQ_CTL_CUR_DEPTH                        (0x3ffL<<22)
4059
4060 #define BCE_RXP_SCRATCH                         0x000e0000
4061
4062
4063 /*
4064  *  com_reg definition
4065  *  offset: 0x100000
4066  */
4067 #define BCE_COM_CPU_MODE                                0x00105000
4068 #define BCE_COM_CPU_MODE_LOCAL_RST                       (1L<<0)
4069 #define BCE_COM_CPU_MODE_STEP_ENA                        (1L<<1)
4070 #define BCE_COM_CPU_MODE_PAGE_0_DATA_ENA                 (1L<<2)
4071 #define BCE_COM_CPU_MODE_PAGE_0_INST_ENA                 (1L<<3)
4072 #define BCE_COM_CPU_MODE_MSG_BIT1                        (1L<<6)
4073 #define BCE_COM_CPU_MODE_INTERRUPT_ENA                   (1L<<7)
4074 #define BCE_COM_CPU_MODE_SOFT_HALT                       (1L<<10)
4075 #define BCE_COM_CPU_MODE_BAD_DATA_HALT_ENA               (1L<<11)
4076 #define BCE_COM_CPU_MODE_BAD_INST_HALT_ENA               (1L<<12)
4077 #define BCE_COM_CPU_MODE_FIO_ABORT_HALT_ENA              (1L<<13)
4078 #define BCE_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA         (1L<<15)
4079
4080 #define BCE_COM_CPU_STATE                               0x00105004
4081 #define BCE_COM_CPU_STATE_BREAKPOINT                     (1L<<0)
4082 #define BCE_COM_CPU_STATE_BAD_INST_HALTED                (1L<<2)
4083 #define BCE_COM_CPU_STATE_PAGE_0_DATA_HALTED             (1L<<3)
4084 #define BCE_COM_CPU_STATE_PAGE_0_INST_HALTED             (1L<<4)
4085 #define BCE_COM_CPU_STATE_BAD_DATA_ADDR_HALTED           (1L<<5)
4086 #define BCE_COM_CPU_STATE_BAD_pc_HALTED          (1L<<6)
4087 #define BCE_COM_CPU_STATE_ALIGN_HALTED                   (1L<<7)
4088 #define BCE_COM_CPU_STATE_FIO_ABORT_HALTED               (1L<<8)
4089 #define BCE_COM_CPU_STATE_SOFT_HALTED                    (1L<<10)
4090 #define BCE_COM_CPU_STATE_SPAD_UNDERFLOW                 (1L<<11)
4091 #define BCE_COM_CPU_STATE_INTERRRUPT                     (1L<<12)
4092 #define BCE_COM_CPU_STATE_DATA_ACCESS_STALL              (1L<<14)
4093 #define BCE_COM_CPU_STATE_INST_FETCH_STALL               (1L<<15)
4094 #define BCE_COM_CPU_STATE_BLOCKED_READ                   (1L<<31)
4095
4096 #define BCE_COM_CPU_EVENT_MASK                          0x00105008
4097 #define BCE_COM_CPU_EVENT_MASK_BREAKPOINT_MASK           (1L<<0)
4098 #define BCE_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK      (1L<<2)
4099 #define BCE_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK   (1L<<3)
4100 #define BCE_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK   (1L<<4)
4101 #define BCE_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK         (1L<<5)
4102 #define BCE_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK        (1L<<6)
4103 #define BCE_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK         (1L<<7)
4104 #define BCE_COM_CPU_EVENT_MASK_FIO_ABORT_MASK            (1L<<8)
4105 #define BCE_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK  (1L<<10)
4106 #define BCE_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK       (1L<<11)
4107 #define BCE_COM_CPU_EVENT_MASK_INTERRUPT_MASK            (1L<<12)
4108
4109 #define BCE_COM_CPU_PROGRAM_COUNTER                     0x0010501c
4110 #define BCE_COM_CPU_INSTRUCTION                 0x00105020
4111 #define BCE_COM_CPU_DATA_ACCESS                 0x00105024
4112 #define BCE_COM_CPU_INTERRUPT_ENABLE                    0x00105028
4113 #define BCE_COM_CPU_INTERRUPT_VECTOR                    0x0010502c
4114 #define BCE_COM_CPU_INTERRUPT_SAVED_PC                  0x00105030
4115 #define BCE_COM_CPU_HW_BREAKPOINT                       0x00105034
4116 #define BCE_COM_CPU_HW_BREAKPOINT_DISABLE                (1L<<0)
4117 #define BCE_COM_CPU_HW_BREAKPOINT_ADDRESS                (0x3fffffffL<<2)
4118
4119 #define BCE_COM_CPU_DEBUG_VECT_PEEK                     0x00105038
4120 #define BCE_COM_CPU_DEBUG_VECT_PEEK_1_VALUE              (0x7ffL<<0)
4121 #define BCE_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN            (1L<<11)
4122 #define BCE_COM_CPU_DEBUG_VECT_PEEK_1_SEL                (0xfL<<12)
4123 #define BCE_COM_CPU_DEBUG_VECT_PEEK_2_VALUE              (0x7ffL<<16)
4124 #define BCE_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN            (1L<<27)
4125 #define BCE_COM_CPU_DEBUG_VECT_PEEK_2_SEL                (0xfL<<28)
4126
4127 #define BCE_COM_CPU_LAST_BRANCH_ADDR                    0x00105048
4128 #define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE                (1L<<1)
4129 #define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP           (0L<<1)
4130 #define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH         (1L<<1)
4131 #define BCE_COM_CPU_LAST_BRANCH_ADDR_LBA                 (0x3fffffffL<<2)
4132
4133 #define BCE_COM_CPU_REG_FILE                            0x00105200
4134 #define BCE_COM_COMXQ_FTQ_DATA                          0x00105340
4135 #define BCE_COM_COMXQ_FTQ_CMD                           0x00105378
4136 #define BCE_COM_COMXQ_FTQ_CMD_OFFSET                     (0x3ffL<<0)
4137 #define BCE_COM_COMXQ_FTQ_CMD_WR_TOP                     (1L<<10)
4138 #define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_0                   (0L<<10)
4139 #define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_1                   (1L<<10)
4140 #define BCE_COM_COMXQ_FTQ_CMD_SFT_RESET          (1L<<25)
4141 #define BCE_COM_COMXQ_FTQ_CMD_RD_DATA                    (1L<<26)
4142 #define BCE_COM_COMXQ_FTQ_CMD_ADD_INTERVEN               (1L<<27)
4143 #define BCE_COM_COMXQ_FTQ_CMD_ADD_DATA                   (1L<<28)
4144 #define BCE_COM_COMXQ_FTQ_CMD_INTERVENE_CLR              (1L<<29)
4145 #define BCE_COM_COMXQ_FTQ_CMD_POP                        (1L<<30)
4146 #define BCE_COM_COMXQ_FTQ_CMD_BUSY                       (1L<<31)
4147
4148 #define BCE_COM_COMXQ_FTQ_CTL                           0x0010537c
4149 #define BCE_COM_COMXQ_FTQ_CTL_INTERVENE          (1L<<0)
4150 #define BCE_COM_COMXQ_FTQ_CTL_OVERFLOW                   (1L<<1)
4151 #define BCE_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE            (1L<<2)
4152 #define BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH          (0x3ffL<<12)
4153 #define BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH          (0x3ffL<<22)
4154
4155 #define BCE_COM_COMTQ_FTQ_DATA                          0x00105380
4156 #define BCE_COM_COMTQ_FTQ_CMD                           0x001053b8
4157 #define BCE_COM_COMTQ_FTQ_CMD_OFFSET                     (0x3ffL<<0)
4158 #define BCE_COM_COMTQ_FTQ_CMD_WR_TOP                     (1L<<10)
4159 #define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_0                   (0L<<10)
4160 #define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_1                   (1L<<10)
4161 #define BCE_COM_COMTQ_FTQ_CMD_SFT_RESET          (1L<<25)
4162 #define BCE_COM_COMTQ_FTQ_CMD_RD_DATA                    (1L<<26)
4163 #define BCE_COM_COMTQ_FTQ_CMD_ADD_INTERVEN               (1L<<27)
4164 #define BCE_COM_COMTQ_FTQ_CMD_ADD_DATA                   (1L<<28)
4165 #define BCE_COM_COMTQ_FTQ_CMD_INTERVENE_CLR              (1L<<29)
4166 #define BCE_COM_COMTQ_FTQ_CMD_POP                        (1L<<30)
4167 #define BCE_COM_COMTQ_FTQ_CMD_BUSY                       (1L<<31)
4168
4169 #define BCE_COM_COMTQ_FTQ_CTL                           0x001053bc
4170 #define BCE_COM_COMTQ_FTQ_CTL_INTERVENE          (1L<<0)
4171 #define BCE_COM_COMTQ_FTQ_CTL_OVERFLOW                   (1L<<1)
4172 #define BCE_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE            (1L<<2)
4173 #define BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH          (0x3ffL<<12)
4174 #define BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH          (0x3ffL<<22)
4175
4176 #define BCE_COM_COMQ_FTQ_DATA                           0x001053c0
4177 #define BCE_COM_COMQ_FTQ_CMD                            0x001053f8
4178 #define BCE_COM_COMQ_FTQ_CMD_OFFSET                      (0x3ffL<<0)
4179 #define BCE_COM_COMQ_FTQ_CMD_WR_TOP                      (1L<<10)
4180 #define BCE_COM_COMQ_FTQ_CMD_WR_TOP_0                    (0L<<10)
4181 #define BCE_COM_COMQ_FTQ_CMD_WR_TOP_1                    (1L<<10)
4182 #define BCE_COM_COMQ_FTQ_CMD_SFT_RESET                   (1L<<25)
4183 #define BCE_COM_COMQ_FTQ_CMD_RD_DATA                     (1L<<26)
4184 #define BCE_COM_COMQ_FTQ_CMD_ADD_INTERVEN                (1L<<27)
4185 #define BCE_COM_COMQ_FTQ_CMD_ADD_DATA                    (1L<<28)
4186 #define BCE_COM_COMQ_FTQ_CMD_INTERVENE_CLR               (1L<<29)
4187 #define BCE_COM_COMQ_FTQ_CMD_POP                         (1L<<30)
4188 #define BCE_COM_COMQ_FTQ_CMD_BUSY                        (1L<<31)
4189
4190 #define BCE_COM_COMQ_FTQ_CTL                            0x001053fc
4191 #define BCE_COM_COMQ_FTQ_CTL_INTERVENE                   (1L<<0)
4192 #define BCE_COM_COMQ_FTQ_CTL_OVERFLOW                    (1L<<1)
4193 #define BCE_COM_COMQ_FTQ_CTL_FORCE_INTERVENE             (1L<<2)
4194 #define BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH                   (0x3ffL<<12)
4195 #define BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH                   (0x3ffL<<22)
4196
4197 #define BCE_COM_SCRATCH                         0x00120000
4198
4199
4200 /*
4201  *  cp_reg definition
4202  *  offset: 0x180000
4203  */
4204 #define BCE_CP_CPU_MODE                         0x00185000
4205 #define BCE_CP_CPU_MODE_LOCAL_RST                        (1L<<0)
4206 #define BCE_CP_CPU_MODE_STEP_ENA                         (1L<<1)
4207 #define BCE_CP_CPU_MODE_PAGE_0_DATA_ENA          (1L<<2)
4208 #define BCE_CP_CPU_MODE_PAGE_0_INST_ENA          (1L<<3)
4209 #define BCE_CP_CPU_MODE_MSG_BIT1                         (1L<<6)
4210 #define BCE_CP_CPU_MODE_INTERRUPT_ENA                    (1L<<7)
4211 #define BCE_CP_CPU_MODE_SOFT_HALT                        (1L<<10)
4212 #define BCE_CP_CPU_MODE_BAD_DATA_HALT_ENA                (1L<<11)
4213 #define BCE_CP_CPU_MODE_BAD_INST_HALT_ENA                (1L<<12)
4214 #define BCE_CP_CPU_MODE_FIO_ABORT_HALT_ENA               (1L<<13)
4215 #define BCE_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA  (1L<<15)
4216
4217 #define BCE_CP_CPU_STATE                                0x00185004
4218 #define BCE_CP_CPU_STATE_BREAKPOINT                      (1L<<0)
4219 #define BCE_CP_CPU_STATE_BAD_INST_HALTED                 (1L<<2)
4220 #define BCE_CP_CPU_STATE_PAGE_0_DATA_HALTED              (1L<<3)
4221 #define BCE_CP_CPU_STATE_PAGE_0_INST_HALTED              (1L<<4)
4222 #define BCE_CP_CPU_STATE_BAD_DATA_ADDR_HALTED            (1L<<5)
4223 #define BCE_CP_CPU_STATE_BAD_pc_HALTED                   (1L<<6)
4224 #define BCE_CP_CPU_STATE_ALIGN_HALTED                    (1L<<7)
4225 #define BCE_CP_CPU_STATE_FIO_ABORT_HALTED                (1L<<8)
4226 #define BCE_CP_CPU_STATE_SOFT_HALTED                     (1L<<10)
4227 #define BCE_CP_CPU_STATE_SPAD_UNDERFLOW          (1L<<11)
4228 #define BCE_CP_CPU_STATE_INTERRRUPT                      (1L<<12)
4229 #define BCE_CP_CPU_STATE_DATA_ACCESS_STALL               (1L<<14)
4230 #define BCE_CP_CPU_STATE_INST_FETCH_STALL                (1L<<15)
4231 #define BCE_CP_CPU_STATE_BLOCKED_READ                    (1L<<31)
4232
4233 #define BCE_CP_CPU_EVENT_MASK                           0x00185008
4234 #define BCE_CP_CPU_EVENT_MASK_BREAKPOINT_MASK            (1L<<0)
4235 #define BCE_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK       (1L<<2)
4236 #define BCE_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK    (1L<<3)
4237 #define BCE_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK    (1L<<4)
4238 #define BCE_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK  (1L<<5)
4239 #define BCE_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK         (1L<<6)
4240 #define BCE_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK  (1L<<7)
4241 #define BCE_CP_CPU_EVENT_MASK_FIO_ABORT_MASK             (1L<<8)
4242 #define BCE_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK           (1L<<10)
4243 #define BCE_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK        (1L<<11)
4244 #define BCE_CP_CPU_EVENT_MASK_INTERRUPT_MASK             (1L<<12)
4245
4246 #define BCE_CP_CPU_PROGRAM_COUNTER                      0x0018501c
4247 #define BCE_CP_CPU_INSTRUCTION                          0x00185020
4248 #define BCE_CP_CPU_DATA_ACCESS                          0x00185024
4249 #define BCE_CP_CPU_INTERRUPT_ENABLE                     0x00185028
4250 #define BCE_CP_CPU_INTERRUPT_VECTOR                     0x0018502c
4251 #define BCE_CP_CPU_INTERRUPT_SAVED_PC                   0x00185030
4252 #define BCE_CP_CPU_HW_BREAKPOINT                        0x00185034
4253 #define BCE_CP_CPU_HW_BREAKPOINT_DISABLE                 (1L<<0)
4254 #define BCE_CP_CPU_HW_BREAKPOINT_ADDRESS                 (0x3fffffffL<<2)
4255
4256 #define BCE_CP_CPU_DEBUG_VECT_PEEK                      0x00185038
4257 #define BCE_CP_CPU_DEBUG_VECT_PEEK_1_VALUE               (0x7ffL<<0)
4258 #define BCE_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN             (1L<<11)
4259 #define BCE_CP_CPU_DEBUG_VECT_PEEK_1_SEL                 (0xfL<<12)
4260 #define BCE_CP_CPU_DEBUG_VECT_PEEK_2_VALUE               (0x7ffL<<16)
4261 #define BCE_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN             (1L<<27)
4262 #define BCE_CP_CPU_DEBUG_VECT_PEEK_2_SEL                 (0xfL<<28)
4263
4264 #define BCE_CP_CPU_LAST_BRANCH_ADDR                     0x00185048
4265 #define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE                 (1L<<1)
4266 #define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP            (0L<<1)
4267 #define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH  (1L<<1)
4268 #define BCE_CP_CPU_LAST_BRANCH_ADDR_LBA          (0x3fffffffL<<2)
4269
4270 #define BCE_CP_CPU_REG_FILE                             0x00185200
4271 #define BCE_CP_CPQ_FTQ_DATA                             0x001853c0
4272 #define BCE_CP_CPQ_FTQ_CMD                              0x001853f8
4273 #define BCE_CP_CPQ_FTQ_CMD_OFFSET                        (0x3ffL<<0)
4274 #define BCE_CP_CPQ_FTQ_CMD_WR_TOP                        (1L<<10)
4275 #define BCE_CP_CPQ_FTQ_CMD_WR_TOP_0                      (0L<<10)
4276 #define BCE_CP_CPQ_FTQ_CMD_WR_TOP_1                      (1L<<10)
4277 #define BCE_CP_CPQ_FTQ_CMD_SFT_RESET                     (1L<<25)
4278 #define BCE_CP_CPQ_FTQ_CMD_RD_DATA                       (1L<<26)
4279 #define BCE_CP_CPQ_FTQ_CMD_ADD_INTERVEN          (1L<<27)
4280 #define BCE_CP_CPQ_FTQ_CMD_ADD_DATA                      (1L<<28)
4281 #define BCE_CP_CPQ_FTQ_CMD_INTERVENE_CLR                 (1L<<29)
4282 #define BCE_CP_CPQ_FTQ_CMD_POP                           (1L<<30)
4283 #define BCE_CP_CPQ_FTQ_CMD_BUSY                  (1L<<31)
4284
4285 #define BCE_CP_CPQ_FTQ_CTL                              0x001853fc
4286 #define BCE_CP_CPQ_FTQ_CTL_INTERVENE                     (1L<<0)
4287 #define BCE_CP_CPQ_FTQ_CTL_OVERFLOW                      (1L<<1)
4288 #define BCE_CP_CPQ_FTQ_CTL_FORCE_INTERVENE               (1L<<2)
4289 #define BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH                     (0x3ffL<<12)
4290 #define BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH                     (0x3ffL<<22)
4291
4292 #define BCE_CP_SCRATCH                                  0x001a0000
4293
4294
4295 /*
4296  *  mcp_reg definition
4297  *  offset: 0x140000
4298  */
4299 #define BCE_MCP_CPU_MODE                                0x00145000
4300 #define BCE_MCP_CPU_MODE_LOCAL_RST                       (1L<<0)
4301 #define BCE_MCP_CPU_MODE_STEP_ENA                        (1L<<1)
4302 #define BCE_MCP_CPU_MODE_PAGE_0_DATA_ENA                 (1L<<2)
4303 #define BCE_MCP_CPU_MODE_PAGE_0_INST_ENA                 (1L<<3)
4304 #define BCE_MCP_CPU_MODE_MSG_BIT1                        (1L<<6)
4305 #define BCE_MCP_CPU_MODE_INTERRUPT_ENA                   (1L<<7)
4306 #define BCE_MCP_CPU_MODE_SOFT_HALT                       (1L<<10)
4307 #define BCE_MCP_CPU_MODE_BAD_DATA_HALT_ENA               (1L<<11)
4308 #define BCE_MCP_CPU_MODE_BAD_INST_HALT_ENA               (1L<<12)
4309 #define BCE_MCP_CPU_MODE_FIO_ABORT_HALT_ENA              (1L<<13)
4310 #define BCE_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA         (1L<<15)
4311
4312 #define BCE_MCP_CPU_STATE                               0x00145004
4313 #define BCE_MCP_CPU_STATE_BREAKPOINT                     (1L<<0)
4314 #define BCE_MCP_CPU_STATE_BAD_INST_HALTED                (1L<<2)
4315 #define BCE_MCP_CPU_STATE_PAGE_0_DATA_HALTED             (1L<<3)
4316 #define BCE_MCP_CPU_STATE_PAGE_0_INST_HALTED             (1L<<4)
4317 #define BCE_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED           (1L<<5)
4318 #define BCE_MCP_CPU_STATE_BAD_pc_HALTED          (1L<<6)
4319 #define BCE_MCP_CPU_STATE_ALIGN_HALTED                   (1L<<7)
4320 #define BCE_MCP_CPU_STATE_FIO_ABORT_HALTED               (1L<<8)
4321 #define BCE_MCP_CPU_STATE_SOFT_HALTED                    (1L<<10)
4322 #define BCE_MCP_CPU_STATE_SPAD_UNDERFLOW                 (1L<<11)
4323 #define BCE_MCP_CPU_STATE_INTERRRUPT                     (1L<<12)
4324 #define BCE_MCP_CPU_STATE_DATA_ACCESS_STALL              (1L<<14)
4325 #define BCE_MCP_CPU_STATE_INST_FETCH_STALL               (1L<<15)
4326 #define BCE_MCP_CPU_STATE_BLOCKED_READ                   (1L<<31)
4327
4328 #define BCE_MCP_CPU_EVENT_MASK                          0x00145008
4329 #define BCE_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK           (1L<<0)
4330 #define BCE_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK      (1L<<2)
4331 #define BCE_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK   (1L<<3)
4332 #define BCE_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK   (1L<<4)
4333 #define BCE_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK         (1L<<5)
4334 #define BCE_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK        (1L<<6)
4335 #define BCE_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK         (1L<<7)
4336 #define BCE_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK            (1L<<8)
4337 #define BCE_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK  (1L<<10)
4338 #define BCE_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK       (1L<<11)
4339 #define BCE_MCP_CPU_EVENT_MASK_INTERRUPT_MASK            (1L<<12)
4340
4341 #define BCE_MCP_CPU_PROGRAM_COUNTER                     0x0014501c
4342 #define BCE_MCP_CPU_INSTRUCTION                 0x00145020
4343 #define BCE_MCP_CPU_DATA_ACCESS                 0x00145024
4344 #define BCE_MCP_CPU_INTERRUPT_ENABLE                    0x00145028
4345 #define BCE_MCP_CPU_INTERRUPT_VECTOR                    0x0014502c
4346 #define BCE_MCP_CPU_INTERRUPT_SAVED_PC                  0x00145030
4347 #define BCE_MCP_CPU_HW_BREAKPOINT                       0x00145034
4348 #define BCE_MCP_CPU_HW_BREAKPOINT_DISABLE                (1L<<0)
4349 #define BCE_MCP_CPU_HW_BREAKPOINT_ADDRESS                (0x3fffffffL<<2)
4350
4351 #define BCE_MCP_CPU_DEBUG_VECT_PEEK                     0x00145038
4352 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE              (0x7ffL<<0)
4353 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN            (1L<<11)
4354 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_SEL                (0xfL<<12)
4355 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE              (0x7ffL<<16)
4356 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN            (1L<<27)
4357 #define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_SEL                (0xfL<<28)
4358
4359 #define BCE_MCP_CPU_LAST_BRANCH_ADDR                    0x00145048
4360 #define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE                (1L<<1)
4361 #define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP           (0L<<1)
4362 #define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH         (1L<<1)
4363 #define BCE_MCP_CPU_LAST_BRANCH_ADDR_LBA                 (0x3fffffffL<<2)
4364
4365 #define BCE_MCP_CPU_REG_FILE                            0x00145200
4366 #define BCE_MCP_MCPQ_FTQ_DATA                           0x001453c0
4367 #define BCE_MCP_MCPQ_FTQ_CMD                            0x001453f8
4368 #define BCE_MCP_MCPQ_FTQ_CMD_OFFSET                      (0x3ffL<<0)
4369 #define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP                      (1L<<10)
4370 #define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_0                    (0L<<10)
4371 #define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_1                    (1L<<10)
4372 #define BCE_MCP_MCPQ_FTQ_CMD_SFT_RESET                   (1L<<25)
4373 #define BCE_MCP_MCPQ_FTQ_CMD_RD_DATA                     (1L<<26)
4374 #define BCE_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN                (1L<<27)
4375 #define BCE_MCP_MCPQ_FTQ_CMD_ADD_DATA                    (1L<<28)
4376 #define BCE_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR               (1L<<29)
4377 #define BCE_MCP_MCPQ_FTQ_CMD_POP                         (1L<<30)
4378 #define BCE_MCP_MCPQ_FTQ_CMD_BUSY                        (1L<<31)
4379
4380 #define BCE_MCP_MCPQ_FTQ_CTL                            0x001453fc
4381 #define BCE_MCP_MCPQ_FTQ_CTL_INTERVENE                   (1L<<0)
4382 #define BCE_MCP_MCPQ_FTQ_CTL_OVERFLOW                    (1L<<1)
4383 #define BCE_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE             (1L<<2)
4384 #define BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH                   (0x3ffL<<12)
4385 #define BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH                   (0x3ffL<<22)
4386
4387 #define BCE_MCP_ROM                                                             0x00150000
4388 #define BCE_MCP_SCRATCH                                                 0x00160000
4389
4390 #define BCE_SHM_HDR_SIGNATURE                                   BCE_MCP_SCRATCH
4391 #define BCE_SHM_HDR_SIGNATURE_SIG_MASK                  0xffff0000
4392 #define BCE_SHM_HDR_SIGNATURE_SIG                               0x53530000
4393 #define BCE_SHM_HDR_SIGNATURE_VER_MASK                  0x000000ff
4394 #define BCE_SHM_HDR_SIGNATURE_VER_ONE                   0x00000001
4395
4396 #define BCE_SHM_HDR_ADDR_0                              BCE_MCP_SCRATCH + 4
4397 #define BCE_SHM_HDR_ADDR_1                              BCE_MCP_SCRATCH + 8
4398
4399 /****************************************************************************/
4400 /* End machine generated definitions.                                     */
4401 /****************************************************************************/
4402
4403 #define NUM_MC_HASH_REGISTERS   8
4404
4405
4406 /* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0.  */
4407 #define PHY_BCM5706_PHY_ID                          0x00206160
4408
4409 #define PHY_ID(id)                                  ((id) & 0xfffffff0)
4410 #define PHY_REV_ID(id)                              ((id) & 0xf)
4411
4412 /* 5708 Serdes PHY registers */
4413
4414 #define BCM5708S_UP1                            0xb
4415
4416 #define BCM5708S_UP1_2G5                        0x1
4417
4418 #define BCM5708S_BLK_ADDR                       0x1f
4419
4420 #define BCM5708S_BLK_ADDR_DIG                   0x0000
4421 #define BCM5708S_BLK_ADDR_DIG3                  0x0002
4422 #define BCM5708S_BLK_ADDR_TX_MISC               0x0005
4423
4424 /* Digital Block */
4425 #define BCM5708S_1000X_CTL1                     0x10
4426
4427 #define BCM5708S_1000X_CTL1_FIBER_MODE          0x0001
4428 #define BCM5708S_1000X_CTL1_AUTODET_EN          0x0010
4429
4430 #define BCM5708S_1000X_CTL2                     0x11
4431
4432 #define BCM5708S_1000X_CTL2_PLLEL_DET_EN        0x0001
4433
4434 #define BCM5708S_1000X_STAT1                    0x14
4435
4436 #define BCM5708S_1000X_STAT1_SGMII              0x0001
4437 #define BCM5708S_1000X_STAT1_LINK               0x0002
4438 #define BCM5708S_1000X_STAT1_FD                 0x0004
4439 #define BCM5708S_1000X_STAT1_SPEED_MASK         0x0018
4440 #define BCM5708S_1000X_STAT1_SPEED_10           0x0000
4441 #define BCM5708S_1000X_STAT1_SPEED_100          0x0008
4442 #define BCM5708S_1000X_STAT1_SPEED_1G           0x0010
4443 #define BCM5708S_1000X_STAT1_SPEED_2G5          0x0018
4444 #define BCM5708S_1000X_STAT1_TX_PAUSE           0x0020
4445 #define BCM5708S_1000X_STAT1_RX_PAUSE           0x0040
4446
4447 /* Digital3 Block */
4448 #define BCM5708S_DIG_3_0                        0x10
4449
4450 #define BCM5708S_DIG_3_0_USE_IEEE               0x0001
4451
4452 /* Tx/Misc Block */
4453 #define BCM5708S_TX_ACTL1                       0x15
4454
4455 #define BCM5708S_TX_ACTL1_DRIVER_VCM            0x30
4456
4457 #define BCM5708S_TX_ACTL3                       0x17
4458
4459 #define RX_COPY_THRESH                  92
4460
4461 #define DMA_READ_CHANS  5
4462 #define DMA_WRITE_CHANS 3
4463
4464 /* Use the natural page size of the host CPU. */
4465 /* XXX: This has only been tested on amd64/i386 systems using 4KB pages. */
4466 #define BCM_PAGE_BITS   PAGE_SHIFT
4467 #define BCM_PAGE_SIZE   PAGE_SIZE
4468
4469 #define TX_PAGES        2
4470 #define TOTAL_TX_BD_PER_PAGE  (BCM_PAGE_SIZE / sizeof(struct tx_bd))
4471 #define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1)
4472 #define TOTAL_TX_BD (TOTAL_TX_BD_PER_PAGE * TX_PAGES)
4473 #define USABLE_TX_BD (USABLE_TX_BD_PER_PAGE * TX_PAGES)
4474 #define MAX_TX_BD (TOTAL_TX_BD - 1)
4475 #define BCE_TX_SLACK_SPACE 16
4476
4477 #define RX_PAGES        2
4478 #define TOTAL_RX_BD_PER_PAGE  (BCM_PAGE_SIZE / sizeof(struct rx_bd))
4479 #define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 1)
4480 #define TOTAL_RX_BD (TOTAL_RX_BD_PER_PAGE * RX_PAGES)
4481 #define USABLE_RX_BD (USABLE_RX_BD_PER_PAGE * RX_PAGES)
4482 #define MAX_RX_BD (TOTAL_RX_BD - 1)
4483 #define BCE_RX_SLACK_SPACE (MAX_RX_BD - 8)
4484
4485 #define NEXT_TX_BD(x) (((x) & USABLE_TX_BD_PER_PAGE) == \
4486                 (USABLE_TX_BD_PER_PAGE - 1)) ?                                          \
4487                 (x) + 2 : (x) + 1
4488
4489 #define TX_CHAIN_IDX(x) ((x) & MAX_TX_BD)
4490
4491 #define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> 8)
4492 #define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE)
4493
4494 #define NEXT_RX_BD(x) (((x) & USABLE_RX_BD_PER_PAGE) == \
4495                 (USABLE_RX_BD_PER_PAGE - 1)) ?                                  \
4496                 (x) + 2 : (x) + 1
4497
4498 #define RX_CHAIN_IDX(x) ((x) & MAX_RX_BD)
4499
4500 #define RX_PAGE(x) (((x) & ~USABLE_RX_BD_PER_PAGE) >> 8)
4501 #define RX_IDX(x) ((x) & USABLE_RX_BD_PER_PAGE)
4502
4503 /* Context size. */
4504 #define CTX_SHIFT                   7
4505 #define CTX_SIZE                    (1 << CTX_SHIFT)
4506 #define CTX_MASK                    (CTX_SIZE - 1)
4507 #define GET_CID_ADDR(_cid)          ((_cid) << CTX_SHIFT)
4508 #define GET_CID(_cid_addr)          ((_cid_addr) >> CTX_SHIFT)
4509
4510 #define PHY_CTX_SHIFT               6
4511 #define PHY_CTX_SIZE                (1 << PHY_CTX_SHIFT)
4512 #define PHY_CTX_MASK                (PHY_CTX_SIZE - 1)
4513 #define GET_PCID_ADDR(_pcid)        ((_pcid) << PHY_CTX_SHIFT)
4514 #define GET_PCID(_pcid_addr)        ((_pcid_addr) >> PHY_CTX_SHIFT)
4515
4516 #define MB_KERNEL_CTX_SHIFT         8
4517 #define MB_KERNEL_CTX_SIZE          (1 << MB_KERNEL_CTX_SHIFT)
4518 #define MB_KERNEL_CTX_MASK          (MB_KERNEL_CTX_SIZE - 1)
4519 #define MB_GET_CID_ADDR(_cid)       (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT))
4520
4521 #define MAX_CID_CNT                 0x4000
4522 #define MAX_CID_ADDR                (GET_CID_ADDR(MAX_CID_CNT))
4523 #define INVALID_CID_ADDR            0xffffffff
4524
4525 #define TX_CID          16
4526 #define RX_CID          0
4527
4528 #define MB_TX_CID_ADDR  MB_GET_CID_ADDR(TX_CID)
4529 #define MB_RX_CID_ADDR  MB_GET_CID_ADDR(RX_CID)
4530
4531 /****************************************************************************/
4532 /* BCE Processor Firmwware Load Definitions                                 */
4533 /****************************************************************************/
4534
4535 struct cpu_reg {
4536         u32 mode;
4537         u32 mode_value_halt;
4538         u32 mode_value_sstep;
4539
4540         u32 state;
4541         u32 state_value_clear;
4542
4543         u32 gpr0;
4544         u32 evmask;
4545         u32 pc;
4546         u32 inst;
4547         u32 bp;
4548
4549         u32 spad_base;
4550
4551         u32 mips_view_base;
4552 };
4553
4554 struct fw_info {
4555         u32 ver_major;
4556         u32 ver_minor;
4557         u32 ver_fix;
4558
4559         u32 start_addr;
4560
4561         /* Text section. */
4562         u32 text_addr;
4563         u32 text_len;
4564         u32 text_index;
4565         u32 *text;
4566
4567         /* Data section. */
4568         u32 data_addr;
4569         u32 data_len;
4570         u32 data_index;
4571         u32 *data;
4572
4573         /* SBSS section. */
4574         u32 sbss_addr;
4575         u32 sbss_len;
4576         u32 sbss_index;
4577         u32 *sbss;
4578
4579         /* BSS section. */
4580         u32 bss_addr;
4581         u32 bss_len;
4582         u32 bss_index;
4583         u32 *bss;
4584
4585         /* Read-only section. */
4586         u32 rodata_addr;
4587         u32 rodata_len;
4588         u32 rodata_index;
4589         u32 *rodata;
4590 };
4591
4592 #define RV2P_PROC1                              0
4593 #define RV2P_PROC2                              1
4594
4595 #define BCE_MIREG(x)    ((x & 0x1F) << 16)
4596 #define BCE_MIPHY(x)    ((x & 0x1F) << 21)
4597 #define BCE_PHY_TIMEOUT 50
4598
4599 #define BCE_NVRAM_SIZE                                  0x200
4600 #define BCE_NVRAM_MAGIC                                 0x669955aa
4601 #define BCE_CRC32_RESIDUAL                              0xdebb20e3
4602
4603 #define BCE_TX_TIMEOUT                                  5
4604
4605 #define BCE_MAX_SEGMENTS                                8
4606 #define BCE_DMA_ALIGN                                   8
4607 #define BCE_DMA_BOUNDARY                                0
4608
4609 /* The BCM5708 has a problem with addresses greater that 40bits. */
4610 /* Handle the sizing issue in an architecture agnostic fashion.  */
4611 #if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF)
4612 #define BCE_BUS_SPACE_MAXADDR           BUS_SPACE_MAXADDR
4613 #else
4614 #define BCE_BUS_SPACE_MAXADDR           0xFFFFFFFFFF
4615 #endif
4616
4617 #define BCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP)
4618
4619 #if __FreeBSD_version < 700000
4620 #define BCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
4621                                                         IFCAP_HWCSUM | IFCAP_JUMBO_MTU)
4622 #else
4623 #define BCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
4624                                                         IFCAP_HWCSUM | IFCAP_JUMBO_MTU | IFCAP_VLAN_HWCSUM)
4625 #endif
4626
4627 #define BCE_MIN_MTU                                             60
4628 #define BCE_MIN_ETHER_MTU                               64
4629
4630 #define BCE_MAX_STD_MTU                                 1500
4631 #define BCE_MAX_STD_ETHER_MTU                   1518
4632 #define BCE_MAX_STD_ETHER_MTU_VLAN              1522
4633
4634 #define BCE_MAX_JUMBO_MTU                               9000
4635 #define BCE_MAX_JUMBO_ETHER_MTU                 9018
4636 #define BCE_MAX_JUMBO_ETHER_MTU_VLAN    9022
4637
4638 // #define BCE_MAX_MTU          ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN      /* 9022 */
4639
4640 /****************************************************************************/
4641 /* BCE Device State Data Structure                                          */
4642 /****************************************************************************/
4643
4644 #define BCE_STATUS_BLK_SZ               sizeof(struct status_block)
4645 #define BCE_STATS_BLK_SZ                sizeof(struct statistics_block)
4646 #define BCE_TX_CHAIN_PAGE_SZ    BCM_PAGE_SIZE
4647 #define BCE_RX_CHAIN_PAGE_SZ    BCM_PAGE_SIZE
4648 /*
4649  * Mbuf pointers. We need these to keep track of the virtual addresses
4650  * of our mbuf chains since we can only convert from physical to virtual,
4651  * not the other way around.
4652  */
4653
4654 struct bce_dmamap_arg {
4655         struct bce_softc        *sc;                            /* Pointer back to device context */
4656         bus_addr_t                      busaddr;                /* Physical address of mapped memory */
4657         u32                                     tx_flags;               /* Flags for frame transmit */
4658         u16                                     prod;
4659         u16                                     chain_prod;
4660         int                                     maxsegs;                /* Max segments supported for this mapped memory */
4661         u32                                     prod_bseq;
4662         struct tx_bd            *tx_chain[TX_PAGES];
4663 };
4664
4665
4666 struct bce_softc
4667 {
4668         /* MUST start with ifnet pointer (see definition of miibus_statchg()) */
4669         struct ifnet            *bce_ifp;                       /* Interface info */
4670         device_t                        bce_dev;                        /* Parent device handle */
4671         u_int8_t                        bce_unit;                       /* Interface number */
4672         struct resource         *bce_res;                       /* Device resource handle */
4673         struct ifmedia          bce_ifmedia;            /* TBI media info */
4674         bus_space_tag_t         bce_btag;                       /* Device bus tag */
4675         bus_space_handle_t      bce_bhandle;            /* Device bus handle */
4676         vm_offset_t                     bce_vhandle;            /* Device virtual memory handle */
4677         struct resource         *bce_irq;                       /* IRQ Resource Handle */
4678         struct mtx                      bce_mtx;                        /* Mutex */
4679         void                            *bce_intrhand;          /* Interrupt handler */
4680
4681         /* ASIC Chip ID. */
4682         u32                                     bce_chipid;
4683
4684         /* General controller flags. */
4685         u32                                     bce_flags;
4686 #define BCE_PCIX_FLAG                   0x01
4687 #define BCE_PCI_32BIT_FLAG              0x02
4688 #define BCE_ONE_TDMA_FLAG               0x04            /* Deprecated */
4689 #define BCE_NO_WOL_FLAG                 0x08
4690 #define BCE_USING_DAC_FLAG              0x10
4691 #define BCE_USING_MSI_FLAG              0x20
4692 #define BCE_MFW_ENABLE_FLAG             0x40
4693
4694         /* PHY specific flags. */
4695         u32                                     bce_phy_flags;
4696 #define BCE_PHY_SERDES_FLAG                                     1
4697 #define BCE_PHY_CRC_FIX_FLAG                            2
4698 #define BCE_PHY_PARALLEL_DETECT_FLAG            4
4699 #define BCE_PHY_2_5G_CAPABLE_FLAG                       8
4700 #define BCE_PHY_INT_MODE_MASK_FLAG                      0x300
4701 #define BCE_PHY_INT_MODE_AUTO_POLLING_FLAG      0x100
4702 #define BCE_PHY_INT_MODE_LINK_READY_FLAG        0x200
4703
4704         bus_addr_t                              max_bus_addr;
4705         u16                                     bus_speed_mhz;          /* PCI bus speed */
4706         struct flash_spec       *bce_flash_info;        /* Flash NVRAM settings */
4707         u32                                     bce_flash_size;         /* Flash NVRAM size */
4708         u32                                     bce_shmem_base;         /* Shared Memory base address */
4709         char *                          bce_name;                       /* Name string */
4710
4711         /* Tracks the version of bootcode firmware. */
4712         u32                                     bce_fw_ver;
4713
4714         /* Tracks the state of the firmware.  0 = Running while any     */
4715         /* other value indicates that the firmware is not responding.   */
4716         u16                                     bce_fw_timed_out;
4717
4718         /* An incrementing sequence used to coordinate messages passed   */
4719         /* from the driver to the firmware.                              */
4720         u16                                     bce_fw_wr_seq;
4721
4722         /* An incrementing sequence used to let the firmware know that   */
4723         /* the driver is still operating.  Without the pulse, management */
4724         /* firmware such as IPMI or UMP will operate in OS absent state. */
4725         u16                                     bce_fw_drv_pulse_wr_seq;
4726
4727         /* Ethernet MAC address. */
4728         u_char                          eaddr[6];
4729
4730         /* These setting are used by the host coalescing (HC) block to   */
4731         /* to control how often the status block, statistics block and   */
4732         /* interrupts are generated.                                     */
4733         u16                                     bce_tx_quick_cons_trip_int;
4734         u16                                     bce_tx_quick_cons_trip;
4735         u16                                     bce_rx_quick_cons_trip_int;
4736         u16                                     bce_rx_quick_cons_trip;
4737         u16                                     bce_comp_prod_trip_int;
4738         u16                                     bce_comp_prod_trip;
4739         u16                                     bce_tx_ticks_int;
4740         u16                                     bce_tx_ticks;
4741         u16                                     bce_rx_ticks_int;
4742         u16                                     bce_rx_ticks;
4743         u16                                     bce_com_ticks_int;
4744         u16                                     bce_com_ticks;
4745         u16                                     bce_cmd_ticks_int;
4746         u16                                     bce_cmd_ticks;
4747         u32                                     bce_stats_ticks;
4748
4749         /* The address of the integrated PHY on the MII bus. */
4750         int                                     bce_phy_addr;
4751
4752         /* The device handle for the MII bus child device. */
4753         device_t                        bce_miibus;
4754
4755         /* Driver maintained TX chain pointers and byte counter. */
4756         u16                                     rx_prod;
4757         u16                                     rx_cons;
4758         u32                                     rx_prod_bseq;   /* Counts the bytes used.  */
4759         u16                                     tx_prod;
4760         u16                                     tx_cons;
4761         u32                                     tx_prod_bseq;   /* Counts the bytes used.  */
4762
4763         int                                     bce_link;
4764         struct callout          bce_stat_ch;
4765
4766         /* Frame size and mbuf allocation size for RX frames. */
4767         u32                                     max_frame_size;
4768         int                                     mbuf_alloc_size;
4769
4770         /* Receive mode settings (i.e promiscuous, multicast, etc.). */
4771         u32                                     rx_mode;
4772
4773 #ifdef DEVICE_POLLING
4774         int                                     bce_rxcycles;                           /* Counter for receive polling cycles */
4775 #endif
4776
4777         /* Bus tag for the bce controller. */
4778         bus_dma_tag_t           parent_tag;
4779
4780         /* H/W maintained TX buffer descriptor chain structure. */
4781         bus_dma_tag_t           tx_bd_chain_tag;
4782         bus_dmamap_t            tx_bd_chain_map[TX_PAGES];
4783         struct tx_bd            *tx_bd_chain[TX_PAGES];
4784         bus_addr_t                      tx_bd_chain_paddr[TX_PAGES];
4785
4786         /* H/W maintained RX buffer descriptor chain structure. */
4787         bus_dma_tag_t           rx_bd_chain_tag;
4788         bus_dmamap_t            rx_bd_chain_map[RX_PAGES];
4789         struct rx_bd            *rx_bd_chain[RX_PAGES];
4790         bus_addr_t                      rx_bd_chain_paddr[RX_PAGES];
4791
4792         /* H/W maintained status block. */
4793         bus_dma_tag_t           status_tag;
4794         bus_dmamap_t            status_map;
4795         struct status_block     *status_block;                          /* virtual address */
4796         bus_addr_t                      status_block_paddr;                     /* Physical address */
4797
4798         /* Driver maintained status block values. */
4799         u16                                     last_status_idx;
4800         u16                                     hw_rx_cons;
4801         u16                                     hw_tx_cons;
4802
4803         /* H/W maintained statistics block. */
4804         bus_dma_tag_t           stats_tag;
4805         bus_dmamap_t            stats_map;
4806         struct statistics_block *stats_block;           /* Virtual address */
4807         bus_addr_t                      stats_block_paddr;              /* Physical address */
4808
4809         /* Bus tag for RX/TX mbufs. */
4810         bus_dma_tag_t           rx_mbuf_tag;
4811         bus_dma_tag_t           tx_mbuf_tag;
4812
4813         /* S/W maintained mbuf TX chain structure. */
4814         bus_dmamap_t            tx_mbuf_map[TOTAL_TX_BD];
4815         struct mbuf                     *tx_mbuf_ptr[TOTAL_TX_BD];
4816
4817         /* S/W maintained mbuf RX chain structure. */
4818         bus_dmamap_t            rx_mbuf_map[TOTAL_RX_BD];
4819         struct mbuf                     *rx_mbuf_ptr[TOTAL_RX_BD];
4820
4821         /* Track the number of rx_bd and tx_bd's in use. */
4822         u16 free_rx_bd;
4823         u16 used_tx_bd;
4824
4825         /* Provides access to hardware statistics through sysctl. */
4826         u64 stat_IfHCInOctets;
4827         u64 stat_IfHCInBadOctets;
4828         u64 stat_IfHCOutOctets;
4829         u64 stat_IfHCOutBadOctets;
4830         u64 stat_IfHCInUcastPkts;
4831         u64 stat_IfHCInMulticastPkts;
4832         u64 stat_IfHCInBroadcastPkts;
4833         u64 stat_IfHCOutUcastPkts;
4834         u64 stat_IfHCOutMulticastPkts;
4835         u64 stat_IfHCOutBroadcastPkts;
4836
4837         u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
4838         u32 stat_Dot3StatsCarrierSenseErrors;
4839         u32 stat_Dot3StatsFCSErrors;
4840         u32 stat_Dot3StatsAlignmentErrors;
4841         u32 stat_Dot3StatsSingleCollisionFrames;
4842         u32 stat_Dot3StatsMultipleCollisionFrames;
4843         u32 stat_Dot3StatsDeferredTransmissions;
4844         u32 stat_Dot3StatsExcessiveCollisions;
4845         u32 stat_Dot3StatsLateCollisions;
4846         u32 stat_EtherStatsCollisions;
4847         u32 stat_EtherStatsFragments;
4848         u32 stat_EtherStatsJabbers;
4849         u32 stat_EtherStatsUndersizePkts;
4850         u32 stat_EtherStatsOverrsizePkts;
4851         u32 stat_EtherStatsPktsRx64Octets;
4852         u32 stat_EtherStatsPktsRx65Octetsto127Octets;
4853         u32 stat_EtherStatsPktsRx128Octetsto255Octets;
4854         u32 stat_EtherStatsPktsRx256Octetsto511Octets;
4855         u32 stat_EtherStatsPktsRx512Octetsto1023Octets;
4856         u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;
4857         u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;
4858         u32 stat_EtherStatsPktsTx64Octets;
4859         u32 stat_EtherStatsPktsTx65Octetsto127Octets;
4860         u32 stat_EtherStatsPktsTx128Octetsto255Octets;
4861         u32 stat_EtherStatsPktsTx256Octetsto511Octets;
4862         u32 stat_EtherStatsPktsTx512Octetsto1023Octets;
4863         u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;
4864         u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;
4865         u32 stat_XonPauseFramesReceived;
4866         u32 stat_XoffPauseFramesReceived;
4867         u32 stat_OutXonSent;
4868         u32 stat_OutXoffSent;
4869         u32 stat_FlowControlDone;
4870         u32 stat_MacControlFramesReceived;
4871         u32 stat_XoffStateEntered;
4872         u32 stat_IfInFramesL2FilterDiscards;
4873         u32 stat_IfInRuleCheckerDiscards;
4874         u32 stat_IfInFTQDiscards;
4875         u32 stat_IfInMBUFDiscards;
4876         u32 stat_IfInRuleCheckerP4Hit;
4877         u32 stat_CatchupInRuleCheckerDiscards;
4878         u32 stat_CatchupInFTQDiscards;
4879         u32 stat_CatchupInMBUFDiscards;
4880         u32 stat_CatchupInRuleCheckerP4Hit;
4881
4882 #ifdef BCE_DEBUG
4883         /* Track the number of enqueued mbufs. */
4884         int     tx_mbuf_alloc;
4885         int rx_mbuf_alloc;
4886
4887         /* Track how many and what type of interrupts are generated. */
4888         u32 interrupts_generated;
4889         u32 interrupts_handled;
4890         u32 rx_interrupts;
4891         u32 tx_interrupts;
4892
4893         u32     rx_low_watermark;                       /* Lowest number of rx_bd's free. */
4894         u32 tx_hi_watermark;                    /* Greatest number of tx_bd's used. */
4895         u32     mbuf_alloc_failed;                      /* Mbuf allocation failure counter. */
4896         u32 l2fhdr_status_errors;
4897         u32 unexpected_attentions;
4898         u32     lost_status_block_updates;
4899 #endif
4900 };
4901
4902 #endif /* #ifndef _BCE_H_DEFINED */