2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
5 * and Duncan Barclay<dmlb@dmlb.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/endian.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
40 #include <sys/module.h>
42 #include <sys/socket.h>
43 #include <sys/sockio.h>
44 #include <sys/sysctl.h>
48 #include <net/if_var.h>
49 #include <net/ethernet.h>
50 #include <net/if_dl.h>
51 #include <net/if_media.h>
52 #include <net/if_types.h>
53 #include <net/if_vlan_var.h>
55 #include <dev/mii/mii.h>
56 #include <dev/mii/miivar.h>
58 #include <dev/pci/pcireg.h>
59 #include <dev/pci/pcivar.h>
61 #include <machine/bus.h>
63 #include <dev/bfe/if_bfereg.h>
65 MODULE_DEPEND(bfe, pci, 1, 1, 1);
66 MODULE_DEPEND(bfe, ether, 1, 1, 1);
67 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
69 /* "device miibus" required. See GENERIC if you get errors here. */
70 #include "miibus_if.h"
72 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
74 static struct bfe_type bfe_devs[] = {
75 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401,
76 "Broadcom BCM4401 Fast Ethernet" },
77 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0,
78 "Broadcom BCM4401-B0 Fast Ethernet" },
82 static int bfe_probe (device_t);
83 static int bfe_attach (device_t);
84 static int bfe_detach (device_t);
85 static int bfe_suspend (device_t);
86 static int bfe_resume (device_t);
87 static void bfe_release_resources (struct bfe_softc *);
88 static void bfe_intr (void *);
89 static int bfe_encap (struct bfe_softc *, struct mbuf **);
90 static void bfe_start (struct ifnet *);
91 static void bfe_start_locked (struct ifnet *);
92 static int bfe_ioctl (struct ifnet *, u_long, caddr_t);
93 static void bfe_init (void *);
94 static void bfe_init_locked (void *);
95 static void bfe_stop (struct bfe_softc *);
96 static void bfe_watchdog (struct bfe_softc *);
97 static int bfe_shutdown (device_t);
98 static void bfe_tick (void *);
99 static void bfe_txeof (struct bfe_softc *);
100 static void bfe_rxeof (struct bfe_softc *);
101 static void bfe_set_rx_mode (struct bfe_softc *);
102 static int bfe_list_rx_init (struct bfe_softc *);
103 static void bfe_list_tx_init (struct bfe_softc *);
104 static void bfe_discard_buf (struct bfe_softc *, int);
105 static int bfe_list_newbuf (struct bfe_softc *, int);
106 static void bfe_rx_ring_free (struct bfe_softc *);
108 static void bfe_pci_setup (struct bfe_softc *, u_int32_t);
109 static int bfe_ifmedia_upd (struct ifnet *);
110 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *);
111 static int bfe_miibus_readreg (device_t, int, int);
112 static int bfe_miibus_writereg (device_t, int, int, int);
113 static void bfe_miibus_statchg (device_t);
114 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t,
116 static void bfe_get_config (struct bfe_softc *sc);
117 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *);
118 static void bfe_stats_update (struct bfe_softc *);
119 static void bfe_clear_stats (struct bfe_softc *);
120 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*);
121 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t);
122 static int bfe_resetphy (struct bfe_softc *);
123 static int bfe_setupphy (struct bfe_softc *);
124 static void bfe_chip_reset (struct bfe_softc *);
125 static void bfe_chip_halt (struct bfe_softc *);
126 static void bfe_core_reset (struct bfe_softc *);
127 static void bfe_core_disable (struct bfe_softc *);
128 static int bfe_dma_alloc (struct bfe_softc *);
129 static void bfe_dma_free (struct bfe_softc *sc);
130 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int);
131 static void bfe_cam_write (struct bfe_softc *, u_char *, int);
132 static int sysctl_bfe_stats (SYSCTL_HANDLER_ARGS);
134 static device_method_t bfe_methods[] = {
135 /* Device interface */
136 DEVMETHOD(device_probe, bfe_probe),
137 DEVMETHOD(device_attach, bfe_attach),
138 DEVMETHOD(device_detach, bfe_detach),
139 DEVMETHOD(device_shutdown, bfe_shutdown),
140 DEVMETHOD(device_suspend, bfe_suspend),
141 DEVMETHOD(device_resume, bfe_resume),
144 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
145 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
146 DEVMETHOD(miibus_statchg, bfe_miibus_statchg),
151 static driver_t bfe_driver = {
154 sizeof(struct bfe_softc)
157 static devclass_t bfe_devclass;
159 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
160 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, bfe, bfe_devs,
161 nitems(bfe_devs) - 1);
162 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
165 * Probe for a Broadcom 4401 chip.
168 bfe_probe(device_t dev)
174 while (t->bfe_name != NULL) {
175 if (pci_get_vendor(dev) == t->bfe_vid &&
176 pci_get_device(dev) == t->bfe_did) {
177 device_set_desc(dev, t->bfe_name);
178 return (BUS_PROBE_DEFAULT);
186 struct bfe_dmamap_arg {
187 bus_addr_t bfe_busaddr;
191 bfe_dma_alloc(struct bfe_softc *sc)
193 struct bfe_dmamap_arg ctx;
194 struct bfe_rx_data *rd;
195 struct bfe_tx_data *td;
199 * parent tag. Apparently the chip cannot handle any DMA address
202 error = bus_dma_tag_create(bus_get_dma_tag(sc->bfe_dev), /* parent */
203 1, 0, /* alignment, boundary */
204 BFE_DMA_MAXADDR, /* lowaddr */
205 BUS_SPACE_MAXADDR, /* highaddr */
206 NULL, NULL, /* filter, filterarg */
207 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
209 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
211 NULL, NULL, /* lockfunc, lockarg */
212 &sc->bfe_parent_tag);
214 device_printf(sc->bfe_dev, "cannot create parent DMA tag.\n");
218 /* Create tag for Tx ring. */
219 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
220 BFE_TX_RING_ALIGN, 0, /* alignment, boundary */
221 BUS_SPACE_MAXADDR, /* lowaddr */
222 BUS_SPACE_MAXADDR, /* highaddr */
223 NULL, NULL, /* filter, filterarg */
224 BFE_TX_LIST_SIZE, /* maxsize */
226 BFE_TX_LIST_SIZE, /* maxsegsize */
228 NULL, NULL, /* lockfunc, lockarg */
231 device_printf(sc->bfe_dev, "cannot create Tx ring DMA tag.\n");
235 /* Create tag for Rx ring. */
236 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
237 BFE_RX_RING_ALIGN, 0, /* alignment, boundary */
238 BUS_SPACE_MAXADDR, /* lowaddr */
239 BUS_SPACE_MAXADDR, /* highaddr */
240 NULL, NULL, /* filter, filterarg */
241 BFE_RX_LIST_SIZE, /* maxsize */
243 BFE_RX_LIST_SIZE, /* maxsegsize */
245 NULL, NULL, /* lockfunc, lockarg */
248 device_printf(sc->bfe_dev, "cannot create Rx ring DMA tag.\n");
252 /* Create tag for Tx buffers. */
253 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
254 1, 0, /* alignment, boundary */
255 BUS_SPACE_MAXADDR, /* lowaddr */
256 BUS_SPACE_MAXADDR, /* highaddr */
257 NULL, NULL, /* filter, filterarg */
258 MCLBYTES * BFE_MAXTXSEGS, /* maxsize */
259 BFE_MAXTXSEGS, /* nsegments */
260 MCLBYTES, /* maxsegsize */
262 NULL, NULL, /* lockfunc, lockarg */
263 &sc->bfe_txmbuf_tag);
265 device_printf(sc->bfe_dev,
266 "cannot create Tx buffer DMA tag.\n");
270 /* Create tag for Rx buffers. */
271 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
272 1, 0, /* alignment, boundary */
273 BUS_SPACE_MAXADDR, /* lowaddr */
274 BUS_SPACE_MAXADDR, /* highaddr */
275 NULL, NULL, /* filter, filterarg */
276 MCLBYTES, /* maxsize */
278 MCLBYTES, /* maxsegsize */
280 NULL, NULL, /* lockfunc, lockarg */
281 &sc->bfe_rxmbuf_tag);
283 device_printf(sc->bfe_dev,
284 "cannot create Rx buffer DMA tag.\n");
288 /* Allocate DMA'able memory and load DMA map. */
289 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
290 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_tx_map);
292 device_printf(sc->bfe_dev,
293 "cannot allocate DMA'able memory for Tx ring.\n");
297 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
298 sc->bfe_tx_list, BFE_TX_LIST_SIZE, bfe_dma_map, &ctx,
300 if (error != 0 || ctx.bfe_busaddr == 0) {
301 device_printf(sc->bfe_dev,
302 "cannot load DMA'able memory for Tx ring.\n");
305 sc->bfe_tx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
307 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
308 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_rx_map);
310 device_printf(sc->bfe_dev,
311 "cannot allocate DMA'able memory for Rx ring.\n");
315 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
316 sc->bfe_rx_list, BFE_RX_LIST_SIZE, bfe_dma_map, &ctx,
318 if (error != 0 || ctx.bfe_busaddr == 0) {
319 device_printf(sc->bfe_dev,
320 "cannot load DMA'able memory for Rx ring.\n");
323 sc->bfe_rx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
325 /* Create DMA maps for Tx buffers. */
326 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
327 td = &sc->bfe_tx_ring[i];
330 error = bus_dmamap_create(sc->bfe_txmbuf_tag, 0, &td->bfe_map);
332 device_printf(sc->bfe_dev,
333 "cannot create DMA map for Tx.\n");
338 /* Create spare DMA map for Rx buffers. */
339 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &sc->bfe_rx_sparemap);
341 device_printf(sc->bfe_dev, "cannot create spare DMA map for Rx.\n");
344 /* Create DMA maps for Rx buffers. */
345 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
346 rd = &sc->bfe_rx_ring[i];
350 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &rd->bfe_map);
352 device_printf(sc->bfe_dev,
353 "cannot create DMA map for Rx.\n");
363 bfe_dma_free(struct bfe_softc *sc)
365 struct bfe_tx_data *td;
366 struct bfe_rx_data *rd;
370 if (sc->bfe_tx_tag != NULL) {
371 if (sc->bfe_tx_dma != 0)
372 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
373 if (sc->bfe_tx_list != NULL)
374 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
377 sc->bfe_tx_list = NULL;
378 bus_dma_tag_destroy(sc->bfe_tx_tag);
379 sc->bfe_tx_tag = NULL;
383 if (sc->bfe_rx_tag != NULL) {
384 if (sc->bfe_rx_dma != 0)
385 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
386 if (sc->bfe_rx_list != NULL)
387 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
390 sc->bfe_rx_list = NULL;
391 bus_dma_tag_destroy(sc->bfe_rx_tag);
392 sc->bfe_rx_tag = NULL;
396 if (sc->bfe_txmbuf_tag != NULL) {
397 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
398 td = &sc->bfe_tx_ring[i];
399 if (td->bfe_map != NULL) {
400 bus_dmamap_destroy(sc->bfe_txmbuf_tag,
405 bus_dma_tag_destroy(sc->bfe_txmbuf_tag);
406 sc->bfe_txmbuf_tag = NULL;
410 if (sc->bfe_rxmbuf_tag != NULL) {
411 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
412 rd = &sc->bfe_rx_ring[i];
413 if (rd->bfe_map != NULL) {
414 bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
419 if (sc->bfe_rx_sparemap != NULL) {
420 bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
421 sc->bfe_rx_sparemap);
422 sc->bfe_rx_sparemap = NULL;
424 bus_dma_tag_destroy(sc->bfe_rxmbuf_tag);
425 sc->bfe_rxmbuf_tag = NULL;
428 if (sc->bfe_parent_tag != NULL) {
429 bus_dma_tag_destroy(sc->bfe_parent_tag);
430 sc->bfe_parent_tag = NULL;
435 bfe_attach(device_t dev)
437 struct ifnet *ifp = NULL;
438 struct bfe_softc *sc;
441 sc = device_get_softc(dev);
442 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
444 callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0);
449 * Map control/status registers.
451 pci_enable_busmaster(dev);
454 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
456 if (sc->bfe_res == NULL) {
457 device_printf(dev, "couldn't map memory\n");
462 /* Allocate interrupt */
465 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
466 RF_SHAREABLE | RF_ACTIVE);
467 if (sc->bfe_irq == NULL) {
468 device_printf(dev, "couldn't map interrupt\n");
473 if (bfe_dma_alloc(sc) != 0) {
474 device_printf(dev, "failed to allocate DMA resources\n");
479 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
480 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
481 "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_bfe_stats,
484 /* Set up ifnet structure */
485 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER);
487 device_printf(dev, "failed to if_alloc()\n");
492 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
493 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
494 ifp->if_ioctl = bfe_ioctl;
495 ifp->if_start = bfe_start;
496 ifp->if_init = bfe_init;
497 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN);
498 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN;
499 IFQ_SET_READY(&ifp->if_snd);
503 /* Reset the chip and turn on the PHY */
508 error = mii_attach(dev, &sc->bfe_miibus, ifp, bfe_ifmedia_upd,
509 bfe_ifmedia_sts, BMSR_DEFCAPMASK, sc->bfe_phyaddr, MII_OFFSET_ANY,
512 device_printf(dev, "attaching PHYs failed\n");
516 ether_ifattach(ifp, sc->bfe_enaddr);
519 * Tell the upper layer(s) we support long frames.
521 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
522 ifp->if_capabilities |= IFCAP_VLAN_MTU;
523 ifp->if_capenable |= IFCAP_VLAN_MTU;
526 * Hook interrupt last to avoid having to lock softc
528 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE,
529 NULL, bfe_intr, sc, &sc->bfe_intrhand);
532 device_printf(dev, "couldn't set up irq\n");
542 bfe_detach(device_t dev)
544 struct bfe_softc *sc;
547 sc = device_get_softc(dev);
551 if (device_is_attached(dev)) {
553 sc->bfe_flags |= BFE_FLAG_DETACH;
556 callout_drain(&sc->bfe_stat_co);
565 bus_generic_detach(dev);
566 if (sc->bfe_miibus != NULL)
567 device_delete_child(dev, sc->bfe_miibus);
569 bfe_release_resources(sc);
571 mtx_destroy(&sc->bfe_mtx);
577 * Stop all chip I/O so that the kernel's probe routines don't
578 * get confused by errant DMAs when rebooting.
581 bfe_shutdown(device_t dev)
583 struct bfe_softc *sc;
585 sc = device_get_softc(dev);
595 bfe_suspend(device_t dev)
597 struct bfe_softc *sc;
599 sc = device_get_softc(dev);
608 bfe_resume(device_t dev)
610 struct bfe_softc *sc;
613 sc = device_get_softc(dev);
617 if (ifp->if_flags & IFF_UP) {
619 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
620 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
621 bfe_start_locked(ifp);
629 bfe_miibus_readreg(device_t dev, int phy, int reg)
631 struct bfe_softc *sc;
634 sc = device_get_softc(dev);
635 bfe_readphy(sc, reg, &ret);
641 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
643 struct bfe_softc *sc;
645 sc = device_get_softc(dev);
646 bfe_writephy(sc, reg, val);
652 bfe_miibus_statchg(device_t dev)
654 struct bfe_softc *sc;
655 struct mii_data *mii;
658 sc = device_get_softc(dev);
659 mii = device_get_softc(sc->bfe_miibus);
661 sc->bfe_flags &= ~BFE_FLAG_LINK;
662 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
663 (IFM_ACTIVE | IFM_AVALID)) {
664 switch (IFM_SUBTYPE(mii->mii_media_active)) {
667 sc->bfe_flags |= BFE_FLAG_LINK;
674 /* XXX Should stop Rx/Tx engine prior to touching MAC. */
675 val = CSR_READ_4(sc, BFE_TX_CTRL);
676 val &= ~BFE_TX_DUPLEX;
677 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
678 val |= BFE_TX_DUPLEX;
681 flow = CSR_READ_4(sc, BFE_RXCONF);
682 flow &= ~BFE_RXCONF_FLOW;
683 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
684 IFM_ETH_RXPAUSE) != 0)
685 flow |= BFE_RXCONF_FLOW;
686 CSR_WRITE_4(sc, BFE_RXCONF, flow);
688 * It seems that the hardware has Tx pause issues
689 * so enable only Rx pause.
691 flow = CSR_READ_4(sc, BFE_MAC_FLOW);
692 flow &= ~BFE_FLOW_PAUSE_ENAB;
693 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow);
696 CSR_WRITE_4(sc, BFE_TX_CTRL, val);
700 bfe_tx_ring_free(struct bfe_softc *sc)
704 for(i = 0; i < BFE_TX_LIST_CNT; i++) {
705 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
706 bus_dmamap_sync(sc->bfe_txmbuf_tag,
707 sc->bfe_tx_ring[i].bfe_map, BUS_DMASYNC_POSTWRITE);
708 bus_dmamap_unload(sc->bfe_txmbuf_tag,
709 sc->bfe_tx_ring[i].bfe_map);
710 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
711 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
714 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
715 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
716 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
720 bfe_rx_ring_free(struct bfe_softc *sc)
724 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
725 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
726 bus_dmamap_sync(sc->bfe_rxmbuf_tag,
727 sc->bfe_rx_ring[i].bfe_map, BUS_DMASYNC_POSTREAD);
728 bus_dmamap_unload(sc->bfe_rxmbuf_tag,
729 sc->bfe_rx_ring[i].bfe_map);
730 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
731 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
734 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
735 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
736 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
740 bfe_list_rx_init(struct bfe_softc *sc)
742 struct bfe_rx_data *rd;
745 sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
746 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
747 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
748 rd = &sc->bfe_rx_ring[i];
751 if (bfe_list_newbuf(sc, i) != 0)
755 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
756 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
757 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
763 bfe_list_tx_init(struct bfe_softc *sc)
767 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
768 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
769 for (i = 0; i < BFE_TX_LIST_CNT; i++)
770 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
772 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
773 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
777 bfe_discard_buf(struct bfe_softc *sc, int c)
779 struct bfe_rx_data *r;
782 r = &sc->bfe_rx_ring[c];
783 d = &sc->bfe_rx_list[c];
784 d->bfe_ctrl = htole32(r->bfe_ctrl);
788 bfe_list_newbuf(struct bfe_softc *sc, int c)
790 struct bfe_rxheader *rx_header;
792 struct bfe_rx_data *r;
794 bus_dma_segment_t segs[1];
799 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
802 m->m_len = m->m_pkthdr.len = MCLBYTES;
804 if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap,
805 m, segs, &nsegs, 0) != 0) {
810 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
811 r = &sc->bfe_rx_ring[c];
812 if (r->bfe_mbuf != NULL) {
813 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map,
814 BUS_DMASYNC_POSTREAD);
815 bus_dmamap_unload(sc->bfe_rxmbuf_tag, r->bfe_map);
818 r->bfe_map = sc->bfe_rx_sparemap;
819 sc->bfe_rx_sparemap = map;
822 rx_header = mtod(m, struct bfe_rxheader *);
824 rx_header->flags = 0;
825 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, BUS_DMASYNC_PREREAD);
827 ctrl = segs[0].ds_len & BFE_DESC_LEN;
828 KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!",
830 if (c == BFE_RX_LIST_CNT - 1)
831 ctrl |= BFE_DESC_EOT;
834 d = &sc->bfe_rx_list[c];
835 d->bfe_ctrl = htole32(ctrl);
836 /* The chip needs all addresses to be added to BFE_PCI_DMA. */
837 d->bfe_addr = htole32(BFE_ADDR_LO(segs[0].ds_addr) + BFE_PCI_DMA);
843 bfe_get_config(struct bfe_softc *sc)
845 u_int8_t eeprom[128];
847 bfe_read_eeprom(sc, eeprom);
849 sc->bfe_enaddr[0] = eeprom[79];
850 sc->bfe_enaddr[1] = eeprom[78];
851 sc->bfe_enaddr[2] = eeprom[81];
852 sc->bfe_enaddr[3] = eeprom[80];
853 sc->bfe_enaddr[4] = eeprom[83];
854 sc->bfe_enaddr[5] = eeprom[82];
856 sc->bfe_phyaddr = eeprom[90] & 0x1f;
857 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
859 sc->bfe_core_unit = 0;
860 sc->bfe_dma_offset = BFE_PCI_DMA;
864 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores)
866 u_int32_t bar_orig, pci_rev, val;
868 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
869 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
870 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
872 val = CSR_READ_4(sc, BFE_SBINTVEC);
874 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
876 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
877 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
878 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
880 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
884 bfe_clear_stats(struct bfe_softc *sc)
890 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
891 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
893 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
898 bfe_resetphy(struct bfe_softc *sc)
902 bfe_writephy(sc, 0, BMCR_RESET);
904 bfe_readphy(sc, 0, &val);
905 if (val & BMCR_RESET) {
906 device_printf(sc->bfe_dev, "PHY Reset would not complete.\n");
913 bfe_chip_halt(struct bfe_softc *sc)
916 /* disable interrupts - not that it actually does..*/
917 CSR_WRITE_4(sc, BFE_IMASK, 0);
918 CSR_READ_4(sc, BFE_IMASK);
920 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
921 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
923 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
924 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
929 bfe_chip_reset(struct bfe_softc *sc)
935 /* Set the interrupt vector for the enet core */
936 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
939 val = CSR_READ_4(sc, BFE_SBTMSLOW) &
940 (BFE_RESET | BFE_REJECT | BFE_CLOCK);
941 if (val == BFE_CLOCK) {
942 /* It is, so shut it down */
943 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
944 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
945 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
946 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
947 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
948 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE,
950 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
957 * We want the phy registers to be accessible even when
958 * the driver is "downed" so initialize MDC preamble, frequency,
959 * and whether internal or external phy here.
962 /* 4402 has 62.5Mhz SB clock and internal phy */
963 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
965 /* Internal or external PHY? */
966 val = CSR_READ_4(sc, BFE_DEVCTRL);
967 if (!(val & BFE_IPP))
968 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
969 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
970 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
974 /* Enable CRC32 generation and set proper LED modes */
975 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
977 /* Reset or clear powerdown control bit */
978 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
980 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
984 * We don't want lazy interrupts, so just send them at
985 * the end of a frame, please
987 BFE_OR(sc, BFE_RCV_LAZY, 0);
989 /* Set max lengths, accounting for VLAN tags */
990 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
991 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
993 /* Set watermark XXX - magic */
994 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
997 * Initialise DMA channels
998 * - not forgetting dma addresses need to be added to BFE_PCI_DMA
1000 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
1001 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
1003 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
1004 BFE_RX_CTRL_ENABLE);
1005 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
1012 bfe_core_disable(struct bfe_softc *sc)
1014 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
1018 * Set reject, wait for it set, then wait for the core to stop
1019 * being busy, then set reset and reject and enable the clocks.
1021 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
1022 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
1023 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
1024 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
1026 CSR_READ_4(sc, BFE_SBTMSLOW);
1028 /* Leave reset and reject set */
1029 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
1034 bfe_core_reset(struct bfe_softc *sc)
1038 /* Disable the core */
1039 bfe_core_disable(sc);
1041 /* and bring it back up */
1042 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
1043 CSR_READ_4(sc, BFE_SBTMSLOW);
1046 /* Chip bug, clear SERR, IB and TO if they are set. */
1047 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
1048 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
1049 val = CSR_READ_4(sc, BFE_SBIMSTATE);
1050 if (val & (BFE_IBE | BFE_TO))
1051 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
1053 /* Clear reset and allow it to move through the core */
1054 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
1055 CSR_READ_4(sc, BFE_SBTMSLOW);
1058 /* Leave the clock set */
1059 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
1060 CSR_READ_4(sc, BFE_SBTMSLOW);
1065 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
1069 val = ((u_int32_t) data[2]) << 24;
1070 val |= ((u_int32_t) data[3]) << 16;
1071 val |= ((u_int32_t) data[4]) << 8;
1072 val |= ((u_int32_t) data[5]);
1073 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
1074 val = (BFE_CAM_HI_VALID |
1075 (((u_int32_t) data[0]) << 8) |
1076 (((u_int32_t) data[1])));
1077 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
1078 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
1079 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT)));
1080 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
1084 bfe_set_rx_mode(struct bfe_softc *sc)
1086 struct ifnet *ifp = sc->bfe_ifp;
1087 struct ifmultiaddr *ifma;
1091 BFE_LOCK_ASSERT(sc);
1093 val = CSR_READ_4(sc, BFE_RXCONF);
1095 if (ifp->if_flags & IFF_PROMISC)
1096 val |= BFE_RXCONF_PROMISC;
1098 val &= ~BFE_RXCONF_PROMISC;
1100 if (ifp->if_flags & IFF_BROADCAST)
1101 val &= ~BFE_RXCONF_DBCAST;
1103 val |= BFE_RXCONF_DBCAST;
1106 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
1107 bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++);
1109 if (ifp->if_flags & IFF_ALLMULTI)
1110 val |= BFE_RXCONF_ALLMULTI;
1112 val &= ~BFE_RXCONF_ALLMULTI;
1113 if_maddr_rlock(ifp);
1114 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1115 if (ifma->ifma_addr->sa_family != AF_LINK)
1118 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++);
1120 if_maddr_runlock(ifp);
1123 CSR_WRITE_4(sc, BFE_RXCONF, val);
1124 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
1128 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1130 struct bfe_dmamap_arg *ctx;
1135 KASSERT(nseg == 1, ("%s : %d segments returned!", __func__, nseg));
1137 ctx = (struct bfe_dmamap_arg *)arg;
1138 ctx->bfe_busaddr = segs[0].ds_addr;
1142 bfe_release_resources(struct bfe_softc *sc)
1145 if (sc->bfe_intrhand != NULL)
1146 bus_teardown_intr(sc->bfe_dev, sc->bfe_irq, sc->bfe_intrhand);
1148 if (sc->bfe_irq != NULL)
1149 bus_release_resource(sc->bfe_dev, SYS_RES_IRQ, 0, sc->bfe_irq);
1151 if (sc->bfe_res != NULL)
1152 bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0),
1155 if (sc->bfe_ifp != NULL)
1156 if_free(sc->bfe_ifp);
1160 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data)
1163 u_int16_t *ptr = (u_int16_t *)data;
1165 for(i = 0; i < 128; i += 2)
1166 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
1170 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit,
1171 u_long timeout, const int clear)
1175 for (i = 0; i < timeout; i++) {
1176 u_int32_t val = CSR_READ_4(sc, reg);
1178 if (clear && !(val & bit))
1180 if (!clear && (val & bit))
1185 device_printf(sc->bfe_dev,
1186 "BUG! Timeout waiting for bit %08x of register "
1187 "%x to %s.\n", bit, reg, (clear ? "clear" : "set"));
1194 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val)
1199 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1200 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1201 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
1202 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1203 (reg << BFE_MDIO_RA_SHIFT) |
1204 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
1205 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1206 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
1212 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val)
1216 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1217 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1218 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1219 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1220 (reg << BFE_MDIO_RA_SHIFT) |
1221 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1222 (val & BFE_MDIO_DATA_DATA)));
1223 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1229 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1233 bfe_setupphy(struct bfe_softc *sc)
1237 /* Enable activity LED */
1238 bfe_readphy(sc, 26, &val);
1239 bfe_writephy(sc, 26, val & 0x7fff);
1240 bfe_readphy(sc, 26, &val);
1242 /* Enable traffic meter LED mode */
1243 bfe_readphy(sc, 27, &val);
1244 bfe_writephy(sc, 27, val | (1 << 6));
1250 bfe_stats_update(struct bfe_softc *sc)
1252 struct bfe_hw_stats *stats;
1254 uint32_t mib[BFE_MIB_CNT];
1257 BFE_LOCK_ASSERT(sc);
1260 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
1261 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1262 *val++ = CSR_READ_4(sc, reg);
1263 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1264 *val++ = CSR_READ_4(sc, reg);
1267 stats = &sc->bfe_stats;
1269 stats->tx_good_octets += mib[MIB_TX_GOOD_O];
1270 stats->tx_good_frames += mib[MIB_TX_GOOD_P];
1271 stats->tx_octets += mib[MIB_TX_O];
1272 stats->tx_frames += mib[MIB_TX_P];
1273 stats->tx_bcast_frames += mib[MIB_TX_BCAST];
1274 stats->tx_mcast_frames += mib[MIB_TX_MCAST];
1275 stats->tx_pkts_64 += mib[MIB_TX_64];
1276 stats->tx_pkts_65_127 += mib[MIB_TX_65_127];
1277 stats->tx_pkts_128_255 += mib[MIB_TX_128_255];
1278 stats->tx_pkts_256_511 += mib[MIB_TX_256_511];
1279 stats->tx_pkts_512_1023 += mib[MIB_TX_512_1023];
1280 stats->tx_pkts_1024_max += mib[MIB_TX_1024_MAX];
1281 stats->tx_jabbers += mib[MIB_TX_JABBER];
1282 stats->tx_oversize_frames += mib[MIB_TX_OSIZE];
1283 stats->tx_frag_frames += mib[MIB_TX_FRAG];
1284 stats->tx_underruns += mib[MIB_TX_URUNS];
1285 stats->tx_colls += mib[MIB_TX_TCOLS];
1286 stats->tx_single_colls += mib[MIB_TX_SCOLS];
1287 stats->tx_multi_colls += mib[MIB_TX_MCOLS];
1288 stats->tx_excess_colls += mib[MIB_TX_ECOLS];
1289 stats->tx_late_colls += mib[MIB_TX_LCOLS];
1290 stats->tx_deferrals += mib[MIB_TX_DEFERED];
1291 stats->tx_carrier_losts += mib[MIB_TX_CLOST];
1292 stats->tx_pause_frames += mib[MIB_TX_PAUSE];
1294 stats->rx_good_octets += mib[MIB_RX_GOOD_O];
1295 stats->rx_good_frames += mib[MIB_RX_GOOD_P];
1296 stats->rx_octets += mib[MIB_RX_O];
1297 stats->rx_frames += mib[MIB_RX_P];
1298 stats->rx_bcast_frames += mib[MIB_RX_BCAST];
1299 stats->rx_mcast_frames += mib[MIB_RX_MCAST];
1300 stats->rx_pkts_64 += mib[MIB_RX_64];
1301 stats->rx_pkts_65_127 += mib[MIB_RX_65_127];
1302 stats->rx_pkts_128_255 += mib[MIB_RX_128_255];
1303 stats->rx_pkts_256_511 += mib[MIB_RX_256_511];
1304 stats->rx_pkts_512_1023 += mib[MIB_RX_512_1023];
1305 stats->rx_pkts_1024_max += mib[MIB_RX_1024_MAX];
1306 stats->rx_jabbers += mib[MIB_RX_JABBER];
1307 stats->rx_oversize_frames += mib[MIB_RX_OSIZE];
1308 stats->rx_frag_frames += mib[MIB_RX_FRAG];
1309 stats->rx_missed_frames += mib[MIB_RX_MISS];
1310 stats->rx_crc_align_errs += mib[MIB_RX_CRCA];
1311 stats->rx_runts += mib[MIB_RX_USIZE];
1312 stats->rx_crc_errs += mib[MIB_RX_CRC];
1313 stats->rx_align_errs += mib[MIB_RX_ALIGN];
1314 stats->rx_symbol_errs += mib[MIB_RX_SYM];
1315 stats->rx_pause_frames += mib[MIB_RX_PAUSE];
1316 stats->rx_control_frames += mib[MIB_RX_NPAUSE];
1318 /* Update counters in ifnet. */
1319 if_inc_counter(ifp, IFCOUNTER_OPACKETS, (u_long)mib[MIB_TX_GOOD_P]);
1320 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (u_long)mib[MIB_TX_TCOLS]);
1321 if_inc_counter(ifp, IFCOUNTER_OERRORS, (u_long)mib[MIB_TX_URUNS] +
1322 (u_long)mib[MIB_TX_ECOLS] +
1323 (u_long)mib[MIB_TX_DEFERED] +
1324 (u_long)mib[MIB_TX_CLOST]);
1326 if_inc_counter(ifp, IFCOUNTER_IPACKETS, (u_long)mib[MIB_RX_GOOD_P]);
1328 if_inc_counter(ifp, IFCOUNTER_IERRORS, mib[MIB_RX_JABBER] +
1338 bfe_txeof(struct bfe_softc *sc)
1340 struct bfe_tx_data *r;
1344 BFE_LOCK_ASSERT(sc);
1348 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1349 chipidx /= sizeof(struct bfe_desc);
1351 i = sc->bfe_tx_cons;
1354 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
1355 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1356 /* Go through the mbufs and free those that have been transmitted */
1357 for (; i != chipidx; BFE_INC(i, BFE_TX_LIST_CNT)) {
1358 r = &sc->bfe_tx_ring[i];
1360 if (r->bfe_mbuf == NULL)
1362 bus_dmamap_sync(sc->bfe_txmbuf_tag, r->bfe_map,
1363 BUS_DMASYNC_POSTWRITE);
1364 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
1366 m_freem(r->bfe_mbuf);
1370 if (i != sc->bfe_tx_cons) {
1371 /* we freed up some mbufs */
1372 sc->bfe_tx_cons = i;
1373 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1376 if (sc->bfe_tx_cnt == 0)
1377 sc->bfe_watchdog_timer = 0;
1380 /* Pass a received packet up the stack */
1382 bfe_rxeof(struct bfe_softc *sc)
1386 struct bfe_rxheader *rxheader;
1387 struct bfe_rx_data *r;
1389 u_int32_t status, current, len, flags;
1391 BFE_LOCK_ASSERT(sc);
1392 cons = sc->bfe_rx_cons;
1393 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1394 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1398 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
1399 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1401 for (prog = 0; current != cons; prog++,
1402 BFE_INC(cons, BFE_RX_LIST_CNT)) {
1403 r = &sc->bfe_rx_ring[cons];
1406 * Rx status should be read from mbuf such that we can't
1407 * delay bus_dmamap_sync(9). This hardware limiation
1408 * results in inefficent mbuf usage as bfe(4) couldn't
1409 * reuse mapped buffer from errored frame.
1411 if (bfe_list_newbuf(sc, cons) != 0) {
1412 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1413 bfe_discard_buf(sc, cons);
1416 rxheader = mtod(m, struct bfe_rxheader*);
1417 len = le16toh(rxheader->len);
1418 flags = le16toh(rxheader->flags);
1420 /* Remove CRC bytes. */
1421 len -= ETHER_CRC_LEN;
1423 /* flag an error and try again */
1424 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1429 /* Make sure to skip header bytes written by hardware. */
1430 m_adj(m, BFE_RX_OFFSET);
1431 m->m_len = m->m_pkthdr.len = len;
1433 m->m_pkthdr.rcvif = ifp;
1435 (*ifp->if_input)(ifp, m);
1440 sc->bfe_rx_cons = cons;
1441 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
1442 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1449 struct bfe_softc *sc = xsc;
1457 istat = CSR_READ_4(sc, BFE_ISTAT);
1460 * Defer unsolicited interrupts - This is necessary because setting the
1461 * chips interrupt mask register to 0 doesn't actually stop the
1464 istat &= BFE_IMASK_DEF;
1465 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1466 CSR_READ_4(sc, BFE_ISTAT);
1468 /* not expecting this interrupt, disregard it */
1469 if (istat == 0 || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1474 /* A packet was received */
1475 if (istat & BFE_ISTAT_RX)
1478 /* A packet was sent */
1479 if (istat & BFE_ISTAT_TX)
1482 if (istat & BFE_ISTAT_ERRORS) {
1484 if (istat & BFE_ISTAT_DSCE) {
1485 device_printf(sc->bfe_dev, "Descriptor Error\n");
1491 if (istat & BFE_ISTAT_DPE) {
1492 device_printf(sc->bfe_dev,
1493 "Descriptor Protocol Error\n");
1498 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1499 bfe_init_locked(sc);
1502 /* We have packets pending, fire them out */
1503 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1504 bfe_start_locked(ifp);
1510 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head)
1513 struct bfe_tx_data *r, *r1;
1516 bus_dma_segment_t txsegs[BFE_MAXTXSEGS];
1518 int error, i, nsegs;
1520 BFE_LOCK_ASSERT(sc);
1522 M_ASSERTPKTHDR((*m_head));
1524 si = cur = sc->bfe_tx_prod;
1525 r = &sc->bfe_tx_ring[cur];
1526 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head,
1528 if (error == EFBIG) {
1529 m = m_collapse(*m_head, M_NOWAIT, BFE_MAXTXSEGS);
1536 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map,
1537 *m_head, txsegs, &nsegs, 0);
1543 } else if (error != 0)
1551 if (sc->bfe_tx_cnt + nsegs > BFE_TX_LIST_CNT - 1) {
1552 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
1556 for (i = 0; i < nsegs; i++) {
1557 d = &sc->bfe_tx_list[cur];
1558 d->bfe_ctrl = htole32(txsegs[i].ds_len & BFE_DESC_LEN);
1559 d->bfe_ctrl |= htole32(BFE_DESC_IOC);
1560 if (cur == BFE_TX_LIST_CNT - 1)
1562 * Tell the chip to wrap to the start of
1563 * the descriptor list.
1565 d->bfe_ctrl |= htole32(BFE_DESC_EOT);
1566 /* The chip needs all addresses to be added to BFE_PCI_DMA. */
1567 d->bfe_addr = htole32(BFE_ADDR_LO(txsegs[i].ds_addr) +
1569 BFE_INC(cur, BFE_TX_LIST_CNT);
1572 /* Update producer index. */
1573 sc->bfe_tx_prod = cur;
1575 /* Set EOF on the last descriptor. */
1576 cur = (cur + BFE_TX_LIST_CNT - 1) % BFE_TX_LIST_CNT;
1577 d = &sc->bfe_tx_list[cur];
1578 d->bfe_ctrl |= htole32(BFE_DESC_EOF);
1580 /* Lastly set SOF on the first descriptor to avoid races. */
1581 d = &sc->bfe_tx_list[si];
1582 d->bfe_ctrl |= htole32(BFE_DESC_SOF);
1584 r1 = &sc->bfe_tx_ring[cur];
1586 r->bfe_map = r1->bfe_map;
1588 r1->bfe_mbuf = *m_head;
1589 sc->bfe_tx_cnt += nsegs;
1591 bus_dmamap_sync(sc->bfe_txmbuf_tag, map, BUS_DMASYNC_PREWRITE);
1597 * Set up to transmit a packet.
1600 bfe_start(struct ifnet *ifp)
1602 BFE_LOCK((struct bfe_softc *)ifp->if_softc);
1603 bfe_start_locked(ifp);
1604 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc);
1608 * Set up to transmit a packet. The softc is already locked.
1611 bfe_start_locked(struct ifnet *ifp)
1613 struct bfe_softc *sc;
1614 struct mbuf *m_head;
1619 BFE_LOCK_ASSERT(sc);
1622 * Not much point trying to send if the link is down
1623 * or we have nothing to send.
1625 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1626 IFF_DRV_RUNNING || (sc->bfe_flags & BFE_FLAG_LINK) == 0)
1629 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1630 sc->bfe_tx_cnt < BFE_TX_LIST_CNT - 1;) {
1631 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1636 * Pack the data into the tx ring. If we dont have
1637 * enough room, let the chip drain the ring.
1639 if (bfe_encap(sc, &m_head)) {
1642 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1643 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1650 * If there's a BPF listener, bounce a copy of this frame
1653 BPF_MTAP(ifp, m_head);
1657 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
1658 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1659 /* Transmit - twice due to apparent hardware bug */
1660 CSR_WRITE_4(sc, BFE_DMATX_PTR,
1661 sc->bfe_tx_prod * sizeof(struct bfe_desc));
1663 * XXX It seems the following write is not necessary
1664 * to kick Tx command. What might be required would be
1665 * a way flushing PCI posted write. Reading the register
1666 * back ensures the flush operation. In addition,
1667 * hardware will execute PCI posted write in the long
1668 * run and watchdog timer for the kick command was set
1669 * to 5 seconds. Therefore I think the second write
1670 * access is not necessary or could be replaced with
1673 CSR_WRITE_4(sc, BFE_DMATX_PTR,
1674 sc->bfe_tx_prod * sizeof(struct bfe_desc));
1677 * Set a timeout in case the chip goes out to lunch.
1679 sc->bfe_watchdog_timer = 5;
1686 BFE_LOCK((struct bfe_softc *)xsc);
1687 bfe_init_locked(xsc);
1688 BFE_UNLOCK((struct bfe_softc *)xsc);
1692 bfe_init_locked(void *xsc)
1694 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1695 struct ifnet *ifp = sc->bfe_ifp;
1696 struct mii_data *mii;
1698 BFE_LOCK_ASSERT(sc);
1700 mii = device_get_softc(sc->bfe_miibus);
1702 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1708 if (bfe_list_rx_init(sc) == ENOBUFS) {
1709 device_printf(sc->bfe_dev,
1710 "%s: Not enough memory for list buffers\n", __func__);
1714 bfe_list_tx_init(sc);
1716 bfe_set_rx_mode(sc);
1718 /* Enable the chip and core */
1719 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1720 /* Enable interrupts */
1721 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1723 /* Clear link state and change media. */
1724 sc->bfe_flags &= ~BFE_FLAG_LINK;
1727 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1728 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1730 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
1734 * Set media options.
1737 bfe_ifmedia_upd(struct ifnet *ifp)
1739 struct bfe_softc *sc;
1740 struct mii_data *mii;
1741 struct mii_softc *miisc;
1747 mii = device_get_softc(sc->bfe_miibus);
1748 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1750 error = mii_mediachg(mii);
1757 * Report current media status.
1760 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1762 struct bfe_softc *sc = ifp->if_softc;
1763 struct mii_data *mii;
1766 mii = device_get_softc(sc->bfe_miibus);
1768 ifmr->ifm_active = mii->mii_media_active;
1769 ifmr->ifm_status = mii->mii_media_status;
1774 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1776 struct bfe_softc *sc = ifp->if_softc;
1777 struct ifreq *ifr = (struct ifreq *) data;
1778 struct mii_data *mii;
1784 if (ifp->if_flags & IFF_UP) {
1785 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1786 bfe_set_rx_mode(sc);
1787 else if ((sc->bfe_flags & BFE_FLAG_DETACH) == 0)
1788 bfe_init_locked(sc);
1789 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1796 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1797 bfe_set_rx_mode(sc);
1802 mii = device_get_softc(sc->bfe_miibus);
1803 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1806 error = ether_ioctl(ifp, command, data);
1814 bfe_watchdog(struct bfe_softc *sc)
1818 BFE_LOCK_ASSERT(sc);
1820 if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer)
1825 device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n");
1827 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1828 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1829 bfe_init_locked(sc);
1831 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1832 bfe_start_locked(ifp);
1838 struct bfe_softc *sc = xsc;
1839 struct mii_data *mii;
1841 BFE_LOCK_ASSERT(sc);
1843 mii = device_get_softc(sc->bfe_miibus);
1845 bfe_stats_update(sc);
1847 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
1851 * Stop the adapter and free any mbufs allocated to the
1855 bfe_stop(struct bfe_softc *sc)
1859 BFE_LOCK_ASSERT(sc);
1862 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1863 sc->bfe_flags &= ~BFE_FLAG_LINK;
1864 callout_stop(&sc->bfe_stat_co);
1865 sc->bfe_watchdog_timer = 0;
1868 bfe_tx_ring_free(sc);
1869 bfe_rx_ring_free(sc);
1873 sysctl_bfe_stats(SYSCTL_HANDLER_ARGS)
1875 struct bfe_softc *sc;
1876 struct bfe_hw_stats *stats;
1880 error = sysctl_handle_int(oidp, &result, 0, req);
1882 if (error != 0 || req->newptr == NULL)
1888 sc = (struct bfe_softc *)arg1;
1889 stats = &sc->bfe_stats;
1891 printf("%s statistics:\n", device_get_nameunit(sc->bfe_dev));
1892 printf("Transmit good octets : %ju\n",
1893 (uintmax_t)stats->tx_good_octets);
1894 printf("Transmit good frames : %ju\n",
1895 (uintmax_t)stats->tx_good_frames);
1896 printf("Transmit octets : %ju\n",
1897 (uintmax_t)stats->tx_octets);
1898 printf("Transmit frames : %ju\n",
1899 (uintmax_t)stats->tx_frames);
1900 printf("Transmit broadcast frames : %ju\n",
1901 (uintmax_t)stats->tx_bcast_frames);
1902 printf("Transmit multicast frames : %ju\n",
1903 (uintmax_t)stats->tx_mcast_frames);
1904 printf("Transmit frames 64 bytes : %ju\n",
1905 (uint64_t)stats->tx_pkts_64);
1906 printf("Transmit frames 65 to 127 bytes : %ju\n",
1907 (uint64_t)stats->tx_pkts_65_127);
1908 printf("Transmit frames 128 to 255 bytes : %ju\n",
1909 (uint64_t)stats->tx_pkts_128_255);
1910 printf("Transmit frames 256 to 511 bytes : %ju\n",
1911 (uint64_t)stats->tx_pkts_256_511);
1912 printf("Transmit frames 512 to 1023 bytes : %ju\n",
1913 (uint64_t)stats->tx_pkts_512_1023);
1914 printf("Transmit frames 1024 to max bytes : %ju\n",
1915 (uint64_t)stats->tx_pkts_1024_max);
1916 printf("Transmit jabber errors : %u\n", stats->tx_jabbers);
1917 printf("Transmit oversized frames : %ju\n",
1918 (uint64_t)stats->tx_oversize_frames);
1919 printf("Transmit fragmented frames : %ju\n",
1920 (uint64_t)stats->tx_frag_frames);
1921 printf("Transmit underruns : %u\n", stats->tx_colls);
1922 printf("Transmit total collisions : %u\n", stats->tx_single_colls);
1923 printf("Transmit single collisions : %u\n", stats->tx_single_colls);
1924 printf("Transmit multiple collisions : %u\n", stats->tx_multi_colls);
1925 printf("Transmit excess collisions : %u\n", stats->tx_excess_colls);
1926 printf("Transmit late collisions : %u\n", stats->tx_late_colls);
1927 printf("Transmit deferrals : %u\n", stats->tx_deferrals);
1928 printf("Transmit carrier losts : %u\n", stats->tx_carrier_losts);
1929 printf("Transmit pause frames : %u\n", stats->tx_pause_frames);
1931 printf("Receive good octets : %ju\n",
1932 (uintmax_t)stats->rx_good_octets);
1933 printf("Receive good frames : %ju\n",
1934 (uintmax_t)stats->rx_good_frames);
1935 printf("Receive octets : %ju\n",
1936 (uintmax_t)stats->rx_octets);
1937 printf("Receive frames : %ju\n",
1938 (uintmax_t)stats->rx_frames);
1939 printf("Receive broadcast frames : %ju\n",
1940 (uintmax_t)stats->rx_bcast_frames);
1941 printf("Receive multicast frames : %ju\n",
1942 (uintmax_t)stats->rx_mcast_frames);
1943 printf("Receive frames 64 bytes : %ju\n",
1944 (uint64_t)stats->rx_pkts_64);
1945 printf("Receive frames 65 to 127 bytes : %ju\n",
1946 (uint64_t)stats->rx_pkts_65_127);
1947 printf("Receive frames 128 to 255 bytes : %ju\n",
1948 (uint64_t)stats->rx_pkts_128_255);
1949 printf("Receive frames 256 to 511 bytes : %ju\n",
1950 (uint64_t)stats->rx_pkts_256_511);
1951 printf("Receive frames 512 to 1023 bytes : %ju\n",
1952 (uint64_t)stats->rx_pkts_512_1023);
1953 printf("Receive frames 1024 to max bytes : %ju\n",
1954 (uint64_t)stats->rx_pkts_1024_max);
1955 printf("Receive jabber errors : %u\n", stats->rx_jabbers);
1956 printf("Receive oversized frames : %ju\n",
1957 (uint64_t)stats->rx_oversize_frames);
1958 printf("Receive fragmented frames : %ju\n",
1959 (uint64_t)stats->rx_frag_frames);
1960 printf("Receive missed frames : %u\n", stats->rx_missed_frames);
1961 printf("Receive CRC align errors : %u\n", stats->rx_crc_align_errs);
1962 printf("Receive undersized frames : %u\n", stats->rx_runts);
1963 printf("Receive CRC errors : %u\n", stats->rx_crc_errs);
1964 printf("Receive align errors : %u\n", stats->rx_align_errs);
1965 printf("Receive symbol errors : %u\n", stats->rx_symbol_errs);
1966 printf("Receive pause frames : %u\n", stats->rx_pause_frames);
1967 printf("Receive control frames : %u\n", stats->rx_control_frames);