2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 2001 Wind River Systems
5 * Copyright (c) 1997, 1998, 1999, 2001
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
40 * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver
42 * The Broadcom BCM5700 is based on technology originally developed by
43 * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet
44 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
45 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
46 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
47 * frames, highly configurable RX filtering, and 16 RX and TX queues
48 * (which, along with RX filter rules, can be used for QOS applications).
49 * Other features, such as TCP segmentation, may be available as part
50 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
51 * firmware images can be stored in hardware and need not be compiled
54 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
55 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
57 * The BCM5701 is a single-chip solution incorporating both the BCM5700
58 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
59 * does not support external SSRAM.
61 * Broadcom also produces a variation of the BCM5700 under the "Altima"
62 * brand name, which is functionally similar but lacks PCI-X support.
64 * Without external SSRAM, you can only have at most 4 TX rings,
65 * and the use of the mini RX ring is disabled. This seems to imply
66 * that these features are simply not available on the BCM5701. As a
67 * result, this driver does not implement any support for the mini RX
71 #ifdef HAVE_KERNEL_OPTION_HEADERS
72 #include "opt_device_polling.h"
75 #include <sys/param.h>
76 #include <sys/endian.h>
77 #include <sys/systm.h>
78 #include <sys/sockio.h>
80 #include <sys/malloc.h>
81 #include <sys/kernel.h>
82 #include <sys/module.h>
83 #include <sys/socket.h>
84 #include <sys/sysctl.h>
85 #include <sys/taskqueue.h>
87 #include <net/debugnet.h>
89 #include <net/if_var.h>
90 #include <net/if_arp.h>
91 #include <net/ethernet.h>
92 #include <net/if_dl.h>
93 #include <net/if_media.h>
97 #include <net/if_types.h>
98 #include <net/if_vlan_var.h>
100 #include <netinet/in_systm.h>
101 #include <netinet/in.h>
102 #include <netinet/ip.h>
103 #include <netinet/tcp.h>
105 #include <machine/bus.h>
106 #include <machine/resource.h>
108 #include <sys/rman.h>
110 #include <dev/mii/mii.h>
111 #include <dev/mii/miivar.h>
113 #include <dev/mii/brgphyreg.h>
116 #include <dev/ofw/ofw_bus.h>
117 #include <dev/ofw/openfirm.h>
118 #include <machine/ofw_machdep.h>
119 #include <machine/ver.h>
122 #include <dev/pci/pcireg.h>
123 #include <dev/pci/pcivar.h>
125 #include <dev/bge/if_bgereg.h>
127 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP)
128 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
130 MODULE_DEPEND(bge, pci, 1, 1, 1);
131 MODULE_DEPEND(bge, ether, 1, 1, 1);
132 MODULE_DEPEND(bge, miibus, 1, 1, 1);
134 /* "device miibus" required. See GENERIC if you get errors here. */
135 #include "miibus_if.h"
138 * Various supported device vendors/types and their names. Note: the
139 * spec seems to indicate that the hardware still has Alteon's vendor
140 * ID burned into it, though it will always be overriden by the vendor
141 * ID in the EEPROM. Just to be safe, we cover all possibilities.
143 static const struct bge_type {
147 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 },
148 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 },
150 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 },
151 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 },
152 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 },
154 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 },
156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 },
157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 },
158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 },
159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT },
160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X },
161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 },
162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT },
163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X },
164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C },
165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S },
166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT },
167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 },
168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F },
169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K },
170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M },
171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT },
172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C },
173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S },
174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 },
175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S },
176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 },
177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717C },
178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 },
179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 },
180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 },
181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 },
182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 },
183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 },
184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5725 },
185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5727 },
186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 },
187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M },
188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 },
189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F },
190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M },
191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 },
192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M },
193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 },
194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F },
195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M },
196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 },
197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M },
198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 },
199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M },
200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 },
201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 },
202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E },
203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S },
204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE },
205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5762 },
206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 },
207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 },
208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S },
209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 },
210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 },
211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 },
212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F },
213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G },
214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 },
215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 },
216 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F },
217 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M },
218 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 },
219 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 },
220 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 },
221 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 },
222 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M },
223 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 },
224 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M },
225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 },
226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 },
227 { BCOM_VENDORID, BCOM_DEVICEID_BCM57762 },
228 { BCOM_VENDORID, BCOM_DEVICEID_BCM57764 },
229 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 },
230 { BCOM_VENDORID, BCOM_DEVICEID_BCM57766 },
231 { BCOM_VENDORID, BCOM_DEVICEID_BCM57767 },
232 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 },
233 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 },
234 { BCOM_VENDORID, BCOM_DEVICEID_BCM57782 },
235 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 },
236 { BCOM_VENDORID, BCOM_DEVICEID_BCM57786 },
237 { BCOM_VENDORID, BCOM_DEVICEID_BCM57787 },
238 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 },
239 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 },
240 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 },
241 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 },
243 { SK_VENDORID, SK_DEVICEID_ALTIMA },
245 { TC_VENDORID, TC_DEVICEID_3C996 },
247 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 },
248 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 },
249 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 },
254 static const struct bge_vendor {
258 { ALTEON_VENDORID, "Alteon" },
259 { ALTIMA_VENDORID, "Altima" },
260 { APPLE_VENDORID, "Apple" },
261 { BCOM_VENDORID, "Broadcom" },
262 { SK_VENDORID, "SysKonnect" },
263 { TC_VENDORID, "3Com" },
264 { FJTSU_VENDORID, "Fujitsu" },
269 static const struct bge_revision {
272 } bge_revisions[] = {
273 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" },
274 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" },
275 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" },
276 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" },
277 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" },
278 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" },
279 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" },
280 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" },
281 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" },
282 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" },
283 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" },
284 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" },
285 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" },
286 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" },
287 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" },
288 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" },
289 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" },
290 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" },
291 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" },
292 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" },
293 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" },
294 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" },
295 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" },
296 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" },
297 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" },
298 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" },
299 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" },
300 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" },
301 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" },
302 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" },
303 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" },
304 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" },
305 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" },
306 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" },
307 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
308 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
309 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
310 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
311 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
312 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
313 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
314 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
315 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
316 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" },
317 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" },
318 { BGE_CHIPID_BCM5717_C0, "BCM5717 C0" },
319 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" },
320 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" },
321 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
322 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
323 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
324 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" },
325 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" },
326 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" },
327 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" },
328 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" },
329 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" },
330 /* 5754 and 5787 share the same ASIC ID */
331 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
332 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
333 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
334 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" },
335 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" },
336 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" },
337 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" },
338 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" },
339 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" },
345 * Some defaults for major revisions, so that newer steppings
346 * that we don't know about have a shot at working.
348 static const struct bge_revision bge_majorrevs[] = {
349 { BGE_ASICREV_BCM5700, "unknown BCM5700" },
350 { BGE_ASICREV_BCM5701, "unknown BCM5701" },
351 { BGE_ASICREV_BCM5703, "unknown BCM5703" },
352 { BGE_ASICREV_BCM5704, "unknown BCM5704" },
353 { BGE_ASICREV_BCM5705, "unknown BCM5705" },
354 { BGE_ASICREV_BCM5750, "unknown BCM5750" },
355 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
356 { BGE_ASICREV_BCM5752, "unknown BCM5752" },
357 { BGE_ASICREV_BCM5780, "unknown BCM5780" },
358 { BGE_ASICREV_BCM5714, "unknown BCM5714" },
359 { BGE_ASICREV_BCM5755, "unknown BCM5755" },
360 { BGE_ASICREV_BCM5761, "unknown BCM5761" },
361 { BGE_ASICREV_BCM5784, "unknown BCM5784" },
362 { BGE_ASICREV_BCM5785, "unknown BCM5785" },
363 /* 5754 and 5787 share the same ASIC ID */
364 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
365 { BGE_ASICREV_BCM5906, "unknown BCM5906" },
366 { BGE_ASICREV_BCM57765, "unknown BCM57765" },
367 { BGE_ASICREV_BCM57766, "unknown BCM57766" },
368 { BGE_ASICREV_BCM57780, "unknown BCM57780" },
369 { BGE_ASICREV_BCM5717, "unknown BCM5717" },
370 { BGE_ASICREV_BCM5719, "unknown BCM5719" },
371 { BGE_ASICREV_BCM5720, "unknown BCM5720" },
372 { BGE_ASICREV_BCM5762, "unknown BCM5762" },
377 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
378 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
379 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
380 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
381 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
382 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
383 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS)
384 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_57765_PLUS)
386 static uint32_t bge_chipid(device_t);
387 static const struct bge_vendor * bge_lookup_vendor(uint16_t);
388 static const struct bge_revision * bge_lookup_rev(uint32_t);
390 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
392 static int bge_probe(device_t);
393 static int bge_attach(device_t);
394 static int bge_detach(device_t);
395 static int bge_suspend(device_t);
396 static int bge_resume(device_t);
397 static void bge_release_resources(struct bge_softc *);
398 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
399 static int bge_dma_alloc(struct bge_softc *);
400 static void bge_dma_free(struct bge_softc *);
401 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t,
402 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
404 static void bge_devinfo(struct bge_softc *);
405 static int bge_mbox_reorder(struct bge_softc *);
407 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
408 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
409 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
410 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
411 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
413 static void bge_txeof(struct bge_softc *, uint16_t);
414 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
415 static int bge_rxeof(struct bge_softc *, uint16_t, int);
417 static void bge_asf_driver_up (struct bge_softc *);
418 static void bge_tick(void *);
419 static void bge_stats_clear_regs(struct bge_softc *);
420 static void bge_stats_update(struct bge_softc *);
421 static void bge_stats_update_regs(struct bge_softc *);
422 static struct mbuf *bge_check_short_dma(struct mbuf *);
423 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
424 uint16_t *, uint16_t *);
425 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
427 static void bge_intr(void *);
428 static int bge_msi_intr(void *);
429 static void bge_intr_task(void *, int);
430 static void bge_start(if_t);
431 static void bge_start_locked(if_t);
432 static void bge_start_tx(struct bge_softc *, uint32_t);
433 static int bge_ioctl(if_t, u_long, caddr_t);
434 static void bge_init_locked(struct bge_softc *);
435 static void bge_init(void *);
436 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
437 static void bge_stop(struct bge_softc *);
438 static void bge_watchdog(struct bge_softc *);
439 static int bge_shutdown(device_t);
440 static int bge_ifmedia_upd_locked(if_t);
441 static int bge_ifmedia_upd(if_t);
442 static void bge_ifmedia_sts(if_t, struct ifmediareq *);
443 static uint64_t bge_get_counter(if_t, ift_counter);
445 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
446 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
448 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
449 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
451 static void bge_setpromisc(struct bge_softc *);
452 static void bge_setmulti(struct bge_softc *);
453 static void bge_setvlan(struct bge_softc *);
455 static __inline void bge_rxreuse_std(struct bge_softc *, int);
456 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
457 static int bge_newbuf_std(struct bge_softc *, int);
458 static int bge_newbuf_jumbo(struct bge_softc *, int);
459 static int bge_init_rx_ring_std(struct bge_softc *);
460 static void bge_free_rx_ring_std(struct bge_softc *);
461 static int bge_init_rx_ring_jumbo(struct bge_softc *);
462 static void bge_free_rx_ring_jumbo(struct bge_softc *);
463 static void bge_free_tx_ring(struct bge_softc *);
464 static int bge_init_tx_ring(struct bge_softc *);
466 static int bge_chipinit(struct bge_softc *);
467 static int bge_blockinit(struct bge_softc *);
468 static uint32_t bge_dma_swap_options(struct bge_softc *);
470 static int bge_has_eaddr(struct bge_softc *);
471 static uint32_t bge_readmem_ind(struct bge_softc *, int);
472 static void bge_writemem_ind(struct bge_softc *, int, int);
473 static void bge_writembx(struct bge_softc *, int, int);
475 static uint32_t bge_readreg_ind(struct bge_softc *, int);
477 static void bge_writemem_direct(struct bge_softc *, int, int);
478 static void bge_writereg_ind(struct bge_softc *, int, int);
480 static int bge_miibus_readreg(device_t, int, int);
481 static int bge_miibus_writereg(device_t, int, int, int);
482 static void bge_miibus_statchg(device_t);
483 #ifdef DEVICE_POLLING
484 static int bge_poll(if_t ifp, enum poll_cmd cmd, int count);
487 #define BGE_RESET_SHUTDOWN 0
488 #define BGE_RESET_START 1
489 #define BGE_RESET_SUSPEND 2
490 static void bge_sig_post_reset(struct bge_softc *, int);
491 static void bge_sig_legacy(struct bge_softc *, int);
492 static void bge_sig_pre_reset(struct bge_softc *, int);
493 static void bge_stop_fw(struct bge_softc *);
494 static int bge_reset(struct bge_softc *);
495 static void bge_link_upd(struct bge_softc *);
497 static void bge_ape_lock_init(struct bge_softc *);
498 static void bge_ape_read_fw_ver(struct bge_softc *);
499 static int bge_ape_lock(struct bge_softc *, int);
500 static void bge_ape_unlock(struct bge_softc *, int);
501 static void bge_ape_send_event(struct bge_softc *, uint32_t);
502 static void bge_ape_driver_state_change(struct bge_softc *, int);
505 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may
506 * leak information to untrusted users. It is also known to cause alignment
507 * traps on certain architectures.
509 #ifdef BGE_REGISTER_DEBUG
510 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
511 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
512 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS);
513 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
515 static void bge_add_sysctls(struct bge_softc *);
516 static void bge_add_sysctl_stats_regs(struct bge_softc *,
517 struct sysctl_ctx_list *, struct sysctl_oid_list *);
518 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *,
519 struct sysctl_oid_list *);
520 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
522 DEBUGNET_DEFINE(bge);
524 static device_method_t bge_methods[] = {
525 /* Device interface */
526 DEVMETHOD(device_probe, bge_probe),
527 DEVMETHOD(device_attach, bge_attach),
528 DEVMETHOD(device_detach, bge_detach),
529 DEVMETHOD(device_shutdown, bge_shutdown),
530 DEVMETHOD(device_suspend, bge_suspend),
531 DEVMETHOD(device_resume, bge_resume),
534 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
535 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
536 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
541 static driver_t bge_driver = {
544 sizeof(struct bge_softc)
547 static devclass_t bge_devclass;
549 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
550 MODULE_PNP_INFO("U16:vendor;U16:device", pci, bge, bge_devs,
551 nitems(bge_devs) - 1);
552 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
554 static int bge_allow_asf = 1;
556 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
557 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RDTUN, &bge_allow_asf, 0,
558 "Allow ASF mode if available");
560 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500"
561 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2"
562 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500"
563 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3"
564 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id"
567 bge_has_eaddr(struct bge_softc *sc)
570 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
577 * The on-board BGEs found in sun4u machines aren't fitted with
578 * an EEPROM which means that we have to obtain the MAC address
579 * via OFW and that some tests will always fail. We distinguish
580 * such BGEs by the subvendor ID, which also has to be obtained
581 * from OFW instead of the PCI configuration space as the latter
582 * indicates Broadcom as the subvendor of the netboot interface.
583 * For early Blade 1500 and 2500 we even have to check the OFW
584 * device path as the subvendor ID always defaults to Broadcom
587 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
588 &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
589 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID))
591 memset(buf, 0, sizeof(buf));
592 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
593 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
594 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
596 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
597 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
605 bge_readmem_ind(struct bge_softc *sc, int off)
610 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
611 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
616 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
617 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
618 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
623 bge_writemem_ind(struct bge_softc *sc, int off, int val)
627 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
628 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
633 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
634 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
635 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
640 bge_readreg_ind(struct bge_softc *sc, int off)
646 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
647 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
652 bge_writereg_ind(struct bge_softc *sc, int off, int val)
658 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
659 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
663 bge_writemem_direct(struct bge_softc *sc, int off, int val)
665 CSR_WRITE_4(sc, off, val);
669 bge_writembx(struct bge_softc *sc, int off, int val)
671 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
672 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
674 CSR_WRITE_4(sc, off, val);
675 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0)
680 * Clear all stale locks and select the lock for this driver instance.
683 bge_ape_lock_init(struct bge_softc *sc)
685 uint32_t bit, regbase;
688 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
689 regbase = BGE_APE_LOCK_GRANT;
691 regbase = BGE_APE_PER_LOCK_GRANT;
693 /* Clear any stale locks. */
694 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
696 case BGE_APE_LOCK_PHY0:
697 case BGE_APE_LOCK_PHY1:
698 case BGE_APE_LOCK_PHY2:
699 case BGE_APE_LOCK_PHY3:
700 bit = BGE_APE_LOCK_GRANT_DRIVER0;
703 if (sc->bge_func_addr == 0)
704 bit = BGE_APE_LOCK_GRANT_DRIVER0;
706 bit = (1 << sc->bge_func_addr);
708 APE_WRITE_4(sc, regbase + 4 * i, bit);
711 /* Select the PHY lock based on the device's function number. */
712 switch (sc->bge_func_addr) {
714 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
717 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
720 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
723 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
726 device_printf(sc->bge_dev,
727 "PHY lock not supported on this function\n");
732 * Check for APE firmware, set flags, and print version info.
735 bge_ape_read_fw_ver(struct bge_softc *sc)
738 uint32_t apedata, features;
740 /* Check for a valid APE signature in shared memory. */
741 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
742 if (apedata != BGE_APE_SEG_SIG_MAGIC) {
743 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE;
747 /* Check if APE firmware is running. */
748 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
749 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) {
750 device_printf(sc->bge_dev, "APE signature found "
751 "but FW status not ready! 0x%08x\n", apedata);
755 sc->bge_mfw_flags |= BGE_MFW_ON_APE;
757 /* Fetch the APE firwmare type and version. */
758 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
759 features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
760 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) {
761 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
763 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) {
764 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
769 /* Print the APE firmware version. */
770 device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n",
772 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT,
773 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT,
774 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT,
775 (apedata & BGE_APE_FW_VERSION_BLDMSK));
779 bge_ape_lock(struct bge_softc *sc, int locknum)
781 uint32_t bit, gnt, req, status;
784 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
787 /* Lock request/grant registers have different bases. */
788 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) {
789 req = BGE_APE_LOCK_REQ;
790 gnt = BGE_APE_LOCK_GRANT;
792 req = BGE_APE_PER_LOCK_REQ;
793 gnt = BGE_APE_PER_LOCK_GRANT;
799 case BGE_APE_LOCK_GPIO:
800 /* Lock required when using GPIO. */
801 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
803 if (sc->bge_func_addr == 0)
804 bit = BGE_APE_LOCK_REQ_DRIVER0;
806 bit = (1 << sc->bge_func_addr);
808 case BGE_APE_LOCK_GRC:
809 /* Lock required to reset the device. */
810 if (sc->bge_func_addr == 0)
811 bit = BGE_APE_LOCK_REQ_DRIVER0;
813 bit = (1 << sc->bge_func_addr);
815 case BGE_APE_LOCK_MEM:
816 /* Lock required when accessing certain APE memory. */
817 if (sc->bge_func_addr == 0)
818 bit = BGE_APE_LOCK_REQ_DRIVER0;
820 bit = (1 << sc->bge_func_addr);
822 case BGE_APE_LOCK_PHY0:
823 case BGE_APE_LOCK_PHY1:
824 case BGE_APE_LOCK_PHY2:
825 case BGE_APE_LOCK_PHY3:
826 /* Lock required when accessing PHYs. */
827 bit = BGE_APE_LOCK_REQ_DRIVER0;
833 /* Request a lock. */
834 APE_WRITE_4(sc, req + off, bit);
836 /* Wait up to 1 second to acquire lock. */
837 for (i = 0; i < 20000; i++) {
838 status = APE_READ_4(sc, gnt + off);
844 /* Handle any errors. */
846 device_printf(sc->bge_dev, "APE lock %d request failed! "
847 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
848 locknum, req + off, bit & 0xFFFF, gnt + off,
850 /* Revoke the lock request. */
851 APE_WRITE_4(sc, gnt + off, bit);
859 bge_ape_unlock(struct bge_softc *sc, int locknum)
864 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
867 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
868 gnt = BGE_APE_LOCK_GRANT;
870 gnt = BGE_APE_PER_LOCK_GRANT;
875 case BGE_APE_LOCK_GPIO:
876 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
878 if (sc->bge_func_addr == 0)
879 bit = BGE_APE_LOCK_GRANT_DRIVER0;
881 bit = (1 << sc->bge_func_addr);
883 case BGE_APE_LOCK_GRC:
884 if (sc->bge_func_addr == 0)
885 bit = BGE_APE_LOCK_GRANT_DRIVER0;
887 bit = (1 << sc->bge_func_addr);
889 case BGE_APE_LOCK_MEM:
890 if (sc->bge_func_addr == 0)
891 bit = BGE_APE_LOCK_GRANT_DRIVER0;
893 bit = (1 << sc->bge_func_addr);
895 case BGE_APE_LOCK_PHY0:
896 case BGE_APE_LOCK_PHY1:
897 case BGE_APE_LOCK_PHY2:
898 case BGE_APE_LOCK_PHY3:
899 bit = BGE_APE_LOCK_GRANT_DRIVER0;
905 APE_WRITE_4(sc, gnt + off, bit);
909 * Send an event to the APE firmware.
912 bge_ape_send_event(struct bge_softc *sc, uint32_t event)
917 /* NCSI does not support APE events. */
918 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
921 /* Wait up to 1ms for APE to service previous event. */
922 for (i = 10; i > 0; i--) {
923 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
925 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
926 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) {
927 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
928 BGE_APE_EVENT_STATUS_EVENT_PENDING);
929 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
930 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
933 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
937 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n",
942 bge_ape_driver_state_change(struct bge_softc *sc, int kind)
944 uint32_t apedata, event;
946 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
950 case BGE_RESET_START:
951 /* If this is the first load, clear the load counter. */
952 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
953 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC)
954 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
956 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
957 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
959 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
960 BGE_APE_HOST_SEG_SIG_MAGIC);
961 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
962 BGE_APE_HOST_SEG_LEN_MAGIC);
964 /* Add some version info if bge(4) supports it. */
965 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
966 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0));
967 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
968 BGE_APE_HOST_BEHAV_NO_PHYLOCK);
969 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
970 BGE_APE_HOST_HEARTBEAT_INT_DISABLE);
971 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
972 BGE_APE_HOST_DRVR_STATE_START);
973 event = BGE_APE_EVENT_STATUS_STATE_START;
975 case BGE_RESET_SHUTDOWN:
976 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
977 BGE_APE_HOST_DRVR_STATE_UNLOAD);
978 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
980 case BGE_RESET_SUSPEND:
981 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
987 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
988 BGE_APE_EVENT_STATUS_STATE_CHNGE);
992 * Map a single buffer address.
996 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
998 struct bge_dmamap_arg *ctx;
1003 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
1006 ctx->bge_busaddr = segs->ds_addr;
1010 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1012 uint32_t access, byte = 0;
1016 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
1017 for (i = 0; i < 8000; i++) {
1018 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
1025 /* Enable access. */
1026 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
1027 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
1029 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
1030 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
1031 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
1033 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
1039 if (i == BGE_TIMEOUT * 10) {
1040 if_printf(sc->bge_ifp, "nvram read timed out\n");
1045 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
1047 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
1049 /* Disable access. */
1050 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
1053 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
1054 CSR_READ_4(sc, BGE_NVRAM_SWARB);
1060 * Read a sequence of bytes from NVRAM.
1063 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1068 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1071 for (i = 0; i < cnt; i++) {
1072 err = bge_nvram_getbyte(sc, off + i, &byte);
1078 return (err ? 1 : 0);
1082 * Read a byte of data stored in the EEPROM at address 'addr.' The
1083 * BCM570x supports both the traditional bitbang interface and an
1084 * auto access interface for reading the EEPROM. We use the auto
1088 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1094 * Enable use of auto EEPROM access so we can avoid
1095 * having to use the bitbang method.
1097 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
1099 /* Reset the EEPROM, load the clock period. */
1100 CSR_WRITE_4(sc, BGE_EE_ADDR,
1101 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
1104 /* Issue the read EEPROM command. */
1105 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
1107 /* Wait for completion */
1108 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
1110 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1114 if (i == BGE_TIMEOUT * 10) {
1115 device_printf(sc->bge_dev, "EEPROM read timed out\n");
1120 byte = CSR_READ_4(sc, BGE_EE_DATA);
1122 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
1128 * Read a sequence of bytes from the EEPROM.
1131 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1136 for (i = 0; i < cnt; i++) {
1137 error = bge_eeprom_getbyte(sc, off + i, &byte);
1143 return (error ? 1 : 0);
1147 bge_miibus_readreg(device_t dev, int phy, int reg)
1149 struct bge_softc *sc;
1153 sc = device_get_softc(dev);
1155 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1158 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1159 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1160 CSR_WRITE_4(sc, BGE_MI_MODE,
1161 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1165 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
1166 BGE_MIPHY(phy) | BGE_MIREG(reg));
1168 /* Poll for the PHY register access to complete. */
1169 for (i = 0; i < BGE_TIMEOUT; i++) {
1171 val = CSR_READ_4(sc, BGE_MI_COMM);
1172 if ((val & BGE_MICOMM_BUSY) == 0) {
1174 val = CSR_READ_4(sc, BGE_MI_COMM);
1179 if (i == BGE_TIMEOUT) {
1180 device_printf(sc->bge_dev,
1181 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
1186 /* Restore the autopoll bit if necessary. */
1187 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1188 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1192 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1194 if (val & BGE_MICOMM_READFAIL)
1197 return (val & 0xFFFF);
1201 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
1203 struct bge_softc *sc;
1206 sc = device_get_softc(dev);
1208 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1209 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
1212 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1215 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1216 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1217 CSR_WRITE_4(sc, BGE_MI_MODE,
1218 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1222 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
1223 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
1225 for (i = 0; i < BGE_TIMEOUT; i++) {
1227 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
1229 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
1234 /* Restore the autopoll bit if necessary. */
1235 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1236 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1240 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1242 if (i == BGE_TIMEOUT)
1243 device_printf(sc->bge_dev,
1244 "PHY write timed out (phy %d, reg %d, val 0x%04x)\n",
1251 bge_miibus_statchg(device_t dev)
1253 struct bge_softc *sc;
1254 struct mii_data *mii;
1255 uint32_t mac_mode, rx_mode, tx_mode;
1257 sc = device_get_softc(dev);
1258 if ((if_getdrvflags(sc->bge_ifp) & IFF_DRV_RUNNING) == 0)
1260 mii = device_get_softc(sc->bge_miibus);
1262 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1263 (IFM_ACTIVE | IFM_AVALID)) {
1264 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1272 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1283 if (sc->bge_link == 0)
1287 * APE firmware touches these registers to keep the MAC
1288 * connected to the outside world. Try to keep the
1292 /* Set the port mode (MII/GMII) to match the link speed. */
1293 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
1294 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
1295 tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
1296 rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
1298 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1299 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
1300 mac_mode |= BGE_PORTMODE_GMII;
1302 mac_mode |= BGE_PORTMODE_MII;
1304 /* Set MAC flow control behavior to match link flow control settings. */
1305 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE;
1306 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE;
1307 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1308 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1309 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE;
1310 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1311 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE;
1313 mac_mode |= BGE_MACMODE_HALF_DUPLEX;
1315 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
1317 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
1318 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
1322 * Intialize a standard receive ring descriptor.
1325 bge_newbuf_std(struct bge_softc *sc, int i)
1328 struct bge_rx_bd *r;
1329 bus_dma_segment_t segs[1];
1333 if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
1334 (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
1335 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) {
1336 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1339 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1341 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1344 m->m_len = m->m_pkthdr.len = MCLBYTES;
1346 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1347 m_adj(m, ETHER_ALIGN);
1349 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
1350 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
1355 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1356 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1357 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
1358 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1359 sc->bge_cdata.bge_rx_std_dmamap[i]);
1361 map = sc->bge_cdata.bge_rx_std_dmamap[i];
1362 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
1363 sc->bge_cdata.bge_rx_std_sparemap = map;
1364 sc->bge_cdata.bge_rx_std_chain[i] = m;
1365 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
1366 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
1367 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1368 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1369 r->bge_flags = BGE_RXBDFLAG_END;
1370 r->bge_len = segs[0].ds_len;
1373 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1374 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
1380 * Initialize a jumbo receive ring descriptor. This allocates
1381 * a jumbo buffer from the pool managed internally by the driver.
1384 bge_newbuf_jumbo(struct bge_softc *sc, int i)
1386 bus_dma_segment_t segs[BGE_NSEG_JUMBO];
1388 struct bge_extrx_bd *r;
1392 MGETHDR(m, M_NOWAIT, MT_DATA);
1396 if (m_cljget(m, M_NOWAIT, MJUM9BYTES) == NULL) {
1400 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1401 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1402 m_adj(m, ETHER_ALIGN);
1404 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1405 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1411 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1412 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1413 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1414 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1415 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1417 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1418 sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1419 sc->bge_cdata.bge_rx_jumbo_sparemap;
1420 sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1421 sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1422 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1423 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1424 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1425 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1428 * Fill in the extended RX buffer descriptor.
1430 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1431 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1433 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1436 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1437 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1438 r->bge_len3 = segs[3].ds_len;
1439 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1441 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1442 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1443 r->bge_len2 = segs[2].ds_len;
1444 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1446 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1447 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1448 r->bge_len1 = segs[1].ds_len;
1449 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1451 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1452 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1453 r->bge_len0 = segs[0].ds_len;
1454 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1457 panic("%s: %d segments\n", __func__, nsegs);
1460 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1461 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1467 bge_init_rx_ring_std(struct bge_softc *sc)
1471 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1473 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1474 if ((error = bge_newbuf_std(sc, i)) != 0)
1476 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1479 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1480 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1483 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1489 bge_free_rx_ring_std(struct bge_softc *sc)
1493 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1494 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1495 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1496 sc->bge_cdata.bge_rx_std_dmamap[i],
1497 BUS_DMASYNC_POSTREAD);
1498 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1499 sc->bge_cdata.bge_rx_std_dmamap[i]);
1500 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1501 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1503 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1504 sizeof(struct bge_rx_bd));
1509 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1511 struct bge_rcb *rcb;
1514 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1516 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1517 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1519 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1522 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1523 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1527 /* Enable the jumbo receive producer ring. */
1528 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1529 rcb->bge_maxlen_flags =
1530 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD);
1531 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1533 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1539 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1543 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1544 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1545 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1546 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1547 BUS_DMASYNC_POSTREAD);
1548 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1549 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1550 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1551 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1553 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1554 sizeof(struct bge_extrx_bd));
1559 bge_free_tx_ring(struct bge_softc *sc)
1563 if (sc->bge_ldata.bge_tx_ring == NULL)
1566 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1567 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1568 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1569 sc->bge_cdata.bge_tx_dmamap[i],
1570 BUS_DMASYNC_POSTWRITE);
1571 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1572 sc->bge_cdata.bge_tx_dmamap[i]);
1573 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1574 sc->bge_cdata.bge_tx_chain[i] = NULL;
1576 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1577 sizeof(struct bge_tx_bd));
1582 bge_init_tx_ring(struct bge_softc *sc)
1585 sc->bge_tx_saved_considx = 0;
1587 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1588 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1589 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1591 /* Initialize transmit producer index for host-memory send ring. */
1592 sc->bge_tx_prodidx = 0;
1593 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1595 /* 5700 b2 errata */
1596 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1597 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1599 /* NIC-memory send ring not used; initialize to zero. */
1600 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1601 /* 5700 b2 errata */
1602 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1603 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1609 bge_setpromisc(struct bge_softc *sc)
1613 BGE_LOCK_ASSERT(sc);
1617 /* Enable or disable promiscuous mode as needed. */
1618 if (if_getflags(ifp) & IFF_PROMISC)
1619 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1621 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1625 bge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1627 uint32_t *hashes = arg;
1630 h = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0x7F;
1631 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1637 bge_setmulti(struct bge_softc *sc)
1640 uint32_t hashes[4] = { 0, 0, 0, 0 };
1643 BGE_LOCK_ASSERT(sc);
1647 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) {
1648 for (i = 0; i < 4; i++)
1649 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1653 /* First, zot all the existing filters. */
1654 for (i = 0; i < 4; i++)
1655 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1657 if_foreach_llmaddr(ifp, bge_hash_maddr, hashes);
1659 for (i = 0; i < 4; i++)
1660 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1664 bge_setvlan(struct bge_softc *sc)
1668 BGE_LOCK_ASSERT(sc);
1672 /* Enable or disable VLAN tag stripping as needed. */
1673 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING)
1674 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1676 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1680 bge_sig_pre_reset(struct bge_softc *sc, int type)
1684 * Some chips don't like this so only do this if ASF is enabled
1686 if (sc->bge_asf_mode)
1687 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
1689 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1691 case BGE_RESET_START:
1692 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1693 BGE_FW_DRV_STATE_START);
1695 case BGE_RESET_SHUTDOWN:
1696 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1697 BGE_FW_DRV_STATE_UNLOAD);
1699 case BGE_RESET_SUSPEND:
1700 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1701 BGE_FW_DRV_STATE_SUSPEND);
1706 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
1707 bge_ape_driver_state_change(sc, type);
1711 bge_sig_post_reset(struct bge_softc *sc, int type)
1714 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1716 case BGE_RESET_START:
1717 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1718 BGE_FW_DRV_STATE_START_DONE);
1721 case BGE_RESET_SHUTDOWN:
1722 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1723 BGE_FW_DRV_STATE_UNLOAD_DONE);
1727 if (type == BGE_RESET_SHUTDOWN)
1728 bge_ape_driver_state_change(sc, type);
1732 bge_sig_legacy(struct bge_softc *sc, int type)
1735 if (sc->bge_asf_mode) {
1737 case BGE_RESET_START:
1738 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1739 BGE_FW_DRV_STATE_START);
1741 case BGE_RESET_SHUTDOWN:
1742 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1743 BGE_FW_DRV_STATE_UNLOAD);
1750 bge_stop_fw(struct bge_softc *sc)
1754 if (sc->bge_asf_mode) {
1755 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
1756 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
1757 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
1759 for (i = 0; i < 100; i++ ) {
1760 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1761 BGE_RX_CPU_DRV_EVENT))
1769 bge_dma_swap_options(struct bge_softc *sc)
1771 uint32_t dma_options;
1773 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
1774 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
1775 #if BYTE_ORDER == BIG_ENDIAN
1776 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
1778 return (dma_options);
1782 * Do endian, PCI and DMA initialization.
1785 bge_chipinit(struct bge_softc *sc)
1787 uint32_t dma_rw_ctl, misc_ctl, mode_ctl;
1791 /* Set endianness before we access any non-PCI registers. */
1792 misc_ctl = BGE_INIT;
1793 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1794 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1795 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1798 * Clear the MAC statistics block in the NIC's
1801 for (i = BGE_STATS_BLOCK;
1802 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1803 BGE_MEMWIN_WRITE(sc, i, 0);
1805 for (i = BGE_STATUS_BLOCK;
1806 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1807 BGE_MEMWIN_WRITE(sc, i, 0);
1809 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1811 * Fix data corruption caused by non-qword write with WB.
1812 * Fix master abort in PCI mode.
1813 * Fix PCI latency timer.
1815 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1816 val |= (1 << 10) | (1 << 12) | (1 << 13);
1817 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1820 if (sc->bge_asicrev == BGE_ASICREV_BCM57765 ||
1821 sc->bge_asicrev == BGE_ASICREV_BCM57766) {
1823 * For the 57766 and non Ax versions of 57765, bootcode
1824 * needs to setup the PCIE Fast Training Sequence (FTS)
1825 * value to prevent transmit hangs.
1827 if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) {
1828 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL,
1829 CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) |
1830 BGE_CPMU_PADRNG_CTL_RDIV2);
1835 * Set up the PCI DMA control register.
1837 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1838 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1839 if (sc->bge_flags & BGE_FLAG_PCIE) {
1840 if (sc->bge_mps >= 256)
1841 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1843 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1844 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1845 if (BGE_IS_5714_FAMILY(sc)) {
1846 /* 256 bytes for read and write. */
1847 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1848 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1849 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1850 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1851 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1852 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1854 * In the BCM5703, the DMA read watermark should
1855 * be set to less than or equal to the maximum
1856 * memory read byte count of the PCI-X command
1859 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1860 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1861 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1862 /* 1536 bytes for read, 384 bytes for write. */
1863 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1864 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1866 /* 384 bytes for read and write. */
1867 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1868 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1871 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1872 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1875 /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1876 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1877 if (tmp == 6 || tmp == 7)
1879 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1881 /* Set PCI-X DMA write workaround. */
1882 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1885 /* Conventional PCI bus: 256 bytes for read and write. */
1886 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1887 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1889 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1890 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1893 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1894 sc->bge_asicrev == BGE_ASICREV_BCM5701)
1895 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1896 BGE_PCIDMARWCTL_ASRT_ALL_BE;
1897 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1898 sc->bge_asicrev == BGE_ASICREV_BCM5704)
1899 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1900 if (BGE_IS_5717_PLUS(sc)) {
1901 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1902 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
1903 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1905 * Enable HW workaround for controllers that misinterpret
1906 * a status tag update and leave interrupts permanently
1909 if (!BGE_IS_57765_PLUS(sc) &&
1910 sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
1911 sc->bge_asicrev != BGE_ASICREV_BCM5762)
1912 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1914 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1917 * Set up general mode register.
1919 mode_ctl = bge_dma_swap_options(sc);
1920 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
1921 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
1922 /* Retain Host-2-BMC settings written by APE firmware. */
1923 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
1924 (BGE_MODECTL_BYTESWAP_B2HRX_DATA |
1925 BGE_MODECTL_WORDSWAP_B2HRX_DATA |
1926 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE);
1928 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1929 BGE_MODECTL_TX_NO_PHDR_CSUM;
1932 * BCM5701 B5 have a bug causing data corruption when using
1933 * 64-bit DMA reads, which can be terminated early and then
1934 * completed later as 32-bit accesses, in combination with
1937 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1938 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1939 mode_ctl |= BGE_MODECTL_FORCE_PCI32;
1942 * Tell the firmware the driver is running
1944 if (sc->bge_asf_mode & ASF_STACKUP)
1945 mode_ctl |= BGE_MODECTL_STACKUP;
1947 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1950 * Disable memory write invalidate. Apparently it is not supported
1951 * properly by these devices.
1953 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1955 /* Set the timer prescaler (always 66 MHz). */
1956 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1958 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1959 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1960 DELAY(40); /* XXX */
1962 /* Put PHY into ready state */
1963 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1964 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1972 bge_blockinit(struct bge_softc *sc)
1974 struct bge_rcb *rcb;
1977 uint32_t dmactl, rdmareg, val;
1981 * Initialize the memory window pointer register so that
1982 * we can access the first 32K of internal NIC RAM. This will
1983 * allow us to set up the TX send ring RCBs and the RX return
1984 * ring RCBs, plus other things which live in NIC memory.
1986 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1988 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1990 if (!(BGE_IS_5705_PLUS(sc))) {
1991 /* Configure mbuf memory pool */
1992 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1993 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1994 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1996 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1998 /* Configure DMA resource pool */
1999 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
2000 BGE_DMA_DESCRIPTORS);
2001 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
2004 /* Configure mbuf pool watermarks */
2005 if (BGE_IS_5717_PLUS(sc)) {
2006 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2007 if (if_getmtu(sc->bge_ifp) > ETHERMTU) {
2008 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
2009 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
2011 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
2012 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
2014 } else if (!BGE_IS_5705_PLUS(sc)) {
2015 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
2016 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
2017 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2018 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2019 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2020 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
2021 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
2023 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2024 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
2025 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2028 /* Configure DMA resource watermarks */
2029 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
2030 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
2032 /* Enable buffer manager */
2033 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
2035 * Change the arbitration algorithm of TXMBUF read request to
2036 * round-robin instead of priority based for BCM5719. When
2037 * TXFIFO is almost empty, RDMA will hold its request until
2038 * TXFIFO is not almost empty.
2040 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2041 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
2042 CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
2044 /* Poll for buffer manager start indication */
2045 for (i = 0; i < BGE_TIMEOUT; i++) {
2047 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
2051 if (i == BGE_TIMEOUT) {
2052 device_printf(sc->bge_dev, "buffer manager failed to start\n");
2056 /* Enable flow-through queues */
2057 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2058 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2060 /* Wait until queue initialization is complete */
2061 for (i = 0; i < BGE_TIMEOUT; i++) {
2063 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
2067 if (i == BGE_TIMEOUT) {
2068 device_printf(sc->bge_dev, "flow-through queue init failed\n");
2073 * Summary of rings supported by the controller:
2075 * Standard Receive Producer Ring
2076 * - This ring is used to feed receive buffers for "standard"
2077 * sized frames (typically 1536 bytes) to the controller.
2079 * Jumbo Receive Producer Ring
2080 * - This ring is used to feed receive buffers for jumbo sized
2081 * frames (i.e. anything bigger than the "standard" frames)
2082 * to the controller.
2084 * Mini Receive Producer Ring
2085 * - This ring is used to feed receive buffers for "mini"
2086 * sized frames to the controller.
2087 * - This feature required external memory for the controller
2088 * but was never used in a production system. Should always
2091 * Receive Return Ring
2092 * - After the controller has placed an incoming frame into a
2093 * receive buffer that buffer is moved into a receive return
2094 * ring. The driver is then responsible to passing the
2095 * buffer up to the stack. Many versions of the controller
2096 * support multiple RR rings.
2099 * - This ring is used for outgoing frames. Many versions of
2100 * the controller support multiple send rings.
2103 /* Initialize the standard receive producer ring control block. */
2104 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
2105 rcb->bge_hostaddr.bge_addr_lo =
2106 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
2107 rcb->bge_hostaddr.bge_addr_hi =
2108 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
2109 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2110 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
2111 if (BGE_IS_5717_PLUS(sc)) {
2113 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
2114 * Bits 15-2 : Maximum RX frame size
2115 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled
2118 rcb->bge_maxlen_flags =
2119 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
2120 } else if (BGE_IS_5705_PLUS(sc)) {
2122 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
2123 * Bits 15-2 : Reserved (should be 0)
2124 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
2127 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
2130 * Ring size is always XXX entries
2131 * Bits 31-16: Maximum RX frame size
2132 * Bits 15-2 : Reserved (should be 0)
2133 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
2136 rcb->bge_maxlen_flags =
2137 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
2139 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2140 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2141 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2142 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
2144 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
2145 /* Write the standard receive producer ring control block. */
2146 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
2147 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
2148 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
2149 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
2151 /* Reset the standard receive producer ring producer index. */
2152 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
2155 * Initialize the jumbo RX producer ring control
2156 * block. We set the 'ring disabled' bit in the
2157 * flags field until we're actually ready to start
2158 * using this ring (i.e. once we set the MTU
2159 * high enough to require it).
2161 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2162 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
2163 /* Get the jumbo receive producer ring RCB parameters. */
2164 rcb->bge_hostaddr.bge_addr_lo =
2165 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2166 rcb->bge_hostaddr.bge_addr_hi =
2167 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2168 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2169 sc->bge_cdata.bge_rx_jumbo_ring_map,
2170 BUS_DMASYNC_PREREAD);
2171 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
2172 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
2173 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2174 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2175 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2176 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
2178 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
2179 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
2180 rcb->bge_hostaddr.bge_addr_hi);
2181 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
2182 rcb->bge_hostaddr.bge_addr_lo);
2183 /* Program the jumbo receive producer ring RCB parameters. */
2184 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
2185 rcb->bge_maxlen_flags);
2186 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
2187 /* Reset the jumbo receive producer ring producer index. */
2188 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
2191 /* Disable the mini receive producer ring RCB. */
2192 if (BGE_IS_5700_FAMILY(sc)) {
2193 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
2194 rcb->bge_maxlen_flags =
2195 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
2196 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
2197 rcb->bge_maxlen_flags);
2198 /* Reset the mini receive producer ring producer index. */
2199 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
2202 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
2203 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2204 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
2205 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
2206 sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
2207 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
2208 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
2211 * The BD ring replenish thresholds control how often the
2212 * hardware fetches new BD's from the producer rings in host
2213 * memory. Setting the value too low on a busy system can
2214 * starve the hardware and recue the throughpout.
2216 * Set the BD ring replentish thresholds. The recommended
2217 * values are 1/8th the number of descriptors allocated to
2219 * XXX The 5754 requires a lower threshold, so it might be a
2220 * requirement of all 575x family chips. The Linux driver sets
2221 * the lower threshold for all 5705 family chips as well, but there
2222 * are reports that it might not need to be so strict.
2224 * XXX Linux does some extra fiddling here for the 5906 parts as
2227 if (BGE_IS_5705_PLUS(sc))
2230 val = BGE_STD_RX_RING_CNT / 8;
2231 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
2232 if (BGE_IS_JUMBO_CAPABLE(sc))
2233 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
2234 BGE_JUMBO_RX_RING_CNT/8);
2235 if (BGE_IS_5717_PLUS(sc)) {
2236 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
2237 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
2241 * Disable all send rings by setting the 'ring disabled' bit
2242 * in the flags field of all the TX send ring control blocks,
2243 * located in NIC memory.
2245 if (!BGE_IS_5705_PLUS(sc))
2246 /* 5700 to 5704 had 16 send rings. */
2247 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
2248 else if (BGE_IS_57765_PLUS(sc) ||
2249 sc->bge_asicrev == BGE_ASICREV_BCM5762)
2251 else if (BGE_IS_5717_PLUS(sc))
2255 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2256 for (i = 0; i < limit; i++) {
2257 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2258 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
2259 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2260 vrcb += sizeof(struct bge_rcb);
2263 /* Configure send ring RCB 0 (we use only the first ring) */
2264 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2265 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
2266 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2267 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2268 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2269 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2270 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2271 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
2273 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
2274 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
2275 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2276 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
2279 * Disable all receive return rings by setting the
2280 * 'ring diabled' bit in the flags field of all the receive
2281 * return ring control blocks, located in NIC memory.
2283 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2284 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2285 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2286 /* Should be 17, use 16 until we get an SRAM map. */
2288 } else if (!BGE_IS_5705_PLUS(sc))
2289 limit = BGE_RX_RINGS_MAX;
2290 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2291 sc->bge_asicrev == BGE_ASICREV_BCM5762 ||
2292 BGE_IS_57765_PLUS(sc))
2296 /* Disable all receive return rings. */
2297 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2298 for (i = 0; i < limit; i++) {
2299 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
2300 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
2301 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2302 BGE_RCB_FLAG_RING_DISABLED);
2303 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2304 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
2305 (i * (sizeof(uint64_t))), 0);
2306 vrcb += sizeof(struct bge_rcb);
2310 * Set up receive return ring 0. Note that the NIC address
2311 * for RX return rings is 0x0. The return rings live entirely
2312 * within the host, so the nicaddr field in the RCB isn't used.
2314 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2315 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
2316 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2317 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2318 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2319 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2320 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
2322 /* Set random backoff seed for TX */
2323 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
2324 (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
2325 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
2326 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) &
2327 BGE_TX_BACKOFF_SEED_MASK);
2329 /* Set inter-packet gap */
2331 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2332 sc->bge_asicrev == BGE_ASICREV_BCM5762)
2333 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
2334 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
2335 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
2338 * Specify which ring to use for packets that don't match
2341 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
2344 * Configure number of RX lists. One interrupt distribution
2345 * list, sixteen active lists, one bad frames class.
2347 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
2349 /* Inialize RX list placement stats mask. */
2350 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
2351 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
2353 /* Disable host coalescing until we get it set up */
2354 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
2356 /* Poll to make sure it's shut down. */
2357 for (i = 0; i < BGE_TIMEOUT; i++) {
2359 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
2363 if (i == BGE_TIMEOUT) {
2364 device_printf(sc->bge_dev,
2365 "host coalescing engine failed to idle\n");
2369 /* Set up host coalescing defaults */
2370 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
2371 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
2372 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
2373 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
2374 if (!(BGE_IS_5705_PLUS(sc))) {
2375 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
2376 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
2378 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
2379 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
2381 /* Set up address of statistics block */
2382 if (!(BGE_IS_5705_PLUS(sc))) {
2383 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
2384 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
2385 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
2386 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
2387 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
2388 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
2389 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
2392 /* Set up address of status block */
2393 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
2394 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
2395 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
2396 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
2398 /* Set up status block size. */
2399 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2400 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
2401 val = BGE_STATBLKSZ_FULL;
2402 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2404 val = BGE_STATBLKSZ_32BYTE;
2405 bzero(sc->bge_ldata.bge_status_block, 32);
2407 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2408 sc->bge_cdata.bge_status_map,
2409 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2411 /* Turn on host coalescing state machine */
2412 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2414 /* Turn on RX BD completion state machine and enable attentions */
2415 CSR_WRITE_4(sc, BGE_RBDC_MODE,
2416 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
2418 /* Turn on RX list placement state machine */
2419 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2421 /* Turn on RX list selector state machine. */
2422 if (!(BGE_IS_5705_PLUS(sc)))
2423 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2425 /* Turn on DMA, clear stats. */
2426 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
2427 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
2428 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
2429 BGE_MACMODE_FRMHDR_DMA_ENB;
2431 if (sc->bge_flags & BGE_FLAG_TBI)
2432 val |= BGE_PORTMODE_TBI;
2433 else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
2434 val |= BGE_PORTMODE_GMII;
2436 val |= BGE_PORTMODE_MII;
2438 /* Allow APE to send/receive frames. */
2439 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
2440 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
2442 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
2445 /* Set misc. local control, enable interrupts on attentions */
2446 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2449 /* Assert GPIO pins for PHY reset */
2450 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
2451 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
2452 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
2453 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
2456 /* Turn on DMA completion state machine */
2457 if (!(BGE_IS_5705_PLUS(sc)))
2458 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2460 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
2462 /* Enable host coalescing bug fix. */
2463 if (BGE_IS_5755_PLUS(sc))
2464 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
2466 /* Request larger DMA burst size to get better performance. */
2467 if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
2468 val |= BGE_WDMAMODE_BURST_ALL_DATA;
2470 /* Turn on write DMA state machine */
2471 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
2474 /* Turn on read DMA state machine */
2475 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
2477 if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
2478 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
2480 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2481 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2482 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2483 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
2484 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
2485 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
2486 if (sc->bge_flags & BGE_FLAG_PCIE)
2487 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2488 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2489 val |= BGE_RDMAMODE_TSO4_ENABLE;
2490 if (sc->bge_flags & BGE_FLAG_TSO3 ||
2491 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2492 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2493 val |= BGE_RDMAMODE_TSO6_ENABLE;
2496 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2497 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2498 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
2499 BGE_RDMAMODE_H2BNC_VLAN_DET;
2501 * Allow multiple outstanding read requests from
2502 * non-LSO read DMA engine.
2504 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
2507 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2508 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2509 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2510 sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2511 BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) {
2512 if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
2513 rdmareg = BGE_RDMA_RSRVCTRL_REG2;
2515 rdmareg = BGE_RDMA_RSRVCTRL;
2516 dmactl = CSR_READ_4(sc, rdmareg);
2518 * Adjust tx margin to prevent TX data corruption and
2519 * fix internal FIFO overflow.
2521 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 ||
2522 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2523 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2524 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2525 BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2526 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2527 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2528 BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2531 * Enable fix for read DMA FIFO overruns.
2532 * The fix is to limit the number of RX BDs
2533 * the hardware would fetch at a fime.
2535 CSR_WRITE_4(sc, rdmareg, dmactl |
2536 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2539 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2540 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2541 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2542 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2543 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2544 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2546 * Allow 4KB burst length reads for non-LSO frames.
2547 * Enable 512B burst length reads for buffer descriptors.
2549 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2550 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2551 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
2552 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2553 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2554 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2,
2555 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |
2556 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2557 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2560 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2563 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
2564 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) {
2565 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);
2566 if ((val & 0xFFFF) > BGE_FRAMELEN)
2568 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN)
2571 if (i != BGE_NUM_RDMA_CHANNELS / 2) {
2572 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
2573 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2574 val |= BGE_RDMA_TX_LENGTH_WA_5719;
2576 val |= BGE_RDMA_TX_LENGTH_WA_5720;
2577 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
2581 /* Turn on RX data completion state machine */
2582 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2584 /* Turn on RX BD initiator state machine */
2585 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2587 /* Turn on RX data and RX BD initiator state machine */
2588 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2590 /* Turn on Mbuf cluster free state machine */
2591 if (!(BGE_IS_5705_PLUS(sc)))
2592 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2594 /* Turn on send BD completion state machine */
2595 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2597 /* Turn on send data completion state machine */
2598 val = BGE_SDCMODE_ENABLE;
2599 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2600 val |= BGE_SDCMODE_CDELAY;
2601 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2603 /* Turn on send data initiator state machine */
2604 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2605 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2606 BGE_SDIMODE_HW_LSO_PRE_DMA);
2608 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2610 /* Turn on send BD initiator state machine */
2611 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2613 /* Turn on send BD selector state machine */
2614 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2616 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
2617 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
2618 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
2620 /* ack/clear link change events */
2621 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2622 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2623 BGE_MACSTAT_LINK_CHANGED);
2624 CSR_WRITE_4(sc, BGE_MI_STS, 0);
2627 * Enable attention when the link has changed state for
2628 * devices that use auto polling.
2630 if (sc->bge_flags & BGE_FLAG_TBI) {
2631 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
2633 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2634 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
2637 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2638 sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
2639 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2640 BGE_EVTENB_MI_INTERRUPT);
2644 * Clear any pending link state attention.
2645 * Otherwise some link state change events may be lost until attention
2646 * is cleared by bge_intr() -> bge_link_upd() sequence.
2647 * It's not necessary on newer BCM chips - perhaps enabling link
2648 * state change attentions implies clearing pending attention.
2650 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2651 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2652 BGE_MACSTAT_LINK_CHANGED);
2654 /* Enable link state change attentions. */
2655 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2660 static const struct bge_revision *
2661 bge_lookup_rev(uint32_t chipid)
2663 const struct bge_revision *br;
2665 for (br = bge_revisions; br->br_name != NULL; br++) {
2666 if (br->br_chipid == chipid)
2670 for (br = bge_majorrevs; br->br_name != NULL; br++) {
2671 if (br->br_chipid == BGE_ASICREV(chipid))
2678 static const struct bge_vendor *
2679 bge_lookup_vendor(uint16_t vid)
2681 const struct bge_vendor *v;
2683 for (v = bge_vendors; v->v_name != NULL; v++)
2691 bge_chipid(device_t dev)
2695 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2696 BGE_PCIMISCCTL_ASICREV_SHIFT;
2697 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
2699 * Find the ASCI revision. Different chips use different
2702 switch (pci_get_device(dev)) {
2703 case BCOM_DEVICEID_BCM5717C:
2704 /* 5717 C0 seems to belong to 5720 line. */
2705 id = BGE_CHIPID_BCM5720_A0;
2707 case BCOM_DEVICEID_BCM5717:
2708 case BCOM_DEVICEID_BCM5718:
2709 case BCOM_DEVICEID_BCM5719:
2710 case BCOM_DEVICEID_BCM5720:
2711 case BCOM_DEVICEID_BCM5725:
2712 case BCOM_DEVICEID_BCM5727:
2713 case BCOM_DEVICEID_BCM5762:
2714 case BCOM_DEVICEID_BCM57764:
2715 case BCOM_DEVICEID_BCM57767:
2716 case BCOM_DEVICEID_BCM57787:
2717 id = pci_read_config(dev,
2718 BGE_PCI_GEN2_PRODID_ASICREV, 4);
2720 case BCOM_DEVICEID_BCM57761:
2721 case BCOM_DEVICEID_BCM57762:
2722 case BCOM_DEVICEID_BCM57765:
2723 case BCOM_DEVICEID_BCM57766:
2724 case BCOM_DEVICEID_BCM57781:
2725 case BCOM_DEVICEID_BCM57782:
2726 case BCOM_DEVICEID_BCM57785:
2727 case BCOM_DEVICEID_BCM57786:
2728 case BCOM_DEVICEID_BCM57791:
2729 case BCOM_DEVICEID_BCM57795:
2730 id = pci_read_config(dev,
2731 BGE_PCI_GEN15_PRODID_ASICREV, 4);
2734 id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
2741 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
2742 * against our list and return its name if we find a match.
2744 * Note that since the Broadcom controller contains VPD support, we
2745 * try to get the device name string from the controller itself instead
2746 * of the compiled-in string. It guarantees we'll always announce the
2747 * right product name. We fall back to the compiled-in string when
2748 * VPD is unavailable or corrupt.
2751 bge_probe(device_t dev)
2755 const struct bge_revision *br;
2757 struct bge_softc *sc;
2758 const struct bge_type *t = bge_devs;
2759 const struct bge_vendor *v;
2763 sc = device_get_softc(dev);
2765 vid = pci_get_vendor(dev);
2766 did = pci_get_device(dev);
2767 while(t->bge_vid != 0) {
2768 if ((vid == t->bge_vid) && (did == t->bge_did)) {
2769 id = bge_chipid(dev);
2770 br = bge_lookup_rev(id);
2771 if (bge_has_eaddr(sc) &&
2772 pci_get_vpd_ident(dev, &pname) == 0)
2773 snprintf(model, sizeof(model), "%s", pname);
2775 v = bge_lookup_vendor(vid);
2776 snprintf(model, sizeof(model), "%s %s",
2777 v != NULL ? v->v_name : "Unknown",
2778 br != NULL ? br->br_name :
2779 "NetXtreme/NetLink Ethernet Controller");
2781 snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x",
2782 model, br != NULL ? "" : "unknown ", id);
2783 device_set_desc_copy(dev, buf);
2784 return (BUS_PROBE_DEFAULT);
2793 bge_dma_free(struct bge_softc *sc)
2797 /* Destroy DMA maps for RX buffers. */
2798 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2799 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2800 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2801 sc->bge_cdata.bge_rx_std_dmamap[i]);
2803 if (sc->bge_cdata.bge_rx_std_sparemap)
2804 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2805 sc->bge_cdata.bge_rx_std_sparemap);
2807 /* Destroy DMA maps for jumbo RX buffers. */
2808 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2809 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2810 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2811 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2813 if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2814 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2815 sc->bge_cdata.bge_rx_jumbo_sparemap);
2817 /* Destroy DMA maps for TX buffers. */
2818 for (i = 0; i < BGE_TX_RING_CNT; i++) {
2819 if (sc->bge_cdata.bge_tx_dmamap[i])
2820 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2821 sc->bge_cdata.bge_tx_dmamap[i]);
2824 if (sc->bge_cdata.bge_rx_mtag)
2825 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2826 if (sc->bge_cdata.bge_mtag_jumbo)
2827 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
2828 if (sc->bge_cdata.bge_tx_mtag)
2829 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2831 /* Destroy standard RX ring. */
2832 if (sc->bge_ldata.bge_rx_std_ring_paddr)
2833 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2834 sc->bge_cdata.bge_rx_std_ring_map);
2835 if (sc->bge_ldata.bge_rx_std_ring)
2836 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2837 sc->bge_ldata.bge_rx_std_ring,
2838 sc->bge_cdata.bge_rx_std_ring_map);
2840 if (sc->bge_cdata.bge_rx_std_ring_tag)
2841 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2843 /* Destroy jumbo RX ring. */
2844 if (sc->bge_ldata.bge_rx_jumbo_ring_paddr)
2845 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2846 sc->bge_cdata.bge_rx_jumbo_ring_map);
2848 if (sc->bge_ldata.bge_rx_jumbo_ring)
2849 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2850 sc->bge_ldata.bge_rx_jumbo_ring,
2851 sc->bge_cdata.bge_rx_jumbo_ring_map);
2853 if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2854 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2856 /* Destroy RX return ring. */
2857 if (sc->bge_ldata.bge_rx_return_ring_paddr)
2858 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2859 sc->bge_cdata.bge_rx_return_ring_map);
2861 if (sc->bge_ldata.bge_rx_return_ring)
2862 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2863 sc->bge_ldata.bge_rx_return_ring,
2864 sc->bge_cdata.bge_rx_return_ring_map);
2866 if (sc->bge_cdata.bge_rx_return_ring_tag)
2867 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2869 /* Destroy TX ring. */
2870 if (sc->bge_ldata.bge_tx_ring_paddr)
2871 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2872 sc->bge_cdata.bge_tx_ring_map);
2874 if (sc->bge_ldata.bge_tx_ring)
2875 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2876 sc->bge_ldata.bge_tx_ring,
2877 sc->bge_cdata.bge_tx_ring_map);
2879 if (sc->bge_cdata.bge_tx_ring_tag)
2880 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2882 /* Destroy status block. */
2883 if (sc->bge_ldata.bge_status_block_paddr)
2884 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2885 sc->bge_cdata.bge_status_map);
2887 if (sc->bge_ldata.bge_status_block)
2888 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2889 sc->bge_ldata.bge_status_block,
2890 sc->bge_cdata.bge_status_map);
2892 if (sc->bge_cdata.bge_status_tag)
2893 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2895 /* Destroy statistics block. */
2896 if (sc->bge_ldata.bge_stats_paddr)
2897 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2898 sc->bge_cdata.bge_stats_map);
2900 if (sc->bge_ldata.bge_stats)
2901 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2902 sc->bge_ldata.bge_stats,
2903 sc->bge_cdata.bge_stats_map);
2905 if (sc->bge_cdata.bge_stats_tag)
2906 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2908 if (sc->bge_cdata.bge_buffer_tag)
2909 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
2911 /* Destroy the parent tag. */
2912 if (sc->bge_cdata.bge_parent_tag)
2913 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2917 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
2918 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
2919 bus_addr_t *paddr, const char *msg)
2921 struct bge_dmamap_arg ctx;
2923 bus_size_t ring_end;
2926 lowaddr = BUS_SPACE_MAXADDR;
2928 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2929 alignment, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2930 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
2932 device_printf(sc->bge_dev,
2933 "could not create %s dma tag\n", msg);
2936 /* Allocate DMA'able memory for ring. */
2937 error = bus_dmamem_alloc(*tag, (void **)ring,
2938 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
2940 device_printf(sc->bge_dev,
2941 "could not allocate DMA'able memory for %s\n", msg);
2944 /* Load the address of the ring. */
2945 ctx.bge_busaddr = 0;
2946 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr,
2947 &ctx, BUS_DMA_NOWAIT);
2949 device_printf(sc->bge_dev,
2950 "could not load DMA'able memory for %s\n", msg);
2953 *paddr = ctx.bge_busaddr;
2954 ring_end = *paddr + maxsize;
2955 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0 &&
2956 BGE_ADDR_HI(*paddr) != BGE_ADDR_HI(ring_end)) {
2958 * 4GB boundary crossed. Limit maximum allowable DMA
2959 * address space to 32bit and try again.
2961 bus_dmamap_unload(*tag, *map);
2962 bus_dmamem_free(*tag, *ring, *map);
2963 bus_dma_tag_destroy(*tag);
2965 device_printf(sc->bge_dev, "4GB boundary crossed, "
2966 "limit DMA address space to 32bit for %s\n", msg);
2970 lowaddr = BUS_SPACE_MAXADDR_32BIT;
2977 bge_dma_alloc(struct bge_softc *sc)
2980 bus_size_t boundary, sbsz, rxmaxsegsz, txsegsz, txmaxsegsz;
2983 lowaddr = BUS_SPACE_MAXADDR;
2984 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2985 lowaddr = BGE_DMA_MAXADDR;
2987 * Allocate the parent bus DMA tag appropriate for PCI.
2989 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2990 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2991 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2992 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2994 device_printf(sc->bge_dev,
2995 "could not allocate parent dma tag\n");
2999 /* Create tag for standard RX ring. */
3000 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
3001 &sc->bge_cdata.bge_rx_std_ring_tag,
3002 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
3003 &sc->bge_cdata.bge_rx_std_ring_map,
3004 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
3008 /* Create tag for RX return ring. */
3009 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
3010 &sc->bge_cdata.bge_rx_return_ring_tag,
3011 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
3012 &sc->bge_cdata.bge_rx_return_ring_map,
3013 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
3017 /* Create tag for TX ring. */
3018 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
3019 &sc->bge_cdata.bge_tx_ring_tag,
3020 (uint8_t **)&sc->bge_ldata.bge_tx_ring,
3021 &sc->bge_cdata.bge_tx_ring_map,
3022 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
3027 * Create tag for status block.
3028 * Because we only use single Tx/Rx/Rx return ring, use
3029 * minimum status block size except BCM5700 AX/BX which
3030 * seems to want to see full status block size regardless
3031 * of configured number of ring.
3033 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3034 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
3035 sbsz = BGE_STATUS_BLK_SZ;
3038 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
3039 &sc->bge_cdata.bge_status_tag,
3040 (uint8_t **)&sc->bge_ldata.bge_status_block,
3041 &sc->bge_cdata.bge_status_map,
3042 &sc->bge_ldata.bge_status_block_paddr, "status block");
3046 /* Create tag for statistics block. */
3047 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
3048 &sc->bge_cdata.bge_stats_tag,
3049 (uint8_t **)&sc->bge_ldata.bge_stats,
3050 &sc->bge_cdata.bge_stats_map,
3051 &sc->bge_ldata.bge_stats_paddr, "statistics block");
3055 /* Create tag for jumbo RX ring. */
3056 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3057 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
3058 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
3059 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
3060 &sc->bge_cdata.bge_rx_jumbo_ring_map,
3061 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
3066 /* Create parent tag for buffers. */
3068 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
3069 boundary = BGE_DMA_BNDRY;
3072 * watchdog timeout issue was observed on BCM5704 which
3073 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge).
3074 * Both limiting DMA address space to 32bits and flushing
3075 * mailbox write seem to address the issue.
3077 if (sc->bge_pcixcap != 0)
3078 lowaddr = BUS_SPACE_MAXADDR_32BIT;
3080 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
3081 1, boundary, lowaddr, BUS_SPACE_MAXADDR, NULL,
3082 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3083 0, NULL, NULL, &sc->bge_cdata.bge_buffer_tag);
3085 device_printf(sc->bge_dev,
3086 "could not allocate buffer dma tag\n");
3089 /* Create tag for Tx mbufs. */
3090 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
3091 txsegsz = BGE_TSOSEG_SZ;
3092 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
3095 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
3097 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
3098 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
3099 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
3100 &sc->bge_cdata.bge_tx_mtag);
3103 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
3107 /* Create tag for Rx mbufs. */
3108 if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
3109 rxmaxsegsz = MJUM9BYTES;
3111 rxmaxsegsz = MCLBYTES;
3112 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
3113 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1,
3114 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
3117 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
3121 /* Create DMA maps for RX buffers. */
3122 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3123 &sc->bge_cdata.bge_rx_std_sparemap);
3125 device_printf(sc->bge_dev,
3126 "can't create spare DMA map for RX\n");
3129 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3130 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3131 &sc->bge_cdata.bge_rx_std_dmamap[i]);
3133 device_printf(sc->bge_dev,
3134 "can't create DMA map for RX\n");
3139 /* Create DMA maps for TX buffers. */
3140 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3141 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
3142 &sc->bge_cdata.bge_tx_dmamap[i]);
3144 device_printf(sc->bge_dev,
3145 "can't create DMA map for TX\n");
3150 /* Create tags for jumbo RX buffers. */
3151 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3152 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
3153 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
3154 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
3155 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
3157 device_printf(sc->bge_dev,
3158 "could not allocate jumbo dma tag\n");
3161 /* Create DMA maps for jumbo RX buffers. */
3162 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3163 0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
3165 device_printf(sc->bge_dev,
3166 "can't create spare DMA map for jumbo RX\n");
3169 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
3170 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3171 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
3173 device_printf(sc->bge_dev,
3174 "can't create DMA map for jumbo RX\n");
3184 * Return true if this device has more than one port.
3187 bge_has_multiple_ports(struct bge_softc *sc)
3189 device_t dev = sc->bge_dev;
3190 u_int b, d, f, fscan, s;
3192 d = pci_get_domain(dev);
3193 b = pci_get_bus(dev);
3194 s = pci_get_slot(dev);
3195 f = pci_get_function(dev);
3196 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
3197 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
3203 * Return true if MSI can be used with this device.
3206 bge_can_use_msi(struct bge_softc *sc)
3208 int can_use_msi = 0;
3210 if (sc->bge_msi == 0)
3213 /* Disable MSI for polling(4). */
3214 #ifdef DEVICE_POLLING
3217 switch (sc->bge_asicrev) {
3218 case BGE_ASICREV_BCM5714_A0:
3219 case BGE_ASICREV_BCM5714:
3221 * Apparently, MSI doesn't work when these chips are
3222 * configured in single-port mode.
3224 if (bge_has_multiple_ports(sc))
3227 case BGE_ASICREV_BCM5750:
3228 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
3229 sc->bge_chiprev != BGE_CHIPREV_5750_BX)
3232 case BGE_ASICREV_BCM5784:
3234 * Prevent infinite "watchdog timeout" errors
3235 * in some MacBook Pro and make it work out-of-the-box.
3237 if (sc->bge_chiprev == BGE_CHIPREV_5784_AX)
3241 if (BGE_IS_575X_PLUS(sc))
3244 return (can_use_msi);
3248 bge_mbox_reorder(struct bge_softc *sc)
3250 /* Lists of PCI bridges that are known to reorder mailbox writes. */
3251 static const struct mbox_reorder {
3252 const uint16_t vendor;
3253 const uint16_t device;
3255 } mbox_reorder_lists[] = {
3256 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" },
3258 devclass_t pci, pcib;
3262 pci = devclass_find("pci");
3263 pcib = devclass_find("pcib");
3265 bus = device_get_parent(dev);
3267 dev = device_get_parent(bus);
3268 bus = device_get_parent(dev);
3269 if (device_get_devclass(dev) != pcib)
3271 if (device_get_devclass(bus) != pci)
3273 for (i = 0; i < nitems(mbox_reorder_lists); i++) {
3274 if (pci_get_vendor(dev) ==
3275 mbox_reorder_lists[i].vendor &&
3276 pci_get_device(dev) ==
3277 mbox_reorder_lists[i].device) {
3278 device_printf(sc->bge_dev,
3279 "enabling MBOX workaround for %s\n",
3280 mbox_reorder_lists[i].desc);
3289 bge_devinfo(struct bge_softc *sc)
3293 device_printf(sc->bge_dev,
3294 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ",
3295 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev);
3296 if (sc->bge_flags & BGE_FLAG_PCIE)
3298 else if (sc->bge_flags & BGE_FLAG_PCIX) {
3300 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3301 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE)
3304 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
3323 printf("%u MHz\n", clk);
3325 if (sc->bge_pcixcap != 0)
3326 printf("PCI on PCI-X ");
3329 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3330 if (cfg & BGE_PCISTATE_PCI_BUSSPEED)
3334 if (cfg & BGE_PCISTATE_32BIT_BUS)
3335 printf("%u MHz; 32bit\n", clk);
3337 printf("%u MHz; 64bit\n", clk);
3342 bge_attach(device_t dev)
3345 struct bge_softc *sc;
3346 uint32_t hwcfg = 0, misccfg, pcistate;
3347 u_char eaddr[ETHER_ADDR_LEN];
3348 int capmask, error, reg, rid, trys;
3350 sc = device_get_softc(dev);
3353 BGE_LOCK_INIT(sc, device_get_nameunit(dev));
3354 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
3355 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
3357 pci_enable_busmaster(dev);
3360 * Allocate control/status registers.
3363 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3366 if (sc->bge_res == NULL) {
3367 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n");
3372 /* Save various chip information. */
3373 sc->bge_func_addr = pci_get_function(dev);
3374 sc->bge_chipid = bge_chipid(dev);
3375 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
3376 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
3378 /* Set default PHY address. */
3379 sc->bge_phy_addr = 1;
3381 * PHY address mapping for various devices.
3383 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
3384 * ---------+-------+-------+-------+-------+
3385 * BCM57XX | 1 | X | X | X |
3386 * BCM5704 | 1 | X | 1 | X |
3387 * BCM5717 | 1 | 8 | 2 | 9 |
3388 * BCM5719 | 1 | 8 | 2 | 9 |
3389 * BCM5720 | 1 | 8 | 2 | 9 |
3391 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr |
3392 * ---------+-------+-------+-------+-------+
3393 * BCM57XX | X | X | X | X |
3394 * BCM5704 | X | X | X | X |
3395 * BCM5717 | X | X | X | X |
3396 * BCM5719 | 3 | 10 | 4 | 11 |
3397 * BCM5720 | X | X | X | X |
3399 * Other addresses may respond but they are not
3400 * IEEE compliant PHYs and should be ignored.
3402 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
3403 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3404 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3405 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) {
3406 if (CSR_READ_4(sc, BGE_SGDIG_STS) &
3407 BGE_SGDIGSTS_IS_SERDES)
3408 sc->bge_phy_addr = sc->bge_func_addr + 8;
3410 sc->bge_phy_addr = sc->bge_func_addr + 1;
3412 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
3413 BGE_CPMU_PHY_STRAP_IS_SERDES)
3414 sc->bge_phy_addr = sc->bge_func_addr + 8;
3416 sc->bge_phy_addr = sc->bge_func_addr + 1;
3420 if (bge_has_eaddr(sc))
3421 sc->bge_flags |= BGE_FLAG_EADDR;
3423 /* Save chipset family. */
3424 switch (sc->bge_asicrev) {
3425 case BGE_ASICREV_BCM5762:
3426 case BGE_ASICREV_BCM57765:
3427 case BGE_ASICREV_BCM57766:
3428 sc->bge_flags |= BGE_FLAG_57765_PLUS;
3430 case BGE_ASICREV_BCM5717:
3431 case BGE_ASICREV_BCM5719:
3432 case BGE_ASICREV_BCM5720:
3433 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
3434 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
3435 BGE_FLAG_JUMBO_FRAME;
3436 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3437 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3439 * Enable work around for DMA engine miscalculation
3440 * of TXMBUF available space.
3442 sc->bge_flags |= BGE_FLAG_RDMA_BUG;
3443 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3444 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3445 /* Jumbo frame on BCM5719 A0 does not work. */
3446 sc->bge_flags &= ~BGE_FLAG_JUMBO;
3450 case BGE_ASICREV_BCM5755:
3451 case BGE_ASICREV_BCM5761:
3452 case BGE_ASICREV_BCM5784:
3453 case BGE_ASICREV_BCM5785:
3454 case BGE_ASICREV_BCM5787:
3455 case BGE_ASICREV_BCM57780:
3456 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
3459 case BGE_ASICREV_BCM5700:
3460 case BGE_ASICREV_BCM5701:
3461 case BGE_ASICREV_BCM5703:
3462 case BGE_ASICREV_BCM5704:
3463 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
3465 case BGE_ASICREV_BCM5714_A0:
3466 case BGE_ASICREV_BCM5780:
3467 case BGE_ASICREV_BCM5714:
3468 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
3470 case BGE_ASICREV_BCM5750:
3471 case BGE_ASICREV_BCM5752:
3472 case BGE_ASICREV_BCM5906:
3473 sc->bge_flags |= BGE_FLAG_575X_PLUS;
3475 case BGE_ASICREV_BCM5705:
3476 sc->bge_flags |= BGE_FLAG_5705_PLUS;
3480 /* Identify chips with APE processor. */
3481 switch (sc->bge_asicrev) {
3482 case BGE_ASICREV_BCM5717:
3483 case BGE_ASICREV_BCM5719:
3484 case BGE_ASICREV_BCM5720:
3485 case BGE_ASICREV_BCM5761:
3486 case BGE_ASICREV_BCM5762:
3487 sc->bge_flags |= BGE_FLAG_APE;
3491 /* Chips with APE need BAR2 access for APE registers/memory. */
3492 if ((sc->bge_flags & BGE_FLAG_APE) != 0) {
3494 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3496 if (sc->bge_res2 == NULL) {
3497 device_printf (sc->bge_dev,
3498 "couldn't map BAR2 memory\n");
3503 /* Enable APE register/memory access by host driver. */
3504 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3505 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
3506 BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
3507 BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
3508 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4);
3510 bge_ape_lock_init(sc);
3511 bge_ape_read_fw_ver(sc);
3514 /* Add SYSCTLs, requires the chipset family to be set. */
3515 bge_add_sysctls(sc);
3517 /* Identify the chips that use an CPMU. */
3518 if (BGE_IS_5717_PLUS(sc) ||
3519 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3520 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3521 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
3522 sc->bge_asicrev == BGE_ASICREV_BCM57780)
3523 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
3524 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
3525 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
3527 sc->bge_mi_mode = BGE_MIMODE_BASE;
3528 /* Enable auto polling for BCM570[0-5]. */
3529 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
3530 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
3533 * All Broadcom controllers have 4GB boundary DMA bug.
3534 * Whenever an address crosses a multiple of the 4GB boundary
3535 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3536 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3537 * state machine will lockup and cause the device to hang.
3539 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
3541 /* BCM5755 or higher and BCM5906 have short DMA bug. */
3542 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3543 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
3546 * BCM5719 cannot handle DMA requests for DMA segments that
3547 * have larger than 4KB in size. However the maximum DMA
3548 * segment size created in DMA tag is 4KB for TSO, so we
3549 * wouldn't encounter the issue here.
3551 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
3552 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG;
3554 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3555 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
3556 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
3557 misccfg == BGE_MISCCFG_BOARD_ID_5788M)
3558 sc->bge_flags |= BGE_FLAG_5788;
3561 capmask = BMSR_DEFCAPMASK;
3562 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
3563 (misccfg == 0x4000 || misccfg == 0x8000)) ||
3564 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3565 pci_get_vendor(dev) == BCOM_VENDORID &&
3566 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 ||
3567 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 ||
3568 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) ||
3569 (pci_get_vendor(dev) == BCOM_VENDORID &&
3570 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F ||
3571 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F ||
3572 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) ||
3573 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 ||
3574 pci_get_device(dev) == BCOM_DEVICEID_BCM57791 ||
3575 pci_get_device(dev) == BCOM_DEVICEID_BCM57795 ||
3576 sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3577 /* These chips are 10/100 only. */
3578 capmask &= ~BMSR_EXTSTAT;
3579 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3583 * Some controllers seem to require a special firmware to use
3584 * TSO. But the firmware is not available to FreeBSD and Linux
3585 * claims that the TSO performed by the firmware is slower than
3586 * hardware based TSO. Moreover the firmware based TSO has one
3587 * known bug which can't handle TSO if Ethernet header + IP/TCP
3588 * header is greater than 80 bytes. A workaround for the TSO
3589 * bug exist but it seems it's too expensive than not using
3590 * TSO at all. Some hardwares also have the TSO bug so limit
3591 * the TSO to the controllers that are not affected TSO issues
3592 * (e.g. 5755 or higher).
3594 if (BGE_IS_5717_PLUS(sc)) {
3595 /* BCM5717 requires different TSO configuration. */
3596 sc->bge_flags |= BGE_FLAG_TSO3;
3597 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3598 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3599 /* TSO on BCM5719 A0 does not work. */
3600 sc->bge_flags &= ~BGE_FLAG_TSO3;
3602 } else if (BGE_IS_5755_PLUS(sc)) {
3604 * BCM5754 and BCM5787 shares the same ASIC id so
3605 * explicit device id check is required.
3606 * Due to unknown reason TSO does not work on BCM5755M.
3608 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
3609 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
3610 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
3611 sc->bge_flags |= BGE_FLAG_TSO;
3615 * Check if this is a PCI-X or PCI Express device.
3617 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
3619 * Found a PCI Express capabilities register, this
3620 * must be a PCI Express device.
3622 sc->bge_flags |= BGE_FLAG_PCIE;
3623 sc->bge_expcap = reg;
3624 /* Extract supported maximum payload size. */
3625 sc->bge_mps = pci_read_config(dev, sc->bge_expcap +
3626 PCIER_DEVICE_CAP, 2);
3627 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD);
3628 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3629 sc->bge_asicrev == BGE_ASICREV_BCM5720)
3630 sc->bge_expmrq = 2048;
3632 sc->bge_expmrq = 4096;
3633 pci_set_max_read_req(dev, sc->bge_expmrq);
3636 * Check if the device is in PCI-X Mode.
3637 * (This bit is not valid on PCI Express controllers.)
3639 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0)
3640 sc->bge_pcixcap = reg;
3641 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
3642 BGE_PCISTATE_PCI_BUSMODE) == 0)
3643 sc->bge_flags |= BGE_FLAG_PCIX;
3647 * The 40bit DMA bug applies to the 5714/5715 controllers and is
3648 * not actually a MAC controller bug but an issue with the embedded
3649 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
3651 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
3652 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
3654 * Some PCI-X bridges are known to trigger write reordering to
3655 * the mailbox registers. Typical phenomena is watchdog timeouts
3656 * caused by out-of-order TX completions. Enable workaround for
3657 * PCI-X devices that live behind these bridges.
3658 * Note, PCI-X controllers can run in PCI mode so we can't use
3659 * BGE_FLAG_PCIX flag to detect PCI-X controllers.
3661 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0)
3662 sc->bge_flags |= BGE_FLAG_MBOX_REORDER;
3664 * Allocate the interrupt, using MSI if possible. These devices
3665 * support 8 MSI messages, but only the first one is used in
3669 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) {
3670 sc->bge_msicap = reg;
3672 if (bge_can_use_msi(sc) && pci_alloc_msi(dev, ®) == 0) {
3674 sc->bge_flags |= BGE_FLAG_MSI;
3679 * All controllers except BCM5700 supports tagged status but
3680 * we use tagged status only for MSI case on BCM5717. Otherwise
3681 * MSI on BCM5717 does not work.
3683 #ifndef DEVICE_POLLING
3684 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
3685 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
3688 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3689 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
3691 if (sc->bge_irq == NULL) {
3692 device_printf(sc->bge_dev, "couldn't map interrupt\n");
3699 sc->bge_asf_mode = 0;
3700 /* No ASF if APE present. */
3701 if ((sc->bge_flags & BGE_FLAG_APE) == 0) {
3702 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3703 BGE_SRAM_DATA_SIG_MAGIC)) {
3704 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
3706 sc->bge_asf_mode |= ASF_ENABLE;
3707 sc->bge_asf_mode |= ASF_STACKUP;
3708 if (BGE_IS_575X_PLUS(sc))
3709 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3715 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
3716 if (bge_reset(sc)) {
3717 device_printf(sc->bge_dev, "chip reset failed\n");
3722 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
3723 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
3725 if (bge_chipinit(sc)) {
3726 device_printf(sc->bge_dev, "chip initialization failed\n");
3731 error = bge_get_eaddr(sc, eaddr);
3733 device_printf(sc->bge_dev,
3734 "failed to read station address\n");
3739 /* 5705 limits RX return ring to 512 entries. */
3740 if (BGE_IS_5717_PLUS(sc))
3741 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3742 else if (BGE_IS_5705_PLUS(sc))
3743 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3745 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3747 if (bge_dma_alloc(sc)) {
3748 device_printf(sc->bge_dev,
3749 "failed to allocate DMA resources\n");
3754 /* Set default tuneable values. */
3755 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3756 sc->bge_rx_coal_ticks = 150;
3757 sc->bge_tx_coal_ticks = 150;
3758 sc->bge_rx_max_coal_bds = 10;
3759 sc->bge_tx_max_coal_bds = 10;
3761 /* Initialize checksum features to use. */
3762 sc->bge_csum_features = BGE_CSUM_FEATURES;
3763 if (sc->bge_forced_udpcsum != 0)
3764 sc->bge_csum_features |= CSUM_UDP;
3766 /* Set up ifnet structure */
3767 ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
3769 device_printf(sc->bge_dev, "failed to if_alloc()\n");
3773 if_setsoftc(ifp, sc);
3774 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3775 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
3776 if_setioctlfn(ifp, bge_ioctl);
3777 if_setstartfn(ifp, bge_start);
3778 if_setinitfn(ifp, bge_init);
3779 if_setgetcounterfn(ifp, bge_get_counter);
3780 if_setsendqlen(ifp, BGE_TX_RING_CNT - 1);
3781 if_setsendqready(ifp);
3782 if_sethwassist(ifp, sc->bge_csum_features);
3783 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3785 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3786 if_sethwassistbits(ifp, CSUM_TSO, 0);
3787 if_setcapabilitiesbit(ifp, IFCAP_TSO4 | IFCAP_VLAN_HWTSO, 0);
3789 #ifdef IFCAP_VLAN_HWCSUM
3790 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0);
3792 if_setcapenable(ifp, if_getcapabilities(ifp));
3793 #ifdef DEVICE_POLLING
3794 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
3798 * 5700 B0 chips do not support checksumming correctly due
3801 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
3802 if_setcapabilitiesbit(ifp, 0, IFCAP_HWCSUM);
3803 if_setcapenablebit(ifp, 0, IFCAP_HWCSUM);
3804 if_sethwassist(ifp, 0);
3808 * Figure out what sort of media we have by checking the
3809 * hardware config word in the first 32k of NIC internal memory,
3810 * or fall back to examining the EEPROM if necessary.
3811 * Note: on some BCM5700 cards, this value appears to be unset.
3812 * If that's the case, we have to rely on identifying the NIC
3813 * by its PCI subsystem ID, as we do below for the SysKonnect
3816 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
3817 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3818 else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
3819 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3820 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
3822 device_printf(sc->bge_dev, "failed to read EEPROM\n");
3826 hwcfg = ntohl(hwcfg);
3829 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
3830 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
3831 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
3832 if (BGE_IS_5705_PLUS(sc)) {
3833 sc->bge_flags |= BGE_FLAG_MII_SERDES;
3834 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3836 sc->bge_flags |= BGE_FLAG_TBI;
3839 /* Set various PHY bug flags. */
3840 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
3841 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
3842 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
3843 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
3844 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
3845 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
3846 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
3847 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
3848 if (pci_get_subvendor(dev) == DELL_VENDORID)
3849 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
3850 if ((BGE_IS_5705_PLUS(sc)) &&
3851 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
3852 sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
3853 sc->bge_asicrev != BGE_ASICREV_BCM57780 &&
3854 !BGE_IS_5717_PLUS(sc)) {
3855 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
3856 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3857 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3858 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
3859 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
3860 pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
3861 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
3862 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
3863 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
3865 sc->bge_phy_flags |= BGE_PHY_BER_BUG;
3869 * Don't enable Ethernet@WireSpeed for the 5700 or the
3870 * 5705 A0 and A1 chips.
3872 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3873 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3874 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
3875 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)))
3876 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3878 if (sc->bge_flags & BGE_FLAG_TBI) {
3879 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3881 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
3882 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
3884 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3885 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3886 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3889 * Do transceiver setup and tell the firmware the
3890 * driver is down so we can try to get access the
3891 * probe if ASF is running. Retry a couple of times
3892 * if we get a conflict with the ASF firmware accessing
3896 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3898 bge_asf_driver_up(sc);
3900 error = mii_attach(dev, &sc->bge_miibus, ifp,
3901 (ifm_change_cb_t)bge_ifmedia_upd,
3902 (ifm_stat_cb_t)bge_ifmedia_sts, capmask, sc->bge_phy_addr,
3903 MII_OFFSET_ANY, MIIF_DOPAUSE);
3906 device_printf(sc->bge_dev, "Try again\n");
3907 bge_miibus_writereg(sc->bge_dev,
3908 sc->bge_phy_addr, MII_BMCR, BMCR_RESET);
3911 device_printf(sc->bge_dev, "attaching PHYs failed\n");
3916 * Now tell the firmware we are going up after probing the PHY
3918 if (sc->bge_asf_mode & ASF_STACKUP)
3919 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3923 * When using the BCM5701 in PCI-X mode, data corruption has
3924 * been observed in the first few bytes of some received packets.
3925 * Aligning the packet buffer in memory eliminates the corruption.
3926 * Unfortunately, this misaligns the packet payloads. On platforms
3927 * which do not support unaligned accesses, we will realign the
3928 * payloads by copying the received packets.
3930 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
3931 sc->bge_flags & BGE_FLAG_PCIX)
3932 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
3935 * Call MI attach routine.
3937 ether_ifattach(ifp, eaddr);
3939 /* Tell upper layer we support long frames. */
3940 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
3945 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
3946 /* Take advantage of single-shot MSI. */
3947 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
3948 ~BGE_MSIMODE_ONE_SHOT_DISABLE);
3949 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
3950 taskqueue_thread_enqueue, &sc->bge_tq);
3951 if (sc->bge_tq == NULL) {
3952 device_printf(dev, "could not create taskqueue.\n");
3953 ether_ifdetach(ifp);
3957 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET,
3958 "%s taskq", device_get_nameunit(sc->bge_dev));
3960 device_printf(dev, "could not start threads.\n");
3961 ether_ifdetach(ifp);
3964 error = bus_setup_intr(dev, sc->bge_irq,
3965 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
3968 error = bus_setup_intr(dev, sc->bge_irq,
3969 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
3973 ether_ifdetach(ifp);
3974 device_printf(sc->bge_dev, "couldn't set up irq\n");
3978 /* Attach driver debugnet methods. */
3979 DEBUGNET_SET(ifp, bge);
3988 bge_detach(device_t dev)
3990 struct bge_softc *sc;
3993 sc = device_get_softc(dev);
3996 #ifdef DEVICE_POLLING
3997 if (if_getcapenable(ifp) & IFCAP_POLLING)
3998 ether_poll_deregister(ifp);
4001 if (device_is_attached(dev)) {
4002 ether_ifdetach(ifp);
4006 callout_drain(&sc->bge_stat_ch);
4010 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
4012 if (sc->bge_flags & BGE_FLAG_TBI)
4013 ifmedia_removeall(&sc->bge_ifmedia);
4014 else if (sc->bge_miibus != NULL) {
4015 bus_generic_detach(dev);
4016 device_delete_child(dev, sc->bge_miibus);
4019 bge_release_resources(sc);
4025 bge_release_resources(struct bge_softc *sc)
4031 if (sc->bge_tq != NULL)
4032 taskqueue_free(sc->bge_tq);
4034 if (sc->bge_intrhand != NULL)
4035 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
4037 if (sc->bge_irq != NULL) {
4038 bus_release_resource(dev, SYS_RES_IRQ,
4039 rman_get_rid(sc->bge_irq), sc->bge_irq);
4040 pci_release_msi(dev);
4043 if (sc->bge_res != NULL)
4044 bus_release_resource(dev, SYS_RES_MEMORY,
4045 rman_get_rid(sc->bge_res), sc->bge_res);
4047 if (sc->bge_res2 != NULL)
4048 bus_release_resource(dev, SYS_RES_MEMORY,
4049 rman_get_rid(sc->bge_res2), sc->bge_res2);
4051 if (sc->bge_ifp != NULL)
4052 if_free(sc->bge_ifp);
4056 if (mtx_initialized(&sc->bge_mtx)) /* XXX */
4057 BGE_LOCK_DESTROY(sc);
4061 bge_reset(struct bge_softc *sc)
4064 uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val;
4065 void (*write_op)(struct bge_softc *, int, int);
4071 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
4072 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4073 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
4074 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
4076 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
4077 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
4078 if (sc->bge_flags & BGE_FLAG_PCIE)
4079 write_op = bge_writemem_direct;
4081 write_op = bge_writemem_ind;
4083 write_op = bge_writereg_ind;
4085 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
4086 sc->bge_asicrev != BGE_ASICREV_BCM5701) {
4087 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
4088 for (i = 0; i < 8000; i++) {
4089 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
4090 BGE_NVRAMSWARB_GNT1)
4096 device_printf(dev, "NVRAM lock timedout!\n");
4099 /* Take APE lock when performing reset. */
4100 bge_ape_lock(sc, BGE_APE_LOCK_GRC);
4102 /* Save some important PCI state. */
4103 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
4104 command = pci_read_config(dev, BGE_PCI_CMD, 4);
4106 pci_write_config(dev, BGE_PCI_MISC_CTL,
4107 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4108 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4110 /* Disable fastboot on controllers that support it. */
4111 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
4112 BGE_IS_5755_PLUS(sc)) {
4114 device_printf(dev, "Disabling fastboot\n");
4115 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
4119 * Write the magic number to SRAM at offset 0xB50.
4120 * When firmware finishes its initialization it will
4121 * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
4123 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
4125 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
4127 /* XXX: Broadcom Linux driver. */
4128 if (sc->bge_flags & BGE_FLAG_PCIE) {
4129 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
4130 (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) {
4131 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */
4132 CSR_WRITE_4(sc, 0x7E2C, 0x20);
4134 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
4135 /* Prevent PCIE link training during global reset */
4136 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
4141 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4142 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4143 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
4144 val | BGE_VCPU_STATUS_DRV_RESET);
4145 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
4146 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
4147 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
4151 * Set GPHY Power Down Override to leave GPHY
4152 * powered up in D0 uninitialized.
4154 if (BGE_IS_5705_PLUS(sc) &&
4155 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0)
4156 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
4158 /* Issue global reset */
4159 write_op(sc, BGE_MISC_CFG, reset);
4161 if (sc->bge_flags & BGE_FLAG_PCIE)
4166 /* XXX: Broadcom Linux driver. */
4167 if (sc->bge_flags & BGE_FLAG_PCIE) {
4168 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
4169 DELAY(500000); /* wait for link training to complete */
4170 val = pci_read_config(dev, 0xC4, 4);
4171 pci_write_config(dev, 0xC4, val | (1 << 15), 4);
4173 devctl = pci_read_config(dev,
4174 sc->bge_expcap + PCIER_DEVICE_CTL, 2);
4175 /* Clear enable no snoop and disable relaxed ordering. */
4176 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE |
4177 PCIEM_CTL_NOSNOOP_ENABLE);
4178 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL,
4180 pci_set_max_read_req(dev, sc->bge_expmrq);
4181 /* Clear error status. */
4182 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA,
4183 PCIEM_STA_CORRECTABLE_ERROR |
4184 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
4185 PCIEM_STA_UNSUPPORTED_REQ, 2);
4188 /* Reset some of the PCI state that got zapped by reset. */
4189 pci_write_config(dev, BGE_PCI_MISC_CTL,
4190 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4191 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4192 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
4193 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
4194 (sc->bge_flags & BGE_FLAG_PCIX) != 0)
4195 val |= BGE_PCISTATE_RETRY_SAME_DMA;
4196 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4197 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
4198 BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
4199 BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
4200 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4);
4201 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
4202 pci_write_config(dev, BGE_PCI_CMD, command, 4);
4204 * Disable PCI-X relaxed ordering to ensure status block update
4205 * comes first then packet buffer DMA. Otherwise driver may
4206 * read stale status block.
4208 if (sc->bge_flags & BGE_FLAG_PCIX) {
4209 devctl = pci_read_config(dev,
4210 sc->bge_pcixcap + PCIXR_COMMAND, 2);
4211 devctl &= ~PCIXM_COMMAND_ERO;
4212 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
4213 devctl &= ~PCIXM_COMMAND_MAX_READ;
4214 devctl |= PCIXM_COMMAND_MAX_READ_2048;
4215 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4216 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
4217 PCIXM_COMMAND_MAX_READ);
4218 devctl |= PCIXM_COMMAND_MAX_READ_2048;
4220 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
4223 /* Re-enable MSI, if necessary, and enable the memory arbiter. */
4224 if (BGE_IS_5714_FAMILY(sc)) {
4225 /* This chip disables MSI on reset. */
4226 if (sc->bge_flags & BGE_FLAG_MSI) {
4227 val = pci_read_config(dev,
4228 sc->bge_msicap + PCIR_MSI_CTRL, 2);
4229 pci_write_config(dev,
4230 sc->bge_msicap + PCIR_MSI_CTRL,
4231 val | PCIM_MSICTRL_MSI_ENABLE, 2);
4232 val = CSR_READ_4(sc, BGE_MSI_MODE);
4233 CSR_WRITE_4(sc, BGE_MSI_MODE,
4234 val | BGE_MSIMODE_ENABLE);
4236 val = CSR_READ_4(sc, BGE_MARB_MODE);
4237 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
4239 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4241 /* Fix up byte swapping. */
4242 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
4244 val = CSR_READ_4(sc, BGE_MAC_MODE);
4245 val = (val & ~mac_mode_mask) | mac_mode;
4246 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
4249 bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
4251 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4252 for (i = 0; i < BGE_TIMEOUT; i++) {
4253 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4254 if (val & BGE_VCPU_STATUS_INIT_DONE)
4258 if (i == BGE_TIMEOUT) {
4259 device_printf(dev, "reset timed out\n");
4264 * Poll until we see the 1's complement of the magic number.
4265 * This indicates that the firmware initialization is complete.
4266 * We expect this to fail if no chip containing the Ethernet
4267 * address is fitted though.
4269 for (i = 0; i < BGE_TIMEOUT; i++) {
4271 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
4272 if (val == ~BGE_SRAM_FW_MB_MAGIC)
4276 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
4278 "firmware handshake timed out, found 0x%08x\n",
4280 /* BCM57765 A0 needs additional time before accessing. */
4281 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
4282 DELAY(10 * 1000); /* XXX */
4286 * The 5704 in TBI mode apparently needs some special
4287 * adjustment to insure the SERDES drive level is set
4290 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
4291 sc->bge_flags & BGE_FLAG_TBI) {
4292 val = CSR_READ_4(sc, BGE_SERDES_CFG);
4293 val = (val & ~0xFFF) | 0x880;
4294 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
4297 /* XXX: Broadcom Linux driver. */
4298 if (sc->bge_flags & BGE_FLAG_PCIE &&
4299 !BGE_IS_5717_PLUS(sc) &&
4300 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
4301 sc->bge_asicrev != BGE_ASICREV_BCM5785) {
4302 /* Enable Data FIFO protection. */
4303 val = CSR_READ_4(sc, 0x7C00);
4304 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
4307 if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
4308 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
4309 CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
4314 static __inline void
4315 bge_rxreuse_std(struct bge_softc *sc, int i)
4317 struct bge_rx_bd *r;
4319 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
4320 r->bge_flags = BGE_RXBDFLAG_END;
4321 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
4323 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4326 static __inline void
4327 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
4329 struct bge_extrx_bd *r;
4331 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
4332 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
4333 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
4334 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
4335 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
4336 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
4338 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4342 * Frame reception handling. This is called if there's a frame
4343 * on the receive return list.
4345 * Note: we have to be able to handle two possibilities here:
4346 * 1) the frame is from the jumbo receive ring
4347 * 2) the frame is from the standard receive ring
4351 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
4354 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
4357 rx_cons = sc->bge_rx_saved_considx;
4359 /* Nothing to do. */
4360 if (rx_cons == rx_prod)
4365 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4366 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
4367 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4368 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
4369 if (BGE_IS_JUMBO_CAPABLE(sc) &&
4370 if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
4371 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))
4372 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4373 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
4375 while (rx_cons != rx_prod) {
4376 struct bge_rx_bd *cur_rx;
4378 struct mbuf *m = NULL;
4379 uint16_t vlan_tag = 0;
4382 #ifdef DEVICE_POLLING
4383 if (if_getcapenable(ifp) & IFCAP_POLLING) {
4384 if (sc->rxcycles <= 0)
4390 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
4392 rxidx = cur_rx->bge_idx;
4393 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
4395 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING &&
4396 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
4398 vlan_tag = cur_rx->bge_vlan_tag;
4401 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
4403 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
4404 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4405 bge_rxreuse_jumbo(sc, rxidx);
4408 if (bge_newbuf_jumbo(sc, rxidx) != 0) {
4409 bge_rxreuse_jumbo(sc, rxidx);
4410 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
4413 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4416 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
4417 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4418 bge_rxreuse_std(sc, rxidx);
4421 if (bge_newbuf_std(sc, rxidx) != 0) {
4422 bge_rxreuse_std(sc, rxidx);
4423 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
4426 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4429 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
4430 #ifndef __NO_STRICT_ALIGNMENT
4432 * For architectures with strict alignment we must make sure
4433 * the payload is aligned.
4435 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
4436 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
4438 m->m_data += ETHER_ALIGN;
4441 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
4442 m->m_pkthdr.rcvif = ifp;
4444 if (if_getcapenable(ifp) & IFCAP_RXCSUM)
4445 bge_rxcsum(sc, cur_rx, m);
4448 * If we received a packet with a vlan tag,
4449 * attach that information to the packet.
4452 m->m_pkthdr.ether_vtag = vlan_tag;
4453 m->m_flags |= M_VLANTAG;
4464 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4468 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4469 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
4471 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4472 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
4475 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4476 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
4478 sc->bge_rx_saved_considx = rx_cons;
4479 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
4481 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
4482 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT);
4484 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
4485 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT);
4488 * This register wraps very quickly under heavy packet drops.
4489 * If you need correct statistics, you can enable this check.
4491 if (BGE_IS_5705_PLUS(sc))
4492 if_incierrors(ifp, CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS));
4498 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
4501 if (BGE_IS_5717_PLUS(sc)) {
4502 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
4503 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4504 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4505 if ((cur_rx->bge_error_flag &
4506 BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
4507 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4509 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
4510 m->m_pkthdr.csum_data =
4511 cur_rx->bge_tcp_udp_csum;
4512 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4517 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4518 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4519 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
4520 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4522 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
4523 m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
4524 m->m_pkthdr.csum_data =
4525 cur_rx->bge_tcp_udp_csum;
4526 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4533 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
4535 struct bge_tx_bd *cur_tx;
4538 BGE_LOCK_ASSERT(sc);
4540 /* Nothing to do. */
4541 if (sc->bge_tx_saved_considx == tx_cons)
4546 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4547 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
4549 * Go through our tx ring and free mbufs for those
4550 * frames that have been sent.
4552 while (sc->bge_tx_saved_considx != tx_cons) {
4555 idx = sc->bge_tx_saved_considx;
4556 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
4557 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
4558 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
4559 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
4560 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
4561 sc->bge_cdata.bge_tx_dmamap[idx],
4562 BUS_DMASYNC_POSTWRITE);
4563 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
4564 sc->bge_cdata.bge_tx_dmamap[idx]);
4565 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
4566 sc->bge_cdata.bge_tx_chain[idx] = NULL;
4569 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
4572 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
4573 if (sc->bge_txcnt == 0)
4577 #ifdef DEVICE_POLLING
4579 bge_poll(if_t ifp, enum poll_cmd cmd, int count)
4581 struct bge_softc *sc = if_getsoftc(ifp);
4582 uint16_t rx_prod, tx_cons;
4583 uint32_t statusword;
4587 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
4592 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4593 sc->bge_cdata.bge_status_map,
4594 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4595 /* Fetch updates from the status block. */
4596 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4597 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4599 statusword = sc->bge_ldata.bge_status_block->bge_status;
4600 /* Clear the status so the next pass only sees the changes. */
4601 sc->bge_ldata.bge_status_block->bge_status = 0;
4603 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4604 sc->bge_cdata.bge_status_map,
4605 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4607 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
4608 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
4611 if (cmd == POLL_AND_CHECK_STATUS)
4612 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4613 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4614 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
4617 sc->rxcycles = count;
4618 rx_npkts = bge_rxeof(sc, rx_prod, 1);
4619 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
4623 bge_txeof(sc, tx_cons);
4624 if (!if_sendq_empty(ifp))
4625 bge_start_locked(ifp);
4630 #endif /* DEVICE_POLLING */
4633 bge_msi_intr(void *arg)
4635 struct bge_softc *sc;
4637 sc = (struct bge_softc *)arg;
4639 * This interrupt is not shared and controller already
4640 * disabled further interrupt.
4642 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
4643 return (FILTER_HANDLED);
4647 bge_intr_task(void *arg, int pending)
4649 struct bge_softc *sc;
4651 uint32_t status, status_tag;
4652 uint16_t rx_prod, tx_cons;
4654 sc = (struct bge_softc *)arg;
4658 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
4663 /* Get updated status block. */
4664 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4665 sc->bge_cdata.bge_status_map,
4666 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4668 /* Save producer/consumer indices. */
4669 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4670 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4671 status = sc->bge_ldata.bge_status_block->bge_status;
4672 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
4673 /* Dirty the status flag. */
4674 sc->bge_ldata.bge_status_block->bge_status = 0;
4675 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4676 sc->bge_cdata.bge_status_map,
4677 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4678 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
4681 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
4684 /* Let controller work. */
4685 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
4687 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
4688 sc->bge_rx_saved_considx != rx_prod) {
4689 /* Check RX return ring producer/consumer. */
4691 bge_rxeof(sc, rx_prod, 0);
4694 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4695 /* Check TX ring producer/consumer. */
4696 bge_txeof(sc, tx_cons);
4697 if (!if_sendq_empty(ifp))
4698 bge_start_locked(ifp);
4706 struct bge_softc *sc;
4708 uint32_t statusword;
4709 uint16_t rx_prod, tx_cons;
4717 #ifdef DEVICE_POLLING
4718 if (if_getcapenable(ifp) & IFCAP_POLLING) {
4725 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
4726 * disable interrupts by writing nonzero like we used to, since with
4727 * our current organization this just gives complications and
4728 * pessimizations for re-enabling interrupts. We used to have races
4729 * instead of the necessary complications. Disabling interrupts
4730 * would just reduce the chance of a status update while we are
4731 * running (by switching to the interrupt-mode coalescence
4732 * parameters), but this chance is already very low so it is more
4733 * efficient to get another interrupt than prevent it.
4735 * We do the ack first to ensure another interrupt if there is a
4736 * status update after the ack. We don't check for the status
4737 * changing later because it is more efficient to get another
4738 * interrupt than prevent it, not quite as above (not checking is
4739 * a smaller optimization than not toggling the interrupt enable,
4740 * since checking doesn't involve PCI accesses and toggling require
4741 * the status check). So toggling would probably be a pessimization
4742 * even with MSI. It would only be needed for using a task queue.
4744 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4747 * Do the mandatory PCI flush as well as get the link status.
4749 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
4751 /* Make sure the descriptor ring indexes are coherent. */
4752 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4753 sc->bge_cdata.bge_status_map,
4754 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4755 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4756 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4757 sc->bge_ldata.bge_status_block->bge_status = 0;
4758 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4759 sc->bge_cdata.bge_status_map,
4760 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4762 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4763 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4764 statusword || sc->bge_link_evt)
4767 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4768 /* Check RX return ring producer/consumer. */
4769 bge_rxeof(sc, rx_prod, 1);
4772 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4773 /* Check TX ring producer/consumer. */
4774 bge_txeof(sc, tx_cons);
4777 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
4778 !if_sendq_empty(ifp))
4779 bge_start_locked(ifp);
4785 bge_asf_driver_up(struct bge_softc *sc)
4787 if (sc->bge_asf_mode & ASF_STACKUP) {
4788 /* Send ASF heartbeat aprox. every 2s */
4789 if (sc->bge_asf_count)
4790 sc->bge_asf_count --;
4792 sc->bge_asf_count = 2;
4793 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4794 BGE_FW_CMD_DRV_ALIVE);
4795 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4796 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
4797 BGE_FW_HB_TIMEOUT_SEC);
4798 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
4799 CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4800 BGE_RX_CPU_DRV_EVENT);
4808 struct bge_softc *sc = xsc;
4809 struct mii_data *mii = NULL;
4811 BGE_LOCK_ASSERT(sc);
4813 /* Synchronize with possible callout reset/stop. */
4814 if (callout_pending(&sc->bge_stat_ch) ||
4815 !callout_active(&sc->bge_stat_ch))
4818 if (BGE_IS_5705_PLUS(sc))
4819 bge_stats_update_regs(sc);
4821 bge_stats_update(sc);
4823 /* XXX Add APE heartbeat check here? */
4825 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4826 mii = device_get_softc(sc->bge_miibus);
4828 * Do not touch PHY if we have link up. This could break
4829 * IPMI/ASF mode or produce extra input errors
4830 * (extra errors was reported for bcm5701 & bcm5704).
4836 * Since in TBI mode auto-polling can't be used we should poll
4837 * link status manually. Here we register pending link event
4838 * and trigger interrupt.
4840 #ifdef DEVICE_POLLING
4841 /* In polling mode we poll link state in bge_poll(). */
4842 if (!(if_getcapenable(sc->bge_ifp) & IFCAP_POLLING))
4846 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4847 sc->bge_flags & BGE_FLAG_5788)
4848 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4850 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4854 bge_asf_driver_up(sc);
4857 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4861 bge_stats_update_regs(struct bge_softc *sc)
4864 struct bge_mac_stats *stats;
4868 stats = &sc->bge_mac_stats;
4870 stats->ifHCOutOctets +=
4871 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4872 stats->etherStatsCollisions +=
4873 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4874 stats->outXonSent +=
4875 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4876 stats->outXoffSent +=
4877 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4878 stats->dot3StatsInternalMacTransmitErrors +=
4879 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4880 stats->dot3StatsSingleCollisionFrames +=
4881 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4882 stats->dot3StatsMultipleCollisionFrames +=
4883 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4884 stats->dot3StatsDeferredTransmissions +=
4885 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4886 stats->dot3StatsExcessiveCollisions +=
4887 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4888 stats->dot3StatsLateCollisions +=
4889 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4890 stats->ifHCOutUcastPkts +=
4891 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4892 stats->ifHCOutMulticastPkts +=
4893 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4894 stats->ifHCOutBroadcastPkts +=
4895 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4897 stats->ifHCInOctets +=
4898 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4899 stats->etherStatsFragments +=
4900 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4901 stats->ifHCInUcastPkts +=
4902 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4903 stats->ifHCInMulticastPkts +=
4904 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4905 stats->ifHCInBroadcastPkts +=
4906 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4907 stats->dot3StatsFCSErrors +=
4908 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4909 stats->dot3StatsAlignmentErrors +=
4910 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4911 stats->xonPauseFramesReceived +=
4912 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4913 stats->xoffPauseFramesReceived +=
4914 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4915 stats->macControlFramesReceived +=
4916 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4917 stats->xoffStateEntered +=
4918 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4919 stats->dot3StatsFramesTooLong +=
4920 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4921 stats->etherStatsJabbers +=
4922 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4923 stats->etherStatsUndersizePkts +=
4924 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4926 stats->FramesDroppedDueToFilters +=
4927 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4928 stats->DmaWriteQueueFull +=
4929 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4930 stats->DmaWriteHighPriQueueFull +=
4931 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4932 stats->NoMoreRxBDs +=
4933 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4936 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS
4937 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0
4938 * includes number of unwanted multicast frames. This comes
4939 * from silicon bug and known workaround to get rough(not
4940 * exact) counter is to enable interrupt on MBUF low water
4941 * attention. This can be accomplished by setting
4942 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE,
4943 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and
4944 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL.
4945 * However that change would generate more interrupts and
4946 * there are still possibilities of losing multiple frames
4947 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling.
4948 * Given that the workaround still would not get correct
4949 * counter I don't think it's worth to implement it. So
4950 * ignore reading the counter on controllers that have the
4953 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
4954 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
4955 sc->bge_chipid != BGE_CHIPID_BCM5720_A0)
4956 stats->InputDiscards +=
4957 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4958 stats->InputErrors +=
4959 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4960 stats->RecvThresholdHit +=
4961 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4963 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
4965 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS
4966 * frames, it's safe to disable workaround for DMA engine's
4967 * miscalculation of TXMBUF space.
4969 if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts +
4970 stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) {
4971 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
4972 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
4973 val &= ~BGE_RDMA_TX_LENGTH_WA_5719;
4975 val &= ~BGE_RDMA_TX_LENGTH_WA_5720;
4976 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
4977 sc->bge_flags &= ~BGE_FLAG_RDMA_BUG;
4983 bge_stats_clear_regs(struct bge_softc *sc)
4986 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4987 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4988 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4989 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4990 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4991 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4992 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4993 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4994 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4995 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4996 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4997 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4998 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
5000 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
5001 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
5002 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
5003 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
5004 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
5005 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
5006 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
5007 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
5008 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
5009 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
5010 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
5011 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
5012 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
5013 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
5015 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
5016 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
5017 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
5018 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
5019 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
5020 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
5021 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
5025 bge_stats_update(struct bge_softc *sc)
5029 uint32_t cnt; /* current register value */
5033 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
5035 #define READ_STAT(sc, stats, stat) \
5036 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
5038 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
5039 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, cnt - sc->bge_tx_collisions);
5040 sc->bge_tx_collisions = cnt;
5042 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo);
5043 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_nobds);
5044 sc->bge_rx_nobds = cnt;
5045 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo);
5046 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_inerrs);
5047 sc->bge_rx_inerrs = cnt;
5048 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
5049 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_discards);
5050 sc->bge_rx_discards = cnt;
5052 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
5053 if_inc_counter(ifp, IFCOUNTER_OERRORS, cnt - sc->bge_tx_discards);
5054 sc->bge_tx_discards = cnt;
5060 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
5061 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
5062 * but when such padded frames employ the bge IP/TCP checksum offload,
5063 * the hardware checksum assist gives incorrect results (possibly
5064 * from incorporating its own padding into the UDP/TCP checksum; who knows).
5065 * If we pad such runts with zeros, the onboard checksum comes out correct.
5068 bge_cksum_pad(struct mbuf *m)
5070 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
5073 /* If there's only the packet-header and we can pad there, use it. */
5074 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
5075 M_TRAILINGSPACE(m) >= padlen) {
5079 * Walk packet chain to find last mbuf. We will either
5080 * pad there, or append a new mbuf and pad it.
5082 for (last = m; last->m_next != NULL; last = last->m_next);
5083 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
5084 /* Allocate new empty mbuf, pad it. Compact later. */
5087 MGET(n, M_NOWAIT, MT_DATA);
5096 /* Now zero the pad area, to avoid the bge cksum-assist bug. */
5097 memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
5098 last->m_len += padlen;
5099 m->m_pkthdr.len += padlen;
5104 static struct mbuf *
5105 bge_check_short_dma(struct mbuf *m)
5111 * If device receive two back-to-back send BDs with less than
5112 * or equal to 8 total bytes then the device may hang. The two
5113 * back-to-back send BDs must in the same frame for this failure
5114 * to occur. Scan mbuf chains and see whether two back-to-back
5115 * send BDs are there. If this is the case, allocate new mbuf
5116 * and copy the frame to workaround the silicon bug.
5118 for (n = m, found = 0; n != NULL; n = n->m_next) {
5129 n = m_defrag(m, M_NOWAIT);
5137 static struct mbuf *
5138 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
5147 if (M_WRITABLE(m) == 0) {
5148 /* Get a writable copy. */
5149 n = m_dup(m, M_NOWAIT);
5155 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
5158 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5159 poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
5160 m = m_pullup(m, poff + sizeof(struct tcphdr));
5163 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5164 m = m_pullup(m, poff + (tcp->th_off << 2));
5168 * It seems controller doesn't modify IP length and TCP pseudo
5169 * checksum. These checksum computed by upper stack should be 0.
5171 *mss = m->m_pkthdr.tso_segsz;
5172 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5174 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
5175 /* Clear pseudo checksum computed by TCP stack. */
5176 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5179 * Broadcom controllers uses different descriptor format for
5180 * TSO depending on ASIC revision. Due to TSO-capable firmware
5181 * license issue and lower performance of firmware based TSO
5182 * we only support hardware based TSO.
5184 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */
5185 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
5186 if (sc->bge_flags & BGE_FLAG_TSO3) {
5188 * For BCM5717 and newer controllers, hardware based TSO
5189 * uses the 14 lower bits of the bge_mss field to store the
5190 * MSS and the upper 2 bits to store the lowest 2 bits of
5191 * the IP/TCP header length. The upper 6 bits of the header
5192 * length are stored in the bge_flags[14:10,4] field. Jumbo
5193 * frames are supported.
5195 *mss |= ((hlen & 0x3) << 14);
5196 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2);
5199 * For BCM5755 and newer controllers, hardware based TSO uses
5200 * the lower 11 bits to store the MSS and the upper 5 bits to
5201 * store the IP/TCP header length. Jumbo frames are not
5204 *mss |= (hlen << 11);
5210 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
5211 * pointers to descriptors.
5214 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
5216 bus_dma_segment_t segs[BGE_NSEG_NEW];
5218 struct bge_tx_bd *d;
5219 struct mbuf *m = *m_head;
5220 uint32_t idx = *txidx;
5221 uint16_t csum_flags, mss, vlan_tag;
5222 int nsegs, i, error;
5227 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
5228 m->m_next != NULL) {
5229 *m_head = bge_check_short_dma(m);
5230 if (*m_head == NULL)
5234 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5235 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
5236 if (*m_head == NULL)
5238 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
5239 BGE_TXBDFLAG_CPU_POST_DMA;
5240 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
5241 if (m->m_pkthdr.csum_flags & CSUM_IP)
5242 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
5243 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
5244 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
5245 if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
5246 (error = bge_cksum_pad(m)) != 0) {
5254 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
5255 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
5256 m->m_pkthdr.len > ETHER_MAX_LEN)
5257 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME;
5258 if (sc->bge_forced_collapse > 0 &&
5259 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
5261 * Forcedly collapse mbuf chains to overcome hardware
5262 * limitation which only support a single outstanding
5263 * DMA read operation.
5265 if (sc->bge_forced_collapse == 1)
5266 m = m_defrag(m, M_NOWAIT);
5268 m = m_collapse(m, M_NOWAIT,
5269 sc->bge_forced_collapse);
5276 map = sc->bge_cdata.bge_tx_dmamap[idx];
5277 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
5278 &nsegs, BUS_DMA_NOWAIT);
5279 if (error == EFBIG) {
5280 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW);
5287 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
5288 m, segs, &nsegs, BUS_DMA_NOWAIT);
5294 } else if (error != 0)
5297 /* Check if we have enough free send BDs. */
5298 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
5299 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5303 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
5305 if (m->m_flags & M_VLANTAG) {
5306 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
5307 vlan_tag = m->m_pkthdr.ether_vtag;
5310 if (sc->bge_asicrev == BGE_ASICREV_BCM5762 &&
5311 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5313 * 5725 family of devices corrupts TSO packets when TSO DMA
5314 * buffers cross into regions which are within MSS bytes of
5315 * a 4GB boundary. If we encounter the condition, drop the
5318 for (i = 0; ; i++) {
5319 d = &sc->bge_ldata.bge_tx_ring[idx];
5320 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5321 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5322 d->bge_len = segs[i].ds_len;
5323 if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss <
5324 d->bge_addr.bge_addr_lo)
5326 d->bge_flags = csum_flags;
5327 d->bge_vlan_tag = vlan_tag;
5331 BGE_INC(idx, BGE_TX_RING_CNT);
5333 if (i != nsegs - 1) {
5334 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map,
5335 BUS_DMASYNC_POSTWRITE);
5336 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5342 for (i = 0; ; i++) {
5343 d = &sc->bge_ldata.bge_tx_ring[idx];
5344 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5345 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5346 d->bge_len = segs[i].ds_len;
5347 d->bge_flags = csum_flags;
5348 d->bge_vlan_tag = vlan_tag;
5352 BGE_INC(idx, BGE_TX_RING_CNT);
5356 /* Mark the last segment as end of packet... */
5357 d->bge_flags |= BGE_TXBDFLAG_END;
5360 * Insure that the map for this transmission
5361 * is placed at the array index of the last descriptor
5364 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
5365 sc->bge_cdata.bge_tx_dmamap[idx] = map;
5366 sc->bge_cdata.bge_tx_chain[idx] = m;
5367 sc->bge_txcnt += nsegs;
5369 BGE_INC(idx, BGE_TX_RING_CNT);
5376 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5377 * to the mbuf data regions directly in the transmit descriptors.
5380 bge_start_locked(if_t ifp)
5382 struct bge_softc *sc;
5383 struct mbuf *m_head;
5387 sc = if_getsoftc(ifp);
5388 BGE_LOCK_ASSERT(sc);
5390 if (!sc->bge_link ||
5391 (if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
5395 prodidx = sc->bge_tx_prodidx;
5397 for (count = 0; !if_sendq_empty(ifp);) {
5398 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
5399 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5402 m_head = if_dequeue(ifp);
5407 * Pack the data into the transmit ring. If we
5408 * don't have room, set the OACTIVE flag and wait
5409 * for the NIC to drain the ring.
5411 if (bge_encap(sc, &m_head, &prodidx)) {
5414 if_sendq_prepend(ifp, m_head);
5415 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5421 * If there's a BPF listener, bounce a copy of this frame
5424 if_bpfmtap(ifp, m_head);
5428 bge_start_tx(sc, prodidx);
5432 bge_start_tx(struct bge_softc *sc, uint32_t prodidx)
5435 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
5436 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
5438 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5439 /* 5700 b2 errata */
5440 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
5441 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5443 sc->bge_tx_prodidx = prodidx;
5445 /* Set a timeout in case the chip goes out to lunch. */
5446 sc->bge_timer = BGE_TX_TIMEOUT;
5450 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5451 * to the mbuf data regions directly in the transmit descriptors.
5456 struct bge_softc *sc;
5458 sc = if_getsoftc(ifp);
5460 bge_start_locked(ifp);
5465 bge_init_locked(struct bge_softc *sc)
5471 BGE_LOCK_ASSERT(sc);
5475 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
5478 /* Cancel pending I/O and flush buffers. */
5482 bge_sig_pre_reset(sc, BGE_RESET_START);
5484 bge_sig_legacy(sc, BGE_RESET_START);
5485 bge_sig_post_reset(sc, BGE_RESET_START);
5490 * Init the various state machines, ring
5491 * control blocks and firmware.
5493 if (bge_blockinit(sc)) {
5494 device_printf(sc->bge_dev, "initialization failure\n");
5501 CSR_WRITE_4(sc, BGE_RX_MTU, if_getmtu(ifp) +
5502 ETHER_HDR_LEN + ETHER_CRC_LEN +
5503 (if_getcapenable(ifp) & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
5505 /* Load our MAC address. */
5506 m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
5507 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
5508 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
5510 /* Program promiscuous mode. */
5513 /* Program multicast filter. */
5516 /* Program VLAN tag stripping. */
5519 /* Override UDP checksum offloading. */
5520 if (sc->bge_forced_udpcsum == 0)
5521 sc->bge_csum_features &= ~CSUM_UDP;
5523 sc->bge_csum_features |= CSUM_UDP;
5524 if (if_getcapabilities(ifp) & IFCAP_TXCSUM &&
5525 if_getcapenable(ifp) & IFCAP_TXCSUM) {
5526 if_sethwassistbits(ifp, 0, (BGE_CSUM_FEATURES | CSUM_UDP));
5527 if_sethwassistbits(ifp, sc->bge_csum_features, 0);
5531 if (bge_init_rx_ring_std(sc) != 0) {
5532 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
5538 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
5539 * memory to insure that the chip has in fact read the first
5540 * entry of the ring.
5542 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
5544 for (i = 0; i < 10; i++) {
5546 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
5547 if (v == (MCLBYTES - ETHER_ALIGN))
5551 device_printf (sc->bge_dev,
5552 "5705 A0 chip failed to load RX ring\n");
5555 /* Init jumbo RX ring. */
5556 if (BGE_IS_JUMBO_CAPABLE(sc) &&
5557 if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
5558 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) {
5559 if (bge_init_rx_ring_jumbo(sc) != 0) {
5560 device_printf(sc->bge_dev,
5561 "no memory for jumbo Rx buffers.\n");
5567 /* Init our RX return ring index. */
5568 sc->bge_rx_saved_considx = 0;
5570 /* Init our RX/TX stat counters. */
5571 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
5574 bge_init_tx_ring(sc);
5576 /* Enable TX MAC state machine lockup fix. */
5577 mode = CSR_READ_4(sc, BGE_TX_MODE);
5578 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
5579 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
5580 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
5581 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
5582 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5583 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
5584 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5586 /* Turn on transmitter. */
5587 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
5590 /* Turn on receiver. */
5591 mode = CSR_READ_4(sc, BGE_RX_MODE);
5592 if (BGE_IS_5755_PLUS(sc))
5593 mode |= BGE_RXMODE_IPV6_ENABLE;
5594 if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
5595 mode |= BGE_RXMODE_IPV4_FRAG_FIX;
5596 CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
5600 * Set the number of good frames to receive after RX MBUF
5601 * Low Watermark has been reached. After the RX MAC receives
5602 * this number of frames, it will drop subsequent incoming
5603 * frames until the MBUF High Watermark is reached.
5605 if (BGE_IS_57765_PLUS(sc))
5606 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
5608 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
5610 /* Clear MAC statistics. */
5611 if (BGE_IS_5705_PLUS(sc))
5612 bge_stats_clear_regs(sc);
5614 /* Tell firmware we're alive. */
5615 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5617 #ifdef DEVICE_POLLING
5618 /* Disable interrupts if we are polling. */
5619 if (if_getcapenable(ifp) & IFCAP_POLLING) {
5620 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5621 BGE_PCIMISCCTL_MASK_PCI_INTR);
5622 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5626 /* Enable host interrupts. */
5628 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
5629 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5630 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5633 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
5634 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
5636 bge_ifmedia_upd_locked(ifp);
5638 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
5644 struct bge_softc *sc = xsc;
5647 bge_init_locked(sc);
5652 * Set media options.
5655 bge_ifmedia_upd(if_t ifp)
5657 struct bge_softc *sc = if_getsoftc(ifp);
5661 res = bge_ifmedia_upd_locked(ifp);
5668 bge_ifmedia_upd_locked(if_t ifp)
5670 struct bge_softc *sc = if_getsoftc(ifp);
5671 struct mii_data *mii;
5672 struct mii_softc *miisc;
5673 struct ifmedia *ifm;
5675 BGE_LOCK_ASSERT(sc);
5677 ifm = &sc->bge_ifmedia;
5679 /* If this is a 1000baseX NIC, enable the TBI port. */
5680 if (sc->bge_flags & BGE_FLAG_TBI) {
5681 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
5683 switch(IFM_SUBTYPE(ifm->ifm_media)) {
5686 * The BCM5704 ASIC appears to have a special
5687 * mechanism for programming the autoneg
5688 * advertisement registers in TBI mode.
5690 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
5692 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5693 if (sgdig & BGE_SGDIGSTS_DONE) {
5694 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5695 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5696 sgdig |= BGE_SGDIGCFG_AUTO |
5697 BGE_SGDIGCFG_PAUSE_CAP |
5698 BGE_SGDIGCFG_ASYM_PAUSE;
5699 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
5700 sgdig | BGE_SGDIGCFG_SEND);
5702 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
5707 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
5708 BGE_CLRBIT(sc, BGE_MAC_MODE,
5709 BGE_MACMODE_HALF_DUPLEX);
5711 BGE_SETBIT(sc, BGE_MAC_MODE,
5712 BGE_MACMODE_HALF_DUPLEX);
5723 mii = device_get_softc(sc->bge_miibus);
5724 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
5729 * Force an interrupt so that we will call bge_link_upd
5730 * if needed and clear any pending link state attention.
5731 * Without this we are not getting any further interrupts
5732 * for link state changes and thus will not UP the link and
5733 * not be able to send in bge_start_locked. The only
5734 * way to get things working was to receive a packet and
5736 * bge_tick should help for fiber cards and we might not
5737 * need to do this here if BGE_FLAG_TBI is set but as
5738 * we poll for fiber anyway it should not harm.
5740 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
5741 sc->bge_flags & BGE_FLAG_5788)
5742 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
5744 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
5750 * Report current media status.
5753 bge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
5755 struct bge_softc *sc = if_getsoftc(ifp);
5756 struct mii_data *mii;
5760 if ((if_getflags(ifp) & IFF_UP) == 0) {
5764 if (sc->bge_flags & BGE_FLAG_TBI) {
5765 ifmr->ifm_status = IFM_AVALID;
5766 ifmr->ifm_active = IFM_ETHER;
5767 if (CSR_READ_4(sc, BGE_MAC_STS) &
5768 BGE_MACSTAT_TBI_PCS_SYNCHED)
5769 ifmr->ifm_status |= IFM_ACTIVE;
5771 ifmr->ifm_active |= IFM_NONE;
5775 ifmr->ifm_active |= IFM_1000_SX;
5776 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5777 ifmr->ifm_active |= IFM_HDX;
5779 ifmr->ifm_active |= IFM_FDX;
5784 mii = device_get_softc(sc->bge_miibus);
5786 ifmr->ifm_active = mii->mii_media_active;
5787 ifmr->ifm_status = mii->mii_media_status;
5793 bge_ioctl(if_t ifp, u_long command, caddr_t data)
5795 struct bge_softc *sc = if_getsoftc(ifp);
5796 struct ifreq *ifr = (struct ifreq *) data;
5797 struct mii_data *mii;
5798 int flags, mask, error = 0;
5802 if (BGE_IS_JUMBO_CAPABLE(sc) ||
5803 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
5804 if (ifr->ifr_mtu < ETHERMIN ||
5805 ifr->ifr_mtu > BGE_JUMBO_MTU) {
5809 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) {
5814 if (if_getmtu(ifp) != ifr->ifr_mtu) {
5815 if_setmtu(ifp, ifr->ifr_mtu);
5816 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5817 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5818 bge_init_locked(sc);
5825 if (if_getflags(ifp) & IFF_UP) {
5827 * If only the state of the PROMISC flag changed,
5828 * then just use the 'set promisc mode' command
5829 * instead of reinitializing the entire NIC. Doing
5830 * a full re-init means reloading the firmware and
5831 * waiting for it to start up, which may take a
5832 * second or two. Similarly for ALLMULTI.
5834 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5835 flags = if_getflags(ifp) ^ sc->bge_if_flags;
5836 if (flags & IFF_PROMISC)
5838 if (flags & IFF_ALLMULTI)
5841 bge_init_locked(sc);
5843 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5847 sc->bge_if_flags = if_getflags(ifp);
5853 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5862 if (sc->bge_flags & BGE_FLAG_TBI) {
5863 error = ifmedia_ioctl(ifp, ifr,
5864 &sc->bge_ifmedia, command);
5866 mii = device_get_softc(sc->bge_miibus);
5867 error = ifmedia_ioctl(ifp, ifr,
5868 &mii->mii_media, command);
5872 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
5873 #ifdef DEVICE_POLLING
5874 if (mask & IFCAP_POLLING) {
5875 if (ifr->ifr_reqcap & IFCAP_POLLING) {
5876 error = ether_poll_register(bge_poll, ifp);
5880 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5881 BGE_PCIMISCCTL_MASK_PCI_INTR);
5882 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5883 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
5886 error = ether_poll_deregister(ifp);
5887 /* Enable interrupt even in error case */
5889 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
5890 BGE_PCIMISCCTL_MASK_PCI_INTR);
5891 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5892 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
5897 if ((mask & IFCAP_TXCSUM) != 0 &&
5898 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
5899 if_togglecapenable(ifp, IFCAP_TXCSUM);
5900 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
5901 if_sethwassistbits(ifp,
5902 sc->bge_csum_features, 0);
5904 if_sethwassistbits(ifp, 0,
5905 sc->bge_csum_features);
5908 if ((mask & IFCAP_RXCSUM) != 0 &&
5909 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0)
5910 if_togglecapenable(ifp, IFCAP_RXCSUM);
5912 if ((mask & IFCAP_TSO4) != 0 &&
5913 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
5914 if_togglecapenable(ifp, IFCAP_TSO4);
5915 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
5916 if_sethwassistbits(ifp, CSUM_TSO, 0);
5918 if_sethwassistbits(ifp, 0, CSUM_TSO);
5921 if (mask & IFCAP_VLAN_MTU) {
5922 if_togglecapenable(ifp, IFCAP_VLAN_MTU);
5923 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5927 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
5928 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
5929 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
5930 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
5931 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
5932 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
5933 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
5934 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO);
5939 #ifdef VLAN_CAPABILITIES
5944 error = ether_ioctl(ifp, command, data);
5952 bge_watchdog(struct bge_softc *sc)
5957 BGE_LOCK_ASSERT(sc);
5959 if (sc->bge_timer == 0 || --sc->bge_timer)
5962 /* If pause frames are active then don't reset the hardware. */
5963 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) {
5964 status = CSR_READ_4(sc, BGE_RX_STS);
5965 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) {
5967 * If link partner has us in XOFF state then wait for
5968 * the condition to clear.
5970 CSR_WRITE_4(sc, BGE_RX_STS, status);
5971 sc->bge_timer = BGE_TX_TIMEOUT;
5973 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 &&
5974 (status & BGE_RXSTAT_RCVD_XON) != 0) {
5976 * If link partner has us in XOFF state then wait for
5977 * the condition to clear.
5979 CSR_WRITE_4(sc, BGE_RX_STS, status);
5980 sc->bge_timer = BGE_TX_TIMEOUT;
5984 * Any other condition is unexpected and the controller
5991 if_printf(ifp, "watchdog timeout -- resetting\n");
5993 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5994 bge_init_locked(sc);
5996 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
6000 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
6004 BGE_CLRBIT(sc, reg, bit);
6006 for (i = 0; i < BGE_TIMEOUT; i++) {
6007 if ((CSR_READ_4(sc, reg) & bit) == 0)
6014 * Stop the adapter and free any mbufs allocated to the
6018 bge_stop(struct bge_softc *sc)
6022 BGE_LOCK_ASSERT(sc);
6026 callout_stop(&sc->bge_stat_ch);
6028 /* Disable host interrupts. */
6029 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
6030 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
6033 * Tell firmware we're shutting down.
6036 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
6039 * Disable all of the receiver blocks.
6041 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
6042 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
6043 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
6044 if (BGE_IS_5700_FAMILY(sc))
6045 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
6046 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
6047 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
6048 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
6051 * Disable all of the transmit blocks.
6053 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
6054 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
6055 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
6056 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
6057 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
6058 if (BGE_IS_5700_FAMILY(sc))
6059 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
6060 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
6063 * Shut down all of the memory managers and related
6066 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
6067 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
6068 if (BGE_IS_5700_FAMILY(sc))
6069 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
6071 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
6072 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
6073 if (!(BGE_IS_5705_PLUS(sc))) {
6074 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
6075 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
6077 /* Update MAC statistics. */
6078 if (BGE_IS_5705_PLUS(sc))
6079 bge_stats_update_regs(sc);
6082 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
6083 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
6086 * Keep the ASF firmware running if up.
6088 if (sc->bge_asf_mode & ASF_STACKUP)
6089 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6091 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6093 /* Free the RX lists. */
6094 bge_free_rx_ring_std(sc);
6096 /* Free jumbo RX list. */
6097 if (BGE_IS_JUMBO_CAPABLE(sc))
6098 bge_free_rx_ring_jumbo(sc);
6100 /* Free TX buffers. */
6101 bge_free_tx_ring(sc);
6103 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
6105 /* Clear MAC's link state (PHY may still have link UP). */
6106 if (bootverbose && sc->bge_link)
6107 if_printf(sc->bge_ifp, "link DOWN\n");
6110 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
6114 * Stop all chip I/O so that the kernel's probe routines don't
6115 * get confused by errant DMAs when rebooting.
6118 bge_shutdown(device_t dev)
6120 struct bge_softc *sc;
6122 sc = device_get_softc(dev);
6131 bge_suspend(device_t dev)
6133 struct bge_softc *sc;
6135 sc = device_get_softc(dev);
6144 bge_resume(device_t dev)
6146 struct bge_softc *sc;
6149 sc = device_get_softc(dev);
6152 if (if_getflags(ifp) & IFF_UP) {
6153 bge_init_locked(sc);
6154 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
6155 bge_start_locked(ifp);
6163 bge_link_upd(struct bge_softc *sc)
6165 struct mii_data *mii;
6166 uint32_t link, status;
6168 BGE_LOCK_ASSERT(sc);
6170 /* Clear 'pending link event' flag. */
6171 sc->bge_link_evt = 0;
6174 * Process link state changes.
6175 * Grrr. The link status word in the status block does
6176 * not work correctly on the BCM5700 rev AX and BX chips,
6177 * according to all available information. Hence, we have
6178 * to enable MII interrupts in order to properly obtain
6179 * async link changes. Unfortunately, this also means that
6180 * we have to read the MAC status register to detect link
6181 * changes, thereby adding an additional register access to
6182 * the interrupt handler.
6184 * XXX: perhaps link state detection procedure used for
6185 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
6188 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6189 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
6190 status = CSR_READ_4(sc, BGE_MAC_STS);
6191 if (status & BGE_MACSTAT_MI_INTERRUPT) {
6192 mii = device_get_softc(sc->bge_miibus);
6194 if (!sc->bge_link &&
6195 mii->mii_media_status & IFM_ACTIVE &&
6196 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6199 if_printf(sc->bge_ifp, "link UP\n");
6200 } else if (sc->bge_link &&
6201 (!(mii->mii_media_status & IFM_ACTIVE) ||
6202 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6205 if_printf(sc->bge_ifp, "link DOWN\n");
6208 /* Clear the interrupt. */
6209 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
6210 BGE_EVTENB_MI_INTERRUPT);
6211 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
6213 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
6214 BRGPHY_MII_IMR, BRGPHY_INTRS);
6219 if (sc->bge_flags & BGE_FLAG_TBI) {
6220 status = CSR_READ_4(sc, BGE_MAC_STS);
6221 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
6222 if (!sc->bge_link) {
6224 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
6225 BGE_CLRBIT(sc, BGE_MAC_MODE,
6226 BGE_MACMODE_TBI_SEND_CFGS);
6229 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
6231 if_printf(sc->bge_ifp, "link UP\n");
6232 if_link_state_change(sc->bge_ifp,
6235 } else if (sc->bge_link) {
6238 if_printf(sc->bge_ifp, "link DOWN\n");
6239 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
6241 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
6243 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
6244 * in status word always set. Workaround this bug by reading
6245 * PHY link status directly.
6247 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
6249 if (link != sc->bge_link ||
6250 sc->bge_asicrev == BGE_ASICREV_BCM5700) {
6251 mii = device_get_softc(sc->bge_miibus);
6253 if (!sc->bge_link &&
6254 mii->mii_media_status & IFM_ACTIVE &&
6255 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6258 if_printf(sc->bge_ifp, "link UP\n");
6259 } else if (sc->bge_link &&
6260 (!(mii->mii_media_status & IFM_ACTIVE) ||
6261 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6264 if_printf(sc->bge_ifp, "link DOWN\n");
6269 * For controllers that call mii_tick, we have to poll
6272 mii = device_get_softc(sc->bge_miibus);
6274 bge_miibus_statchg(sc->bge_dev);
6277 /* Disable MAC attention when link is up. */
6278 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
6279 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
6280 BGE_MACSTAT_LINK_CHANGED);
6284 bge_add_sysctls(struct bge_softc *sc)
6286 struct sysctl_ctx_list *ctx;
6287 struct sysctl_oid_list *children;
6290 ctx = device_get_sysctl_ctx(sc->bge_dev);
6291 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
6293 #ifdef BGE_REGISTER_DEBUG
6294 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
6295 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
6296 "Debug Information");
6298 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
6299 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
6300 "MAC Register Read");
6302 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read",
6303 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I",
6304 "APE Register Read");
6306 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
6307 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
6312 unit = device_get_unit(sc->bge_dev);
6314 * A common design characteristic for many Broadcom client controllers
6315 * is that they only support a single outstanding DMA read operation
6316 * on the PCIe bus. This means that it will take twice as long to fetch
6317 * a TX frame that is split into header and payload buffers as it does
6318 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
6319 * these controllers, coalescing buffers to reduce the number of memory
6320 * reads is effective way to get maximum performance(about 940Mbps).
6321 * Without collapsing TX buffers the maximum TCP bulk transfer
6322 * performance is about 850Mbps. However forcing coalescing mbufs
6323 * consumes a lot of CPU cycles, so leave it off by default.
6325 sc->bge_forced_collapse = 0;
6326 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
6327 CTLFLAG_RWTUN, &sc->bge_forced_collapse, 0,
6328 "Number of fragmented TX buffers of a frame allowed before "
6329 "forced collapsing");
6332 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi",
6333 CTLFLAG_RDTUN, &sc->bge_msi, 0, "Enable MSI");
6336 * It seems all Broadcom controllers have a bug that can generate UDP
6337 * datagrams with checksum value 0 when TX UDP checksum offloading is
6338 * enabled. Generating UDP checksum value 0 is RFC 768 violation.
6339 * Even though the probability of generating such UDP datagrams is
6340 * low, I don't want to see FreeBSD boxes to inject such datagrams
6341 * into network so disable UDP checksum offloading by default. Users
6342 * still override this behavior by setting a sysctl variable,
6343 * dev.bge.0.forced_udpcsum.
6345 sc->bge_forced_udpcsum = 0;
6346 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum",
6347 CTLFLAG_RWTUN, &sc->bge_forced_udpcsum, 0,
6348 "Enable UDP checksum offloading even if controller can "
6349 "generate UDP checksum value 0");
6351 if (BGE_IS_5705_PLUS(sc))
6352 bge_add_sysctl_stats_regs(sc, ctx, children);
6354 bge_add_sysctl_stats(sc, ctx, children);
6357 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
6358 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
6359 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
6363 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6364 struct sysctl_oid_list *parent)
6366 struct sysctl_oid *tree;
6367 struct sysctl_oid_list *children, *schildren;
6369 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6370 NULL, "BGE Statistics");
6371 schildren = children = SYSCTL_CHILDREN(tree);
6372 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
6373 children, COSFramesDroppedDueToFilters,
6374 "FramesDroppedDueToFilters");
6375 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
6376 children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
6377 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
6378 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
6379 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
6380 children, nicNoMoreRxBDs, "NoMoreRxBDs");
6381 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
6382 children, ifInDiscards, "InputDiscards");
6383 BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
6384 children, ifInErrors, "InputErrors");
6385 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
6386 children, nicRecvThresholdHit, "RecvThresholdHit");
6387 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
6388 children, nicDmaReadQueueFull, "DmaReadQueueFull");
6389 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
6390 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
6391 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
6392 children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
6393 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
6394 children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
6395 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
6396 children, nicRingStatusUpdate, "RingStatusUpdate");
6397 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
6398 children, nicInterrupts, "Interrupts");
6399 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
6400 children, nicAvoidedInterrupts, "AvoidedInterrupts");
6401 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
6402 children, nicSendThresholdHit, "SendThresholdHit");
6404 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
6405 NULL, "BGE RX Statistics");
6406 children = SYSCTL_CHILDREN(tree);
6407 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
6408 children, rxstats.ifHCInOctets, "ifHCInOctets");
6409 BGE_SYSCTL_STAT(sc, ctx, "Fragments",
6410 children, rxstats.etherStatsFragments, "Fragments");
6411 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
6412 children, rxstats.ifHCInUcastPkts, "UnicastPkts");
6413 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
6414 children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
6415 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
6416 children, rxstats.dot3StatsFCSErrors, "FCSErrors");
6417 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
6418 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
6419 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
6420 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
6421 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
6422 children, rxstats.xoffPauseFramesReceived,
6423 "xoffPauseFramesReceived");
6424 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
6425 children, rxstats.macControlFramesReceived,
6426 "ControlFramesReceived");
6427 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
6428 children, rxstats.xoffStateEntered, "xoffStateEntered");
6429 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
6430 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
6431 BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
6432 children, rxstats.etherStatsJabbers, "Jabbers");
6433 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
6434 children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
6435 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
6436 children, rxstats.inRangeLengthError, "inRangeLengthError");
6437 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
6438 children, rxstats.outRangeLengthError, "outRangeLengthError");
6440 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
6441 NULL, "BGE TX Statistics");
6442 children = SYSCTL_CHILDREN(tree);
6443 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
6444 children, txstats.ifHCOutOctets, "ifHCOutOctets");
6445 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
6446 children, txstats.etherStatsCollisions, "Collisions");
6447 BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
6448 children, txstats.outXonSent, "XonSent");
6449 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
6450 children, txstats.outXoffSent, "XoffSent");
6451 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
6452 children, txstats.flowControlDone, "flowControlDone");
6453 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
6454 children, txstats.dot3StatsInternalMacTransmitErrors,
6455 "InternalMacTransmitErrors");
6456 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
6457 children, txstats.dot3StatsSingleCollisionFrames,
6458 "SingleCollisionFrames");
6459 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
6460 children, txstats.dot3StatsMultipleCollisionFrames,
6461 "MultipleCollisionFrames");
6462 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
6463 children, txstats.dot3StatsDeferredTransmissions,
6464 "DeferredTransmissions");
6465 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
6466 children, txstats.dot3StatsExcessiveCollisions,
6467 "ExcessiveCollisions");
6468 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
6469 children, txstats.dot3StatsLateCollisions,
6471 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
6472 children, txstats.ifHCOutUcastPkts, "UnicastPkts");
6473 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
6474 children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
6475 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
6476 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
6477 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
6478 children, txstats.dot3StatsCarrierSenseErrors,
6479 "CarrierSenseErrors");
6480 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
6481 children, txstats.ifOutDiscards, "Discards");
6482 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
6483 children, txstats.ifOutErrors, "Errors");
6486 #undef BGE_SYSCTL_STAT
6488 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
6489 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
6492 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6493 struct sysctl_oid_list *parent)
6495 struct sysctl_oid *tree;
6496 struct sysctl_oid_list *child, *schild;
6497 struct bge_mac_stats *stats;
6499 stats = &sc->bge_mac_stats;
6500 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6501 NULL, "BGE Statistics");
6502 schild = child = SYSCTL_CHILDREN(tree);
6503 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters",
6504 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters");
6505 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull",
6506 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full");
6507 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull",
6508 &stats->DmaWriteHighPriQueueFull,
6509 "NIC DMA Write High Priority Queue Full");
6510 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs",
6511 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors");
6512 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards",
6513 &stats->InputDiscards, "Discarded Input Frames");
6514 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors",
6515 &stats->InputErrors, "Input Errors");
6516 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit",
6517 &stats->RecvThresholdHit, "NIC Recv Threshold Hit");
6519 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD,
6520 NULL, "BGE RX Statistics");
6521 child = SYSCTL_CHILDREN(tree);
6522 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets",
6523 &stats->ifHCInOctets, "Inbound Octets");
6524 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments",
6525 &stats->etherStatsFragments, "Fragments");
6526 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6527 &stats->ifHCInUcastPkts, "Inbound Unicast Packets");
6528 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6529 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets");
6530 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6531 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets");
6532 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors",
6533 &stats->dot3StatsFCSErrors, "FCS Errors");
6534 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors",
6535 &stats->dot3StatsAlignmentErrors, "Alignment Errors");
6536 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived",
6537 &stats->xonPauseFramesReceived, "XON Pause Frames Received");
6538 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived",
6539 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received");
6540 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived",
6541 &stats->macControlFramesReceived, "MAC Control Frames Received");
6542 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered",
6543 &stats->xoffStateEntered, "XOFF State Entered");
6544 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong",
6545 &stats->dot3StatsFramesTooLong, "Frames Too Long");
6546 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers",
6547 &stats->etherStatsJabbers, "Jabbers");
6548 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts",
6549 &stats->etherStatsUndersizePkts, "Undersized Packets");
6551 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD,
6552 NULL, "BGE TX Statistics");
6553 child = SYSCTL_CHILDREN(tree);
6554 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets",
6555 &stats->ifHCOutOctets, "Outbound Octets");
6556 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions",
6557 &stats->etherStatsCollisions, "TX Collisions");
6558 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent",
6559 &stats->outXonSent, "XON Sent");
6560 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent",
6561 &stats->outXoffSent, "XOFF Sent");
6562 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors",
6563 &stats->dot3StatsInternalMacTransmitErrors,
6564 "Internal MAC TX Errors");
6565 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames",
6566 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames");
6567 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames",
6568 &stats->dot3StatsMultipleCollisionFrames,
6569 "Multiple Collision Frames");
6570 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions",
6571 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions");
6572 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions",
6573 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions");
6574 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions",
6575 &stats->dot3StatsLateCollisions, "Late Collisions");
6576 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6577 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets");
6578 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6579 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets");
6580 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6581 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets");
6584 #undef BGE_SYSCTL_STAT_ADD64
6587 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
6589 struct bge_softc *sc;
6593 sc = (struct bge_softc *)arg1;
6595 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
6596 offsetof(bge_hostaddr, bge_addr_lo));
6597 return (sysctl_handle_int(oidp, &result, 0, req));
6600 #ifdef BGE_REGISTER_DEBUG
6602 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
6604 struct bge_softc *sc;
6606 int error, result, sbsz;
6610 error = sysctl_handle_int(oidp, &result, 0, req);
6611 if (error || (req->newptr == NULL))
6615 sc = (struct bge_softc *)arg1;
6617 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6618 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
6619 sbsz = BGE_STATUS_BLK_SZ;
6622 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
6623 printf("Status Block:\n");
6625 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6626 sc->bge_cdata.bge_status_map,
6627 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6628 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) {
6630 for (j = 0; j < 8; j++)
6631 printf(" %04x", sbdata[i++]);
6635 printf("Registers:\n");
6636 for (i = 0x800; i < 0xA00; ) {
6638 for (j = 0; j < 8; j++) {
6639 printf(" %08x", CSR_READ_4(sc, i));
6646 printf("Hardware Flags:\n");
6647 if (BGE_IS_5717_PLUS(sc))
6648 printf(" - 5717 Plus\n");
6649 if (BGE_IS_5755_PLUS(sc))
6650 printf(" - 5755 Plus\n");
6651 if (BGE_IS_575X_PLUS(sc))
6652 printf(" - 575X Plus\n");
6653 if (BGE_IS_5705_PLUS(sc))
6654 printf(" - 5705 Plus\n");
6655 if (BGE_IS_5714_FAMILY(sc))
6656 printf(" - 5714 Family\n");
6657 if (BGE_IS_5700_FAMILY(sc))
6658 printf(" - 5700 Family\n");
6659 if (sc->bge_flags & BGE_FLAG_JUMBO)
6660 printf(" - Supports Jumbo Frames\n");
6661 if (sc->bge_flags & BGE_FLAG_PCIX)
6662 printf(" - PCI-X Bus\n");
6663 if (sc->bge_flags & BGE_FLAG_PCIE)
6664 printf(" - PCI Express Bus\n");
6665 if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
6666 printf(" - No 3 LEDs\n");
6667 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
6668 printf(" - RX Alignment Bug\n");
6675 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6677 struct bge_softc *sc;
6683 error = sysctl_handle_int(oidp, &result, 0, req);
6684 if (error || (req->newptr == NULL))
6687 if (result < 0x8000) {
6688 sc = (struct bge_softc *)arg1;
6689 val = CSR_READ_4(sc, result);
6690 printf("reg 0x%06X = 0x%08X\n", result, val);
6697 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS)
6699 struct bge_softc *sc;
6705 error = sysctl_handle_int(oidp, &result, 0, req);
6706 if (error || (req->newptr == NULL))
6709 if (result < 0x8000) {
6710 sc = (struct bge_softc *)arg1;
6711 val = APE_READ_4(sc, result);
6712 printf("reg 0x%06X = 0x%08X\n", result, val);
6719 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
6721 struct bge_softc *sc;
6727 error = sysctl_handle_int(oidp, &result, 0, req);
6728 if (error || (req->newptr == NULL))
6731 if (result < 0x8000) {
6732 sc = (struct bge_softc *)arg1;
6733 val = bge_readmem_ind(sc, result);
6734 printf("mem 0x%06X = 0x%08X\n", result, val);
6742 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
6745 if (sc->bge_flags & BGE_FLAG_EADDR)
6748 OF_getetheraddr(sc->bge_dev, ether_addr);
6756 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
6760 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
6761 if ((mac_addr >> 16) == 0x484b) {
6762 ether_addr[0] = (uint8_t)(mac_addr >> 8);
6763 ether_addr[1] = (uint8_t)mac_addr;
6764 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
6765 ether_addr[2] = (uint8_t)(mac_addr >> 24);
6766 ether_addr[3] = (uint8_t)(mac_addr >> 16);
6767 ether_addr[4] = (uint8_t)(mac_addr >> 8);
6768 ether_addr[5] = (uint8_t)mac_addr;
6775 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
6777 int mac_offset = BGE_EE_MAC_OFFSET;
6779 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6780 mac_offset = BGE_EE_MAC_OFFSET_5906;
6782 return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
6787 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
6790 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6793 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
6798 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
6800 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
6801 /* NOTE: Order is critical */
6804 bge_get_eaddr_nvram,
6805 bge_get_eaddr_eeprom,
6808 const bge_eaddr_fcn_t *func;
6810 for (func = bge_eaddr_funcs; *func != NULL; ++func) {
6811 if ((*func)(sc, eaddr) == 0)
6814 return (*func == NULL ? ENXIO : 0);
6818 bge_get_counter(if_t ifp, ift_counter cnt)
6820 struct bge_softc *sc;
6821 struct bge_mac_stats *stats;
6823 sc = if_getsoftc(ifp);
6824 if (!BGE_IS_5705_PLUS(sc))
6825 return (if_get_counter_default(ifp, cnt));
6826 stats = &sc->bge_mac_stats;
6829 case IFCOUNTER_IERRORS:
6830 return (stats->NoMoreRxBDs + stats->InputDiscards +
6831 stats->InputErrors);
6832 case IFCOUNTER_COLLISIONS:
6833 return (stats->etherStatsCollisions);
6835 return (if_get_counter_default(ifp, cnt));
6841 bge_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6843 struct bge_softc *sc;
6845 sc = if_getsoftc(ifp);
6847 *nrxr = sc->bge_return_ring_cnt;
6848 *ncl = DEBUGNET_MAX_IN_FLIGHT;
6849 if ((sc->bge_flags & BGE_FLAG_JUMBO_STD) != 0 &&
6850 (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
6851 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)))
6852 *clsize = MJUM9BYTES;
6859 bge_debugnet_event(if_t ifp __unused, enum debugnet_ev event __unused)
6864 bge_debugnet_transmit(if_t ifp, struct mbuf *m)
6866 struct bge_softc *sc;
6870 sc = if_getsoftc(ifp);
6871 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6875 prodidx = sc->bge_tx_prodidx;
6876 error = bge_encap(sc, &m, &prodidx);
6878 bge_start_tx(sc, prodidx);
6883 bge_debugnet_poll(if_t ifp, int count)
6885 struct bge_softc *sc;
6886 uint32_t rx_prod, tx_cons;
6888 sc = if_getsoftc(ifp);
6889 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6893 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6894 sc->bge_cdata.bge_status_map,
6895 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6897 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
6898 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
6900 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6901 sc->bge_cdata.bge_status_map,
6902 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
6904 (void)bge_rxeof(sc, rx_prod, 0);
6905 bge_txeof(sc, tx_cons);
6908 #endif /* DEBUGNET */