sys/dev/bge/if_bge.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-4-Clause
   3  *
   4  * Copyright (c) 2001 Wind River Systems
   5  * Copyright (c) 1997, 1998, 1999, 2001
   6  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed by Bill Paul.
  19  * 4. Neither the name of the author nor the names of any co-contributors
  20  *    may be used to endorse or promote products derived from this software
  21  *    without specific prior written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  27  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  33  * THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35
  36 #include <sys/cdefs.h>
  37 __FBSDID("$FreeBSD$");
  38
  39 /*
  40  * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver
  41  *
  42  * The Broadcom BCM5700 is based on technology originally developed by
  43  * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet
  44  * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
  45  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  46  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  47  * frames, highly configurable RX filtering, and 16 RX and TX queues
  48  * (which, along with RX filter rules, can be used for QOS applications).
  49  * Other features, such as TCP segmentation, may be available as part
  50  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  51  * firmware images can be stored in hardware and need not be compiled
  52  * into the driver.
  53  *
  54  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  55  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  56  *
  57  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  58  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  59  * does not support external SSRAM.
  60  *
  61  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  62  * brand name, which is functionally similar but lacks PCI-X support.
  63  *
  64  * Without external SSRAM, you can only have at most 4 TX rings,
  65  * and the use of the mini RX ring is disabled. This seems to imply
  66  * that these features are simply not available on the BCM5701. As a
  67  * result, this driver does not implement any support for the mini RX
  68  * ring.
  69  */
  70
  71 #ifdef HAVE_KERNEL_OPTION_HEADERS
  72 #include "opt_device_polling.h"
  73 #endif
  74
  75 #include <sys/param.h>
  76 #include <sys/endian.h>
  77 #include <sys/systm.h>
  78 #include <sys/sockio.h>
  79 #include <sys/mbuf.h>
  80 #include <sys/malloc.h>
  81 #include <sys/kernel.h>
  82 #include <sys/module.h>
  83 #include <sys/socket.h>
  84 #include <sys/sysctl.h>
  85 #include <sys/taskqueue.h>
  86
  87 #include <net/debugnet.h>
  88 #include <net/if.h>
  89 #include <net/if_var.h>
  90 #include <net/if_arp.h>
  91 #include <net/ethernet.h>
  92 #include <net/if_dl.h>
  93 #include <net/if_media.h>
  94
  95 #include <net/bpf.h>
  96
  97 #include <net/if_types.h>
  98 #include <net/if_vlan_var.h>
  99
 100 #include <netinet/in_systm.h>
 101 #include <netinet/in.h>
 102 #include <netinet/ip.h>
 103 #include <netinet/tcp.h>
 104
 105 #include <machine/bus.h>
 106 #include <machine/resource.h>
 107 #include <sys/bus.h>
 108 #include <sys/rman.h>
 109
 110 #include <dev/mii/mii.h>
 111 #include <dev/mii/miivar.h>
 112 #include "miidevs.h"
 113 #include <dev/mii/brgphyreg.h>
 114
 115 #include <dev/pci/pcireg.h>
 116 #include <dev/pci/pcivar.h>
 117
 118 #include <dev/bge/if_bgereg.h>
 119
 120 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP)
 121 #define ETHER_MIN_NOPAD         (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
 122
 123 MODULE_DEPEND(bge, pci, 1, 1, 1);
 124 MODULE_DEPEND(bge, ether, 1, 1, 1);
 125 MODULE_DEPEND(bge, miibus, 1, 1, 1);
 126
 127 /* "device miibus" required.  See GENERIC if you get errors here. */
 128 #include "miibus_if.h"
 129
 130 /*
 131  * Various supported device vendors/types and their names. Note: the
 132  * spec seems to indicate that the hardware still has Alteon's vendor
 133  * ID burned into it, though it will always be overriden by the vendor
 134  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 135  */
 136 static const struct bge_type {
 137         uint16_t        bge_vid;
 138         uint16_t        bge_did;
 139 } bge_devs[] = {
 140         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5700 },
 141         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5701 },
 142
 143         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1000 },
 144         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1002 },
 145         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC9100 },
 146
 147         { APPLE_VENDORID,       APPLE_DEVICE_BCM5701 },
 148
 149         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5700 },
 150         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5701 },
 151         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702 },
 152         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702_ALT },
 153         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702X },
 154         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703 },
 155         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703_ALT },
 156         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703X },
 157         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704C },
 158         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S },
 159         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S_ALT },
 160         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705 },
 161         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705F },
 162         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705K },
 163         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M },
 164         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M_ALT },
 165         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714C },
 166         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714S },
 167         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715 },
 168         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715S },
 169         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5717 },
 170         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5717C },
 171         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5718 },
 172         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5719 },
 173         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5720 },
 174         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5721 },
 175         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5722 },
 176         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5723 },
 177         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5725 },
 178         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5727 },
 179         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750 },
 180         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750M },
 181         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751 },
 182         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751F },
 183         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751M },
 184         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752 },
 185         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752M },
 186         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753 },
 187         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753F },
 188         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753M },
 189         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754 },
 190         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754M },
 191         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755 },
 192         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755M },
 193         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5756 },
 194         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761 },
 195         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761E },
 196         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761S },
 197         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761SE },
 198         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5762 },
 199         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5764 },
 200         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780 },
 201         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780S },
 202         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5781 },
 203         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5782 },
 204         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5784 },
 205         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785F },
 206         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785G },
 207         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5786 },
 208         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787 },
 209         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787F },
 210         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787M },
 211         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5788 },
 212         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5789 },
 213         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901 },
 214         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901A2 },
 215         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5903M },
 216         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906 },
 217         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906M },
 218         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57760 },
 219         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57761 },
 220         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57762 },
 221         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57764 },
 222         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57765 },
 223         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57766 },
 224         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57767 },
 225         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57780 },
 226         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57781 },
 227         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57782 },
 228         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57785 },
 229         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57786 },
 230         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57787 },
 231         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57788 },
 232         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57790 },
 233         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57791 },
 234         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57795 },
 235
 236         { SK_VENDORID,          SK_DEVICEID_ALTIMA },
 237
 238         { TC_VENDORID,          TC_DEVICEID_3C996 },
 239
 240         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE4 },
 241         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE5 },
 242         { 0, 0 }
 243 };
 244
 245 static const struct bge_vendor {
 246         uint16_t        v_id;
 247         const char      *v_name;
 248 } bge_vendors[] = {
 249         { ALTEON_VENDORID,      "Alteon" },
 250         { ALTIMA_VENDORID,      "Altima" },
 251         { APPLE_VENDORID,       "Apple" },
 252         { BCOM_VENDORID,        "Broadcom" },
 253         { SK_VENDORID,          "SysKonnect" },
 254         { TC_VENDORID,          "3Com" },
 255         { FJTSU_VENDORID,       "Fujitsu" },
 256         { 0, NULL }
 257 };
 258
 259 static const struct bge_revision {
 260         uint32_t        br_chipid;
 261         const char      *br_name;
 262 } bge_revisions[] = {
 263         { BGE_CHIPID_BCM5700_A0,        "BCM5700 A0" },
 264         { BGE_CHIPID_BCM5700_A1,        "BCM5700 A1" },
 265         { BGE_CHIPID_BCM5700_B0,        "BCM5700 B0" },
 266         { BGE_CHIPID_BCM5700_B1,        "BCM5700 B1" },
 267         { BGE_CHIPID_BCM5700_B2,        "BCM5700 B2" },
 268         { BGE_CHIPID_BCM5700_B3,        "BCM5700 B3" },
 269         { BGE_CHIPID_BCM5700_ALTIMA,    "BCM5700 Altima" },
 270         { BGE_CHIPID_BCM5700_C0,        "BCM5700 C0" },
 271         { BGE_CHIPID_BCM5701_A0,        "BCM5701 A0" },
 272         { BGE_CHIPID_BCM5701_B0,        "BCM5701 B0" },
 273         { BGE_CHIPID_BCM5701_B2,        "BCM5701 B2" },
 274         { BGE_CHIPID_BCM5701_B5,        "BCM5701 B5" },
 275         { BGE_CHIPID_BCM5703_A0,        "BCM5703 A0" },
 276         { BGE_CHIPID_BCM5703_A1,        "BCM5703 A1" },
 277         { BGE_CHIPID_BCM5703_A2,        "BCM5703 A2" },
 278         { BGE_CHIPID_BCM5703_A3,        "BCM5703 A3" },
 279         { BGE_CHIPID_BCM5703_B0,        "BCM5703 B0" },
 280         { BGE_CHIPID_BCM5704_A0,        "BCM5704 A0" },
 281         { BGE_CHIPID_BCM5704_A1,        "BCM5704 A1" },
 282         { BGE_CHIPID_BCM5704_A2,        "BCM5704 A2" },
 283         { BGE_CHIPID_BCM5704_A3,        "BCM5704 A3" },
 284         { BGE_CHIPID_BCM5704_B0,        "BCM5704 B0" },
 285         { BGE_CHIPID_BCM5705_A0,        "BCM5705 A0" },
 286         { BGE_CHIPID_BCM5705_A1,        "BCM5705 A1" },
 287         { BGE_CHIPID_BCM5705_A2,        "BCM5705 A2" },
 288         { BGE_CHIPID_BCM5705_A3,        "BCM5705 A3" },
 289         { BGE_CHIPID_BCM5750_A0,        "BCM5750 A0" },
 290         { BGE_CHIPID_BCM5750_A1,        "BCM5750 A1" },
 291         { BGE_CHIPID_BCM5750_A3,        "BCM5750 A3" },
 292         { BGE_CHIPID_BCM5750_B0,        "BCM5750 B0" },
 293         { BGE_CHIPID_BCM5750_B1,        "BCM5750 B1" },
 294         { BGE_CHIPID_BCM5750_C0,        "BCM5750 C0" },
 295         { BGE_CHIPID_BCM5750_C1,        "BCM5750 C1" },
 296         { BGE_CHIPID_BCM5750_C2,        "BCM5750 C2" },
 297         { BGE_CHIPID_BCM5714_A0,        "BCM5714 A0" },
 298         { BGE_CHIPID_BCM5752_A0,        "BCM5752 A0" },
 299         { BGE_CHIPID_BCM5752_A1,        "BCM5752 A1" },
 300         { BGE_CHIPID_BCM5752_A2,        "BCM5752 A2" },
 301         { BGE_CHIPID_BCM5714_B0,        "BCM5714 B0" },
 302         { BGE_CHIPID_BCM5714_B3,        "BCM5714 B3" },
 303         { BGE_CHIPID_BCM5715_A0,        "BCM5715 A0" },
 304         { BGE_CHIPID_BCM5715_A1,        "BCM5715 A1" },
 305         { BGE_CHIPID_BCM5715_A3,        "BCM5715 A3" },
 306         { BGE_CHIPID_BCM5717_A0,        "BCM5717 A0" },
 307         { BGE_CHIPID_BCM5717_B0,        "BCM5717 B0" },
 308         { BGE_CHIPID_BCM5717_C0,        "BCM5717 C0" },
 309         { BGE_CHIPID_BCM5719_A0,        "BCM5719 A0" },
 310         { BGE_CHIPID_BCM5720_A0,        "BCM5720 A0" },
 311         { BGE_CHIPID_BCM5755_A0,        "BCM5755 A0" },
 312         { BGE_CHIPID_BCM5755_A1,        "BCM5755 A1" },
 313         { BGE_CHIPID_BCM5755_A2,        "BCM5755 A2" },
 314         { BGE_CHIPID_BCM5722_A0,        "BCM5722 A0" },
 315         { BGE_CHIPID_BCM5761_A0,        "BCM5761 A0" },
 316         { BGE_CHIPID_BCM5761_A1,        "BCM5761 A1" },
 317         { BGE_CHIPID_BCM5762_A0,        "BCM5762 A0" },
 318         { BGE_CHIPID_BCM5784_A0,        "BCM5784 A0" },
 319         { BGE_CHIPID_BCM5784_A1,        "BCM5784 A1" },
 320         /* 5754 and 5787 share the same ASIC ID */
 321         { BGE_CHIPID_BCM5787_A0,        "BCM5754/5787 A0" },
 322         { BGE_CHIPID_BCM5787_A1,        "BCM5754/5787 A1" },
 323         { BGE_CHIPID_BCM5787_A2,        "BCM5754/5787 A2" },
 324         { BGE_CHIPID_BCM5906_A1,        "BCM5906 A1" },
 325         { BGE_CHIPID_BCM5906_A2,        "BCM5906 A2" },
 326         { BGE_CHIPID_BCM57765_A0,       "BCM57765 A0" },
 327         { BGE_CHIPID_BCM57765_B0,       "BCM57765 B0" },
 328         { BGE_CHIPID_BCM57780_A0,       "BCM57780 A0" },
 329         { BGE_CHIPID_BCM57780_A1,       "BCM57780 A1" },
 330         { 0, NULL }
 331 };
 332
 333 /*
 334  * Some defaults for major revisions, so that newer steppings
 335  * that we don't know about have a shot at working.
 336  */
 337 static const struct bge_revision bge_majorrevs[] = {
 338         { BGE_ASICREV_BCM5700,          "unknown BCM5700" },
 339         { BGE_ASICREV_BCM5701,          "unknown BCM5701" },
 340         { BGE_ASICREV_BCM5703,          "unknown BCM5703" },
 341         { BGE_ASICREV_BCM5704,          "unknown BCM5704" },
 342         { BGE_ASICREV_BCM5705,          "unknown BCM5705" },
 343         { BGE_ASICREV_BCM5750,          "unknown BCM5750" },
 344         { BGE_ASICREV_BCM5714_A0,       "unknown BCM5714" },
 345         { BGE_ASICREV_BCM5752,          "unknown BCM5752" },
 346         { BGE_ASICREV_BCM5780,          "unknown BCM5780" },
 347         { BGE_ASICREV_BCM5714,          "unknown BCM5714" },
 348         { BGE_ASICREV_BCM5755,          "unknown BCM5755" },
 349         { BGE_ASICREV_BCM5761,          "unknown BCM5761" },
 350         { BGE_ASICREV_BCM5784,          "unknown BCM5784" },
 351         { BGE_ASICREV_BCM5785,          "unknown BCM5785" },
 352         /* 5754 and 5787 share the same ASIC ID */
 353         { BGE_ASICREV_BCM5787,          "unknown BCM5754/5787" },
 354         { BGE_ASICREV_BCM5906,          "unknown BCM5906" },
 355         { BGE_ASICREV_BCM57765,         "unknown BCM57765" },
 356         { BGE_ASICREV_BCM57766,         "unknown BCM57766" },
 357         { BGE_ASICREV_BCM57780,         "unknown BCM57780" },
 358         { BGE_ASICREV_BCM5717,          "unknown BCM5717" },
 359         { BGE_ASICREV_BCM5719,          "unknown BCM5719" },
 360         { BGE_ASICREV_BCM5720,          "unknown BCM5720" },
 361         { BGE_ASICREV_BCM5762,          "unknown BCM5762" },
 362         { 0, NULL }
 363 };
 364
 365 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 366 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 367 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 368 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 369 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 370 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 371 #define BGE_IS_5717_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5717_PLUS)
 372 #define BGE_IS_57765_PLUS(sc)           ((sc)->bge_flags & BGE_FLAG_57765_PLUS)
 373
 374 static uint32_t bge_chipid(device_t);
 375 static const struct bge_vendor * bge_lookup_vendor(uint16_t);
 376 static const struct bge_revision * bge_lookup_rev(uint32_t);
 377
 378 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 379
 380 static int bge_probe(device_t);
 381 static int bge_attach(device_t);
 382 static int bge_detach(device_t);
 383 static int bge_suspend(device_t);
 384 static int bge_resume(device_t);
 385 static void bge_release_resources(struct bge_softc *);
 386 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 387 static int bge_dma_alloc(struct bge_softc *);
 388 static void bge_dma_free(struct bge_softc *);
 389 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t,
 390     bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
 391
 392 static void bge_devinfo(struct bge_softc *);
 393 static int bge_mbox_reorder(struct bge_softc *);
 394
 395 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
 396 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 397 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 398 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 399 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
 400
 401 static void bge_txeof(struct bge_softc *, uint16_t);
 402 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
 403 static int bge_rxeof(struct bge_softc *, uint16_t, int);
 404
 405 static void bge_asf_driver_up (struct bge_softc *);
 406 static void bge_tick(void *);
 407 static void bge_stats_clear_regs(struct bge_softc *);
 408 static void bge_stats_update(struct bge_softc *);
 409 static void bge_stats_update_regs(struct bge_softc *);
 410 static struct mbuf *bge_check_short_dma(struct mbuf *);
 411 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
 412     uint16_t *, uint16_t *);
 413 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 414
 415 static void bge_intr(void *);
 416 static int bge_msi_intr(void *);
 417 static void bge_intr_task(void *, int);
 418 static void bge_start(if_t);
 419 static void bge_start_locked(if_t);
 420 static void bge_start_tx(struct bge_softc *, uint32_t);
 421 static int bge_ioctl(if_t, u_long, caddr_t);
 422 static void bge_init_locked(struct bge_softc *);
 423 static void bge_init(void *);
 424 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
 425 static void bge_stop(struct bge_softc *);
 426 static void bge_watchdog(struct bge_softc *);
 427 static int bge_shutdown(device_t);
 428 static int bge_ifmedia_upd_locked(if_t);
 429 static int bge_ifmedia_upd(if_t);
 430 static void bge_ifmedia_sts(if_t, struct ifmediareq *);
 431 static uint64_t bge_get_counter(if_t, ift_counter);
 432
 433 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 434 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 435
 436 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
 437 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
 438
 439 static void bge_setpromisc(struct bge_softc *);
 440 static void bge_setmulti(struct bge_softc *);
 441 static void bge_setvlan(struct bge_softc *);
 442
 443 static __inline void bge_rxreuse_std(struct bge_softc *, int);
 444 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
 445 static int bge_newbuf_std(struct bge_softc *, int);
 446 static int bge_newbuf_jumbo(struct bge_softc *, int);
 447 static int bge_init_rx_ring_std(struct bge_softc *);
 448 static void bge_free_rx_ring_std(struct bge_softc *);
 449 static int bge_init_rx_ring_jumbo(struct bge_softc *);
 450 static void bge_free_rx_ring_jumbo(struct bge_softc *);
 451 static void bge_free_tx_ring(struct bge_softc *);
 452 static int bge_init_tx_ring(struct bge_softc *);
 453
 454 static int bge_chipinit(struct bge_softc *);
 455 static int bge_blockinit(struct bge_softc *);
 456 static uint32_t bge_dma_swap_options(struct bge_softc *);
 457
 458 static int bge_has_eaddr(struct bge_softc *);
 459 static uint32_t bge_readmem_ind(struct bge_softc *, int);
 460 static void bge_writemem_ind(struct bge_softc *, int, int);
 461 static void bge_writembx(struct bge_softc *, int, int);
 462 #ifdef notdef
 463 static uint32_t bge_readreg_ind(struct bge_softc *, int);
 464 #endif
 465 static void bge_writemem_direct(struct bge_softc *, int, int);
 466 static void bge_writereg_ind(struct bge_softc *, int, int);
 467
 468 static int bge_miibus_readreg(device_t, int, int);
 469 static int bge_miibus_writereg(device_t, int, int, int);
 470 static void bge_miibus_statchg(device_t);
 471 #ifdef DEVICE_POLLING
 472 static int bge_poll(if_t ifp, enum poll_cmd cmd, int count);
 473 #endif
 474
 475 #define BGE_RESET_SHUTDOWN      0
 476 #define BGE_RESET_START         1
 477 #define BGE_RESET_SUSPEND       2
 478 static void bge_sig_post_reset(struct bge_softc *, int);
 479 static void bge_sig_legacy(struct bge_softc *, int);
 480 static void bge_sig_pre_reset(struct bge_softc *, int);
 481 static void bge_stop_fw(struct bge_softc *);
 482 static int bge_reset(struct bge_softc *);
 483 static void bge_link_upd(struct bge_softc *);
 484
 485 static void bge_ape_lock_init(struct bge_softc *);
 486 static void bge_ape_read_fw_ver(struct bge_softc *);
 487 static int bge_ape_lock(struct bge_softc *, int);
 488 static void bge_ape_unlock(struct bge_softc *, int);
 489 static void bge_ape_send_event(struct bge_softc *, uint32_t);
 490 static void bge_ape_driver_state_change(struct bge_softc *, int);
 491
 492 /*
 493  * The BGE_REGISTER_DEBUG option is only for low-level debugging.  It may
 494  * leak information to untrusted users.  It is also known to cause alignment
 495  * traps on certain architectures.
 496  */
 497 #ifdef BGE_REGISTER_DEBUG
 498 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 499 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
 500 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS);
 501 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
 502 #endif
 503 static void bge_add_sysctls(struct bge_softc *);
 504 static void bge_add_sysctl_stats_regs(struct bge_softc *,
 505     struct sysctl_ctx_list *, struct sysctl_oid_list *);
 506 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *,
 507     struct sysctl_oid_list *);
 508 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
 509
 510 DEBUGNET_DEFINE(bge);
 511
 512 static device_method_t bge_methods[] = {
 513         /* Device interface */
 514         DEVMETHOD(device_probe,         bge_probe),
 515         DEVMETHOD(device_attach,        bge_attach),
 516         DEVMETHOD(device_detach,        bge_detach),
 517         DEVMETHOD(device_shutdown,      bge_shutdown),
 518         DEVMETHOD(device_suspend,       bge_suspend),
 519         DEVMETHOD(device_resume,        bge_resume),
 520
 521         /* MII interface */
 522         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 523         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 524         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 525
 526         DEVMETHOD_END
 527 };
 528
 529 static driver_t bge_driver = {
 530         "bge",
 531         bge_methods,
 532         sizeof(struct bge_softc)
 533 };
 534
 535 static devclass_t bge_devclass;
 536
 537 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
 538 MODULE_PNP_INFO("U16:vendor;U16:device", pci, bge, bge_devs,
 539     nitems(bge_devs) - 1);
 540 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 541
 542 static int bge_allow_asf = 1;
 543
 544 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
 545     "BGE driver parameters");
 546 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RDTUN, &bge_allow_asf, 0,
 547         "Allow ASF mode if available");
 548
 549 static int
 550 bge_has_eaddr(struct bge_softc *sc)
 551 {
 552         return (1);
 553 }
 554
 555 static uint32_t
 556 bge_readmem_ind(struct bge_softc *sc, int off)
 557 {
 558         device_t dev;
 559         uint32_t val;
 560
 561         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 562             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 563                 return (0);
 564
 565         dev = sc->bge_dev;
 566
 567         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 568         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 569         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 570         return (val);
 571 }
 572
 573 static void
 574 bge_writemem_ind(struct bge_softc *sc, int off, int val)
 575 {
 576         device_t dev;
 577
 578         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 579             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 580                 return;
 581
 582         dev = sc->bge_dev;
 583
 584         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 585         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 586         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 587 }
 588
 589 #ifdef notdef
 590 static uint32_t
 591 bge_readreg_ind(struct bge_softc *sc, int off)
 592 {
 593         device_t dev;
 594
 595         dev = sc->bge_dev;
 596
 597         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 598         return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 599 }
 600 #endif
 601
 602 static void
 603 bge_writereg_ind(struct bge_softc *sc, int off, int val)
 604 {
 605         device_t dev;
 606
 607         dev = sc->bge_dev;
 608
 609         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 610         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 611 }
 612
 613 static void
 614 bge_writemem_direct(struct bge_softc *sc, int off, int val)
 615 {
 616         CSR_WRITE_4(sc, off, val);
 617 }
 618
 619 static void
 620 bge_writembx(struct bge_softc *sc, int off, int val)
 621 {
 622         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 623                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 624
 625         CSR_WRITE_4(sc, off, val);
 626         if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0)
 627                 CSR_READ_4(sc, off);
 628 }
 629
 630 /*
 631  * Clear all stale locks and select the lock for this driver instance.
 632  */
 633 static void
 634 bge_ape_lock_init(struct bge_softc *sc)
 635 {
 636         uint32_t bit, regbase;
 637         int i;
 638
 639         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 640                 regbase = BGE_APE_LOCK_GRANT;
 641         else
 642                 regbase = BGE_APE_PER_LOCK_GRANT;
 643
 644         /* Clear any stale locks. */
 645         for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
 646                 switch (i) {
 647                 case BGE_APE_LOCK_PHY0:
 648                 case BGE_APE_LOCK_PHY1:
 649                 case BGE_APE_LOCK_PHY2:
 650                 case BGE_APE_LOCK_PHY3:
 651                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
 652                         break;
 653                 default:
 654                         if (sc->bge_func_addr == 0)
 655                                 bit = BGE_APE_LOCK_GRANT_DRIVER0;
 656                         else
 657                                 bit = (1 << sc->bge_func_addr);
 658                 }
 659                 APE_WRITE_4(sc, regbase + 4 * i, bit);
 660         }
 661
 662         /* Select the PHY lock based on the device's function number. */
 663         switch (sc->bge_func_addr) {
 664         case 0:
 665                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
 666                 break;
 667         case 1:
 668                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
 669                 break;
 670         case 2:
 671                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
 672                 break;
 673         case 3:
 674                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
 675                 break;
 676         default:
 677                 device_printf(sc->bge_dev,
 678                     "PHY lock not supported on this function\n");
 679         }
 680 }
 681
 682 /*
 683  * Check for APE firmware, set flags, and print version info.
 684  */
 685 static void
 686 bge_ape_read_fw_ver(struct bge_softc *sc)
 687 {
 688         const char *fwtype;
 689         uint32_t apedata, features;
 690
 691         /* Check for a valid APE signature in shared memory. */
 692         apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
 693         if (apedata != BGE_APE_SEG_SIG_MAGIC) {
 694                 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE;
 695                 return;
 696         }
 697
 698         /* Check if APE firmware is running. */
 699         apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
 700         if ((apedata & BGE_APE_FW_STATUS_READY) == 0) {
 701                 device_printf(sc->bge_dev, "APE signature found "
 702                     "but FW status not ready! 0x%08x\n", apedata);
 703                 return;
 704         }
 705
 706         sc->bge_mfw_flags |= BGE_MFW_ON_APE;
 707
 708         /* Fetch the APE firwmare type and version. */
 709         apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
 710         features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
 711         if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) {
 712                 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
 713                 fwtype = "NCSI";
 714         } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) {
 715                 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
 716                 fwtype = "DASH";
 717         } else
 718                 fwtype = "UNKN";
 719
 720         /* Print the APE firmware version. */
 721         device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n",
 722             fwtype,
 723             (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT,
 724             (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT,
 725             (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT,
 726             (apedata & BGE_APE_FW_VERSION_BLDMSK));
 727 }
 728
 729 static int
 730 bge_ape_lock(struct bge_softc *sc, int locknum)
 731 {
 732         uint32_t bit, gnt, req, status;
 733         int i, off;
 734
 735         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
 736                 return (0);
 737
 738         /* Lock request/grant registers have different bases. */
 739         if (sc->bge_asicrev == BGE_ASICREV_BCM5761) {
 740                 req = BGE_APE_LOCK_REQ;
 741                 gnt = BGE_APE_LOCK_GRANT;
 742         } else {
 743                 req = BGE_APE_PER_LOCK_REQ;
 744                 gnt = BGE_APE_PER_LOCK_GRANT;
 745         }
 746
 747         off = 4 * locknum;
 748
 749         switch (locknum) {
 750         case BGE_APE_LOCK_GPIO:
 751                 /* Lock required when using GPIO. */
 752                 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 753                         return (0);
 754                 if (sc->bge_func_addr == 0)
 755                         bit = BGE_APE_LOCK_REQ_DRIVER0;
 756                 else
 757                         bit = (1 << sc->bge_func_addr);
 758                 break;
 759         case BGE_APE_LOCK_GRC:
 760                 /* Lock required to reset the device. */
 761                 if (sc->bge_func_addr == 0)
 762                         bit = BGE_APE_LOCK_REQ_DRIVER0;
 763                 else
 764                         bit = (1 << sc->bge_func_addr);
 765                 break;
 766         case BGE_APE_LOCK_MEM:
 767                 /* Lock required when accessing certain APE memory. */
 768                 if (sc->bge_func_addr == 0)
 769                         bit = BGE_APE_LOCK_REQ_DRIVER0;
 770                 else
 771                         bit = (1 << sc->bge_func_addr);
 772                 break;
 773         case BGE_APE_LOCK_PHY0:
 774         case BGE_APE_LOCK_PHY1:
 775         case BGE_APE_LOCK_PHY2:
 776         case BGE_APE_LOCK_PHY3:
 777                 /* Lock required when accessing PHYs. */
 778                 bit = BGE_APE_LOCK_REQ_DRIVER0;
 779                 break;
 780         default:
 781                 return (EINVAL);
 782         }
 783
 784         /* Request a lock. */
 785         APE_WRITE_4(sc, req + off, bit);
 786
 787         /* Wait up to 1 second to acquire lock. */
 788         for (i = 0; i < 20000; i++) {
 789                 status = APE_READ_4(sc, gnt + off);
 790                 if (status == bit)
 791                         break;
 792                 DELAY(50);
 793         }
 794
 795         /* Handle any errors. */
 796         if (status != bit) {
 797                 device_printf(sc->bge_dev, "APE lock %d request failed! "
 798                     "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
 799                     locknum, req + off, bit & 0xFFFF, gnt + off,
 800                     status & 0xFFFF);
 801                 /* Revoke the lock request. */
 802                 APE_WRITE_4(sc, gnt + off, bit);
 803                 return (EBUSY);
 804         }
 805
 806         return (0);
 807 }
 808
 809 static void
 810 bge_ape_unlock(struct bge_softc *sc, int locknum)
 811 {
 812         uint32_t bit, gnt;
 813         int off;
 814
 815         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
 816                 return;
 817
 818         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 819                 gnt = BGE_APE_LOCK_GRANT;
 820         else
 821                 gnt = BGE_APE_PER_LOCK_GRANT;
 822
 823         off = 4 * locknum;
 824
 825         switch (locknum) {
 826         case BGE_APE_LOCK_GPIO:
 827                 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 828                         return;
 829                 if (sc->bge_func_addr == 0)
 830                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
 831                 else
 832                         bit = (1 << sc->bge_func_addr);
 833                 break;
 834         case BGE_APE_LOCK_GRC:
 835                 if (sc->bge_func_addr == 0)
 836                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
 837                 else
 838                         bit = (1 << sc->bge_func_addr);
 839                 break;
 840         case BGE_APE_LOCK_MEM:
 841                 if (sc->bge_func_addr == 0)
 842                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
 843                 else
 844                         bit = (1 << sc->bge_func_addr);
 845                 break;
 846         case BGE_APE_LOCK_PHY0:
 847         case BGE_APE_LOCK_PHY1:
 848         case BGE_APE_LOCK_PHY2:
 849         case BGE_APE_LOCK_PHY3:
 850                 bit = BGE_APE_LOCK_GRANT_DRIVER0;
 851                 break;
 852         default:
 853                 return;
 854         }
 855
 856         APE_WRITE_4(sc, gnt + off, bit);
 857 }
 858
 859 /*
 860  * Send an event to the APE firmware.
 861  */
 862 static void
 863 bge_ape_send_event(struct bge_softc *sc, uint32_t event)
 864 {
 865         uint32_t apedata;
 866         int i;
 867
 868         /* NCSI does not support APE events. */
 869         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
 870                 return;
 871
 872         /* Wait up to 1ms for APE to service previous event. */
 873         for (i = 10; i > 0; i--) {
 874                 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
 875                         break;
 876                 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
 877                 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) {
 878                         APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
 879                             BGE_APE_EVENT_STATUS_EVENT_PENDING);
 880                         bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
 881                         APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
 882                         break;
 883                 }
 884                 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
 885                 DELAY(100);
 886         }
 887         if (i == 0)
 888                 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n",
 889                     event);
 890 }
 891
 892 static void
 893 bge_ape_driver_state_change(struct bge_softc *sc, int kind)
 894 {
 895         uint32_t apedata, event;
 896
 897         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
 898                 return;
 899
 900         switch (kind) {
 901         case BGE_RESET_START:
 902                 /* If this is the first load, clear the load counter. */
 903                 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
 904                 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC)
 905                         APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
 906                 else {
 907                         apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
 908                         APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
 909                 }
 910                 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
 911                     BGE_APE_HOST_SEG_SIG_MAGIC);
 912                 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
 913                     BGE_APE_HOST_SEG_LEN_MAGIC);
 914
 915                 /* Add some version info if bge(4) supports it. */
 916                 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
 917                     BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0));
 918                 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
 919                     BGE_APE_HOST_BEHAV_NO_PHYLOCK);
 920                 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
 921                     BGE_APE_HOST_HEARTBEAT_INT_DISABLE);
 922                 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
 923                     BGE_APE_HOST_DRVR_STATE_START);
 924                 event = BGE_APE_EVENT_STATUS_STATE_START;
 925                 break;
 926         case BGE_RESET_SHUTDOWN:
 927                 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
 928                     BGE_APE_HOST_DRVR_STATE_UNLOAD);
 929                 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
 930                 break;
 931         case BGE_RESET_SUSPEND:
 932                 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
 933                 break;
 934         default:
 935                 return;
 936         }
 937
 938         bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
 939             BGE_APE_EVENT_STATUS_STATE_CHNGE);
 940 }
 941
 942 /*
 943  * Map a single buffer address.
 944  */
 945
 946 static void
 947 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 948 {
 949         struct bge_dmamap_arg *ctx;
 950
 951         if (error)
 952                 return;
 953
 954         KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
 955
 956         ctx = arg;
 957         ctx->bge_busaddr = segs->ds_addr;
 958 }
 959
 960 static uint8_t
 961 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 962 {
 963         uint32_t access, byte = 0;
 964         int i;
 965
 966         /* Lock. */
 967         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 968         for (i = 0; i < 8000; i++) {
 969                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 970                         break;
 971                 DELAY(20);
 972         }
 973         if (i == 8000)
 974                 return (1);
 975
 976         /* Enable access. */
 977         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 978         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 979
 980         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 981         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 982         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 983                 DELAY(10);
 984                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 985                         DELAY(10);
 986                         break;
 987                 }
 988         }
 989
 990         if (i == BGE_TIMEOUT * 10) {
 991                 if_printf(sc->bge_ifp, "nvram read timed out\n");
 992                 return (1);
 993         }
 994
 995         /* Get result. */
 996         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 997
 998         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 999
1000         /* Disable access. */
1001         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
1002
1003         /* Unlock. */
1004         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
1005         CSR_READ_4(sc, BGE_NVRAM_SWARB);
1006
1007         return (0);
1008 }
1009
1010 /*
1011  * Read a sequence of bytes from NVRAM.
1012  */
1013 static int
1014 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1015 {
1016         int err = 0, i;
1017         uint8_t byte = 0;
1018
1019         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1020                 return (1);
1021
1022         for (i = 0; i < cnt; i++) {
1023                 err = bge_nvram_getbyte(sc, off + i, &byte);
1024                 if (err)
1025                         break;
1026                 *(dest + i) = byte;
1027         }
1028
1029         return (err ? 1 : 0);
1030 }
1031
1032 /*
1033  * Read a byte of data stored in the EEPROM at address 'addr.' The
1034  * BCM570x supports both the traditional bitbang interface and an
1035  * auto access interface for reading the EEPROM. We use the auto
1036  * access method.
1037  */
1038 static uint8_t
1039 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1040 {
1041         int i;
1042         uint32_t byte = 0;
1043
1044         /*
1045          * Enable use of auto EEPROM access so we can avoid
1046          * having to use the bitbang method.
1047          */
1048         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
1049
1050         /* Reset the EEPROM, load the clock period. */
1051         CSR_WRITE_4(sc, BGE_EE_ADDR,
1052             BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
1053         DELAY(20);
1054
1055         /* Issue the read EEPROM command. */
1056         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
1057
1058         /* Wait for completion */
1059         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
1060                 DELAY(10);
1061                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1062                         break;
1063         }
1064
1065         if (i == BGE_TIMEOUT * 10) {
1066                 device_printf(sc->bge_dev, "EEPROM read timed out\n");
1067                 return (1);
1068         }
1069
1070         /* Get result. */
1071         byte = CSR_READ_4(sc, BGE_EE_DATA);
1072
1073         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
1074
1075         return (0);
1076 }
1077
1078 /*
1079  * Read a sequence of bytes from the EEPROM.
1080  */
1081 static int
1082 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1083 {
1084         int i, error = 0;
1085         uint8_t byte = 0;
1086
1087         for (i = 0; i < cnt; i++) {
1088                 error = bge_eeprom_getbyte(sc, off + i, &byte);
1089                 if (error)
1090                         break;
1091                 *(dest + i) = byte;
1092         }
1093
1094         return (error ? 1 : 0);
1095 }
1096
1097 static int
1098 bge_miibus_readreg(device_t dev, int phy, int reg)
1099 {
1100         struct bge_softc *sc;
1101         uint32_t val;
1102         int i;
1103
1104         sc = device_get_softc(dev);
1105
1106         if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1107                 return (0);
1108
1109         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1110         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1111                 CSR_WRITE_4(sc, BGE_MI_MODE,
1112                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1113                 DELAY(80);
1114         }
1115
1116         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
1117             BGE_MIPHY(phy) | BGE_MIREG(reg));
1118
1119         /* Poll for the PHY register access to complete. */
1120         for (i = 0; i < BGE_TIMEOUT; i++) {
1121                 DELAY(10);
1122                 val = CSR_READ_4(sc, BGE_MI_COMM);
1123                 if ((val & BGE_MICOMM_BUSY) == 0) {
1124                         DELAY(5);
1125                         val = CSR_READ_4(sc, BGE_MI_COMM);
1126                         break;
1127                 }
1128         }
1129
1130         if (i == BGE_TIMEOUT) {
1131                 device_printf(sc->bge_dev,
1132                     "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
1133                     phy, reg, val);
1134                 val = 0;
1135         }
1136
1137         /* Restore the autopoll bit if necessary. */
1138         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1139                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1140                 DELAY(80);
1141         }
1142
1143         bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1144
1145         if (val & BGE_MICOMM_READFAIL)
1146                 return (0);
1147
1148         return (val & 0xFFFF);
1149 }
1150
1151 static int
1152 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
1153 {
1154         struct bge_softc *sc;
1155         int i;
1156
1157         sc = device_get_softc(dev);
1158
1159         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1160             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
1161                 return (0);
1162
1163         if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1164                 return (0);
1165
1166         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1167         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1168                 CSR_WRITE_4(sc, BGE_MI_MODE,
1169                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1170                 DELAY(80);
1171         }
1172
1173         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
1174             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
1175
1176         for (i = 0; i < BGE_TIMEOUT; i++) {
1177                 DELAY(10);
1178                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
1179                         DELAY(5);
1180                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
1181                         break;
1182                 }
1183         }
1184
1185         /* Restore the autopoll bit if necessary. */
1186         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1187                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1188                 DELAY(80);
1189         }
1190
1191         bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1192
1193         if (i == BGE_TIMEOUT)
1194                 device_printf(sc->bge_dev,
1195                     "PHY write timed out (phy %d, reg %d, val 0x%04x)\n",
1196                     phy, reg, val);
1197
1198         return (0);
1199 }
1200
1201 static void
1202 bge_miibus_statchg(device_t dev)
1203 {
1204         struct bge_softc *sc;
1205         struct mii_data *mii;
1206         uint32_t mac_mode, rx_mode, tx_mode;
1207
1208         sc = device_get_softc(dev);
1209         if ((if_getdrvflags(sc->bge_ifp) & IFF_DRV_RUNNING) == 0)
1210                 return;
1211         mii = device_get_softc(sc->bge_miibus);
1212
1213         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1214             (IFM_ACTIVE | IFM_AVALID)) {
1215                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1216                 case IFM_10_T:
1217                 case IFM_100_TX:
1218                         sc->bge_link = 1;
1219                         break;
1220                 case IFM_1000_T:
1221                 case IFM_1000_SX:
1222                 case IFM_2500_SX:
1223                         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1224                                 sc->bge_link = 1;
1225                         else
1226                                 sc->bge_link = 0;
1227                         break;
1228                 default:
1229                         sc->bge_link = 0;
1230                         break;
1231                 }
1232         } else
1233                 sc->bge_link = 0;
1234         if (sc->bge_link == 0)
1235                 return;
1236
1237         /*
1238          * APE firmware touches these registers to keep the MAC
1239          * connected to the outside world.  Try to keep the
1240          * accesses atomic.
1241          */
1242
1243         /* Set the port mode (MII/GMII) to match the link speed. */
1244         mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
1245             ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
1246         tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
1247         rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
1248
1249         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1250             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
1251                 mac_mode |= BGE_PORTMODE_GMII;
1252         else
1253                 mac_mode |= BGE_PORTMODE_MII;
1254
1255         /* Set MAC flow control behavior to match link flow control settings. */
1256         tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE;
1257         rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE;
1258         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1259                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1260                         tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE;
1261                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1262                         rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE;
1263         } else
1264                 mac_mode |= BGE_MACMODE_HALF_DUPLEX;
1265
1266         CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
1267         DELAY(40);
1268         CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
1269         CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
1270 }
1271
1272 /*
1273  * Intialize a standard receive ring descriptor.
1274  */
1275 static int
1276 bge_newbuf_std(struct bge_softc *sc, int i)
1277 {
1278         struct mbuf *m;
1279         struct bge_rx_bd *r;
1280         bus_dma_segment_t segs[1];
1281         bus_dmamap_t map;
1282         int error, nsegs;
1283
1284         if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
1285             (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
1286             ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) {
1287                 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1288                 if (m == NULL)
1289                         return (ENOBUFS);
1290                 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1291         } else {
1292                 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1293                 if (m == NULL)
1294                         return (ENOBUFS);
1295                 m->m_len = m->m_pkthdr.len = MCLBYTES;
1296         }
1297         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1298                 m_adj(m, ETHER_ALIGN);
1299
1300         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
1301             sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
1302         if (error != 0) {
1303                 m_freem(m);
1304                 return (error);
1305         }
1306         if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1307                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1308                     sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
1309                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1310                     sc->bge_cdata.bge_rx_std_dmamap[i]);
1311         }
1312         map = sc->bge_cdata.bge_rx_std_dmamap[i];
1313         sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
1314         sc->bge_cdata.bge_rx_std_sparemap = map;
1315         sc->bge_cdata.bge_rx_std_chain[i] = m;
1316         sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
1317         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
1318         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1319         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1320         r->bge_flags = BGE_RXBDFLAG_END;
1321         r->bge_len = segs[0].ds_len;
1322         r->bge_idx = i;
1323
1324         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1325             sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
1326
1327         return (0);
1328 }
1329
1330 /*
1331  * Initialize a jumbo receive ring descriptor. This allocates
1332  * a jumbo buffer from the pool managed internally by the driver.
1333  */
1334 static int
1335 bge_newbuf_jumbo(struct bge_softc *sc, int i)
1336 {
1337         bus_dma_segment_t segs[BGE_NSEG_JUMBO];
1338         bus_dmamap_t map;
1339         struct bge_extrx_bd *r;
1340         struct mbuf *m;
1341         int error, nsegs;
1342
1343         MGETHDR(m, M_NOWAIT, MT_DATA);
1344         if (m == NULL)
1345                 return (ENOBUFS);
1346
1347         if (m_cljget(m, M_NOWAIT, MJUM9BYTES) == NULL) {
1348                 m_freem(m);
1349                 return (ENOBUFS);
1350         }
1351         m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1352         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1353                 m_adj(m, ETHER_ALIGN);
1354
1355         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1356             sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1357         if (error != 0) {
1358                 m_freem(m);
1359                 return (error);
1360         }
1361
1362         if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1363                 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1364                     sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1365                 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1366                     sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1367         }
1368         map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1369         sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1370             sc->bge_cdata.bge_rx_jumbo_sparemap;
1371         sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1372         sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1373         sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1374         sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1375         sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1376         sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1377
1378         /*
1379          * Fill in the extended RX buffer descriptor.
1380          */
1381         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1382         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1383         r->bge_idx = i;
1384         r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1385         switch (nsegs) {
1386         case 4:
1387                 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1388                 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1389                 r->bge_len3 = segs[3].ds_len;
1390                 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1391         case 3:
1392                 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1393                 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1394                 r->bge_len2 = segs[2].ds_len;
1395                 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1396         case 2:
1397                 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1398                 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1399                 r->bge_len1 = segs[1].ds_len;
1400                 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1401         case 1:
1402                 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1403                 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1404                 r->bge_len0 = segs[0].ds_len;
1405                 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1406                 break;
1407         default:
1408                 panic("%s: %d segments\n", __func__, nsegs);
1409         }
1410
1411         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1412             sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1413
1414         return (0);
1415 }
1416
1417 static int
1418 bge_init_rx_ring_std(struct bge_softc *sc)
1419 {
1420         int error, i;
1421
1422         bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1423         sc->bge_std = 0;
1424         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1425                 if ((error = bge_newbuf_std(sc, i)) != 0)
1426                         return (error);
1427                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1428         }
1429
1430         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1431             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1432
1433         sc->bge_std = 0;
1434         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1435
1436         return (0);
1437 }
1438
1439 static void
1440 bge_free_rx_ring_std(struct bge_softc *sc)
1441 {
1442         int i;
1443
1444         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1445                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1446                         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1447                             sc->bge_cdata.bge_rx_std_dmamap[i],
1448                             BUS_DMASYNC_POSTREAD);
1449                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1450                             sc->bge_cdata.bge_rx_std_dmamap[i]);
1451                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1452                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1453                 }
1454                 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1455                     sizeof(struct bge_rx_bd));
1456         }
1457 }
1458
1459 static int
1460 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1461 {
1462         struct bge_rcb *rcb;
1463         int error, i;
1464
1465         bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1466         sc->bge_jumbo = 0;
1467         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1468                 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1469                         return (error);
1470                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1471         }
1472
1473         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1474             sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1475
1476         sc->bge_jumbo = 0;
1477
1478         /* Enable the jumbo receive producer ring. */
1479         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1480         rcb->bge_maxlen_flags =
1481             BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD);
1482         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1483
1484         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1485
1486         return (0);
1487 }
1488
1489 static void
1490 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1491 {
1492         int i;
1493
1494         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1495                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1496                         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1497                             sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1498                             BUS_DMASYNC_POSTREAD);
1499                         bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1500                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1501                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1502                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1503                 }
1504                 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1505                     sizeof(struct bge_extrx_bd));
1506         }
1507 }
1508
1509 static void
1510 bge_free_tx_ring(struct bge_softc *sc)
1511 {
1512         int i;
1513
1514         if (sc->bge_ldata.bge_tx_ring == NULL)
1515                 return;
1516
1517         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1518                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1519                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1520                             sc->bge_cdata.bge_tx_dmamap[i],
1521                             BUS_DMASYNC_POSTWRITE);
1522                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1523                             sc->bge_cdata.bge_tx_dmamap[i]);
1524                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1525                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1526                 }
1527                 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1528                     sizeof(struct bge_tx_bd));
1529         }
1530 }
1531
1532 static int
1533 bge_init_tx_ring(struct bge_softc *sc)
1534 {
1535         sc->bge_txcnt = 0;
1536         sc->bge_tx_saved_considx = 0;
1537
1538         bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1539         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1540             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1541
1542         /* Initialize transmit producer index for host-memory send ring. */
1543         sc->bge_tx_prodidx = 0;
1544         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1545
1546         /* 5700 b2 errata */
1547         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1548                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1549
1550         /* NIC-memory send ring not used; initialize to zero. */
1551         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1552         /* 5700 b2 errata */
1553         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1554                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1555
1556         return (0);
1557 }
1558
1559 static void
1560 bge_setpromisc(struct bge_softc *sc)
1561 {
1562         if_t ifp;
1563
1564         BGE_LOCK_ASSERT(sc);
1565
1566         ifp = sc->bge_ifp;
1567
1568         /* Enable or disable promiscuous mode as needed. */
1569         if (if_getflags(ifp) & IFF_PROMISC)
1570                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1571         else
1572                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1573 }
1574
1575 static u_int
1576 bge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1577 {
1578         uint32_t *hashes = arg;
1579         int h;
1580
1581         h = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0x7F;
1582         hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1583
1584         return (1);
1585 }
1586
1587 static void
1588 bge_setmulti(struct bge_softc *sc)
1589 {
1590         if_t ifp;
1591         uint32_t hashes[4] = { 0, 0, 0, 0 };
1592         int i;
1593
1594         BGE_LOCK_ASSERT(sc);
1595
1596         ifp = sc->bge_ifp;
1597
1598         if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) {
1599                 for (i = 0; i < 4; i++)
1600                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1601                 return;
1602         }
1603
1604         /* First, zot all the existing filters. */
1605         for (i = 0; i < 4; i++)
1606                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1607
1608         if_foreach_llmaddr(ifp, bge_hash_maddr, hashes);
1609
1610         for (i = 0; i < 4; i++)
1611                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1612 }
1613
1614 static void
1615 bge_setvlan(struct bge_softc *sc)
1616 {
1617         if_t ifp;
1618
1619         BGE_LOCK_ASSERT(sc);
1620
1621         ifp = sc->bge_ifp;
1622
1623         /* Enable or disable VLAN tag stripping as needed. */
1624         if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING)
1625                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1626         else
1627                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1628 }
1629
1630 static void
1631 bge_sig_pre_reset(struct bge_softc *sc, int type)
1632 {
1633
1634         /*
1635          * Some chips don't like this so only do this if ASF is enabled
1636          */
1637         if (sc->bge_asf_mode)
1638                 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
1639
1640         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1641                 switch (type) {
1642                 case BGE_RESET_START:
1643                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1644                             BGE_FW_DRV_STATE_START);
1645                         break;
1646                 case BGE_RESET_SHUTDOWN:
1647                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1648                             BGE_FW_DRV_STATE_UNLOAD);
1649                         break;
1650                 case BGE_RESET_SUSPEND:
1651                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1652                             BGE_FW_DRV_STATE_SUSPEND);
1653                         break;
1654                 }
1655         }
1656
1657         if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
1658                 bge_ape_driver_state_change(sc, type);
1659 }
1660
1661 static void
1662 bge_sig_post_reset(struct bge_softc *sc, int type)
1663 {
1664
1665         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1666                 switch (type) {
1667                 case BGE_RESET_START:
1668                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1669                             BGE_FW_DRV_STATE_START_DONE);
1670                         /* START DONE */
1671                         break;
1672                 case BGE_RESET_SHUTDOWN:
1673                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1674                             BGE_FW_DRV_STATE_UNLOAD_DONE);
1675                         break;
1676                 }
1677         }
1678         if (type == BGE_RESET_SHUTDOWN)
1679                 bge_ape_driver_state_change(sc, type);
1680 }
1681
1682 static void
1683 bge_sig_legacy(struct bge_softc *sc, int type)
1684 {
1685
1686         if (sc->bge_asf_mode) {
1687                 switch (type) {
1688                 case BGE_RESET_START:
1689                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1690                             BGE_FW_DRV_STATE_START);
1691                         break;
1692                 case BGE_RESET_SHUTDOWN:
1693                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1694                             BGE_FW_DRV_STATE_UNLOAD);
1695                         break;
1696                 }
1697         }
1698 }
1699
1700 static void
1701 bge_stop_fw(struct bge_softc *sc)
1702 {
1703         int i;
1704
1705         if (sc->bge_asf_mode) {
1706                 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
1707                 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
1708                     CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
1709
1710                 for (i = 0; i < 100; i++ ) {
1711                         if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1712                             BGE_RX_CPU_DRV_EVENT))
1713                                 break;
1714                         DELAY(10);
1715                 }
1716         }
1717 }
1718
1719 static uint32_t
1720 bge_dma_swap_options(struct bge_softc *sc)
1721 {
1722         uint32_t dma_options;
1723
1724         dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
1725             BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
1726 #if BYTE_ORDER == BIG_ENDIAN
1727         dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
1728 #endif
1729         return (dma_options);
1730 }
1731
1732 /*
1733  * Do endian, PCI and DMA initialization.
1734  */
1735 static int
1736 bge_chipinit(struct bge_softc *sc)
1737 {
1738         uint32_t dma_rw_ctl, misc_ctl, mode_ctl;
1739         uint16_t val;
1740         int i;
1741
1742         /* Set endianness before we access any non-PCI registers. */
1743         misc_ctl = BGE_INIT;
1744         if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1745                 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1746         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1747
1748         /*
1749          * Clear the MAC statistics block in the NIC's
1750          * internal memory.
1751          */
1752         for (i = BGE_STATS_BLOCK;
1753             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1754                 BGE_MEMWIN_WRITE(sc, i, 0);
1755
1756         for (i = BGE_STATUS_BLOCK;
1757             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1758                 BGE_MEMWIN_WRITE(sc, i, 0);
1759
1760         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1761                 /*
1762                  *  Fix data corruption caused by non-qword write with WB.
1763                  *  Fix master abort in PCI mode.
1764                  *  Fix PCI latency timer.
1765                  */
1766                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1767                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1768                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1769         }
1770
1771         if (sc->bge_asicrev == BGE_ASICREV_BCM57765 ||
1772             sc->bge_asicrev == BGE_ASICREV_BCM57766) {
1773                 /*
1774                  * For the 57766 and non Ax versions of 57765, bootcode
1775                  * needs to setup the PCIE Fast Training Sequence (FTS)
1776                  * value to prevent transmit hangs.
1777                  */
1778                 if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) {
1779                         CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL,
1780                             CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) |
1781                             BGE_CPMU_PADRNG_CTL_RDIV2);
1782                 }
1783         }
1784
1785         /*
1786          * Set up the PCI DMA control register.
1787          */
1788         dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1789             BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1790         if (sc->bge_flags & BGE_FLAG_PCIE) {
1791                 if (sc->bge_mps >= 256)
1792                         dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1793                 else
1794                         dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1795         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1796                 if (BGE_IS_5714_FAMILY(sc)) {
1797                         /* 256 bytes for read and write. */
1798                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1799                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1800                         dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1801                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1802                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1803                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1804                         /*
1805                          * In the BCM5703, the DMA read watermark should
1806                          * be set to less than or equal to the maximum
1807                          * memory read byte count of the PCI-X command
1808                          * register.
1809                          */
1810                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1811                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1812                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1813                         /* 1536 bytes for read, 384 bytes for write. */
1814                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1815                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1816                 } else {
1817                         /* 384 bytes for read and write. */
1818                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1819                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1820                             0x0F;
1821                 }
1822                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1823                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1824                         uint32_t tmp;
1825
1826                         /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1827                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1828                         if (tmp == 6 || tmp == 7)
1829                                 dma_rw_ctl |=
1830                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1831
1832                         /* Set PCI-X DMA write workaround. */
1833                         dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1834                 }
1835         } else {
1836                 /* Conventional PCI bus: 256 bytes for read and write. */
1837                 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1838                     BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1839
1840                 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1841                     sc->bge_asicrev != BGE_ASICREV_BCM5750)
1842                         dma_rw_ctl |= 0x0F;
1843         }
1844         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1845             sc->bge_asicrev == BGE_ASICREV_BCM5701)
1846                 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1847                     BGE_PCIDMARWCTL_ASRT_ALL_BE;
1848         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1849             sc->bge_asicrev == BGE_ASICREV_BCM5704)
1850                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1851         if (BGE_IS_5717_PLUS(sc)) {
1852                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1853                 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
1854                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1855                 /*
1856                  * Enable HW workaround for controllers that misinterpret
1857                  * a status tag update and leave interrupts permanently
1858                  * disabled.
1859                  */
1860                 if (!BGE_IS_57765_PLUS(sc) &&
1861                     sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
1862                     sc->bge_asicrev != BGE_ASICREV_BCM5762)
1863                         dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1864         }
1865         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1866
1867         /*
1868          * Set up general mode register.
1869          */
1870         mode_ctl = bge_dma_swap_options(sc);
1871         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
1872             sc->bge_asicrev == BGE_ASICREV_BCM5762) {
1873                 /* Retain Host-2-BMC settings written by APE firmware. */
1874                 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
1875                     (BGE_MODECTL_BYTESWAP_B2HRX_DATA |
1876                     BGE_MODECTL_WORDSWAP_B2HRX_DATA |
1877                     BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE);
1878         }
1879         mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1880             BGE_MODECTL_TX_NO_PHDR_CSUM;
1881
1882         /*
1883          * BCM5701 B5 have a bug causing data corruption when using
1884          * 64-bit DMA reads, which can be terminated early and then
1885          * completed later as 32-bit accesses, in combination with
1886          * certain bridges.
1887          */
1888         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1889             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1890                 mode_ctl |= BGE_MODECTL_FORCE_PCI32;
1891
1892         /*
1893          * Tell the firmware the driver is running
1894          */
1895         if (sc->bge_asf_mode & ASF_STACKUP)
1896                 mode_ctl |= BGE_MODECTL_STACKUP;
1897
1898         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1899
1900         /*
1901          * Disable memory write invalidate.  Apparently it is not supported
1902          * properly by these devices.
1903          */
1904         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1905
1906         /* Set the timer prescaler (always 66 MHz). */
1907         CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1908
1909         /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1910         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1911                 DELAY(40);      /* XXX */
1912
1913                 /* Put PHY into ready state */
1914                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1915                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1916                 DELAY(40);
1917         }
1918
1919         return (0);
1920 }
1921
1922 static int
1923 bge_blockinit(struct bge_softc *sc)
1924 {
1925         struct bge_rcb *rcb;
1926         bus_size_t vrcb;
1927         bge_hostaddr taddr;
1928         uint32_t dmactl, rdmareg, val;
1929         int i, limit;
1930
1931         /*
1932          * Initialize the memory window pointer register so that
1933          * we can access the first 32K of internal NIC RAM. This will
1934          * allow us to set up the TX send ring RCBs and the RX return
1935          * ring RCBs, plus other things which live in NIC memory.
1936          */
1937         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1938
1939         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1940
1941         if (!(BGE_IS_5705_PLUS(sc))) {
1942                 /* Configure mbuf memory pool */
1943                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1944                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1945                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1946                 else
1947                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1948
1949                 /* Configure DMA resource pool */
1950                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1951                     BGE_DMA_DESCRIPTORS);
1952                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1953         }
1954
1955         /* Configure mbuf pool watermarks */
1956         if (BGE_IS_5717_PLUS(sc)) {
1957                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1958                 if (if_getmtu(sc->bge_ifp) > ETHERMTU) {
1959                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1960                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1961                 } else {
1962                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1963                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1964                 }
1965         } else if (!BGE_IS_5705_PLUS(sc)) {
1966                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1967                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1968                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1969         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1970                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1971                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1972                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1973         } else {
1974                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1975                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1976                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1977         }
1978
1979         /* Configure DMA resource watermarks */
1980         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1981         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1982
1983         /* Enable buffer manager */
1984         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1985         /*
1986          * Change the arbitration algorithm of TXMBUF read request to
1987          * round-robin instead of priority based for BCM5719.  When
1988          * TXFIFO is almost empty, RDMA will hold its request until
1989          * TXFIFO is not almost empty.
1990          */
1991         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
1992                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1993         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1994
1995         /* Poll for buffer manager start indication */
1996         for (i = 0; i < BGE_TIMEOUT; i++) {
1997                 DELAY(10);
1998                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1999                         break;
2000         }
2001
2002         if (i == BGE_TIMEOUT) {
2003                 device_printf(sc->bge_dev, "buffer manager failed to start\n");
2004                 return (ENXIO);
2005         }
2006
2007         /* Enable flow-through queues */
2008         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2009         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2010
2011         /* Wait until queue initialization is complete */
2012         for (i = 0; i < BGE_TIMEOUT; i++) {
2013                 DELAY(10);
2014                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
2015                         break;
2016         }
2017
2018         if (i == BGE_TIMEOUT) {
2019                 device_printf(sc->bge_dev, "flow-through queue init failed\n");
2020                 return (ENXIO);
2021         }
2022
2023         /*
2024          * Summary of rings supported by the controller:
2025          *
2026          * Standard Receive Producer Ring
2027          * - This ring is used to feed receive buffers for "standard"
2028          *   sized frames (typically 1536 bytes) to the controller.
2029          *
2030          * Jumbo Receive Producer Ring
2031          * - This ring is used to feed receive buffers for jumbo sized
2032          *   frames (i.e. anything bigger than the "standard" frames)
2033          *   to the controller.
2034          *
2035          * Mini Receive Producer Ring
2036          * - This ring is used to feed receive buffers for "mini"
2037          *   sized frames to the controller.
2038          * - This feature required external memory for the controller
2039          *   but was never used in a production system.  Should always
2040          *   be disabled.
2041          *
2042          * Receive Return Ring
2043          * - After the controller has placed an incoming frame into a
2044          *   receive buffer that buffer is moved into a receive return
2045          *   ring.  The driver is then responsible to passing the
2046          *   buffer up to the stack.  Many versions of the controller
2047          *   support multiple RR rings.
2048          *
2049          * Send Ring
2050          * - This ring is used for outgoing frames.  Many versions of
2051          *   the controller support multiple send rings.
2052          */
2053
2054         /* Initialize the standard receive producer ring control block. */
2055         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
2056         rcb->bge_hostaddr.bge_addr_lo =
2057             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
2058         rcb->bge_hostaddr.bge_addr_hi =
2059             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
2060         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2061             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
2062         if (BGE_IS_5717_PLUS(sc)) {
2063                 /*
2064                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
2065                  * Bits 15-2 : Maximum RX frame size
2066                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
2067                  * Bit 0     : Reserved
2068                  */
2069                 rcb->bge_maxlen_flags =
2070                     BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
2071         } else if (BGE_IS_5705_PLUS(sc)) {
2072                 /*
2073                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
2074                  * Bits 15-2 : Reserved (should be 0)
2075                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
2076                  * Bit 0     : Reserved
2077                  */
2078                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
2079         } else {
2080                 /*
2081                  * Ring size is always XXX entries
2082                  * Bits 31-16: Maximum RX frame size
2083                  * Bits 15-2 : Reserved (should be 0)
2084                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
2085                  * Bit 0     : Reserved
2086                  */
2087                 rcb->bge_maxlen_flags =
2088                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
2089         }
2090         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2091             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2092             sc->bge_asicrev == BGE_ASICREV_BCM5720)
2093                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
2094         else
2095                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
2096         /* Write the standard receive producer ring control block. */
2097         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
2098         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
2099         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
2100         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
2101
2102         /* Reset the standard receive producer ring producer index. */
2103         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
2104
2105         /*
2106          * Initialize the jumbo RX producer ring control
2107          * block.  We set the 'ring disabled' bit in the
2108          * flags field until we're actually ready to start
2109          * using this ring (i.e. once we set the MTU
2110          * high enough to require it).
2111          */
2112         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2113                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
2114                 /* Get the jumbo receive producer ring RCB parameters. */
2115                 rcb->bge_hostaddr.bge_addr_lo =
2116                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2117                 rcb->bge_hostaddr.bge_addr_hi =
2118                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2119                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2120                     sc->bge_cdata.bge_rx_jumbo_ring_map,
2121                     BUS_DMASYNC_PREREAD);
2122                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
2123                     BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
2124                 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2125                     sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2126                     sc->bge_asicrev == BGE_ASICREV_BCM5720)
2127                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
2128                 else
2129                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
2130                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
2131                     rcb->bge_hostaddr.bge_addr_hi);
2132                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
2133                     rcb->bge_hostaddr.bge_addr_lo);
2134                 /* Program the jumbo receive producer ring RCB parameters. */
2135                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
2136                     rcb->bge_maxlen_flags);
2137                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
2138                 /* Reset the jumbo receive producer ring producer index. */
2139                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
2140         }
2141
2142         /* Disable the mini receive producer ring RCB. */
2143         if (BGE_IS_5700_FAMILY(sc)) {
2144                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
2145                 rcb->bge_maxlen_flags =
2146                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
2147                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
2148                     rcb->bge_maxlen_flags);
2149                 /* Reset the mini receive producer ring producer index. */
2150                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
2151         }
2152
2153         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
2154         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2155                 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
2156                     sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
2157                     sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
2158                         CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
2159                             (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
2160         }
2161         /*
2162          * The BD ring replenish thresholds control how often the
2163          * hardware fetches new BD's from the producer rings in host
2164          * memory.  Setting the value too low on a busy system can
2165          * starve the hardware and recue the throughpout.
2166          *
2167          * Set the BD ring replentish thresholds. The recommended
2168          * values are 1/8th the number of descriptors allocated to
2169          * each ring.
2170          * XXX The 5754 requires a lower threshold, so it might be a
2171          * requirement of all 575x family chips.  The Linux driver sets
2172          * the lower threshold for all 5705 family chips as well, but there
2173          * are reports that it might not need to be so strict.
2174          *
2175          * XXX Linux does some extra fiddling here for the 5906 parts as
2176          * well.
2177          */
2178         if (BGE_IS_5705_PLUS(sc))
2179                 val = 8;
2180         else
2181                 val = BGE_STD_RX_RING_CNT / 8;
2182         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
2183         if (BGE_IS_JUMBO_CAPABLE(sc))
2184                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
2185                     BGE_JUMBO_RX_RING_CNT/8);
2186         if (BGE_IS_5717_PLUS(sc)) {
2187                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
2188                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
2189         }
2190
2191         /*
2192          * Disable all send rings by setting the 'ring disabled' bit
2193          * in the flags field of all the TX send ring control blocks,
2194          * located in NIC memory.
2195          */
2196         if (!BGE_IS_5705_PLUS(sc))
2197                 /* 5700 to 5704 had 16 send rings. */
2198                 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
2199         else if (BGE_IS_57765_PLUS(sc) ||
2200             sc->bge_asicrev == BGE_ASICREV_BCM5762)
2201                 limit = 2;
2202         else if (BGE_IS_5717_PLUS(sc))
2203                 limit = 4;
2204         else
2205                 limit = 1;
2206         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2207         for (i = 0; i < limit; i++) {
2208                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2209                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
2210                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2211                 vrcb += sizeof(struct bge_rcb);
2212         }
2213
2214         /* Configure send ring RCB 0 (we use only the first ring) */
2215         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2216         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
2217         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2218         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2219         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2220             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2221             sc->bge_asicrev == BGE_ASICREV_BCM5720)
2222                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
2223         else
2224                 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
2225                     BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
2226         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2227             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
2228
2229         /*
2230          * Disable all receive return rings by setting the
2231          * 'ring diabled' bit in the flags field of all the receive
2232          * return ring control blocks, located in NIC memory.
2233          */
2234         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2235             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2236             sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2237                 /* Should be 17, use 16 until we get an SRAM map. */
2238                 limit = 16;
2239         } else if (!BGE_IS_5705_PLUS(sc))
2240                 limit = BGE_RX_RINGS_MAX;
2241         else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2242             sc->bge_asicrev == BGE_ASICREV_BCM5762 ||
2243             BGE_IS_57765_PLUS(sc))
2244                 limit = 4;
2245         else
2246                 limit = 1;
2247         /* Disable all receive return rings. */
2248         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2249         for (i = 0; i < limit; i++) {
2250                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
2251                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
2252                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2253                     BGE_RCB_FLAG_RING_DISABLED);
2254                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2255                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
2256                     (i * (sizeof(uint64_t))), 0);
2257                 vrcb += sizeof(struct bge_rcb);
2258         }
2259
2260         /*
2261          * Set up receive return ring 0.  Note that the NIC address
2262          * for RX return rings is 0x0.  The return rings live entirely
2263          * within the host, so the nicaddr field in the RCB isn't used.
2264          */
2265         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2266         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
2267         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2268         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2269         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2270         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2271             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
2272
2273         /* Set random backoff seed for TX */
2274         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
2275             (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
2276             IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
2277             IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) &
2278             BGE_TX_BACKOFF_SEED_MASK);
2279
2280         /* Set inter-packet gap */
2281         val = 0x2620;
2282         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2283             sc->bge_asicrev == BGE_ASICREV_BCM5762)
2284                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
2285                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
2286         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
2287
2288         /*
2289          * Specify which ring to use for packets that don't match
2290          * any RX rules.
2291          */
2292         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
2293
2294         /*
2295          * Configure number of RX lists. One interrupt distribution
2296          * list, sixteen active lists, one bad frames class.
2297          */
2298         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
2299
2300         /* Inialize RX list placement stats mask. */
2301         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
2302         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
2303
2304         /* Disable host coalescing until we get it set up */
2305         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
2306
2307         /* Poll to make sure it's shut down. */
2308         for (i = 0; i < BGE_TIMEOUT; i++) {
2309                 DELAY(10);
2310                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
2311                         break;
2312         }
2313
2314         if (i == BGE_TIMEOUT) {
2315                 device_printf(sc->bge_dev,
2316                     "host coalescing engine failed to idle\n");
2317                 return (ENXIO);
2318         }
2319
2320         /* Set up host coalescing defaults */
2321         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
2322         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
2323         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
2324         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
2325         if (!(BGE_IS_5705_PLUS(sc))) {
2326                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
2327                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
2328         }
2329         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
2330         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
2331
2332         /* Set up address of statistics block */
2333         if (!(BGE_IS_5705_PLUS(sc))) {
2334                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
2335                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
2336                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
2337                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
2338                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
2339                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
2340                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
2341         }
2342
2343         /* Set up address of status block */
2344         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
2345             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
2346         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
2347             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
2348
2349         /* Set up status block size. */
2350         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2351             sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
2352                 val = BGE_STATBLKSZ_FULL;
2353                 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2354         } else {
2355                 val = BGE_STATBLKSZ_32BYTE;
2356                 bzero(sc->bge_ldata.bge_status_block, 32);
2357         }
2358         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2359             sc->bge_cdata.bge_status_map,
2360             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2361
2362         /* Turn on host coalescing state machine */
2363         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2364
2365         /* Turn on RX BD completion state machine and enable attentions */
2366         CSR_WRITE_4(sc, BGE_RBDC_MODE,
2367             BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
2368
2369         /* Turn on RX list placement state machine */
2370         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2371
2372         /* Turn on RX list selector state machine. */
2373         if (!(BGE_IS_5705_PLUS(sc)))
2374                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2375
2376         /* Turn on DMA, clear stats. */
2377         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
2378             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
2379             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
2380             BGE_MACMODE_FRMHDR_DMA_ENB;
2381
2382         if (sc->bge_flags & BGE_FLAG_TBI)
2383                 val |= BGE_PORTMODE_TBI;
2384         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
2385                 val |= BGE_PORTMODE_GMII;
2386         else
2387                 val |= BGE_PORTMODE_MII;
2388
2389         /* Allow APE to send/receive frames. */
2390         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
2391                 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
2392
2393         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
2394         DELAY(40);
2395
2396         /* Set misc. local control, enable interrupts on attentions */
2397         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2398
2399 #ifdef notdef
2400         /* Assert GPIO pins for PHY reset */
2401         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
2402             BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
2403         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
2404             BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
2405 #endif
2406
2407         /* Turn on DMA completion state machine */
2408         if (!(BGE_IS_5705_PLUS(sc)))
2409                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2410
2411         val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
2412
2413         /* Enable host coalescing bug fix. */
2414         if (BGE_IS_5755_PLUS(sc))
2415                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
2416
2417         /* Request larger DMA burst size to get better performance. */
2418         if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
2419                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
2420
2421         /* Turn on write DMA state machine */
2422         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
2423         DELAY(40);
2424
2425         /* Turn on read DMA state machine */
2426         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
2427
2428         if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
2429                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
2430
2431         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2432             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2433             sc->bge_asicrev == BGE_ASICREV_BCM57780)
2434                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
2435                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
2436                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
2437         if (sc->bge_flags & BGE_FLAG_PCIE)
2438                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2439         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2440                 val |= BGE_RDMAMODE_TSO4_ENABLE;
2441                 if (sc->bge_flags & BGE_FLAG_TSO3 ||
2442                     sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2443                     sc->bge_asicrev == BGE_ASICREV_BCM57780)
2444                         val |= BGE_RDMAMODE_TSO6_ENABLE;
2445         }
2446
2447         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2448             sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2449                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
2450                         BGE_RDMAMODE_H2BNC_VLAN_DET;
2451                 /*
2452                  * Allow multiple outstanding read requests from
2453                  * non-LSO read DMA engine.
2454                  */
2455                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
2456         }
2457
2458         if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2459             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2460             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2461             sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2462             BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) {
2463                 if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
2464                         rdmareg = BGE_RDMA_RSRVCTRL_REG2;
2465                 else
2466                         rdmareg = BGE_RDMA_RSRVCTRL;
2467                 dmactl = CSR_READ_4(sc, rdmareg);
2468                 /*
2469                  * Adjust tx margin to prevent TX data corruption and
2470                  * fix internal FIFO overflow.
2471                  */
2472                 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 ||
2473                     sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2474                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2475                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2476                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2477                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2478                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2479                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2480                 }
2481                 /*
2482                  * Enable fix for read DMA FIFO overruns.
2483                  * The fix is to limit the number of RX BDs
2484                  * the hardware would fetch at a fime.
2485                  */
2486                 CSR_WRITE_4(sc, rdmareg, dmactl |
2487                     BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2488         }
2489
2490         if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2491                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2492                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2493                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2494                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2495         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2496                 /*
2497                  * Allow 4KB burst length reads for non-LSO frames.
2498                  * Enable 512B burst length reads for buffer descriptors.
2499                  */
2500                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2501                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2502                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
2503                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2504         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2505                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2,
2506                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |
2507                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2508                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2509         }
2510
2511         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2512         DELAY(40);
2513
2514         if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
2515                 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) {
2516                         val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);
2517                         if ((val & 0xFFFF) > BGE_FRAMELEN)
2518                                 break;
2519                         if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN)
2520                                 break;
2521                 }
2522                 if (i != BGE_NUM_RDMA_CHANNELS / 2) {
2523                         val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
2524                         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2525                                 val |= BGE_RDMA_TX_LENGTH_WA_5719;
2526                         else
2527                                 val |= BGE_RDMA_TX_LENGTH_WA_5720;
2528                         CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
2529                 }
2530         }
2531
2532         /* Turn on RX data completion state machine */
2533         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2534
2535         /* Turn on RX BD initiator state machine */
2536         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2537
2538         /* Turn on RX data and RX BD initiator state machine */
2539         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2540
2541         /* Turn on Mbuf cluster free state machine */
2542         if (!(BGE_IS_5705_PLUS(sc)))
2543                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2544
2545         /* Turn on send BD completion state machine */
2546         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2547
2548         /* Turn on send data completion state machine */
2549         val = BGE_SDCMODE_ENABLE;
2550         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2551                 val |= BGE_SDCMODE_CDELAY;
2552         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2553
2554         /* Turn on send data initiator state machine */
2555         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2556                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2557                     BGE_SDIMODE_HW_LSO_PRE_DMA);
2558         else
2559                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2560
2561         /* Turn on send BD initiator state machine */
2562         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2563
2564         /* Turn on send BD selector state machine */
2565         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2566
2567         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
2568         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
2569             BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
2570
2571         /* ack/clear link change events */
2572         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2573             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2574             BGE_MACSTAT_LINK_CHANGED);
2575         CSR_WRITE_4(sc, BGE_MI_STS, 0);
2576
2577         /*
2578          * Enable attention when the link has changed state for
2579          * devices that use auto polling.
2580          */
2581         if (sc->bge_flags & BGE_FLAG_TBI) {
2582                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
2583         } else {
2584                 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2585                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
2586                         DELAY(80);
2587                 }
2588                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2589                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
2590                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2591                             BGE_EVTENB_MI_INTERRUPT);
2592         }
2593
2594         /*
2595          * Clear any pending link state attention.
2596          * Otherwise some link state change events may be lost until attention
2597          * is cleared by bge_intr() -> bge_link_upd() sequence.
2598          * It's not necessary on newer BCM chips - perhaps enabling link
2599          * state change attentions implies clearing pending attention.
2600          */
2601         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2602             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2603             BGE_MACSTAT_LINK_CHANGED);
2604
2605         /* Enable link state change attentions. */
2606         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2607
2608         return (0);
2609 }
2610
2611 static const struct bge_revision *
2612 bge_lookup_rev(uint32_t chipid)
2613 {
2614         const struct bge_revision *br;
2615
2616         for (br = bge_revisions; br->br_name != NULL; br++) {
2617                 if (br->br_chipid == chipid)
2618                         return (br);
2619         }
2620
2621         for (br = bge_majorrevs; br->br_name != NULL; br++) {
2622                 if (br->br_chipid == BGE_ASICREV(chipid))
2623                         return (br);
2624         }
2625
2626         return (NULL);
2627 }
2628
2629 static const struct bge_vendor *
2630 bge_lookup_vendor(uint16_t vid)
2631 {
2632         const struct bge_vendor *v;
2633
2634         for (v = bge_vendors; v->v_name != NULL; v++)
2635                 if (v->v_id == vid)
2636                         return (v);
2637
2638         return (NULL);
2639 }
2640
2641 static uint32_t
2642 bge_chipid(device_t dev)
2643 {
2644         uint32_t id;
2645
2646         id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2647             BGE_PCIMISCCTL_ASICREV_SHIFT;
2648         if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
2649                 /*
2650                  * Find the ASCI revision.  Different chips use different
2651                  * registers.
2652                  */
2653                 switch (pci_get_device(dev)) {
2654                 case BCOM_DEVICEID_BCM5717C:
2655                         /* 5717 C0 seems to belong to 5720 line. */
2656                         id = BGE_CHIPID_BCM5720_A0;
2657                         break;
2658                 case BCOM_DEVICEID_BCM5717:
2659                 case BCOM_DEVICEID_BCM5718:
2660                 case BCOM_DEVICEID_BCM5719:
2661                 case BCOM_DEVICEID_BCM5720:
2662                 case BCOM_DEVICEID_BCM5725:
2663                 case BCOM_DEVICEID_BCM5727:
2664                 case BCOM_DEVICEID_BCM5762:
2665                 case BCOM_DEVICEID_BCM57764:
2666                 case BCOM_DEVICEID_BCM57767:
2667                 case BCOM_DEVICEID_BCM57787:
2668                         id = pci_read_config(dev,
2669                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
2670                         break;
2671                 case BCOM_DEVICEID_BCM57761:
2672                 case BCOM_DEVICEID_BCM57762:
2673                 case BCOM_DEVICEID_BCM57765:
2674                 case BCOM_DEVICEID_BCM57766:
2675                 case BCOM_DEVICEID_BCM57781:
2676                 case BCOM_DEVICEID_BCM57782:
2677                 case BCOM_DEVICEID_BCM57785:
2678                 case BCOM_DEVICEID_BCM57786:
2679                 case BCOM_DEVICEID_BCM57791:
2680                 case BCOM_DEVICEID_BCM57795:
2681                         id = pci_read_config(dev,
2682                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
2683                         break;
2684                 default:
2685                         id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
2686                 }
2687         }
2688         return (id);
2689 }
2690
2691 /*
2692  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
2693  * against our list and return its name if we find a match.
2694  *
2695  * Note that since the Broadcom controller contains VPD support, we
2696  * try to get the device name string from the controller itself instead
2697  * of the compiled-in string. It guarantees we'll always announce the
2698  * right product name. We fall back to the compiled-in string when
2699  * VPD is unavailable or corrupt.
2700  */
2701 static int
2702 bge_probe(device_t dev)
2703 {
2704         char buf[96];
2705         char model[64];
2706         const struct bge_revision *br;
2707         const char *pname;
2708         struct bge_softc *sc;
2709         const struct bge_type *t = bge_devs;
2710         const struct bge_vendor *v;
2711         uint32_t id;
2712         uint16_t did, vid;
2713
2714         sc = device_get_softc(dev);
2715         sc->bge_dev = dev;
2716         vid = pci_get_vendor(dev);
2717         did = pci_get_device(dev);
2718         while(t->bge_vid != 0) {
2719                 if ((vid == t->bge_vid) && (did == t->bge_did)) {
2720                         id = bge_chipid(dev);
2721                         br = bge_lookup_rev(id);
2722                         if (bge_has_eaddr(sc) &&
2723                             pci_get_vpd_ident(dev, &pname) == 0)
2724                                 snprintf(model, sizeof(model), "%s", pname);
2725                         else {
2726                                 v = bge_lookup_vendor(vid);
2727                                 snprintf(model, sizeof(model), "%s %s",
2728                                     v != NULL ? v->v_name : "Unknown",
2729                                     br != NULL ? br->br_name :
2730                                     "NetXtreme/NetLink Ethernet Controller");
2731                         }
2732                         snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x",
2733                             model, br != NULL ? "" : "unknown ", id);
2734                         device_set_desc_copy(dev, buf);
2735                         return (BUS_PROBE_DEFAULT);
2736                 }
2737                 t++;
2738         }
2739
2740         return (ENXIO);
2741 }
2742
2743 static void
2744 bge_dma_free(struct bge_softc *sc)
2745 {
2746         int i;
2747
2748         /* Destroy DMA maps for RX buffers. */
2749         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2750                 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2751                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2752                             sc->bge_cdata.bge_rx_std_dmamap[i]);
2753         }
2754         if (sc->bge_cdata.bge_rx_std_sparemap)
2755                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2756                     sc->bge_cdata.bge_rx_std_sparemap);
2757
2758         /* Destroy DMA maps for jumbo RX buffers. */
2759         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2760                 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2761                         bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2762                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2763         }
2764         if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2765                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2766                     sc->bge_cdata.bge_rx_jumbo_sparemap);
2767
2768         /* Destroy DMA maps for TX buffers. */
2769         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2770                 if (sc->bge_cdata.bge_tx_dmamap[i])
2771                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2772                             sc->bge_cdata.bge_tx_dmamap[i]);
2773         }
2774
2775         if (sc->bge_cdata.bge_rx_mtag)
2776                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2777         if (sc->bge_cdata.bge_mtag_jumbo)
2778                 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
2779         if (sc->bge_cdata.bge_tx_mtag)
2780                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2781
2782         /* Destroy standard RX ring. */
2783         if (sc->bge_ldata.bge_rx_std_ring_paddr)
2784                 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2785                     sc->bge_cdata.bge_rx_std_ring_map);
2786         if (sc->bge_ldata.bge_rx_std_ring)
2787                 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2788                     sc->bge_ldata.bge_rx_std_ring,
2789                     sc->bge_cdata.bge_rx_std_ring_map);
2790
2791         if (sc->bge_cdata.bge_rx_std_ring_tag)
2792                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2793
2794         /* Destroy jumbo RX ring. */
2795         if (sc->bge_ldata.bge_rx_jumbo_ring_paddr)
2796                 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2797                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2798
2799         if (sc->bge_ldata.bge_rx_jumbo_ring)
2800                 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2801                     sc->bge_ldata.bge_rx_jumbo_ring,
2802                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2803
2804         if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2805                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2806
2807         /* Destroy RX return ring. */
2808         if (sc->bge_ldata.bge_rx_return_ring_paddr)
2809                 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2810                     sc->bge_cdata.bge_rx_return_ring_map);
2811
2812         if (sc->bge_ldata.bge_rx_return_ring)
2813                 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2814                     sc->bge_ldata.bge_rx_return_ring,
2815                     sc->bge_cdata.bge_rx_return_ring_map);
2816
2817         if (sc->bge_cdata.bge_rx_return_ring_tag)
2818                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2819
2820         /* Destroy TX ring. */
2821         if (sc->bge_ldata.bge_tx_ring_paddr)
2822                 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2823                     sc->bge_cdata.bge_tx_ring_map);
2824
2825         if (sc->bge_ldata.bge_tx_ring)
2826                 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2827                     sc->bge_ldata.bge_tx_ring,
2828                     sc->bge_cdata.bge_tx_ring_map);
2829
2830         if (sc->bge_cdata.bge_tx_ring_tag)
2831                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2832
2833         /* Destroy status block. */
2834         if (sc->bge_ldata.bge_status_block_paddr)
2835                 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2836                     sc->bge_cdata.bge_status_map);
2837
2838         if (sc->bge_ldata.bge_status_block)
2839                 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2840                     sc->bge_ldata.bge_status_block,
2841                     sc->bge_cdata.bge_status_map);
2842
2843         if (sc->bge_cdata.bge_status_tag)
2844                 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2845
2846         /* Destroy statistics block. */
2847         if (sc->bge_ldata.bge_stats_paddr)
2848                 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2849                     sc->bge_cdata.bge_stats_map);
2850
2851         if (sc->bge_ldata.bge_stats)
2852                 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2853                     sc->bge_ldata.bge_stats,
2854                     sc->bge_cdata.bge_stats_map);
2855
2856         if (sc->bge_cdata.bge_stats_tag)
2857                 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2858
2859         if (sc->bge_cdata.bge_buffer_tag)
2860                 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
2861
2862         /* Destroy the parent tag. */
2863         if (sc->bge_cdata.bge_parent_tag)
2864                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2865 }
2866
2867 static int
2868 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
2869     bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
2870     bus_addr_t *paddr, const char *msg)
2871 {
2872         struct bge_dmamap_arg ctx;
2873         bus_addr_t lowaddr;
2874         bus_size_t ring_end;
2875         int error;
2876
2877         lowaddr = BUS_SPACE_MAXADDR;
2878 again:
2879         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2880             alignment, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2881             NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
2882         if (error != 0) {
2883                 device_printf(sc->bge_dev,
2884                     "could not create %s dma tag\n", msg);
2885                 return (ENOMEM);
2886         }
2887         /* Allocate DMA'able memory for ring. */
2888         error = bus_dmamem_alloc(*tag, (void **)ring,
2889             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
2890         if (error != 0) {
2891                 device_printf(sc->bge_dev,
2892                     "could not allocate DMA'able memory for %s\n", msg);
2893                 return (ENOMEM);
2894         }
2895         /* Load the address of the ring. */
2896         ctx.bge_busaddr = 0;
2897         error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr,
2898             &ctx, BUS_DMA_NOWAIT);
2899         if (error != 0) {
2900                 device_printf(sc->bge_dev,
2901                     "could not load DMA'able memory for %s\n", msg);
2902                 return (ENOMEM);
2903         }
2904         *paddr = ctx.bge_busaddr;
2905         ring_end = *paddr + maxsize;
2906         if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0 &&
2907             BGE_ADDR_HI(*paddr) != BGE_ADDR_HI(ring_end)) {
2908                 /*
2909                  * 4GB boundary crossed.  Limit maximum allowable DMA
2910                  * address space to 32bit and try again.
2911                  */
2912                 bus_dmamap_unload(*tag, *map);
2913                 bus_dmamem_free(*tag, *ring, *map);
2914                 bus_dma_tag_destroy(*tag);
2915                 if (bootverbose)
2916                         device_printf(sc->bge_dev, "4GB boundary crossed, "
2917                             "limit DMA address space to 32bit for %s\n", msg);
2918                 *ring = NULL;
2919                 *tag = NULL;
2920                 *map = NULL;
2921                 lowaddr = BUS_SPACE_MAXADDR_32BIT;
2922                 goto again;
2923         }
2924         return (0);
2925 }
2926
2927 static int
2928 bge_dma_alloc(struct bge_softc *sc)
2929 {
2930         bus_addr_t lowaddr;
2931         bus_size_t boundary, sbsz, rxmaxsegsz, txsegsz, txmaxsegsz;
2932         int i, error;
2933
2934         lowaddr = BUS_SPACE_MAXADDR;
2935         if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2936                 lowaddr = BGE_DMA_MAXADDR;
2937         /*
2938          * Allocate the parent bus DMA tag appropriate for PCI.
2939          */
2940         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2941             1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2942             NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2943             0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2944         if (error != 0) {
2945                 device_printf(sc->bge_dev,
2946                     "could not allocate parent dma tag\n");
2947                 return (ENOMEM);
2948         }
2949
2950         /* Create tag for standard RX ring. */
2951         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
2952             &sc->bge_cdata.bge_rx_std_ring_tag,
2953             (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
2954             &sc->bge_cdata.bge_rx_std_ring_map,
2955             &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
2956         if (error)
2957                 return (error);
2958
2959         /* Create tag for RX return ring. */
2960         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
2961             &sc->bge_cdata.bge_rx_return_ring_tag,
2962             (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
2963             &sc->bge_cdata.bge_rx_return_ring_map,
2964             &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
2965         if (error)
2966                 return (error);
2967
2968         /* Create tag for TX ring. */
2969         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
2970             &sc->bge_cdata.bge_tx_ring_tag,
2971             (uint8_t **)&sc->bge_ldata.bge_tx_ring,
2972             &sc->bge_cdata.bge_tx_ring_map,
2973             &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
2974         if (error)
2975                 return (error);
2976
2977         /*
2978          * Create tag for status block.
2979          * Because we only use single Tx/Rx/Rx return ring, use
2980          * minimum status block size except BCM5700 AX/BX which
2981          * seems to want to see full status block size regardless
2982          * of configured number of ring.
2983          */
2984         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2985             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
2986                 sbsz = BGE_STATUS_BLK_SZ;
2987         else
2988                 sbsz = 32;
2989         error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
2990             &sc->bge_cdata.bge_status_tag,
2991             (uint8_t **)&sc->bge_ldata.bge_status_block,
2992             &sc->bge_cdata.bge_status_map,
2993             &sc->bge_ldata.bge_status_block_paddr, "status block");
2994         if (error)
2995                 return (error);
2996
2997         /* Create tag for statistics block. */
2998         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
2999             &sc->bge_cdata.bge_stats_tag,
3000             (uint8_t **)&sc->bge_ldata.bge_stats,
3001             &sc->bge_cdata.bge_stats_map,
3002             &sc->bge_ldata.bge_stats_paddr, "statistics block");
3003         if (error)
3004                 return (error);
3005
3006         /* Create tag for jumbo RX ring. */
3007         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3008                 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
3009                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
3010                     (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
3011                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
3012                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
3013                 if (error)
3014                         return (error);
3015         }
3016
3017         /* Create parent tag for buffers. */
3018         boundary = 0;
3019         if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
3020                 boundary = BGE_DMA_BNDRY;
3021                 /*
3022                  * XXX
3023                  * watchdog timeout issue was observed on BCM5704 which
3024                  * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge).
3025                  * Both limiting DMA address space to 32bits and flushing
3026                  * mailbox write seem to address the issue.
3027                  */
3028                 if (sc->bge_pcixcap != 0)
3029                         lowaddr = BUS_SPACE_MAXADDR_32BIT;
3030         }
3031         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
3032             1, boundary, lowaddr, BUS_SPACE_MAXADDR, NULL,
3033             NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3034             0, NULL, NULL, &sc->bge_cdata.bge_buffer_tag);
3035         if (error != 0) {
3036                 device_printf(sc->bge_dev,
3037                     "could not allocate buffer dma tag\n");
3038                 return (ENOMEM);
3039         }
3040         /* Create tag for Tx mbufs. */
3041         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
3042                 txsegsz = BGE_TSOSEG_SZ;
3043                 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
3044         } else {
3045                 txsegsz = MCLBYTES;
3046                 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
3047         }
3048         error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
3049             0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
3050             txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
3051             &sc->bge_cdata.bge_tx_mtag);
3052
3053         if (error) {
3054                 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
3055                 return (ENOMEM);
3056         }
3057
3058         /* Create tag for Rx mbufs. */
3059         if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
3060                 rxmaxsegsz = MJUM9BYTES;
3061         else
3062                 rxmaxsegsz = MCLBYTES;
3063         error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
3064             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1,
3065             rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
3066
3067         if (error) {
3068                 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
3069                 return (ENOMEM);
3070         }
3071
3072         /* Create DMA maps for RX buffers. */
3073         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3074             &sc->bge_cdata.bge_rx_std_sparemap);
3075         if (error) {
3076                 device_printf(sc->bge_dev,
3077                     "can't create spare DMA map for RX\n");
3078                 return (ENOMEM);
3079         }
3080         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3081                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3082                             &sc->bge_cdata.bge_rx_std_dmamap[i]);
3083                 if (error) {
3084                         device_printf(sc->bge_dev,
3085                             "can't create DMA map for RX\n");
3086                         return (ENOMEM);
3087                 }
3088         }
3089
3090         /* Create DMA maps for TX buffers. */
3091         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3092                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
3093                             &sc->bge_cdata.bge_tx_dmamap[i]);
3094                 if (error) {
3095                         device_printf(sc->bge_dev,
3096                             "can't create DMA map for TX\n");
3097                         return (ENOMEM);
3098                 }
3099         }
3100
3101         /* Create tags for jumbo RX buffers. */
3102         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3103                 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
3104                     1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
3105                     NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
3106                     0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
3107                 if (error) {
3108                         device_printf(sc->bge_dev,
3109                             "could not allocate jumbo dma tag\n");
3110                         return (ENOMEM);
3111                 }
3112                 /* Create DMA maps for jumbo RX buffers. */
3113                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3114                     0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
3115                 if (error) {
3116                         device_printf(sc->bge_dev,
3117                             "can't create spare DMA map for jumbo RX\n");
3118                         return (ENOMEM);
3119                 }
3120                 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
3121                         error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3122                                     0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
3123                         if (error) {
3124                                 device_printf(sc->bge_dev,
3125                                     "can't create DMA map for jumbo RX\n");
3126                                 return (ENOMEM);
3127                         }
3128                 }
3129         }
3130
3131         return (0);
3132 }
3133
3134 /*
3135  * Return true if this device has more than one port.
3136  */
3137 static int
3138 bge_has_multiple_ports(struct bge_softc *sc)
3139 {
3140         device_t dev = sc->bge_dev;
3141         u_int b, d, f, fscan, s;
3142
3143         d = pci_get_domain(dev);
3144         b = pci_get_bus(dev);
3145         s = pci_get_slot(dev);
3146         f = pci_get_function(dev);
3147         for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
3148                 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
3149                         return (1);
3150         return (0);
3151 }
3152
3153 /*
3154  * Return true if MSI can be used with this device.
3155  */
3156 static int
3157 bge_can_use_msi(struct bge_softc *sc)
3158 {
3159         int can_use_msi = 0;
3160
3161         if (sc->bge_msi == 0)
3162                 return (0);
3163
3164         /* Disable MSI for polling(4). */
3165 #ifdef DEVICE_POLLING
3166         return (0);
3167 #endif
3168         switch (sc->bge_asicrev) {
3169         case BGE_ASICREV_BCM5714_A0:
3170         case BGE_ASICREV_BCM5714:
3171                 /*
3172                  * Apparently, MSI doesn't work when these chips are
3173                  * configured in single-port mode.
3174                  */
3175                 if (bge_has_multiple_ports(sc))
3176                         can_use_msi = 1;
3177                 break;
3178         case BGE_ASICREV_BCM5750:
3179                 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
3180                     sc->bge_chiprev != BGE_CHIPREV_5750_BX)
3181                         can_use_msi = 1;
3182                 break;
3183         case BGE_ASICREV_BCM5784:
3184                 /*
3185                  * Prevent infinite "watchdog timeout" errors
3186                  * in some MacBook Pro and make it work out-of-the-box.
3187                  */
3188                 if (sc->bge_chiprev == BGE_CHIPREV_5784_AX)
3189                         break;
3190                 /* FALLTHROUGH */
3191         default:
3192                 if (BGE_IS_575X_PLUS(sc))
3193                         can_use_msi = 1;
3194         }
3195         return (can_use_msi);
3196 }
3197
3198 static int
3199 bge_mbox_reorder(struct bge_softc *sc)
3200 {
3201         /* Lists of PCI bridges that are known to reorder mailbox writes. */
3202         static const struct mbox_reorder {
3203                 const uint16_t vendor;
3204                 const uint16_t device;
3205                 const char *desc;
3206         } mbox_reorder_lists[] = {
3207                 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" },
3208         };
3209         devclass_t pci, pcib;
3210         device_t bus, dev;
3211         int i;
3212
3213         pci = devclass_find("pci");
3214         pcib = devclass_find("pcib");
3215         dev = sc->bge_dev;
3216         bus = device_get_parent(dev);
3217         for (;;) {
3218                 dev = device_get_parent(bus);
3219                 bus = device_get_parent(dev);
3220                 if (device_get_devclass(dev) != pcib)
3221                         break;
3222                 if (device_get_devclass(bus) != pci)
3223                         break;
3224                 for (i = 0; i < nitems(mbox_reorder_lists); i++) {
3225                         if (pci_get_vendor(dev) ==
3226                             mbox_reorder_lists[i].vendor &&
3227                             pci_get_device(dev) ==
3228                             mbox_reorder_lists[i].device) {
3229                                 device_printf(sc->bge_dev,
3230                                     "enabling MBOX workaround for %s\n",
3231                                     mbox_reorder_lists[i].desc);
3232                                 return (1);
3233                         }
3234                 }
3235         }
3236         return (0);
3237 }
3238
3239 static void
3240 bge_devinfo(struct bge_softc *sc)
3241 {
3242         uint32_t cfg, clk;
3243
3244         device_printf(sc->bge_dev,
3245             "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ",
3246             sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev);
3247         if (sc->bge_flags & BGE_FLAG_PCIE)
3248                 printf("PCI-E\n");
3249         else if (sc->bge_flags & BGE_FLAG_PCIX) {
3250                 printf("PCI-X ");
3251                 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3252                 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE)
3253                         clk = 133;
3254                 else {
3255                         clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
3256                         switch (clk) {
3257                         case 0:
3258                                 clk = 33;
3259                                 break;
3260                         case 2:
3261                                 clk = 50;
3262                                 break;
3263                         case 4:
3264                                 clk = 66;
3265                                 break;
3266                         case 6:
3267                                 clk = 100;
3268                                 break;
3269                         case 7:
3270                                 clk = 133;
3271                                 break;
3272                         }
3273                 }
3274                 printf("%u MHz\n", clk);
3275         } else {
3276                 if (sc->bge_pcixcap != 0)
3277                         printf("PCI on PCI-X ");
3278                 else
3279                         printf("PCI ");
3280                 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3281                 if (cfg & BGE_PCISTATE_PCI_BUSSPEED)
3282                         clk = 66;
3283                 else
3284                         clk = 33;
3285                 if (cfg & BGE_PCISTATE_32BIT_BUS)
3286                         printf("%u MHz; 32bit\n", clk);
3287                 else
3288                         printf("%u MHz; 64bit\n", clk);
3289         }
3290 }
3291
3292 static int
3293 bge_attach(device_t dev)
3294 {
3295         if_t ifp;
3296         struct bge_softc *sc;
3297         uint32_t hwcfg = 0, misccfg, pcistate;
3298         u_char eaddr[ETHER_ADDR_LEN];
3299         int capmask, error, reg, rid, trys;
3300
3301         sc = device_get_softc(dev);
3302         sc->bge_dev = dev;
3303
3304         BGE_LOCK_INIT(sc, device_get_nameunit(dev));
3305         NET_TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
3306         callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
3307
3308         pci_enable_busmaster(dev);
3309
3310         /*
3311          * Allocate control/status registers.
3312          */
3313         rid = PCIR_BAR(0);
3314         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3315             RF_ACTIVE);
3316
3317         if (sc->bge_res == NULL) {
3318                 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n");
3319                 error = ENXIO;
3320                 goto fail;
3321         }
3322
3323         /* Save various chip information. */
3324         sc->bge_func_addr = pci_get_function(dev);
3325         sc->bge_chipid = bge_chipid(dev);
3326         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
3327         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
3328
3329         /* Set default PHY address. */
3330         sc->bge_phy_addr = 1;
3331          /*
3332           * PHY address mapping for various devices.
3333           *
3334           *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
3335           * ---------+-------+-------+-------+-------+
3336           * BCM57XX  |   1   |   X   |   X   |   X   |
3337           * BCM5704  |   1   |   X   |   1   |   X   |
3338           * BCM5717  |   1   |   8   |   2   |   9   |
3339           * BCM5719  |   1   |   8   |   2   |   9   |
3340           * BCM5720  |   1   |   8   |   2   |   9   |
3341           *
3342           *          | F2 Cu | F2 Sr | F3 Cu | F3 Sr |
3343           * ---------+-------+-------+-------+-------+
3344           * BCM57XX  |   X   |   X   |   X   |   X   |
3345           * BCM5704  |   X   |   X   |   X   |   X   |
3346           * BCM5717  |   X   |   X   |   X   |   X   |
3347           * BCM5719  |   3   |   10  |   4   |   11  |
3348           * BCM5720  |   X   |   X   |   X   |   X   |
3349           *
3350           * Other addresses may respond but they are not
3351           * IEEE compliant PHYs and should be ignored.
3352           */
3353         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
3354             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3355             sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3356                 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) {
3357                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
3358                             BGE_SGDIGSTS_IS_SERDES)
3359                                 sc->bge_phy_addr = sc->bge_func_addr + 8;
3360                         else
3361                                 sc->bge_phy_addr = sc->bge_func_addr + 1;
3362                 } else {
3363                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
3364                             BGE_CPMU_PHY_STRAP_IS_SERDES)
3365                                 sc->bge_phy_addr = sc->bge_func_addr + 8;
3366                         else
3367                                 sc->bge_phy_addr = sc->bge_func_addr + 1;
3368                 }
3369         }
3370
3371         if (bge_has_eaddr(sc))
3372                 sc->bge_flags |= BGE_FLAG_EADDR;
3373
3374         /* Save chipset family. */
3375         switch (sc->bge_asicrev) {
3376         case BGE_ASICREV_BCM5762:
3377         case BGE_ASICREV_BCM57765:
3378         case BGE_ASICREV_BCM57766:
3379                 sc->bge_flags |= BGE_FLAG_57765_PLUS;
3380                 /* FALLTHROUGH */
3381         case BGE_ASICREV_BCM5717:
3382         case BGE_ASICREV_BCM5719:
3383         case BGE_ASICREV_BCM5720:
3384                 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
3385                     BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
3386                     BGE_FLAG_JUMBO_FRAME;
3387                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3388                     sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3389                         /*
3390                          * Enable work around for DMA engine miscalculation
3391                          * of TXMBUF available space.
3392                          */
3393                         sc->bge_flags |= BGE_FLAG_RDMA_BUG;
3394                         if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3395                             sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3396                                 /* Jumbo frame on BCM5719 A0 does not work. */
3397                                 sc->bge_flags &= ~BGE_FLAG_JUMBO;
3398                         }
3399                 }
3400                 break;
3401         case BGE_ASICREV_BCM5755:
3402         case BGE_ASICREV_BCM5761:
3403         case BGE_ASICREV_BCM5784:
3404         case BGE_ASICREV_BCM5785:
3405         case BGE_ASICREV_BCM5787:
3406         case BGE_ASICREV_BCM57780:
3407                 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
3408                     BGE_FLAG_5705_PLUS;
3409                 break;
3410         case BGE_ASICREV_BCM5700:
3411         case BGE_ASICREV_BCM5701:
3412         case BGE_ASICREV_BCM5703:
3413         case BGE_ASICREV_BCM5704:
3414                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
3415                 break;
3416         case BGE_ASICREV_BCM5714_A0:
3417         case BGE_ASICREV_BCM5780:
3418         case BGE_ASICREV_BCM5714:
3419                 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
3420                 /* FALLTHROUGH */
3421         case BGE_ASICREV_BCM5750:
3422         case BGE_ASICREV_BCM5752:
3423         case BGE_ASICREV_BCM5906:
3424                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
3425                 /* FALLTHROUGH */
3426         case BGE_ASICREV_BCM5705:
3427                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
3428                 break;
3429         }
3430
3431         /* Identify chips with APE processor. */
3432         switch (sc->bge_asicrev) {
3433         case BGE_ASICREV_BCM5717:
3434         case BGE_ASICREV_BCM5719:
3435         case BGE_ASICREV_BCM5720:
3436         case BGE_ASICREV_BCM5761:
3437         case BGE_ASICREV_BCM5762:
3438                 sc->bge_flags |= BGE_FLAG_APE;
3439                 break;
3440         }
3441
3442         /* Chips with APE need BAR2 access for APE registers/memory. */
3443         if ((sc->bge_flags & BGE_FLAG_APE) != 0) {
3444                 rid = PCIR_BAR(2);
3445                 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3446                     RF_ACTIVE);
3447                 if (sc->bge_res2 == NULL) {
3448                         device_printf (sc->bge_dev,
3449                             "couldn't map BAR2 memory\n");
3450                         error = ENXIO;
3451                         goto fail;
3452                 }
3453
3454                 /* Enable APE register/memory access by host driver. */
3455                 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3456                 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
3457                     BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
3458                     BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
3459                 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4);
3460
3461                 bge_ape_lock_init(sc);
3462                 bge_ape_read_fw_ver(sc);
3463         }
3464
3465         /* Add SYSCTLs, requires the chipset family to be set. */
3466         bge_add_sysctls(sc);
3467
3468         /* Identify the chips that use an CPMU. */
3469         if (BGE_IS_5717_PLUS(sc) ||
3470             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3471             sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3472             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
3473             sc->bge_asicrev == BGE_ASICREV_BCM57780)
3474                 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
3475         if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
3476                 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
3477         else
3478                 sc->bge_mi_mode = BGE_MIMODE_BASE;
3479         /* Enable auto polling for BCM570[0-5]. */
3480         if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
3481                 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
3482
3483         /*
3484          * All Broadcom controllers have 4GB boundary DMA bug.
3485          * Whenever an address crosses a multiple of the 4GB boundary
3486          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3487          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3488          * state machine will lockup and cause the device to hang.
3489          */
3490         sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
3491
3492         /* BCM5755 or higher and BCM5906 have short DMA bug. */
3493         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3494                 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
3495
3496         /*
3497          * BCM5719 cannot handle DMA requests for DMA segments that
3498          * have larger than 4KB in size.  However the maximum DMA
3499          * segment size created in DMA tag is 4KB for TSO, so we
3500          * wouldn't encounter the issue here.
3501          */
3502         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
3503                 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG;
3504
3505         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3506         if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
3507                 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
3508                     misccfg == BGE_MISCCFG_BOARD_ID_5788M)
3509                         sc->bge_flags |= BGE_FLAG_5788;
3510         }
3511
3512         capmask = BMSR_DEFCAPMASK;
3513         if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
3514             (misccfg == 0x4000 || misccfg == 0x8000)) ||
3515             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3516             pci_get_vendor(dev) == BCOM_VENDORID &&
3517             (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 ||
3518             pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 ||
3519             pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) ||
3520             (pci_get_vendor(dev) == BCOM_VENDORID &&
3521             (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F ||
3522             pci_get_device(dev) == BCOM_DEVICEID_BCM5753F ||
3523             pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) ||
3524             pci_get_device(dev) == BCOM_DEVICEID_BCM57790 ||
3525             pci_get_device(dev) == BCOM_DEVICEID_BCM57791 ||
3526             pci_get_device(dev) == BCOM_DEVICEID_BCM57795 ||
3527             sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3528                 /* These chips are 10/100 only. */
3529                 capmask &= ~BMSR_EXTSTAT;
3530                 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3531         }
3532
3533         /*
3534          * Some controllers seem to require a special firmware to use
3535          * TSO. But the firmware is not available to FreeBSD and Linux
3536          * claims that the TSO performed by the firmware is slower than
3537          * hardware based TSO. Moreover the firmware based TSO has one
3538          * known bug which can't handle TSO if Ethernet header + IP/TCP
3539          * header is greater than 80 bytes. A workaround for the TSO
3540          * bug exist but it seems it's too expensive than not using
3541          * TSO at all. Some hardwares also have the TSO bug so limit
3542          * the TSO to the controllers that are not affected TSO issues
3543          * (e.g. 5755 or higher).
3544          */
3545         if (BGE_IS_5717_PLUS(sc)) {
3546                 /* BCM5717 requires different TSO configuration. */
3547                 sc->bge_flags |= BGE_FLAG_TSO3;
3548                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3549                     sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3550                         /* TSO on BCM5719 A0 does not work. */
3551                         sc->bge_flags &= ~BGE_FLAG_TSO3;
3552                 }
3553         } else if (BGE_IS_5755_PLUS(sc)) {
3554                 /*
3555                  * BCM5754 and BCM5787 shares the same ASIC id so
3556                  * explicit device id check is required.
3557                  * Due to unknown reason TSO does not work on BCM5755M.
3558                  */
3559                 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
3560                     pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
3561                     pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
3562                         sc->bge_flags |= BGE_FLAG_TSO;
3563         }
3564
3565         /*
3566          * Check if this is a PCI-X or PCI Express device.
3567          */
3568         if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
3569                 /*
3570                  * Found a PCI Express capabilities register, this
3571                  * must be a PCI Express device.
3572                  */
3573                 sc->bge_flags |= BGE_FLAG_PCIE;
3574                 sc->bge_expcap = reg;
3575                 /* Extract supported maximum payload size. */
3576                 sc->bge_mps = pci_read_config(dev, sc->bge_expcap +
3577                     PCIER_DEVICE_CAP, 2);
3578                 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD);
3579                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3580                     sc->bge_asicrev == BGE_ASICREV_BCM5720)
3581                         sc->bge_expmrq = 2048;
3582                 else
3583                         sc->bge_expmrq = 4096;
3584                 pci_set_max_read_req(dev, sc->bge_expmrq);
3585         } else {
3586                 /*
3587                  * Check if the device is in PCI-X Mode.
3588                  * (This bit is not valid on PCI Express controllers.)
3589                  */
3590                 if (pci_find_cap(dev, PCIY_PCIX, &reg) == 0)
3591                         sc->bge_pcixcap = reg;
3592                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
3593                     BGE_PCISTATE_PCI_BUSMODE) == 0)
3594                         sc->bge_flags |= BGE_FLAG_PCIX;
3595         }
3596
3597         /*
3598          * The 40bit DMA bug applies to the 5714/5715 controllers and is
3599          * not actually a MAC controller bug but an issue with the embedded
3600          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
3601          */
3602         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
3603                 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
3604         /*
3605          * Some PCI-X bridges are known to trigger write reordering to
3606          * the mailbox registers. Typical phenomena is watchdog timeouts
3607          * caused by out-of-order TX completions.  Enable workaround for
3608          * PCI-X devices that live behind these bridges.
3609          * Note, PCI-X controllers can run in PCI mode so we can't use
3610          * BGE_FLAG_PCIX flag to detect PCI-X controllers.
3611          */
3612         if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0)
3613                 sc->bge_flags |= BGE_FLAG_MBOX_REORDER;
3614         /*
3615          * Allocate the interrupt, using MSI if possible.  These devices
3616          * support 8 MSI messages, but only the first one is used in
3617          * normal operation.
3618          */
3619         rid = 0;
3620         if (pci_find_cap(sc->bge_dev, PCIY_MSI, &reg) == 0) {
3621                 sc->bge_msicap = reg;
3622                 reg = 1;
3623                 if (bge_can_use_msi(sc) && pci_alloc_msi(dev, &reg) == 0) {
3624                         rid = 1;
3625                         sc->bge_flags |= BGE_FLAG_MSI;
3626                 }
3627         }
3628
3629         /*
3630          * All controllers except BCM5700 supports tagged status but
3631          * we use tagged status only for MSI case on BCM5717. Otherwise
3632          * MSI on BCM5717 does not work.
3633          */
3634 #ifndef DEVICE_POLLING
3635         if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
3636                 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
3637 #endif
3638
3639         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3640             RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
3641
3642         if (sc->bge_irq == NULL) {
3643                 device_printf(sc->bge_dev, "couldn't map interrupt\n");
3644                 error = ENXIO;
3645                 goto fail;
3646         }
3647
3648         bge_devinfo(sc);
3649
3650         sc->bge_asf_mode = 0;
3651         /* No ASF if APE present. */
3652         if ((sc->bge_flags & BGE_FLAG_APE) == 0) {
3653                 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3654                     BGE_SRAM_DATA_SIG_MAGIC)) {
3655                         if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
3656                             BGE_HWCFG_ASF) {
3657                                 sc->bge_asf_mode |= ASF_ENABLE;
3658                                 sc->bge_asf_mode |= ASF_STACKUP;
3659                                 if (BGE_IS_575X_PLUS(sc))
3660                                         sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3661                         }
3662                 }
3663         }
3664
3665         bge_stop_fw(sc);
3666         bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
3667         if (bge_reset(sc)) {
3668                 device_printf(sc->bge_dev, "chip reset failed\n");
3669                 error = ENXIO;
3670                 goto fail;
3671         }
3672
3673         bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
3674         bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
3675
3676         if (bge_chipinit(sc)) {
3677                 device_printf(sc->bge_dev, "chip initialization failed\n");
3678                 error = ENXIO;
3679                 goto fail;
3680         }
3681
3682         error = bge_get_eaddr(sc, eaddr);
3683         if (error) {
3684                 device_printf(sc->bge_dev,
3685                     "failed to read station address\n");
3686                 error = ENXIO;
3687                 goto fail;
3688         }
3689
3690         /* 5705 limits RX return ring to 512 entries. */
3691         if (BGE_IS_5717_PLUS(sc))
3692                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3693         else if (BGE_IS_5705_PLUS(sc))
3694                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3695         else
3696                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3697
3698         if (bge_dma_alloc(sc)) {
3699                 device_printf(sc->bge_dev,
3700                     "failed to allocate DMA resources\n");
3701                 error = ENXIO;
3702                 goto fail;
3703         }
3704
3705         /* Set default tuneable values. */
3706         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3707         sc->bge_rx_coal_ticks = 150;
3708         sc->bge_tx_coal_ticks = 150;
3709         sc->bge_rx_max_coal_bds = 10;
3710         sc->bge_tx_max_coal_bds = 10;
3711
3712         /* Initialize checksum features to use. */
3713         sc->bge_csum_features = BGE_CSUM_FEATURES;
3714         if (sc->bge_forced_udpcsum != 0)
3715                 sc->bge_csum_features |= CSUM_UDP;
3716
3717         /* Set up ifnet structure */
3718         ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
3719         if (ifp == NULL) {
3720                 device_printf(sc->bge_dev, "failed to if_alloc()\n");
3721                 error = ENXIO;
3722                 goto fail;
3723         }
3724         if_setsoftc(ifp, sc);
3725         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3726         if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
3727         if_setioctlfn(ifp, bge_ioctl);
3728         if_setstartfn(ifp, bge_start);
3729         if_setinitfn(ifp, bge_init);
3730         if_setgetcounterfn(ifp, bge_get_counter);
3731         if_setsendqlen(ifp, BGE_TX_RING_CNT - 1);
3732         if_setsendqready(ifp);
3733         if_sethwassist(ifp, sc->bge_csum_features);
3734         if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3735             IFCAP_VLAN_MTU);
3736         if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3737                 if_sethwassistbits(ifp, CSUM_TSO, 0);
3738                 if_setcapabilitiesbit(ifp, IFCAP_TSO4 | IFCAP_VLAN_HWTSO, 0);
3739         }
3740 #ifdef IFCAP_VLAN_HWCSUM
3741         if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0);
3742 #endif
3743         if_setcapenable(ifp, if_getcapabilities(ifp));
3744 #ifdef DEVICE_POLLING
3745         if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
3746 #endif
3747
3748         /*
3749          * 5700 B0 chips do not support checksumming correctly due
3750          * to hardware bugs.
3751          */
3752         if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
3753                 if_setcapabilitiesbit(ifp, 0, IFCAP_HWCSUM);
3754                 if_setcapenablebit(ifp, 0, IFCAP_HWCSUM);
3755                 if_sethwassist(ifp, 0);
3756         }
3757
3758         /*
3759          * Figure out what sort of media we have by checking the
3760          * hardware config word in the first 32k of NIC internal memory,
3761          * or fall back to examining the EEPROM if necessary.
3762          * Note: on some BCM5700 cards, this value appears to be unset.
3763          * If that's the case, we have to rely on identifying the NIC
3764          * by its PCI subsystem ID, as we do below for the SysKonnect
3765          * SK-9D41.
3766          */
3767         if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
3768                 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3769         else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
3770             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3771                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
3772                     sizeof(hwcfg))) {
3773                         device_printf(sc->bge_dev, "failed to read EEPROM\n");
3774                         error = ENXIO;
3775                         goto fail;
3776                 }
3777                 hwcfg = ntohl(hwcfg);
3778         }
3779
3780         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
3781         if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
3782             SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
3783                 if (BGE_IS_5705_PLUS(sc)) {
3784                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
3785                         sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3786                 } else
3787                         sc->bge_flags |= BGE_FLAG_TBI;
3788         }
3789
3790         /* Set various PHY bug flags. */
3791         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
3792             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
3793                 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
3794         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
3795             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
3796                 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
3797         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
3798                 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
3799         if (pci_get_subvendor(dev) == DELL_VENDORID)
3800                 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
3801         if ((BGE_IS_5705_PLUS(sc)) &&
3802             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
3803             sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
3804             sc->bge_asicrev != BGE_ASICREV_BCM57780 &&
3805             !BGE_IS_5717_PLUS(sc)) {
3806                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
3807                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3808                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3809                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
3810                         if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
3811                             pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
3812                                 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
3813                         if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
3814                                 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
3815                 } else
3816                         sc->bge_phy_flags |= BGE_PHY_BER_BUG;
3817         }
3818
3819         /*
3820          * Don't enable Ethernet@WireSpeed for the 5700 or the
3821          * 5705 A0 and A1 chips.
3822          */
3823         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3824             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3825             (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
3826             sc->bge_chipid != BGE_CHIPID_BCM5705_A1)))
3827                 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3828
3829         if (sc->bge_flags & BGE_FLAG_TBI) {
3830                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3831                     bge_ifmedia_sts);
3832                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
3833                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
3834                     0, NULL);
3835                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3836                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3837                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3838         } else {
3839                 /*
3840                  * Do transceiver setup and tell the firmware the
3841                  * driver is down so we can try to get access the
3842                  * probe if ASF is running.  Retry a couple of times
3843                  * if we get a conflict with the ASF firmware accessing
3844                  * the PHY.
3845                  */
3846                 trys = 0;
3847                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3848 again:
3849                 bge_asf_driver_up(sc);
3850
3851                 error = mii_attach(dev, &sc->bge_miibus, ifp,
3852                     (ifm_change_cb_t)bge_ifmedia_upd,
3853                     (ifm_stat_cb_t)bge_ifmedia_sts, capmask, sc->bge_phy_addr,
3854                     MII_OFFSET_ANY, MIIF_DOPAUSE);
3855                 if (error != 0) {
3856                         if (trys++ < 4) {
3857                                 device_printf(sc->bge_dev, "Try again\n");
3858                                 bge_miibus_writereg(sc->bge_dev,
3859                                     sc->bge_phy_addr, MII_BMCR, BMCR_RESET);
3860                                 goto again;
3861                         }
3862                         device_printf(sc->bge_dev, "attaching PHYs failed\n");
3863                         goto fail;
3864                 }
3865
3866                 /*
3867                  * Now tell the firmware we are going up after probing the PHY
3868                  */
3869                 if (sc->bge_asf_mode & ASF_STACKUP)
3870                         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3871         }
3872
3873         /*
3874          * When using the BCM5701 in PCI-X mode, data corruption has
3875          * been observed in the first few bytes of some received packets.
3876          * Aligning the packet buffer in memory eliminates the corruption.
3877          * Unfortunately, this misaligns the packet payloads.  On platforms
3878          * which do not support unaligned accesses, we will realign the
3879          * payloads by copying the received packets.
3880          */
3881         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
3882             sc->bge_flags & BGE_FLAG_PCIX)
3883                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
3884
3885         /*
3886          * Call MI attach routine.
3887          */
3888         ether_ifattach(ifp, eaddr);
3889
3890         /* Tell upper layer we support long frames. */
3891         if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
3892
3893         /*
3894          * Hookup IRQ last.
3895          */
3896         if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
3897                 /* Take advantage of single-shot MSI. */
3898                 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
3899                     ~BGE_MSIMODE_ONE_SHOT_DISABLE);
3900                 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
3901                     taskqueue_thread_enqueue, &sc->bge_tq);
3902                 if (sc->bge_tq == NULL) {
3903                         device_printf(dev, "could not create taskqueue.\n");
3904                         ether_ifdetach(ifp);
3905                         error = ENOMEM;
3906                         goto fail;
3907                 }
3908                 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET,
3909                     "%s taskq", device_get_nameunit(sc->bge_dev));
3910                 if (error != 0) {
3911                         device_printf(dev, "could not start threads.\n");
3912                         ether_ifdetach(ifp);
3913                         goto fail;
3914                 }
3915                 error = bus_setup_intr(dev, sc->bge_irq,
3916                     INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
3917                     &sc->bge_intrhand);
3918         } else
3919                 error = bus_setup_intr(dev, sc->bge_irq,
3920                     INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
3921                     &sc->bge_intrhand);
3922
3923         if (error) {
3924                 ether_ifdetach(ifp);
3925                 device_printf(sc->bge_dev, "couldn't set up irq\n");
3926                 goto fail;
3927         }
3928
3929         /* Attach driver debugnet methods. */
3930         DEBUGNET_SET(ifp, bge);
3931
3932 fail:
3933         if (error)
3934                 bge_detach(dev);
3935         return (error);
3936 }
3937
3938 static int
3939 bge_detach(device_t dev)
3940 {
3941         struct bge_softc *sc;
3942         if_t ifp;
3943
3944         sc = device_get_softc(dev);
3945         ifp = sc->bge_ifp;
3946
3947 #ifdef DEVICE_POLLING
3948         if (if_getcapenable(ifp) & IFCAP_POLLING)
3949                 ether_poll_deregister(ifp);
3950 #endif
3951
3952         if (device_is_attached(dev)) {
3953                 ether_ifdetach(ifp);
3954                 BGE_LOCK(sc);
3955                 bge_stop(sc);
3956                 BGE_UNLOCK(sc);
3957                 callout_drain(&sc->bge_stat_ch);
3958         }
3959
3960         if (sc->bge_tq)
3961                 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3962
3963         if (sc->bge_flags & BGE_FLAG_TBI)
3964                 ifmedia_removeall(&sc->bge_ifmedia);
3965         else if (sc->bge_miibus != NULL) {
3966                 bus_generic_detach(dev);
3967                 device_delete_child(dev, sc->bge_miibus);
3968         }
3969
3970         bge_release_resources(sc);
3971
3972         return (0);
3973 }
3974
3975 static void
3976 bge_release_resources(struct bge_softc *sc)
3977 {
3978         device_t dev;
3979
3980         dev = sc->bge_dev;
3981
3982         if (sc->bge_tq != NULL)
3983                 taskqueue_free(sc->bge_tq);
3984
3985         if (sc->bge_intrhand != NULL)
3986                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3987
3988         if (sc->bge_irq != NULL) {
3989                 bus_release_resource(dev, SYS_RES_IRQ,
3990                     rman_get_rid(sc->bge_irq), sc->bge_irq);
3991                 pci_release_msi(dev);
3992         }
3993
3994         if (sc->bge_res != NULL)
3995                 bus_release_resource(dev, SYS_RES_MEMORY,
3996                     rman_get_rid(sc->bge_res), sc->bge_res);
3997
3998         if (sc->bge_res2 != NULL)
3999                 bus_release_resource(dev, SYS_RES_MEMORY,
4000                     rman_get_rid(sc->bge_res2), sc->bge_res2);
4001
4002         if (sc->bge_ifp != NULL)
4003                 if_free(sc->bge_ifp);
4004
4005         bge_dma_free(sc);
4006
4007         if (mtx_initialized(&sc->bge_mtx))      /* XXX */
4008                 BGE_LOCK_DESTROY(sc);
4009 }
4010
4011 static int
4012 bge_reset(struct bge_softc *sc)
4013 {
4014         device_t dev;
4015         uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val;
4016         void (*write_op)(struct bge_softc *, int, int);
4017         uint16_t devctl;
4018         int i;
4019
4020         dev = sc->bge_dev;
4021
4022         mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
4023         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4024                 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
4025         mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
4026
4027         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
4028             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
4029                 if (sc->bge_flags & BGE_FLAG_PCIE)
4030                         write_op = bge_writemem_direct;
4031                 else
4032                         write_op = bge_writemem_ind;
4033         } else
4034                 write_op = bge_writereg_ind;
4035
4036         if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
4037             sc->bge_asicrev != BGE_ASICREV_BCM5701) {
4038                 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
4039                 for (i = 0; i < 8000; i++) {
4040                         if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
4041                             BGE_NVRAMSWARB_GNT1)
4042                                 break;
4043                         DELAY(20);
4044                 }
4045                 if (i == 8000) {
4046                         if (bootverbose)
4047                                 device_printf(dev, "NVRAM lock timedout!\n");
4048                 }
4049         }
4050         /* Take APE lock when performing reset. */
4051         bge_ape_lock(sc, BGE_APE_LOCK_GRC);
4052
4053         /* Save some important PCI state. */
4054         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
4055         command = pci_read_config(dev, BGE_PCI_CMD, 4);
4056
4057         pci_write_config(dev, BGE_PCI_MISC_CTL,
4058             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4059             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4060
4061         /* Disable fastboot on controllers that support it. */
4062         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
4063             BGE_IS_5755_PLUS(sc)) {
4064                 if (bootverbose)
4065                         device_printf(dev, "Disabling fastboot\n");
4066                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
4067         }
4068
4069         /*
4070          * Write the magic number to SRAM at offset 0xB50.
4071          * When firmware finishes its initialization it will
4072          * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
4073          */
4074         bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
4075
4076         reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
4077
4078         /* XXX: Broadcom Linux driver. */
4079         if (sc->bge_flags & BGE_FLAG_PCIE) {
4080                 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
4081                     (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) {
4082                         if (CSR_READ_4(sc, 0x7E2C) == 0x60)     /* PCIE 1.0 */
4083                                 CSR_WRITE_4(sc, 0x7E2C, 0x20);
4084                 }
4085                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
4086                         /* Prevent PCIE link training during global reset */
4087                         CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
4088                         reset |= 1 << 29;
4089                 }
4090         }
4091
4092         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4093                 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4094                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
4095                     val | BGE_VCPU_STATUS_DRV_RESET);
4096                 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
4097                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
4098                     val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
4099         }
4100
4101         /*
4102          * Set GPHY Power Down Override to leave GPHY
4103          * powered up in D0 uninitialized.
4104          */
4105         if (BGE_IS_5705_PLUS(sc) &&
4106             (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0)
4107                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
4108
4109         /* Issue global reset */
4110         write_op(sc, BGE_MISC_CFG, reset);
4111
4112         if (sc->bge_flags & BGE_FLAG_PCIE)
4113                 DELAY(100 * 1000);
4114         else
4115                 DELAY(1000);
4116
4117         /* XXX: Broadcom Linux driver. */
4118         if (sc->bge_flags & BGE_FLAG_PCIE) {
4119                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
4120                         DELAY(500000); /* wait for link training to complete */
4121                         val = pci_read_config(dev, 0xC4, 4);
4122                         pci_write_config(dev, 0xC4, val | (1 << 15), 4);
4123                 }
4124                 devctl = pci_read_config(dev,
4125                     sc->bge_expcap + PCIER_DEVICE_CTL, 2);
4126                 /* Clear enable no snoop and disable relaxed ordering. */
4127                 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE |
4128                     PCIEM_CTL_NOSNOOP_ENABLE);
4129                 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL,
4130                     devctl, 2);
4131                 pci_set_max_read_req(dev, sc->bge_expmrq);
4132                 /* Clear error status. */
4133                 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA,
4134                     PCIEM_STA_CORRECTABLE_ERROR |
4135                     PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
4136                     PCIEM_STA_UNSUPPORTED_REQ, 2);
4137         }
4138
4139         /* Reset some of the PCI state that got zapped by reset. */
4140         pci_write_config(dev, BGE_PCI_MISC_CTL,
4141             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4142             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4143         val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
4144         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
4145             (sc->bge_flags & BGE_FLAG_PCIX) != 0)
4146                 val |= BGE_PCISTATE_RETRY_SAME_DMA;
4147         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4148                 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
4149                     BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
4150                     BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
4151         pci_write_config(dev, BGE_PCI_PCISTATE, val, 4);
4152         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
4153         pci_write_config(dev, BGE_PCI_CMD, command, 4);
4154         /*
4155          * Disable PCI-X relaxed ordering to ensure status block update
4156          * comes first then packet buffer DMA. Otherwise driver may
4157          * read stale status block.
4158          */
4159         if (sc->bge_flags & BGE_FLAG_PCIX) {
4160                 devctl = pci_read_config(dev,
4161                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
4162                 devctl &= ~PCIXM_COMMAND_ERO;
4163                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
4164                         devctl &= ~PCIXM_COMMAND_MAX_READ;
4165                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
4166                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4167                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
4168                             PCIXM_COMMAND_MAX_READ);
4169                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
4170                 }
4171                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
4172                     devctl, 2);
4173         }
4174         /* Re-enable MSI, if necessary, and enable the memory arbiter. */
4175         if (BGE_IS_5714_FAMILY(sc)) {
4176                 /* This chip disables MSI on reset. */
4177                 if (sc->bge_flags & BGE_FLAG_MSI) {
4178                         val = pci_read_config(dev,
4179                             sc->bge_msicap + PCIR_MSI_CTRL, 2);
4180                         pci_write_config(dev,
4181                             sc->bge_msicap + PCIR_MSI_CTRL,
4182                             val | PCIM_MSICTRL_MSI_ENABLE, 2);
4183                         val = CSR_READ_4(sc, BGE_MSI_MODE);
4184                         CSR_WRITE_4(sc, BGE_MSI_MODE,
4185                             val | BGE_MSIMODE_ENABLE);
4186                 }
4187                 val = CSR_READ_4(sc, BGE_MARB_MODE);
4188                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
4189         } else
4190                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4191
4192         /* Fix up byte swapping. */
4193         CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
4194
4195         val = CSR_READ_4(sc, BGE_MAC_MODE);
4196         val = (val & ~mac_mode_mask) | mac_mode;
4197         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
4198         DELAY(40);
4199
4200         bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
4201
4202         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4203                 for (i = 0; i < BGE_TIMEOUT; i++) {
4204                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4205                         if (val & BGE_VCPU_STATUS_INIT_DONE)
4206                                 break;
4207                         DELAY(100);
4208                 }
4209                 if (i == BGE_TIMEOUT) {
4210                         device_printf(dev, "reset timed out\n");
4211                         return (1);
4212                 }
4213         } else {
4214                 /*
4215                  * Poll until we see the 1's complement of the magic number.
4216                  * This indicates that the firmware initialization is complete.
4217                  * We expect this to fail if no chip containing the Ethernet
4218                  * address is fitted though.
4219                  */
4220                 for (i = 0; i < BGE_TIMEOUT; i++) {
4221                         DELAY(10);
4222                         val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
4223                         if (val == ~BGE_SRAM_FW_MB_MAGIC)
4224                                 break;
4225                 }
4226
4227                 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
4228                         device_printf(dev,
4229                             "firmware handshake timed out, found 0x%08x\n",
4230                             val);
4231                 /* BCM57765 A0 needs additional time before accessing. */
4232                 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
4233                         DELAY(10 * 1000);       /* XXX */
4234         }
4235
4236         /*
4237          * The 5704 in TBI mode apparently needs some special
4238          * adjustment to insure the SERDES drive level is set
4239          * to 1.2V.
4240          */
4241         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
4242             sc->bge_flags & BGE_FLAG_TBI) {
4243                 val = CSR_READ_4(sc, BGE_SERDES_CFG);
4244                 val = (val & ~0xFFF) | 0x880;
4245                 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
4246         }
4247
4248         /* XXX: Broadcom Linux driver. */
4249         if (sc->bge_flags & BGE_FLAG_PCIE &&
4250             !BGE_IS_5717_PLUS(sc) &&
4251             sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
4252             sc->bge_asicrev != BGE_ASICREV_BCM5785) {
4253                 /* Enable Data FIFO protection. */
4254                 val = CSR_READ_4(sc, 0x7C00);
4255                 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
4256         }
4257
4258         if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
4259                 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
4260                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
4261
4262         return (0);
4263 }
4264
4265 static __inline void
4266 bge_rxreuse_std(struct bge_softc *sc, int i)
4267 {
4268         struct bge_rx_bd *r;
4269
4270         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
4271         r->bge_flags = BGE_RXBDFLAG_END;
4272         r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
4273         r->bge_idx = i;
4274         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4275 }
4276
4277 static __inline void
4278 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
4279 {
4280         struct bge_extrx_bd *r;
4281
4282         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
4283         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
4284         r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
4285         r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
4286         r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
4287         r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
4288         r->bge_idx = i;
4289         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4290 }
4291
4292 /*
4293  * Frame reception handling. This is called if there's a frame
4294  * on the receive return list.
4295  *
4296  * Note: we have to be able to handle two possibilities here:
4297  * 1) the frame is from the jumbo receive ring
4298  * 2) the frame is from the standard receive ring
4299  */
4300
4301 static int
4302 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
4303 {
4304         if_t ifp;
4305         int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
4306         uint16_t rx_cons;
4307
4308         rx_cons = sc->bge_rx_saved_considx;
4309
4310         /* Nothing to do. */
4311         if (rx_cons == rx_prod)
4312                 return (rx_npkts);
4313
4314         ifp = sc->bge_ifp;
4315
4316         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4317             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
4318         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4319             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
4320         if (BGE_IS_JUMBO_CAPABLE(sc) &&
4321             if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
4322             ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))
4323                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4324                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
4325
4326         while (rx_cons != rx_prod) {
4327                 struct bge_rx_bd        *cur_rx;
4328                 uint32_t                rxidx;
4329                 struct mbuf             *m = NULL;
4330                 uint16_t                vlan_tag = 0;
4331                 int                     have_tag = 0;
4332
4333 #ifdef DEVICE_POLLING
4334                 if (if_getcapenable(ifp) & IFCAP_POLLING) {
4335                         if (sc->rxcycles <= 0)
4336                                 break;
4337                         sc->rxcycles--;
4338                 }
4339 #endif
4340
4341                 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
4342
4343                 rxidx = cur_rx->bge_idx;
4344                 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
4345
4346                 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING &&
4347                     cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
4348                         have_tag = 1;
4349                         vlan_tag = cur_rx->bge_vlan_tag;
4350                 }
4351
4352                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
4353                         jumbocnt++;
4354                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
4355                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4356                                 bge_rxreuse_jumbo(sc, rxidx);
4357                                 continue;
4358                         }
4359                         if (bge_newbuf_jumbo(sc, rxidx) != 0) {
4360                                 bge_rxreuse_jumbo(sc, rxidx);
4361                                 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
4362                                 continue;
4363                         }
4364                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4365                 } else {
4366                         stdcnt++;
4367                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
4368                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4369                                 bge_rxreuse_std(sc, rxidx);
4370                                 continue;
4371                         }
4372                         if (bge_newbuf_std(sc, rxidx) != 0) {
4373                                 bge_rxreuse_std(sc, rxidx);
4374                                 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
4375                                 continue;
4376                         }
4377                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4378                 }
4379
4380                 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
4381 #ifndef __NO_STRICT_ALIGNMENT
4382                 /*
4383                  * For architectures with strict alignment we must make sure
4384                  * the payload is aligned.
4385                  */
4386                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
4387                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
4388                             cur_rx->bge_len);
4389                         m->m_data += ETHER_ALIGN;
4390                 }
4391 #endif
4392                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
4393                 m->m_pkthdr.rcvif = ifp;
4394
4395                 if (if_getcapenable(ifp) & IFCAP_RXCSUM)
4396                         bge_rxcsum(sc, cur_rx, m);
4397
4398                 /*
4399                  * If we received a packet with a vlan tag,
4400                  * attach that information to the packet.
4401                  */
4402                 if (have_tag) {
4403                         m->m_pkthdr.ether_vtag = vlan_tag;
4404                         m->m_flags |= M_VLANTAG;
4405                 }
4406
4407                 if (holdlck != 0) {
4408                         BGE_UNLOCK(sc);
4409                         if_input(ifp, m);
4410                         BGE_LOCK(sc);
4411                 } else
4412                         if_input(ifp, m);
4413                 rx_npkts++;
4414
4415                 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4416                         return (rx_npkts);
4417         }
4418
4419         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4420             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
4421         if (stdcnt > 0)
4422                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4423                     sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
4424
4425         if (jumbocnt > 0)
4426                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4427                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
4428
4429         sc->bge_rx_saved_considx = rx_cons;
4430         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
4431         if (stdcnt)
4432                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
4433                     BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT);
4434         if (jumbocnt)
4435                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
4436                     BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT);
4437 #ifdef notyet
4438         /*
4439          * This register wraps very quickly under heavy packet drops.
4440          * If you need correct statistics, you can enable this check.
4441          */
4442         if (BGE_IS_5705_PLUS(sc))
4443                 if_incierrors(ifp, CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS));
4444 #endif
4445         return (rx_npkts);
4446 }
4447
4448 static void
4449 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
4450 {
4451
4452         if (BGE_IS_5717_PLUS(sc)) {
4453                 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
4454                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4455                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4456                                 if ((cur_rx->bge_error_flag &
4457                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
4458                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4459                         }
4460                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
4461                                 m->m_pkthdr.csum_data =
4462                                     cur_rx->bge_tcp_udp_csum;
4463                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4464                                     CSUM_PSEUDO_HDR;
4465                         }
4466                 }
4467         } else {
4468                 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4469                         m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4470                         if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
4471                                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4472                 }
4473                 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
4474                     m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
4475                         m->m_pkthdr.csum_data =
4476                             cur_rx->bge_tcp_udp_csum;
4477                         m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4478                             CSUM_PSEUDO_HDR;
4479                 }
4480         }
4481 }
4482
4483 static void
4484 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
4485 {
4486         struct bge_tx_bd *cur_tx;
4487         if_t ifp;
4488
4489         BGE_LOCK_ASSERT(sc);
4490
4491         /* Nothing to do. */
4492         if (sc->bge_tx_saved_considx == tx_cons)
4493                 return;
4494
4495         ifp = sc->bge_ifp;
4496
4497         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4498             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
4499         /*
4500          * Go through our tx ring and free mbufs for those
4501          * frames that have been sent.
4502          */
4503         while (sc->bge_tx_saved_considx != tx_cons) {
4504                 uint32_t                idx;
4505
4506                 idx = sc->bge_tx_saved_considx;
4507                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
4508                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
4509                         if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
4510                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
4511                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
4512                             sc->bge_cdata.bge_tx_dmamap[idx],
4513                             BUS_DMASYNC_POSTWRITE);
4514                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
4515                             sc->bge_cdata.bge_tx_dmamap[idx]);
4516                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
4517                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
4518                 }
4519                 sc->bge_txcnt--;
4520                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
4521         }
4522
4523         if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
4524         if (sc->bge_txcnt == 0)
4525                 sc->bge_timer = 0;
4526 }
4527
4528 #ifdef DEVICE_POLLING
4529 static int
4530 bge_poll(if_t ifp, enum poll_cmd cmd, int count)
4531 {
4532         struct bge_softc *sc = if_getsoftc(ifp);
4533         uint16_t rx_prod, tx_cons;
4534         uint32_t statusword;
4535         int rx_npkts = 0;
4536
4537         BGE_LOCK(sc);
4538         if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
4539                 BGE_UNLOCK(sc);
4540                 return (rx_npkts);
4541         }
4542
4543         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4544             sc->bge_cdata.bge_status_map,
4545             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4546         /* Fetch updates from the status block. */
4547         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4548         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4549
4550         statusword = sc->bge_ldata.bge_status_block->bge_status;
4551         /* Clear the status so the next pass only sees the changes. */
4552         sc->bge_ldata.bge_status_block->bge_status = 0;
4553
4554         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4555             sc->bge_cdata.bge_status_map,
4556             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4557
4558         /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
4559         if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
4560                 sc->bge_link_evt++;
4561
4562         if (cmd == POLL_AND_CHECK_STATUS)
4563                 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4564                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4565                     sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
4566                         bge_link_upd(sc);
4567
4568         sc->rxcycles = count;
4569         rx_npkts = bge_rxeof(sc, rx_prod, 1);
4570         if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
4571                 BGE_UNLOCK(sc);
4572                 return (rx_npkts);
4573         }
4574         bge_txeof(sc, tx_cons);
4575         if (!if_sendq_empty(ifp))
4576                 bge_start_locked(ifp);
4577
4578         BGE_UNLOCK(sc);
4579         return (rx_npkts);
4580 }
4581 #endif /* DEVICE_POLLING */
4582
4583 static int
4584 bge_msi_intr(void *arg)
4585 {
4586         struct bge_softc *sc;
4587
4588         sc = (struct bge_softc *)arg;
4589         /*
4590          * This interrupt is not shared and controller already
4591          * disabled further interrupt.
4592          */
4593         taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
4594         return (FILTER_HANDLED);
4595 }
4596
4597 static void
4598 bge_intr_task(void *arg, int pending)
4599 {
4600         struct bge_softc *sc;
4601         if_t ifp;
4602         uint32_t status, status_tag;
4603         uint16_t rx_prod, tx_cons;
4604
4605         sc = (struct bge_softc *)arg;
4606         ifp = sc->bge_ifp;
4607
4608         BGE_LOCK(sc);
4609         if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
4610                 BGE_UNLOCK(sc);
4611                 return;
4612         }
4613
4614         /* Get updated status block. */
4615         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4616             sc->bge_cdata.bge_status_map,
4617             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4618
4619         /* Save producer/consumer indices. */
4620         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4621         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4622         status = sc->bge_ldata.bge_status_block->bge_status;
4623         status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
4624         /* Dirty the status flag. */
4625         sc->bge_ldata.bge_status_block->bge_status = 0;
4626         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4627             sc->bge_cdata.bge_status_map,
4628             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4629         if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
4630                 status_tag = 0;
4631
4632         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
4633                 bge_link_upd(sc);
4634
4635         /* Let controller work. */
4636         bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
4637
4638         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
4639             sc->bge_rx_saved_considx != rx_prod) {
4640                 /* Check RX return ring producer/consumer. */
4641                 BGE_UNLOCK(sc);
4642                 bge_rxeof(sc, rx_prod, 0);
4643                 BGE_LOCK(sc);
4644         }
4645         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4646                 /* Check TX ring producer/consumer. */
4647                 bge_txeof(sc, tx_cons);
4648                 if (!if_sendq_empty(ifp))
4649                         bge_start_locked(ifp);
4650         }
4651         BGE_UNLOCK(sc);
4652 }
4653
4654 static void
4655 bge_intr(void *xsc)
4656 {
4657         struct bge_softc *sc;
4658         if_t ifp;
4659         uint32_t statusword;
4660         uint16_t rx_prod, tx_cons;
4661
4662         sc = xsc;
4663
4664         BGE_LOCK(sc);
4665
4666         ifp = sc->bge_ifp;
4667
4668 #ifdef DEVICE_POLLING
4669         if (if_getcapenable(ifp) & IFCAP_POLLING) {
4670                 BGE_UNLOCK(sc);
4671                 return;
4672         }
4673 #endif
4674
4675         /*
4676          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
4677          * disable interrupts by writing nonzero like we used to, since with
4678          * our current organization this just gives complications and
4679          * pessimizations for re-enabling interrupts.  We used to have races
4680          * instead of the necessary complications.  Disabling interrupts
4681          * would just reduce the chance of a status update while we are
4682          * running (by switching to the interrupt-mode coalescence
4683          * parameters), but this chance is already very low so it is more
4684          * efficient to get another interrupt than prevent it.
4685          *
4686          * We do the ack first to ensure another interrupt if there is a
4687          * status update after the ack.  We don't check for the status
4688          * changing later because it is more efficient to get another
4689          * interrupt than prevent it, not quite as above (not checking is
4690          * a smaller optimization than not toggling the interrupt enable,
4691          * since checking doesn't involve PCI accesses and toggling require
4692          * the status check).  So toggling would probably be a pessimization
4693          * even with MSI.  It would only be needed for using a task queue.
4694          */
4695         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4696
4697         /*
4698          * Do the mandatory PCI flush as well as get the link status.
4699          */
4700         statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
4701
4702         /* Make sure the descriptor ring indexes are coherent. */
4703         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4704             sc->bge_cdata.bge_status_map,
4705             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4706         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4707         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4708         sc->bge_ldata.bge_status_block->bge_status = 0;
4709         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4710             sc->bge_cdata.bge_status_map,
4711             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4712
4713         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4714             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4715             statusword || sc->bge_link_evt)
4716                 bge_link_upd(sc);
4717
4718         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4719                 /* Check RX return ring producer/consumer. */
4720                 bge_rxeof(sc, rx_prod, 1);
4721         }
4722
4723         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4724                 /* Check TX ring producer/consumer. */
4725                 bge_txeof(sc, tx_cons);
4726         }
4727
4728         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
4729             !if_sendq_empty(ifp))
4730                 bge_start_locked(ifp);
4731
4732         BGE_UNLOCK(sc);
4733 }
4734
4735 static void
4736 bge_asf_driver_up(struct bge_softc *sc)
4737 {
4738         if (sc->bge_asf_mode & ASF_STACKUP) {
4739                 /* Send ASF heartbeat aprox. every 2s */
4740                 if (sc->bge_asf_count)
4741                         sc->bge_asf_count --;
4742                 else {
4743                         sc->bge_asf_count = 2;
4744                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4745                             BGE_FW_CMD_DRV_ALIVE);
4746                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4747                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
4748                             BGE_FW_HB_TIMEOUT_SEC);
4749                         CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
4750                             CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4751                             BGE_RX_CPU_DRV_EVENT);
4752                 }
4753         }
4754 }
4755
4756 static void
4757 bge_tick(void *xsc)
4758 {
4759         struct bge_softc *sc = xsc;
4760         struct mii_data *mii = NULL;
4761
4762         BGE_LOCK_ASSERT(sc);
4763
4764         /* Synchronize with possible callout reset/stop. */
4765         if (callout_pending(&sc->bge_stat_ch) ||
4766             !callout_active(&sc->bge_stat_ch))
4767                 return;
4768
4769         if (BGE_IS_5705_PLUS(sc))
4770                 bge_stats_update_regs(sc);
4771         else
4772                 bge_stats_update(sc);
4773
4774         /* XXX Add APE heartbeat check here? */
4775
4776         if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4777                 mii = device_get_softc(sc->bge_miibus);
4778                 /*
4779                  * Do not touch PHY if we have link up. This could break
4780                  * IPMI/ASF mode or produce extra input errors
4781                  * (extra errors was reported for bcm5701 & bcm5704).
4782                  */
4783                 if (!sc->bge_link)
4784                         mii_tick(mii);
4785         } else {
4786                 /*
4787                  * Since in TBI mode auto-polling can't be used we should poll
4788                  * link status manually. Here we register pending link event
4789                  * and trigger interrupt.
4790                  */
4791 #ifdef DEVICE_POLLING
4792                 /* In polling mode we poll link state in bge_poll(). */
4793                 if (!(if_getcapenable(sc->bge_ifp) & IFCAP_POLLING))
4794 #endif
4795                 {
4796                 sc->bge_link_evt++;
4797                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4798                     sc->bge_flags & BGE_FLAG_5788)
4799                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4800                 else
4801                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4802                 }
4803         }
4804
4805         bge_asf_driver_up(sc);
4806         bge_watchdog(sc);
4807
4808         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4809 }
4810
4811 static void
4812 bge_stats_update_regs(struct bge_softc *sc)
4813 {
4814         if_t ifp;
4815         struct bge_mac_stats *stats;
4816         uint32_t val;
4817
4818         ifp = sc->bge_ifp;
4819         stats = &sc->bge_mac_stats;
4820
4821         stats->ifHCOutOctets +=
4822             CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4823         stats->etherStatsCollisions +=
4824             CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4825         stats->outXonSent +=
4826             CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4827         stats->outXoffSent +=
4828             CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4829         stats->dot3StatsInternalMacTransmitErrors +=
4830             CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4831         stats->dot3StatsSingleCollisionFrames +=
4832             CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4833         stats->dot3StatsMultipleCollisionFrames +=
4834             CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4835         stats->dot3StatsDeferredTransmissions +=
4836             CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4837         stats->dot3StatsExcessiveCollisions +=
4838             CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4839         stats->dot3StatsLateCollisions +=
4840             CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4841         stats->ifHCOutUcastPkts +=
4842             CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4843         stats->ifHCOutMulticastPkts +=
4844             CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4845         stats->ifHCOutBroadcastPkts +=
4846             CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4847
4848         stats->ifHCInOctets +=
4849             CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4850         stats->etherStatsFragments +=
4851             CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4852         stats->ifHCInUcastPkts +=
4853             CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4854         stats->ifHCInMulticastPkts +=
4855             CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4856         stats->ifHCInBroadcastPkts +=
4857             CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4858         stats->dot3StatsFCSErrors +=
4859             CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4860         stats->dot3StatsAlignmentErrors +=
4861             CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4862         stats->xonPauseFramesReceived +=
4863             CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4864         stats->xoffPauseFramesReceived +=
4865             CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4866         stats->macControlFramesReceived +=
4867             CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4868         stats->xoffStateEntered +=
4869             CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4870         stats->dot3StatsFramesTooLong +=
4871             CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4872         stats->etherStatsJabbers +=
4873             CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4874         stats->etherStatsUndersizePkts +=
4875             CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4876
4877         stats->FramesDroppedDueToFilters +=
4878             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4879         stats->DmaWriteQueueFull +=
4880             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4881         stats->DmaWriteHighPriQueueFull +=
4882             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4883         stats->NoMoreRxBDs +=
4884             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4885         /*
4886          * XXX
4887          * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS
4888          * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0
4889          * includes number of unwanted multicast frames.  This comes
4890          * from silicon bug and known workaround to get rough(not
4891          * exact) counter is to enable interrupt on MBUF low water
4892          * attention.  This can be accomplished by setting
4893          * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE,
4894          * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and
4895          * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL.
4896          * However that change would generate more interrupts and
4897          * there are still possibilities of losing multiple frames
4898          * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling.
4899          * Given that the workaround still would not get correct
4900          * counter I don't think it's worth to implement it.  So
4901          * ignore reading the counter on controllers that have the
4902          * silicon bug.
4903          */
4904         if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
4905             sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
4906             sc->bge_chipid != BGE_CHIPID_BCM5720_A0)
4907                 stats->InputDiscards +=
4908                     CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4909         stats->InputErrors +=
4910             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4911         stats->RecvThresholdHit +=
4912             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4913
4914         if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
4915                 /*
4916                  * If controller transmitted more than BGE_NUM_RDMA_CHANNELS
4917                  * frames, it's safe to disable workaround for DMA engine's
4918                  * miscalculation of TXMBUF space.
4919                  */
4920                 if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts +
4921                     stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) {
4922                         val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
4923                         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
4924                                 val &= ~BGE_RDMA_TX_LENGTH_WA_5719;
4925                         else
4926                                 val &= ~BGE_RDMA_TX_LENGTH_WA_5720;
4927                         CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
4928                         sc->bge_flags &= ~BGE_FLAG_RDMA_BUG;
4929                 }
4930         }
4931 }
4932
4933 static void
4934 bge_stats_clear_regs(struct bge_softc *sc)
4935 {
4936
4937         CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4938         CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4939         CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4940         CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4941         CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4942         CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4943         CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4944         CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4945         CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4946         CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4947         CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4948         CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4949         CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4950
4951         CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4952         CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4953         CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4954         CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4955         CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4956         CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4957         CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4958         CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4959         CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4960         CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4961         CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4962         CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4963         CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4964         CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4965
4966         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4967         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4968         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4969         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4970         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4971         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4972         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4973 }
4974
4975 static void
4976 bge_stats_update(struct bge_softc *sc)
4977 {
4978         if_t ifp;
4979         bus_size_t stats;
4980         uint32_t cnt;   /* current register value */
4981
4982         ifp = sc->bge_ifp;
4983
4984         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
4985
4986 #define READ_STAT(sc, stats, stat) \
4987         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
4988
4989         cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
4990         if_inc_counter(ifp, IFCOUNTER_COLLISIONS, cnt - sc->bge_tx_collisions);
4991         sc->bge_tx_collisions = cnt;
4992
4993         cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo);
4994         if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_nobds);
4995         sc->bge_rx_nobds = cnt;
4996         cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo);
4997         if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_inerrs);
4998         sc->bge_rx_inerrs = cnt;
4999         cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
5000         if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_discards);
5001         sc->bge_rx_discards = cnt;
5002
5003         cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
5004         if_inc_counter(ifp, IFCOUNTER_OERRORS, cnt - sc->bge_tx_discards);
5005         sc->bge_tx_discards = cnt;
5006
5007 #undef  READ_STAT
5008 }
5009
5010 /*
5011  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
5012  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
5013  * but when such padded frames employ the bge IP/TCP checksum offload,
5014  * the hardware checksum assist gives incorrect results (possibly
5015  * from incorporating its own padding into the UDP/TCP checksum; who knows).
5016  * If we pad such runts with zeros, the onboard checksum comes out correct.
5017  */
5018 static __inline int
5019 bge_cksum_pad(struct mbuf *m)
5020 {
5021         int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
5022         struct mbuf *last;
5023
5024         /* If there's only the packet-header and we can pad there, use it. */
5025         if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
5026             M_TRAILINGSPACE(m) >= padlen) {
5027                 last = m;
5028         } else {
5029                 /*
5030                  * Walk packet chain to find last mbuf. We will either
5031                  * pad there, or append a new mbuf and pad it.
5032                  */
5033                 for (last = m; last->m_next != NULL; last = last->m_next);
5034                 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
5035                         /* Allocate new empty mbuf, pad it. Compact later. */
5036                         struct mbuf *n;
5037
5038                         MGET(n, M_NOWAIT, MT_DATA);
5039                         if (n == NULL)
5040                                 return (ENOBUFS);
5041                         n->m_len = 0;
5042                         last->m_next = n;
5043                         last = n;
5044                 }
5045         }
5046
5047         /* Now zero the pad area, to avoid the bge cksum-assist bug. */
5048         memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
5049         last->m_len += padlen;
5050         m->m_pkthdr.len += padlen;
5051
5052         return (0);
5053 }
5054
5055 static struct mbuf *
5056 bge_check_short_dma(struct mbuf *m)
5057 {
5058         struct mbuf *n;
5059         int found;
5060
5061         /*
5062          * If device receive two back-to-back send BDs with less than
5063          * or equal to 8 total bytes then the device may hang.  The two
5064          * back-to-back send BDs must in the same frame for this failure
5065          * to occur.  Scan mbuf chains and see whether two back-to-back
5066          * send BDs are there. If this is the case, allocate new mbuf
5067          * and copy the frame to workaround the silicon bug.
5068          */
5069         for (n = m, found = 0; n != NULL; n = n->m_next) {
5070                 if (n->m_len < 8) {
5071                         found++;
5072                         if (found > 1)
5073                                 break;
5074                         continue;
5075                 }
5076                 found = 0;
5077         }
5078
5079         if (found > 1) {
5080                 n = m_defrag(m, M_NOWAIT);
5081                 if (n == NULL)
5082                         m_freem(m);
5083         } else
5084                 n = m;
5085         return (n);
5086 }
5087
5088 static struct mbuf *
5089 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
5090     uint16_t *flags)
5091 {
5092         struct ip *ip;
5093         struct tcphdr *tcp;
5094         struct mbuf *n;
5095         uint16_t hlen;
5096         uint32_t poff;
5097
5098         if (M_WRITABLE(m) == 0) {
5099                 /* Get a writable copy. */
5100                 n = m_dup(m, M_NOWAIT);
5101                 m_freem(m);
5102                 if (n == NULL)
5103                         return (NULL);
5104                 m = n;
5105         }
5106         m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
5107         if (m == NULL)
5108                 return (NULL);
5109         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5110         poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
5111         m = m_pullup(m, poff + sizeof(struct tcphdr));
5112         if (m == NULL)
5113                 return (NULL);
5114         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5115         m = m_pullup(m, poff + (tcp->th_off << 2));
5116         if (m == NULL)
5117                 return (NULL);
5118         /*
5119          * It seems controller doesn't modify IP length and TCP pseudo
5120          * checksum. These checksum computed by upper stack should be 0.
5121          */
5122         *mss = m->m_pkthdr.tso_segsz;
5123         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5124         ip->ip_sum = 0;
5125         ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
5126         /* Clear pseudo checksum computed by TCP stack. */
5127         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5128         tcp->th_sum = 0;
5129         /*
5130          * Broadcom controllers uses different descriptor format for
5131          * TSO depending on ASIC revision. Due to TSO-capable firmware
5132          * license issue and lower performance of firmware based TSO
5133          * we only support hardware based TSO.
5134          */
5135         /* Calculate header length, incl. TCP/IP options, in 32 bit units. */
5136         hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
5137         if (sc->bge_flags & BGE_FLAG_TSO3) {
5138                 /*
5139                  * For BCM5717 and newer controllers, hardware based TSO
5140                  * uses the 14 lower bits of the bge_mss field to store the
5141                  * MSS and the upper 2 bits to store the lowest 2 bits of
5142                  * the IP/TCP header length.  The upper 6 bits of the header
5143                  * length are stored in the bge_flags[14:10,4] field.  Jumbo
5144                  * frames are supported.
5145                  */
5146                 *mss |= ((hlen & 0x3) << 14);
5147                 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2);
5148         } else {
5149                 /*
5150                  * For BCM5755 and newer controllers, hardware based TSO uses
5151                  * the lower 11 bits to store the MSS and the upper 5 bits to
5152                  * store the IP/TCP header length. Jumbo frames are not
5153                  * supported.
5154                  */
5155                 *mss |= (hlen << 11);
5156         }
5157         return (m);
5158 }
5159
5160 /*
5161  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
5162  * pointers to descriptors.
5163  */
5164 static int
5165 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
5166 {
5167         bus_dma_segment_t       segs[BGE_NSEG_NEW];
5168         bus_dmamap_t            map;
5169         struct bge_tx_bd        *d;
5170         struct mbuf             *m = *m_head;
5171         uint32_t                idx = *txidx;
5172         uint16_t                csum_flags, mss, vlan_tag;
5173         int                     nsegs, i, error;
5174
5175         csum_flags = 0;
5176         mss = 0;
5177         vlan_tag = 0;
5178         if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
5179             m->m_next != NULL) {
5180                 *m_head = bge_check_short_dma(m);
5181                 if (*m_head == NULL)
5182                         return (ENOBUFS);
5183                 m = *m_head;
5184         }
5185         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5186                 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
5187                 if (*m_head == NULL)
5188                         return (ENOBUFS);
5189                 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
5190                     BGE_TXBDFLAG_CPU_POST_DMA;
5191         } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
5192                 if (m->m_pkthdr.csum_flags & CSUM_IP)
5193                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
5194                 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
5195                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
5196                         if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
5197                             (error = bge_cksum_pad(m)) != 0) {
5198                                 m_freem(m);
5199                                 *m_head = NULL;
5200                                 return (error);
5201                         }
5202                 }
5203         }
5204
5205         if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
5206                 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
5207                     m->m_pkthdr.len > ETHER_MAX_LEN)
5208                         csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME;
5209                 if (sc->bge_forced_collapse > 0 &&
5210                     (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
5211                         /*
5212                          * Forcedly collapse mbuf chains to overcome hardware
5213                          * limitation which only support a single outstanding
5214                          * DMA read operation.
5215                          */
5216                         if (sc->bge_forced_collapse == 1)
5217                                 m = m_defrag(m, M_NOWAIT);
5218                         else
5219                                 m = m_collapse(m, M_NOWAIT,
5220                                     sc->bge_forced_collapse);
5221                         if (m == NULL)
5222                                 m = *m_head;
5223                         *m_head = m;
5224                 }
5225         }
5226
5227         map = sc->bge_cdata.bge_tx_dmamap[idx];
5228         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
5229             &nsegs, BUS_DMA_NOWAIT);
5230         if (error == EFBIG) {
5231                 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW);
5232                 if (m == NULL) {
5233                         m_freem(*m_head);
5234                         *m_head = NULL;
5235                         return (ENOBUFS);
5236                 }
5237                 *m_head = m;
5238                 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
5239                     m, segs, &nsegs, BUS_DMA_NOWAIT);
5240                 if (error) {
5241                         m_freem(m);
5242                         *m_head = NULL;
5243                         return (error);
5244                 }
5245         } else if (error != 0)
5246                 return (error);
5247
5248         /* Check if we have enough free send BDs. */
5249         if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
5250                 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5251                 return (ENOBUFS);
5252         }
5253
5254         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
5255
5256         if (m->m_flags & M_VLANTAG) {
5257                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
5258                 vlan_tag = m->m_pkthdr.ether_vtag;
5259         }
5260
5261         if (sc->bge_asicrev == BGE_ASICREV_BCM5762 &&
5262             (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5263                 /*
5264                  * 5725 family of devices corrupts TSO packets when TSO DMA
5265                  * buffers cross into regions which are within MSS bytes of
5266                  * a 4GB boundary.  If we encounter the condition, drop the
5267                  * packet.
5268                  */
5269                 for (i = 0; ; i++) {
5270                         d = &sc->bge_ldata.bge_tx_ring[idx];
5271                         d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5272                         d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5273                         d->bge_len = segs[i].ds_len;
5274                         if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss <
5275                             d->bge_addr.bge_addr_lo)
5276                                 break;
5277                         d->bge_flags = csum_flags;
5278                         d->bge_vlan_tag = vlan_tag;
5279                         d->bge_mss = mss;
5280                         if (i == nsegs - 1)
5281                                 break;
5282                         BGE_INC(idx, BGE_TX_RING_CNT);
5283                 }
5284                 if (i != nsegs - 1) {
5285                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map,
5286                             BUS_DMASYNC_POSTWRITE);
5287                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5288                         m_freem(*m_head);
5289                         *m_head = NULL;
5290                         return (EIO);
5291                 }
5292         } else {
5293                 for (i = 0; ; i++) {
5294                         d = &sc->bge_ldata.bge_tx_ring[idx];
5295                         d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5296                         d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5297                         d->bge_len = segs[i].ds_len;
5298                         d->bge_flags = csum_flags;
5299                         d->bge_vlan_tag = vlan_tag;
5300                         d->bge_mss = mss;
5301                         if (i == nsegs - 1)
5302                                 break;
5303                         BGE_INC(idx, BGE_TX_RING_CNT);
5304                 }
5305         }
5306
5307         /* Mark the last segment as end of packet... */
5308         d->bge_flags |= BGE_TXBDFLAG_END;
5309
5310         /*
5311          * Insure that the map for this transmission
5312          * is placed at the array index of the last descriptor
5313          * in this chain.
5314          */
5315         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
5316         sc->bge_cdata.bge_tx_dmamap[idx] = map;
5317         sc->bge_cdata.bge_tx_chain[idx] = m;
5318         sc->bge_txcnt += nsegs;
5319
5320         BGE_INC(idx, BGE_TX_RING_CNT);
5321         *txidx = idx;
5322
5323         return (0);
5324 }
5325
5326 /*
5327  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5328  * to the mbuf data regions directly in the transmit descriptors.
5329  */
5330 static void
5331 bge_start_locked(if_t ifp)
5332 {
5333         struct bge_softc *sc;
5334         struct mbuf *m_head;
5335         uint32_t prodidx;
5336         int count;
5337
5338         sc = if_getsoftc(ifp);
5339         BGE_LOCK_ASSERT(sc);
5340
5341         if (!sc->bge_link ||
5342             (if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
5343             IFF_DRV_RUNNING)
5344                 return;
5345
5346         prodidx = sc->bge_tx_prodidx;
5347
5348         for (count = 0; !if_sendq_empty(ifp);) {
5349                 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
5350                         if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5351                         break;
5352                 }
5353                 m_head = if_dequeue(ifp);
5354                 if (m_head == NULL)
5355                         break;
5356
5357                 /*
5358                  * Pack the data into the transmit ring. If we
5359                  * don't have room, set the OACTIVE flag and wait
5360                  * for the NIC to drain the ring.
5361                  */
5362                 if (bge_encap(sc, &m_head, &prodidx)) {
5363                         if (m_head == NULL)
5364                                 break;
5365                         if_sendq_prepend(ifp, m_head);
5366                         if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5367                         break;
5368                 }
5369                 ++count;
5370
5371                 /*
5372                  * If there's a BPF listener, bounce a copy of this frame
5373                  * to him.
5374                  */
5375                 if_bpfmtap(ifp, m_head);
5376         }
5377
5378         if (count > 0)
5379                 bge_start_tx(sc, prodidx);
5380 }
5381
5382 static void
5383 bge_start_tx(struct bge_softc *sc, uint32_t prodidx)
5384 {
5385
5386         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
5387             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
5388         /* Transmit. */
5389         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5390         /* 5700 b2 errata */
5391         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
5392                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5393
5394         sc->bge_tx_prodidx = prodidx;
5395
5396         /* Set a timeout in case the chip goes out to lunch. */
5397         sc->bge_timer = BGE_TX_TIMEOUT;
5398 }
5399
5400 /*
5401  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5402  * to the mbuf data regions directly in the transmit descriptors.
5403  */
5404 static void
5405 bge_start(if_t ifp)
5406 {
5407         struct bge_softc *sc;
5408
5409         sc = if_getsoftc(ifp);
5410         BGE_LOCK(sc);
5411         bge_start_locked(ifp);
5412         BGE_UNLOCK(sc);
5413 }
5414
5415 static void
5416 bge_init_locked(struct bge_softc *sc)
5417 {
5418         if_t ifp;
5419         uint16_t *m;
5420         uint32_t mode;
5421
5422         BGE_LOCK_ASSERT(sc);
5423
5424         ifp = sc->bge_ifp;
5425
5426         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
5427                 return;
5428
5429         /* Cancel pending I/O and flush buffers. */
5430         bge_stop(sc);
5431
5432         bge_stop_fw(sc);
5433         bge_sig_pre_reset(sc, BGE_RESET_START);
5434         bge_reset(sc);
5435         bge_sig_legacy(sc, BGE_RESET_START);
5436         bge_sig_post_reset(sc, BGE_RESET_START);
5437
5438         bge_chipinit(sc);
5439
5440         /*
5441          * Init the various state machines, ring
5442          * control blocks and firmware.
5443          */
5444         if (bge_blockinit(sc)) {
5445                 device_printf(sc->bge_dev, "initialization failure\n");
5446                 return;
5447         }
5448
5449         ifp = sc->bge_ifp;
5450
5451         /* Specify MTU. */
5452         CSR_WRITE_4(sc, BGE_RX_MTU, if_getmtu(ifp) +
5453             ETHER_HDR_LEN + ETHER_CRC_LEN +
5454             (if_getcapenable(ifp) & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
5455
5456         /* Load our MAC address. */
5457         m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
5458         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
5459         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
5460
5461         /* Program promiscuous mode. */
5462         bge_setpromisc(sc);
5463
5464         /* Program multicast filter. */
5465         bge_setmulti(sc);
5466
5467         /* Program VLAN tag stripping. */
5468         bge_setvlan(sc);
5469
5470         /* Override UDP checksum offloading. */
5471         if (sc->bge_forced_udpcsum == 0)
5472                 sc->bge_csum_features &= ~CSUM_UDP;
5473         else
5474                 sc->bge_csum_features |= CSUM_UDP;
5475         if (if_getcapabilities(ifp) & IFCAP_TXCSUM &&
5476             if_getcapenable(ifp) & IFCAP_TXCSUM) {
5477                 if_sethwassistbits(ifp, 0, (BGE_CSUM_FEATURES | CSUM_UDP));
5478                 if_sethwassistbits(ifp, sc->bge_csum_features, 0);
5479         }
5480
5481         /* Init RX ring. */
5482         if (bge_init_rx_ring_std(sc) != 0) {
5483                 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
5484                 bge_stop(sc);
5485                 return;
5486         }
5487
5488         /*
5489          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
5490          * memory to insure that the chip has in fact read the first
5491          * entry of the ring.
5492          */
5493         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
5494                 uint32_t                v, i;
5495                 for (i = 0; i < 10; i++) {
5496                         DELAY(20);
5497                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
5498                         if (v == (MCLBYTES - ETHER_ALIGN))
5499                                 break;
5500                 }
5501                 if (i == 10)
5502                         device_printf (sc->bge_dev,
5503                             "5705 A0 chip failed to load RX ring\n");
5504         }
5505
5506         /* Init jumbo RX ring. */
5507         if (BGE_IS_JUMBO_CAPABLE(sc) &&
5508             if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
5509             ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) {
5510                 if (bge_init_rx_ring_jumbo(sc) != 0) {
5511                         device_printf(sc->bge_dev,
5512                             "no memory for jumbo Rx buffers.\n");
5513                         bge_stop(sc);
5514                         return;
5515                 }
5516         }
5517
5518         /* Init our RX return ring index. */
5519         sc->bge_rx_saved_considx = 0;
5520
5521         /* Init our RX/TX stat counters. */
5522         sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
5523
5524         /* Init TX ring. */
5525         bge_init_tx_ring(sc);
5526
5527         /* Enable TX MAC state machine lockup fix. */
5528         mode = CSR_READ_4(sc, BGE_TX_MODE);
5529         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
5530                 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
5531         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
5532             sc->bge_asicrev == BGE_ASICREV_BCM5762) {
5533                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5534                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
5535                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5536         }
5537         /* Turn on transmitter. */
5538         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
5539         DELAY(100);
5540
5541         /* Turn on receiver. */
5542         mode = CSR_READ_4(sc, BGE_RX_MODE);
5543         if (BGE_IS_5755_PLUS(sc))
5544                 mode |= BGE_RXMODE_IPV6_ENABLE;
5545         if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
5546                 mode |= BGE_RXMODE_IPV4_FRAG_FIX;
5547         CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
5548         DELAY(10);
5549
5550         /*
5551          * Set the number of good frames to receive after RX MBUF
5552          * Low Watermark has been reached. After the RX MAC receives
5553          * this number of frames, it will drop subsequent incoming
5554          * frames until the MBUF High Watermark is reached.
5555          */
5556         if (BGE_IS_57765_PLUS(sc))
5557                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
5558         else
5559                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
5560
5561         /* Clear MAC statistics. */
5562         if (BGE_IS_5705_PLUS(sc))
5563                 bge_stats_clear_regs(sc);
5564
5565         /* Tell firmware we're alive. */
5566         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5567
5568 #ifdef DEVICE_POLLING
5569         /* Disable interrupts if we are polling. */
5570         if (if_getcapenable(ifp) & IFCAP_POLLING) {
5571                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5572                     BGE_PCIMISCCTL_MASK_PCI_INTR);
5573                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5574         } else
5575 #endif
5576
5577         /* Enable host interrupts. */
5578         {
5579         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
5580         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5581         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5582         }
5583
5584         if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
5585         if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
5586
5587         bge_ifmedia_upd_locked(ifp);
5588
5589         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
5590 }
5591
5592 static void
5593 bge_init(void *xsc)
5594 {
5595         struct bge_softc *sc = xsc;
5596
5597         BGE_LOCK(sc);
5598         bge_init_locked(sc);
5599         BGE_UNLOCK(sc);
5600 }
5601
5602 /*
5603  * Set media options.
5604  */
5605 static int
5606 bge_ifmedia_upd(if_t ifp)
5607 {
5608         struct bge_softc *sc = if_getsoftc(ifp);
5609         int res;
5610
5611         BGE_LOCK(sc);
5612         res = bge_ifmedia_upd_locked(ifp);
5613         BGE_UNLOCK(sc);
5614
5615         return (res);
5616 }
5617
5618 static int
5619 bge_ifmedia_upd_locked(if_t ifp)
5620 {
5621         struct bge_softc *sc = if_getsoftc(ifp);
5622         struct mii_data *mii;
5623         struct mii_softc *miisc;
5624         struct ifmedia *ifm;
5625
5626         BGE_LOCK_ASSERT(sc);
5627
5628         ifm = &sc->bge_ifmedia;
5629
5630         /* If this is a 1000baseX NIC, enable the TBI port. */
5631         if (sc->bge_flags & BGE_FLAG_TBI) {
5632                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
5633                         return (EINVAL);
5634                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
5635                 case IFM_AUTO:
5636                         /*
5637                          * The BCM5704 ASIC appears to have a special
5638                          * mechanism for programming the autoneg
5639                          * advertisement registers in TBI mode.
5640                          */
5641                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
5642                                 uint32_t sgdig;
5643                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5644                                 if (sgdig & BGE_SGDIGSTS_DONE) {
5645                                         CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5646                                         sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5647                                         sgdig |= BGE_SGDIGCFG_AUTO |
5648                                             BGE_SGDIGCFG_PAUSE_CAP |
5649                                             BGE_SGDIGCFG_ASYM_PAUSE;
5650                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG,
5651                                             sgdig | BGE_SGDIGCFG_SEND);
5652                                         DELAY(5);
5653                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
5654                                 }
5655                         }
5656                         break;
5657                 case IFM_1000_SX:
5658                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
5659                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
5660                                     BGE_MACMODE_HALF_DUPLEX);
5661                         } else {
5662                                 BGE_SETBIT(sc, BGE_MAC_MODE,
5663                                     BGE_MACMODE_HALF_DUPLEX);
5664                         }
5665                         DELAY(40);
5666                         break;
5667                 default:
5668                         return (EINVAL);
5669                 }
5670                 return (0);
5671         }
5672
5673         sc->bge_link_evt++;
5674         mii = device_get_softc(sc->bge_miibus);
5675         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
5676                 PHY_RESET(miisc);
5677         mii_mediachg(mii);
5678
5679         /*
5680          * Force an interrupt so that we will call bge_link_upd
5681          * if needed and clear any pending link state attention.
5682          * Without this we are not getting any further interrupts
5683          * for link state changes and thus will not UP the link and
5684          * not be able to send in bge_start_locked. The only
5685          * way to get things working was to receive a packet and
5686          * get an RX intr.
5687          * bge_tick should help for fiber cards and we might not
5688          * need to do this here if BGE_FLAG_TBI is set but as
5689          * we poll for fiber anyway it should not harm.
5690          */
5691         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
5692             sc->bge_flags & BGE_FLAG_5788)
5693                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
5694         else
5695                 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
5696
5697         return (0);
5698 }
5699
5700 /*
5701  * Report current media status.
5702  */
5703 static void
5704 bge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
5705 {
5706         struct bge_softc *sc = if_getsoftc(ifp);
5707         struct mii_data *mii;
5708
5709         BGE_LOCK(sc);
5710
5711         if ((if_getflags(ifp) & IFF_UP) == 0) {
5712                 BGE_UNLOCK(sc);
5713                 return;
5714         }
5715         if (sc->bge_flags & BGE_FLAG_TBI) {
5716                 ifmr->ifm_status = IFM_AVALID;
5717                 ifmr->ifm_active = IFM_ETHER;
5718                 if (CSR_READ_4(sc, BGE_MAC_STS) &
5719                     BGE_MACSTAT_TBI_PCS_SYNCHED)
5720                         ifmr->ifm_status |= IFM_ACTIVE;
5721                 else {
5722                         ifmr->ifm_active |= IFM_NONE;
5723                         BGE_UNLOCK(sc);
5724                         return;
5725                 }
5726                 ifmr->ifm_active |= IFM_1000_SX;
5727                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5728                         ifmr->ifm_active |= IFM_HDX;
5729                 else
5730                         ifmr->ifm_active |= IFM_FDX;
5731                 BGE_UNLOCK(sc);
5732                 return;
5733         }
5734
5735         mii = device_get_softc(sc->bge_miibus);
5736         mii_pollstat(mii);
5737         ifmr->ifm_active = mii->mii_media_active;
5738         ifmr->ifm_status = mii->mii_media_status;
5739
5740         BGE_UNLOCK(sc);
5741 }
5742
5743 static int
5744 bge_ioctl(if_t ifp, u_long command, caddr_t data)
5745 {
5746         struct bge_softc *sc = if_getsoftc(ifp);
5747         struct ifreq *ifr = (struct ifreq *) data;
5748         struct mii_data *mii;
5749         int flags, mask, error = 0;
5750
5751         switch (command) {
5752         case SIOCSIFMTU:
5753                 if (BGE_IS_JUMBO_CAPABLE(sc) ||
5754                     (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
5755                         if (ifr->ifr_mtu < ETHERMIN ||
5756                             ifr->ifr_mtu > BGE_JUMBO_MTU) {
5757                                 error = EINVAL;
5758                                 break;
5759                         }
5760                 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) {
5761                         error = EINVAL;
5762                         break;
5763                 }
5764                 BGE_LOCK(sc);
5765                 if (if_getmtu(ifp) != ifr->ifr_mtu) {
5766                         if_setmtu(ifp, ifr->ifr_mtu);
5767                         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5768                                 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5769                                 bge_init_locked(sc);
5770                         }
5771                 }
5772                 BGE_UNLOCK(sc);
5773                 break;
5774         case SIOCSIFFLAGS:
5775                 BGE_LOCK(sc);
5776                 if (if_getflags(ifp) & IFF_UP) {
5777                         /*
5778                          * If only the state of the PROMISC flag changed,
5779                          * then just use the 'set promisc mode' command
5780                          * instead of reinitializing the entire NIC. Doing
5781                          * a full re-init means reloading the firmware and
5782                          * waiting for it to start up, which may take a
5783                          * second or two.  Similarly for ALLMULTI.
5784                          */
5785                         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5786                                 flags = if_getflags(ifp) ^ sc->bge_if_flags;
5787                                 if (flags & IFF_PROMISC)
5788                                         bge_setpromisc(sc);
5789                                 if (flags & IFF_ALLMULTI)
5790                                         bge_setmulti(sc);
5791                         } else
5792                                 bge_init_locked(sc);
5793                 } else {
5794                         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5795                                 bge_stop(sc);
5796                         }
5797                 }
5798                 sc->bge_if_flags = if_getflags(ifp);
5799                 BGE_UNLOCK(sc);
5800                 error = 0;
5801                 break;
5802         case SIOCADDMULTI:
5803         case SIOCDELMULTI:
5804                 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5805                         BGE_LOCK(sc);
5806                         bge_setmulti(sc);
5807                         BGE_UNLOCK(sc);
5808                         error = 0;
5809                 }
5810                 break;
5811         case SIOCSIFMEDIA:
5812         case SIOCGIFMEDIA:
5813                 if (sc->bge_flags & BGE_FLAG_TBI) {
5814                         error = ifmedia_ioctl(ifp, ifr,
5815                             &sc->bge_ifmedia, command);
5816                 } else {
5817                         mii = device_get_softc(sc->bge_miibus);
5818                         error = ifmedia_ioctl(ifp, ifr,
5819                             &mii->mii_media, command);
5820                 }
5821                 break;
5822         case SIOCSIFCAP:
5823                 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
5824 #ifdef DEVICE_POLLING
5825                 if (mask & IFCAP_POLLING) {
5826                         if (ifr->ifr_reqcap & IFCAP_POLLING) {
5827                                 error = ether_poll_register(bge_poll, ifp);
5828                                 if (error)
5829                                         return (error);
5830                                 BGE_LOCK(sc);
5831                                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5832                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
5833                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5834                                 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
5835                                 BGE_UNLOCK(sc);
5836                         } else {
5837                                 error = ether_poll_deregister(ifp);
5838                                 /* Enable interrupt even in error case */
5839                                 BGE_LOCK(sc);
5840                                 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
5841                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
5842                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5843                                 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
5844                                 BGE_UNLOCK(sc);
5845                         }
5846                 }
5847 #endif
5848                 if ((mask & IFCAP_TXCSUM) != 0 &&
5849                     (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
5850                         if_togglecapenable(ifp, IFCAP_TXCSUM);
5851                         if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
5852                                 if_sethwassistbits(ifp,
5853                                     sc->bge_csum_features, 0);
5854                         else
5855                                 if_sethwassistbits(ifp, 0,
5856                                     sc->bge_csum_features);
5857                 }
5858
5859                 if ((mask & IFCAP_RXCSUM) != 0 &&
5860                     (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0)
5861                         if_togglecapenable(ifp, IFCAP_RXCSUM);
5862
5863                 if ((mask & IFCAP_TSO4) != 0 &&
5864                     (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
5865                         if_togglecapenable(ifp, IFCAP_TSO4);
5866                         if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
5867                                 if_sethwassistbits(ifp, CSUM_TSO, 0);
5868                         else
5869                                 if_sethwassistbits(ifp, 0, CSUM_TSO);
5870                 }
5871
5872                 if (mask & IFCAP_VLAN_MTU) {
5873                         if_togglecapenable(ifp, IFCAP_VLAN_MTU);
5874                         if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5875                         bge_init(sc);
5876                 }
5877
5878                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
5879                     (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
5880                         if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
5881                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
5882                     (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
5883                         if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
5884                         if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
5885                                 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO);
5886                         BGE_LOCK(sc);
5887                         bge_setvlan(sc);
5888                         BGE_UNLOCK(sc);
5889                 }
5890 #ifdef VLAN_CAPABILITIES
5891                 if_vlancap(ifp);
5892 #endif
5893                 break;
5894         default:
5895                 error = ether_ioctl(ifp, command, data);
5896                 break;
5897         }
5898
5899         return (error);
5900 }
5901
5902 static void
5903 bge_watchdog(struct bge_softc *sc)
5904 {
5905         if_t ifp;
5906         uint32_t status;
5907
5908         BGE_LOCK_ASSERT(sc);
5909
5910         if (sc->bge_timer == 0 || --sc->bge_timer)
5911                 return;
5912
5913         /* If pause frames are active then don't reset the hardware. */
5914         if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) {
5915                 status = CSR_READ_4(sc, BGE_RX_STS);
5916                 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) {
5917                         /*
5918                          * If link partner has us in XOFF state then wait for
5919                          * the condition to clear.
5920                          */
5921                         CSR_WRITE_4(sc, BGE_RX_STS, status);
5922                         sc->bge_timer = BGE_TX_TIMEOUT;
5923                         return;
5924                 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 &&
5925                     (status & BGE_RXSTAT_RCVD_XON) != 0) {
5926                         /*
5927                          * If link partner has us in XOFF state then wait for
5928                          * the condition to clear.
5929                          */
5930                         CSR_WRITE_4(sc, BGE_RX_STS, status);
5931                         sc->bge_timer = BGE_TX_TIMEOUT;
5932                         return;
5933                 }
5934                 /*
5935                  * Any other condition is unexpected and the controller
5936                  * should be reset.
5937                  */
5938         }
5939
5940         ifp = sc->bge_ifp;
5941
5942         if_printf(ifp, "watchdog timeout -- resetting\n");
5943
5944         if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5945         bge_init_locked(sc);
5946
5947         if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
5948 }
5949
5950 static void
5951 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
5952 {
5953         int i;
5954
5955         BGE_CLRBIT(sc, reg, bit);
5956
5957         for (i = 0; i < BGE_TIMEOUT; i++) {
5958                 if ((CSR_READ_4(sc, reg) & bit) == 0)
5959                         return;
5960                 DELAY(100);
5961         }
5962 }
5963
5964 /*
5965  * Stop the adapter and free any mbufs allocated to the
5966  * RX and TX lists.
5967  */
5968 static void
5969 bge_stop(struct bge_softc *sc)
5970 {
5971         if_t ifp;
5972
5973         BGE_LOCK_ASSERT(sc);
5974
5975         ifp = sc->bge_ifp;
5976
5977         callout_stop(&sc->bge_stat_ch);
5978
5979         /* Disable host interrupts. */
5980         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5981         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5982
5983         /*
5984          * Tell firmware we're shutting down.
5985          */
5986         bge_stop_fw(sc);
5987         bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
5988
5989         /*
5990          * Disable all of the receiver blocks.
5991          */
5992         bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
5993         bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
5994         bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
5995         if (BGE_IS_5700_FAMILY(sc))
5996                 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
5997         bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
5998         bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
5999         bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
6000
6001         /*
6002          * Disable all of the transmit blocks.
6003          */
6004         bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
6005         bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
6006         bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
6007         bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
6008         bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
6009         if (BGE_IS_5700_FAMILY(sc))
6010                 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
6011         bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
6012
6013         /*
6014          * Shut down all of the memory managers and related
6015          * state machines.
6016          */
6017         bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
6018         bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
6019         if (BGE_IS_5700_FAMILY(sc))
6020                 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
6021
6022         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
6023         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
6024         if (!(BGE_IS_5705_PLUS(sc))) {
6025                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
6026                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
6027         }
6028         /* Update MAC statistics. */
6029         if (BGE_IS_5705_PLUS(sc))
6030                 bge_stats_update_regs(sc);
6031
6032         bge_reset(sc);
6033         bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
6034         bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
6035
6036         /*
6037          * Keep the ASF firmware running if up.
6038          */
6039         if (sc->bge_asf_mode & ASF_STACKUP)
6040                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6041         else
6042                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6043
6044         /* Free the RX lists. */
6045         bge_free_rx_ring_std(sc);
6046
6047         /* Free jumbo RX list. */
6048         if (BGE_IS_JUMBO_CAPABLE(sc))
6049                 bge_free_rx_ring_jumbo(sc);
6050
6051         /* Free TX buffers. */
6052         bge_free_tx_ring(sc);
6053
6054         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
6055
6056         /* Clear MAC's link state (PHY may still have link UP). */
6057         if (bootverbose && sc->bge_link)
6058                 if_printf(sc->bge_ifp, "link DOWN\n");
6059         sc->bge_link = 0;
6060
6061         if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
6062 }
6063
6064 /*
6065  * Stop all chip I/O so that the kernel's probe routines don't
6066  * get confused by errant DMAs when rebooting.
6067  */
6068 static int
6069 bge_shutdown(device_t dev)
6070 {
6071         struct bge_softc *sc;
6072
6073         sc = device_get_softc(dev);
6074         BGE_LOCK(sc);
6075         bge_stop(sc);
6076         BGE_UNLOCK(sc);
6077
6078         return (0);
6079 }
6080
6081 static int
6082 bge_suspend(device_t dev)
6083 {
6084         struct bge_softc *sc;
6085
6086         sc = device_get_softc(dev);
6087         BGE_LOCK(sc);
6088         bge_stop(sc);
6089         BGE_UNLOCK(sc);
6090
6091         return (0);
6092 }
6093
6094 static int
6095 bge_resume(device_t dev)
6096 {
6097         struct bge_softc *sc;
6098         if_t ifp;
6099
6100         sc = device_get_softc(dev);
6101         BGE_LOCK(sc);
6102         ifp = sc->bge_ifp;
6103         if (if_getflags(ifp) & IFF_UP) {
6104                 bge_init_locked(sc);
6105                 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
6106                         bge_start_locked(ifp);
6107         }
6108         BGE_UNLOCK(sc);
6109
6110         return (0);
6111 }
6112
6113 static void
6114 bge_link_upd(struct bge_softc *sc)
6115 {
6116         struct mii_data *mii;
6117         uint32_t link, status;
6118
6119         BGE_LOCK_ASSERT(sc);
6120
6121         /* Clear 'pending link event' flag. */
6122         sc->bge_link_evt = 0;
6123
6124         /*
6125          * Process link state changes.
6126          * Grrr. The link status word in the status block does
6127          * not work correctly on the BCM5700 rev AX and BX chips,
6128          * according to all available information. Hence, we have
6129          * to enable MII interrupts in order to properly obtain
6130          * async link changes. Unfortunately, this also means that
6131          * we have to read the MAC status register to detect link
6132          * changes, thereby adding an additional register access to
6133          * the interrupt handler.
6134          *
6135          * XXX: perhaps link state detection procedure used for
6136          * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
6137          */
6138
6139         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6140             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
6141                 status = CSR_READ_4(sc, BGE_MAC_STS);
6142                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
6143                         mii = device_get_softc(sc->bge_miibus);
6144                         mii_pollstat(mii);
6145                         if (!sc->bge_link &&
6146                             mii->mii_media_status & IFM_ACTIVE &&
6147                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6148                                 sc->bge_link++;
6149                                 if (bootverbose)
6150                                         if_printf(sc->bge_ifp, "link UP\n");
6151                         } else if (sc->bge_link &&
6152                             (!(mii->mii_media_status & IFM_ACTIVE) ||
6153                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6154                                 sc->bge_link = 0;
6155                                 if (bootverbose)
6156                                         if_printf(sc->bge_ifp, "link DOWN\n");
6157                         }
6158
6159                         /* Clear the interrupt. */
6160                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
6161                             BGE_EVTENB_MI_INTERRUPT);
6162                         bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
6163                             BRGPHY_MII_ISR);
6164                         bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
6165                             BRGPHY_MII_IMR, BRGPHY_INTRS);
6166                 }
6167                 return;
6168         }
6169
6170         if (sc->bge_flags & BGE_FLAG_TBI) {
6171                 status = CSR_READ_4(sc, BGE_MAC_STS);
6172                 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
6173                         if (!sc->bge_link) {
6174                                 sc->bge_link++;
6175                                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
6176                                         BGE_CLRBIT(sc, BGE_MAC_MODE,
6177                                             BGE_MACMODE_TBI_SEND_CFGS);
6178                                         DELAY(40);
6179                                 }
6180                                 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
6181                                 if (bootverbose)
6182                                         if_printf(sc->bge_ifp, "link UP\n");
6183                                 if_link_state_change(sc->bge_ifp,
6184                                     LINK_STATE_UP);
6185                         }
6186                 } else if (sc->bge_link) {
6187                         sc->bge_link = 0;
6188                         if (bootverbose)
6189                                 if_printf(sc->bge_ifp, "link DOWN\n");
6190                         if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
6191                 }
6192         } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
6193                 /*
6194                  * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
6195                  * in status word always set. Workaround this bug by reading
6196                  * PHY link status directly.
6197                  */
6198                 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
6199
6200                 if (link != sc->bge_link ||
6201                     sc->bge_asicrev == BGE_ASICREV_BCM5700) {
6202                         mii = device_get_softc(sc->bge_miibus);
6203                         mii_pollstat(mii);
6204                         if (!sc->bge_link &&
6205                             mii->mii_media_status & IFM_ACTIVE &&
6206                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6207                                 sc->bge_link++;
6208                                 if (bootverbose)
6209                                         if_printf(sc->bge_ifp, "link UP\n");
6210                         } else if (sc->bge_link &&
6211                             (!(mii->mii_media_status & IFM_ACTIVE) ||
6212                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6213                                 sc->bge_link = 0;
6214                                 if (bootverbose)
6215                                         if_printf(sc->bge_ifp, "link DOWN\n");
6216                         }
6217                 }
6218         } else {
6219                 /*
6220                  * For controllers that call mii_tick, we have to poll
6221                  * link status.
6222                  */
6223                 mii = device_get_softc(sc->bge_miibus);
6224                 mii_pollstat(mii);
6225                 bge_miibus_statchg(sc->bge_dev);
6226         }
6227
6228         /* Disable MAC attention when link is up. */
6229         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
6230             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
6231             BGE_MACSTAT_LINK_CHANGED);
6232 }
6233
6234 static void
6235 bge_add_sysctls(struct bge_softc *sc)
6236 {
6237         struct sysctl_ctx_list *ctx;
6238         struct sysctl_oid_list *children;
6239         int unit;
6240
6241         ctx = device_get_sysctl_ctx(sc->bge_dev);
6242         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
6243
6244 #ifdef BGE_REGISTER_DEBUG
6245         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
6246             CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6247             bge_sysctl_debug_info, "I", "Debug Information");
6248
6249         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
6250             CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6251             bge_sysctl_reg_read, "I", "MAC Register Read");
6252
6253         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read",
6254             CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6255             bge_sysctl_ape_read, "I", "APE Register Read");
6256
6257         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
6258             CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
6259             bge_sysctl_mem_read, "I", "Memory Read");
6260
6261 #endif
6262
6263         unit = device_get_unit(sc->bge_dev);
6264         /*
6265          * A common design characteristic for many Broadcom client controllers
6266          * is that they only support a single outstanding DMA read operation
6267          * on the PCIe bus. This means that it will take twice as long to fetch
6268          * a TX frame that is split into header and payload buffers as it does
6269          * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
6270          * these controllers, coalescing buffers to reduce the number of memory
6271          * reads is effective way to get maximum performance(about 940Mbps).
6272          * Without collapsing TX buffers the maximum TCP bulk transfer
6273          * performance is about 850Mbps. However forcing coalescing mbufs
6274          * consumes a lot of CPU cycles, so leave it off by default.
6275          */
6276         sc->bge_forced_collapse = 0;
6277         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
6278             CTLFLAG_RWTUN, &sc->bge_forced_collapse, 0,
6279             "Number of fragmented TX buffers of a frame allowed before "
6280             "forced collapsing");
6281
6282         sc->bge_msi = 1;
6283         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi",
6284             CTLFLAG_RDTUN, &sc->bge_msi, 0, "Enable MSI");
6285
6286         /*
6287          * It seems all Broadcom controllers have a bug that can generate UDP
6288          * datagrams with checksum value 0 when TX UDP checksum offloading is
6289          * enabled.  Generating UDP checksum value 0 is RFC 768 violation.
6290          * Even though the probability of generating such UDP datagrams is
6291          * low, I don't want to see FreeBSD boxes to inject such datagrams
6292          * into network so disable UDP checksum offloading by default.  Users
6293          * still override this behavior by setting a sysctl variable,
6294          * dev.bge.0.forced_udpcsum.
6295          */
6296         sc->bge_forced_udpcsum = 0;
6297         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum",
6298             CTLFLAG_RWTUN, &sc->bge_forced_udpcsum, 0,
6299             "Enable UDP checksum offloading even if controller can "
6300             "generate UDP checksum value 0");
6301
6302         if (BGE_IS_5705_PLUS(sc))
6303                 bge_add_sysctl_stats_regs(sc, ctx, children);
6304         else
6305                 bge_add_sysctl_stats(sc, ctx, children);
6306 }
6307
6308 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
6309     SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, \
6310         CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, \
6311         offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", desc)
6312
6313 static void
6314 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6315     struct sysctl_oid_list *parent)
6316 {
6317         struct sysctl_oid *tree;
6318         struct sysctl_oid_list *children, *schildren;
6319
6320         tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats",
6321             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE Statistics");
6322         schildren = children = SYSCTL_CHILDREN(tree);
6323         BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
6324             children, COSFramesDroppedDueToFilters,
6325             "FramesDroppedDueToFilters");
6326         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
6327             children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
6328         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
6329             children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
6330         BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
6331             children, nicNoMoreRxBDs, "NoMoreRxBDs");
6332         BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
6333             children, ifInDiscards, "InputDiscards");
6334         BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
6335             children, ifInErrors, "InputErrors");
6336         BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
6337             children, nicRecvThresholdHit, "RecvThresholdHit");
6338         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
6339             children, nicDmaReadQueueFull, "DmaReadQueueFull");
6340         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
6341             children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
6342         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
6343             children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
6344         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
6345             children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
6346         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
6347             children, nicRingStatusUpdate, "RingStatusUpdate");
6348         BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
6349             children, nicInterrupts, "Interrupts");
6350         BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
6351             children, nicAvoidedInterrupts, "AvoidedInterrupts");
6352         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
6353             children, nicSendThresholdHit, "SendThresholdHit");
6354
6355         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx",
6356             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE RX Statistics");
6357         children = SYSCTL_CHILDREN(tree);
6358         BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
6359             children, rxstats.ifHCInOctets, "ifHCInOctets");
6360         BGE_SYSCTL_STAT(sc, ctx, "Fragments",
6361             children, rxstats.etherStatsFragments, "Fragments");
6362         BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
6363             children, rxstats.ifHCInUcastPkts, "UnicastPkts");
6364         BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
6365             children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
6366         BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
6367             children, rxstats.dot3StatsFCSErrors, "FCSErrors");
6368         BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
6369             children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
6370         BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
6371             children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
6372         BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
6373             children, rxstats.xoffPauseFramesReceived,
6374             "xoffPauseFramesReceived");
6375         BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
6376             children, rxstats.macControlFramesReceived,
6377             "ControlFramesReceived");
6378         BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
6379             children, rxstats.xoffStateEntered, "xoffStateEntered");
6380         BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
6381             children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
6382         BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
6383             children, rxstats.etherStatsJabbers, "Jabbers");
6384         BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
6385             children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
6386         BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
6387             children, rxstats.inRangeLengthError, "inRangeLengthError");
6388         BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
6389             children, rxstats.outRangeLengthError, "outRangeLengthError");
6390
6391         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx",
6392             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE TX Statistics");
6393         children = SYSCTL_CHILDREN(tree);
6394         BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
6395             children, txstats.ifHCOutOctets, "ifHCOutOctets");
6396         BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
6397             children, txstats.etherStatsCollisions, "Collisions");
6398         BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
6399             children, txstats.outXonSent, "XonSent");
6400         BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
6401             children, txstats.outXoffSent, "XoffSent");
6402         BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
6403             children, txstats.flowControlDone, "flowControlDone");
6404         BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
6405             children, txstats.dot3StatsInternalMacTransmitErrors,
6406             "InternalMacTransmitErrors");
6407         BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
6408             children, txstats.dot3StatsSingleCollisionFrames,
6409             "SingleCollisionFrames");
6410         BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
6411             children, txstats.dot3StatsMultipleCollisionFrames,
6412             "MultipleCollisionFrames");
6413         BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
6414             children, txstats.dot3StatsDeferredTransmissions,
6415             "DeferredTransmissions");
6416         BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
6417             children, txstats.dot3StatsExcessiveCollisions,
6418             "ExcessiveCollisions");
6419         BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
6420             children, txstats.dot3StatsLateCollisions,
6421             "LateCollisions");
6422         BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
6423             children, txstats.ifHCOutUcastPkts, "UnicastPkts");
6424         BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
6425             children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
6426         BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
6427             children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
6428         BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
6429             children, txstats.dot3StatsCarrierSenseErrors,
6430             "CarrierSenseErrors");
6431         BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
6432             children, txstats.ifOutDiscards, "Discards");
6433         BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
6434             children, txstats.ifOutErrors, "Errors");
6435 }
6436
6437 #undef BGE_SYSCTL_STAT
6438
6439 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d)    \
6440             SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
6441
6442 static void
6443 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6444     struct sysctl_oid_list *parent)
6445 {
6446         struct sysctl_oid *tree;
6447         struct sysctl_oid_list *child, *schild;
6448         struct bge_mac_stats *stats;
6449
6450         stats = &sc->bge_mac_stats;
6451         tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats",
6452             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE Statistics");
6453         schild = child = SYSCTL_CHILDREN(tree);
6454         BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters",
6455             &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters");
6456         BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull",
6457             &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full");
6458         BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull",
6459             &stats->DmaWriteHighPriQueueFull,
6460             "NIC DMA Write High Priority Queue Full");
6461         BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs",
6462             &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors");
6463         BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards",
6464             &stats->InputDiscards, "Discarded Input Frames");
6465         BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors",
6466             &stats->InputErrors, "Input Errors");
6467         BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit",
6468             &stats->RecvThresholdHit, "NIC Recv Threshold Hit");
6469
6470         tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx",
6471             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE RX Statistics");
6472         child = SYSCTL_CHILDREN(tree);
6473         BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets",
6474             &stats->ifHCInOctets, "Inbound Octets");
6475         BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments",
6476             &stats->etherStatsFragments, "Fragments");
6477         BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6478             &stats->ifHCInUcastPkts, "Inbound Unicast Packets");
6479         BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6480             &stats->ifHCInMulticastPkts, "Inbound Multicast Packets");
6481         BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6482             &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets");
6483         BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors",
6484             &stats->dot3StatsFCSErrors, "FCS Errors");
6485         BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors",
6486             &stats->dot3StatsAlignmentErrors, "Alignment Errors");
6487         BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived",
6488             &stats->xonPauseFramesReceived, "XON Pause Frames Received");
6489         BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived",
6490             &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received");
6491         BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived",
6492             &stats->macControlFramesReceived, "MAC Control Frames Received");
6493         BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered",
6494             &stats->xoffStateEntered, "XOFF State Entered");
6495         BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong",
6496             &stats->dot3StatsFramesTooLong, "Frames Too Long");
6497         BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers",
6498             &stats->etherStatsJabbers, "Jabbers");
6499         BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts",
6500             &stats->etherStatsUndersizePkts, "Undersized Packets");
6501
6502         tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx",
6503             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "BGE TX Statistics");
6504         child = SYSCTL_CHILDREN(tree);
6505         BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets",
6506             &stats->ifHCOutOctets, "Outbound Octets");
6507         BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions",
6508             &stats->etherStatsCollisions, "TX Collisions");
6509         BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent",
6510             &stats->outXonSent, "XON Sent");
6511         BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent",
6512             &stats->outXoffSent, "XOFF Sent");
6513         BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors",
6514             &stats->dot3StatsInternalMacTransmitErrors,
6515             "Internal MAC TX Errors");
6516         BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames",
6517             &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames");
6518         BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames",
6519             &stats->dot3StatsMultipleCollisionFrames,
6520             "Multiple Collision Frames");
6521         BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions",
6522             &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions");
6523         BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions",
6524             &stats->dot3StatsExcessiveCollisions, "Excessive Collisions");
6525         BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions",
6526             &stats->dot3StatsLateCollisions, "Late Collisions");
6527         BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6528             &stats->ifHCOutUcastPkts, "Outbound Unicast Packets");
6529         BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6530             &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets");
6531         BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6532             &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets");
6533 }
6534
6535 #undef  BGE_SYSCTL_STAT_ADD64
6536
6537 static int
6538 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
6539 {
6540         struct bge_softc *sc;
6541         uint32_t result;
6542         int offset;
6543
6544         sc = (struct bge_softc *)arg1;
6545         offset = arg2;
6546         result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
6547             offsetof(bge_hostaddr, bge_addr_lo));
6548         return (sysctl_handle_int(oidp, &result, 0, req));
6549 }
6550
6551 #ifdef BGE_REGISTER_DEBUG
6552 static int
6553 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
6554 {
6555         struct bge_softc *sc;
6556         uint16_t *sbdata;
6557         int error, result, sbsz;
6558         int i, j;
6559
6560         result = -1;
6561         error = sysctl_handle_int(oidp, &result, 0, req);
6562         if (error || (req->newptr == NULL))
6563                 return (error);
6564
6565         if (result == 1) {
6566                 sc = (struct bge_softc *)arg1;
6567
6568                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6569                     sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
6570                         sbsz = BGE_STATUS_BLK_SZ;
6571                 else
6572                         sbsz = 32;
6573                 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
6574                 printf("Status Block:\n");
6575                 BGE_LOCK(sc);
6576                 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6577                     sc->bge_cdata.bge_status_map,
6578                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6579                 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) {
6580                         printf("%06x:", i);
6581                         for (j = 0; j < 8; j++)
6582                                 printf(" %04x", sbdata[i++]);
6583                         printf("\n");
6584                 }
6585
6586                 printf("Registers:\n");
6587                 for (i = 0x800; i < 0xA00; ) {
6588                         printf("%06x:", i);
6589                         for (j = 0; j < 8; j++) {
6590                                 printf(" %08x", CSR_READ_4(sc, i));
6591                                 i += 4;
6592                         }
6593                         printf("\n");
6594                 }
6595                 BGE_UNLOCK(sc);
6596
6597                 printf("Hardware Flags:\n");
6598                 if (BGE_IS_5717_PLUS(sc))
6599                         printf(" - 5717 Plus\n");
6600                 if (BGE_IS_5755_PLUS(sc))
6601                         printf(" - 5755 Plus\n");
6602                 if (BGE_IS_575X_PLUS(sc))
6603                         printf(" - 575X Plus\n");
6604                 if (BGE_IS_5705_PLUS(sc))
6605                         printf(" - 5705 Plus\n");
6606                 if (BGE_IS_5714_FAMILY(sc))
6607                         printf(" - 5714 Family\n");
6608                 if (BGE_IS_5700_FAMILY(sc))
6609                         printf(" - 5700 Family\n");
6610                 if (sc->bge_flags & BGE_FLAG_JUMBO)
6611                         printf(" - Supports Jumbo Frames\n");
6612                 if (sc->bge_flags & BGE_FLAG_PCIX)
6613                         printf(" - PCI-X Bus\n");
6614                 if (sc->bge_flags & BGE_FLAG_PCIE)
6615                         printf(" - PCI Express Bus\n");
6616                 if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
6617                         printf(" - No 3 LEDs\n");
6618                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
6619                         printf(" - RX Alignment Bug\n");
6620         }
6621
6622         return (error);
6623 }
6624
6625 static int
6626 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6627 {
6628         struct bge_softc *sc;
6629         int error;
6630         uint16_t result;
6631         uint32_t val;
6632
6633         result = -1;
6634         error = sysctl_handle_int(oidp, &result, 0, req);
6635         if (error || (req->newptr == NULL))
6636                 return (error);
6637
6638         if (result < 0x8000) {
6639                 sc = (struct bge_softc *)arg1;
6640                 val = CSR_READ_4(sc, result);
6641                 printf("reg 0x%06X = 0x%08X\n", result, val);
6642         }
6643
6644         return (error);
6645 }
6646
6647 static int
6648 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS)
6649 {
6650         struct bge_softc *sc;
6651         int error;
6652         uint16_t result;
6653         uint32_t val;
6654
6655         result = -1;
6656         error = sysctl_handle_int(oidp, &result, 0, req);
6657         if (error || (req->newptr == NULL))
6658                 return (error);
6659
6660         if (result < 0x8000) {
6661                 sc = (struct bge_softc *)arg1;
6662                 val = APE_READ_4(sc, result);
6663                 printf("reg 0x%06X = 0x%08X\n", result, val);
6664         }
6665
6666         return (error);
6667 }
6668
6669 static int
6670 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
6671 {
6672         struct bge_softc *sc;
6673         int error;
6674         uint16_t result;
6675         uint32_t val;
6676
6677         result = -1;
6678         error = sysctl_handle_int(oidp, &result, 0, req);
6679         if (error || (req->newptr == NULL))
6680                 return (error);
6681
6682         if (result < 0x8000) {
6683                 sc = (struct bge_softc *)arg1;
6684                 val = bge_readmem_ind(sc, result);
6685                 printf("mem 0x%06X = 0x%08X\n", result, val);
6686         }
6687
6688         return (error);
6689 }
6690 #endif
6691
6692 static int
6693 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
6694 {
6695         return (1);
6696 }
6697
6698 static int
6699 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
6700 {
6701         uint32_t mac_addr;
6702
6703         mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
6704         if ((mac_addr >> 16) == 0x484b) {
6705                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
6706                 ether_addr[1] = (uint8_t)mac_addr;
6707                 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
6708                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
6709                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
6710                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
6711                 ether_addr[5] = (uint8_t)mac_addr;
6712                 return (0);
6713         }
6714         return (1);
6715 }
6716
6717 static int
6718 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
6719 {
6720         int mac_offset = BGE_EE_MAC_OFFSET;
6721
6722         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6723                 mac_offset = BGE_EE_MAC_OFFSET_5906;
6724
6725         return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
6726             ETHER_ADDR_LEN));
6727 }
6728
6729 static int
6730 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
6731 {
6732
6733         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6734                 return (1);
6735
6736         return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
6737            ETHER_ADDR_LEN));
6738 }
6739
6740 static int
6741 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
6742 {
6743         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
6744                 /* NOTE: Order is critical */
6745                 bge_get_eaddr_fw,
6746                 bge_get_eaddr_mem,
6747                 bge_get_eaddr_nvram,
6748                 bge_get_eaddr_eeprom,
6749                 NULL
6750         };
6751         const bge_eaddr_fcn_t *func;
6752
6753         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
6754                 if ((*func)(sc, eaddr) == 0)
6755                         break;
6756         }
6757         return (*func == NULL ? ENXIO : 0);
6758 }
6759
6760 static uint64_t
6761 bge_get_counter(if_t ifp, ift_counter cnt)
6762 {
6763         struct bge_softc *sc;
6764         struct bge_mac_stats *stats;
6765
6766         sc = if_getsoftc(ifp);
6767         if (!BGE_IS_5705_PLUS(sc))
6768                 return (if_get_counter_default(ifp, cnt));
6769         stats = &sc->bge_mac_stats;
6770
6771         switch (cnt) {
6772         case IFCOUNTER_IERRORS:
6773                 return (stats->NoMoreRxBDs + stats->InputDiscards +
6774                     stats->InputErrors);
6775         case IFCOUNTER_COLLISIONS:
6776                 return (stats->etherStatsCollisions);
6777         default:
6778                 return (if_get_counter_default(ifp, cnt));
6779         }
6780 }
6781
6782 #ifdef DEBUGNET
6783 static void
6784 bge_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6785 {
6786         struct bge_softc *sc;
6787
6788         sc = if_getsoftc(ifp);
6789         BGE_LOCK(sc);
6790         *nrxr = sc->bge_return_ring_cnt;
6791         *ncl = DEBUGNET_MAX_IN_FLIGHT;
6792         if ((sc->bge_flags & BGE_FLAG_JUMBO_STD) != 0 &&
6793             (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
6794             ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)))
6795                 *clsize = MJUM9BYTES;
6796         else
6797                 *clsize = MCLBYTES;
6798         BGE_UNLOCK(sc);
6799 }
6800
6801 static void
6802 bge_debugnet_event(if_t ifp __unused, enum debugnet_ev event __unused)
6803 {
6804 }
6805
6806 static int
6807 bge_debugnet_transmit(if_t ifp, struct mbuf *m)
6808 {
6809         struct bge_softc *sc;
6810         uint32_t prodidx;
6811         int error;
6812
6813         sc = if_getsoftc(ifp);
6814         if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6815             IFF_DRV_RUNNING)
6816                 return (1);
6817
6818         prodidx = sc->bge_tx_prodidx;
6819         error = bge_encap(sc, &m, &prodidx);
6820         if (error == 0)
6821                 bge_start_tx(sc, prodidx);
6822         return (error);
6823 }
6824
6825 static int
6826 bge_debugnet_poll(if_t ifp, int count)
6827 {
6828         struct bge_softc *sc;
6829         uint32_t rx_prod, tx_cons;
6830
6831         sc = if_getsoftc(ifp);
6832         if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6833             IFF_DRV_RUNNING)
6834                 return (1);
6835
6836         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6837             sc->bge_cdata.bge_status_map,
6838             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6839
6840         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
6841         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
6842
6843         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6844             sc->bge_cdata.bge_status_map,
6845             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
6846
6847         (void)bge_rxeof(sc, rx_prod, 0);
6848         bge_txeof(sc, tx_cons);
6849         return (0);
6850 }
6851 #endif /* DEBUGNET */