sys/dev/bge/if_bge.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-4-Clause
   3  *
   4  * Copyright (c) 2001 Wind River Systems
   5  * Copyright (c) 1997, 1998, 1999, 2001
   6  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed by Bill Paul.
  19  * 4. Neither the name of the author nor the names of any co-contributors
  20  *    may be used to endorse or promote products derived from this software
  21  *    without specific prior written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  27  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  33  * THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35
  36 #include <sys/cdefs.h>
  37 __FBSDID("$FreeBSD$");
  38
  39 /*
  40  * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver
  41  *
  42  * The Broadcom BCM5700 is based on technology originally developed by
  43  * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet
  44  * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
  45  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  46  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  47  * frames, highly configurable RX filtering, and 16 RX and TX queues
  48  * (which, along with RX filter rules, can be used for QOS applications).
  49  * Other features, such as TCP segmentation, may be available as part
  50  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  51  * firmware images can be stored in hardware and need not be compiled
  52  * into the driver.
  53  *
  54  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  55  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  56  *
  57  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  58  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  59  * does not support external SSRAM.
  60  *
  61  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  62  * brand name, which is functionally similar but lacks PCI-X support.
  63  *
  64  * Without external SSRAM, you can only have at most 4 TX rings,
  65  * and the use of the mini RX ring is disabled. This seems to imply
  66  * that these features are simply not available on the BCM5701. As a
  67  * result, this driver does not implement any support for the mini RX
  68  * ring.
  69  */
  70
  71 #ifdef HAVE_KERNEL_OPTION_HEADERS
  72 #include "opt_device_polling.h"
  73 #endif
  74
  75 #include <sys/param.h>
  76 #include <sys/endian.h>
  77 #include <sys/systm.h>
  78 #include <sys/sockio.h>
  79 #include <sys/mbuf.h>
  80 #include <sys/malloc.h>
  81 #include <sys/kernel.h>
  82 #include <sys/module.h>
  83 #include <sys/socket.h>
  84 #include <sys/sysctl.h>
  85 #include <sys/taskqueue.h>
  86
  87 #include <net/if.h>
  88 #include <net/if_var.h>
  89 #include <net/if_arp.h>
  90 #include <net/ethernet.h>
  91 #include <net/if_dl.h>
  92 #include <net/if_media.h>
  93
  94 #include <net/bpf.h>
  95
  96 #include <net/if_types.h>
  97 #include <net/if_vlan_var.h>
  98
  99 #include <netinet/in_systm.h>
 100 #include <netinet/in.h>
 101 #include <netinet/ip.h>
 102 #include <netinet/tcp.h>
 103
 104 #include <machine/bus.h>
 105 #include <machine/resource.h>
 106 #include <sys/bus.h>
 107 #include <sys/rman.h>
 108
 109 #include <dev/mii/mii.h>
 110 #include <dev/mii/miivar.h>
 111 #include "miidevs.h"
 112 #include <dev/mii/brgphyreg.h>
 113
 114 #ifdef __sparc64__
 115 #include <dev/ofw/ofw_bus.h>
 116 #include <dev/ofw/openfirm.h>
 117 #include <machine/ofw_machdep.h>
 118 #include <machine/ver.h>
 119 #endif
 120
 121 #include <dev/pci/pcireg.h>
 122 #include <dev/pci/pcivar.h>
 123
 124 #include <dev/bge/if_bgereg.h>
 125
 126 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP)
 127 #define ETHER_MIN_NOPAD         (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
 128
 129 MODULE_DEPEND(bge, pci, 1, 1, 1);
 130 MODULE_DEPEND(bge, ether, 1, 1, 1);
 131 MODULE_DEPEND(bge, miibus, 1, 1, 1);
 132
 133 /* "device miibus" required.  See GENERIC if you get errors here. */
 134 #include "miibus_if.h"
 135
 136 /*
 137  * Various supported device vendors/types and their names. Note: the
 138  * spec seems to indicate that the hardware still has Alteon's vendor
 139  * ID burned into it, though it will always be overriden by the vendor
 140  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 141  */
 142 static const struct bge_type {
 143         uint16_t        bge_vid;
 144         uint16_t        bge_did;
 145 } bge_devs[] = {
 146         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5700 },
 147         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5701 },
 148
 149         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1000 },
 150         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1002 },
 151         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC9100 },
 152
 153         { APPLE_VENDORID,       APPLE_DEVICE_BCM5701 },
 154
 155         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5700 },
 156         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5701 },
 157         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702 },
 158         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702_ALT },
 159         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702X },
 160         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703 },
 161         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703_ALT },
 162         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703X },
 163         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704C },
 164         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S },
 165         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S_ALT },
 166         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705 },
 167         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705F },
 168         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705K },
 169         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M },
 170         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M_ALT },
 171         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714C },
 172         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714S },
 173         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715 },
 174         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715S },
 175         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5717 },
 176         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5717C },
 177         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5718 },
 178         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5719 },
 179         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5720 },
 180         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5721 },
 181         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5722 },
 182         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5723 },
 183         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5725 },
 184         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5727 },
 185         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750 },
 186         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750M },
 187         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751 },
 188         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751F },
 189         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751M },
 190         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752 },
 191         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752M },
 192         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753 },
 193         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753F },
 194         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753M },
 195         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754 },
 196         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754M },
 197         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755 },
 198         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755M },
 199         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5756 },
 200         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761 },
 201         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761E },
 202         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761S },
 203         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761SE },
 204         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5762 },
 205         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5764 },
 206         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780 },
 207         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780S },
 208         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5781 },
 209         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5782 },
 210         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5784 },
 211         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785F },
 212         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785G },
 213         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5786 },
 214         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787 },
 215         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787F },
 216         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787M },
 217         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5788 },
 218         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5789 },
 219         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901 },
 220         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901A2 },
 221         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5903M },
 222         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906 },
 223         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906M },
 224         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57760 },
 225         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57761 },
 226         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57762 },
 227         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57764 },
 228         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57765 },
 229         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57766 },
 230         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57767 },
 231         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57780 },
 232         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57781 },
 233         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57782 },
 234         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57785 },
 235         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57786 },
 236         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57787 },
 237         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57788 },
 238         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57790 },
 239         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57791 },
 240         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57795 },
 241
 242         { SK_VENDORID,          SK_DEVICEID_ALTIMA },
 243
 244         { TC_VENDORID,          TC_DEVICEID_3C996 },
 245
 246         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE4 },
 247         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE5 },
 248         { FJTSU_VENDORID,       FJTSU_DEVICEID_PP250450 },
 249
 250         { 0, 0 }
 251 };
 252
 253 static const struct bge_vendor {
 254         uint16_t        v_id;
 255         const char      *v_name;
 256 } bge_vendors[] = {
 257         { ALTEON_VENDORID,      "Alteon" },
 258         { ALTIMA_VENDORID,      "Altima" },
 259         { APPLE_VENDORID,       "Apple" },
 260         { BCOM_VENDORID,        "Broadcom" },
 261         { SK_VENDORID,          "SysKonnect" },
 262         { TC_VENDORID,          "3Com" },
 263         { FJTSU_VENDORID,       "Fujitsu" },
 264
 265         { 0, NULL }
 266 };
 267
 268 static const struct bge_revision {
 269         uint32_t        br_chipid;
 270         const char      *br_name;
 271 } bge_revisions[] = {
 272         { BGE_CHIPID_BCM5700_A0,        "BCM5700 A0" },
 273         { BGE_CHIPID_BCM5700_A1,        "BCM5700 A1" },
 274         { BGE_CHIPID_BCM5700_B0,        "BCM5700 B0" },
 275         { BGE_CHIPID_BCM5700_B1,        "BCM5700 B1" },
 276         { BGE_CHIPID_BCM5700_B2,        "BCM5700 B2" },
 277         { BGE_CHIPID_BCM5700_B3,        "BCM5700 B3" },
 278         { BGE_CHIPID_BCM5700_ALTIMA,    "BCM5700 Altima" },
 279         { BGE_CHIPID_BCM5700_C0,        "BCM5700 C0" },
 280         { BGE_CHIPID_BCM5701_A0,        "BCM5701 A0" },
 281         { BGE_CHIPID_BCM5701_B0,        "BCM5701 B0" },
 282         { BGE_CHIPID_BCM5701_B2,        "BCM5701 B2" },
 283         { BGE_CHIPID_BCM5701_B5,        "BCM5701 B5" },
 284         { BGE_CHIPID_BCM5703_A0,        "BCM5703 A0" },
 285         { BGE_CHIPID_BCM5703_A1,        "BCM5703 A1" },
 286         { BGE_CHIPID_BCM5703_A2,        "BCM5703 A2" },
 287         { BGE_CHIPID_BCM5703_A3,        "BCM5703 A3" },
 288         { BGE_CHIPID_BCM5703_B0,        "BCM5703 B0" },
 289         { BGE_CHIPID_BCM5704_A0,        "BCM5704 A0" },
 290         { BGE_CHIPID_BCM5704_A1,        "BCM5704 A1" },
 291         { BGE_CHIPID_BCM5704_A2,        "BCM5704 A2" },
 292         { BGE_CHIPID_BCM5704_A3,        "BCM5704 A3" },
 293         { BGE_CHIPID_BCM5704_B0,        "BCM5704 B0" },
 294         { BGE_CHIPID_BCM5705_A0,        "BCM5705 A0" },
 295         { BGE_CHIPID_BCM5705_A1,        "BCM5705 A1" },
 296         { BGE_CHIPID_BCM5705_A2,        "BCM5705 A2" },
 297         { BGE_CHIPID_BCM5705_A3,        "BCM5705 A3" },
 298         { BGE_CHIPID_BCM5750_A0,        "BCM5750 A0" },
 299         { BGE_CHIPID_BCM5750_A1,        "BCM5750 A1" },
 300         { BGE_CHIPID_BCM5750_A3,        "BCM5750 A3" },
 301         { BGE_CHIPID_BCM5750_B0,        "BCM5750 B0" },
 302         { BGE_CHIPID_BCM5750_B1,        "BCM5750 B1" },
 303         { BGE_CHIPID_BCM5750_C0,        "BCM5750 C0" },
 304         { BGE_CHIPID_BCM5750_C1,        "BCM5750 C1" },
 305         { BGE_CHIPID_BCM5750_C2,        "BCM5750 C2" },
 306         { BGE_CHIPID_BCM5714_A0,        "BCM5714 A0" },
 307         { BGE_CHIPID_BCM5752_A0,        "BCM5752 A0" },
 308         { BGE_CHIPID_BCM5752_A1,        "BCM5752 A1" },
 309         { BGE_CHIPID_BCM5752_A2,        "BCM5752 A2" },
 310         { BGE_CHIPID_BCM5714_B0,        "BCM5714 B0" },
 311         { BGE_CHIPID_BCM5714_B3,        "BCM5714 B3" },
 312         { BGE_CHIPID_BCM5715_A0,        "BCM5715 A0" },
 313         { BGE_CHIPID_BCM5715_A1,        "BCM5715 A1" },
 314         { BGE_CHIPID_BCM5715_A3,        "BCM5715 A3" },
 315         { BGE_CHIPID_BCM5717_A0,        "BCM5717 A0" },
 316         { BGE_CHIPID_BCM5717_B0,        "BCM5717 B0" },
 317         { BGE_CHIPID_BCM5717_C0,        "BCM5717 C0" },
 318         { BGE_CHIPID_BCM5719_A0,        "BCM5719 A0" },
 319         { BGE_CHIPID_BCM5720_A0,        "BCM5720 A0" },
 320         { BGE_CHIPID_BCM5755_A0,        "BCM5755 A0" },
 321         { BGE_CHIPID_BCM5755_A1,        "BCM5755 A1" },
 322         { BGE_CHIPID_BCM5755_A2,        "BCM5755 A2" },
 323         { BGE_CHIPID_BCM5722_A0,        "BCM5722 A0" },
 324         { BGE_CHIPID_BCM5761_A0,        "BCM5761 A0" },
 325         { BGE_CHIPID_BCM5761_A1,        "BCM5761 A1" },
 326         { BGE_CHIPID_BCM5762_A0,        "BCM5762 A0" },
 327         { BGE_CHIPID_BCM5784_A0,        "BCM5784 A0" },
 328         { BGE_CHIPID_BCM5784_A1,        "BCM5784 A1" },
 329         /* 5754 and 5787 share the same ASIC ID */
 330         { BGE_CHIPID_BCM5787_A0,        "BCM5754/5787 A0" },
 331         { BGE_CHIPID_BCM5787_A1,        "BCM5754/5787 A1" },
 332         { BGE_CHIPID_BCM5787_A2,        "BCM5754/5787 A2" },
 333         { BGE_CHIPID_BCM5906_A1,        "BCM5906 A1" },
 334         { BGE_CHIPID_BCM5906_A2,        "BCM5906 A2" },
 335         { BGE_CHIPID_BCM57765_A0,       "BCM57765 A0" },
 336         { BGE_CHIPID_BCM57765_B0,       "BCM57765 B0" },
 337         { BGE_CHIPID_BCM57780_A0,       "BCM57780 A0" },
 338         { BGE_CHIPID_BCM57780_A1,       "BCM57780 A1" },
 339
 340         { 0, NULL }
 341 };
 342
 343 /*
 344  * Some defaults for major revisions, so that newer steppings
 345  * that we don't know about have a shot at working.
 346  */
 347 static const struct bge_revision bge_majorrevs[] = {
 348         { BGE_ASICREV_BCM5700,          "unknown BCM5700" },
 349         { BGE_ASICREV_BCM5701,          "unknown BCM5701" },
 350         { BGE_ASICREV_BCM5703,          "unknown BCM5703" },
 351         { BGE_ASICREV_BCM5704,          "unknown BCM5704" },
 352         { BGE_ASICREV_BCM5705,          "unknown BCM5705" },
 353         { BGE_ASICREV_BCM5750,          "unknown BCM5750" },
 354         { BGE_ASICREV_BCM5714_A0,       "unknown BCM5714" },
 355         { BGE_ASICREV_BCM5752,          "unknown BCM5752" },
 356         { BGE_ASICREV_BCM5780,          "unknown BCM5780" },
 357         { BGE_ASICREV_BCM5714,          "unknown BCM5714" },
 358         { BGE_ASICREV_BCM5755,          "unknown BCM5755" },
 359         { BGE_ASICREV_BCM5761,          "unknown BCM5761" },
 360         { BGE_ASICREV_BCM5784,          "unknown BCM5784" },
 361         { BGE_ASICREV_BCM5785,          "unknown BCM5785" },
 362         /* 5754 and 5787 share the same ASIC ID */
 363         { BGE_ASICREV_BCM5787,          "unknown BCM5754/5787" },
 364         { BGE_ASICREV_BCM5906,          "unknown BCM5906" },
 365         { BGE_ASICREV_BCM57765,         "unknown BCM57765" },
 366         { BGE_ASICREV_BCM57766,         "unknown BCM57766" },
 367         { BGE_ASICREV_BCM57780,         "unknown BCM57780" },
 368         { BGE_ASICREV_BCM5717,          "unknown BCM5717" },
 369         { BGE_ASICREV_BCM5719,          "unknown BCM5719" },
 370         { BGE_ASICREV_BCM5720,          "unknown BCM5720" },
 371         { BGE_ASICREV_BCM5762,          "unknown BCM5762" },
 372
 373         { 0, NULL }
 374 };
 375
 376 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 377 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 378 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 379 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 380 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 381 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 382 #define BGE_IS_5717_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5717_PLUS)
 383 #define BGE_IS_57765_PLUS(sc)           ((sc)->bge_flags & BGE_FLAG_57765_PLUS)
 384
 385 static uint32_t bge_chipid(device_t);
 386 static const struct bge_vendor * bge_lookup_vendor(uint16_t);
 387 static const struct bge_revision * bge_lookup_rev(uint32_t);
 388
 389 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 390
 391 static int bge_probe(device_t);
 392 static int bge_attach(device_t);
 393 static int bge_detach(device_t);
 394 static int bge_suspend(device_t);
 395 static int bge_resume(device_t);
 396 static void bge_release_resources(struct bge_softc *);
 397 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 398 static int bge_dma_alloc(struct bge_softc *);
 399 static void bge_dma_free(struct bge_softc *);
 400 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t,
 401     bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
 402
 403 static void bge_devinfo(struct bge_softc *);
 404 static int bge_mbox_reorder(struct bge_softc *);
 405
 406 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
 407 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 408 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 409 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 410 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
 411
 412 static void bge_txeof(struct bge_softc *, uint16_t);
 413 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
 414 static int bge_rxeof(struct bge_softc *, uint16_t, int);
 415
 416 static void bge_asf_driver_up (struct bge_softc *);
 417 static void bge_tick(void *);
 418 static void bge_stats_clear_regs(struct bge_softc *);
 419 static void bge_stats_update(struct bge_softc *);
 420 static void bge_stats_update_regs(struct bge_softc *);
 421 static struct mbuf *bge_check_short_dma(struct mbuf *);
 422 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
 423     uint16_t *, uint16_t *);
 424 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 425
 426 static void bge_intr(void *);
 427 static int bge_msi_intr(void *);
 428 static void bge_intr_task(void *, int);
 429 static void bge_start_locked(if_t);
 430 static void bge_start(if_t);
 431 static int bge_ioctl(if_t, u_long, caddr_t);
 432 static void bge_init_locked(struct bge_softc *);
 433 static void bge_init(void *);
 434 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
 435 static void bge_stop(struct bge_softc *);
 436 static void bge_watchdog(struct bge_softc *);
 437 static int bge_shutdown(device_t);
 438 static int bge_ifmedia_upd_locked(if_t);
 439 static int bge_ifmedia_upd(if_t);
 440 static void bge_ifmedia_sts(if_t, struct ifmediareq *);
 441 static uint64_t bge_get_counter(if_t, ift_counter);
 442
 443 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 444 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 445
 446 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
 447 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
 448
 449 static void bge_setpromisc(struct bge_softc *);
 450 static void bge_setmulti(struct bge_softc *);
 451 static void bge_setvlan(struct bge_softc *);
 452
 453 static __inline void bge_rxreuse_std(struct bge_softc *, int);
 454 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
 455 static int bge_newbuf_std(struct bge_softc *, int);
 456 static int bge_newbuf_jumbo(struct bge_softc *, int);
 457 static int bge_init_rx_ring_std(struct bge_softc *);
 458 static void bge_free_rx_ring_std(struct bge_softc *);
 459 static int bge_init_rx_ring_jumbo(struct bge_softc *);
 460 static void bge_free_rx_ring_jumbo(struct bge_softc *);
 461 static void bge_free_tx_ring(struct bge_softc *);
 462 static int bge_init_tx_ring(struct bge_softc *);
 463
 464 static int bge_chipinit(struct bge_softc *);
 465 static int bge_blockinit(struct bge_softc *);
 466 static uint32_t bge_dma_swap_options(struct bge_softc *);
 467
 468 static int bge_has_eaddr(struct bge_softc *);
 469 static uint32_t bge_readmem_ind(struct bge_softc *, int);
 470 static void bge_writemem_ind(struct bge_softc *, int, int);
 471 static void bge_writembx(struct bge_softc *, int, int);
 472 #ifdef notdef
 473 static uint32_t bge_readreg_ind(struct bge_softc *, int);
 474 #endif
 475 static void bge_writemem_direct(struct bge_softc *, int, int);
 476 static void bge_writereg_ind(struct bge_softc *, int, int);
 477
 478 static int bge_miibus_readreg(device_t, int, int);
 479 static int bge_miibus_writereg(device_t, int, int, int);
 480 static void bge_miibus_statchg(device_t);
 481 #ifdef DEVICE_POLLING
 482 static int bge_poll(if_t ifp, enum poll_cmd cmd, int count);
 483 #endif
 484
 485 #define BGE_RESET_SHUTDOWN      0
 486 #define BGE_RESET_START         1
 487 #define BGE_RESET_SUSPEND       2
 488 static void bge_sig_post_reset(struct bge_softc *, int);
 489 static void bge_sig_legacy(struct bge_softc *, int);
 490 static void bge_sig_pre_reset(struct bge_softc *, int);
 491 static void bge_stop_fw(struct bge_softc *);
 492 static int bge_reset(struct bge_softc *);
 493 static void bge_link_upd(struct bge_softc *);
 494
 495 static void bge_ape_lock_init(struct bge_softc *);
 496 static void bge_ape_read_fw_ver(struct bge_softc *);
 497 static int bge_ape_lock(struct bge_softc *, int);
 498 static void bge_ape_unlock(struct bge_softc *, int);
 499 static void bge_ape_send_event(struct bge_softc *, uint32_t);
 500 static void bge_ape_driver_state_change(struct bge_softc *, int);
 501
 502 /*
 503  * The BGE_REGISTER_DEBUG option is only for low-level debugging.  It may
 504  * leak information to untrusted users.  It is also known to cause alignment
 505  * traps on certain architectures.
 506  */
 507 #ifdef BGE_REGISTER_DEBUG
 508 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 509 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
 510 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS);
 511 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
 512 #endif
 513 static void bge_add_sysctls(struct bge_softc *);
 514 static void bge_add_sysctl_stats_regs(struct bge_softc *,
 515     struct sysctl_ctx_list *, struct sysctl_oid_list *);
 516 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *,
 517     struct sysctl_oid_list *);
 518 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
 519
 520 static device_method_t bge_methods[] = {
 521         /* Device interface */
 522         DEVMETHOD(device_probe,         bge_probe),
 523         DEVMETHOD(device_attach,        bge_attach),
 524         DEVMETHOD(device_detach,        bge_detach),
 525         DEVMETHOD(device_shutdown,      bge_shutdown),
 526         DEVMETHOD(device_suspend,       bge_suspend),
 527         DEVMETHOD(device_resume,        bge_resume),
 528
 529         /* MII interface */
 530         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 531         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 532         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 533
 534         DEVMETHOD_END
 535 };
 536
 537 static driver_t bge_driver = {
 538         "bge",
 539         bge_methods,
 540         sizeof(struct bge_softc)
 541 };
 542
 543 static devclass_t bge_devclass;
 544
 545 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
 546 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 547
 548 static int bge_allow_asf = 1;
 549
 550 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
 551 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RDTUN, &bge_allow_asf, 0,
 552         "Allow ASF mode if available");
 553
 554 #define SPARC64_BLADE_1500_MODEL        "SUNW,Sun-Blade-1500"
 555 #define SPARC64_BLADE_1500_PATH_BGE     "/pci@1f,700000/network@2"
 556 #define SPARC64_BLADE_2500_MODEL        "SUNW,Sun-Blade-2500"
 557 #define SPARC64_BLADE_2500_PATH_BGE     "/pci@1c,600000/network@3"
 558 #define SPARC64_OFW_SUBVENDOR           "subsystem-vendor-id"
 559
 560 static int
 561 bge_has_eaddr(struct bge_softc *sc)
 562 {
 563 #ifdef __sparc64__
 564         char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
 565         device_t dev;
 566         uint32_t subvendor;
 567
 568         dev = sc->bge_dev;
 569
 570         /*
 571          * The on-board BGEs found in sun4u machines aren't fitted with
 572          * an EEPROM which means that we have to obtain the MAC address
 573          * via OFW and that some tests will always fail.  We distinguish
 574          * such BGEs by the subvendor ID, which also has to be obtained
 575          * from OFW instead of the PCI configuration space as the latter
 576          * indicates Broadcom as the subvendor of the netboot interface.
 577          * For early Blade 1500 and 2500 we even have to check the OFW
 578          * device path as the subvendor ID always defaults to Broadcom
 579          * there.
 580          */
 581         if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
 582             &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
 583             (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID))
 584                 return (0);
 585         memset(buf, 0, sizeof(buf));
 586         if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
 587                 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
 588                     strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
 589                         return (0);
 590                 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
 591                     strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
 592                         return (0);
 593         }
 594 #endif
 595         return (1);
 596 }
 597
 598 static uint32_t
 599 bge_readmem_ind(struct bge_softc *sc, int off)
 600 {
 601         device_t dev;
 602         uint32_t val;
 603
 604         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 605             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 606                 return (0);
 607
 608         dev = sc->bge_dev;
 609
 610         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 611         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 612         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 613         return (val);
 614 }
 615
 616 static void
 617 bge_writemem_ind(struct bge_softc *sc, int off, int val)
 618 {
 619         device_t dev;
 620
 621         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 622             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 623                 return;
 624
 625         dev = sc->bge_dev;
 626
 627         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 628         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 629         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 630 }
 631
 632 #ifdef notdef
 633 static uint32_t
 634 bge_readreg_ind(struct bge_softc *sc, int off)
 635 {
 636         device_t dev;
 637
 638         dev = sc->bge_dev;
 639
 640         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 641         return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 642 }
 643 #endif
 644
 645 static void
 646 bge_writereg_ind(struct bge_softc *sc, int off, int val)
 647 {
 648         device_t dev;
 649
 650         dev = sc->bge_dev;
 651
 652         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 653         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 654 }
 655
 656 static void
 657 bge_writemem_direct(struct bge_softc *sc, int off, int val)
 658 {
 659         CSR_WRITE_4(sc, off, val);
 660 }
 661
 662 static void
 663 bge_writembx(struct bge_softc *sc, int off, int val)
 664 {
 665         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 666                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 667
 668         CSR_WRITE_4(sc, off, val);
 669         if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0)
 670                 CSR_READ_4(sc, off);
 671 }
 672
 673 /*
 674  * Clear all stale locks and select the lock for this driver instance.
 675  */
 676 static void
 677 bge_ape_lock_init(struct bge_softc *sc)
 678 {
 679         uint32_t bit, regbase;
 680         int i;
 681
 682         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 683                 regbase = BGE_APE_LOCK_GRANT;
 684         else
 685                 regbase = BGE_APE_PER_LOCK_GRANT;
 686
 687         /* Clear any stale locks. */
 688         for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
 689                 switch (i) {
 690                 case BGE_APE_LOCK_PHY0:
 691                 case BGE_APE_LOCK_PHY1:
 692                 case BGE_APE_LOCK_PHY2:
 693                 case BGE_APE_LOCK_PHY3:
 694                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
 695                         break;
 696                 default:
 697                         if (sc->bge_func_addr == 0)
 698                                 bit = BGE_APE_LOCK_GRANT_DRIVER0;
 699                         else
 700                                 bit = (1 << sc->bge_func_addr);
 701                 }
 702                 APE_WRITE_4(sc, regbase + 4 * i, bit);
 703         }
 704
 705         /* Select the PHY lock based on the device's function number. */
 706         switch (sc->bge_func_addr) {
 707         case 0:
 708                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
 709                 break;
 710         case 1:
 711                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
 712                 break;
 713         case 2:
 714                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
 715                 break;
 716         case 3:
 717                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
 718                 break;
 719         default:
 720                 device_printf(sc->bge_dev,
 721                     "PHY lock not supported on this function\n");
 722         }
 723 }
 724
 725 /*
 726  * Check for APE firmware, set flags, and print version info.
 727  */
 728 static void
 729 bge_ape_read_fw_ver(struct bge_softc *sc)
 730 {
 731         const char *fwtype;
 732         uint32_t apedata, features;
 733
 734         /* Check for a valid APE signature in shared memory. */
 735         apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
 736         if (apedata != BGE_APE_SEG_SIG_MAGIC) {
 737                 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE;
 738                 return;
 739         }
 740
 741         /* Check if APE firmware is running. */
 742         apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
 743         if ((apedata & BGE_APE_FW_STATUS_READY) == 0) {
 744                 device_printf(sc->bge_dev, "APE signature found "
 745                     "but FW status not ready! 0x%08x\n", apedata);
 746                 return;
 747         }
 748
 749         sc->bge_mfw_flags |= BGE_MFW_ON_APE;
 750
 751         /* Fetch the APE firwmare type and version. */
 752         apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
 753         features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
 754         if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) {
 755                 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
 756                 fwtype = "NCSI";
 757         } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) {
 758                 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
 759                 fwtype = "DASH";
 760         } else
 761                 fwtype = "UNKN";
 762
 763         /* Print the APE firmware version. */
 764         device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n",
 765             fwtype,
 766             (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT,
 767             (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT,
 768             (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT,
 769             (apedata & BGE_APE_FW_VERSION_BLDMSK));
 770 }
 771
 772 static int
 773 bge_ape_lock(struct bge_softc *sc, int locknum)
 774 {
 775         uint32_t bit, gnt, req, status;
 776         int i, off;
 777
 778         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
 779                 return (0);
 780
 781         /* Lock request/grant registers have different bases. */
 782         if (sc->bge_asicrev == BGE_ASICREV_BCM5761) {
 783                 req = BGE_APE_LOCK_REQ;
 784                 gnt = BGE_APE_LOCK_GRANT;
 785         } else {
 786                 req = BGE_APE_PER_LOCK_REQ;
 787                 gnt = BGE_APE_PER_LOCK_GRANT;
 788         }
 789
 790         off = 4 * locknum;
 791
 792         switch (locknum) {
 793         case BGE_APE_LOCK_GPIO:
 794                 /* Lock required when using GPIO. */
 795                 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 796                         return (0);
 797                 if (sc->bge_func_addr == 0)
 798                         bit = BGE_APE_LOCK_REQ_DRIVER0;
 799                 else
 800                         bit = (1 << sc->bge_func_addr);
 801                 break;
 802         case BGE_APE_LOCK_GRC:
 803                 /* Lock required to reset the device. */
 804                 if (sc->bge_func_addr == 0)
 805                         bit = BGE_APE_LOCK_REQ_DRIVER0;
 806                 else
 807                         bit = (1 << sc->bge_func_addr);
 808                 break;
 809         case BGE_APE_LOCK_MEM:
 810                 /* Lock required when accessing certain APE memory. */
 811                 if (sc->bge_func_addr == 0)
 812                         bit = BGE_APE_LOCK_REQ_DRIVER0;
 813                 else
 814                         bit = (1 << sc->bge_func_addr);
 815                 break;
 816         case BGE_APE_LOCK_PHY0:
 817         case BGE_APE_LOCK_PHY1:
 818         case BGE_APE_LOCK_PHY2:
 819         case BGE_APE_LOCK_PHY3:
 820                 /* Lock required when accessing PHYs. */
 821                 bit = BGE_APE_LOCK_REQ_DRIVER0;
 822                 break;
 823         default:
 824                 return (EINVAL);
 825         }
 826
 827         /* Request a lock. */
 828         APE_WRITE_4(sc, req + off, bit);
 829
 830         /* Wait up to 1 second to acquire lock. */
 831         for (i = 0; i < 20000; i++) {
 832                 status = APE_READ_4(sc, gnt + off);
 833                 if (status == bit)
 834                         break;
 835                 DELAY(50);
 836         }
 837
 838         /* Handle any errors. */
 839         if (status != bit) {
 840                 device_printf(sc->bge_dev, "APE lock %d request failed! "
 841                     "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
 842                     locknum, req + off, bit & 0xFFFF, gnt + off,
 843                     status & 0xFFFF);
 844                 /* Revoke the lock request. */
 845                 APE_WRITE_4(sc, gnt + off, bit);
 846                 return (EBUSY);
 847         }
 848
 849         return (0);
 850 }
 851
 852 static void
 853 bge_ape_unlock(struct bge_softc *sc, int locknum)
 854 {
 855         uint32_t bit, gnt;
 856         int off;
 857
 858         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
 859                 return;
 860
 861         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 862                 gnt = BGE_APE_LOCK_GRANT;
 863         else
 864                 gnt = BGE_APE_PER_LOCK_GRANT;
 865
 866         off = 4 * locknum;
 867
 868         switch (locknum) {
 869         case BGE_APE_LOCK_GPIO:
 870                 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 871                         return;
 872                 if (sc->bge_func_addr == 0)
 873                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
 874                 else
 875                         bit = (1 << sc->bge_func_addr);
 876                 break;
 877         case BGE_APE_LOCK_GRC:
 878                 if (sc->bge_func_addr == 0)
 879                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
 880                 else
 881                         bit = (1 << sc->bge_func_addr);
 882                 break;
 883         case BGE_APE_LOCK_MEM:
 884                 if (sc->bge_func_addr == 0)
 885                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
 886                 else
 887                         bit = (1 << sc->bge_func_addr);
 888                 break;
 889         case BGE_APE_LOCK_PHY0:
 890         case BGE_APE_LOCK_PHY1:
 891         case BGE_APE_LOCK_PHY2:
 892         case BGE_APE_LOCK_PHY3:
 893                 bit = BGE_APE_LOCK_GRANT_DRIVER0;
 894                 break;
 895         default:
 896                 return;
 897         }
 898
 899         APE_WRITE_4(sc, gnt + off, bit);
 900 }
 901
 902 /*
 903  * Send an event to the APE firmware.
 904  */
 905 static void
 906 bge_ape_send_event(struct bge_softc *sc, uint32_t event)
 907 {
 908         uint32_t apedata;
 909         int i;
 910
 911         /* NCSI does not support APE events. */
 912         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
 913                 return;
 914
 915         /* Wait up to 1ms for APE to service previous event. */
 916         for (i = 10; i > 0; i--) {
 917                 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
 918                         break;
 919                 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
 920                 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) {
 921                         APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
 922                             BGE_APE_EVENT_STATUS_EVENT_PENDING);
 923                         bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
 924                         APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
 925                         break;
 926                 }
 927                 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
 928                 DELAY(100);
 929         }
 930         if (i == 0)
 931                 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n",
 932                     event);
 933 }
 934
 935 static void
 936 bge_ape_driver_state_change(struct bge_softc *sc, int kind)
 937 {
 938         uint32_t apedata, event;
 939
 940         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
 941                 return;
 942
 943         switch (kind) {
 944         case BGE_RESET_START:
 945                 /* If this is the first load, clear the load counter. */
 946                 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
 947                 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC)
 948                         APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
 949                 else {
 950                         apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
 951                         APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
 952                 }
 953                 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
 954                     BGE_APE_HOST_SEG_SIG_MAGIC);
 955                 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
 956                     BGE_APE_HOST_SEG_LEN_MAGIC);
 957
 958                 /* Add some version info if bge(4) supports it. */
 959                 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
 960                     BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0));
 961                 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
 962                     BGE_APE_HOST_BEHAV_NO_PHYLOCK);
 963                 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
 964                     BGE_APE_HOST_HEARTBEAT_INT_DISABLE);
 965                 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
 966                     BGE_APE_HOST_DRVR_STATE_START);
 967                 event = BGE_APE_EVENT_STATUS_STATE_START;
 968                 break;
 969         case BGE_RESET_SHUTDOWN:
 970                 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
 971                     BGE_APE_HOST_DRVR_STATE_UNLOAD);
 972                 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
 973                 break;
 974         case BGE_RESET_SUSPEND:
 975                 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
 976                 break;
 977         default:
 978                 return;
 979         }
 980
 981         bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
 982             BGE_APE_EVENT_STATUS_STATE_CHNGE);
 983 }
 984
 985 /*
 986  * Map a single buffer address.
 987  */
 988
 989 static void
 990 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 991 {
 992         struct bge_dmamap_arg *ctx;
 993
 994         if (error)
 995                 return;
 996
 997         KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
 998
 999         ctx = arg;
1000         ctx->bge_busaddr = segs->ds_addr;
1001 }
1002
1003 static uint8_t
1004 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1005 {
1006         uint32_t access, byte = 0;
1007         int i;
1008
1009         /* Lock. */
1010         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
1011         for (i = 0; i < 8000; i++) {
1012                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
1013                         break;
1014                 DELAY(20);
1015         }
1016         if (i == 8000)
1017                 return (1);
1018
1019         /* Enable access. */
1020         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
1021         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
1022
1023         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
1024         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
1025         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
1026                 DELAY(10);
1027                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
1028                         DELAY(10);
1029                         break;
1030                 }
1031         }
1032
1033         if (i == BGE_TIMEOUT * 10) {
1034                 if_printf(sc->bge_ifp, "nvram read timed out\n");
1035                 return (1);
1036         }
1037
1038         /* Get result. */
1039         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
1040
1041         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
1042
1043         /* Disable access. */
1044         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
1045
1046         /* Unlock. */
1047         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
1048         CSR_READ_4(sc, BGE_NVRAM_SWARB);
1049
1050         return (0);
1051 }
1052
1053 /*
1054  * Read a sequence of bytes from NVRAM.
1055  */
1056 static int
1057 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1058 {
1059         int err = 0, i;
1060         uint8_t byte = 0;
1061
1062         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1063                 return (1);
1064
1065         for (i = 0; i < cnt; i++) {
1066                 err = bge_nvram_getbyte(sc, off + i, &byte);
1067                 if (err)
1068                         break;
1069                 *(dest + i) = byte;
1070         }
1071
1072         return (err ? 1 : 0);
1073 }
1074
1075 /*
1076  * Read a byte of data stored in the EEPROM at address 'addr.' The
1077  * BCM570x supports both the traditional bitbang interface and an
1078  * auto access interface for reading the EEPROM. We use the auto
1079  * access method.
1080  */
1081 static uint8_t
1082 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1083 {
1084         int i;
1085         uint32_t byte = 0;
1086
1087         /*
1088          * Enable use of auto EEPROM access so we can avoid
1089          * having to use the bitbang method.
1090          */
1091         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
1092
1093         /* Reset the EEPROM, load the clock period. */
1094         CSR_WRITE_4(sc, BGE_EE_ADDR,
1095             BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
1096         DELAY(20);
1097
1098         /* Issue the read EEPROM command. */
1099         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
1100
1101         /* Wait for completion */
1102         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
1103                 DELAY(10);
1104                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1105                         break;
1106         }
1107
1108         if (i == BGE_TIMEOUT * 10) {
1109                 device_printf(sc->bge_dev, "EEPROM read timed out\n");
1110                 return (1);
1111         }
1112
1113         /* Get result. */
1114         byte = CSR_READ_4(sc, BGE_EE_DATA);
1115
1116         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
1117
1118         return (0);
1119 }
1120
1121 /*
1122  * Read a sequence of bytes from the EEPROM.
1123  */
1124 static int
1125 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1126 {
1127         int i, error = 0;
1128         uint8_t byte = 0;
1129
1130         for (i = 0; i < cnt; i++) {
1131                 error = bge_eeprom_getbyte(sc, off + i, &byte);
1132                 if (error)
1133                         break;
1134                 *(dest + i) = byte;
1135         }
1136
1137         return (error ? 1 : 0);
1138 }
1139
1140 static int
1141 bge_miibus_readreg(device_t dev, int phy, int reg)
1142 {
1143         struct bge_softc *sc;
1144         uint32_t val;
1145         int i;
1146
1147         sc = device_get_softc(dev);
1148
1149         if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1150                 return (0);
1151
1152         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1153         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1154                 CSR_WRITE_4(sc, BGE_MI_MODE,
1155                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1156                 DELAY(80);
1157         }
1158
1159         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
1160             BGE_MIPHY(phy) | BGE_MIREG(reg));
1161
1162         /* Poll for the PHY register access to complete. */
1163         for (i = 0; i < BGE_TIMEOUT; i++) {
1164                 DELAY(10);
1165                 val = CSR_READ_4(sc, BGE_MI_COMM);
1166                 if ((val & BGE_MICOMM_BUSY) == 0) {
1167                         DELAY(5);
1168                         val = CSR_READ_4(sc, BGE_MI_COMM);
1169                         break;
1170                 }
1171         }
1172
1173         if (i == BGE_TIMEOUT) {
1174                 device_printf(sc->bge_dev,
1175                     "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
1176                     phy, reg, val);
1177                 val = 0;
1178         }
1179
1180         /* Restore the autopoll bit if necessary. */
1181         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1182                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1183                 DELAY(80);
1184         }
1185
1186         bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1187
1188         if (val & BGE_MICOMM_READFAIL)
1189                 return (0);
1190
1191         return (val & 0xFFFF);
1192 }
1193
1194 static int
1195 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
1196 {
1197         struct bge_softc *sc;
1198         int i;
1199
1200         sc = device_get_softc(dev);
1201
1202         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1203             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
1204                 return (0);
1205
1206         if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1207                 return (0);
1208
1209         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1210         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1211                 CSR_WRITE_4(sc, BGE_MI_MODE,
1212                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1213                 DELAY(80);
1214         }
1215
1216         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
1217             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
1218
1219         for (i = 0; i < BGE_TIMEOUT; i++) {
1220                 DELAY(10);
1221                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
1222                         DELAY(5);
1223                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
1224                         break;
1225                 }
1226         }
1227
1228         /* Restore the autopoll bit if necessary. */
1229         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1230                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1231                 DELAY(80);
1232         }
1233
1234         bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1235
1236         if (i == BGE_TIMEOUT)
1237                 device_printf(sc->bge_dev,
1238                     "PHY write timed out (phy %d, reg %d, val 0x%04x)\n",
1239                     phy, reg, val);
1240
1241         return (0);
1242 }
1243
1244 static void
1245 bge_miibus_statchg(device_t dev)
1246 {
1247         struct bge_softc *sc;
1248         struct mii_data *mii;
1249         uint32_t mac_mode, rx_mode, tx_mode;
1250
1251         sc = device_get_softc(dev);
1252         if ((if_getdrvflags(sc->bge_ifp) & IFF_DRV_RUNNING) == 0)
1253                 return;
1254         mii = device_get_softc(sc->bge_miibus);
1255
1256         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1257             (IFM_ACTIVE | IFM_AVALID)) {
1258                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1259                 case IFM_10_T:
1260                 case IFM_100_TX:
1261                         sc->bge_link = 1;
1262                         break;
1263                 case IFM_1000_T:
1264                 case IFM_1000_SX:
1265                 case IFM_2500_SX:
1266                         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1267                                 sc->bge_link = 1;
1268                         else
1269                                 sc->bge_link = 0;
1270                         break;
1271                 default:
1272                         sc->bge_link = 0;
1273                         break;
1274                 }
1275         } else
1276                 sc->bge_link = 0;
1277         if (sc->bge_link == 0)
1278                 return;
1279
1280         /*
1281          * APE firmware touches these registers to keep the MAC
1282          * connected to the outside world.  Try to keep the
1283          * accesses atomic.
1284          */
1285
1286         /* Set the port mode (MII/GMII) to match the link speed. */
1287         mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
1288             ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
1289         tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
1290         rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
1291
1292         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1293             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
1294                 mac_mode |= BGE_PORTMODE_GMII;
1295         else
1296                 mac_mode |= BGE_PORTMODE_MII;
1297
1298         /* Set MAC flow control behavior to match link flow control settings. */
1299         tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE;
1300         rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE;
1301         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1302                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1303                         tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE;
1304                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1305                         rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE;
1306         } else
1307                 mac_mode |= BGE_MACMODE_HALF_DUPLEX;
1308
1309         CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
1310         DELAY(40);
1311         CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
1312         CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
1313 }
1314
1315 /*
1316  * Intialize a standard receive ring descriptor.
1317  */
1318 static int
1319 bge_newbuf_std(struct bge_softc *sc, int i)
1320 {
1321         struct mbuf *m;
1322         struct bge_rx_bd *r;
1323         bus_dma_segment_t segs[1];
1324         bus_dmamap_t map;
1325         int error, nsegs;
1326
1327         if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
1328             (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
1329             ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) {
1330                 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1331                 if (m == NULL)
1332                         return (ENOBUFS);
1333                 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1334         } else {
1335                 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1336                 if (m == NULL)
1337                         return (ENOBUFS);
1338                 m->m_len = m->m_pkthdr.len = MCLBYTES;
1339         }
1340         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1341                 m_adj(m, ETHER_ALIGN);
1342
1343         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
1344             sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
1345         if (error != 0) {
1346                 m_freem(m);
1347                 return (error);
1348         }
1349         if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1350                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1351                     sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
1352                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1353                     sc->bge_cdata.bge_rx_std_dmamap[i]);
1354         }
1355         map = sc->bge_cdata.bge_rx_std_dmamap[i];
1356         sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
1357         sc->bge_cdata.bge_rx_std_sparemap = map;
1358         sc->bge_cdata.bge_rx_std_chain[i] = m;
1359         sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
1360         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
1361         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1362         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1363         r->bge_flags = BGE_RXBDFLAG_END;
1364         r->bge_len = segs[0].ds_len;
1365         r->bge_idx = i;
1366
1367         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1368             sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
1369
1370         return (0);
1371 }
1372
1373 /*
1374  * Initialize a jumbo receive ring descriptor. This allocates
1375  * a jumbo buffer from the pool managed internally by the driver.
1376  */
1377 static int
1378 bge_newbuf_jumbo(struct bge_softc *sc, int i)
1379 {
1380         bus_dma_segment_t segs[BGE_NSEG_JUMBO];
1381         bus_dmamap_t map;
1382         struct bge_extrx_bd *r;
1383         struct mbuf *m;
1384         int error, nsegs;
1385
1386         MGETHDR(m, M_NOWAIT, MT_DATA);
1387         if (m == NULL)
1388                 return (ENOBUFS);
1389
1390         if (m_cljget(m, M_NOWAIT, MJUM9BYTES) == NULL) {
1391                 m_freem(m);
1392                 return (ENOBUFS);
1393         }
1394         m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1395         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1396                 m_adj(m, ETHER_ALIGN);
1397
1398         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1399             sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1400         if (error != 0) {
1401                 m_freem(m);
1402                 return (error);
1403         }
1404
1405         if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1406                 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1407                     sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1408                 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1409                     sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1410         }
1411         map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1412         sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1413             sc->bge_cdata.bge_rx_jumbo_sparemap;
1414         sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1415         sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1416         sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1417         sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1418         sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1419         sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1420
1421         /*
1422          * Fill in the extended RX buffer descriptor.
1423          */
1424         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1425         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1426         r->bge_idx = i;
1427         r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1428         switch (nsegs) {
1429         case 4:
1430                 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1431                 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1432                 r->bge_len3 = segs[3].ds_len;
1433                 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1434         case 3:
1435                 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1436                 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1437                 r->bge_len2 = segs[2].ds_len;
1438                 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1439         case 2:
1440                 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1441                 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1442                 r->bge_len1 = segs[1].ds_len;
1443                 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1444         case 1:
1445                 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1446                 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1447                 r->bge_len0 = segs[0].ds_len;
1448                 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1449                 break;
1450         default:
1451                 panic("%s: %d segments\n", __func__, nsegs);
1452         }
1453
1454         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1455             sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1456
1457         return (0);
1458 }
1459
1460 static int
1461 bge_init_rx_ring_std(struct bge_softc *sc)
1462 {
1463         int error, i;
1464
1465         bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1466         sc->bge_std = 0;
1467         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1468                 if ((error = bge_newbuf_std(sc, i)) != 0)
1469                         return (error);
1470                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1471         }
1472
1473         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1474             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1475
1476         sc->bge_std = 0;
1477         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1478
1479         return (0);
1480 }
1481
1482 static void
1483 bge_free_rx_ring_std(struct bge_softc *sc)
1484 {
1485         int i;
1486
1487         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1488                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1489                         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1490                             sc->bge_cdata.bge_rx_std_dmamap[i],
1491                             BUS_DMASYNC_POSTREAD);
1492                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1493                             sc->bge_cdata.bge_rx_std_dmamap[i]);
1494                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1495                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1496                 }
1497                 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1498                     sizeof(struct bge_rx_bd));
1499         }
1500 }
1501
1502 static int
1503 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1504 {
1505         struct bge_rcb *rcb;
1506         int error, i;
1507
1508         bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1509         sc->bge_jumbo = 0;
1510         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1511                 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1512                         return (error);
1513                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1514         }
1515
1516         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1517             sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1518
1519         sc->bge_jumbo = 0;
1520
1521         /* Enable the jumbo receive producer ring. */
1522         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1523         rcb->bge_maxlen_flags =
1524             BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD);
1525         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1526
1527         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1528
1529         return (0);
1530 }
1531
1532 static void
1533 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1534 {
1535         int i;
1536
1537         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1538                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1539                         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1540                             sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1541                             BUS_DMASYNC_POSTREAD);
1542                         bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1543                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1544                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1545                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1546                 }
1547                 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1548                     sizeof(struct bge_extrx_bd));
1549         }
1550 }
1551
1552 static void
1553 bge_free_tx_ring(struct bge_softc *sc)
1554 {
1555         int i;
1556
1557         if (sc->bge_ldata.bge_tx_ring == NULL)
1558                 return;
1559
1560         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1561                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1562                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1563                             sc->bge_cdata.bge_tx_dmamap[i],
1564                             BUS_DMASYNC_POSTWRITE);
1565                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1566                             sc->bge_cdata.bge_tx_dmamap[i]);
1567                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1568                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1569                 }
1570                 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1571                     sizeof(struct bge_tx_bd));
1572         }
1573 }
1574
1575 static int
1576 bge_init_tx_ring(struct bge_softc *sc)
1577 {
1578         sc->bge_txcnt = 0;
1579         sc->bge_tx_saved_considx = 0;
1580
1581         bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1582         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1583             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1584
1585         /* Initialize transmit producer index for host-memory send ring. */
1586         sc->bge_tx_prodidx = 0;
1587         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1588
1589         /* 5700 b2 errata */
1590         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1591                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1592
1593         /* NIC-memory send ring not used; initialize to zero. */
1594         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1595         /* 5700 b2 errata */
1596         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1597                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1598
1599         return (0);
1600 }
1601
1602 static void
1603 bge_setpromisc(struct bge_softc *sc)
1604 {
1605         if_t ifp;
1606
1607         BGE_LOCK_ASSERT(sc);
1608
1609         ifp = sc->bge_ifp;
1610
1611         /* Enable or disable promiscuous mode as needed. */
1612         if (if_getflags(ifp) & IFF_PROMISC)
1613                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1614         else
1615                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1616 }
1617
1618 static void
1619 bge_setmulti(struct bge_softc *sc)
1620 {
1621         if_t ifp;
1622         int mc_count = 0;
1623         uint32_t hashes[4] = { 0, 0, 0, 0 };
1624         int h, i, mcnt;
1625         unsigned char *mta;
1626
1627         BGE_LOCK_ASSERT(sc);
1628
1629         ifp = sc->bge_ifp;
1630
1631         mc_count = if_multiaddr_count(ifp, -1);
1632         mta = malloc(sizeof(unsigned char) *  ETHER_ADDR_LEN *
1633             mc_count, M_DEVBUF, M_NOWAIT);
1634
1635         if(mta == NULL) {
1636                 device_printf(sc->bge_dev,
1637                     "Failed to allocated temp mcast list\n");
1638                 return;
1639         }
1640
1641         if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) {
1642                 for (i = 0; i < 4; i++)
1643                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1644                 free(mta, M_DEVBUF);
1645                 return;
1646         }
1647
1648         /* First, zot all the existing filters. */
1649         for (i = 0; i < 4; i++)
1650                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1651
1652         if_multiaddr_array(ifp, mta, &mcnt, mc_count);
1653         for(i = 0; i < mcnt; i++) {
1654                 h = ether_crc32_le(mta + (i * ETHER_ADDR_LEN),
1655                     ETHER_ADDR_LEN) & 0x7F;
1656                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1657         }
1658
1659         for (i = 0; i < 4; i++)
1660                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1661
1662         free(mta, M_DEVBUF);
1663 }
1664
1665 static void
1666 bge_setvlan(struct bge_softc *sc)
1667 {
1668         if_t ifp;
1669
1670         BGE_LOCK_ASSERT(sc);
1671
1672         ifp = sc->bge_ifp;
1673
1674         /* Enable or disable VLAN tag stripping as needed. */
1675         if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING)
1676                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1677         else
1678                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1679 }
1680
1681 static void
1682 bge_sig_pre_reset(struct bge_softc *sc, int type)
1683 {
1684
1685         /*
1686          * Some chips don't like this so only do this if ASF is enabled
1687          */
1688         if (sc->bge_asf_mode)
1689                 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
1690
1691         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1692                 switch (type) {
1693                 case BGE_RESET_START:
1694                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1695                             BGE_FW_DRV_STATE_START);
1696                         break;
1697                 case BGE_RESET_SHUTDOWN:
1698                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1699                             BGE_FW_DRV_STATE_UNLOAD);
1700                         break;
1701                 case BGE_RESET_SUSPEND:
1702                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1703                             BGE_FW_DRV_STATE_SUSPEND);
1704                         break;
1705                 }
1706         }
1707
1708         if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
1709                 bge_ape_driver_state_change(sc, type);
1710 }
1711
1712 static void
1713 bge_sig_post_reset(struct bge_softc *sc, int type)
1714 {
1715
1716         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1717                 switch (type) {
1718                 case BGE_RESET_START:
1719                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1720                             BGE_FW_DRV_STATE_START_DONE);
1721                         /* START DONE */
1722                         break;
1723                 case BGE_RESET_SHUTDOWN:
1724                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1725                             BGE_FW_DRV_STATE_UNLOAD_DONE);
1726                         break;
1727                 }
1728         }
1729         if (type == BGE_RESET_SHUTDOWN)
1730                 bge_ape_driver_state_change(sc, type);
1731 }
1732
1733 static void
1734 bge_sig_legacy(struct bge_softc *sc, int type)
1735 {
1736
1737         if (sc->bge_asf_mode) {
1738                 switch (type) {
1739                 case BGE_RESET_START:
1740                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1741                             BGE_FW_DRV_STATE_START);
1742                         break;
1743                 case BGE_RESET_SHUTDOWN:
1744                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1745                             BGE_FW_DRV_STATE_UNLOAD);
1746                         break;
1747                 }
1748         }
1749 }
1750
1751 static void
1752 bge_stop_fw(struct bge_softc *sc)
1753 {
1754         int i;
1755
1756         if (sc->bge_asf_mode) {
1757                 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
1758                 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
1759                     CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
1760
1761                 for (i = 0; i < 100; i++ ) {
1762                         if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1763                             BGE_RX_CPU_DRV_EVENT))
1764                                 break;
1765                         DELAY(10);
1766                 }
1767         }
1768 }
1769
1770 static uint32_t
1771 bge_dma_swap_options(struct bge_softc *sc)
1772 {
1773         uint32_t dma_options;
1774
1775         dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
1776             BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
1777 #if BYTE_ORDER == BIG_ENDIAN
1778         dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
1779 #endif
1780         return (dma_options);
1781 }
1782
1783 /*
1784  * Do endian, PCI and DMA initialization.
1785  */
1786 static int
1787 bge_chipinit(struct bge_softc *sc)
1788 {
1789         uint32_t dma_rw_ctl, misc_ctl, mode_ctl;
1790         uint16_t val;
1791         int i;
1792
1793         /* Set endianness before we access any non-PCI registers. */
1794         misc_ctl = BGE_INIT;
1795         if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1796                 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1797         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1798
1799         /*
1800          * Clear the MAC statistics block in the NIC's
1801          * internal memory.
1802          */
1803         for (i = BGE_STATS_BLOCK;
1804             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1805                 BGE_MEMWIN_WRITE(sc, i, 0);
1806
1807         for (i = BGE_STATUS_BLOCK;
1808             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1809                 BGE_MEMWIN_WRITE(sc, i, 0);
1810
1811         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1812                 /*
1813                  *  Fix data corruption caused by non-qword write with WB.
1814                  *  Fix master abort in PCI mode.
1815                  *  Fix PCI latency timer.
1816                  */
1817                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1818                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1819                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1820         }
1821
1822         if (sc->bge_asicrev == BGE_ASICREV_BCM57765 ||
1823             sc->bge_asicrev == BGE_ASICREV_BCM57766) {
1824                 /*
1825                  * For the 57766 and non Ax versions of 57765, bootcode
1826                  * needs to setup the PCIE Fast Training Sequence (FTS)
1827                  * value to prevent transmit hangs.
1828                  */
1829                 if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) {
1830                         CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL,
1831                             CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) |
1832                             BGE_CPMU_PADRNG_CTL_RDIV2);
1833                 }
1834         }
1835
1836         /*
1837          * Set up the PCI DMA control register.
1838          */
1839         dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1840             BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1841         if (sc->bge_flags & BGE_FLAG_PCIE) {
1842                 if (sc->bge_mps >= 256)
1843                         dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1844                 else
1845                         dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1846         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1847                 if (BGE_IS_5714_FAMILY(sc)) {
1848                         /* 256 bytes for read and write. */
1849                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1850                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1851                         dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1852                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1853                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1854                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1855                         /*
1856                          * In the BCM5703, the DMA read watermark should
1857                          * be set to less than or equal to the maximum
1858                          * memory read byte count of the PCI-X command
1859                          * register.
1860                          */
1861                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1862                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1863                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1864                         /* 1536 bytes for read, 384 bytes for write. */
1865                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1866                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1867                 } else {
1868                         /* 384 bytes for read and write. */
1869                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1870                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1871                             0x0F;
1872                 }
1873                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1874                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1875                         uint32_t tmp;
1876
1877                         /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1878                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1879                         if (tmp == 6 || tmp == 7)
1880                                 dma_rw_ctl |=
1881                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1882
1883                         /* Set PCI-X DMA write workaround. */
1884                         dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1885                 }
1886         } else {
1887                 /* Conventional PCI bus: 256 bytes for read and write. */
1888                 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1889                     BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1890
1891                 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1892                     sc->bge_asicrev != BGE_ASICREV_BCM5750)
1893                         dma_rw_ctl |= 0x0F;
1894         }
1895         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1896             sc->bge_asicrev == BGE_ASICREV_BCM5701)
1897                 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1898                     BGE_PCIDMARWCTL_ASRT_ALL_BE;
1899         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1900             sc->bge_asicrev == BGE_ASICREV_BCM5704)
1901                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1902         if (BGE_IS_5717_PLUS(sc)) {
1903                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1904                 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
1905                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1906                 /*
1907                  * Enable HW workaround for controllers that misinterpret
1908                  * a status tag update and leave interrupts permanently
1909                  * disabled.
1910                  */
1911                 if (!BGE_IS_57765_PLUS(sc) &&
1912                     sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
1913                     sc->bge_asicrev != BGE_ASICREV_BCM5762)
1914                         dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1915         }
1916         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1917
1918         /*
1919          * Set up general mode register.
1920          */
1921         mode_ctl = bge_dma_swap_options(sc);
1922         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
1923             sc->bge_asicrev == BGE_ASICREV_BCM5762) {
1924                 /* Retain Host-2-BMC settings written by APE firmware. */
1925                 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
1926                     (BGE_MODECTL_BYTESWAP_B2HRX_DATA |
1927                     BGE_MODECTL_WORDSWAP_B2HRX_DATA |
1928                     BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE);
1929         }
1930         mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1931             BGE_MODECTL_TX_NO_PHDR_CSUM;
1932
1933         /*
1934          * BCM5701 B5 have a bug causing data corruption when using
1935          * 64-bit DMA reads, which can be terminated early and then
1936          * completed later as 32-bit accesses, in combination with
1937          * certain bridges.
1938          */
1939         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1940             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1941                 mode_ctl |= BGE_MODECTL_FORCE_PCI32;
1942
1943         /*
1944          * Tell the firmware the driver is running
1945          */
1946         if (sc->bge_asf_mode & ASF_STACKUP)
1947                 mode_ctl |= BGE_MODECTL_STACKUP;
1948
1949         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1950
1951         /*
1952          * Disable memory write invalidate.  Apparently it is not supported
1953          * properly by these devices.
1954          */
1955         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1956
1957         /* Set the timer prescaler (always 66 MHz). */
1958         CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1959
1960         /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1961         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1962                 DELAY(40);      /* XXX */
1963
1964                 /* Put PHY into ready state */
1965                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1966                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1967                 DELAY(40);
1968         }
1969
1970         return (0);
1971 }
1972
1973 static int
1974 bge_blockinit(struct bge_softc *sc)
1975 {
1976         struct bge_rcb *rcb;
1977         bus_size_t vrcb;
1978         bge_hostaddr taddr;
1979         uint32_t dmactl, rdmareg, val;
1980         int i, limit;
1981
1982         /*
1983          * Initialize the memory window pointer register so that
1984          * we can access the first 32K of internal NIC RAM. This will
1985          * allow us to set up the TX send ring RCBs and the RX return
1986          * ring RCBs, plus other things which live in NIC memory.
1987          */
1988         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1989
1990         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1991
1992         if (!(BGE_IS_5705_PLUS(sc))) {
1993                 /* Configure mbuf memory pool */
1994                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1995                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1996                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1997                 else
1998                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1999
2000                 /* Configure DMA resource pool */
2001                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
2002                     BGE_DMA_DESCRIPTORS);
2003                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
2004         }
2005
2006         /* Configure mbuf pool watermarks */
2007         if (BGE_IS_5717_PLUS(sc)) {
2008                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2009                 if (if_getmtu(sc->bge_ifp) > ETHERMTU) {
2010                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
2011                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
2012                 } else {
2013                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
2014                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
2015                 }
2016         } else if (!BGE_IS_5705_PLUS(sc)) {
2017                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
2018                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
2019                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2020         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2021                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2022                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
2023                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
2024         } else {
2025                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2026                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
2027                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2028         }
2029
2030         /* Configure DMA resource watermarks */
2031         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
2032         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
2033
2034         /* Enable buffer manager */
2035         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
2036         /*
2037          * Change the arbitration algorithm of TXMBUF read request to
2038          * round-robin instead of priority based for BCM5719.  When
2039          * TXFIFO is almost empty, RDMA will hold its request until
2040          * TXFIFO is not almost empty.
2041          */
2042         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2043                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
2044         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
2045
2046         /* Poll for buffer manager start indication */
2047         for (i = 0; i < BGE_TIMEOUT; i++) {
2048                 DELAY(10);
2049                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
2050                         break;
2051         }
2052
2053         if (i == BGE_TIMEOUT) {
2054                 device_printf(sc->bge_dev, "buffer manager failed to start\n");
2055                 return (ENXIO);
2056         }
2057
2058         /* Enable flow-through queues */
2059         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2060         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2061
2062         /* Wait until queue initialization is complete */
2063         for (i = 0; i < BGE_TIMEOUT; i++) {
2064                 DELAY(10);
2065                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
2066                         break;
2067         }
2068
2069         if (i == BGE_TIMEOUT) {
2070                 device_printf(sc->bge_dev, "flow-through queue init failed\n");
2071                 return (ENXIO);
2072         }
2073
2074         /*
2075          * Summary of rings supported by the controller:
2076          *
2077          * Standard Receive Producer Ring
2078          * - This ring is used to feed receive buffers for "standard"
2079          *   sized frames (typically 1536 bytes) to the controller.
2080          *
2081          * Jumbo Receive Producer Ring
2082          * - This ring is used to feed receive buffers for jumbo sized
2083          *   frames (i.e. anything bigger than the "standard" frames)
2084          *   to the controller.
2085          *
2086          * Mini Receive Producer Ring
2087          * - This ring is used to feed receive buffers for "mini"
2088          *   sized frames to the controller.
2089          * - This feature required external memory for the controller
2090          *   but was never used in a production system.  Should always
2091          *   be disabled.
2092          *
2093          * Receive Return Ring
2094          * - After the controller has placed an incoming frame into a
2095          *   receive buffer that buffer is moved into a receive return
2096          *   ring.  The driver is then responsible to passing the
2097          *   buffer up to the stack.  Many versions of the controller
2098          *   support multiple RR rings.
2099          *
2100          * Send Ring
2101          * - This ring is used for outgoing frames.  Many versions of
2102          *   the controller support multiple send rings.
2103          */
2104
2105         /* Initialize the standard receive producer ring control block. */
2106         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
2107         rcb->bge_hostaddr.bge_addr_lo =
2108             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
2109         rcb->bge_hostaddr.bge_addr_hi =
2110             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
2111         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2112             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
2113         if (BGE_IS_5717_PLUS(sc)) {
2114                 /*
2115                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
2116                  * Bits 15-2 : Maximum RX frame size
2117                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
2118                  * Bit 0     : Reserved
2119                  */
2120                 rcb->bge_maxlen_flags =
2121                     BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
2122         } else if (BGE_IS_5705_PLUS(sc)) {
2123                 /*
2124                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
2125                  * Bits 15-2 : Reserved (should be 0)
2126                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
2127                  * Bit 0     : Reserved
2128                  */
2129                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
2130         } else {
2131                 /*
2132                  * Ring size is always XXX entries
2133                  * Bits 31-16: Maximum RX frame size
2134                  * Bits 15-2 : Reserved (should be 0)
2135                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
2136                  * Bit 0     : Reserved
2137                  */
2138                 rcb->bge_maxlen_flags =
2139                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
2140         }
2141         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2142             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2143             sc->bge_asicrev == BGE_ASICREV_BCM5720)
2144                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
2145         else
2146                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
2147         /* Write the standard receive producer ring control block. */
2148         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
2149         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
2150         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
2151         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
2152
2153         /* Reset the standard receive producer ring producer index. */
2154         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
2155
2156         /*
2157          * Initialize the jumbo RX producer ring control
2158          * block.  We set the 'ring disabled' bit in the
2159          * flags field until we're actually ready to start
2160          * using this ring (i.e. once we set the MTU
2161          * high enough to require it).
2162          */
2163         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2164                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
2165                 /* Get the jumbo receive producer ring RCB parameters. */
2166                 rcb->bge_hostaddr.bge_addr_lo =
2167                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2168                 rcb->bge_hostaddr.bge_addr_hi =
2169                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2170                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2171                     sc->bge_cdata.bge_rx_jumbo_ring_map,
2172                     BUS_DMASYNC_PREREAD);
2173                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
2174                     BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
2175                 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2176                     sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2177                     sc->bge_asicrev == BGE_ASICREV_BCM5720)
2178                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
2179                 else
2180                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
2181                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
2182                     rcb->bge_hostaddr.bge_addr_hi);
2183                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
2184                     rcb->bge_hostaddr.bge_addr_lo);
2185                 /* Program the jumbo receive producer ring RCB parameters. */
2186                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
2187                     rcb->bge_maxlen_flags);
2188                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
2189                 /* Reset the jumbo receive producer ring producer index. */
2190                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
2191         }
2192
2193         /* Disable the mini receive producer ring RCB. */
2194         if (BGE_IS_5700_FAMILY(sc)) {
2195                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
2196                 rcb->bge_maxlen_flags =
2197                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
2198                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
2199                     rcb->bge_maxlen_flags);
2200                 /* Reset the mini receive producer ring producer index. */
2201                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
2202         }
2203
2204         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
2205         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2206                 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
2207                     sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
2208                     sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
2209                         CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
2210                             (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
2211         }
2212         /*
2213          * The BD ring replenish thresholds control how often the
2214          * hardware fetches new BD's from the producer rings in host
2215          * memory.  Setting the value too low on a busy system can
2216          * starve the hardware and recue the throughpout.
2217          *
2218          * Set the BD ring replentish thresholds. The recommended
2219          * values are 1/8th the number of descriptors allocated to
2220          * each ring.
2221          * XXX The 5754 requires a lower threshold, so it might be a
2222          * requirement of all 575x family chips.  The Linux driver sets
2223          * the lower threshold for all 5705 family chips as well, but there
2224          * are reports that it might not need to be so strict.
2225          *
2226          * XXX Linux does some extra fiddling here for the 5906 parts as
2227          * well.
2228          */
2229         if (BGE_IS_5705_PLUS(sc))
2230                 val = 8;
2231         else
2232                 val = BGE_STD_RX_RING_CNT / 8;
2233         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
2234         if (BGE_IS_JUMBO_CAPABLE(sc))
2235                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
2236                     BGE_JUMBO_RX_RING_CNT/8);
2237         if (BGE_IS_5717_PLUS(sc)) {
2238                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
2239                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
2240         }
2241
2242         /*
2243          * Disable all send rings by setting the 'ring disabled' bit
2244          * in the flags field of all the TX send ring control blocks,
2245          * located in NIC memory.
2246          */
2247         if (!BGE_IS_5705_PLUS(sc))
2248                 /* 5700 to 5704 had 16 send rings. */
2249                 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
2250         else if (BGE_IS_57765_PLUS(sc) ||
2251             sc->bge_asicrev == BGE_ASICREV_BCM5762)
2252                 limit = 2;
2253         else if (BGE_IS_5717_PLUS(sc))
2254                 limit = 4;
2255         else
2256                 limit = 1;
2257         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2258         for (i = 0; i < limit; i++) {
2259                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2260                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
2261                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2262                 vrcb += sizeof(struct bge_rcb);
2263         }
2264
2265         /* Configure send ring RCB 0 (we use only the first ring) */
2266         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2267         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
2268         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2269         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2270         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2271             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2272             sc->bge_asicrev == BGE_ASICREV_BCM5720)
2273                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
2274         else
2275                 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
2276                     BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
2277         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2278             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
2279
2280         /*
2281          * Disable all receive return rings by setting the
2282          * 'ring diabled' bit in the flags field of all the receive
2283          * return ring control blocks, located in NIC memory.
2284          */
2285         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2286             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2287             sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2288                 /* Should be 17, use 16 until we get an SRAM map. */
2289                 limit = 16;
2290         } else if (!BGE_IS_5705_PLUS(sc))
2291                 limit = BGE_RX_RINGS_MAX;
2292         else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2293             sc->bge_asicrev == BGE_ASICREV_BCM5762 ||
2294             BGE_IS_57765_PLUS(sc))
2295                 limit = 4;
2296         else
2297                 limit = 1;
2298         /* Disable all receive return rings. */
2299         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2300         for (i = 0; i < limit; i++) {
2301                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
2302                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
2303                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2304                     BGE_RCB_FLAG_RING_DISABLED);
2305                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2306                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
2307                     (i * (sizeof(uint64_t))), 0);
2308                 vrcb += sizeof(struct bge_rcb);
2309         }
2310
2311         /*
2312          * Set up receive return ring 0.  Note that the NIC address
2313          * for RX return rings is 0x0.  The return rings live entirely
2314          * within the host, so the nicaddr field in the RCB isn't used.
2315          */
2316         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2317         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
2318         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2319         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2320         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2321         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2322             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
2323
2324         /* Set random backoff seed for TX */
2325         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
2326             (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
2327             IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
2328             IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) &
2329             BGE_TX_BACKOFF_SEED_MASK);
2330
2331         /* Set inter-packet gap */
2332         val = 0x2620;
2333         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2334             sc->bge_asicrev == BGE_ASICREV_BCM5762)
2335                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
2336                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
2337         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
2338
2339         /*
2340          * Specify which ring to use for packets that don't match
2341          * any RX rules.
2342          */
2343         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
2344
2345         /*
2346          * Configure number of RX lists. One interrupt distribution
2347          * list, sixteen active lists, one bad frames class.
2348          */
2349         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
2350
2351         /* Inialize RX list placement stats mask. */
2352         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
2353         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
2354
2355         /* Disable host coalescing until we get it set up */
2356         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
2357
2358         /* Poll to make sure it's shut down. */
2359         for (i = 0; i < BGE_TIMEOUT; i++) {
2360                 DELAY(10);
2361                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
2362                         break;
2363         }
2364
2365         if (i == BGE_TIMEOUT) {
2366                 device_printf(sc->bge_dev,
2367                     "host coalescing engine failed to idle\n");
2368                 return (ENXIO);
2369         }
2370
2371         /* Set up host coalescing defaults */
2372         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
2373         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
2374         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
2375         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
2376         if (!(BGE_IS_5705_PLUS(sc))) {
2377                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
2378                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
2379         }
2380         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
2381         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
2382
2383         /* Set up address of statistics block */
2384         if (!(BGE_IS_5705_PLUS(sc))) {
2385                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
2386                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
2387                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
2388                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
2389                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
2390                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
2391                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
2392         }
2393
2394         /* Set up address of status block */
2395         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
2396             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
2397         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
2398             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
2399
2400         /* Set up status block size. */
2401         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2402             sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
2403                 val = BGE_STATBLKSZ_FULL;
2404                 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2405         } else {
2406                 val = BGE_STATBLKSZ_32BYTE;
2407                 bzero(sc->bge_ldata.bge_status_block, 32);
2408         }
2409         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2410             sc->bge_cdata.bge_status_map,
2411             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2412
2413         /* Turn on host coalescing state machine */
2414         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2415
2416         /* Turn on RX BD completion state machine and enable attentions */
2417         CSR_WRITE_4(sc, BGE_RBDC_MODE,
2418             BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
2419
2420         /* Turn on RX list placement state machine */
2421         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2422
2423         /* Turn on RX list selector state machine. */
2424         if (!(BGE_IS_5705_PLUS(sc)))
2425                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2426
2427         /* Turn on DMA, clear stats. */
2428         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
2429             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
2430             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
2431             BGE_MACMODE_FRMHDR_DMA_ENB;
2432
2433         if (sc->bge_flags & BGE_FLAG_TBI)
2434                 val |= BGE_PORTMODE_TBI;
2435         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
2436                 val |= BGE_PORTMODE_GMII;
2437         else
2438                 val |= BGE_PORTMODE_MII;
2439
2440         /* Allow APE to send/receive frames. */
2441         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
2442                 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
2443
2444         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
2445         DELAY(40);
2446
2447         /* Set misc. local control, enable interrupts on attentions */
2448         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2449
2450 #ifdef notdef
2451         /* Assert GPIO pins for PHY reset */
2452         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
2453             BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
2454         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
2455             BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
2456 #endif
2457
2458         /* Turn on DMA completion state machine */
2459         if (!(BGE_IS_5705_PLUS(sc)))
2460                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2461
2462         val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
2463
2464         /* Enable host coalescing bug fix. */
2465         if (BGE_IS_5755_PLUS(sc))
2466                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
2467
2468         /* Request larger DMA burst size to get better performance. */
2469         if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
2470                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
2471
2472         /* Turn on write DMA state machine */
2473         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
2474         DELAY(40);
2475
2476         /* Turn on read DMA state machine */
2477         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
2478
2479         if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
2480                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
2481
2482         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2483             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2484             sc->bge_asicrev == BGE_ASICREV_BCM57780)
2485                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
2486                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
2487                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
2488         if (sc->bge_flags & BGE_FLAG_PCIE)
2489                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2490         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2491                 val |= BGE_RDMAMODE_TSO4_ENABLE;
2492                 if (sc->bge_flags & BGE_FLAG_TSO3 ||
2493                     sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2494                     sc->bge_asicrev == BGE_ASICREV_BCM57780)
2495                         val |= BGE_RDMAMODE_TSO6_ENABLE;
2496         }
2497
2498         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2499             sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2500                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
2501                         BGE_RDMAMODE_H2BNC_VLAN_DET;
2502                 /*
2503                  * Allow multiple outstanding read requests from
2504                  * non-LSO read DMA engine.
2505                  */
2506                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
2507         }
2508
2509         if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2510             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2511             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2512             sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2513             BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) {
2514                 if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
2515                         rdmareg = BGE_RDMA_RSRVCTRL_REG2;
2516                 else
2517                         rdmareg = BGE_RDMA_RSRVCTRL;
2518                 dmactl = CSR_READ_4(sc, rdmareg);
2519                 /*
2520                  * Adjust tx margin to prevent TX data corruption and
2521                  * fix internal FIFO overflow.
2522                  */
2523                 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 ||
2524                     sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2525                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2526                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2527                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2528                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2529                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2530                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2531                 }
2532                 /*
2533                  * Enable fix for read DMA FIFO overruns.
2534                  * The fix is to limit the number of RX BDs
2535                  * the hardware would fetch at a fime.
2536                  */
2537                 CSR_WRITE_4(sc, rdmareg, dmactl |
2538                     BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2539         }
2540
2541         if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2542                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2543                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2544                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2545                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2546         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2547                 /*
2548                  * Allow 4KB burst length reads for non-LSO frames.
2549                  * Enable 512B burst length reads for buffer descriptors.
2550                  */
2551                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2552                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2553                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
2554                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2555         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2556                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2,
2557                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |
2558                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2559                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2560         }
2561
2562         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2563         DELAY(40);
2564
2565         if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
2566                 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) {
2567                         val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);
2568                         if ((val & 0xFFFF) > BGE_FRAMELEN)
2569                                 break;
2570                         if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN)
2571                                 break;
2572                 }
2573                 if (i != BGE_NUM_RDMA_CHANNELS / 2) {
2574                         val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
2575                         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2576                                 val |= BGE_RDMA_TX_LENGTH_WA_5719;
2577                         else
2578                                 val |= BGE_RDMA_TX_LENGTH_WA_5720;
2579                         CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
2580                 }
2581         }
2582
2583         /* Turn on RX data completion state machine */
2584         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2585
2586         /* Turn on RX BD initiator state machine */
2587         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2588
2589         /* Turn on RX data and RX BD initiator state machine */
2590         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2591
2592         /* Turn on Mbuf cluster free state machine */
2593         if (!(BGE_IS_5705_PLUS(sc)))
2594                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2595
2596         /* Turn on send BD completion state machine */
2597         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2598
2599         /* Turn on send data completion state machine */
2600         val = BGE_SDCMODE_ENABLE;
2601         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2602                 val |= BGE_SDCMODE_CDELAY;
2603         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2604
2605         /* Turn on send data initiator state machine */
2606         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2607                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2608                     BGE_SDIMODE_HW_LSO_PRE_DMA);
2609         else
2610                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2611
2612         /* Turn on send BD initiator state machine */
2613         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2614
2615         /* Turn on send BD selector state machine */
2616         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2617
2618         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
2619         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
2620             BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
2621
2622         /* ack/clear link change events */
2623         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2624             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2625             BGE_MACSTAT_LINK_CHANGED);
2626         CSR_WRITE_4(sc, BGE_MI_STS, 0);
2627
2628         /*
2629          * Enable attention when the link has changed state for
2630          * devices that use auto polling.
2631          */
2632         if (sc->bge_flags & BGE_FLAG_TBI) {
2633                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
2634         } else {
2635                 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2636                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
2637                         DELAY(80);
2638                 }
2639                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2640                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
2641                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2642                             BGE_EVTENB_MI_INTERRUPT);
2643         }
2644
2645         /*
2646          * Clear any pending link state attention.
2647          * Otherwise some link state change events may be lost until attention
2648          * is cleared by bge_intr() -> bge_link_upd() sequence.
2649          * It's not necessary on newer BCM chips - perhaps enabling link
2650          * state change attentions implies clearing pending attention.
2651          */
2652         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2653             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2654             BGE_MACSTAT_LINK_CHANGED);
2655
2656         /* Enable link state change attentions. */
2657         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2658
2659         return (0);
2660 }
2661
2662 static const struct bge_revision *
2663 bge_lookup_rev(uint32_t chipid)
2664 {
2665         const struct bge_revision *br;
2666
2667         for (br = bge_revisions; br->br_name != NULL; br++) {
2668                 if (br->br_chipid == chipid)
2669                         return (br);
2670         }
2671
2672         for (br = bge_majorrevs; br->br_name != NULL; br++) {
2673                 if (br->br_chipid == BGE_ASICREV(chipid))
2674                         return (br);
2675         }
2676
2677         return (NULL);
2678 }
2679
2680 static const struct bge_vendor *
2681 bge_lookup_vendor(uint16_t vid)
2682 {
2683         const struct bge_vendor *v;
2684
2685         for (v = bge_vendors; v->v_name != NULL; v++)
2686                 if (v->v_id == vid)
2687                         return (v);
2688
2689         return (NULL);
2690 }
2691
2692 static uint32_t
2693 bge_chipid(device_t dev)
2694 {
2695         uint32_t id;
2696
2697         id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2698             BGE_PCIMISCCTL_ASICREV_SHIFT;
2699         if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
2700                 /*
2701                  * Find the ASCI revision.  Different chips use different
2702                  * registers.
2703                  */
2704                 switch (pci_get_device(dev)) {
2705                 case BCOM_DEVICEID_BCM5717C:
2706                         /* 5717 C0 seems to belong to 5720 line. */
2707                         id = BGE_CHIPID_BCM5720_A0;
2708                         break;
2709                 case BCOM_DEVICEID_BCM5717:
2710                 case BCOM_DEVICEID_BCM5718:
2711                 case BCOM_DEVICEID_BCM5719:
2712                 case BCOM_DEVICEID_BCM5720:
2713                 case BCOM_DEVICEID_BCM5725:
2714                 case BCOM_DEVICEID_BCM5727:
2715                 case BCOM_DEVICEID_BCM5762:
2716                 case BCOM_DEVICEID_BCM57764:
2717                 case BCOM_DEVICEID_BCM57767:
2718                 case BCOM_DEVICEID_BCM57787:
2719                         id = pci_read_config(dev,
2720                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
2721                         break;
2722                 case BCOM_DEVICEID_BCM57761:
2723                 case BCOM_DEVICEID_BCM57762:
2724                 case BCOM_DEVICEID_BCM57765:
2725                 case BCOM_DEVICEID_BCM57766:
2726                 case BCOM_DEVICEID_BCM57781:
2727                 case BCOM_DEVICEID_BCM57782:
2728                 case BCOM_DEVICEID_BCM57785:
2729                 case BCOM_DEVICEID_BCM57786:
2730                 case BCOM_DEVICEID_BCM57791:
2731                 case BCOM_DEVICEID_BCM57795:
2732                         id = pci_read_config(dev,
2733                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
2734                         break;
2735                 default:
2736                         id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
2737                 }
2738         }
2739         return (id);
2740 }
2741
2742 /*
2743  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
2744  * against our list and return its name if we find a match.
2745  *
2746  * Note that since the Broadcom controller contains VPD support, we
2747  * try to get the device name string from the controller itself instead
2748  * of the compiled-in string. It guarantees we'll always announce the
2749  * right product name. We fall back to the compiled-in string when
2750  * VPD is unavailable or corrupt.
2751  */
2752 static int
2753 bge_probe(device_t dev)
2754 {
2755         char buf[96];
2756         char model[64];
2757         const struct bge_revision *br;
2758         const char *pname;
2759         struct bge_softc *sc;
2760         const struct bge_type *t = bge_devs;
2761         const struct bge_vendor *v;
2762         uint32_t id;
2763         uint16_t did, vid;
2764
2765         sc = device_get_softc(dev);
2766         sc->bge_dev = dev;
2767         vid = pci_get_vendor(dev);
2768         did = pci_get_device(dev);
2769         while(t->bge_vid != 0) {
2770                 if ((vid == t->bge_vid) && (did == t->bge_did)) {
2771                         id = bge_chipid(dev);
2772                         br = bge_lookup_rev(id);
2773                         if (bge_has_eaddr(sc) &&
2774                             pci_get_vpd_ident(dev, &pname) == 0)
2775                                 snprintf(model, sizeof(model), "%s", pname);
2776                         else {
2777                                 v = bge_lookup_vendor(vid);
2778                                 snprintf(model, sizeof(model), "%s %s",
2779                                     v != NULL ? v->v_name : "Unknown",
2780                                     br != NULL ? br->br_name :
2781                                     "NetXtreme/NetLink Ethernet Controller");
2782                         }
2783                         snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x",
2784                             model, br != NULL ? "" : "unknown ", id);
2785                         device_set_desc_copy(dev, buf);
2786                         return (BUS_PROBE_DEFAULT);
2787                 }
2788                 t++;
2789         }
2790
2791         return (ENXIO);
2792 }
2793
2794 static void
2795 bge_dma_free(struct bge_softc *sc)
2796 {
2797         int i;
2798
2799         /* Destroy DMA maps for RX buffers. */
2800         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2801                 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2802                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2803                             sc->bge_cdata.bge_rx_std_dmamap[i]);
2804         }
2805         if (sc->bge_cdata.bge_rx_std_sparemap)
2806                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2807                     sc->bge_cdata.bge_rx_std_sparemap);
2808
2809         /* Destroy DMA maps for jumbo RX buffers. */
2810         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2811                 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2812                         bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2813                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2814         }
2815         if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2816                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2817                     sc->bge_cdata.bge_rx_jumbo_sparemap);
2818
2819         /* Destroy DMA maps for TX buffers. */
2820         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2821                 if (sc->bge_cdata.bge_tx_dmamap[i])
2822                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2823                             sc->bge_cdata.bge_tx_dmamap[i]);
2824         }
2825
2826         if (sc->bge_cdata.bge_rx_mtag)
2827                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2828         if (sc->bge_cdata.bge_mtag_jumbo)
2829                 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
2830         if (sc->bge_cdata.bge_tx_mtag)
2831                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2832
2833         /* Destroy standard RX ring. */
2834         if (sc->bge_ldata.bge_rx_std_ring_paddr)
2835                 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2836                     sc->bge_cdata.bge_rx_std_ring_map);
2837         if (sc->bge_ldata.bge_rx_std_ring)
2838                 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2839                     sc->bge_ldata.bge_rx_std_ring,
2840                     sc->bge_cdata.bge_rx_std_ring_map);
2841
2842         if (sc->bge_cdata.bge_rx_std_ring_tag)
2843                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2844
2845         /* Destroy jumbo RX ring. */
2846         if (sc->bge_ldata.bge_rx_jumbo_ring_paddr)
2847                 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2848                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2849
2850         if (sc->bge_ldata.bge_rx_jumbo_ring)
2851                 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2852                     sc->bge_ldata.bge_rx_jumbo_ring,
2853                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2854
2855         if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2856                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2857
2858         /* Destroy RX return ring. */
2859         if (sc->bge_ldata.bge_rx_return_ring_paddr)
2860                 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2861                     sc->bge_cdata.bge_rx_return_ring_map);
2862
2863         if (sc->bge_ldata.bge_rx_return_ring)
2864                 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2865                     sc->bge_ldata.bge_rx_return_ring,
2866                     sc->bge_cdata.bge_rx_return_ring_map);
2867
2868         if (sc->bge_cdata.bge_rx_return_ring_tag)
2869                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2870
2871         /* Destroy TX ring. */
2872         if (sc->bge_ldata.bge_tx_ring_paddr)
2873                 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2874                     sc->bge_cdata.bge_tx_ring_map);
2875
2876         if (sc->bge_ldata.bge_tx_ring)
2877                 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2878                     sc->bge_ldata.bge_tx_ring,
2879                     sc->bge_cdata.bge_tx_ring_map);
2880
2881         if (sc->bge_cdata.bge_tx_ring_tag)
2882                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2883
2884         /* Destroy status block. */
2885         if (sc->bge_ldata.bge_status_block_paddr)
2886                 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2887                     sc->bge_cdata.bge_status_map);
2888
2889         if (sc->bge_ldata.bge_status_block)
2890                 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2891                     sc->bge_ldata.bge_status_block,
2892                     sc->bge_cdata.bge_status_map);
2893
2894         if (sc->bge_cdata.bge_status_tag)
2895                 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2896
2897         /* Destroy statistics block. */
2898         if (sc->bge_ldata.bge_stats_paddr)
2899                 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2900                     sc->bge_cdata.bge_stats_map);
2901
2902         if (sc->bge_ldata.bge_stats)
2903                 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2904                     sc->bge_ldata.bge_stats,
2905                     sc->bge_cdata.bge_stats_map);
2906
2907         if (sc->bge_cdata.bge_stats_tag)
2908                 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2909
2910         if (sc->bge_cdata.bge_buffer_tag)
2911                 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
2912
2913         /* Destroy the parent tag. */
2914         if (sc->bge_cdata.bge_parent_tag)
2915                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2916 }
2917
2918 static int
2919 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
2920     bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
2921     bus_addr_t *paddr, const char *msg)
2922 {
2923         struct bge_dmamap_arg ctx;
2924         int error;
2925
2926         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2927             alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2928             NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
2929         if (error != 0) {
2930                 device_printf(sc->bge_dev,
2931                     "could not create %s dma tag\n", msg);
2932                 return (ENOMEM);
2933         }
2934         /* Allocate DMA'able memory for ring. */
2935         error = bus_dmamem_alloc(*tag, (void **)ring,
2936             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
2937         if (error != 0) {
2938                 device_printf(sc->bge_dev,
2939                     "could not allocate DMA'able memory for %s\n", msg);
2940                 return (ENOMEM);
2941         }
2942         /* Load the address of the ring. */
2943         ctx.bge_busaddr = 0;
2944         error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr,
2945             &ctx, BUS_DMA_NOWAIT);
2946         if (error != 0) {
2947                 device_printf(sc->bge_dev,
2948                     "could not load DMA'able memory for %s\n", msg);
2949                 return (ENOMEM);
2950         }
2951         *paddr = ctx.bge_busaddr;
2952         return (0);
2953 }
2954
2955 static int
2956 bge_dma_alloc(struct bge_softc *sc)
2957 {
2958         bus_addr_t lowaddr;
2959         bus_size_t rxmaxsegsz, sbsz, txsegsz, txmaxsegsz;
2960         int i, error;
2961
2962         lowaddr = BUS_SPACE_MAXADDR;
2963         if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2964                 lowaddr = BGE_DMA_MAXADDR;
2965         /*
2966          * Allocate the parent bus DMA tag appropriate for PCI.
2967          */
2968         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2969             1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2970             NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2971             0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2972         if (error != 0) {
2973                 device_printf(sc->bge_dev,
2974                     "could not allocate parent dma tag\n");
2975                 return (ENOMEM);
2976         }
2977
2978         /* Create tag for standard RX ring. */
2979         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
2980             &sc->bge_cdata.bge_rx_std_ring_tag,
2981             (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
2982             &sc->bge_cdata.bge_rx_std_ring_map,
2983             &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
2984         if (error)
2985                 return (error);
2986
2987         /* Create tag for RX return ring. */
2988         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
2989             &sc->bge_cdata.bge_rx_return_ring_tag,
2990             (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
2991             &sc->bge_cdata.bge_rx_return_ring_map,
2992             &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
2993         if (error)
2994                 return (error);
2995
2996         /* Create tag for TX ring. */
2997         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
2998             &sc->bge_cdata.bge_tx_ring_tag,
2999             (uint8_t **)&sc->bge_ldata.bge_tx_ring,
3000             &sc->bge_cdata.bge_tx_ring_map,
3001             &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
3002         if (error)
3003                 return (error);
3004
3005         /*
3006          * Create tag for status block.
3007          * Because we only use single Tx/Rx/Rx return ring, use
3008          * minimum status block size except BCM5700 AX/BX which
3009          * seems to want to see full status block size regardless
3010          * of configured number of ring.
3011          */
3012         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3013             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
3014                 sbsz = BGE_STATUS_BLK_SZ;
3015         else
3016                 sbsz = 32;
3017         error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
3018             &sc->bge_cdata.bge_status_tag,
3019             (uint8_t **)&sc->bge_ldata.bge_status_block,
3020             &sc->bge_cdata.bge_status_map,
3021             &sc->bge_ldata.bge_status_block_paddr, "status block");
3022         if (error)
3023                 return (error);
3024
3025         /* Create tag for statistics block. */
3026         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
3027             &sc->bge_cdata.bge_stats_tag,
3028             (uint8_t **)&sc->bge_ldata.bge_stats,
3029             &sc->bge_cdata.bge_stats_map,
3030             &sc->bge_ldata.bge_stats_paddr, "statistics block");
3031         if (error)
3032                 return (error);
3033
3034         /* Create tag for jumbo RX ring. */
3035         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3036                 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
3037                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
3038                     (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
3039                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
3040                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
3041                 if (error)
3042                         return (error);
3043         }
3044
3045         /* Create parent tag for buffers. */
3046         if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
3047                 /*
3048                  * XXX
3049                  * watchdog timeout issue was observed on BCM5704 which
3050                  * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge).
3051                  * Both limiting DMA address space to 32bits and flushing
3052                  * mailbox write seem to address the issue.
3053                  */
3054                 if (sc->bge_pcixcap != 0)
3055                         lowaddr = BUS_SPACE_MAXADDR_32BIT;
3056         }
3057         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 1, 0, lowaddr,
3058             BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0,
3059             BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
3060             &sc->bge_cdata.bge_buffer_tag);
3061         if (error != 0) {
3062                 device_printf(sc->bge_dev,
3063                     "could not allocate buffer dma tag\n");
3064                 return (ENOMEM);
3065         }
3066         /* Create tag for Tx mbufs. */
3067         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
3068                 txsegsz = BGE_TSOSEG_SZ;
3069                 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
3070         } else {
3071                 txsegsz = MCLBYTES;
3072                 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
3073         }
3074         error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
3075             0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
3076             txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
3077             &sc->bge_cdata.bge_tx_mtag);
3078
3079         if (error) {
3080                 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
3081                 return (ENOMEM);
3082         }
3083
3084         /* Create tag for Rx mbufs. */
3085         if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
3086                 rxmaxsegsz = MJUM9BYTES;
3087         else
3088                 rxmaxsegsz = MCLBYTES;
3089         error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
3090             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1,
3091             rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
3092
3093         if (error) {
3094                 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
3095                 return (ENOMEM);
3096         }
3097
3098         /* Create DMA maps for RX buffers. */
3099         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3100             &sc->bge_cdata.bge_rx_std_sparemap);
3101         if (error) {
3102                 device_printf(sc->bge_dev,
3103                     "can't create spare DMA map for RX\n");
3104                 return (ENOMEM);
3105         }
3106         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3107                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3108                             &sc->bge_cdata.bge_rx_std_dmamap[i]);
3109                 if (error) {
3110                         device_printf(sc->bge_dev,
3111                             "can't create DMA map for RX\n");
3112                         return (ENOMEM);
3113                 }
3114         }
3115
3116         /* Create DMA maps for TX buffers. */
3117         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3118                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
3119                             &sc->bge_cdata.bge_tx_dmamap[i]);
3120                 if (error) {
3121                         device_printf(sc->bge_dev,
3122                             "can't create DMA map for TX\n");
3123                         return (ENOMEM);
3124                 }
3125         }
3126
3127         /* Create tags for jumbo RX buffers. */
3128         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3129                 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
3130                     1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
3131                     NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
3132                     0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
3133                 if (error) {
3134                         device_printf(sc->bge_dev,
3135                             "could not allocate jumbo dma tag\n");
3136                         return (ENOMEM);
3137                 }
3138                 /* Create DMA maps for jumbo RX buffers. */
3139                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3140                     0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
3141                 if (error) {
3142                         device_printf(sc->bge_dev,
3143                             "can't create spare DMA map for jumbo RX\n");
3144                         return (ENOMEM);
3145                 }
3146                 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
3147                         error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3148                                     0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
3149                         if (error) {
3150                                 device_printf(sc->bge_dev,
3151                                     "can't create DMA map for jumbo RX\n");
3152                                 return (ENOMEM);
3153                         }
3154                 }
3155         }
3156
3157         return (0);
3158 }
3159
3160 /*
3161  * Return true if this device has more than one port.
3162  */
3163 static int
3164 bge_has_multiple_ports(struct bge_softc *sc)
3165 {
3166         device_t dev = sc->bge_dev;
3167         u_int b, d, f, fscan, s;
3168
3169         d = pci_get_domain(dev);
3170         b = pci_get_bus(dev);
3171         s = pci_get_slot(dev);
3172         f = pci_get_function(dev);
3173         for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
3174                 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
3175                         return (1);
3176         return (0);
3177 }
3178
3179 /*
3180  * Return true if MSI can be used with this device.
3181  */
3182 static int
3183 bge_can_use_msi(struct bge_softc *sc)
3184 {
3185         int can_use_msi = 0;
3186
3187         if (sc->bge_msi == 0)
3188                 return (0);
3189
3190         /* Disable MSI for polling(4). */
3191 #ifdef DEVICE_POLLING
3192         return (0);
3193 #endif
3194         switch (sc->bge_asicrev) {
3195         case BGE_ASICREV_BCM5714_A0:
3196         case BGE_ASICREV_BCM5714:
3197                 /*
3198                  * Apparently, MSI doesn't work when these chips are
3199                  * configured in single-port mode.
3200                  */
3201                 if (bge_has_multiple_ports(sc))
3202                         can_use_msi = 1;
3203                 break;
3204         case BGE_ASICREV_BCM5750:
3205                 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
3206                     sc->bge_chiprev != BGE_CHIPREV_5750_BX)
3207                         can_use_msi = 1;
3208                 break;
3209         default:
3210                 if (BGE_IS_575X_PLUS(sc))
3211                         can_use_msi = 1;
3212         }
3213         return (can_use_msi);
3214 }
3215
3216 static int
3217 bge_mbox_reorder(struct bge_softc *sc)
3218 {
3219         /* Lists of PCI bridges that are known to reorder mailbox writes. */
3220         static const struct mbox_reorder {
3221                 const uint16_t vendor;
3222                 const uint16_t device;
3223                 const char *desc;
3224         } mbox_reorder_lists[] = {
3225                 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" },
3226         };
3227         devclass_t pci, pcib;
3228         device_t bus, dev;
3229         int i;
3230
3231         pci = devclass_find("pci");
3232         pcib = devclass_find("pcib");
3233         dev = sc->bge_dev;
3234         bus = device_get_parent(dev);
3235         for (;;) {
3236                 dev = device_get_parent(bus);
3237                 bus = device_get_parent(dev);
3238                 if (device_get_devclass(dev) != pcib)
3239                         break;
3240                 for (i = 0; i < nitems(mbox_reorder_lists); i++) {
3241                         if (pci_get_vendor(dev) ==
3242                             mbox_reorder_lists[i].vendor &&
3243                             pci_get_device(dev) ==
3244                             mbox_reorder_lists[i].device) {
3245                                 device_printf(sc->bge_dev,
3246                                     "enabling MBOX workaround for %s\n",
3247                                     mbox_reorder_lists[i].desc);
3248                                 return (1);
3249                         }
3250                 }
3251                 if (device_get_devclass(bus) != pci)
3252                         break;
3253         }
3254         return (0);
3255 }
3256
3257 static void
3258 bge_devinfo(struct bge_softc *sc)
3259 {
3260         uint32_t cfg, clk;
3261
3262         device_printf(sc->bge_dev,
3263             "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ",
3264             sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev);
3265         if (sc->bge_flags & BGE_FLAG_PCIE)
3266                 printf("PCI-E\n");
3267         else if (sc->bge_flags & BGE_FLAG_PCIX) {
3268                 printf("PCI-X ");
3269                 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3270                 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE)
3271                         clk = 133;
3272                 else {
3273                         clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
3274                         switch (clk) {
3275                         case 0:
3276                                 clk = 33;
3277                                 break;
3278                         case 2:
3279                                 clk = 50;
3280                                 break;
3281                         case 4:
3282                                 clk = 66;
3283                                 break;
3284                         case 6:
3285                                 clk = 100;
3286                                 break;
3287                         case 7:
3288                                 clk = 133;
3289                                 break;
3290                         }
3291                 }
3292                 printf("%u MHz\n", clk);
3293         } else {
3294                 if (sc->bge_pcixcap != 0)
3295                         printf("PCI on PCI-X ");
3296                 else
3297                         printf("PCI ");
3298                 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3299                 if (cfg & BGE_PCISTATE_PCI_BUSSPEED)
3300                         clk = 66;
3301                 else
3302                         clk = 33;
3303                 if (cfg & BGE_PCISTATE_32BIT_BUS)
3304                         printf("%u MHz; 32bit\n", clk);
3305                 else
3306                         printf("%u MHz; 64bit\n", clk);
3307         }
3308 }
3309
3310 static int
3311 bge_attach(device_t dev)
3312 {
3313         if_t ifp;
3314         struct bge_softc *sc;
3315         uint32_t hwcfg = 0, misccfg, pcistate;
3316         u_char eaddr[ETHER_ADDR_LEN];
3317         int capmask, error, reg, rid, trys;
3318
3319         sc = device_get_softc(dev);
3320         sc->bge_dev = dev;
3321
3322         BGE_LOCK_INIT(sc, device_get_nameunit(dev));
3323         TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
3324         callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
3325
3326         pci_enable_busmaster(dev);
3327
3328         /*
3329          * Allocate control/status registers.
3330          */
3331         rid = PCIR_BAR(0);
3332         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3333             RF_ACTIVE);
3334
3335         if (sc->bge_res == NULL) {
3336                 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n");
3337                 error = ENXIO;
3338                 goto fail;
3339         }
3340
3341         /* Save various chip information. */
3342         sc->bge_func_addr = pci_get_function(dev);
3343         sc->bge_chipid = bge_chipid(dev);
3344         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
3345         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
3346
3347         /* Set default PHY address. */
3348         sc->bge_phy_addr = 1;
3349          /*
3350           * PHY address mapping for various devices.
3351           *
3352           *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
3353           * ---------+-------+-------+-------+-------+
3354           * BCM57XX  |   1   |   X   |   X   |   X   |
3355           * BCM5704  |   1   |   X   |   1   |   X   |
3356           * BCM5717  |   1   |   8   |   2   |   9   |
3357           * BCM5719  |   1   |   8   |   2   |   9   |
3358           * BCM5720  |   1   |   8   |   2   |   9   |
3359           *
3360           *          | F2 Cu | F2 Sr | F3 Cu | F3 Sr |
3361           * ---------+-------+-------+-------+-------+
3362           * BCM57XX  |   X   |   X   |   X   |   X   |
3363           * BCM5704  |   X   |   X   |   X   |   X   |
3364           * BCM5717  |   X   |   X   |   X   |   X   |
3365           * BCM5719  |   3   |   10  |   4   |   11  |
3366           * BCM5720  |   X   |   X   |   X   |   X   |
3367           *
3368           * Other addresses may respond but they are not
3369           * IEEE compliant PHYs and should be ignored.
3370           */
3371         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
3372             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3373             sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3374                 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) {
3375                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
3376                             BGE_SGDIGSTS_IS_SERDES)
3377                                 sc->bge_phy_addr = sc->bge_func_addr + 8;
3378                         else
3379                                 sc->bge_phy_addr = sc->bge_func_addr + 1;
3380                 } else {
3381                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
3382                             BGE_CPMU_PHY_STRAP_IS_SERDES)
3383                                 sc->bge_phy_addr = sc->bge_func_addr + 8;
3384                         else
3385                                 sc->bge_phy_addr = sc->bge_func_addr + 1;
3386                 }
3387         }
3388
3389         if (bge_has_eaddr(sc))
3390                 sc->bge_flags |= BGE_FLAG_EADDR;
3391
3392         /* Save chipset family. */
3393         switch (sc->bge_asicrev) {
3394         case BGE_ASICREV_BCM5762:
3395         case BGE_ASICREV_BCM57765:
3396         case BGE_ASICREV_BCM57766:
3397                 sc->bge_flags |= BGE_FLAG_57765_PLUS;
3398                 /* FALLTHROUGH */
3399         case BGE_ASICREV_BCM5717:
3400         case BGE_ASICREV_BCM5719:
3401         case BGE_ASICREV_BCM5720:
3402                 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
3403                     BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
3404                     BGE_FLAG_JUMBO_FRAME;
3405                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3406                     sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3407                         /*
3408                          * Enable work around for DMA engine miscalculation
3409                          * of TXMBUF available space.
3410                          */
3411                         sc->bge_flags |= BGE_FLAG_RDMA_BUG;
3412                         if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3413                             sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3414                                 /* Jumbo frame on BCM5719 A0 does not work. */
3415                                 sc->bge_flags &= ~BGE_FLAG_JUMBO;
3416                         }
3417                 }
3418                 break;
3419         case BGE_ASICREV_BCM5755:
3420         case BGE_ASICREV_BCM5761:
3421         case BGE_ASICREV_BCM5784:
3422         case BGE_ASICREV_BCM5785:
3423         case BGE_ASICREV_BCM5787:
3424         case BGE_ASICREV_BCM57780:
3425                 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
3426                     BGE_FLAG_5705_PLUS;
3427                 break;
3428         case BGE_ASICREV_BCM5700:
3429         case BGE_ASICREV_BCM5701:
3430         case BGE_ASICREV_BCM5703:
3431         case BGE_ASICREV_BCM5704:
3432                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
3433                 break;
3434         case BGE_ASICREV_BCM5714_A0:
3435         case BGE_ASICREV_BCM5780:
3436         case BGE_ASICREV_BCM5714:
3437                 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
3438                 /* FALLTHROUGH */
3439         case BGE_ASICREV_BCM5750:
3440         case BGE_ASICREV_BCM5752:
3441         case BGE_ASICREV_BCM5906:
3442                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
3443                 /* FALLTHROUGH */
3444         case BGE_ASICREV_BCM5705:
3445                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
3446                 break;
3447         }
3448
3449         /* Identify chips with APE processor. */
3450         switch (sc->bge_asicrev) {
3451         case BGE_ASICREV_BCM5717:
3452         case BGE_ASICREV_BCM5719:
3453         case BGE_ASICREV_BCM5720:
3454         case BGE_ASICREV_BCM5761:
3455         case BGE_ASICREV_BCM5762:
3456                 sc->bge_flags |= BGE_FLAG_APE;
3457                 break;
3458         }
3459
3460         /* Chips with APE need BAR2 access for APE registers/memory. */
3461         if ((sc->bge_flags & BGE_FLAG_APE) != 0) {
3462                 rid = PCIR_BAR(2);
3463                 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3464                     RF_ACTIVE);
3465                 if (sc->bge_res2 == NULL) {
3466                         device_printf (sc->bge_dev,
3467                             "couldn't map BAR2 memory\n");
3468                         error = ENXIO;
3469                         goto fail;
3470                 }
3471
3472                 /* Enable APE register/memory access by host driver. */
3473                 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3474                 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
3475                     BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
3476                     BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
3477                 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4);
3478
3479                 bge_ape_lock_init(sc);
3480                 bge_ape_read_fw_ver(sc);
3481         }
3482
3483         /* Add SYSCTLs, requires the chipset family to be set. */
3484         bge_add_sysctls(sc);
3485
3486         /* Identify the chips that use an CPMU. */
3487         if (BGE_IS_5717_PLUS(sc) ||
3488             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3489             sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3490             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
3491             sc->bge_asicrev == BGE_ASICREV_BCM57780)
3492                 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
3493         if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
3494                 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
3495         else
3496                 sc->bge_mi_mode = BGE_MIMODE_BASE;
3497         /* Enable auto polling for BCM570[0-5]. */
3498         if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
3499                 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
3500
3501         /*
3502          * All Broadcom controllers have 4GB boundary DMA bug.
3503          * Whenever an address crosses a multiple of the 4GB boundary
3504          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3505          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3506          * state machine will lockup and cause the device to hang.
3507          */
3508         sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
3509
3510         /* BCM5755 or higher and BCM5906 have short DMA bug. */
3511         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3512                 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
3513
3514         /*
3515          * BCM5719 cannot handle DMA requests for DMA segments that
3516          * have larger than 4KB in size.  However the maximum DMA
3517          * segment size created in DMA tag is 4KB for TSO, so we
3518          * wouldn't encounter the issue here.
3519          */
3520         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
3521                 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG;
3522
3523         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3524         if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
3525                 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
3526                     misccfg == BGE_MISCCFG_BOARD_ID_5788M)
3527                         sc->bge_flags |= BGE_FLAG_5788;
3528         }
3529
3530         capmask = BMSR_DEFCAPMASK;
3531         if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
3532             (misccfg == 0x4000 || misccfg == 0x8000)) ||
3533             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3534             pci_get_vendor(dev) == BCOM_VENDORID &&
3535             (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 ||
3536             pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 ||
3537             pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) ||
3538             (pci_get_vendor(dev) == BCOM_VENDORID &&
3539             (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F ||
3540             pci_get_device(dev) == BCOM_DEVICEID_BCM5753F ||
3541             pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) ||
3542             pci_get_device(dev) == BCOM_DEVICEID_BCM57790 ||
3543             pci_get_device(dev) == BCOM_DEVICEID_BCM57791 ||
3544             pci_get_device(dev) == BCOM_DEVICEID_BCM57795 ||
3545             sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3546                 /* These chips are 10/100 only. */
3547                 capmask &= ~BMSR_EXTSTAT;
3548                 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3549         }
3550
3551         /*
3552          * Some controllers seem to require a special firmware to use
3553          * TSO. But the firmware is not available to FreeBSD and Linux
3554          * claims that the TSO performed by the firmware is slower than
3555          * hardware based TSO. Moreover the firmware based TSO has one
3556          * known bug which can't handle TSO if Ethernet header + IP/TCP
3557          * header is greater than 80 bytes. A workaround for the TSO
3558          * bug exist but it seems it's too expensive than not using
3559          * TSO at all. Some hardwares also have the TSO bug so limit
3560          * the TSO to the controllers that are not affected TSO issues
3561          * (e.g. 5755 or higher).
3562          */
3563         if (BGE_IS_5717_PLUS(sc)) {
3564                 /* BCM5717 requires different TSO configuration. */
3565                 sc->bge_flags |= BGE_FLAG_TSO3;
3566                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3567                     sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3568                         /* TSO on BCM5719 A0 does not work. */
3569                         sc->bge_flags &= ~BGE_FLAG_TSO3;
3570                 }
3571         } else if (BGE_IS_5755_PLUS(sc)) {
3572                 /*
3573                  * BCM5754 and BCM5787 shares the same ASIC id so
3574                  * explicit device id check is required.
3575                  * Due to unknown reason TSO does not work on BCM5755M.
3576                  */
3577                 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
3578                     pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
3579                     pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
3580                         sc->bge_flags |= BGE_FLAG_TSO;
3581         }
3582
3583         /*
3584          * Check if this is a PCI-X or PCI Express device.
3585          */
3586         if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
3587                 /*
3588                  * Found a PCI Express capabilities register, this
3589                  * must be a PCI Express device.
3590                  */
3591                 sc->bge_flags |= BGE_FLAG_PCIE;
3592                 sc->bge_expcap = reg;
3593                 /* Extract supported maximum payload size. */
3594                 sc->bge_mps = pci_read_config(dev, sc->bge_expcap +
3595                     PCIER_DEVICE_CAP, 2);
3596                 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD);
3597                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3598                     sc->bge_asicrev == BGE_ASICREV_BCM5720)
3599                         sc->bge_expmrq = 2048;
3600                 else
3601                         sc->bge_expmrq = 4096;
3602                 pci_set_max_read_req(dev, sc->bge_expmrq);
3603         } else {
3604                 /*
3605                  * Check if the device is in PCI-X Mode.
3606                  * (This bit is not valid on PCI Express controllers.)
3607                  */
3608                 if (pci_find_cap(dev, PCIY_PCIX, &reg) == 0)
3609                         sc->bge_pcixcap = reg;
3610                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
3611                     BGE_PCISTATE_PCI_BUSMODE) == 0)
3612                         sc->bge_flags |= BGE_FLAG_PCIX;
3613         }
3614
3615         /*
3616          * The 40bit DMA bug applies to the 5714/5715 controllers and is
3617          * not actually a MAC controller bug but an issue with the embedded
3618          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
3619          */
3620         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
3621                 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
3622         /*
3623          * Some PCI-X bridges are known to trigger write reordering to
3624          * the mailbox registers. Typical phenomena is watchdog timeouts
3625          * caused by out-of-order TX completions.  Enable workaround for
3626          * PCI-X devices that live behind these bridges.
3627          * Note, PCI-X controllers can run in PCI mode so we can't use
3628          * BGE_FLAG_PCIX flag to detect PCI-X controllers.
3629          */
3630         if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0)
3631                 sc->bge_flags |= BGE_FLAG_MBOX_REORDER;
3632         /*
3633          * Allocate the interrupt, using MSI if possible.  These devices
3634          * support 8 MSI messages, but only the first one is used in
3635          * normal operation.
3636          */
3637         rid = 0;
3638         if (pci_find_cap(sc->bge_dev, PCIY_MSI, &reg) == 0) {
3639                 sc->bge_msicap = reg;
3640                 reg = 1;
3641                 if (bge_can_use_msi(sc) && pci_alloc_msi(dev, &reg) == 0) {
3642                         rid = 1;
3643                         sc->bge_flags |= BGE_FLAG_MSI;
3644                 }
3645         }
3646
3647         /*
3648          * All controllers except BCM5700 supports tagged status but
3649          * we use tagged status only for MSI case on BCM5717. Otherwise
3650          * MSI on BCM5717 does not work.
3651          */
3652 #ifndef DEVICE_POLLING
3653         if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
3654                 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
3655 #endif
3656
3657         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3658             RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
3659
3660         if (sc->bge_irq == NULL) {
3661                 device_printf(sc->bge_dev, "couldn't map interrupt\n");
3662                 error = ENXIO;
3663                 goto fail;
3664         }
3665
3666         bge_devinfo(sc);
3667
3668         sc->bge_asf_mode = 0;
3669         /* No ASF if APE present. */
3670         if ((sc->bge_flags & BGE_FLAG_APE) == 0) {
3671                 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3672                     BGE_SRAM_DATA_SIG_MAGIC)) {
3673                         if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
3674                             BGE_HWCFG_ASF) {
3675                                 sc->bge_asf_mode |= ASF_ENABLE;
3676                                 sc->bge_asf_mode |= ASF_STACKUP;
3677                                 if (BGE_IS_575X_PLUS(sc))
3678                                         sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3679                         }
3680                 }
3681         }
3682
3683         bge_stop_fw(sc);
3684         bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
3685         if (bge_reset(sc)) {
3686                 device_printf(sc->bge_dev, "chip reset failed\n");
3687                 error = ENXIO;
3688                 goto fail;
3689         }
3690
3691         bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
3692         bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
3693
3694         if (bge_chipinit(sc)) {
3695                 device_printf(sc->bge_dev, "chip initialization failed\n");
3696                 error = ENXIO;
3697                 goto fail;
3698         }
3699
3700         error = bge_get_eaddr(sc, eaddr);
3701         if (error) {
3702                 device_printf(sc->bge_dev,
3703                     "failed to read station address\n");
3704                 error = ENXIO;
3705                 goto fail;
3706         }
3707
3708         /* 5705 limits RX return ring to 512 entries. */
3709         if (BGE_IS_5717_PLUS(sc))
3710                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3711         else if (BGE_IS_5705_PLUS(sc))
3712                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3713         else
3714                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3715
3716         if (bge_dma_alloc(sc)) {
3717                 device_printf(sc->bge_dev,
3718                     "failed to allocate DMA resources\n");
3719                 error = ENXIO;
3720                 goto fail;
3721         }
3722
3723         /* Set default tuneable values. */
3724         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3725         sc->bge_rx_coal_ticks = 150;
3726         sc->bge_tx_coal_ticks = 150;
3727         sc->bge_rx_max_coal_bds = 10;
3728         sc->bge_tx_max_coal_bds = 10;
3729
3730         /* Initialize checksum features to use. */
3731         sc->bge_csum_features = BGE_CSUM_FEATURES;
3732         if (sc->bge_forced_udpcsum != 0)
3733                 sc->bge_csum_features |= CSUM_UDP;
3734
3735         /* Set up ifnet structure */
3736         ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
3737         if (ifp == NULL) {
3738                 device_printf(sc->bge_dev, "failed to if_alloc()\n");
3739                 error = ENXIO;
3740                 goto fail;
3741         }
3742         if_setsoftc(ifp, sc);
3743         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3744         if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
3745         if_setioctlfn(ifp, bge_ioctl);
3746         if_setstartfn(ifp, bge_start);
3747         if_setinitfn(ifp, bge_init);
3748         if_setgetcounterfn(ifp, bge_get_counter);
3749         if_setsendqlen(ifp, BGE_TX_RING_CNT - 1);
3750         if_setsendqready(ifp);
3751         if_sethwassist(ifp, sc->bge_csum_features);
3752         if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3753             IFCAP_VLAN_MTU);
3754         if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3755                 if_sethwassistbits(ifp, CSUM_TSO, 0);
3756                 if_setcapabilitiesbit(ifp, IFCAP_TSO4 | IFCAP_VLAN_HWTSO, 0);
3757         }
3758 #ifdef IFCAP_VLAN_HWCSUM
3759         if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0);
3760 #endif
3761         if_setcapenable(ifp, if_getcapabilities(ifp));
3762 #ifdef DEVICE_POLLING
3763         if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
3764 #endif
3765
3766         /*
3767          * 5700 B0 chips do not support checksumming correctly due
3768          * to hardware bugs.
3769          */
3770         if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
3771                 if_setcapabilitiesbit(ifp, 0, IFCAP_HWCSUM);
3772                 if_setcapenablebit(ifp, 0, IFCAP_HWCSUM);
3773                 if_sethwassist(ifp, 0);
3774         }
3775
3776         /*
3777          * Figure out what sort of media we have by checking the
3778          * hardware config word in the first 32k of NIC internal memory,
3779          * or fall back to examining the EEPROM if necessary.
3780          * Note: on some BCM5700 cards, this value appears to be unset.
3781          * If that's the case, we have to rely on identifying the NIC
3782          * by its PCI subsystem ID, as we do below for the SysKonnect
3783          * SK-9D41.
3784          */
3785         if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
3786                 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3787         else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
3788             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3789                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
3790                     sizeof(hwcfg))) {
3791                         device_printf(sc->bge_dev, "failed to read EEPROM\n");
3792                         error = ENXIO;
3793                         goto fail;
3794                 }
3795                 hwcfg = ntohl(hwcfg);
3796         }
3797
3798         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
3799         if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
3800             SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
3801                 if (BGE_IS_5705_PLUS(sc)) {
3802                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
3803                         sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3804                 } else
3805                         sc->bge_flags |= BGE_FLAG_TBI;
3806         }
3807
3808         /* Set various PHY bug flags. */
3809         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
3810             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
3811                 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
3812         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
3813             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
3814                 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
3815         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
3816                 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
3817         if (pci_get_subvendor(dev) == DELL_VENDORID)
3818                 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
3819         if ((BGE_IS_5705_PLUS(sc)) &&
3820             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
3821             sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
3822             sc->bge_asicrev != BGE_ASICREV_BCM57780 &&
3823             !BGE_IS_5717_PLUS(sc)) {
3824                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
3825                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3826                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3827                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
3828                         if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
3829                             pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
3830                                 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
3831                         if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
3832                                 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
3833                 } else
3834                         sc->bge_phy_flags |= BGE_PHY_BER_BUG;
3835         }
3836
3837         /*
3838          * Don't enable Ethernet@WireSpeed for the 5700 or the
3839          * 5705 A0 and A1 chips.
3840          */
3841         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3842             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3843             (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
3844             sc->bge_chipid != BGE_CHIPID_BCM5705_A1)))
3845                 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3846
3847         if (sc->bge_flags & BGE_FLAG_TBI) {
3848                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3849                     bge_ifmedia_sts);
3850                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
3851                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
3852                     0, NULL);
3853                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3854                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3855                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3856         } else {
3857                 /*
3858                  * Do transceiver setup and tell the firmware the
3859                  * driver is down so we can try to get access the
3860                  * probe if ASF is running.  Retry a couple of times
3861                  * if we get a conflict with the ASF firmware accessing
3862                  * the PHY.
3863                  */
3864                 trys = 0;
3865                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3866 again:
3867                 bge_asf_driver_up(sc);
3868
3869                 error = mii_attach(dev, &sc->bge_miibus, ifp,
3870                     (ifm_change_cb_t)bge_ifmedia_upd,
3871                     (ifm_stat_cb_t)bge_ifmedia_sts, capmask, sc->bge_phy_addr,
3872                     MII_OFFSET_ANY, MIIF_DOPAUSE);
3873                 if (error != 0) {
3874                         if (trys++ < 4) {
3875                                 device_printf(sc->bge_dev, "Try again\n");
3876                                 bge_miibus_writereg(sc->bge_dev,
3877                                     sc->bge_phy_addr, MII_BMCR, BMCR_RESET);
3878                                 goto again;
3879                         }
3880                         device_printf(sc->bge_dev, "attaching PHYs failed\n");
3881                         goto fail;
3882                 }
3883
3884                 /*
3885                  * Now tell the firmware we are going up after probing the PHY
3886                  */
3887                 if (sc->bge_asf_mode & ASF_STACKUP)
3888                         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3889         }
3890
3891         /*
3892          * When using the BCM5701 in PCI-X mode, data corruption has
3893          * been observed in the first few bytes of some received packets.
3894          * Aligning the packet buffer in memory eliminates the corruption.
3895          * Unfortunately, this misaligns the packet payloads.  On platforms
3896          * which do not support unaligned accesses, we will realign the
3897          * payloads by copying the received packets.
3898          */
3899         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
3900             sc->bge_flags & BGE_FLAG_PCIX)
3901                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
3902
3903         /*
3904          * Call MI attach routine.
3905          */
3906         ether_ifattach(ifp, eaddr);
3907
3908         /* Tell upper layer we support long frames. */
3909         if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
3910
3911         /*
3912          * Hookup IRQ last.
3913          */
3914         if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
3915                 /* Take advantage of single-shot MSI. */
3916                 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
3917                     ~BGE_MSIMODE_ONE_SHOT_DISABLE);
3918                 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
3919                     taskqueue_thread_enqueue, &sc->bge_tq);
3920                 if (sc->bge_tq == NULL) {
3921                         device_printf(dev, "could not create taskqueue.\n");
3922                         ether_ifdetach(ifp);
3923                         error = ENOMEM;
3924                         goto fail;
3925                 }
3926                 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET,
3927                     "%s taskq", device_get_nameunit(sc->bge_dev));
3928                 if (error != 0) {
3929                         device_printf(dev, "could not start threads.\n");
3930                         ether_ifdetach(ifp);
3931                         goto fail;
3932                 }
3933                 error = bus_setup_intr(dev, sc->bge_irq,
3934                     INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
3935                     &sc->bge_intrhand);
3936         } else
3937                 error = bus_setup_intr(dev, sc->bge_irq,
3938                     INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
3939                     &sc->bge_intrhand);
3940
3941         if (error) {
3942                 ether_ifdetach(ifp);
3943                 device_printf(sc->bge_dev, "couldn't set up irq\n");
3944         }
3945
3946 fail:
3947         if (error)
3948                 bge_detach(dev);
3949         return (error);
3950 }
3951
3952 static int
3953 bge_detach(device_t dev)
3954 {
3955         struct bge_softc *sc;
3956         if_t ifp;
3957
3958         sc = device_get_softc(dev);
3959         ifp = sc->bge_ifp;
3960
3961 #ifdef DEVICE_POLLING
3962         if (if_getcapenable(ifp) & IFCAP_POLLING)
3963                 ether_poll_deregister(ifp);
3964 #endif
3965
3966         if (device_is_attached(dev)) {
3967                 ether_ifdetach(ifp);
3968                 BGE_LOCK(sc);
3969                 bge_stop(sc);
3970                 BGE_UNLOCK(sc);
3971                 callout_drain(&sc->bge_stat_ch);
3972         }
3973
3974         if (sc->bge_tq)
3975                 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3976
3977         if (sc->bge_flags & BGE_FLAG_TBI)
3978                 ifmedia_removeall(&sc->bge_ifmedia);
3979         else if (sc->bge_miibus != NULL) {
3980                 bus_generic_detach(dev);
3981                 device_delete_child(dev, sc->bge_miibus);
3982         }
3983
3984         bge_release_resources(sc);
3985
3986         return (0);
3987 }
3988
3989 static void
3990 bge_release_resources(struct bge_softc *sc)
3991 {
3992         device_t dev;
3993
3994         dev = sc->bge_dev;
3995
3996         if (sc->bge_tq != NULL)
3997                 taskqueue_free(sc->bge_tq);
3998
3999         if (sc->bge_intrhand != NULL)
4000                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
4001
4002         if (sc->bge_irq != NULL) {
4003                 bus_release_resource(dev, SYS_RES_IRQ,
4004                     rman_get_rid(sc->bge_irq), sc->bge_irq);
4005                 pci_release_msi(dev);
4006         }
4007
4008         if (sc->bge_res != NULL)
4009                 bus_release_resource(dev, SYS_RES_MEMORY,
4010                     rman_get_rid(sc->bge_res), sc->bge_res);
4011
4012         if (sc->bge_res2 != NULL)
4013                 bus_release_resource(dev, SYS_RES_MEMORY,
4014                     rman_get_rid(sc->bge_res2), sc->bge_res2);
4015
4016         if (sc->bge_ifp != NULL)
4017                 if_free(sc->bge_ifp);
4018
4019         bge_dma_free(sc);
4020
4021         if (mtx_initialized(&sc->bge_mtx))      /* XXX */
4022                 BGE_LOCK_DESTROY(sc);
4023 }
4024
4025 static int
4026 bge_reset(struct bge_softc *sc)
4027 {
4028         device_t dev;
4029         uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val;
4030         void (*write_op)(struct bge_softc *, int, int);
4031         uint16_t devctl;
4032         int i;
4033
4034         dev = sc->bge_dev;
4035
4036         mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
4037         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4038                 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
4039         mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
4040
4041         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
4042             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
4043                 if (sc->bge_flags & BGE_FLAG_PCIE)
4044                         write_op = bge_writemem_direct;
4045                 else
4046                         write_op = bge_writemem_ind;
4047         } else
4048                 write_op = bge_writereg_ind;
4049
4050         if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
4051             sc->bge_asicrev != BGE_ASICREV_BCM5701) {
4052                 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
4053                 for (i = 0; i < 8000; i++) {
4054                         if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
4055                             BGE_NVRAMSWARB_GNT1)
4056                                 break;
4057                         DELAY(20);
4058                 }
4059                 if (i == 8000) {
4060                         if (bootverbose)
4061                                 device_printf(dev, "NVRAM lock timedout!\n");
4062                 }
4063         }
4064         /* Take APE lock when performing reset. */
4065         bge_ape_lock(sc, BGE_APE_LOCK_GRC);
4066
4067         /* Save some important PCI state. */
4068         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
4069         command = pci_read_config(dev, BGE_PCI_CMD, 4);
4070
4071         pci_write_config(dev, BGE_PCI_MISC_CTL,
4072             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4073             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4074
4075         /* Disable fastboot on controllers that support it. */
4076         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
4077             BGE_IS_5755_PLUS(sc)) {
4078                 if (bootverbose)
4079                         device_printf(dev, "Disabling fastboot\n");
4080                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
4081         }
4082
4083         /*
4084          * Write the magic number to SRAM at offset 0xB50.
4085          * When firmware finishes its initialization it will
4086          * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
4087          */
4088         bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
4089
4090         reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
4091
4092         /* XXX: Broadcom Linux driver. */
4093         if (sc->bge_flags & BGE_FLAG_PCIE) {
4094                 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
4095                     (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) {
4096                         if (CSR_READ_4(sc, 0x7E2C) == 0x60)     /* PCIE 1.0 */
4097                                 CSR_WRITE_4(sc, 0x7E2C, 0x20);
4098                 }
4099                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
4100                         /* Prevent PCIE link training during global reset */
4101                         CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
4102                         reset |= 1 << 29;
4103                 }
4104         }
4105
4106         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4107                 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4108                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
4109                     val | BGE_VCPU_STATUS_DRV_RESET);
4110                 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
4111                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
4112                     val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
4113         }
4114
4115         /*
4116          * Set GPHY Power Down Override to leave GPHY
4117          * powered up in D0 uninitialized.
4118          */
4119         if (BGE_IS_5705_PLUS(sc) &&
4120             (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0)
4121                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
4122
4123         /* Issue global reset */
4124         write_op(sc, BGE_MISC_CFG, reset);
4125
4126         if (sc->bge_flags & BGE_FLAG_PCIE)
4127                 DELAY(100 * 1000);
4128         else
4129                 DELAY(1000);
4130
4131         /* XXX: Broadcom Linux driver. */
4132         if (sc->bge_flags & BGE_FLAG_PCIE) {
4133                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
4134                         DELAY(500000); /* wait for link training to complete */
4135                         val = pci_read_config(dev, 0xC4, 4);
4136                         pci_write_config(dev, 0xC4, val | (1 << 15), 4);
4137                 }
4138                 devctl = pci_read_config(dev,
4139                     sc->bge_expcap + PCIER_DEVICE_CTL, 2);
4140                 /* Clear enable no snoop and disable relaxed ordering. */
4141                 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE |
4142                     PCIEM_CTL_NOSNOOP_ENABLE);
4143                 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL,
4144                     devctl, 2);
4145                 pci_set_max_read_req(dev, sc->bge_expmrq);
4146                 /* Clear error status. */
4147                 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA,
4148                     PCIEM_STA_CORRECTABLE_ERROR |
4149                     PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
4150                     PCIEM_STA_UNSUPPORTED_REQ, 2);
4151         }
4152
4153         /* Reset some of the PCI state that got zapped by reset. */
4154         pci_write_config(dev, BGE_PCI_MISC_CTL,
4155             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4156             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4157         val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
4158         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
4159             (sc->bge_flags & BGE_FLAG_PCIX) != 0)
4160                 val |= BGE_PCISTATE_RETRY_SAME_DMA;
4161         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4162                 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
4163                     BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
4164                     BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
4165         pci_write_config(dev, BGE_PCI_PCISTATE, val, 4);
4166         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
4167         pci_write_config(dev, BGE_PCI_CMD, command, 4);
4168         /*
4169          * Disable PCI-X relaxed ordering to ensure status block update
4170          * comes first then packet buffer DMA. Otherwise driver may
4171          * read stale status block.
4172          */
4173         if (sc->bge_flags & BGE_FLAG_PCIX) {
4174                 devctl = pci_read_config(dev,
4175                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
4176                 devctl &= ~PCIXM_COMMAND_ERO;
4177                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
4178                         devctl &= ~PCIXM_COMMAND_MAX_READ;
4179                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
4180                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4181                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
4182                             PCIXM_COMMAND_MAX_READ);
4183                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
4184                 }
4185                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
4186                     devctl, 2);
4187         }
4188         /* Re-enable MSI, if necessary, and enable the memory arbiter. */
4189         if (BGE_IS_5714_FAMILY(sc)) {
4190                 /* This chip disables MSI on reset. */
4191                 if (sc->bge_flags & BGE_FLAG_MSI) {
4192                         val = pci_read_config(dev,
4193                             sc->bge_msicap + PCIR_MSI_CTRL, 2);
4194                         pci_write_config(dev,
4195                             sc->bge_msicap + PCIR_MSI_CTRL,
4196                             val | PCIM_MSICTRL_MSI_ENABLE, 2);
4197                         val = CSR_READ_4(sc, BGE_MSI_MODE);
4198                         CSR_WRITE_4(sc, BGE_MSI_MODE,
4199                             val | BGE_MSIMODE_ENABLE);
4200                 }
4201                 val = CSR_READ_4(sc, BGE_MARB_MODE);
4202                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
4203         } else
4204                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4205
4206         /* Fix up byte swapping. */
4207         CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
4208
4209         val = CSR_READ_4(sc, BGE_MAC_MODE);
4210         val = (val & ~mac_mode_mask) | mac_mode;
4211         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
4212         DELAY(40);
4213
4214         bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
4215
4216         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4217                 for (i = 0; i < BGE_TIMEOUT; i++) {
4218                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4219                         if (val & BGE_VCPU_STATUS_INIT_DONE)
4220                                 break;
4221                         DELAY(100);
4222                 }
4223                 if (i == BGE_TIMEOUT) {
4224                         device_printf(dev, "reset timed out\n");
4225                         return (1);
4226                 }
4227         } else {
4228                 /*
4229                  * Poll until we see the 1's complement of the magic number.
4230                  * This indicates that the firmware initialization is complete.
4231                  * We expect this to fail if no chip containing the Ethernet
4232                  * address is fitted though.
4233                  */
4234                 for (i = 0; i < BGE_TIMEOUT; i++) {
4235                         DELAY(10);
4236                         val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
4237                         if (val == ~BGE_SRAM_FW_MB_MAGIC)
4238                                 break;
4239                 }
4240
4241                 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
4242                         device_printf(dev,
4243                             "firmware handshake timed out, found 0x%08x\n",
4244                             val);
4245                 /* BCM57765 A0 needs additional time before accessing. */
4246                 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
4247                         DELAY(10 * 1000);       /* XXX */
4248         }
4249
4250         /*
4251          * The 5704 in TBI mode apparently needs some special
4252          * adjustment to insure the SERDES drive level is set
4253          * to 1.2V.
4254          */
4255         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
4256             sc->bge_flags & BGE_FLAG_TBI) {
4257                 val = CSR_READ_4(sc, BGE_SERDES_CFG);
4258                 val = (val & ~0xFFF) | 0x880;
4259                 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
4260         }
4261
4262         /* XXX: Broadcom Linux driver. */
4263         if (sc->bge_flags & BGE_FLAG_PCIE &&
4264             !BGE_IS_5717_PLUS(sc) &&
4265             sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
4266             sc->bge_asicrev != BGE_ASICREV_BCM5785) {
4267                 /* Enable Data FIFO protection. */
4268                 val = CSR_READ_4(sc, 0x7C00);
4269                 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
4270         }
4271
4272         if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
4273                 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
4274                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
4275
4276         return (0);
4277 }
4278
4279 static __inline void
4280 bge_rxreuse_std(struct bge_softc *sc, int i)
4281 {
4282         struct bge_rx_bd *r;
4283
4284         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
4285         r->bge_flags = BGE_RXBDFLAG_END;
4286         r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
4287         r->bge_idx = i;
4288         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4289 }
4290
4291 static __inline void
4292 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
4293 {
4294         struct bge_extrx_bd *r;
4295
4296         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
4297         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
4298         r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
4299         r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
4300         r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
4301         r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
4302         r->bge_idx = i;
4303         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4304 }
4305
4306 /*
4307  * Frame reception handling. This is called if there's a frame
4308  * on the receive return list.
4309  *
4310  * Note: we have to be able to handle two possibilities here:
4311  * 1) the frame is from the jumbo receive ring
4312  * 2) the frame is from the standard receive ring
4313  */
4314
4315 static int
4316 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
4317 {
4318         if_t ifp;
4319         int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
4320         uint16_t rx_cons;
4321
4322         rx_cons = sc->bge_rx_saved_considx;
4323
4324         /* Nothing to do. */
4325         if (rx_cons == rx_prod)
4326                 return (rx_npkts);
4327
4328         ifp = sc->bge_ifp;
4329
4330         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4331             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
4332         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4333             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
4334         if (BGE_IS_JUMBO_CAPABLE(sc) &&
4335             if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
4336             ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))
4337                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4338                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
4339
4340         while (rx_cons != rx_prod) {
4341                 struct bge_rx_bd        *cur_rx;
4342                 uint32_t                rxidx;
4343                 struct mbuf             *m = NULL;
4344                 uint16_t                vlan_tag = 0;
4345                 int                     have_tag = 0;
4346
4347 #ifdef DEVICE_POLLING
4348                 if (if_getcapenable(ifp) & IFCAP_POLLING) {
4349                         if (sc->rxcycles <= 0)
4350                                 break;
4351                         sc->rxcycles--;
4352                 }
4353 #endif
4354
4355                 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
4356
4357                 rxidx = cur_rx->bge_idx;
4358                 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
4359
4360                 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING &&
4361                     cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
4362                         have_tag = 1;
4363                         vlan_tag = cur_rx->bge_vlan_tag;
4364                 }
4365
4366                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
4367                         jumbocnt++;
4368                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
4369                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4370                                 bge_rxreuse_jumbo(sc, rxidx);
4371                                 continue;
4372                         }
4373                         if (bge_newbuf_jumbo(sc, rxidx) != 0) {
4374                                 bge_rxreuse_jumbo(sc, rxidx);
4375                                 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
4376                                 continue;
4377                         }
4378                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4379                 } else {
4380                         stdcnt++;
4381                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
4382                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4383                                 bge_rxreuse_std(sc, rxidx);
4384                                 continue;
4385                         }
4386                         if (bge_newbuf_std(sc, rxidx) != 0) {
4387                                 bge_rxreuse_std(sc, rxidx);
4388                                 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
4389                                 continue;
4390                         }
4391                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4392                 }
4393
4394                 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
4395 #ifndef __NO_STRICT_ALIGNMENT
4396                 /*
4397                  * For architectures with strict alignment we must make sure
4398                  * the payload is aligned.
4399                  */
4400                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
4401                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
4402                             cur_rx->bge_len);
4403                         m->m_data += ETHER_ALIGN;
4404                 }
4405 #endif
4406                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
4407                 m->m_pkthdr.rcvif = ifp;
4408
4409                 if (if_getcapenable(ifp) & IFCAP_RXCSUM)
4410                         bge_rxcsum(sc, cur_rx, m);
4411
4412                 /*
4413                  * If we received a packet with a vlan tag,
4414                  * attach that information to the packet.
4415                  */
4416                 if (have_tag) {
4417                         m->m_pkthdr.ether_vtag = vlan_tag;
4418                         m->m_flags |= M_VLANTAG;
4419                 }
4420
4421                 if (holdlck != 0) {
4422                         BGE_UNLOCK(sc);
4423                         if_input(ifp, m);
4424                         BGE_LOCK(sc);
4425                 } else
4426                         if_input(ifp, m);
4427                 rx_npkts++;
4428
4429                 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4430                         return (rx_npkts);
4431         }
4432
4433         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4434             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
4435         if (stdcnt > 0)
4436                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4437                     sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
4438
4439         if (jumbocnt > 0)
4440                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4441                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
4442
4443         sc->bge_rx_saved_considx = rx_cons;
4444         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
4445         if (stdcnt)
4446                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
4447                     BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT);
4448         if (jumbocnt)
4449                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
4450                     BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT);
4451 #ifdef notyet
4452         /*
4453          * This register wraps very quickly under heavy packet drops.
4454          * If you need correct statistics, you can enable this check.
4455          */
4456         if (BGE_IS_5705_PLUS(sc))
4457                 if_incierrors(ifp, CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS));
4458 #endif
4459         return (rx_npkts);
4460 }
4461
4462 static void
4463 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
4464 {
4465
4466         if (BGE_IS_5717_PLUS(sc)) {
4467                 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
4468                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4469                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4470                                 if ((cur_rx->bge_error_flag &
4471                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
4472                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4473                         }
4474                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
4475                                 m->m_pkthdr.csum_data =
4476                                     cur_rx->bge_tcp_udp_csum;
4477                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4478                                     CSUM_PSEUDO_HDR;
4479                         }
4480                 }
4481         } else {
4482                 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4483                         m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4484                         if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
4485                                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4486                 }
4487                 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
4488                     m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
4489                         m->m_pkthdr.csum_data =
4490                             cur_rx->bge_tcp_udp_csum;
4491                         m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4492                             CSUM_PSEUDO_HDR;
4493                 }
4494         }
4495 }
4496
4497 static void
4498 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
4499 {
4500         struct bge_tx_bd *cur_tx;
4501         if_t ifp;
4502
4503         BGE_LOCK_ASSERT(sc);
4504
4505         /* Nothing to do. */
4506         if (sc->bge_tx_saved_considx == tx_cons)
4507                 return;
4508
4509         ifp = sc->bge_ifp;
4510
4511         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4512             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
4513         /*
4514          * Go through our tx ring and free mbufs for those
4515          * frames that have been sent.
4516          */
4517         while (sc->bge_tx_saved_considx != tx_cons) {
4518                 uint32_t                idx;
4519
4520                 idx = sc->bge_tx_saved_considx;
4521                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
4522                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
4523                         if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
4524                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
4525                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
4526                             sc->bge_cdata.bge_tx_dmamap[idx],
4527                             BUS_DMASYNC_POSTWRITE);
4528                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
4529                             sc->bge_cdata.bge_tx_dmamap[idx]);
4530                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
4531                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
4532                 }
4533                 sc->bge_txcnt--;
4534                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
4535         }
4536
4537         if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
4538         if (sc->bge_txcnt == 0)
4539                 sc->bge_timer = 0;
4540 }
4541
4542 #ifdef DEVICE_POLLING
4543 static int
4544 bge_poll(if_t ifp, enum poll_cmd cmd, int count)
4545 {
4546         struct bge_softc *sc = if_getsoftc(ifp);
4547         uint16_t rx_prod, tx_cons;
4548         uint32_t statusword;
4549         int rx_npkts = 0;
4550
4551         BGE_LOCK(sc);
4552         if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
4553                 BGE_UNLOCK(sc);
4554                 return (rx_npkts);
4555         }
4556
4557         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4558             sc->bge_cdata.bge_status_map,
4559             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4560         /* Fetch updates from the status block. */
4561         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4562         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4563
4564         statusword = sc->bge_ldata.bge_status_block->bge_status;
4565         /* Clear the status so the next pass only sees the changes. */
4566         sc->bge_ldata.bge_status_block->bge_status = 0;
4567
4568         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4569             sc->bge_cdata.bge_status_map,
4570             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4571
4572         /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
4573         if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
4574                 sc->bge_link_evt++;
4575
4576         if (cmd == POLL_AND_CHECK_STATUS)
4577                 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4578                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4579                     sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
4580                         bge_link_upd(sc);
4581
4582         sc->rxcycles = count;
4583         rx_npkts = bge_rxeof(sc, rx_prod, 1);
4584         if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
4585                 BGE_UNLOCK(sc);
4586                 return (rx_npkts);
4587         }
4588         bge_txeof(sc, tx_cons);
4589         if (!if_sendq_empty(ifp))
4590                 bge_start_locked(ifp);
4591
4592         BGE_UNLOCK(sc);
4593         return (rx_npkts);
4594 }
4595 #endif /* DEVICE_POLLING */
4596
4597 static int
4598 bge_msi_intr(void *arg)
4599 {
4600         struct bge_softc *sc;
4601
4602         sc = (struct bge_softc *)arg;
4603         /*
4604          * This interrupt is not shared and controller already
4605          * disabled further interrupt.
4606          */
4607         taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
4608         return (FILTER_HANDLED);
4609 }
4610
4611 static void
4612 bge_intr_task(void *arg, int pending)
4613 {
4614         struct bge_softc *sc;
4615         if_t ifp;
4616         uint32_t status, status_tag;
4617         uint16_t rx_prod, tx_cons;
4618
4619         sc = (struct bge_softc *)arg;
4620         ifp = sc->bge_ifp;
4621
4622         BGE_LOCK(sc);
4623         if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
4624                 BGE_UNLOCK(sc);
4625                 return;
4626         }
4627
4628         /* Get updated status block. */
4629         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4630             sc->bge_cdata.bge_status_map,
4631             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4632
4633         /* Save producer/consumer indices. */
4634         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4635         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4636         status = sc->bge_ldata.bge_status_block->bge_status;
4637         status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
4638         /* Dirty the status flag. */
4639         sc->bge_ldata.bge_status_block->bge_status = 0;
4640         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4641             sc->bge_cdata.bge_status_map,
4642             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4643         if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
4644                 status_tag = 0;
4645
4646         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
4647                 bge_link_upd(sc);
4648
4649         /* Let controller work. */
4650         bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
4651
4652         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
4653             sc->bge_rx_saved_considx != rx_prod) {
4654                 /* Check RX return ring producer/consumer. */
4655                 BGE_UNLOCK(sc);
4656                 bge_rxeof(sc, rx_prod, 0);
4657                 BGE_LOCK(sc);
4658         }
4659         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4660                 /* Check TX ring producer/consumer. */
4661                 bge_txeof(sc, tx_cons);
4662                 if (!if_sendq_empty(ifp))
4663                         bge_start_locked(ifp);
4664         }
4665         BGE_UNLOCK(sc);
4666 }
4667
4668 static void
4669 bge_intr(void *xsc)
4670 {
4671         struct bge_softc *sc;
4672         if_t ifp;
4673         uint32_t statusword;
4674         uint16_t rx_prod, tx_cons;
4675
4676         sc = xsc;
4677
4678         BGE_LOCK(sc);
4679
4680         ifp = sc->bge_ifp;
4681
4682 #ifdef DEVICE_POLLING
4683         if (if_getcapenable(ifp) & IFCAP_POLLING) {
4684                 BGE_UNLOCK(sc);
4685                 return;
4686         }
4687 #endif
4688
4689         /*
4690          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
4691          * disable interrupts by writing nonzero like we used to, since with
4692          * our current organization this just gives complications and
4693          * pessimizations for re-enabling interrupts.  We used to have races
4694          * instead of the necessary complications.  Disabling interrupts
4695          * would just reduce the chance of a status update while we are
4696          * running (by switching to the interrupt-mode coalescence
4697          * parameters), but this chance is already very low so it is more
4698          * efficient to get another interrupt than prevent it.
4699          *
4700          * We do the ack first to ensure another interrupt if there is a
4701          * status update after the ack.  We don't check for the status
4702          * changing later because it is more efficient to get another
4703          * interrupt than prevent it, not quite as above (not checking is
4704          * a smaller optimization than not toggling the interrupt enable,
4705          * since checking doesn't involve PCI accesses and toggling require
4706          * the status check).  So toggling would probably be a pessimization
4707          * even with MSI.  It would only be needed for using a task queue.
4708          */
4709         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4710
4711         /*
4712          * Do the mandatory PCI flush as well as get the link status.
4713          */
4714         statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
4715
4716         /* Make sure the descriptor ring indexes are coherent. */
4717         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4718             sc->bge_cdata.bge_status_map,
4719             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4720         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4721         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4722         sc->bge_ldata.bge_status_block->bge_status = 0;
4723         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4724             sc->bge_cdata.bge_status_map,
4725             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4726
4727         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4728             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4729             statusword || sc->bge_link_evt)
4730                 bge_link_upd(sc);
4731
4732         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4733                 /* Check RX return ring producer/consumer. */
4734                 bge_rxeof(sc, rx_prod, 1);
4735         }
4736
4737         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4738                 /* Check TX ring producer/consumer. */
4739                 bge_txeof(sc, tx_cons);
4740         }
4741
4742         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
4743             !if_sendq_empty(ifp))
4744                 bge_start_locked(ifp);
4745
4746         BGE_UNLOCK(sc);
4747 }
4748
4749 static void
4750 bge_asf_driver_up(struct bge_softc *sc)
4751 {
4752         if (sc->bge_asf_mode & ASF_STACKUP) {
4753                 /* Send ASF heartbeat aprox. every 2s */
4754                 if (sc->bge_asf_count)
4755                         sc->bge_asf_count --;
4756                 else {
4757                         sc->bge_asf_count = 2;
4758                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4759                             BGE_FW_CMD_DRV_ALIVE);
4760                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4761                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
4762                             BGE_FW_HB_TIMEOUT_SEC);
4763                         CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
4764                             CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4765                             BGE_RX_CPU_DRV_EVENT);
4766                 }
4767         }
4768 }
4769
4770 static void
4771 bge_tick(void *xsc)
4772 {
4773         struct bge_softc *sc = xsc;
4774         struct mii_data *mii = NULL;
4775
4776         BGE_LOCK_ASSERT(sc);
4777
4778         /* Synchronize with possible callout reset/stop. */
4779         if (callout_pending(&sc->bge_stat_ch) ||
4780             !callout_active(&sc->bge_stat_ch))
4781                 return;
4782
4783         if (BGE_IS_5705_PLUS(sc))
4784                 bge_stats_update_regs(sc);
4785         else
4786                 bge_stats_update(sc);
4787
4788         /* XXX Add APE heartbeat check here? */
4789
4790         if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4791                 mii = device_get_softc(sc->bge_miibus);
4792                 /*
4793                  * Do not touch PHY if we have link up. This could break
4794                  * IPMI/ASF mode or produce extra input errors
4795                  * (extra errors was reported for bcm5701 & bcm5704).
4796                  */
4797                 if (!sc->bge_link)
4798                         mii_tick(mii);
4799         } else {
4800                 /*
4801                  * Since in TBI mode auto-polling can't be used we should poll
4802                  * link status manually. Here we register pending link event
4803                  * and trigger interrupt.
4804                  */
4805 #ifdef DEVICE_POLLING
4806                 /* In polling mode we poll link state in bge_poll(). */
4807                 if (!(if_getcapenable(sc->bge_ifp) & IFCAP_POLLING))
4808 #endif
4809                 {
4810                 sc->bge_link_evt++;
4811                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4812                     sc->bge_flags & BGE_FLAG_5788)
4813                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4814                 else
4815                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4816                 }
4817         }
4818
4819         bge_asf_driver_up(sc);
4820         bge_watchdog(sc);
4821
4822         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4823 }
4824
4825 static void
4826 bge_stats_update_regs(struct bge_softc *sc)
4827 {
4828         if_t ifp;
4829         struct bge_mac_stats *stats;
4830         uint32_t val;
4831
4832         ifp = sc->bge_ifp;
4833         stats = &sc->bge_mac_stats;
4834
4835         stats->ifHCOutOctets +=
4836             CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4837         stats->etherStatsCollisions +=
4838             CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4839         stats->outXonSent +=
4840             CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4841         stats->outXoffSent +=
4842             CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4843         stats->dot3StatsInternalMacTransmitErrors +=
4844             CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4845         stats->dot3StatsSingleCollisionFrames +=
4846             CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4847         stats->dot3StatsMultipleCollisionFrames +=
4848             CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4849         stats->dot3StatsDeferredTransmissions +=
4850             CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4851         stats->dot3StatsExcessiveCollisions +=
4852             CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4853         stats->dot3StatsLateCollisions +=
4854             CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4855         stats->ifHCOutUcastPkts +=
4856             CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4857         stats->ifHCOutMulticastPkts +=
4858             CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4859         stats->ifHCOutBroadcastPkts +=
4860             CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4861
4862         stats->ifHCInOctets +=
4863             CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4864         stats->etherStatsFragments +=
4865             CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4866         stats->ifHCInUcastPkts +=
4867             CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4868         stats->ifHCInMulticastPkts +=
4869             CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4870         stats->ifHCInBroadcastPkts +=
4871             CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4872         stats->dot3StatsFCSErrors +=
4873             CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4874         stats->dot3StatsAlignmentErrors +=
4875             CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4876         stats->xonPauseFramesReceived +=
4877             CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4878         stats->xoffPauseFramesReceived +=
4879             CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4880         stats->macControlFramesReceived +=
4881             CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4882         stats->xoffStateEntered +=
4883             CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4884         stats->dot3StatsFramesTooLong +=
4885             CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4886         stats->etherStatsJabbers +=
4887             CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4888         stats->etherStatsUndersizePkts +=
4889             CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4890
4891         stats->FramesDroppedDueToFilters +=
4892             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4893         stats->DmaWriteQueueFull +=
4894             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4895         stats->DmaWriteHighPriQueueFull +=
4896             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4897         stats->NoMoreRxBDs +=
4898             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4899         /*
4900          * XXX
4901          * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS
4902          * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0
4903          * includes number of unwanted multicast frames.  This comes
4904          * from silicon bug and known workaround to get rough(not
4905          * exact) counter is to enable interrupt on MBUF low water
4906          * attention.  This can be accomplished by setting
4907          * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE,
4908          * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and
4909          * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL.
4910          * However that change would generate more interrupts and
4911          * there are still possibilities of losing multiple frames
4912          * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling.
4913          * Given that the workaround still would not get correct
4914          * counter I don't think it's worth to implement it.  So
4915          * ignore reading the counter on controllers that have the
4916          * silicon bug.
4917          */
4918         if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
4919             sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
4920             sc->bge_chipid != BGE_CHIPID_BCM5720_A0)
4921                 stats->InputDiscards +=
4922                     CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4923         stats->InputErrors +=
4924             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4925         stats->RecvThresholdHit +=
4926             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4927
4928         if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
4929                 /*
4930                  * If controller transmitted more than BGE_NUM_RDMA_CHANNELS
4931                  * frames, it's safe to disable workaround for DMA engine's
4932                  * miscalculation of TXMBUF space.
4933                  */
4934                 if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts +
4935                     stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) {
4936                         val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
4937                         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
4938                                 val &= ~BGE_RDMA_TX_LENGTH_WA_5719;
4939                         else
4940                                 val &= ~BGE_RDMA_TX_LENGTH_WA_5720;
4941                         CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
4942                         sc->bge_flags &= ~BGE_FLAG_RDMA_BUG;
4943                 }
4944         }
4945 }
4946
4947 static void
4948 bge_stats_clear_regs(struct bge_softc *sc)
4949 {
4950
4951         CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4952         CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4953         CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4954         CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4955         CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4956         CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4957         CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4958         CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4959         CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4960         CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4961         CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4962         CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4963         CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4964
4965         CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4966         CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4967         CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4968         CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4969         CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4970         CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4971         CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4972         CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4973         CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4974         CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4975         CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4976         CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4977         CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4978         CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4979
4980         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4981         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4982         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4983         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4984         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4985         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4986         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4987 }
4988
4989 static void
4990 bge_stats_update(struct bge_softc *sc)
4991 {
4992         if_t ifp;
4993         bus_size_t stats;
4994         uint32_t cnt;   /* current register value */
4995
4996         ifp = sc->bge_ifp;
4997
4998         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
4999
5000 #define READ_STAT(sc, stats, stat) \
5001         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
5002
5003         cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
5004         if_inc_counter(ifp, IFCOUNTER_COLLISIONS, cnt - sc->bge_tx_collisions);
5005         sc->bge_tx_collisions = cnt;
5006
5007         cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo);
5008         if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_nobds);
5009         sc->bge_rx_nobds = cnt;
5010         cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo);
5011         if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_inerrs);
5012         sc->bge_rx_inerrs = cnt;
5013         cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
5014         if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_discards);
5015         sc->bge_rx_discards = cnt;
5016
5017         cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
5018         if_inc_counter(ifp, IFCOUNTER_OERRORS, cnt - sc->bge_tx_discards);
5019         sc->bge_tx_discards = cnt;
5020
5021 #undef  READ_STAT
5022 }
5023
5024 /*
5025  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
5026  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
5027  * but when such padded frames employ the bge IP/TCP checksum offload,
5028  * the hardware checksum assist gives incorrect results (possibly
5029  * from incorporating its own padding into the UDP/TCP checksum; who knows).
5030  * If we pad such runts with zeros, the onboard checksum comes out correct.
5031  */
5032 static __inline int
5033 bge_cksum_pad(struct mbuf *m)
5034 {
5035         int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
5036         struct mbuf *last;
5037
5038         /* If there's only the packet-header and we can pad there, use it. */
5039         if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
5040             M_TRAILINGSPACE(m) >= padlen) {
5041                 last = m;
5042         } else {
5043                 /*
5044                  * Walk packet chain to find last mbuf. We will either
5045                  * pad there, or append a new mbuf and pad it.
5046                  */
5047                 for (last = m; last->m_next != NULL; last = last->m_next);
5048                 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
5049                         /* Allocate new empty mbuf, pad it. Compact later. */
5050                         struct mbuf *n;
5051
5052                         MGET(n, M_NOWAIT, MT_DATA);
5053                         if (n == NULL)
5054                                 return (ENOBUFS);
5055                         n->m_len = 0;
5056                         last->m_next = n;
5057                         last = n;
5058                 }
5059         }
5060
5061         /* Now zero the pad area, to avoid the bge cksum-assist bug. */
5062         memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
5063         last->m_len += padlen;
5064         m->m_pkthdr.len += padlen;
5065
5066         return (0);
5067 }
5068
5069 static struct mbuf *
5070 bge_check_short_dma(struct mbuf *m)
5071 {
5072         struct mbuf *n;
5073         int found;
5074
5075         /*
5076          * If device receive two back-to-back send BDs with less than
5077          * or equal to 8 total bytes then the device may hang.  The two
5078          * back-to-back send BDs must in the same frame for this failure
5079          * to occur.  Scan mbuf chains and see whether two back-to-back
5080          * send BDs are there. If this is the case, allocate new mbuf
5081          * and copy the frame to workaround the silicon bug.
5082          */
5083         for (n = m, found = 0; n != NULL; n = n->m_next) {
5084                 if (n->m_len < 8) {
5085                         found++;
5086                         if (found > 1)
5087                                 break;
5088                         continue;
5089                 }
5090                 found = 0;
5091         }
5092
5093         if (found > 1) {
5094                 n = m_defrag(m, M_NOWAIT);
5095                 if (n == NULL)
5096                         m_freem(m);
5097         } else
5098                 n = m;
5099         return (n);
5100 }
5101
5102 static struct mbuf *
5103 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
5104     uint16_t *flags)
5105 {
5106         struct ip *ip;
5107         struct tcphdr *tcp;
5108         struct mbuf *n;
5109         uint16_t hlen;
5110         uint32_t poff;
5111
5112         if (M_WRITABLE(m) == 0) {
5113                 /* Get a writable copy. */
5114                 n = m_dup(m, M_NOWAIT);
5115                 m_freem(m);
5116                 if (n == NULL)
5117                         return (NULL);
5118                 m = n;
5119         }
5120         m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
5121         if (m == NULL)
5122                 return (NULL);
5123         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5124         poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
5125         m = m_pullup(m, poff + sizeof(struct tcphdr));
5126         if (m == NULL)
5127                 return (NULL);
5128         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5129         m = m_pullup(m, poff + (tcp->th_off << 2));
5130         if (m == NULL)
5131                 return (NULL);
5132         /*
5133          * It seems controller doesn't modify IP length and TCP pseudo
5134          * checksum. These checksum computed by upper stack should be 0.
5135          */
5136         *mss = m->m_pkthdr.tso_segsz;
5137         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5138         ip->ip_sum = 0;
5139         ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
5140         /* Clear pseudo checksum computed by TCP stack. */
5141         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5142         tcp->th_sum = 0;
5143         /*
5144          * Broadcom controllers uses different descriptor format for
5145          * TSO depending on ASIC revision. Due to TSO-capable firmware
5146          * license issue and lower performance of firmware based TSO
5147          * we only support hardware based TSO.
5148          */
5149         /* Calculate header length, incl. TCP/IP options, in 32 bit units. */
5150         hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
5151         if (sc->bge_flags & BGE_FLAG_TSO3) {
5152                 /*
5153                  * For BCM5717 and newer controllers, hardware based TSO
5154                  * uses the 14 lower bits of the bge_mss field to store the
5155                  * MSS and the upper 2 bits to store the lowest 2 bits of
5156                  * the IP/TCP header length.  The upper 6 bits of the header
5157                  * length are stored in the bge_flags[14:10,4] field.  Jumbo
5158                  * frames are supported.
5159                  */
5160                 *mss |= ((hlen & 0x3) << 14);
5161                 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2);
5162         } else {
5163                 /*
5164                  * For BCM5755 and newer controllers, hardware based TSO uses
5165                  * the lower 11 bits to store the MSS and the upper 5 bits to
5166                  * store the IP/TCP header length. Jumbo frames are not
5167                  * supported.
5168                  */
5169                 *mss |= (hlen << 11);
5170         }
5171         return (m);
5172 }
5173
5174 /*
5175  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
5176  * pointers to descriptors.
5177  */
5178 static int
5179 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
5180 {
5181         bus_dma_segment_t       segs[BGE_NSEG_NEW];
5182         bus_dmamap_t            map;
5183         struct bge_tx_bd        *d;
5184         struct mbuf             *m = *m_head;
5185         uint32_t                idx = *txidx;
5186         uint16_t                csum_flags, mss, vlan_tag;
5187         int                     nsegs, i, error;
5188
5189         csum_flags = 0;
5190         mss = 0;
5191         vlan_tag = 0;
5192         if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
5193             m->m_next != NULL) {
5194                 *m_head = bge_check_short_dma(m);
5195                 if (*m_head == NULL)
5196                         return (ENOBUFS);
5197                 m = *m_head;
5198         }
5199         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5200                 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
5201                 if (*m_head == NULL)
5202                         return (ENOBUFS);
5203                 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
5204                     BGE_TXBDFLAG_CPU_POST_DMA;
5205         } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
5206                 if (m->m_pkthdr.csum_flags & CSUM_IP)
5207                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
5208                 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
5209                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
5210                         if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
5211                             (error = bge_cksum_pad(m)) != 0) {
5212                                 m_freem(m);
5213                                 *m_head = NULL;
5214                                 return (error);
5215                         }
5216                 }
5217         }
5218
5219         if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
5220                 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
5221                     m->m_pkthdr.len > ETHER_MAX_LEN)
5222                         csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME;
5223                 if (sc->bge_forced_collapse > 0 &&
5224                     (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
5225                         /*
5226                          * Forcedly collapse mbuf chains to overcome hardware
5227                          * limitation which only support a single outstanding
5228                          * DMA read operation.
5229                          */
5230                         if (sc->bge_forced_collapse == 1)
5231                                 m = m_defrag(m, M_NOWAIT);
5232                         else
5233                                 m = m_collapse(m, M_NOWAIT,
5234                                     sc->bge_forced_collapse);
5235                         if (m == NULL)
5236                                 m = *m_head;
5237                         *m_head = m;
5238                 }
5239         }
5240
5241         map = sc->bge_cdata.bge_tx_dmamap[idx];
5242         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
5243             &nsegs, BUS_DMA_NOWAIT);
5244         if (error == EFBIG) {
5245                 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW);
5246                 if (m == NULL) {
5247                         m_freem(*m_head);
5248                         *m_head = NULL;
5249                         return (ENOBUFS);
5250                 }
5251                 *m_head = m;
5252                 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
5253                     m, segs, &nsegs, BUS_DMA_NOWAIT);
5254                 if (error) {
5255                         m_freem(m);
5256                         *m_head = NULL;
5257                         return (error);
5258                 }
5259         } else if (error != 0)
5260                 return (error);
5261
5262         /* Check if we have enough free send BDs. */
5263         if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
5264                 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5265                 return (ENOBUFS);
5266         }
5267
5268         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
5269
5270         if (m->m_flags & M_VLANTAG) {
5271                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
5272                 vlan_tag = m->m_pkthdr.ether_vtag;
5273         }
5274
5275         if (sc->bge_asicrev == BGE_ASICREV_BCM5762 &&
5276             (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5277                 /*
5278                  * 5725 family of devices corrupts TSO packets when TSO DMA
5279                  * buffers cross into regions which are within MSS bytes of
5280                  * a 4GB boundary.  If we encounter the condition, drop the
5281                  * packet.
5282                  */
5283                 for (i = 0; ; i++) {
5284                         d = &sc->bge_ldata.bge_tx_ring[idx];
5285                         d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5286                         d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5287                         d->bge_len = segs[i].ds_len;
5288                         if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss <
5289                             d->bge_addr.bge_addr_lo)
5290                                 break;
5291                         d->bge_flags = csum_flags;
5292                         d->bge_vlan_tag = vlan_tag;
5293                         d->bge_mss = mss;
5294                         if (i == nsegs - 1)
5295                                 break;
5296                         BGE_INC(idx, BGE_TX_RING_CNT);
5297                 }
5298                 if (i != nsegs - 1) {
5299                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map,
5300                             BUS_DMASYNC_POSTWRITE);
5301                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5302                         m_freem(*m_head);
5303                         *m_head = NULL;
5304                         return (EIO);
5305                 }
5306         } else {
5307                 for (i = 0; ; i++) {
5308                         d = &sc->bge_ldata.bge_tx_ring[idx];
5309                         d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5310                         d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5311                         d->bge_len = segs[i].ds_len;
5312                         d->bge_flags = csum_flags;
5313                         d->bge_vlan_tag = vlan_tag;
5314                         d->bge_mss = mss;
5315                         if (i == nsegs - 1)
5316                                 break;
5317                         BGE_INC(idx, BGE_TX_RING_CNT);
5318                 }
5319         }
5320
5321         /* Mark the last segment as end of packet... */
5322         d->bge_flags |= BGE_TXBDFLAG_END;
5323
5324         /*
5325          * Insure that the map for this transmission
5326          * is placed at the array index of the last descriptor
5327          * in this chain.
5328          */
5329         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
5330         sc->bge_cdata.bge_tx_dmamap[idx] = map;
5331         sc->bge_cdata.bge_tx_chain[idx] = m;
5332         sc->bge_txcnt += nsegs;
5333
5334         BGE_INC(idx, BGE_TX_RING_CNT);
5335         *txidx = idx;
5336
5337         return (0);
5338 }
5339
5340 /*
5341  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5342  * to the mbuf data regions directly in the transmit descriptors.
5343  */
5344 static void
5345 bge_start_locked(if_t ifp)
5346 {
5347         struct bge_softc *sc;
5348         struct mbuf *m_head;
5349         uint32_t prodidx;
5350         int count;
5351
5352         sc = if_getsoftc(ifp);
5353         BGE_LOCK_ASSERT(sc);
5354
5355         if (!sc->bge_link ||
5356             (if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
5357             IFF_DRV_RUNNING)
5358                 return;
5359
5360         prodidx = sc->bge_tx_prodidx;
5361
5362         for (count = 0; !if_sendq_empty(ifp);) {
5363                 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
5364                         if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5365                         break;
5366                 }
5367                 m_head = if_dequeue(ifp);
5368                 if (m_head == NULL)
5369                         break;
5370
5371                 /*
5372                  * Pack the data into the transmit ring. If we
5373                  * don't have room, set the OACTIVE flag and wait
5374                  * for the NIC to drain the ring.
5375                  */
5376                 if (bge_encap(sc, &m_head, &prodidx)) {
5377                         if (m_head == NULL)
5378                                 break;
5379                         if_sendq_prepend(ifp, m_head);
5380                         if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5381                         break;
5382                 }
5383                 ++count;
5384
5385                 /*
5386                  * If there's a BPF listener, bounce a copy of this frame
5387                  * to him.
5388                  */
5389                 if_bpfmtap(ifp, m_head);
5390         }
5391
5392         if (count > 0) {
5393                 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
5394                     sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
5395                 /* Transmit. */
5396                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5397                 /* 5700 b2 errata */
5398                 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
5399                         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5400
5401                 sc->bge_tx_prodidx = prodidx;
5402
5403                 /*
5404                  * Set a timeout in case the chip goes out to lunch.
5405                  */
5406                 sc->bge_timer = BGE_TX_TIMEOUT;
5407         }
5408 }
5409
5410 /*
5411  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5412  * to the mbuf data regions directly in the transmit descriptors.
5413  */
5414 static void
5415 bge_start(if_t ifp)
5416 {
5417         struct bge_softc *sc;
5418
5419         sc = if_getsoftc(ifp);
5420         BGE_LOCK(sc);
5421         bge_start_locked(ifp);
5422         BGE_UNLOCK(sc);
5423 }
5424
5425 static void
5426 bge_init_locked(struct bge_softc *sc)
5427 {
5428         if_t ifp;
5429         uint16_t *m;
5430         uint32_t mode;
5431
5432         BGE_LOCK_ASSERT(sc);
5433
5434         ifp = sc->bge_ifp;
5435
5436         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
5437                 return;
5438
5439         /* Cancel pending I/O and flush buffers. */
5440         bge_stop(sc);
5441
5442         bge_stop_fw(sc);
5443         bge_sig_pre_reset(sc, BGE_RESET_START);
5444         bge_reset(sc);
5445         bge_sig_legacy(sc, BGE_RESET_START);
5446         bge_sig_post_reset(sc, BGE_RESET_START);
5447
5448         bge_chipinit(sc);
5449
5450         /*
5451          * Init the various state machines, ring
5452          * control blocks and firmware.
5453          */
5454         if (bge_blockinit(sc)) {
5455                 device_printf(sc->bge_dev, "initialization failure\n");
5456                 return;
5457         }
5458
5459         ifp = sc->bge_ifp;
5460
5461         /* Specify MTU. */
5462         CSR_WRITE_4(sc, BGE_RX_MTU, if_getmtu(ifp) +
5463             ETHER_HDR_LEN + ETHER_CRC_LEN +
5464             (if_getcapenable(ifp) & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
5465
5466         /* Load our MAC address. */
5467         m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
5468         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
5469         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
5470
5471         /* Program promiscuous mode. */
5472         bge_setpromisc(sc);
5473
5474         /* Program multicast filter. */
5475         bge_setmulti(sc);
5476
5477         /* Program VLAN tag stripping. */
5478         bge_setvlan(sc);
5479
5480         /* Override UDP checksum offloading. */
5481         if (sc->bge_forced_udpcsum == 0)
5482                 sc->bge_csum_features &= ~CSUM_UDP;
5483         else
5484                 sc->bge_csum_features |= CSUM_UDP;
5485         if (if_getcapabilities(ifp) & IFCAP_TXCSUM &&
5486             if_getcapenable(ifp) & IFCAP_TXCSUM) {
5487                 if_sethwassistbits(ifp, 0, (BGE_CSUM_FEATURES | CSUM_UDP));
5488                 if_sethwassistbits(ifp, sc->bge_csum_features, 0);
5489         }
5490
5491         /* Init RX ring. */
5492         if (bge_init_rx_ring_std(sc) != 0) {
5493                 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
5494                 bge_stop(sc);
5495                 return;
5496         }
5497
5498         /*
5499          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
5500          * memory to insure that the chip has in fact read the first
5501          * entry of the ring.
5502          */
5503         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
5504                 uint32_t                v, i;
5505                 for (i = 0; i < 10; i++) {
5506                         DELAY(20);
5507                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
5508                         if (v == (MCLBYTES - ETHER_ALIGN))
5509                                 break;
5510                 }
5511                 if (i == 10)
5512                         device_printf (sc->bge_dev,
5513                             "5705 A0 chip failed to load RX ring\n");
5514         }
5515
5516         /* Init jumbo RX ring. */
5517         if (BGE_IS_JUMBO_CAPABLE(sc) &&
5518             if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
5519             ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) {
5520                 if (bge_init_rx_ring_jumbo(sc) != 0) {
5521                         device_printf(sc->bge_dev,
5522                             "no memory for jumbo Rx buffers.\n");
5523                         bge_stop(sc);
5524                         return;
5525                 }
5526         }
5527
5528         /* Init our RX return ring index. */
5529         sc->bge_rx_saved_considx = 0;
5530
5531         /* Init our RX/TX stat counters. */
5532         sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
5533
5534         /* Init TX ring. */
5535         bge_init_tx_ring(sc);
5536
5537         /* Enable TX MAC state machine lockup fix. */
5538         mode = CSR_READ_4(sc, BGE_TX_MODE);
5539         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
5540                 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
5541         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
5542             sc->bge_asicrev == BGE_ASICREV_BCM5762) {
5543                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5544                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
5545                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5546         }
5547         /* Turn on transmitter. */
5548         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
5549         DELAY(100);
5550
5551         /* Turn on receiver. */
5552         mode = CSR_READ_4(sc, BGE_RX_MODE);
5553         if (BGE_IS_5755_PLUS(sc))
5554                 mode |= BGE_RXMODE_IPV6_ENABLE;
5555         if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
5556                 mode |= BGE_RXMODE_IPV4_FRAG_FIX;
5557         CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
5558         DELAY(10);
5559
5560         /*
5561          * Set the number of good frames to receive after RX MBUF
5562          * Low Watermark has been reached. After the RX MAC receives
5563          * this number of frames, it will drop subsequent incoming
5564          * frames until the MBUF High Watermark is reached.
5565          */
5566         if (BGE_IS_57765_PLUS(sc))
5567                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
5568         else
5569                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
5570
5571         /* Clear MAC statistics. */
5572         if (BGE_IS_5705_PLUS(sc))
5573                 bge_stats_clear_regs(sc);
5574
5575         /* Tell firmware we're alive. */
5576         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5577
5578 #ifdef DEVICE_POLLING
5579         /* Disable interrupts if we are polling. */
5580         if (if_getcapenable(ifp) & IFCAP_POLLING) {
5581                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5582                     BGE_PCIMISCCTL_MASK_PCI_INTR);
5583                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5584         } else
5585 #endif
5586
5587         /* Enable host interrupts. */
5588         {
5589         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
5590         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5591         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5592         }
5593
5594         if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
5595         if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
5596
5597         bge_ifmedia_upd_locked(ifp);
5598
5599         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
5600 }
5601
5602 static void
5603 bge_init(void *xsc)
5604 {
5605         struct bge_softc *sc = xsc;
5606
5607         BGE_LOCK(sc);
5608         bge_init_locked(sc);
5609         BGE_UNLOCK(sc);
5610 }
5611
5612 /*
5613  * Set media options.
5614  */
5615 static int
5616 bge_ifmedia_upd(if_t ifp)
5617 {
5618         struct bge_softc *sc = if_getsoftc(ifp);
5619         int res;
5620
5621         BGE_LOCK(sc);
5622         res = bge_ifmedia_upd_locked(ifp);
5623         BGE_UNLOCK(sc);
5624
5625         return (res);
5626 }
5627
5628 static int
5629 bge_ifmedia_upd_locked(if_t ifp)
5630 {
5631         struct bge_softc *sc = if_getsoftc(ifp);
5632         struct mii_data *mii;
5633         struct mii_softc *miisc;
5634         struct ifmedia *ifm;
5635
5636         BGE_LOCK_ASSERT(sc);
5637
5638         ifm = &sc->bge_ifmedia;
5639
5640         /* If this is a 1000baseX NIC, enable the TBI port. */
5641         if (sc->bge_flags & BGE_FLAG_TBI) {
5642                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
5643                         return (EINVAL);
5644                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
5645                 case IFM_AUTO:
5646                         /*
5647                          * The BCM5704 ASIC appears to have a special
5648                          * mechanism for programming the autoneg
5649                          * advertisement registers in TBI mode.
5650                          */
5651                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
5652                                 uint32_t sgdig;
5653                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5654                                 if (sgdig & BGE_SGDIGSTS_DONE) {
5655                                         CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5656                                         sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5657                                         sgdig |= BGE_SGDIGCFG_AUTO |
5658                                             BGE_SGDIGCFG_PAUSE_CAP |
5659                                             BGE_SGDIGCFG_ASYM_PAUSE;
5660                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG,
5661                                             sgdig | BGE_SGDIGCFG_SEND);
5662                                         DELAY(5);
5663                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
5664                                 }
5665                         }
5666                         break;
5667                 case IFM_1000_SX:
5668                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
5669                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
5670                                     BGE_MACMODE_HALF_DUPLEX);
5671                         } else {
5672                                 BGE_SETBIT(sc, BGE_MAC_MODE,
5673                                     BGE_MACMODE_HALF_DUPLEX);
5674                         }
5675                         DELAY(40);
5676                         break;
5677                 default:
5678                         return (EINVAL);
5679                 }
5680                 return (0);
5681         }
5682
5683         sc->bge_link_evt++;
5684         mii = device_get_softc(sc->bge_miibus);
5685         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
5686                 PHY_RESET(miisc);
5687         mii_mediachg(mii);
5688
5689         /*
5690          * Force an interrupt so that we will call bge_link_upd
5691          * if needed and clear any pending link state attention.
5692          * Without this we are not getting any further interrupts
5693          * for link state changes and thus will not UP the link and
5694          * not be able to send in bge_start_locked. The only
5695          * way to get things working was to receive a packet and
5696          * get an RX intr.
5697          * bge_tick should help for fiber cards and we might not
5698          * need to do this here if BGE_FLAG_TBI is set but as
5699          * we poll for fiber anyway it should not harm.
5700          */
5701         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
5702             sc->bge_flags & BGE_FLAG_5788)
5703                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
5704         else
5705                 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
5706
5707         return (0);
5708 }
5709
5710 /*
5711  * Report current media status.
5712  */
5713 static void
5714 bge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
5715 {
5716         struct bge_softc *sc = if_getsoftc(ifp);
5717         struct mii_data *mii;
5718
5719         BGE_LOCK(sc);
5720
5721         if ((if_getflags(ifp) & IFF_UP) == 0) {
5722                 BGE_UNLOCK(sc);
5723                 return;
5724         }
5725         if (sc->bge_flags & BGE_FLAG_TBI) {
5726                 ifmr->ifm_status = IFM_AVALID;
5727                 ifmr->ifm_active = IFM_ETHER;
5728                 if (CSR_READ_4(sc, BGE_MAC_STS) &
5729                     BGE_MACSTAT_TBI_PCS_SYNCHED)
5730                         ifmr->ifm_status |= IFM_ACTIVE;
5731                 else {
5732                         ifmr->ifm_active |= IFM_NONE;
5733                         BGE_UNLOCK(sc);
5734                         return;
5735                 }
5736                 ifmr->ifm_active |= IFM_1000_SX;
5737                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5738                         ifmr->ifm_active |= IFM_HDX;
5739                 else
5740                         ifmr->ifm_active |= IFM_FDX;
5741                 BGE_UNLOCK(sc);
5742                 return;
5743         }
5744
5745         mii = device_get_softc(sc->bge_miibus);
5746         mii_pollstat(mii);
5747         ifmr->ifm_active = mii->mii_media_active;
5748         ifmr->ifm_status = mii->mii_media_status;
5749
5750         BGE_UNLOCK(sc);
5751 }
5752
5753 static int
5754 bge_ioctl(if_t ifp, u_long command, caddr_t data)
5755 {
5756         struct bge_softc *sc = if_getsoftc(ifp);
5757         struct ifreq *ifr = (struct ifreq *) data;
5758         struct mii_data *mii;
5759         int flags, mask, error = 0;
5760
5761         switch (command) {
5762         case SIOCSIFMTU:
5763                 if (BGE_IS_JUMBO_CAPABLE(sc) ||
5764                     (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
5765                         if (ifr->ifr_mtu < ETHERMIN ||
5766                             ifr->ifr_mtu > BGE_JUMBO_MTU) {
5767                                 error = EINVAL;
5768                                 break;
5769                         }
5770                 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) {
5771                         error = EINVAL;
5772                         break;
5773                 }
5774                 BGE_LOCK(sc);
5775                 if (if_getmtu(ifp) != ifr->ifr_mtu) {
5776                         if_setmtu(ifp, ifr->ifr_mtu);
5777                         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5778                                 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5779                                 bge_init_locked(sc);
5780                         }
5781                 }
5782                 BGE_UNLOCK(sc);
5783                 break;
5784         case SIOCSIFFLAGS:
5785                 BGE_LOCK(sc);
5786                 if (if_getflags(ifp) & IFF_UP) {
5787                         /*
5788                          * If only the state of the PROMISC flag changed,
5789                          * then just use the 'set promisc mode' command
5790                          * instead of reinitializing the entire NIC. Doing
5791                          * a full re-init means reloading the firmware and
5792                          * waiting for it to start up, which may take a
5793                          * second or two.  Similarly for ALLMULTI.
5794                          */
5795                         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5796                                 flags = if_getflags(ifp) ^ sc->bge_if_flags;
5797                                 if (flags & IFF_PROMISC)
5798                                         bge_setpromisc(sc);
5799                                 if (flags & IFF_ALLMULTI)
5800                                         bge_setmulti(sc);
5801                         } else
5802                                 bge_init_locked(sc);
5803                 } else {
5804                         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5805                                 bge_stop(sc);
5806                         }
5807                 }
5808                 sc->bge_if_flags = if_getflags(ifp);
5809                 BGE_UNLOCK(sc);
5810                 error = 0;
5811                 break;
5812         case SIOCADDMULTI:
5813         case SIOCDELMULTI:
5814                 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5815                         BGE_LOCK(sc);
5816                         bge_setmulti(sc);
5817                         BGE_UNLOCK(sc);
5818                         error = 0;
5819                 }
5820                 break;
5821         case SIOCSIFMEDIA:
5822         case SIOCGIFMEDIA:
5823                 if (sc->bge_flags & BGE_FLAG_TBI) {
5824                         error = ifmedia_ioctl(ifp, ifr,
5825                             &sc->bge_ifmedia, command);
5826                 } else {
5827                         mii = device_get_softc(sc->bge_miibus);
5828                         error = ifmedia_ioctl(ifp, ifr,
5829                             &mii->mii_media, command);
5830                 }
5831                 break;
5832         case SIOCSIFCAP:
5833                 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
5834 #ifdef DEVICE_POLLING
5835                 if (mask & IFCAP_POLLING) {
5836                         if (ifr->ifr_reqcap & IFCAP_POLLING) {
5837                                 error = ether_poll_register(bge_poll, ifp);
5838                                 if (error)
5839                                         return (error);
5840                                 BGE_LOCK(sc);
5841                                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5842                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
5843                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5844                                 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
5845                                 BGE_UNLOCK(sc);
5846                         } else {
5847                                 error = ether_poll_deregister(ifp);
5848                                 /* Enable interrupt even in error case */
5849                                 BGE_LOCK(sc);
5850                                 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
5851                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
5852                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5853                                 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
5854                                 BGE_UNLOCK(sc);
5855                         }
5856                 }
5857 #endif
5858                 if ((mask & IFCAP_TXCSUM) != 0 &&
5859                     (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
5860                         if_togglecapenable(ifp, IFCAP_TXCSUM);
5861                         if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
5862                                 if_sethwassistbits(ifp,
5863                                     sc->bge_csum_features, 0);
5864                         else
5865                                 if_sethwassistbits(ifp, 0,
5866                                     sc->bge_csum_features);
5867                 }
5868
5869                 if ((mask & IFCAP_RXCSUM) != 0 &&
5870                     (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0)
5871                         if_togglecapenable(ifp, IFCAP_RXCSUM);
5872
5873                 if ((mask & IFCAP_TSO4) != 0 &&
5874                     (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
5875                         if_togglecapenable(ifp, IFCAP_TSO4);
5876                         if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
5877                                 if_sethwassistbits(ifp, CSUM_TSO, 0);
5878                         else
5879                                 if_sethwassistbits(ifp, 0, CSUM_TSO);
5880                 }
5881
5882                 if (mask & IFCAP_VLAN_MTU) {
5883                         if_togglecapenable(ifp, IFCAP_VLAN_MTU);
5884                         if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5885                         bge_init(sc);
5886                 }
5887
5888                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
5889                     (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
5890                         if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
5891                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
5892                     (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
5893                         if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
5894                         if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
5895                                 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO);
5896                         BGE_LOCK(sc);
5897                         bge_setvlan(sc);
5898                         BGE_UNLOCK(sc);
5899                 }
5900 #ifdef VLAN_CAPABILITIES
5901                 if_vlancap(ifp);
5902 #endif
5903                 break;
5904         default:
5905                 error = ether_ioctl(ifp, command, data);
5906                 break;
5907         }
5908
5909         return (error);
5910 }
5911
5912 static void
5913 bge_watchdog(struct bge_softc *sc)
5914 {
5915         if_t ifp;
5916         uint32_t status;
5917
5918         BGE_LOCK_ASSERT(sc);
5919
5920         if (sc->bge_timer == 0 || --sc->bge_timer)
5921                 return;
5922
5923         /* If pause frames are active then don't reset the hardware. */
5924         if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) {
5925                 status = CSR_READ_4(sc, BGE_RX_STS);
5926                 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) {
5927                         /*
5928                          * If link partner has us in XOFF state then wait for
5929                          * the condition to clear.
5930                          */
5931                         CSR_WRITE_4(sc, BGE_RX_STS, status);
5932                         sc->bge_timer = BGE_TX_TIMEOUT;
5933                         return;
5934                 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 &&
5935                     (status & BGE_RXSTAT_RCVD_XON) != 0) {
5936                         /*
5937                          * If link partner has us in XOFF state then wait for
5938                          * the condition to clear.
5939                          */
5940                         CSR_WRITE_4(sc, BGE_RX_STS, status);
5941                         sc->bge_timer = BGE_TX_TIMEOUT;
5942                         return;
5943                 }
5944                 /*
5945                  * Any other condition is unexpected and the controller
5946                  * should be reset.
5947                  */
5948         }
5949
5950         ifp = sc->bge_ifp;
5951
5952         if_printf(ifp, "watchdog timeout -- resetting\n");
5953
5954         if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5955         bge_init_locked(sc);
5956
5957         if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
5958 }
5959
5960 static void
5961 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
5962 {
5963         int i;
5964
5965         BGE_CLRBIT(sc, reg, bit);
5966
5967         for (i = 0; i < BGE_TIMEOUT; i++) {
5968                 if ((CSR_READ_4(sc, reg) & bit) == 0)
5969                         return;
5970                 DELAY(100);
5971         }
5972 }
5973
5974 /*
5975  * Stop the adapter and free any mbufs allocated to the
5976  * RX and TX lists.
5977  */
5978 static void
5979 bge_stop(struct bge_softc *sc)
5980 {
5981         if_t ifp;
5982
5983         BGE_LOCK_ASSERT(sc);
5984
5985         ifp = sc->bge_ifp;
5986
5987         callout_stop(&sc->bge_stat_ch);
5988
5989         /* Disable host interrupts. */
5990         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5991         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5992
5993         /*
5994          * Tell firmware we're shutting down.
5995          */
5996         bge_stop_fw(sc);
5997         bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
5998
5999         /*
6000          * Disable all of the receiver blocks.
6001          */
6002         bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
6003         bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
6004         bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
6005         if (BGE_IS_5700_FAMILY(sc))
6006                 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
6007         bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
6008         bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
6009         bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
6010
6011         /*
6012          * Disable all of the transmit blocks.
6013          */
6014         bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
6015         bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
6016         bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
6017         bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
6018         bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
6019         if (BGE_IS_5700_FAMILY(sc))
6020                 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
6021         bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
6022
6023         /*
6024          * Shut down all of the memory managers and related
6025          * state machines.
6026          */
6027         bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
6028         bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
6029         if (BGE_IS_5700_FAMILY(sc))
6030                 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
6031
6032         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
6033         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
6034         if (!(BGE_IS_5705_PLUS(sc))) {
6035                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
6036                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
6037         }
6038         /* Update MAC statistics. */
6039         if (BGE_IS_5705_PLUS(sc))
6040                 bge_stats_update_regs(sc);
6041
6042         bge_reset(sc);
6043         bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
6044         bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
6045
6046         /*
6047          * Keep the ASF firmware running if up.
6048          */
6049         if (sc->bge_asf_mode & ASF_STACKUP)
6050                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6051         else
6052                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6053
6054         /* Free the RX lists. */
6055         bge_free_rx_ring_std(sc);
6056
6057         /* Free jumbo RX list. */
6058         if (BGE_IS_JUMBO_CAPABLE(sc))
6059                 bge_free_rx_ring_jumbo(sc);
6060
6061         /* Free TX buffers. */
6062         bge_free_tx_ring(sc);
6063
6064         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
6065
6066         /* Clear MAC's link state (PHY may still have link UP). */
6067         if (bootverbose && sc->bge_link)
6068                 if_printf(sc->bge_ifp, "link DOWN\n");
6069         sc->bge_link = 0;
6070
6071         if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
6072 }
6073
6074 /*
6075  * Stop all chip I/O so that the kernel's probe routines don't
6076  * get confused by errant DMAs when rebooting.
6077  */
6078 static int
6079 bge_shutdown(device_t dev)
6080 {
6081         struct bge_softc *sc;
6082
6083         sc = device_get_softc(dev);
6084         BGE_LOCK(sc);
6085         bge_stop(sc);
6086         BGE_UNLOCK(sc);
6087
6088         return (0);
6089 }
6090
6091 static int
6092 bge_suspend(device_t dev)
6093 {
6094         struct bge_softc *sc;
6095
6096         sc = device_get_softc(dev);
6097         BGE_LOCK(sc);
6098         bge_stop(sc);
6099         BGE_UNLOCK(sc);
6100
6101         return (0);
6102 }
6103
6104 static int
6105 bge_resume(device_t dev)
6106 {
6107         struct bge_softc *sc;
6108         if_t ifp;
6109
6110         sc = device_get_softc(dev);
6111         BGE_LOCK(sc);
6112         ifp = sc->bge_ifp;
6113         if (if_getflags(ifp) & IFF_UP) {
6114                 bge_init_locked(sc);
6115                 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
6116                         bge_start_locked(ifp);
6117         }
6118         BGE_UNLOCK(sc);
6119
6120         return (0);
6121 }
6122
6123 static void
6124 bge_link_upd(struct bge_softc *sc)
6125 {
6126         struct mii_data *mii;
6127         uint32_t link, status;
6128
6129         BGE_LOCK_ASSERT(sc);
6130
6131         /* Clear 'pending link event' flag. */
6132         sc->bge_link_evt = 0;
6133
6134         /*
6135          * Process link state changes.
6136          * Grrr. The link status word in the status block does
6137          * not work correctly on the BCM5700 rev AX and BX chips,
6138          * according to all available information. Hence, we have
6139          * to enable MII interrupts in order to properly obtain
6140          * async link changes. Unfortunately, this also means that
6141          * we have to read the MAC status register to detect link
6142          * changes, thereby adding an additional register access to
6143          * the interrupt handler.
6144          *
6145          * XXX: perhaps link state detection procedure used for
6146          * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
6147          */
6148
6149         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6150             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
6151                 status = CSR_READ_4(sc, BGE_MAC_STS);
6152                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
6153                         mii = device_get_softc(sc->bge_miibus);
6154                         mii_pollstat(mii);
6155                         if (!sc->bge_link &&
6156                             mii->mii_media_status & IFM_ACTIVE &&
6157                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6158                                 sc->bge_link++;
6159                                 if (bootverbose)
6160                                         if_printf(sc->bge_ifp, "link UP\n");
6161                         } else if (sc->bge_link &&
6162                             (!(mii->mii_media_status & IFM_ACTIVE) ||
6163                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6164                                 sc->bge_link = 0;
6165                                 if (bootverbose)
6166                                         if_printf(sc->bge_ifp, "link DOWN\n");
6167                         }
6168
6169                         /* Clear the interrupt. */
6170                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
6171                             BGE_EVTENB_MI_INTERRUPT);
6172                         bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
6173                             BRGPHY_MII_ISR);
6174                         bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
6175                             BRGPHY_MII_IMR, BRGPHY_INTRS);
6176                 }
6177                 return;
6178         }
6179
6180         if (sc->bge_flags & BGE_FLAG_TBI) {
6181                 status = CSR_READ_4(sc, BGE_MAC_STS);
6182                 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
6183                         if (!sc->bge_link) {
6184                                 sc->bge_link++;
6185                                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
6186                                         BGE_CLRBIT(sc, BGE_MAC_MODE,
6187                                             BGE_MACMODE_TBI_SEND_CFGS);
6188                                         DELAY(40);
6189                                 }
6190                                 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
6191                                 if (bootverbose)
6192                                         if_printf(sc->bge_ifp, "link UP\n");
6193                                 if_link_state_change(sc->bge_ifp,
6194                                     LINK_STATE_UP);
6195                         }
6196                 } else if (sc->bge_link) {
6197                         sc->bge_link = 0;
6198                         if (bootverbose)
6199                                 if_printf(sc->bge_ifp, "link DOWN\n");
6200                         if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
6201                 }
6202         } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
6203                 /*
6204                  * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
6205                  * in status word always set. Workaround this bug by reading
6206                  * PHY link status directly.
6207                  */
6208                 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
6209
6210                 if (link != sc->bge_link ||
6211                     sc->bge_asicrev == BGE_ASICREV_BCM5700) {
6212                         mii = device_get_softc(sc->bge_miibus);
6213                         mii_pollstat(mii);
6214                         if (!sc->bge_link &&
6215                             mii->mii_media_status & IFM_ACTIVE &&
6216                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6217                                 sc->bge_link++;
6218                                 if (bootverbose)
6219                                         if_printf(sc->bge_ifp, "link UP\n");
6220                         } else if (sc->bge_link &&
6221                             (!(mii->mii_media_status & IFM_ACTIVE) ||
6222                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6223                                 sc->bge_link = 0;
6224                                 if (bootverbose)
6225                                         if_printf(sc->bge_ifp, "link DOWN\n");
6226                         }
6227                 }
6228         } else {
6229                 /*
6230                  * For controllers that call mii_tick, we have to poll
6231                  * link status.
6232                  */
6233                 mii = device_get_softc(sc->bge_miibus);
6234                 mii_pollstat(mii);
6235                 bge_miibus_statchg(sc->bge_dev);
6236         }
6237
6238         /* Disable MAC attention when link is up. */
6239         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
6240             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
6241             BGE_MACSTAT_LINK_CHANGED);
6242 }
6243
6244 static void
6245 bge_add_sysctls(struct bge_softc *sc)
6246 {
6247         struct sysctl_ctx_list *ctx;
6248         struct sysctl_oid_list *children;
6249         int unit;
6250
6251         ctx = device_get_sysctl_ctx(sc->bge_dev);
6252         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
6253
6254 #ifdef BGE_REGISTER_DEBUG
6255         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
6256             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
6257             "Debug Information");
6258
6259         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
6260             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
6261             "MAC Register Read");
6262
6263         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read",
6264             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I",
6265             "APE Register Read");
6266
6267         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
6268             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
6269             "Memory Read");
6270
6271 #endif
6272
6273         unit = device_get_unit(sc->bge_dev);
6274         /*
6275          * A common design characteristic for many Broadcom client controllers
6276          * is that they only support a single outstanding DMA read operation
6277          * on the PCIe bus. This means that it will take twice as long to fetch
6278          * a TX frame that is split into header and payload buffers as it does
6279          * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
6280          * these controllers, coalescing buffers to reduce the number of memory
6281          * reads is effective way to get maximum performance(about 940Mbps).
6282          * Without collapsing TX buffers the maximum TCP bulk transfer
6283          * performance is about 850Mbps. However forcing coalescing mbufs
6284          * consumes a lot of CPU cycles, so leave it off by default.
6285          */
6286         sc->bge_forced_collapse = 0;
6287         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
6288             CTLFLAG_RWTUN, &sc->bge_forced_collapse, 0,
6289             "Number of fragmented TX buffers of a frame allowed before "
6290             "forced collapsing");
6291
6292         sc->bge_msi = 1;
6293         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi",
6294             CTLFLAG_RDTUN, &sc->bge_msi, 0, "Enable MSI");
6295
6296         /*
6297          * It seems all Broadcom controllers have a bug that can generate UDP
6298          * datagrams with checksum value 0 when TX UDP checksum offloading is
6299          * enabled.  Generating UDP checksum value 0 is RFC 768 violation.
6300          * Even though the probability of generating such UDP datagrams is
6301          * low, I don't want to see FreeBSD boxes to inject such datagrams
6302          * into network so disable UDP checksum offloading by default.  Users
6303          * still override this behavior by setting a sysctl variable,
6304          * dev.bge.0.forced_udpcsum.
6305          */
6306         sc->bge_forced_udpcsum = 0;
6307         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum",
6308             CTLFLAG_RWTUN, &sc->bge_forced_udpcsum, 0,
6309             "Enable UDP checksum offloading even if controller can "
6310             "generate UDP checksum value 0");
6311
6312         if (BGE_IS_5705_PLUS(sc))
6313                 bge_add_sysctl_stats_regs(sc, ctx, children);
6314         else
6315                 bge_add_sysctl_stats(sc, ctx, children);
6316 }
6317
6318 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
6319         SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
6320             sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
6321             desc)
6322
6323 static void
6324 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6325     struct sysctl_oid_list *parent)
6326 {
6327         struct sysctl_oid *tree;
6328         struct sysctl_oid_list *children, *schildren;
6329
6330         tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6331             NULL, "BGE Statistics");
6332         schildren = children = SYSCTL_CHILDREN(tree);
6333         BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
6334             children, COSFramesDroppedDueToFilters,
6335             "FramesDroppedDueToFilters");
6336         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
6337             children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
6338         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
6339             children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
6340         BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
6341             children, nicNoMoreRxBDs, "NoMoreRxBDs");
6342         BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
6343             children, ifInDiscards, "InputDiscards");
6344         BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
6345             children, ifInErrors, "InputErrors");
6346         BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
6347             children, nicRecvThresholdHit, "RecvThresholdHit");
6348         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
6349             children, nicDmaReadQueueFull, "DmaReadQueueFull");
6350         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
6351             children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
6352         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
6353             children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
6354         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
6355             children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
6356         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
6357             children, nicRingStatusUpdate, "RingStatusUpdate");
6358         BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
6359             children, nicInterrupts, "Interrupts");
6360         BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
6361             children, nicAvoidedInterrupts, "AvoidedInterrupts");
6362         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
6363             children, nicSendThresholdHit, "SendThresholdHit");
6364
6365         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
6366             NULL, "BGE RX Statistics");
6367         children = SYSCTL_CHILDREN(tree);
6368         BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
6369             children, rxstats.ifHCInOctets, "ifHCInOctets");
6370         BGE_SYSCTL_STAT(sc, ctx, "Fragments",
6371             children, rxstats.etherStatsFragments, "Fragments");
6372         BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
6373             children, rxstats.ifHCInUcastPkts, "UnicastPkts");
6374         BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
6375             children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
6376         BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
6377             children, rxstats.dot3StatsFCSErrors, "FCSErrors");
6378         BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
6379             children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
6380         BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
6381             children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
6382         BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
6383             children, rxstats.xoffPauseFramesReceived,
6384             "xoffPauseFramesReceived");
6385         BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
6386             children, rxstats.macControlFramesReceived,
6387             "ControlFramesReceived");
6388         BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
6389             children, rxstats.xoffStateEntered, "xoffStateEntered");
6390         BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
6391             children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
6392         BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
6393             children, rxstats.etherStatsJabbers, "Jabbers");
6394         BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
6395             children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
6396         BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
6397             children, rxstats.inRangeLengthError, "inRangeLengthError");
6398         BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
6399             children, rxstats.outRangeLengthError, "outRangeLengthError");
6400
6401         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
6402             NULL, "BGE TX Statistics");
6403         children = SYSCTL_CHILDREN(tree);
6404         BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
6405             children, txstats.ifHCOutOctets, "ifHCOutOctets");
6406         BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
6407             children, txstats.etherStatsCollisions, "Collisions");
6408         BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
6409             children, txstats.outXonSent, "XonSent");
6410         BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
6411             children, txstats.outXoffSent, "XoffSent");
6412         BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
6413             children, txstats.flowControlDone, "flowControlDone");
6414         BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
6415             children, txstats.dot3StatsInternalMacTransmitErrors,
6416             "InternalMacTransmitErrors");
6417         BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
6418             children, txstats.dot3StatsSingleCollisionFrames,
6419             "SingleCollisionFrames");
6420         BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
6421             children, txstats.dot3StatsMultipleCollisionFrames,
6422             "MultipleCollisionFrames");
6423         BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
6424             children, txstats.dot3StatsDeferredTransmissions,
6425             "DeferredTransmissions");
6426         BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
6427             children, txstats.dot3StatsExcessiveCollisions,
6428             "ExcessiveCollisions");
6429         BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
6430             children, txstats.dot3StatsLateCollisions,
6431             "LateCollisions");
6432         BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
6433             children, txstats.ifHCOutUcastPkts, "UnicastPkts");
6434         BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
6435             children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
6436         BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
6437             children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
6438         BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
6439             children, txstats.dot3StatsCarrierSenseErrors,
6440             "CarrierSenseErrors");
6441         BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
6442             children, txstats.ifOutDiscards, "Discards");
6443         BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
6444             children, txstats.ifOutErrors, "Errors");
6445 }
6446
6447 #undef BGE_SYSCTL_STAT
6448
6449 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d)    \
6450             SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
6451
6452 static void
6453 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6454     struct sysctl_oid_list *parent)
6455 {
6456         struct sysctl_oid *tree;
6457         struct sysctl_oid_list *child, *schild;
6458         struct bge_mac_stats *stats;
6459
6460         stats = &sc->bge_mac_stats;
6461         tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6462             NULL, "BGE Statistics");
6463         schild = child = SYSCTL_CHILDREN(tree);
6464         BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters",
6465             &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters");
6466         BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull",
6467             &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full");
6468         BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull",
6469             &stats->DmaWriteHighPriQueueFull,
6470             "NIC DMA Write High Priority Queue Full");
6471         BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs",
6472             &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors");
6473         BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards",
6474             &stats->InputDiscards, "Discarded Input Frames");
6475         BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors",
6476             &stats->InputErrors, "Input Errors");
6477         BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit",
6478             &stats->RecvThresholdHit, "NIC Recv Threshold Hit");
6479
6480         tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD,
6481             NULL, "BGE RX Statistics");
6482         child = SYSCTL_CHILDREN(tree);
6483         BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets",
6484             &stats->ifHCInOctets, "Inbound Octets");
6485         BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments",
6486             &stats->etherStatsFragments, "Fragments");
6487         BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6488             &stats->ifHCInUcastPkts, "Inbound Unicast Packets");
6489         BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6490             &stats->ifHCInMulticastPkts, "Inbound Multicast Packets");
6491         BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6492             &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets");
6493         BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors",
6494             &stats->dot3StatsFCSErrors, "FCS Errors");
6495         BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors",
6496             &stats->dot3StatsAlignmentErrors, "Alignment Errors");
6497         BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived",
6498             &stats->xonPauseFramesReceived, "XON Pause Frames Received");
6499         BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived",
6500             &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received");
6501         BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived",
6502             &stats->macControlFramesReceived, "MAC Control Frames Received");
6503         BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered",
6504             &stats->xoffStateEntered, "XOFF State Entered");
6505         BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong",
6506             &stats->dot3StatsFramesTooLong, "Frames Too Long");
6507         BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers",
6508             &stats->etherStatsJabbers, "Jabbers");
6509         BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts",
6510             &stats->etherStatsUndersizePkts, "Undersized Packets");
6511
6512         tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD,
6513             NULL, "BGE TX Statistics");
6514         child = SYSCTL_CHILDREN(tree);
6515         BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets",
6516             &stats->ifHCOutOctets, "Outbound Octets");
6517         BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions",
6518             &stats->etherStatsCollisions, "TX Collisions");
6519         BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent",
6520             &stats->outXonSent, "XON Sent");
6521         BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent",
6522             &stats->outXoffSent, "XOFF Sent");
6523         BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors",
6524             &stats->dot3StatsInternalMacTransmitErrors,
6525             "Internal MAC TX Errors");
6526         BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames",
6527             &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames");
6528         BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames",
6529             &stats->dot3StatsMultipleCollisionFrames,
6530             "Multiple Collision Frames");
6531         BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions",
6532             &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions");
6533         BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions",
6534             &stats->dot3StatsExcessiveCollisions, "Excessive Collisions");
6535         BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions",
6536             &stats->dot3StatsLateCollisions, "Late Collisions");
6537         BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6538             &stats->ifHCOutUcastPkts, "Outbound Unicast Packets");
6539         BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6540             &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets");
6541         BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6542             &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets");
6543 }
6544
6545 #undef  BGE_SYSCTL_STAT_ADD64
6546
6547 static int
6548 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
6549 {
6550         struct bge_softc *sc;
6551         uint32_t result;
6552         int offset;
6553
6554         sc = (struct bge_softc *)arg1;
6555         offset = arg2;
6556         result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
6557             offsetof(bge_hostaddr, bge_addr_lo));
6558         return (sysctl_handle_int(oidp, &result, 0, req));
6559 }
6560
6561 #ifdef BGE_REGISTER_DEBUG
6562 static int
6563 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
6564 {
6565         struct bge_softc *sc;
6566         uint16_t *sbdata;
6567         int error, result, sbsz;
6568         int i, j;
6569
6570         result = -1;
6571         error = sysctl_handle_int(oidp, &result, 0, req);
6572         if (error || (req->newptr == NULL))
6573                 return (error);
6574
6575         if (result == 1) {
6576                 sc = (struct bge_softc *)arg1;
6577
6578                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6579                     sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
6580                         sbsz = BGE_STATUS_BLK_SZ;
6581                 else
6582                         sbsz = 32;
6583                 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
6584                 printf("Status Block:\n");
6585                 BGE_LOCK(sc);
6586                 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6587                     sc->bge_cdata.bge_status_map,
6588                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6589                 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) {
6590                         printf("%06x:", i);
6591                         for (j = 0; j < 8; j++)
6592                                 printf(" %04x", sbdata[i++]);
6593                         printf("\n");
6594                 }
6595
6596                 printf("Registers:\n");
6597                 for (i = 0x800; i < 0xA00; ) {
6598                         printf("%06x:", i);
6599                         for (j = 0; j < 8; j++) {
6600                                 printf(" %08x", CSR_READ_4(sc, i));
6601                                 i += 4;
6602                         }
6603                         printf("\n");
6604                 }
6605                 BGE_UNLOCK(sc);
6606
6607                 printf("Hardware Flags:\n");
6608                 if (BGE_IS_5717_PLUS(sc))
6609                         printf(" - 5717 Plus\n");
6610                 if (BGE_IS_5755_PLUS(sc))
6611                         printf(" - 5755 Plus\n");
6612                 if (BGE_IS_575X_PLUS(sc))
6613                         printf(" - 575X Plus\n");
6614                 if (BGE_IS_5705_PLUS(sc))
6615                         printf(" - 5705 Plus\n");
6616                 if (BGE_IS_5714_FAMILY(sc))
6617                         printf(" - 5714 Family\n");
6618                 if (BGE_IS_5700_FAMILY(sc))
6619                         printf(" - 5700 Family\n");
6620                 if (sc->bge_flags & BGE_FLAG_JUMBO)
6621                         printf(" - Supports Jumbo Frames\n");
6622                 if (sc->bge_flags & BGE_FLAG_PCIX)
6623                         printf(" - PCI-X Bus\n");
6624                 if (sc->bge_flags & BGE_FLAG_PCIE)
6625                         printf(" - PCI Express Bus\n");
6626                 if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
6627                         printf(" - No 3 LEDs\n");
6628                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
6629                         printf(" - RX Alignment Bug\n");
6630         }
6631
6632         return (error);
6633 }
6634
6635 static int
6636 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6637 {
6638         struct bge_softc *sc;
6639         int error;
6640         uint16_t result;
6641         uint32_t val;
6642
6643         result = -1;
6644         error = sysctl_handle_int(oidp, &result, 0, req);
6645         if (error || (req->newptr == NULL))
6646                 return (error);
6647
6648         if (result < 0x8000) {
6649                 sc = (struct bge_softc *)arg1;
6650                 val = CSR_READ_4(sc, result);
6651                 printf("reg 0x%06X = 0x%08X\n", result, val);
6652         }
6653
6654         return (error);
6655 }
6656
6657 static int
6658 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS)
6659 {
6660         struct bge_softc *sc;
6661         int error;
6662         uint16_t result;
6663         uint32_t val;
6664
6665         result = -1;
6666         error = sysctl_handle_int(oidp, &result, 0, req);
6667         if (error || (req->newptr == NULL))
6668                 return (error);
6669
6670         if (result < 0x8000) {
6671                 sc = (struct bge_softc *)arg1;
6672                 val = APE_READ_4(sc, result);
6673                 printf("reg 0x%06X = 0x%08X\n", result, val);
6674         }
6675
6676         return (error);
6677 }
6678
6679 static int
6680 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
6681 {
6682         struct bge_softc *sc;
6683         int error;
6684         uint16_t result;
6685         uint32_t val;
6686
6687         result = -1;
6688         error = sysctl_handle_int(oidp, &result, 0, req);
6689         if (error || (req->newptr == NULL))
6690                 return (error);
6691
6692         if (result < 0x8000) {
6693                 sc = (struct bge_softc *)arg1;
6694                 val = bge_readmem_ind(sc, result);
6695                 printf("mem 0x%06X = 0x%08X\n", result, val);
6696         }
6697
6698         return (error);
6699 }
6700 #endif
6701
6702 static int
6703 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
6704 {
6705
6706         if (sc->bge_flags & BGE_FLAG_EADDR)
6707                 return (1);
6708
6709 #ifdef __sparc64__
6710         OF_getetheraddr(sc->bge_dev, ether_addr);
6711         return (0);
6712 #endif
6713         return (1);
6714 }
6715
6716 static int
6717 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
6718 {
6719         uint32_t mac_addr;
6720
6721         mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
6722         if ((mac_addr >> 16) == 0x484b) {
6723                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
6724                 ether_addr[1] = (uint8_t)mac_addr;
6725                 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
6726                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
6727                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
6728                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
6729                 ether_addr[5] = (uint8_t)mac_addr;
6730                 return (0);
6731         }
6732         return (1);
6733 }
6734
6735 static int
6736 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
6737 {
6738         int mac_offset = BGE_EE_MAC_OFFSET;
6739
6740         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6741                 mac_offset = BGE_EE_MAC_OFFSET_5906;
6742
6743         return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
6744             ETHER_ADDR_LEN));
6745 }
6746
6747 static int
6748 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
6749 {
6750
6751         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6752                 return (1);
6753
6754         return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
6755            ETHER_ADDR_LEN));
6756 }
6757
6758 static int
6759 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
6760 {
6761         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
6762                 /* NOTE: Order is critical */
6763                 bge_get_eaddr_fw,
6764                 bge_get_eaddr_mem,
6765                 bge_get_eaddr_nvram,
6766                 bge_get_eaddr_eeprom,
6767                 NULL
6768         };
6769         const bge_eaddr_fcn_t *func;
6770
6771         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
6772                 if ((*func)(sc, eaddr) == 0)
6773                         break;
6774         }
6775         return (*func == NULL ? ENXIO : 0);
6776 }
6777
6778 static uint64_t
6779 bge_get_counter(if_t ifp, ift_counter cnt)
6780 {
6781         struct bge_softc *sc;
6782         struct bge_mac_stats *stats;
6783
6784         sc = if_getsoftc(ifp);
6785         if (!BGE_IS_5705_PLUS(sc))
6786                 return (if_get_counter_default(ifp, cnt));
6787         stats = &sc->bge_mac_stats;
6788
6789         switch (cnt) {
6790         case IFCOUNTER_IERRORS:
6791                 return (stats->NoMoreRxBDs + stats->InputDiscards +
6792                     stats->InputErrors);
6793         case IFCOUNTER_COLLISIONS:
6794                 return (stats->etherStatsCollisions);
6795         default:
6796                 return (if_get_counter_default(ifp, cnt));
6797         }
6798 }