sys/dev/bge/if_bge.c

   1 /*-
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/cdefs.h>
  35 __FBSDID("$FreeBSD$");
  36
  37 /*
  38  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  39  *
  40  * The Broadcom BCM5700 is based on technology originally developed by
  41  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  42  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  43  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  44  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  45  * frames, highly configurable RX filtering, and 16 RX and TX queues
  46  * (which, along with RX filter rules, can be used for QOS applications).
  47  * Other features, such as TCP segmentation, may be available as part
  48  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  49  * firmware images can be stored in hardware and need not be compiled
  50  * into the driver.
  51  *
  52  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  53  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  54  *
  55  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  56  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  57  * does not support external SSRAM.
  58  *
  59  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  60  * brand name, which is functionally similar but lacks PCI-X support.
  61  *
  62  * Without external SSRAM, you can only have at most 4 TX rings,
  63  * and the use of the mini RX ring is disabled. This seems to imply
  64  * that these features are simply not available on the BCM5701. As a
  65  * result, this driver does not implement any support for the mini RX
  66  * ring.
  67  */
  68
  69 #ifdef HAVE_KERNEL_OPTION_HEADERS
  70 #include "opt_device_polling.h"
  71 #endif
  72
  73 #include <sys/param.h>
  74 #include <sys/endian.h>
  75 #include <sys/systm.h>
  76 #include <sys/sockio.h>
  77 #include <sys/mbuf.h>
  78 #include <sys/malloc.h>
  79 #include <sys/kernel.h>
  80 #include <sys/module.h>
  81 #include <sys/socket.h>
  82 #include <sys/sysctl.h>
  83 #include <sys/taskqueue.h>
  84
  85 #include <net/if.h>
  86 #include <net/if_arp.h>
  87 #include <net/ethernet.h>
  88 #include <net/if_dl.h>
  89 #include <net/if_media.h>
  90
  91 #include <net/bpf.h>
  92
  93 #include <net/if_types.h>
  94 #include <net/if_vlan_var.h>
  95
  96 #include <netinet/in_systm.h>
  97 #include <netinet/in.h>
  98 #include <netinet/ip.h>
  99 #include <netinet/tcp.h>
 100
 101 #include <machine/bus.h>
 102 #include <machine/resource.h>
 103 #include <sys/bus.h>
 104 #include <sys/rman.h>
 105
 106 #include <dev/mii/mii.h>
 107 #include <dev/mii/miivar.h>
 108 #include "miidevs.h"
 109 #include <dev/mii/brgphyreg.h>
 110
 111 #ifdef __sparc64__
 112 #include <dev/ofw/ofw_bus.h>
 113 #include <dev/ofw/openfirm.h>
 114 #include <machine/ofw_machdep.h>
 115 #include <machine/ver.h>
 116 #endif
 117
 118 #include <dev/pci/pcireg.h>
 119 #include <dev/pci/pcivar.h>
 120
 121 #include <dev/bge/if_bgereg.h>
 122
 123 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 124 #define ETHER_MIN_NOPAD         (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
 125
 126 MODULE_DEPEND(bge, pci, 1, 1, 1);
 127 MODULE_DEPEND(bge, ether, 1, 1, 1);
 128 MODULE_DEPEND(bge, miibus, 1, 1, 1);
 129
 130 /* "device miibus" required.  See GENERIC if you get errors here. */
 131 #include "miibus_if.h"
 132
 133 /*
 134  * Various supported device vendors/types and their names. Note: the
 135  * spec seems to indicate that the hardware still has Alteon's vendor
 136  * ID burned into it, though it will always be overriden by the vendor
 137  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 138  */
 139 static const struct bge_type {
 140         uint16_t        bge_vid;
 141         uint16_t        bge_did;
 142 } bge_devs[] = {
 143         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5700 },
 144         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5701 },
 145
 146         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1000 },
 147         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1002 },
 148         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC9100 },
 149
 150         { APPLE_VENDORID,       APPLE_DEVICE_BCM5701 },
 151
 152         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5700 },
 153         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5701 },
 154         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702 },
 155         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702_ALT },
 156         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702X },
 157         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703 },
 158         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703_ALT },
 159         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703X },
 160         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704C },
 161         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S },
 162         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S_ALT },
 163         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705 },
 164         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705F },
 165         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705K },
 166         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M },
 167         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M_ALT },
 168         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714C },
 169         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714S },
 170         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715 },
 171         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715S },
 172         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5720 },
 173         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5721 },
 174         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5722 },
 175         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5723 },
 176         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750 },
 177         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750M },
 178         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751 },
 179         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751F },
 180         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751M },
 181         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752 },
 182         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752M },
 183         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753 },
 184         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753F },
 185         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753M },
 186         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754 },
 187         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754M },
 188         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755 },
 189         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755M },
 190         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5756 },
 191         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761 },
 192         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761E },
 193         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761S },
 194         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761SE },
 195         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5764 },
 196         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780 },
 197         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780S },
 198         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5781 },
 199         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5782 },
 200         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5784 },
 201         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785F },
 202         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785G },
 203         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5786 },
 204         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787 },
 205         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787F },
 206         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787M },
 207         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5788 },
 208         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5789 },
 209         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901 },
 210         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901A2 },
 211         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5903M },
 212         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906 },
 213         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906M },
 214         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57760 },
 215         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57780 },
 216         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57788 },
 217         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57790 },
 218
 219         { SK_VENDORID,          SK_DEVICEID_ALTIMA },
 220
 221         { TC_VENDORID,          TC_DEVICEID_3C996 },
 222
 223         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE4 },
 224         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE5 },
 225         { FJTSU_VENDORID,       FJTSU_DEVICEID_PP250450 },
 226
 227         { 0, 0 }
 228 };
 229
 230 static const struct bge_vendor {
 231         uint16_t        v_id;
 232         const char      *v_name;
 233 } bge_vendors[] = {
 234         { ALTEON_VENDORID,      "Alteon" },
 235         { ALTIMA_VENDORID,      "Altima" },
 236         { APPLE_VENDORID,       "Apple" },
 237         { BCOM_VENDORID,        "Broadcom" },
 238         { SK_VENDORID,          "SysKonnect" },
 239         { TC_VENDORID,          "3Com" },
 240         { FJTSU_VENDORID,       "Fujitsu" },
 241
 242         { 0, NULL }
 243 };
 244
 245 static const struct bge_revision {
 246         uint32_t        br_chipid;
 247         const char      *br_name;
 248 } bge_revisions[] = {
 249         { BGE_CHIPID_BCM5700_A0,        "BCM5700 A0" },
 250         { BGE_CHIPID_BCM5700_A1,        "BCM5700 A1" },
 251         { BGE_CHIPID_BCM5700_B0,        "BCM5700 B0" },
 252         { BGE_CHIPID_BCM5700_B1,        "BCM5700 B1" },
 253         { BGE_CHIPID_BCM5700_B2,        "BCM5700 B2" },
 254         { BGE_CHIPID_BCM5700_B3,        "BCM5700 B3" },
 255         { BGE_CHIPID_BCM5700_ALTIMA,    "BCM5700 Altima" },
 256         { BGE_CHIPID_BCM5700_C0,        "BCM5700 C0" },
 257         { BGE_CHIPID_BCM5701_A0,        "BCM5701 A0" },
 258         { BGE_CHIPID_BCM5701_B0,        "BCM5701 B0" },
 259         { BGE_CHIPID_BCM5701_B2,        "BCM5701 B2" },
 260         { BGE_CHIPID_BCM5701_B5,        "BCM5701 B5" },
 261         { BGE_CHIPID_BCM5703_A0,        "BCM5703 A0" },
 262         { BGE_CHIPID_BCM5703_A1,        "BCM5703 A1" },
 263         { BGE_CHIPID_BCM5703_A2,        "BCM5703 A2" },
 264         { BGE_CHIPID_BCM5703_A3,        "BCM5703 A3" },
 265         { BGE_CHIPID_BCM5703_B0,        "BCM5703 B0" },
 266         { BGE_CHIPID_BCM5704_A0,        "BCM5704 A0" },
 267         { BGE_CHIPID_BCM5704_A1,        "BCM5704 A1" },
 268         { BGE_CHIPID_BCM5704_A2,        "BCM5704 A2" },
 269         { BGE_CHIPID_BCM5704_A3,        "BCM5704 A3" },
 270         { BGE_CHIPID_BCM5704_B0,        "BCM5704 B0" },
 271         { BGE_CHIPID_BCM5705_A0,        "BCM5705 A0" },
 272         { BGE_CHIPID_BCM5705_A1,        "BCM5705 A1" },
 273         { BGE_CHIPID_BCM5705_A2,        "BCM5705 A2" },
 274         { BGE_CHIPID_BCM5705_A3,        "BCM5705 A3" },
 275         { BGE_CHIPID_BCM5750_A0,        "BCM5750 A0" },
 276         { BGE_CHIPID_BCM5750_A1,        "BCM5750 A1" },
 277         { BGE_CHIPID_BCM5750_A3,        "BCM5750 A3" },
 278         { BGE_CHIPID_BCM5750_B0,        "BCM5750 B0" },
 279         { BGE_CHIPID_BCM5750_B1,        "BCM5750 B1" },
 280         { BGE_CHIPID_BCM5750_C0,        "BCM5750 C0" },
 281         { BGE_CHIPID_BCM5750_C1,        "BCM5750 C1" },
 282         { BGE_CHIPID_BCM5750_C2,        "BCM5750 C2" },
 283         { BGE_CHIPID_BCM5714_A0,        "BCM5714 A0" },
 284         { BGE_CHIPID_BCM5752_A0,        "BCM5752 A0" },
 285         { BGE_CHIPID_BCM5752_A1,        "BCM5752 A1" },
 286         { BGE_CHIPID_BCM5752_A2,        "BCM5752 A2" },
 287         { BGE_CHIPID_BCM5714_B0,        "BCM5714 B0" },
 288         { BGE_CHIPID_BCM5714_B3,        "BCM5714 B3" },
 289         { BGE_CHIPID_BCM5715_A0,        "BCM5715 A0" },
 290         { BGE_CHIPID_BCM5715_A1,        "BCM5715 A1" },
 291         { BGE_CHIPID_BCM5715_A3,        "BCM5715 A3" },
 292         { BGE_CHIPID_BCM5755_A0,        "BCM5755 A0" },
 293         { BGE_CHIPID_BCM5755_A1,        "BCM5755 A1" },
 294         { BGE_CHIPID_BCM5755_A2,        "BCM5755 A2" },
 295         { BGE_CHIPID_BCM5722_A0,        "BCM5722 A0" },
 296         { BGE_CHIPID_BCM5761_A0,        "BCM5761 A0" },
 297         { BGE_CHIPID_BCM5761_A1,        "BCM5761 A1" },
 298         { BGE_CHIPID_BCM5784_A0,        "BCM5784 A0" },
 299         { BGE_CHIPID_BCM5784_A1,        "BCM5784 A1" },
 300         /* 5754 and 5787 share the same ASIC ID */
 301         { BGE_CHIPID_BCM5787_A0,        "BCM5754/5787 A0" },
 302         { BGE_CHIPID_BCM5787_A1,        "BCM5754/5787 A1" },
 303         { BGE_CHIPID_BCM5787_A2,        "BCM5754/5787 A2" },
 304         { BGE_CHIPID_BCM5906_A1,        "BCM5906 A1" },
 305         { BGE_CHIPID_BCM5906_A2,        "BCM5906 A2" },
 306         { BGE_CHIPID_BCM57780_A0,       "BCM57780 A0" },
 307         { BGE_CHIPID_BCM57780_A1,       "BCM57780 A1" },
 308
 309         { 0, NULL }
 310 };
 311
 312 /*
 313  * Some defaults for major revisions, so that newer steppings
 314  * that we don't know about have a shot at working.
 315  */
 316 static const struct bge_revision bge_majorrevs[] = {
 317         { BGE_ASICREV_BCM5700,          "unknown BCM5700" },
 318         { BGE_ASICREV_BCM5701,          "unknown BCM5701" },
 319         { BGE_ASICREV_BCM5703,          "unknown BCM5703" },
 320         { BGE_ASICREV_BCM5704,          "unknown BCM5704" },
 321         { BGE_ASICREV_BCM5705,          "unknown BCM5705" },
 322         { BGE_ASICREV_BCM5750,          "unknown BCM5750" },
 323         { BGE_ASICREV_BCM5714_A0,       "unknown BCM5714" },
 324         { BGE_ASICREV_BCM5752,          "unknown BCM5752" },
 325         { BGE_ASICREV_BCM5780,          "unknown BCM5780" },
 326         { BGE_ASICREV_BCM5714,          "unknown BCM5714" },
 327         { BGE_ASICREV_BCM5755,          "unknown BCM5755" },
 328         { BGE_ASICREV_BCM5761,          "unknown BCM5761" },
 329         { BGE_ASICREV_BCM5784,          "unknown BCM5784" },
 330         { BGE_ASICREV_BCM5785,          "unknown BCM5785" },
 331         /* 5754 and 5787 share the same ASIC ID */
 332         { BGE_ASICREV_BCM5787,          "unknown BCM5754/5787" },
 333         { BGE_ASICREV_BCM5906,          "unknown BCM5906" },
 334         { BGE_ASICREV_BCM57780,         "unknown BCM57780" },
 335
 336         { 0, NULL }
 337 };
 338
 339 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 340 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 341 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 342 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 343 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 344 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 345
 346 const struct bge_revision * bge_lookup_rev(uint32_t);
 347 const struct bge_vendor * bge_lookup_vendor(uint16_t);
 348
 349 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 350
 351 static int bge_probe(device_t);
 352 static int bge_attach(device_t);
 353 static int bge_detach(device_t);
 354 static int bge_suspend(device_t);
 355 static int bge_resume(device_t);
 356 static void bge_release_resources(struct bge_softc *);
 357 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 358 static int bge_dma_alloc(device_t);
 359 static void bge_dma_free(struct bge_softc *);
 360
 361 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
 362 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 363 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 364 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 365 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
 366
 367 static void bge_txeof(struct bge_softc *, uint16_t);
 368 static int bge_rxeof(struct bge_softc *, uint16_t, int);
 369
 370 static void bge_asf_driver_up (struct bge_softc *);
 371 static void bge_tick(void *);
 372 static void bge_stats_update(struct bge_softc *);
 373 static void bge_stats_update_regs(struct bge_softc *);
 374 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
 375     uint16_t *);
 376 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 377
 378 static void bge_intr(void *);
 379 static int bge_msi_intr(void *);
 380 static void bge_intr_task(void *, int);
 381 static void bge_start_locked(struct ifnet *);
 382 static void bge_start(struct ifnet *);
 383 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
 384 static void bge_init_locked(struct bge_softc *);
 385 static void bge_init(void *);
 386 static void bge_stop(struct bge_softc *);
 387 static void bge_watchdog(struct bge_softc *);
 388 static int bge_shutdown(device_t);
 389 static int bge_ifmedia_upd_locked(struct ifnet *);
 390 static int bge_ifmedia_upd(struct ifnet *);
 391 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 392
 393 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 394 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 395
 396 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
 397 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
 398
 399 static void bge_setpromisc(struct bge_softc *);
 400 static void bge_setmulti(struct bge_softc *);
 401 static void bge_setvlan(struct bge_softc *);
 402
 403 static __inline void bge_rxreuse_std(struct bge_softc *, int);
 404 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
 405 static int bge_newbuf_std(struct bge_softc *, int);
 406 static int bge_newbuf_jumbo(struct bge_softc *, int);
 407 static int bge_init_rx_ring_std(struct bge_softc *);
 408 static void bge_free_rx_ring_std(struct bge_softc *);
 409 static int bge_init_rx_ring_jumbo(struct bge_softc *);
 410 static void bge_free_rx_ring_jumbo(struct bge_softc *);
 411 static void bge_free_tx_ring(struct bge_softc *);
 412 static int bge_init_tx_ring(struct bge_softc *);
 413
 414 static int bge_chipinit(struct bge_softc *);
 415 static int bge_blockinit(struct bge_softc *);
 416
 417 static int bge_has_eaddr(struct bge_softc *);
 418 static uint32_t bge_readmem_ind(struct bge_softc *, int);
 419 static void bge_writemem_ind(struct bge_softc *, int, int);
 420 static void bge_writembx(struct bge_softc *, int, int);
 421 #ifdef notdef
 422 static uint32_t bge_readreg_ind(struct bge_softc *, int);
 423 #endif
 424 static void bge_writemem_direct(struct bge_softc *, int, int);
 425 static void bge_writereg_ind(struct bge_softc *, int, int);
 426
 427 static int bge_miibus_readreg(device_t, int, int);
 428 static int bge_miibus_writereg(device_t, int, int, int);
 429 static void bge_miibus_statchg(device_t);
 430 #ifdef DEVICE_POLLING
 431 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 432 #endif
 433
 434 #define BGE_RESET_START 1
 435 #define BGE_RESET_STOP  2
 436 static void bge_sig_post_reset(struct bge_softc *, int);
 437 static void bge_sig_legacy(struct bge_softc *, int);
 438 static void bge_sig_pre_reset(struct bge_softc *, int);
 439 static int bge_reset(struct bge_softc *);
 440 static void bge_link_upd(struct bge_softc *);
 441
 442 /*
 443  * The BGE_REGISTER_DEBUG option is only for low-level debugging.  It may
 444  * leak information to untrusted users.  It is also known to cause alignment
 445  * traps on certain architectures.
 446  */
 447 #ifdef BGE_REGISTER_DEBUG
 448 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 449 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
 450 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
 451 #endif
 452 static void bge_add_sysctls(struct bge_softc *);
 453 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
 454
 455 static device_method_t bge_methods[] = {
 456         /* Device interface */
 457         DEVMETHOD(device_probe,         bge_probe),
 458         DEVMETHOD(device_attach,        bge_attach),
 459         DEVMETHOD(device_detach,        bge_detach),
 460         DEVMETHOD(device_shutdown,      bge_shutdown),
 461         DEVMETHOD(device_suspend,       bge_suspend),
 462         DEVMETHOD(device_resume,        bge_resume),
 463
 464         /* bus interface */
 465         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 466         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 467
 468         /* MII interface */
 469         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 470         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 471         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 472
 473         { 0, 0 }
 474 };
 475
 476 static driver_t bge_driver = {
 477         "bge",
 478         bge_methods,
 479         sizeof(struct bge_softc)
 480 };
 481
 482 static devclass_t bge_devclass;
 483
 484 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
 485 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 486
 487 static int bge_allow_asf = 1;
 488
 489 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
 490
 491 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
 492 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
 493         "Allow ASF mode if available");
 494
 495 #define SPARC64_BLADE_1500_MODEL        "SUNW,Sun-Blade-1500"
 496 #define SPARC64_BLADE_1500_PATH_BGE     "/pci@1f,700000/network@2"
 497 #define SPARC64_BLADE_2500_MODEL        "SUNW,Sun-Blade-2500"
 498 #define SPARC64_BLADE_2500_PATH_BGE     "/pci@1c,600000/network@3"
 499 #define SPARC64_OFW_SUBVENDOR           "subsystem-vendor-id"
 500
 501 static int
 502 bge_has_eaddr(struct bge_softc *sc)
 503 {
 504 #ifdef __sparc64__
 505         char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
 506         device_t dev;
 507         uint32_t subvendor;
 508
 509         dev = sc->bge_dev;
 510
 511         /*
 512          * The on-board BGEs found in sun4u machines aren't fitted with
 513          * an EEPROM which means that we have to obtain the MAC address
 514          * via OFW and that some tests will always fail.  We distinguish
 515          * such BGEs by the subvendor ID, which also has to be obtained
 516          * from OFW instead of the PCI configuration space as the latter
 517          * indicates Broadcom as the subvendor of the netboot interface.
 518          * For early Blade 1500 and 2500 we even have to check the OFW
 519          * device path as the subvendor ID always defaults to Broadcom
 520          * there.
 521          */
 522         if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
 523             &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
 524             (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID))
 525                 return (0);
 526         memset(buf, 0, sizeof(buf));
 527         if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
 528                 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
 529                     strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
 530                         return (0);
 531                 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
 532                     strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
 533                         return (0);
 534         }
 535 #endif
 536         return (1);
 537 }
 538
 539 static uint32_t
 540 bge_readmem_ind(struct bge_softc *sc, int off)
 541 {
 542         device_t dev;
 543         uint32_t val;
 544
 545         dev = sc->bge_dev;
 546
 547         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 548         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 549         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 550         return (val);
 551 }
 552
 553 static void
 554 bge_writemem_ind(struct bge_softc *sc, int off, int val)
 555 {
 556         device_t dev;
 557
 558         dev = sc->bge_dev;
 559
 560         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 561         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 562         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 563 }
 564
 565 #ifdef notdef
 566 static uint32_t
 567 bge_readreg_ind(struct bge_softc *sc, int off)
 568 {
 569         device_t dev;
 570
 571         dev = sc->bge_dev;
 572
 573         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 574         return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 575 }
 576 #endif
 577
 578 static void
 579 bge_writereg_ind(struct bge_softc *sc, int off, int val)
 580 {
 581         device_t dev;
 582
 583         dev = sc->bge_dev;
 584
 585         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 586         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 587 }
 588
 589 static void
 590 bge_writemem_direct(struct bge_softc *sc, int off, int val)
 591 {
 592         CSR_WRITE_4(sc, off, val);
 593 }
 594
 595 static void
 596 bge_writembx(struct bge_softc *sc, int off, int val)
 597 {
 598         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 599                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 600
 601         CSR_WRITE_4(sc, off, val);
 602 }
 603
 604 /*
 605  * Map a single buffer address.
 606  */
 607
 608 static void
 609 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 610 {
 611         struct bge_dmamap_arg *ctx;
 612
 613         if (error)
 614                 return;
 615
 616         ctx = arg;
 617
 618         if (nseg > ctx->bge_maxsegs) {
 619                 ctx->bge_maxsegs = 0;
 620                 return;
 621         }
 622
 623         ctx->bge_busaddr = segs->ds_addr;
 624 }
 625
 626 static uint8_t
 627 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 628 {
 629         uint32_t access, byte = 0;
 630         int i;
 631
 632         /* Lock. */
 633         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 634         for (i = 0; i < 8000; i++) {
 635                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 636                         break;
 637                 DELAY(20);
 638         }
 639         if (i == 8000)
 640                 return (1);
 641
 642         /* Enable access. */
 643         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 644         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 645
 646         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 647         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 648         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 649                 DELAY(10);
 650                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 651                         DELAY(10);
 652                         break;
 653                 }
 654         }
 655
 656         if (i == BGE_TIMEOUT * 10) {
 657                 if_printf(sc->bge_ifp, "nvram read timed out\n");
 658                 return (1);
 659         }
 660
 661         /* Get result. */
 662         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 663
 664         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 665
 666         /* Disable access. */
 667         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 668
 669         /* Unlock. */
 670         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 671         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 672
 673         return (0);
 674 }
 675
 676 /*
 677  * Read a sequence of bytes from NVRAM.
 678  */
 679 static int
 680 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 681 {
 682         int err = 0, i;
 683         uint8_t byte = 0;
 684
 685         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 686                 return (1);
 687
 688         for (i = 0; i < cnt; i++) {
 689                 err = bge_nvram_getbyte(sc, off + i, &byte);
 690                 if (err)
 691                         break;
 692                 *(dest + i) = byte;
 693         }
 694
 695         return (err ? 1 : 0);
 696 }
 697
 698 /*
 699  * Read a byte of data stored in the EEPROM at address 'addr.' The
 700  * BCM570x supports both the traditional bitbang interface and an
 701  * auto access interface for reading the EEPROM. We use the auto
 702  * access method.
 703  */
 704 static uint8_t
 705 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 706 {
 707         int i;
 708         uint32_t byte = 0;
 709
 710         /*
 711          * Enable use of auto EEPROM access so we can avoid
 712          * having to use the bitbang method.
 713          */
 714         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 715
 716         /* Reset the EEPROM, load the clock period. */
 717         CSR_WRITE_4(sc, BGE_EE_ADDR,
 718             BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 719         DELAY(20);
 720
 721         /* Issue the read EEPROM command. */
 722         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 723
 724         /* Wait for completion */
 725         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 726                 DELAY(10);
 727                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 728                         break;
 729         }
 730
 731         if (i == BGE_TIMEOUT * 10) {
 732                 device_printf(sc->bge_dev, "EEPROM read timed out\n");
 733                 return (1);
 734         }
 735
 736         /* Get result. */
 737         byte = CSR_READ_4(sc, BGE_EE_DATA);
 738
 739         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 740
 741         return (0);
 742 }
 743
 744 /*
 745  * Read a sequence of bytes from the EEPROM.
 746  */
 747 static int
 748 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 749 {
 750         int i, error = 0;
 751         uint8_t byte = 0;
 752
 753         for (i = 0; i < cnt; i++) {
 754                 error = bge_eeprom_getbyte(sc, off + i, &byte);
 755                 if (error)
 756                         break;
 757                 *(dest + i) = byte;
 758         }
 759
 760         return (error ? 1 : 0);
 761 }
 762
 763 static int
 764 bge_miibus_readreg(device_t dev, int phy, int reg)
 765 {
 766         struct bge_softc *sc;
 767         uint32_t val, autopoll;
 768         int i;
 769
 770         sc = device_get_softc(dev);
 771
 772         /*
 773          * Broadcom's own driver always assumes the internal
 774          * PHY is at GMII address 1. On some chips, the PHY responds
 775          * to accesses at all addresses, which could cause us to
 776          * bogusly attach the PHY 32 times at probe type. Always
 777          * restricting the lookup to address 1 is simpler than
 778          * trying to figure out which chips revisions should be
 779          * special-cased.
 780          */
 781         if (phy != 1)
 782                 return (0);
 783
 784         /* Reading with autopolling on may trigger PCI errors */
 785         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 786         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 787                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 788                 DELAY(40);
 789         }
 790
 791         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 792             BGE_MIPHY(phy) | BGE_MIREG(reg));
 793
 794         for (i = 0; i < BGE_TIMEOUT; i++) {
 795                 DELAY(10);
 796                 val = CSR_READ_4(sc, BGE_MI_COMM);
 797                 if (!(val & BGE_MICOMM_BUSY))
 798                         break;
 799         }
 800
 801         if (i == BGE_TIMEOUT) {
 802                 device_printf(sc->bge_dev,
 803                     "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
 804                     phy, reg, val);
 805                 val = 0;
 806                 goto done;
 807         }
 808
 809         DELAY(5);
 810         val = CSR_READ_4(sc, BGE_MI_COMM);
 811
 812 done:
 813         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 814                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 815                 DELAY(40);
 816         }
 817
 818         if (val & BGE_MICOMM_READFAIL)
 819                 return (0);
 820
 821         return (val & 0xFFFF);
 822 }
 823
 824 static int
 825 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 826 {
 827         struct bge_softc *sc;
 828         uint32_t autopoll;
 829         int i;
 830
 831         sc = device_get_softc(dev);
 832
 833         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 834             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 835                 return(0);
 836
 837         /* Reading with autopolling on may trigger PCI errors */
 838         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 839         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 840                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 841                 DELAY(40);
 842         }
 843
 844         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 845             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 846
 847         for (i = 0; i < BGE_TIMEOUT; i++) {
 848                 DELAY(10);
 849                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 850                         DELAY(5);
 851                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 852                         break;
 853                 }
 854         }
 855
 856         if (i == BGE_TIMEOUT) {
 857                 device_printf(sc->bge_dev,
 858                     "PHY write timed out (phy %d, reg %d, val %d)\n",
 859                     phy, reg, val);
 860                 return (0);
 861         }
 862
 863         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 864                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 865                 DELAY(40);
 866         }
 867
 868         return (0);
 869 }
 870
 871 static void
 872 bge_miibus_statchg(device_t dev)
 873 {
 874         struct bge_softc *sc;
 875         struct mii_data *mii;
 876         sc = device_get_softc(dev);
 877         mii = device_get_softc(sc->bge_miibus);
 878
 879         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 880         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 881             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
 882                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 883         else
 884                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 885
 886         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
 887                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 888         else
 889                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 890 }
 891
 892 /*
 893  * Intialize a standard receive ring descriptor.
 894  */
 895 static int
 896 bge_newbuf_std(struct bge_softc *sc, int i)
 897 {
 898         struct mbuf *m;
 899         struct bge_rx_bd *r;
 900         bus_dma_segment_t segs[1];
 901         bus_dmamap_t map;
 902         int error, nsegs;
 903
 904         m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
 905         if (m == NULL)
 906                 return (ENOBUFS);
 907         m->m_len = m->m_pkthdr.len = MCLBYTES;
 908         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 909                 m_adj(m, ETHER_ALIGN);
 910
 911         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
 912             sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
 913         if (error != 0) {
 914                 m_freem(m);
 915                 return (error);
 916         }
 917         if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 918                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 919                     sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
 920                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 921                     sc->bge_cdata.bge_rx_std_dmamap[i]);
 922         }
 923         map = sc->bge_cdata.bge_rx_std_dmamap[i];
 924         sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
 925         sc->bge_cdata.bge_rx_std_sparemap = map;
 926         sc->bge_cdata.bge_rx_std_chain[i] = m;
 927         sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
 928         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
 929         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
 930         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
 931         r->bge_flags = BGE_RXBDFLAG_END;
 932         r->bge_len = segs[0].ds_len;
 933         r->bge_idx = i;
 934
 935         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 936             sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
 937
 938         return (0);
 939 }
 940
 941 /*
 942  * Initialize a jumbo receive ring descriptor. This allocates
 943  * a jumbo buffer from the pool managed internally by the driver.
 944  */
 945 static int
 946 bge_newbuf_jumbo(struct bge_softc *sc, int i)
 947 {
 948         bus_dma_segment_t segs[BGE_NSEG_JUMBO];
 949         bus_dmamap_t map;
 950         struct bge_extrx_bd *r;
 951         struct mbuf *m;
 952         int error, nsegs;
 953
 954         MGETHDR(m, M_DONTWAIT, MT_DATA);
 955         if (m == NULL)
 956                 return (ENOBUFS);
 957
 958         m_cljget(m, M_DONTWAIT, MJUM9BYTES);
 959         if (!(m->m_flags & M_EXT)) {
 960                 m_freem(m);
 961                 return (ENOBUFS);
 962         }
 963         m->m_len = m->m_pkthdr.len = MJUM9BYTES;
 964         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 965                 m_adj(m, ETHER_ALIGN);
 966
 967         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
 968             sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
 969         if (error != 0) {
 970                 m_freem(m);
 971                 return (error);
 972         }
 973
 974         if (sc->bge_cdata.bge_rx_jumbo_chain[i] == NULL) {
 975                 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
 976                     sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
 977                 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
 978                     sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
 979         }
 980         map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
 981         sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
 982             sc->bge_cdata.bge_rx_jumbo_sparemap;
 983         sc->bge_cdata.bge_rx_jumbo_sparemap = map;
 984         sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
 985         sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
 986         sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
 987         sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
 988         sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
 989
 990         /*
 991          * Fill in the extended RX buffer descriptor.
 992          */
 993         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
 994         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
 995         r->bge_idx = i;
 996         r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
 997         switch (nsegs) {
 998         case 4:
 999                 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1000                 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1001                 r->bge_len3 = segs[3].ds_len;
1002                 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1003         case 3:
1004                 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1005                 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1006                 r->bge_len2 = segs[2].ds_len;
1007                 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1008         case 2:
1009                 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1010                 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1011                 r->bge_len1 = segs[1].ds_len;
1012                 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1013         case 1:
1014                 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1015                 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1016                 r->bge_len0 = segs[0].ds_len;
1017                 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1018                 break;
1019         default:
1020                 panic("%s: %d segments\n", __func__, nsegs);
1021         }
1022
1023         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1024             sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1025
1026         return (0);
1027 }
1028
1029 static int
1030 bge_init_rx_ring_std(struct bge_softc *sc)
1031 {
1032         int error, i;
1033
1034         bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1035         sc->bge_std = 0;
1036         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1037                 if ((error = bge_newbuf_std(sc, i)) != 0)
1038                         return (error);
1039                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1040         };
1041
1042         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1043             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1044
1045         sc->bge_std = 0;
1046         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1047
1048         return (0);
1049 }
1050
1051 static void
1052 bge_free_rx_ring_std(struct bge_softc *sc)
1053 {
1054         int i;
1055
1056         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1057                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1058                         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1059                             sc->bge_cdata.bge_rx_std_dmamap[i],
1060                             BUS_DMASYNC_POSTREAD);
1061                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1062                             sc->bge_cdata.bge_rx_std_dmamap[i]);
1063                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1064                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1065                 }
1066                 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1067                     sizeof(struct bge_rx_bd));
1068         }
1069 }
1070
1071 static int
1072 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1073 {
1074         struct bge_rcb *rcb;
1075         int error, i;
1076
1077         bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1078         sc->bge_jumbo = 0;
1079         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1080                 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1081                         return (error);
1082                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1083         };
1084
1085         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1086             sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1087
1088         sc->bge_jumbo = 0;
1089
1090         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1091         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1092                                     BGE_RCB_FLAG_USE_EXT_RX_BD);
1093         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1094
1095         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1096
1097         return (0);
1098 }
1099
1100 static void
1101 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1102 {
1103         int i;
1104
1105         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1106                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1107                         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1108                             sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1109                             BUS_DMASYNC_POSTREAD);
1110                         bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1111                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1112                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1113                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1114                 }
1115                 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1116                     sizeof(struct bge_extrx_bd));
1117         }
1118 }
1119
1120 static void
1121 bge_free_tx_ring(struct bge_softc *sc)
1122 {
1123         int i;
1124
1125         if (sc->bge_ldata.bge_tx_ring == NULL)
1126                 return;
1127
1128         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1129                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1130                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1131                             sc->bge_cdata.bge_tx_dmamap[i],
1132                             BUS_DMASYNC_POSTWRITE);
1133                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1134                             sc->bge_cdata.bge_tx_dmamap[i]);
1135                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1136                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1137                 }
1138                 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1139                     sizeof(struct bge_tx_bd));
1140         }
1141 }
1142
1143 static int
1144 bge_init_tx_ring(struct bge_softc *sc)
1145 {
1146         sc->bge_txcnt = 0;
1147         sc->bge_tx_saved_considx = 0;
1148
1149         bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1150         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1151             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1152
1153         /* Initialize transmit producer index for host-memory send ring. */
1154         sc->bge_tx_prodidx = 0;
1155         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1156
1157         /* 5700 b2 errata */
1158         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1159                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1160
1161         /* NIC-memory send ring not used; initialize to zero. */
1162         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1163         /* 5700 b2 errata */
1164         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1165                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1166
1167         return (0);
1168 }
1169
1170 static void
1171 bge_setpromisc(struct bge_softc *sc)
1172 {
1173         struct ifnet *ifp;
1174
1175         BGE_LOCK_ASSERT(sc);
1176
1177         ifp = sc->bge_ifp;
1178
1179         /* Enable or disable promiscuous mode as needed. */
1180         if (ifp->if_flags & IFF_PROMISC)
1181                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1182         else
1183                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1184 }
1185
1186 static void
1187 bge_setmulti(struct bge_softc *sc)
1188 {
1189         struct ifnet *ifp;
1190         struct ifmultiaddr *ifma;
1191         uint32_t hashes[4] = { 0, 0, 0, 0 };
1192         int h, i;
1193
1194         BGE_LOCK_ASSERT(sc);
1195
1196         ifp = sc->bge_ifp;
1197
1198         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1199                 for (i = 0; i < 4; i++)
1200                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1201                 return;
1202         }
1203
1204         /* First, zot all the existing filters. */
1205         for (i = 0; i < 4; i++)
1206                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1207
1208         /* Now program new ones. */
1209         if_maddr_rlock(ifp);
1210         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1211                 if (ifma->ifma_addr->sa_family != AF_LINK)
1212                         continue;
1213                 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1214                     ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1215                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1216         }
1217         if_maddr_runlock(ifp);
1218
1219         for (i = 0; i < 4; i++)
1220                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1221 }
1222
1223 static void
1224 bge_setvlan(struct bge_softc *sc)
1225 {
1226         struct ifnet *ifp;
1227
1228         BGE_LOCK_ASSERT(sc);
1229
1230         ifp = sc->bge_ifp;
1231
1232         /* Enable or disable VLAN tag stripping as needed. */
1233         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1234                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1235         else
1236                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1237 }
1238
1239 static void
1240 bge_sig_pre_reset(sc, type)
1241         struct bge_softc *sc;
1242         int type;
1243 {
1244         /*
1245          * Some chips don't like this so only do this if ASF is enabled
1246          */
1247         if (sc->bge_asf_mode)
1248                 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1249
1250         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1251                 switch (type) {
1252                 case BGE_RESET_START:
1253                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1254                         break;
1255                 case BGE_RESET_STOP:
1256                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1257                         break;
1258                 }
1259         }
1260 }
1261
1262 static void
1263 bge_sig_post_reset(sc, type)
1264         struct bge_softc *sc;
1265         int type;
1266 {
1267         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1268                 switch (type) {
1269                 case BGE_RESET_START:
1270                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001);
1271                         /* START DONE */
1272                         break;
1273                 case BGE_RESET_STOP:
1274                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002);
1275                         break;
1276                 }
1277         }
1278 }
1279
1280 static void
1281 bge_sig_legacy(sc, type)
1282         struct bge_softc *sc;
1283         int type;
1284 {
1285         if (sc->bge_asf_mode) {
1286                 switch (type) {
1287                 case BGE_RESET_START:
1288                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1289                         break;
1290                 case BGE_RESET_STOP:
1291                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1292                         break;
1293                 }
1294         }
1295 }
1296
1297 void bge_stop_fw(struct bge_softc *);
1298 void
1299 bge_stop_fw(sc)
1300         struct bge_softc *sc;
1301 {
1302         int i;
1303
1304         if (sc->bge_asf_mode) {
1305                 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE);
1306                 CSR_WRITE_4(sc, BGE_CPU_EVENT,
1307                     CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
1308
1309                 for (i = 0; i < 100; i++ ) {
1310                         if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14)))
1311                                 break;
1312                         DELAY(10);
1313                 }
1314         }
1315 }
1316
1317 /*
1318  * Do endian, PCI and DMA initialization.
1319  */
1320 static int
1321 bge_chipinit(struct bge_softc *sc)
1322 {
1323         uint32_t dma_rw_ctl;
1324         uint16_t val;
1325         int i;
1326
1327         /* Set endianness before we access any non-PCI registers. */
1328         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1329
1330         /* Clear the MAC control register */
1331         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1332
1333         /*
1334          * Clear the MAC statistics block in the NIC's
1335          * internal memory.
1336          */
1337         for (i = BGE_STATS_BLOCK;
1338             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1339                 BGE_MEMWIN_WRITE(sc, i, 0);
1340
1341         for (i = BGE_STATUS_BLOCK;
1342             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1343                 BGE_MEMWIN_WRITE(sc, i, 0);
1344
1345         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1346                 /*
1347                  *  Fix data corruption caused by non-qword write with WB.
1348                  *  Fix master abort in PCI mode.
1349                  *  Fix PCI latency timer.
1350                  */
1351                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1352                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1353                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1354         }
1355
1356         /*
1357          * Set up the PCI DMA control register.
1358          */
1359         dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1360             BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1361         if (sc->bge_flags & BGE_FLAG_PCIE) {
1362                 /* Read watermark not used, 128 bytes for write. */
1363                 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1364         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1365                 if (BGE_IS_5714_FAMILY(sc)) {
1366                         /* 256 bytes for read and write. */
1367                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1368                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1369                         dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1370                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1371                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1372                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1373                         /*
1374                          * In the BCM5703, the DMA read watermark should
1375                          * be set to less than or equal to the maximum
1376                          * memory read byte count of the PCI-X command
1377                          * register.
1378                          */
1379                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1380                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1381                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1382                         /* 1536 bytes for read, 384 bytes for write. */
1383                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1384                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1385                 } else {
1386                         /* 384 bytes for read and write. */
1387                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1388                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1389                             0x0F;
1390                 }
1391                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1392                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1393                         uint32_t tmp;
1394
1395                         /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1396                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1397                         if (tmp == 6 || tmp == 7)
1398                                 dma_rw_ctl |=
1399                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1400
1401                         /* Set PCI-X DMA write workaround. */
1402                         dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1403                 }
1404         } else {
1405                 /* Conventional PCI bus: 256 bytes for read and write. */
1406                 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1407                     BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1408
1409                 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1410                     sc->bge_asicrev != BGE_ASICREV_BCM5750)
1411                         dma_rw_ctl |= 0x0F;
1412         }
1413         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1414             sc->bge_asicrev == BGE_ASICREV_BCM5701)
1415                 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1416                     BGE_PCIDMARWCTL_ASRT_ALL_BE;
1417         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1418             sc->bge_asicrev == BGE_ASICREV_BCM5704)
1419                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1420         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1421
1422         /*
1423          * Set up general mode register.
1424          */
1425         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
1426             BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1427             BGE_MODECTL_TX_NO_PHDR_CSUM);
1428
1429         /*
1430          * BCM5701 B5 have a bug causing data corruption when using
1431          * 64-bit DMA reads, which can be terminated early and then
1432          * completed later as 32-bit accesses, in combination with
1433          * certain bridges.
1434          */
1435         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1436             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1437                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1438
1439         /*
1440          * Tell the firmware the driver is running
1441          */
1442         if (sc->bge_asf_mode & ASF_STACKUP)
1443                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
1444
1445         /*
1446          * Disable memory write invalidate.  Apparently it is not supported
1447          * properly by these devices.  Also ensure that INTx isn't disabled,
1448          * as these chips need it even when using MSI.
1449          */
1450         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1451             PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
1452
1453         /* Set the timer prescaler (always 66Mhz) */
1454         CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1455
1456         /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1457         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1458                 DELAY(40);      /* XXX */
1459
1460                 /* Put PHY into ready state */
1461                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1462                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1463                 DELAY(40);
1464         }
1465
1466         return (0);
1467 }
1468
1469 static int
1470 bge_blockinit(struct bge_softc *sc)
1471 {
1472         struct bge_rcb *rcb;
1473         bus_size_t vrcb;
1474         bge_hostaddr taddr;
1475         uint32_t val;
1476         int i;
1477
1478         /*
1479          * Initialize the memory window pointer register so that
1480          * we can access the first 32K of internal NIC RAM. This will
1481          * allow us to set up the TX send ring RCBs and the RX return
1482          * ring RCBs, plus other things which live in NIC memory.
1483          */
1484         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1485
1486         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1487
1488         if (!(BGE_IS_5705_PLUS(sc))) {
1489                 /* Configure mbuf memory pool */
1490                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1491                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1492                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1493                 else
1494                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1495
1496                 /* Configure DMA resource pool */
1497                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1498                     BGE_DMA_DESCRIPTORS);
1499                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1500         }
1501
1502         /* Configure mbuf pool watermarks */
1503         if (!BGE_IS_5705_PLUS(sc)) {
1504                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1505                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1506                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1507         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1508                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1509                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1510                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1511         } else {
1512                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1513                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1514                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1515         }
1516
1517         /* Configure DMA resource watermarks */
1518         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1519         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1520
1521         /* Enable buffer manager */
1522         if (!(BGE_IS_5705_PLUS(sc))) {
1523                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1524                     BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN);
1525
1526                 /* Poll for buffer manager start indication */
1527                 for (i = 0; i < BGE_TIMEOUT; i++) {
1528                         DELAY(10);
1529                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1530                                 break;
1531                 }
1532
1533                 if (i == BGE_TIMEOUT) {
1534                         device_printf(sc->bge_dev,
1535                             "buffer manager failed to start\n");
1536                         return (ENXIO);
1537                 }
1538         }
1539
1540         /* Enable flow-through queues */
1541         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1542         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1543
1544         /* Wait until queue initialization is complete */
1545         for (i = 0; i < BGE_TIMEOUT; i++) {
1546                 DELAY(10);
1547                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1548                         break;
1549         }
1550
1551         if (i == BGE_TIMEOUT) {
1552                 device_printf(sc->bge_dev, "flow-through queue init failed\n");
1553                 return (ENXIO);
1554         }
1555
1556         /* Initialize the standard RX ring control block */
1557         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1558         rcb->bge_hostaddr.bge_addr_lo =
1559             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1560         rcb->bge_hostaddr.bge_addr_hi =
1561             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1562         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1563             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1564         if (BGE_IS_5705_PLUS(sc))
1565                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1566         else
1567                 rcb->bge_maxlen_flags =
1568                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1569         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1570         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1571         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1572
1573         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1574         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1575
1576         /*
1577          * Initialize the jumbo RX ring control block
1578          * We set the 'ring disabled' bit in the flags
1579          * field until we're actually ready to start
1580          * using this ring (i.e. once we set the MTU
1581          * high enough to require it).
1582          */
1583         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1584                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1585
1586                 rcb->bge_hostaddr.bge_addr_lo =
1587                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1588                 rcb->bge_hostaddr.bge_addr_hi =
1589                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1590                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1591                     sc->bge_cdata.bge_rx_jumbo_ring_map,
1592                     BUS_DMASYNC_PREREAD);
1593                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1594                     BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1595                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1596                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1597                     rcb->bge_hostaddr.bge_addr_hi);
1598                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1599                     rcb->bge_hostaddr.bge_addr_lo);
1600
1601                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1602                     rcb->bge_maxlen_flags);
1603                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1604
1605                 /* Set up dummy disabled mini ring RCB */
1606                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1607                 rcb->bge_maxlen_flags =
1608                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1609                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1610                     rcb->bge_maxlen_flags);
1611         }
1612
1613         /*
1614          * Set the BD ring replentish thresholds. The recommended
1615          * values are 1/8th the number of descriptors allocated to
1616          * each ring.
1617          * XXX The 5754 requires a lower threshold, so it might be a
1618          * requirement of all 575x family chips.  The Linux driver sets
1619          * the lower threshold for all 5705 family chips as well, but there
1620          * are reports that it might not need to be so strict.
1621          *
1622          * XXX Linux does some extra fiddling here for the 5906 parts as
1623          * well.
1624          */
1625         if (BGE_IS_5705_PLUS(sc))
1626                 val = 8;
1627         else
1628                 val = BGE_STD_RX_RING_CNT / 8;
1629         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1630         if (BGE_IS_JUMBO_CAPABLE(sc))
1631                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1632                     BGE_JUMBO_RX_RING_CNT/8);
1633
1634         /*
1635          * Disable all unused send rings by setting the 'ring disabled'
1636          * bit in the flags field of all the TX send ring control blocks.
1637          * These are located in NIC memory.
1638          */
1639         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1640         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1641                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1642                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1643                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1644                 vrcb += sizeof(struct bge_rcb);
1645         }
1646
1647         /* Configure TX RCB 0 (we use only the first ring) */
1648         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1649         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1650         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1651         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1652         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1653             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1654         if (!(BGE_IS_5705_PLUS(sc)))
1655                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1656                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1657
1658         /* Disable all unused RX return rings */
1659         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1660         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1661                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1662                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1663                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1664                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1665                     BGE_RCB_FLAG_RING_DISABLED));
1666                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1667                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1668                     (i * (sizeof(uint64_t))), 0);
1669                 vrcb += sizeof(struct bge_rcb);
1670         }
1671
1672         /* Initialize RX ring indexes */
1673         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1674         if (BGE_IS_JUMBO_CAPABLE(sc))
1675                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1676         if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1677                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1678
1679         /*
1680          * Set up RX return ring 0
1681          * Note that the NIC address for RX return rings is 0x00000000.
1682          * The return rings live entirely within the host, so the
1683          * nicaddr field in the RCB isn't used.
1684          */
1685         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1686         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1687         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1688         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1689         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1690         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1691             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1692
1693         /* Set random backoff seed for TX */
1694         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1695             IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1696             IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1697             IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1698             BGE_TX_BACKOFF_SEED_MASK);
1699
1700         /* Set inter-packet gap */
1701         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1702
1703         /*
1704          * Specify which ring to use for packets that don't match
1705          * any RX rules.
1706          */
1707         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1708
1709         /*
1710          * Configure number of RX lists. One interrupt distribution
1711          * list, sixteen active lists, one bad frames class.
1712          */
1713         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1714
1715         /* Inialize RX list placement stats mask. */
1716         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1717         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1718
1719         /* Disable host coalescing until we get it set up */
1720         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1721
1722         /* Poll to make sure it's shut down. */
1723         for (i = 0; i < BGE_TIMEOUT; i++) {
1724                 DELAY(10);
1725                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1726                         break;
1727         }
1728
1729         if (i == BGE_TIMEOUT) {
1730                 device_printf(sc->bge_dev,
1731                     "host coalescing engine failed to idle\n");
1732                 return (ENXIO);
1733         }
1734
1735         /* Set up host coalescing defaults */
1736         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1737         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1738         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1739         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1740         if (!(BGE_IS_5705_PLUS(sc))) {
1741                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1742                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1743         }
1744         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1745         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1746
1747         /* Set up address of statistics block */
1748         if (!(BGE_IS_5705_PLUS(sc))) {
1749                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1750                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1751                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1752                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1753                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1754                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1755                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1756         }
1757
1758         /* Set up address of status block */
1759         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1760             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1761         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1762             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1763         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1764         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1765
1766         /* Set up status block size. */
1767         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1768             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
1769                 val = BGE_STATBLKSZ_FULL;
1770         else
1771                 val = BGE_STATBLKSZ_32BYTE;
1772
1773         /* Turn on host coalescing state machine */
1774         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1775
1776         /* Turn on RX BD completion state machine and enable attentions */
1777         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1778             BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
1779
1780         /* Turn on RX list placement state machine */
1781         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1782
1783         /* Turn on RX list selector state machine. */
1784         if (!(BGE_IS_5705_PLUS(sc)))
1785                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1786
1787         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1788             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1789             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1790             BGE_MACMODE_FRMHDR_DMA_ENB;
1791
1792         if (sc->bge_flags & BGE_FLAG_TBI)
1793                 val |= BGE_PORTMODE_TBI;
1794         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1795                 val |= BGE_PORTMODE_GMII;
1796         else
1797                 val |= BGE_PORTMODE_MII;
1798
1799         /* Turn on DMA, clear stats */
1800         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1801
1802         /* Set misc. local control, enable interrupts on attentions */
1803         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1804
1805 #ifdef notdef
1806         /* Assert GPIO pins for PHY reset */
1807         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
1808             BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
1809         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
1810             BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
1811 #endif
1812
1813         /* Turn on DMA completion state machine */
1814         if (!(BGE_IS_5705_PLUS(sc)))
1815                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1816
1817         val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
1818
1819         /* Enable host coalescing bug fix. */
1820         if (BGE_IS_5755_PLUS(sc))
1821                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1822
1823         /* Turn on write DMA state machine */
1824         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1825         DELAY(40);
1826
1827         /* Turn on read DMA state machine */
1828         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1829         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1830             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1831             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1832                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1833                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1834                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1835         if (sc->bge_flags & BGE_FLAG_PCIE)
1836                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1837         if (sc->bge_flags & BGE_FLAG_TSO)
1838                 val |= BGE_RDMAMODE_TSO4_ENABLE;
1839         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1840         DELAY(40);
1841
1842         /* Turn on RX data completion state machine */
1843         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1844
1845         /* Turn on RX BD initiator state machine */
1846         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1847
1848         /* Turn on RX data and RX BD initiator state machine */
1849         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1850
1851         /* Turn on Mbuf cluster free state machine */
1852         if (!(BGE_IS_5705_PLUS(sc)))
1853                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1854
1855         /* Turn on send BD completion state machine */
1856         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1857
1858         /* Turn on send data completion state machine */
1859         val = BGE_SDCMODE_ENABLE;
1860         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1861                 val |= BGE_SDCMODE_CDELAY;
1862         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1863
1864         /* Turn on send data initiator state machine */
1865         if (sc->bge_flags & BGE_FLAG_TSO)
1866                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08);
1867         else
1868                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1869
1870         /* Turn on send BD initiator state machine */
1871         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1872
1873         /* Turn on send BD selector state machine */
1874         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1875
1876         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1877         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1878             BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
1879
1880         /* ack/clear link change events */
1881         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1882             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1883             BGE_MACSTAT_LINK_CHANGED);
1884         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1885
1886         /* Enable PHY auto polling (for MII/GMII only) */
1887         if (sc->bge_flags & BGE_FLAG_TBI) {
1888                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1889         } else {
1890                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16));
1891                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1892                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
1893                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1894                             BGE_EVTENB_MI_INTERRUPT);
1895         }
1896
1897         /*
1898          * Clear any pending link state attention.
1899          * Otherwise some link state change events may be lost until attention
1900          * is cleared by bge_intr() -> bge_link_upd() sequence.
1901          * It's not necessary on newer BCM chips - perhaps enabling link
1902          * state change attentions implies clearing pending attention.
1903          */
1904         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1905             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1906             BGE_MACSTAT_LINK_CHANGED);
1907
1908         /* Enable link state change attentions. */
1909         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1910
1911         return (0);
1912 }
1913
1914 const struct bge_revision *
1915 bge_lookup_rev(uint32_t chipid)
1916 {
1917         const struct bge_revision *br;
1918
1919         for (br = bge_revisions; br->br_name != NULL; br++) {
1920                 if (br->br_chipid == chipid)
1921                         return (br);
1922         }
1923
1924         for (br = bge_majorrevs; br->br_name != NULL; br++) {
1925                 if (br->br_chipid == BGE_ASICREV(chipid))
1926                         return (br);
1927         }
1928
1929         return (NULL);
1930 }
1931
1932 const struct bge_vendor *
1933 bge_lookup_vendor(uint16_t vid)
1934 {
1935         const struct bge_vendor *v;
1936
1937         for (v = bge_vendors; v->v_name != NULL; v++)
1938                 if (v->v_id == vid)
1939                         return (v);
1940
1941         panic("%s: unknown vendor %d", __func__, vid);
1942         return (NULL);
1943 }
1944
1945 /*
1946  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1947  * against our list and return its name if we find a match.
1948  *
1949  * Note that since the Broadcom controller contains VPD support, we
1950  * try to get the device name string from the controller itself instead
1951  * of the compiled-in string. It guarantees we'll always announce the
1952  * right product name. We fall back to the compiled-in string when
1953  * VPD is unavailable or corrupt.
1954  */
1955 static int
1956 bge_probe(device_t dev)
1957 {
1958         const struct bge_type *t = bge_devs;
1959         struct bge_softc *sc = device_get_softc(dev);
1960         uint16_t vid, did;
1961
1962         sc->bge_dev = dev;
1963         vid = pci_get_vendor(dev);
1964         did = pci_get_device(dev);
1965         while(t->bge_vid != 0) {
1966                 if ((vid == t->bge_vid) && (did == t->bge_did)) {
1967                         char model[64], buf[96];
1968                         const struct bge_revision *br;
1969                         const struct bge_vendor *v;
1970                         uint32_t id;
1971
1972                         id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1973                             BGE_PCIMISCCTL_ASICREV_SHIFT;
1974                         if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG)
1975                                 id = pci_read_config(dev,
1976                                     BGE_PCI_PRODID_ASICREV, 4);
1977                         br = bge_lookup_rev(id);
1978                         v = bge_lookup_vendor(vid);
1979                         {
1980 #if __FreeBSD_version > 700024
1981                                 const char *pname;
1982
1983                                 if (bge_has_eaddr(sc) &&
1984                                     pci_get_vpd_ident(dev, &pname) == 0)
1985                                         snprintf(model, 64, "%s", pname);
1986                                 else
1987 #endif
1988                                         snprintf(model, 64, "%s %s",
1989                                             v->v_name,
1990                                             br != NULL ? br->br_name :
1991                                             "NetXtreme Ethernet Controller");
1992                         }
1993                         snprintf(buf, 96, "%s, %sASIC rev. %#08x", model,
1994                             br != NULL ? "" : "unknown ", id);
1995                         device_set_desc_copy(dev, buf);
1996                         return (0);
1997                 }
1998                 t++;
1999         }
2000
2001         return (ENXIO);
2002 }
2003
2004 static void
2005 bge_dma_free(struct bge_softc *sc)
2006 {
2007         int i;
2008
2009         /* Destroy DMA maps for RX buffers. */
2010         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2011                 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2012                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2013                             sc->bge_cdata.bge_rx_std_dmamap[i]);
2014         }
2015         if (sc->bge_cdata.bge_rx_std_sparemap)
2016                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2017                     sc->bge_cdata.bge_rx_std_sparemap);
2018
2019         /* Destroy DMA maps for jumbo RX buffers. */
2020         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2021                 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2022                         bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2023                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2024         }
2025         if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2026                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2027                     sc->bge_cdata.bge_rx_jumbo_sparemap);
2028
2029         /* Destroy DMA maps for TX buffers. */
2030         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2031                 if (sc->bge_cdata.bge_tx_dmamap[i])
2032                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2033                             sc->bge_cdata.bge_tx_dmamap[i]);
2034         }
2035
2036         if (sc->bge_cdata.bge_rx_mtag)
2037                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2038         if (sc->bge_cdata.bge_tx_mtag)
2039                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2040
2041
2042         /* Destroy standard RX ring. */
2043         if (sc->bge_cdata.bge_rx_std_ring_map)
2044                 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2045                     sc->bge_cdata.bge_rx_std_ring_map);
2046         if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
2047                 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2048                     sc->bge_ldata.bge_rx_std_ring,
2049                     sc->bge_cdata.bge_rx_std_ring_map);
2050
2051         if (sc->bge_cdata.bge_rx_std_ring_tag)
2052                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2053
2054         /* Destroy jumbo RX ring. */
2055         if (sc->bge_cdata.bge_rx_jumbo_ring_map)
2056                 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2057                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2058
2059         if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
2060             sc->bge_ldata.bge_rx_jumbo_ring)
2061                 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2062                     sc->bge_ldata.bge_rx_jumbo_ring,
2063                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2064
2065         if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2066                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2067
2068         /* Destroy RX return ring. */
2069         if (sc->bge_cdata.bge_rx_return_ring_map)
2070                 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2071                     sc->bge_cdata.bge_rx_return_ring_map);
2072
2073         if (sc->bge_cdata.bge_rx_return_ring_map &&
2074             sc->bge_ldata.bge_rx_return_ring)
2075                 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2076                     sc->bge_ldata.bge_rx_return_ring,
2077                     sc->bge_cdata.bge_rx_return_ring_map);
2078
2079         if (sc->bge_cdata.bge_rx_return_ring_tag)
2080                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2081
2082         /* Destroy TX ring. */
2083         if (sc->bge_cdata.bge_tx_ring_map)
2084                 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2085                     sc->bge_cdata.bge_tx_ring_map);
2086
2087         if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
2088                 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2089                     sc->bge_ldata.bge_tx_ring,
2090                     sc->bge_cdata.bge_tx_ring_map);
2091
2092         if (sc->bge_cdata.bge_tx_ring_tag)
2093                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2094
2095         /* Destroy status block. */
2096         if (sc->bge_cdata.bge_status_map)
2097                 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2098                     sc->bge_cdata.bge_status_map);
2099
2100         if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
2101                 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2102                     sc->bge_ldata.bge_status_block,
2103                     sc->bge_cdata.bge_status_map);
2104
2105         if (sc->bge_cdata.bge_status_tag)
2106                 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2107
2108         /* Destroy statistics block. */
2109         if (sc->bge_cdata.bge_stats_map)
2110                 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2111                     sc->bge_cdata.bge_stats_map);
2112
2113         if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2114                 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2115                     sc->bge_ldata.bge_stats,
2116                     sc->bge_cdata.bge_stats_map);
2117
2118         if (sc->bge_cdata.bge_stats_tag)
2119                 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2120
2121         /* Destroy the parent tag. */
2122         if (sc->bge_cdata.bge_parent_tag)
2123                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2124 }
2125
2126 static int
2127 bge_dma_alloc(device_t dev)
2128 {
2129         struct bge_dmamap_arg ctx;
2130         struct bge_softc *sc;
2131         bus_addr_t lowaddr;
2132         bus_size_t sbsz, txsegsz, txmaxsegsz;
2133         int i, error;
2134
2135         sc = device_get_softc(dev);
2136
2137         lowaddr = BUS_SPACE_MAXADDR;
2138         if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2139                 lowaddr = BGE_DMA_MAXADDR;
2140         if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0)
2141                 lowaddr = BUS_SPACE_MAXADDR_32BIT;
2142         /*
2143          * Allocate the parent bus DMA tag appropriate for PCI.
2144          */
2145         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2146             1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2147             NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2148             0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2149
2150         if (error != 0) {
2151                 device_printf(sc->bge_dev,
2152                     "could not allocate parent dma tag\n");
2153                 return (ENOMEM);
2154         }
2155
2156         /*
2157          * Create tag for Tx mbufs.
2158          */
2159         if (sc->bge_flags & BGE_FLAG_TSO) {
2160                 txsegsz = BGE_TSOSEG_SZ;
2161                 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
2162         } else {
2163                 txsegsz = MCLBYTES;
2164                 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
2165         }
2166         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1,
2167             0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2168             txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
2169             &sc->bge_cdata.bge_tx_mtag);
2170
2171         if (error) {
2172                 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
2173                 return (ENOMEM);
2174         }
2175
2176         /*
2177          * Create tag for Rx mbufs.
2178          */
2179         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
2180             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
2181             MCLBYTES, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
2182
2183         if (error) {
2184                 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
2185                 return (ENOMEM);
2186         }
2187
2188         /* Create DMA maps for RX buffers. */
2189         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2190             &sc->bge_cdata.bge_rx_std_sparemap);
2191         if (error) {
2192                 device_printf(sc->bge_dev,
2193                     "can't create spare DMA map for RX\n");
2194                 return (ENOMEM);
2195         }
2196         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2197                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2198                             &sc->bge_cdata.bge_rx_std_dmamap[i]);
2199                 if (error) {
2200                         device_printf(sc->bge_dev,
2201                             "can't create DMA map for RX\n");
2202                         return (ENOMEM);
2203                 }
2204         }
2205
2206         /* Create DMA maps for TX buffers. */
2207         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2208                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
2209                             &sc->bge_cdata.bge_tx_dmamap[i]);
2210                 if (error) {
2211                         device_printf(sc->bge_dev,
2212                             "can't create DMA map for TX\n");
2213                         return (ENOMEM);
2214                 }
2215         }
2216
2217         /* Create tag for standard RX ring. */
2218         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2219             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2220             NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0,
2221             NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag);
2222
2223         if (error) {
2224                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2225                 return (ENOMEM);
2226         }
2227
2228         /* Allocate DMA'able memory for standard RX ring. */
2229         error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag,
2230             (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT,
2231             &sc->bge_cdata.bge_rx_std_ring_map);
2232         if (error)
2233                 return (ENOMEM);
2234
2235         bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
2236
2237         /* Load the address of the standard RX ring. */
2238         ctx.bge_maxsegs = 1;
2239         ctx.sc = sc;
2240
2241         error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag,
2242             sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring,
2243             BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2244
2245         if (error)
2246                 return (ENOMEM);
2247
2248         sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr;
2249
2250         /* Create tags for jumbo mbufs. */
2251         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2252                 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2253                     1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2254                     NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
2255                     0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
2256                 if (error) {
2257                         device_printf(sc->bge_dev,
2258                             "could not allocate jumbo dma tag\n");
2259                         return (ENOMEM);
2260                 }
2261
2262                 /* Create tag for jumbo RX ring. */
2263                 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2264                     PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2265                     NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0,
2266                     NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag);
2267
2268                 if (error) {
2269                         device_printf(sc->bge_dev,
2270                             "could not allocate jumbo ring dma tag\n");
2271                         return (ENOMEM);
2272                 }
2273
2274                 /* Allocate DMA'able memory for jumbo RX ring. */
2275                 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2276                     (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
2277                     BUS_DMA_NOWAIT | BUS_DMA_ZERO,
2278                     &sc->bge_cdata.bge_rx_jumbo_ring_map);
2279                 if (error)
2280                         return (ENOMEM);
2281
2282                 /* Load the address of the jumbo RX ring. */
2283                 ctx.bge_maxsegs = 1;
2284                 ctx.sc = sc;
2285
2286                 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2287                     sc->bge_cdata.bge_rx_jumbo_ring_map,
2288                     sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ,
2289                     bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2290
2291                 if (error)
2292                         return (ENOMEM);
2293
2294                 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr;
2295
2296                 /* Create DMA maps for jumbo RX buffers. */
2297                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2298                     0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
2299                 if (error) {
2300                         device_printf(sc->bge_dev,
2301                             "can't create spare DMA map for jumbo RX\n");
2302                         return (ENOMEM);
2303                 }
2304                 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2305                         error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2306                                     0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2307                         if (error) {
2308                                 device_printf(sc->bge_dev,
2309                                     "can't create DMA map for jumbo RX\n");
2310                                 return (ENOMEM);
2311                         }
2312                 }
2313
2314         }
2315
2316         /* Create tag for RX return ring. */
2317         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2318             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2319             NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0,
2320             NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag);
2321
2322         if (error) {
2323                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2324                 return (ENOMEM);
2325         }
2326
2327         /* Allocate DMA'able memory for RX return ring. */
2328         error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag,
2329             (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT,
2330             &sc->bge_cdata.bge_rx_return_ring_map);
2331         if (error)
2332                 return (ENOMEM);
2333
2334         bzero((char *)sc->bge_ldata.bge_rx_return_ring,
2335             BGE_RX_RTN_RING_SZ(sc));
2336
2337         /* Load the address of the RX return ring. */
2338         ctx.bge_maxsegs = 1;
2339         ctx.sc = sc;
2340
2341         error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag,
2342             sc->bge_cdata.bge_rx_return_ring_map,
2343             sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc),
2344             bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2345
2346         if (error)
2347                 return (ENOMEM);
2348
2349         sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr;
2350
2351         /* Create tag for TX ring. */
2352         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2353             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2354             NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL,
2355             &sc->bge_cdata.bge_tx_ring_tag);
2356
2357         if (error) {
2358                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2359                 return (ENOMEM);
2360         }
2361
2362         /* Allocate DMA'able memory for TX ring. */
2363         error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag,
2364             (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT,
2365             &sc->bge_cdata.bge_tx_ring_map);
2366         if (error)
2367                 return (ENOMEM);
2368
2369         bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
2370
2371         /* Load the address of the TX ring. */
2372         ctx.bge_maxsegs = 1;
2373         ctx.sc = sc;
2374
2375         error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag,
2376             sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring,
2377             BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2378
2379         if (error)
2380                 return (ENOMEM);
2381
2382         sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr;
2383
2384         /*
2385          * Create tag for status block.
2386          * Because we only use single Tx/Rx/Rx return ring, use
2387          * minimum status block size except BCM5700 AX/BX which
2388          * seems to want to see full status block size regardless
2389          * of configured number of ring.
2390          */
2391         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2392             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
2393                 sbsz = BGE_STATUS_BLK_SZ;
2394         else
2395                 sbsz = 32;
2396         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2397             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2398             NULL, sbsz, 1, sbsz, 0, NULL, NULL, &sc->bge_cdata.bge_status_tag);
2399
2400         if (error) {
2401                 device_printf(sc->bge_dev,
2402                     "could not allocate status dma tag\n");
2403                 return (ENOMEM);
2404         }
2405
2406         /* Allocate DMA'able memory for status block. */
2407         error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag,
2408             (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT,
2409             &sc->bge_cdata.bge_status_map);
2410         if (error)
2411                 return (ENOMEM);
2412
2413         bzero((char *)sc->bge_ldata.bge_status_block, sbsz);
2414
2415         /* Load the address of the status block. */
2416         ctx.sc = sc;
2417         ctx.bge_maxsegs = 1;
2418
2419         error = bus_dmamap_load(sc->bge_cdata.bge_status_tag,
2420             sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block,
2421             sbsz, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2422
2423         if (error)
2424                 return (ENOMEM);
2425
2426         sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr;
2427
2428         /* Create tag for statistics block. */
2429         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2430             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2431             NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL,
2432             &sc->bge_cdata.bge_stats_tag);
2433
2434         if (error) {
2435                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2436                 return (ENOMEM);
2437         }
2438
2439         /* Allocate DMA'able memory for statistics block. */
2440         error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag,
2441             (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT,
2442             &sc->bge_cdata.bge_stats_map);
2443         if (error)
2444                 return (ENOMEM);
2445
2446         bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ);
2447
2448         /* Load the address of the statstics block. */
2449         ctx.sc = sc;
2450         ctx.bge_maxsegs = 1;
2451
2452         error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag,
2453             sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats,
2454             BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2455
2456         if (error)
2457                 return (ENOMEM);
2458
2459         sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr;
2460
2461         return (0);
2462 }
2463
2464 /*
2465  * Return true if this device has more than one port.
2466  */
2467 static int
2468 bge_has_multiple_ports(struct bge_softc *sc)
2469 {
2470         device_t dev = sc->bge_dev;
2471         u_int b, d, f, fscan, s;
2472
2473         d = pci_get_domain(dev);
2474         b = pci_get_bus(dev);
2475         s = pci_get_slot(dev);
2476         f = pci_get_function(dev);
2477         for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
2478                 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
2479                         return (1);
2480         return (0);
2481 }
2482
2483 /*
2484  * Return true if MSI can be used with this device.
2485  */
2486 static int
2487 bge_can_use_msi(struct bge_softc *sc)
2488 {
2489         int can_use_msi = 0;
2490
2491         switch (sc->bge_asicrev) {
2492         case BGE_ASICREV_BCM5714_A0:
2493         case BGE_ASICREV_BCM5714:
2494                 /*
2495                  * Apparently, MSI doesn't work when these chips are
2496                  * configured in single-port mode.
2497                  */
2498                 if (bge_has_multiple_ports(sc))
2499                         can_use_msi = 1;
2500                 break;
2501         case BGE_ASICREV_BCM5750:
2502                 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
2503                     sc->bge_chiprev != BGE_CHIPREV_5750_BX)
2504                         can_use_msi = 1;
2505                 break;
2506         default:
2507                 if (BGE_IS_575X_PLUS(sc))
2508                         can_use_msi = 1;
2509         }
2510         return (can_use_msi);
2511 }
2512
2513 static int
2514 bge_attach(device_t dev)
2515 {
2516         struct ifnet *ifp;
2517         struct bge_softc *sc;
2518         uint32_t hwcfg = 0, misccfg;
2519         u_char eaddr[ETHER_ADDR_LEN];
2520         int error, msicount, reg, rid, trys;
2521
2522         sc = device_get_softc(dev);
2523         sc->bge_dev = dev;
2524
2525         TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
2526
2527         /*
2528          * Map control/status registers.
2529          */
2530         pci_enable_busmaster(dev);
2531
2532         rid = BGE_PCI_BAR0;
2533         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2534             RF_ACTIVE);
2535
2536         if (sc->bge_res == NULL) {
2537                 device_printf (sc->bge_dev, "couldn't map memory\n");
2538                 error = ENXIO;
2539                 goto fail;
2540         }
2541
2542         /* Save various chip information. */
2543         sc->bge_chipid =
2544             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2545             BGE_PCIMISCCTL_ASICREV_SHIFT;
2546         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
2547                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV,
2548                     4);
2549         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2550         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2551
2552         /*
2553          * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the
2554          * 5705 A0 and A1 chips.
2555          */
2556         if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
2557             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2558             sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2559             sc->bge_chipid != BGE_CHIPID_BCM5705_A1)
2560                 sc->bge_flags |= BGE_FLAG_WIRESPEED;
2561
2562         if (bge_has_eaddr(sc))
2563                 sc->bge_flags |= BGE_FLAG_EADDR;
2564
2565         /* Save chipset family. */
2566         switch (sc->bge_asicrev) {
2567         case BGE_ASICREV_BCM5755:
2568         case BGE_ASICREV_BCM5761:
2569         case BGE_ASICREV_BCM5784:
2570         case BGE_ASICREV_BCM5785:
2571         case BGE_ASICREV_BCM5787:
2572         case BGE_ASICREV_BCM57780:
2573                 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2574                     BGE_FLAG_5705_PLUS;
2575                 break;
2576         case BGE_ASICREV_BCM5700:
2577         case BGE_ASICREV_BCM5701:
2578         case BGE_ASICREV_BCM5703:
2579         case BGE_ASICREV_BCM5704:
2580                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2581                 break;
2582         case BGE_ASICREV_BCM5714_A0:
2583         case BGE_ASICREV_BCM5780:
2584         case BGE_ASICREV_BCM5714:
2585                 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */;
2586                 /* FALLTHROUGH */
2587         case BGE_ASICREV_BCM5750:
2588         case BGE_ASICREV_BCM5752:
2589         case BGE_ASICREV_BCM5906:
2590                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2591                 /* FALLTHROUGH */
2592         case BGE_ASICREV_BCM5705:
2593                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2594                 break;
2595         }
2596
2597         /* Set various bug flags. */
2598         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2599             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2600                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
2601         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2602             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2603                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
2604         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2605                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
2606         if (pci_get_subvendor(dev) == DELL_VENDORID)
2607                 sc->bge_flags |= BGE_FLAG_NO_3LED;
2608         if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
2609                 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
2610         if (BGE_IS_5705_PLUS(sc) &&
2611             !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) {
2612                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2613                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2614                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2615                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2616                         if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
2617                             pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
2618                                 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
2619                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
2620                         sc->bge_flags |= BGE_FLAG_BER_BUG;
2621         }
2622
2623         /*
2624          * All controllers that are not 5755 or higher have 4GB
2625          * boundary DMA bug.
2626          * Whenever an address crosses a multiple of the 4GB boundary
2627          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
2628          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
2629          * state machine will lockup and cause the device to hang.
2630          */
2631         if (BGE_IS_5755_PLUS(sc) == 0)
2632                 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
2633
2634         /*
2635          * We could possibly check for BCOM_DEVICEID_BCM5788 in bge_probe()
2636          * but I do not know the DEVICEID for the 5788M.
2637          */
2638         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID;
2639         if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2640             misccfg == BGE_MISCCFG_BOARD_ID_5788M)
2641                 sc->bge_flags |= BGE_FLAG_5788;
2642
2643         /*
2644          * Some controllers seem to require a special firmware to use
2645          * TSO. But the firmware is not available to FreeBSD and Linux
2646          * claims that the TSO performed by the firmware is slower than
2647          * hardware based TSO. Moreover the firmware based TSO has one
2648          * known bug which can't handle TSO if ethernet header + IP/TCP
2649          * header is greater than 80 bytes. The workaround for the TSO
2650          * bug exist but it seems it's too expensive than not using
2651          * TSO at all. Some hardwares also have the TSO bug so limit
2652          * the TSO to the controllers that are not affected TSO issues
2653          * (e.g. 5755 or higher).
2654          */
2655         if (BGE_IS_5755_PLUS(sc)) {
2656                 /*
2657                  * BCM5754 and BCM5787 shares the same ASIC id so
2658                  * explicit device id check is required.
2659                  * Due to unknown reason TSO does not work on BCM5755M.
2660                  */
2661                 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
2662                     pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
2663                     pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
2664                         sc->bge_flags |= BGE_FLAG_TSO;
2665         }
2666
2667         /*
2668          * Check if this is a PCI-X or PCI Express device.
2669          */
2670         if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {
2671                 /*
2672                  * Found a PCI Express capabilities register, this
2673                  * must be a PCI Express device.
2674                  */
2675                 sc->bge_flags |= BGE_FLAG_PCIE;
2676                 sc->bge_expcap = reg;
2677                 if (pci_get_max_read_req(dev) != 4096)
2678                         pci_set_max_read_req(dev, 4096);
2679         } else {
2680                 /*
2681                  * Check if the device is in PCI-X Mode.
2682                  * (This bit is not valid on PCI Express controllers.)
2683                  */
2684                 if (pci_find_extcap(dev, PCIY_PCIX, &reg) == 0)
2685                         sc->bge_pcixcap = reg;
2686                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
2687                     BGE_PCISTATE_PCI_BUSMODE) == 0)
2688                         sc->bge_flags |= BGE_FLAG_PCIX;
2689         }
2690
2691         /*
2692          * The 40bit DMA bug applies to the 5714/5715 controllers and is
2693          * not actually a MAC controller bug but an issue with the embedded
2694          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2695          */
2696         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
2697                 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
2698         /*
2699          * Allocate the interrupt, using MSI if possible.  These devices
2700          * support 8 MSI messages, but only the first one is used in
2701          * normal operation.
2702          */
2703         rid = 0;
2704         if (pci_find_extcap(sc->bge_dev, PCIY_MSI, &reg) == 0) {
2705                 sc->bge_msicap = reg;
2706                 if (bge_can_use_msi(sc)) {
2707                         msicount = pci_msi_count(dev);
2708                         if (msicount > 1)
2709                                 msicount = 1;
2710                 } else
2711                         msicount = 0;
2712                 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
2713                         rid = 1;
2714                         sc->bge_flags |= BGE_FLAG_MSI;
2715                 }
2716         }
2717
2718         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2719             RF_SHAREABLE | RF_ACTIVE);
2720
2721         if (sc->bge_irq == NULL) {
2722                 device_printf(sc->bge_dev, "couldn't map interrupt\n");
2723                 error = ENXIO;
2724                 goto fail;
2725         }
2726
2727         if (bootverbose)
2728                 device_printf(dev,
2729                     "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2730                     sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2731                     (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" :
2732                     ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI"));
2733
2734         BGE_LOCK_INIT(sc, device_get_nameunit(dev));
2735
2736         /* Try to reset the chip. */
2737         if (bge_reset(sc)) {
2738                 device_printf(sc->bge_dev, "chip reset failed\n");
2739                 error = ENXIO;
2740                 goto fail;
2741         }
2742
2743         sc->bge_asf_mode = 0;
2744         if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG)
2745             == BGE_MAGIC_NUMBER)) {
2746                 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG)
2747                     & BGE_HWCFG_ASF) {
2748                         sc->bge_asf_mode |= ASF_ENABLE;
2749                         sc->bge_asf_mode |= ASF_STACKUP;
2750                         if (BGE_IS_575X_PLUS(sc))
2751                                 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
2752                 }
2753         }
2754
2755         /* Try to reset the chip again the nice way. */
2756         bge_stop_fw(sc);
2757         bge_sig_pre_reset(sc, BGE_RESET_STOP);
2758         if (bge_reset(sc)) {
2759                 device_printf(sc->bge_dev, "chip reset failed\n");
2760                 error = ENXIO;
2761                 goto fail;
2762         }
2763
2764         bge_sig_legacy(sc, BGE_RESET_STOP);
2765         bge_sig_post_reset(sc, BGE_RESET_STOP);
2766
2767         if (bge_chipinit(sc)) {
2768                 device_printf(sc->bge_dev, "chip initialization failed\n");
2769                 error = ENXIO;
2770                 goto fail;
2771         }
2772
2773         error = bge_get_eaddr(sc, eaddr);
2774         if (error) {
2775                 device_printf(sc->bge_dev,
2776                     "failed to read station address\n");
2777                 error = ENXIO;
2778                 goto fail;
2779         }
2780
2781         /* 5705 limits RX return ring to 512 entries. */
2782         if (BGE_IS_5705_PLUS(sc))
2783                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2784         else
2785                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2786
2787         if (bge_dma_alloc(dev)) {
2788                 device_printf(sc->bge_dev,
2789                     "failed to allocate DMA resources\n");
2790                 error = ENXIO;
2791                 goto fail;
2792         }
2793
2794         /* Set default tuneable values. */
2795         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2796         sc->bge_rx_coal_ticks = 150;
2797         sc->bge_tx_coal_ticks = 150;
2798         sc->bge_rx_max_coal_bds = 10;
2799         sc->bge_tx_max_coal_bds = 10;
2800
2801         /* Set up ifnet structure */
2802         ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
2803         if (ifp == NULL) {
2804                 device_printf(sc->bge_dev, "failed to if_alloc()\n");
2805                 error = ENXIO;
2806                 goto fail;
2807         }
2808         ifp->if_softc = sc;
2809         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2810         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2811         ifp->if_ioctl = bge_ioctl;
2812         ifp->if_start = bge_start;
2813         ifp->if_init = bge_init;
2814         ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
2815         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2816         IFQ_SET_READY(&ifp->if_snd);
2817         ifp->if_hwassist = BGE_CSUM_FEATURES;
2818         ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
2819             IFCAP_VLAN_MTU;
2820         if ((sc->bge_flags & BGE_FLAG_TSO) != 0) {
2821                 ifp->if_hwassist |= CSUM_TSO;
2822                 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO;
2823         }
2824 #ifdef IFCAP_VLAN_HWCSUM
2825         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
2826 #endif
2827         ifp->if_capenable = ifp->if_capabilities;
2828 #ifdef DEVICE_POLLING
2829         ifp->if_capabilities |= IFCAP_POLLING;
2830 #endif
2831
2832         /*
2833          * 5700 B0 chips do not support checksumming correctly due
2834          * to hardware bugs.
2835          */
2836         if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
2837                 ifp->if_capabilities &= ~IFCAP_HWCSUM;
2838                 ifp->if_capenable &= ~IFCAP_HWCSUM;
2839                 ifp->if_hwassist = 0;
2840         }
2841
2842         /*
2843          * Figure out what sort of media we have by checking the
2844          * hardware config word in the first 32k of NIC internal memory,
2845          * or fall back to examining the EEPROM if necessary.
2846          * Note: on some BCM5700 cards, this value appears to be unset.
2847          * If that's the case, we have to rely on identifying the NIC
2848          * by its PCI subsystem ID, as we do below for the SysKonnect
2849          * SK-9D41.
2850          */
2851         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2852                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2853         else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
2854             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
2855                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2856                     sizeof(hwcfg))) {
2857                         device_printf(sc->bge_dev, "failed to read EEPROM\n");
2858                         error = ENXIO;
2859                         goto fail;
2860                 }
2861                 hwcfg = ntohl(hwcfg);
2862         }
2863
2864         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2865         if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
2866             SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2867                 if (BGE_IS_5714_FAMILY(sc))
2868                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
2869                 else
2870                         sc->bge_flags |= BGE_FLAG_TBI;
2871         }
2872
2873         if (sc->bge_flags & BGE_FLAG_TBI) {
2874                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
2875                     bge_ifmedia_sts);
2876                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
2877                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2878                     0, NULL);
2879                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
2880                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
2881                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2882         } else {
2883                 /*
2884                  * Do transceiver setup and tell the firmware the
2885                  * driver is down so we can try to get access the
2886                  * probe if ASF is running.  Retry a couple of times
2887                  * if we get a conflict with the ASF firmware accessing
2888                  * the PHY.
2889                  */
2890                 trys = 0;
2891                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2892 again:
2893                 bge_asf_driver_up(sc);
2894
2895                 if (mii_phy_probe(dev, &sc->bge_miibus,
2896                     bge_ifmedia_upd, bge_ifmedia_sts)) {
2897                         if (trys++ < 4) {
2898                                 device_printf(sc->bge_dev, "Try again\n");
2899                                 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR,
2900                                     BMCR_RESET);
2901                                 goto again;
2902                         }
2903
2904                         device_printf(sc->bge_dev, "MII without any PHY!\n");
2905                         error = ENXIO;
2906                         goto fail;
2907                 }
2908
2909                 /*
2910                  * Now tell the firmware we are going up after probing the PHY
2911                  */
2912                 if (sc->bge_asf_mode & ASF_STACKUP)
2913                         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2914         }
2915
2916         /*
2917          * When using the BCM5701 in PCI-X mode, data corruption has
2918          * been observed in the first few bytes of some received packets.
2919          * Aligning the packet buffer in memory eliminates the corruption.
2920          * Unfortunately, this misaligns the packet payloads.  On platforms
2921          * which do not support unaligned accesses, we will realign the
2922          * payloads by copying the received packets.
2923          */
2924         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2925             sc->bge_flags & BGE_FLAG_PCIX)
2926                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2927
2928         /*
2929          * Call MI attach routine.
2930          */
2931         ether_ifattach(ifp, eaddr);
2932         callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
2933
2934         /* Tell upper layer we support long frames. */
2935         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2936
2937         /*
2938          * Hookup IRQ last.
2939          */
2940 #if __FreeBSD_version > 700030
2941         if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
2942                 /* Take advantage of single-shot MSI. */
2943                 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
2944                     ~BGE_MSIMODE_ONE_SHOT_DISABLE);
2945                 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
2946                     taskqueue_thread_enqueue, &sc->bge_tq);
2947                 if (sc->bge_tq == NULL) {
2948                         device_printf(dev, "could not create taskqueue.\n");
2949                         ether_ifdetach(ifp);
2950                         error = ENXIO;
2951                         goto fail;
2952                 }
2953                 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq",
2954                     device_get_nameunit(sc->bge_dev));
2955                 error = bus_setup_intr(dev, sc->bge_irq,
2956                     INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
2957                     &sc->bge_intrhand);
2958                 if (error)
2959                         ether_ifdetach(ifp);
2960         } else
2961                 error = bus_setup_intr(dev, sc->bge_irq,
2962                     INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
2963                     &sc->bge_intrhand);
2964 #else
2965         error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2966            bge_intr, sc, &sc->bge_intrhand);
2967 #endif
2968
2969         if (error) {
2970                 bge_detach(dev);
2971                 device_printf(sc->bge_dev, "couldn't set up irq\n");
2972         }
2973
2974         bge_add_sysctls(sc);
2975
2976         return (0);
2977
2978 fail:
2979         bge_release_resources(sc);
2980
2981         return (error);
2982 }
2983
2984 static int
2985 bge_detach(device_t dev)
2986 {
2987         struct bge_softc *sc;
2988         struct ifnet *ifp;
2989
2990         sc = device_get_softc(dev);
2991         ifp = sc->bge_ifp;
2992
2993 #ifdef DEVICE_POLLING
2994         if (ifp->if_capenable & IFCAP_POLLING)
2995                 ether_poll_deregister(ifp);
2996 #endif
2997
2998         BGE_LOCK(sc);
2999         bge_stop(sc);
3000         bge_reset(sc);
3001         BGE_UNLOCK(sc);
3002
3003         callout_drain(&sc->bge_stat_ch);
3004
3005         if (sc->bge_tq)
3006                 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3007         ether_ifdetach(ifp);
3008
3009         if (sc->bge_flags & BGE_FLAG_TBI) {
3010                 ifmedia_removeall(&sc->bge_ifmedia);
3011         } else {
3012                 bus_generic_detach(dev);
3013                 device_delete_child(dev, sc->bge_miibus);
3014         }
3015
3016         bge_release_resources(sc);
3017
3018         return (0);
3019 }
3020
3021 static void
3022 bge_release_resources(struct bge_softc *sc)
3023 {
3024         device_t dev;
3025
3026         dev = sc->bge_dev;
3027
3028         if (sc->bge_tq != NULL)
3029                 taskqueue_free(sc->bge_tq);
3030
3031         if (sc->bge_intrhand != NULL)
3032                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3033
3034         if (sc->bge_irq != NULL)
3035                 bus_release_resource(dev, SYS_RES_IRQ,
3036                     sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
3037
3038         if (sc->bge_flags & BGE_FLAG_MSI)
3039                 pci_release_msi(dev);
3040
3041         if (sc->bge_res != NULL)
3042                 bus_release_resource(dev, SYS_RES_MEMORY,
3043                     BGE_PCI_BAR0, sc->bge_res);
3044
3045         if (sc->bge_ifp != NULL)
3046                 if_free(sc->bge_ifp);
3047
3048         bge_dma_free(sc);
3049
3050         if (mtx_initialized(&sc->bge_mtx))      /* XXX */
3051                 BGE_LOCK_DESTROY(sc);
3052 }
3053
3054 static int
3055 bge_reset(struct bge_softc *sc)
3056 {
3057         device_t dev;
3058         uint32_t cachesize, command, pcistate, reset, val;
3059         void (*write_op)(struct bge_softc *, int, int);
3060         uint16_t devctl;
3061         int i;
3062
3063         dev = sc->bge_dev;
3064
3065         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
3066             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3067                 if (sc->bge_flags & BGE_FLAG_PCIE)
3068                         write_op = bge_writemem_direct;
3069                 else
3070                         write_op = bge_writemem_ind;
3071         } else
3072                 write_op = bge_writereg_ind;
3073
3074         /* Save some important PCI state. */
3075         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
3076         command = pci_read_config(dev, BGE_PCI_CMD, 4);
3077         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3078
3079         pci_write_config(dev, BGE_PCI_MISC_CTL,
3080             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3081             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3082
3083         /* Disable fastboot on controllers that support it. */
3084         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
3085             BGE_IS_5755_PLUS(sc)) {
3086                 if (bootverbose)
3087                         device_printf(sc->bge_dev, "Disabling fastboot\n");
3088                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
3089         }
3090
3091         /*
3092          * Write the magic number to SRAM at offset 0xB50.
3093          * When firmware finishes its initialization it will
3094          * write ~BGE_MAGIC_NUMBER to the same location.
3095          */
3096         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
3097
3098         reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
3099
3100         /* XXX: Broadcom Linux driver. */
3101         if (sc->bge_flags & BGE_FLAG_PCIE) {
3102                 if (CSR_READ_4(sc, 0x7E2C) == 0x60)     /* PCIE 1.0 */
3103                         CSR_WRITE_4(sc, 0x7E2C, 0x20);
3104                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3105                         /* Prevent PCIE link training during global reset */
3106                         CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
3107                         reset |= 1 << 29;
3108                 }
3109         }
3110
3111         /*
3112          * Set GPHY Power Down Override to leave GPHY
3113          * powered up in D0 uninitialized.
3114          */
3115         if (BGE_IS_5705_PLUS(sc))
3116                 reset |= 0x04000000;
3117
3118         /* Issue global reset */
3119         write_op(sc, BGE_MISC_CFG, reset);
3120
3121         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3122                 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3123                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
3124                     val | BGE_VCPU_STATUS_DRV_RESET);
3125                 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
3126                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
3127                     val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
3128         }
3129
3130         DELAY(1000);
3131
3132         /* XXX: Broadcom Linux driver. */
3133         if (sc->bge_flags & BGE_FLAG_PCIE) {
3134                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
3135                         DELAY(500000); /* wait for link training to complete */
3136                         val = pci_read_config(dev, 0xC4, 4);
3137                         pci_write_config(dev, 0xC4, val | (1 << 15), 4);
3138                 }
3139                 devctl = pci_read_config(dev,
3140                     sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
3141                 /* Clear enable no snoop and disable relaxed ordering. */
3142                 devctl &= ~(PCIM_EXP_CTL_RELAXED_ORD_ENABLE |
3143                     PCIM_EXP_CTL_NOSNOOP_ENABLE);
3144                 /* Set PCIE max payload size to 128. */
3145                 devctl &= ~PCIM_EXP_CTL_MAX_PAYLOAD;
3146                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL,
3147                     devctl, 2);
3148                 /* Clear error status. */
3149                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA,
3150                     PCIM_EXP_STA_CORRECTABLE_ERROR |
3151                     PCIM_EXP_STA_NON_FATAL_ERROR | PCIM_EXP_STA_FATAL_ERROR |
3152                     PCIM_EXP_STA_UNSUPPORTED_REQ, 2);
3153         }
3154
3155         /* Reset some of the PCI state that got zapped by reset. */
3156         pci_write_config(dev, BGE_PCI_MISC_CTL,
3157             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3158             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3159         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
3160         pci_write_config(dev, BGE_PCI_CMD, command, 4);
3161         write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
3162         /*
3163          * Disable PCI-X relaxed ordering to ensure status block update
3164          * comes first then packet buffer DMA. Otherwise driver may
3165          * read stale status block.
3166          */
3167         if (sc->bge_flags & BGE_FLAG_PCIX) {
3168                 devctl = pci_read_config(dev,
3169                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
3170                 devctl &= ~PCIXM_COMMAND_ERO;
3171                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
3172                         devctl &= ~PCIXM_COMMAND_MAX_READ;
3173                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
3174                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3175                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
3176                             PCIXM_COMMAND_MAX_READ);
3177                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
3178                 }
3179                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
3180                     devctl, 2);
3181         }
3182         /* Re-enable MSI, if neccesary, and enable the memory arbiter. */
3183         if (BGE_IS_5714_FAMILY(sc)) {
3184                 /* This chip disables MSI on reset. */
3185                 if (sc->bge_flags & BGE_FLAG_MSI) {
3186                         val = pci_read_config(dev,
3187                             sc->bge_msicap + PCIR_MSI_CTRL, 2);
3188                         pci_write_config(dev,
3189                             sc->bge_msicap + PCIR_MSI_CTRL,
3190                             val | PCIM_MSICTRL_MSI_ENABLE, 2);
3191                         val = CSR_READ_4(sc, BGE_MSI_MODE);
3192                         CSR_WRITE_4(sc, BGE_MSI_MODE,
3193                             val | BGE_MSIMODE_ENABLE);
3194                 }
3195                 val = CSR_READ_4(sc, BGE_MARB_MODE);
3196                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
3197         } else
3198                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3199
3200         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3201                 for (i = 0; i < BGE_TIMEOUT; i++) {
3202                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3203                         if (val & BGE_VCPU_STATUS_INIT_DONE)
3204                                 break;
3205                         DELAY(100);
3206                 }
3207                 if (i == BGE_TIMEOUT) {
3208                         device_printf(sc->bge_dev, "reset timed out\n");
3209                         return (1);
3210                 }
3211         } else {
3212                 /*
3213                  * Poll until we see the 1's complement of the magic number.
3214                  * This indicates that the firmware initialization is complete.
3215                  * We expect this to fail if no chip containing the Ethernet
3216                  * address is fitted though.
3217                  */
3218                 for (i = 0; i < BGE_TIMEOUT; i++) {
3219                         DELAY(10);
3220                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
3221                         if (val == ~BGE_MAGIC_NUMBER)
3222                                 break;
3223                 }
3224
3225                 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
3226                         device_printf(sc->bge_dev, "firmware handshake timed out, "
3227                             "found 0x%08x\n", val);
3228         }
3229
3230         /*
3231          * XXX Wait for the value of the PCISTATE register to
3232          * return to its original pre-reset state. This is a
3233          * fairly good indicator of reset completion. If we don't
3234          * wait for the reset to fully complete, trying to read
3235          * from the device's non-PCI registers may yield garbage
3236          * results.
3237          */
3238         for (i = 0; i < BGE_TIMEOUT; i++) {
3239                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
3240                         break;
3241                 DELAY(10);
3242         }
3243
3244         if (sc->bge_flags & BGE_FLAG_PCIE) {
3245                 reset = bge_readmem_ind(sc, 0x7C00);
3246                 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25));
3247         }
3248
3249         /* Fix up byte swapping. */
3250         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
3251             BGE_MODECTL_BYTESWAP_DATA);
3252
3253         /* Tell the ASF firmware we are up */
3254         if (sc->bge_asf_mode & ASF_STACKUP)
3255                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3256
3257         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
3258
3259         /*
3260          * The 5704 in TBI mode apparently needs some special
3261          * adjustment to insure the SERDES drive level is set
3262          * to 1.2V.
3263          */
3264         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
3265             sc->bge_flags & BGE_FLAG_TBI) {
3266                 val = CSR_READ_4(sc, BGE_SERDES_CFG);
3267                 val = (val & ~0xFFF) | 0x880;
3268                 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
3269         }
3270
3271         /* XXX: Broadcom Linux driver. */
3272         if (sc->bge_flags & BGE_FLAG_PCIE &&
3273             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3274                 val = CSR_READ_4(sc, 0x7C00);
3275                 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
3276         }
3277         DELAY(10000);
3278
3279         return(0);
3280 }
3281
3282 static __inline void
3283 bge_rxreuse_std(struct bge_softc *sc, int i)
3284 {
3285         struct bge_rx_bd *r;
3286
3287         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
3288         r->bge_flags = BGE_RXBDFLAG_END;
3289         r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
3290         r->bge_idx = i;
3291         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3292 }
3293
3294 static __inline void
3295 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
3296 {
3297         struct bge_extrx_bd *r;
3298
3299         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
3300         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
3301         r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
3302         r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
3303         r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
3304         r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
3305         r->bge_idx = i;
3306         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3307 }
3308
3309 /*
3310  * Frame reception handling. This is called if there's a frame
3311  * on the receive return list.
3312  *
3313  * Note: we have to be able to handle two possibilities here:
3314  * 1) the frame is from the jumbo receive ring
3315  * 2) the frame is from the standard receive ring
3316  */
3317
3318 static int
3319 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
3320 {
3321         struct ifnet *ifp;
3322         int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
3323         uint16_t rx_cons;
3324
3325         rx_cons = sc->bge_rx_saved_considx;
3326
3327         /* Nothing to do. */
3328         if (rx_cons == rx_prod)
3329                 return (rx_npkts);
3330
3331         ifp = sc->bge_ifp;
3332
3333         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3334             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
3335         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3336             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
3337         if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
3338             (MCLBYTES - ETHER_ALIGN))
3339                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3340                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
3341
3342         while (rx_cons != rx_prod) {
3343                 struct bge_rx_bd        *cur_rx;
3344                 uint32_t                rxidx;
3345                 struct mbuf             *m = NULL;
3346                 uint16_t                vlan_tag = 0;
3347                 int                     have_tag = 0;
3348
3349 #ifdef DEVICE_POLLING
3350                 if (ifp->if_capenable & IFCAP_POLLING) {
3351                         if (sc->rxcycles <= 0)
3352                                 break;
3353                         sc->rxcycles--;
3354                 }
3355 #endif
3356
3357                 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
3358
3359                 rxidx = cur_rx->bge_idx;
3360                 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
3361
3362                 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
3363                     cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
3364                         have_tag = 1;
3365                         vlan_tag = cur_rx->bge_vlan_tag;
3366                 }
3367
3368                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
3369                         jumbocnt++;
3370                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
3371                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3372                                 bge_rxreuse_jumbo(sc, rxidx);
3373                                 continue;
3374                         }
3375                         if (bge_newbuf_jumbo(sc, rxidx) != 0) {
3376                                 bge_rxreuse_jumbo(sc, rxidx);
3377                                 ifp->if_iqdrops++;
3378                                 continue;
3379                         }
3380                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3381                 } else {
3382                         stdcnt++;
3383                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
3384                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3385                                 bge_rxreuse_std(sc, rxidx);
3386                                 continue;
3387                         }
3388                         if (bge_newbuf_std(sc, rxidx) != 0) {
3389                                 bge_rxreuse_std(sc, rxidx);
3390                                 ifp->if_iqdrops++;
3391                                 continue;
3392                         }
3393                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3394                 }
3395
3396                 ifp->if_ipackets++;
3397 #ifndef __NO_STRICT_ALIGNMENT
3398                 /*
3399                  * For architectures with strict alignment we must make sure
3400                  * the payload is aligned.
3401                  */
3402                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
3403                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
3404                             cur_rx->bge_len);
3405                         m->m_data += ETHER_ALIGN;
3406                 }
3407 #endif
3408                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3409                 m->m_pkthdr.rcvif = ifp;
3410
3411                 if (ifp->if_capenable & IFCAP_RXCSUM) {
3412                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3413                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3414                                 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
3415                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3416                         }
3417                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
3418                             m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
3419                                 m->m_pkthdr.csum_data =
3420                                     cur_rx->bge_tcp_udp_csum;
3421                                 m->m_pkthdr.csum_flags |=
3422                                     CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
3423                         }
3424                 }
3425
3426                 /*
3427                  * If we received a packet with a vlan tag,
3428                  * attach that information to the packet.
3429                  */
3430                 if (have_tag) {
3431 #if __FreeBSD_version > 700022
3432                         m->m_pkthdr.ether_vtag = vlan_tag;
3433                         m->m_flags |= M_VLANTAG;
3434 #else
3435                         VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag);
3436                         if (m == NULL)
3437                                 continue;
3438 #endif
3439                 }
3440
3441                 if (holdlck != 0) {
3442                         BGE_UNLOCK(sc);
3443                         (*ifp->if_input)(ifp, m);
3444                         BGE_LOCK(sc);
3445                 } else
3446                         (*ifp->if_input)(ifp, m);
3447                 rx_npkts++;
3448
3449                 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
3450                         return (rx_npkts);
3451         }
3452
3453         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3454             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
3455         if (stdcnt > 0)
3456                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3457                     sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
3458
3459         if (jumbocnt > 0)
3460                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3461                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
3462
3463         sc->bge_rx_saved_considx = rx_cons;
3464         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3465         if (stdcnt)
3466                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
3467         if (jumbocnt)
3468                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
3469 #ifdef notyet
3470         /*
3471          * This register wraps very quickly under heavy packet drops.
3472          * If you need correct statistics, you can enable this check.
3473          */
3474         if (BGE_IS_5705_PLUS(sc))
3475                 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3476 #endif
3477         return (rx_npkts);
3478 }
3479
3480 static void
3481 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
3482 {
3483         struct bge_tx_bd *cur_tx = NULL;
3484         struct ifnet *ifp;
3485
3486         BGE_LOCK_ASSERT(sc);
3487
3488         /* Nothing to do. */
3489         if (sc->bge_tx_saved_considx == tx_cons)
3490                 return;
3491
3492         ifp = sc->bge_ifp;
3493
3494         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
3495             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
3496         /*
3497          * Go through our tx ring and free mbufs for those
3498          * frames that have been sent.
3499          */
3500         while (sc->bge_tx_saved_considx != tx_cons) {
3501                 uint32_t                idx = 0;
3502
3503                 idx = sc->bge_tx_saved_considx;
3504                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
3505                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
3506                         ifp->if_opackets++;
3507                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
3508                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
3509                             sc->bge_cdata.bge_tx_dmamap[idx],
3510                             BUS_DMASYNC_POSTWRITE);
3511                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
3512                             sc->bge_cdata.bge_tx_dmamap[idx]);
3513                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
3514                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
3515                 }
3516                 sc->bge_txcnt--;
3517                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3518         }
3519
3520         if (cur_tx != NULL)
3521                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3522         if (sc->bge_txcnt == 0)
3523                 sc->bge_timer = 0;
3524 }
3525
3526 #ifdef DEVICE_POLLING
3527 static int
3528 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3529 {
3530         struct bge_softc *sc = ifp->if_softc;
3531         uint16_t rx_prod, tx_cons;
3532         uint32_t statusword;
3533         int rx_npkts = 0;
3534
3535         BGE_LOCK(sc);
3536         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3537                 BGE_UNLOCK(sc);
3538                 return (rx_npkts);
3539         }
3540
3541         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3542             sc->bge_cdata.bge_status_map,
3543             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3544         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3545         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3546
3547         statusword = atomic_readandclear_32(
3548             &sc->bge_ldata.bge_status_block->bge_status);
3549
3550         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3551             sc->bge_cdata.bge_status_map,
3552             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3553
3554         /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
3555         if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
3556                 sc->bge_link_evt++;
3557
3558         if (cmd == POLL_AND_CHECK_STATUS)
3559                 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3560                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3561                     sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
3562                         bge_link_upd(sc);
3563
3564         sc->rxcycles = count;
3565         rx_npkts = bge_rxeof(sc, rx_prod, 1);
3566         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3567                 BGE_UNLOCK(sc);
3568                 return (rx_npkts);
3569         }
3570         bge_txeof(sc, tx_cons);
3571         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3572                 bge_start_locked(ifp);
3573
3574         BGE_UNLOCK(sc);
3575         return (rx_npkts);
3576 }
3577 #endif /* DEVICE_POLLING */
3578
3579 static int
3580 bge_msi_intr(void *arg)
3581 {
3582         struct bge_softc *sc;
3583
3584         sc = (struct bge_softc *)arg;
3585         /*
3586          * This interrupt is not shared and controller already
3587          * disabled further interrupt.
3588          */
3589         taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
3590         return (FILTER_HANDLED);
3591 }
3592
3593 static void
3594 bge_intr_task(void *arg, int pending)
3595 {
3596         struct bge_softc *sc;
3597         struct ifnet *ifp;
3598         uint32_t status;
3599         uint16_t rx_prod, tx_cons;
3600
3601         sc = (struct bge_softc *)arg;
3602         ifp = sc->bge_ifp;
3603
3604         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3605                 return;
3606
3607         /* Get updated status block. */
3608         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3609             sc->bge_cdata.bge_status_map,
3610             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3611
3612         /* Save producer/consumer indexess. */
3613         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3614         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3615         status = sc->bge_ldata.bge_status_block->bge_status;
3616         sc->bge_ldata.bge_status_block->bge_status = 0;
3617         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3618             sc->bge_cdata.bge_status_map,
3619             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3620         /* Let controller work. */
3621         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3622
3623         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) {
3624                 BGE_LOCK(sc);
3625                 bge_link_upd(sc);
3626                 BGE_UNLOCK(sc);
3627         }
3628         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3629                 /* Check RX return ring producer/consumer. */
3630                 bge_rxeof(sc, rx_prod, 0);
3631         }
3632         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3633                 BGE_LOCK(sc);
3634                 /* Check TX ring producer/consumer. */
3635                 bge_txeof(sc, tx_cons);
3636                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3637                         bge_start_locked(ifp);
3638                 BGE_UNLOCK(sc);
3639         }
3640 }
3641
3642 static void
3643 bge_intr(void *xsc)
3644 {
3645         struct bge_softc *sc;
3646         struct ifnet *ifp;
3647         uint32_t statusword;
3648         uint16_t rx_prod, tx_cons;
3649
3650         sc = xsc;
3651
3652         BGE_LOCK(sc);
3653
3654         ifp = sc->bge_ifp;
3655
3656 #ifdef DEVICE_POLLING
3657         if (ifp->if_capenable & IFCAP_POLLING) {
3658                 BGE_UNLOCK(sc);
3659                 return;
3660         }
3661 #endif
3662
3663         /*
3664          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
3665          * disable interrupts by writing nonzero like we used to, since with
3666          * our current organization this just gives complications and
3667          * pessimizations for re-enabling interrupts.  We used to have races
3668          * instead of the necessary complications.  Disabling interrupts
3669          * would just reduce the chance of a status update while we are
3670          * running (by switching to the interrupt-mode coalescence
3671          * parameters), but this chance is already very low so it is more
3672          * efficient to get another interrupt than prevent it.
3673          *
3674          * We do the ack first to ensure another interrupt if there is a
3675          * status update after the ack.  We don't check for the status
3676          * changing later because it is more efficient to get another
3677          * interrupt than prevent it, not quite as above (not checking is
3678          * a smaller optimization than not toggling the interrupt enable,
3679          * since checking doesn't involve PCI accesses and toggling require
3680          * the status check).  So toggling would probably be a pessimization
3681          * even with MSI.  It would only be needed for using a task queue.
3682          */
3683         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3684
3685         /*
3686          * Do the mandatory PCI flush as well as get the link status.
3687          */
3688         statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
3689
3690         /* Make sure the descriptor ring indexes are coherent. */
3691         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3692             sc->bge_cdata.bge_status_map,
3693             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3694         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3695         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3696         sc->bge_ldata.bge_status_block->bge_status = 0;
3697         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3698             sc->bge_cdata.bge_status_map,
3699             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3700
3701         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3702             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3703             statusword || sc->bge_link_evt)
3704                 bge_link_upd(sc);
3705
3706         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3707                 /* Check RX return ring producer/consumer. */
3708                 bge_rxeof(sc, rx_prod, 1);
3709         }
3710
3711         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3712                 /* Check TX ring producer/consumer. */
3713                 bge_txeof(sc, tx_cons);
3714         }
3715
3716         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3717             !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3718                 bge_start_locked(ifp);
3719
3720         BGE_UNLOCK(sc);
3721 }
3722
3723 static void
3724 bge_asf_driver_up(struct bge_softc *sc)
3725 {
3726         if (sc->bge_asf_mode & ASF_STACKUP) {
3727                 /* Send ASF heartbeat aprox. every 2s */
3728                 if (sc->bge_asf_count)
3729                         sc->bge_asf_count --;
3730                 else {
3731                         sc->bge_asf_count = 2;
3732                         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW,
3733                             BGE_FW_DRV_ALIVE);
3734                         bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4);
3735                         bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3);
3736                         CSR_WRITE_4(sc, BGE_CPU_EVENT,
3737                             CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
3738                 }
3739         }
3740 }
3741
3742 static void
3743 bge_tick(void *xsc)
3744 {
3745         struct bge_softc *sc = xsc;
3746         struct mii_data *mii = NULL;
3747
3748         BGE_LOCK_ASSERT(sc);
3749
3750         /* Synchronize with possible callout reset/stop. */
3751         if (callout_pending(&sc->bge_stat_ch) ||
3752             !callout_active(&sc->bge_stat_ch))
3753                 return;
3754
3755         if (BGE_IS_5705_PLUS(sc))
3756                 bge_stats_update_regs(sc);
3757         else
3758                 bge_stats_update(sc);
3759
3760         if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
3761                 mii = device_get_softc(sc->bge_miibus);
3762                 /*
3763                  * Do not touch PHY if we have link up. This could break
3764                  * IPMI/ASF mode or produce extra input errors
3765                  * (extra errors was reported for bcm5701 & bcm5704).
3766                  */
3767                 if (!sc->bge_link)
3768                         mii_tick(mii);
3769         } else {
3770                 /*
3771                  * Since in TBI mode auto-polling can't be used we should poll
3772                  * link status manually. Here we register pending link event
3773                  * and trigger interrupt.
3774                  */
3775 #ifdef DEVICE_POLLING
3776                 /* In polling mode we poll link state in bge_poll(). */
3777                 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
3778 #endif
3779                 {
3780                 sc->bge_link_evt++;
3781                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3782                     sc->bge_flags & BGE_FLAG_5788)
3783                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3784                 else
3785                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3786                 }
3787         }
3788
3789         bge_asf_driver_up(sc);
3790         bge_watchdog(sc);
3791
3792         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
3793 }
3794
3795 static void
3796 bge_stats_update_regs(struct bge_softc *sc)
3797 {
3798         struct ifnet *ifp;
3799
3800         ifp = sc->bge_ifp;
3801
3802         ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS +
3803             offsetof(struct bge_mac_stats_regs, etherStatsCollisions));
3804
3805         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
3806         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3807         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
3808 }
3809
3810 static void
3811 bge_stats_update(struct bge_softc *sc)
3812 {
3813         struct ifnet *ifp;
3814         bus_size_t stats;
3815         uint32_t cnt;   /* current register value */
3816
3817         ifp = sc->bge_ifp;
3818
3819         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3820
3821 #define READ_STAT(sc, stats, stat) \
3822         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3823
3824         cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
3825         ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
3826         sc->bge_tx_collisions = cnt;
3827
3828         cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
3829         ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
3830         sc->bge_rx_discards = cnt;
3831
3832         cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
3833         ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
3834         sc->bge_tx_discards = cnt;
3835
3836 #undef  READ_STAT
3837 }
3838
3839 /*
3840  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
3841  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
3842  * but when such padded frames employ the bge IP/TCP checksum offload,
3843  * the hardware checksum assist gives incorrect results (possibly
3844  * from incorporating its own padding into the UDP/TCP checksum; who knows).
3845  * If we pad such runts with zeros, the onboard checksum comes out correct.
3846  */
3847 static __inline int
3848 bge_cksum_pad(struct mbuf *m)
3849 {
3850         int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
3851         struct mbuf *last;
3852
3853         /* If there's only the packet-header and we can pad there, use it. */
3854         if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
3855             M_TRAILINGSPACE(m) >= padlen) {
3856                 last = m;
3857         } else {
3858                 /*
3859                  * Walk packet chain to find last mbuf. We will either
3860                  * pad there, or append a new mbuf and pad it.
3861                  */
3862                 for (last = m; last->m_next != NULL; last = last->m_next);
3863                 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
3864                         /* Allocate new empty mbuf, pad it. Compact later. */
3865                         struct mbuf *n;
3866
3867                         MGET(n, M_DONTWAIT, MT_DATA);
3868                         if (n == NULL)
3869                                 return (ENOBUFS);
3870                         n->m_len = 0;
3871                         last->m_next = n;
3872                         last = n;
3873                 }
3874         }
3875
3876         /* Now zero the pad area, to avoid the bge cksum-assist bug. */
3877         memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
3878         last->m_len += padlen;
3879         m->m_pkthdr.len += padlen;
3880
3881         return (0);
3882 }
3883
3884 static struct mbuf *
3885 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss)
3886 {
3887         struct ip *ip;
3888         struct tcphdr *tcp;
3889         struct mbuf *n;
3890         uint16_t hlen;
3891         uint32_t poff;
3892
3893         if (M_WRITABLE(m) == 0) {
3894                 /* Get a writable copy. */
3895                 n = m_dup(m, M_DONTWAIT);
3896                 m_freem(m);
3897                 if (n == NULL)
3898                         return (NULL);
3899                 m = n;
3900         }
3901         m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
3902         if (m == NULL)
3903                 return (NULL);
3904         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
3905         poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
3906         m = m_pullup(m, poff + sizeof(struct tcphdr));
3907         if (m == NULL)
3908                 return (NULL);
3909         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
3910         m = m_pullup(m, poff + (tcp->th_off << 2));
3911         if (m == NULL)
3912                 return (NULL);
3913         /*
3914          * It seems controller doesn't modify IP length and TCP pseudo
3915          * checksum. These checksum computed by upper stack should be 0.
3916          */
3917         *mss = m->m_pkthdr.tso_segsz;
3918         ip->ip_sum = 0;
3919         ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
3920         /* Clear pseudo checksum computed by TCP stack. */
3921         tcp->th_sum = 0;
3922         /*
3923          * Broadcom controllers uses different descriptor format for
3924          * TSO depending on ASIC revision. Due to TSO-capable firmware
3925          * license issue and lower performance of firmware based TSO
3926          * we only support hardware based TSO which is applicable for
3927          * BCM5755 or newer controllers. Hardware based TSO uses 11
3928          * bits to store MSS and upper 5 bits are used to store IP/TCP
3929          * header length(including IP/TCP options). The header length
3930          * is expressed as 32 bits unit.
3931          */
3932         hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
3933         *mss |= (hlen << 11);
3934         return (m);
3935 }
3936
3937 /*
3938  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
3939  * pointers to descriptors.
3940  */
3941 static int
3942 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
3943 {
3944         bus_dma_segment_t       segs[BGE_NSEG_NEW];
3945         bus_dmamap_t            map;
3946         struct bge_tx_bd        *d;
3947         struct mbuf             *m = *m_head;
3948         uint32_t                idx = *txidx;
3949         uint16_t                csum_flags, mss, vlan_tag;
3950         int                     nsegs, i, error;
3951
3952         csum_flags = 0;
3953         mss = 0;
3954         vlan_tag = 0;
3955         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
3956                 *m_head = m = bge_setup_tso(sc, m, &mss);
3957                 if (*m_head == NULL)
3958                         return (ENOBUFS);
3959                 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
3960                     BGE_TXBDFLAG_CPU_POST_DMA;
3961         } else if ((m->m_pkthdr.csum_flags & BGE_CSUM_FEATURES) != 0) {
3962                 if (m->m_pkthdr.csum_flags & CSUM_IP)
3963                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3964                 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
3965                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3966                         if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
3967                             (error = bge_cksum_pad(m)) != 0) {
3968                                 m_freem(m);
3969                                 *m_head = NULL;
3970                                 return (error);
3971                         }
3972                 }
3973                 if (m->m_flags & M_LASTFRAG)
3974                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3975                 else if (m->m_flags & M_FRAG)
3976                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3977         }
3978
3979         if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
3980             sc->bge_forced_collapse > 0 &&
3981             (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
3982                 /*
3983                  * Forcedly collapse mbuf chains to overcome hardware
3984                  * limitation which only support a single outstanding
3985                  * DMA read operation.
3986                  */
3987                 if (sc->bge_forced_collapse == 1)
3988                         m = m_defrag(m, M_DONTWAIT);
3989                 else
3990                         m = m_collapse(m, M_DONTWAIT, sc->bge_forced_collapse);
3991                 if (m == NULL)
3992                         m = *m_head;
3993                 *m_head = m;
3994         }
3995
3996         map = sc->bge_cdata.bge_tx_dmamap[idx];
3997         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
3998             &nsegs, BUS_DMA_NOWAIT);
3999         if (error == EFBIG) {
4000                 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW);
4001                 if (m == NULL) {
4002                         m_freem(*m_head);
4003                         *m_head = NULL;
4004                         return (ENOBUFS);
4005                 }
4006                 *m_head = m;
4007                 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
4008                     m, segs, &nsegs, BUS_DMA_NOWAIT);
4009                 if (error) {
4010                         m_freem(m);
4011                         *m_head = NULL;
4012                         return (error);
4013                 }
4014         } else if (error != 0)
4015                 return (error);
4016
4017         /* Check if we have enough free send BDs. */
4018         if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
4019                 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
4020                 return (ENOBUFS);
4021         }
4022
4023         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
4024
4025 #if __FreeBSD_version > 700022
4026         if (m->m_flags & M_VLANTAG) {
4027                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
4028                 vlan_tag = m->m_pkthdr.ether_vtag;
4029         }
4030 #else
4031         {
4032                 struct m_tag            *mtag;
4033
4034                 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) {
4035                         csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
4036                         vlan_tag = VLAN_TAG_VALUE(mtag);
4037                 }
4038         }
4039 #endif
4040         for (i = 0; ; i++) {
4041                 d = &sc->bge_ldata.bge_tx_ring[idx];
4042                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
4043                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
4044                 d->bge_len = segs[i].ds_len;
4045                 d->bge_flags = csum_flags;
4046                 d->bge_vlan_tag = vlan_tag;
4047                 d->bge_mss = mss;
4048                 if (i == nsegs - 1)
4049                         break;
4050                 BGE_INC(idx, BGE_TX_RING_CNT);
4051         }
4052
4053         /* Mark the last segment as end of packet... */
4054         d->bge_flags |= BGE_TXBDFLAG_END;
4055
4056         /*
4057          * Insure that the map for this transmission
4058          * is placed at the array index of the last descriptor
4059          * in this chain.
4060          */
4061         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
4062         sc->bge_cdata.bge_tx_dmamap[idx] = map;
4063         sc->bge_cdata.bge_tx_chain[idx] = m;
4064         sc->bge_txcnt += nsegs;
4065
4066         BGE_INC(idx, BGE_TX_RING_CNT);
4067         *txidx = idx;
4068
4069         return (0);
4070 }
4071
4072 /*
4073  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4074  * to the mbuf data regions directly in the transmit descriptors.
4075  */
4076 static void
4077 bge_start_locked(struct ifnet *ifp)
4078 {
4079         struct bge_softc *sc;
4080         struct mbuf *m_head;
4081         uint32_t prodidx;
4082         int count;
4083
4084         sc = ifp->if_softc;
4085         BGE_LOCK_ASSERT(sc);
4086
4087         if (!sc->bge_link ||
4088             (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4089             IFF_DRV_RUNNING)
4090                 return;
4091
4092         prodidx = sc->bge_tx_prodidx;
4093
4094         for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
4095                 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
4096                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4097                         break;
4098                 }
4099                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
4100                 if (m_head == NULL)
4101                         break;
4102
4103                 /*
4104                  * XXX
4105                  * The code inside the if() block is never reached since we
4106                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
4107                  * requests to checksum TCP/UDP in a fragmented packet.
4108                  *
4109                  * XXX
4110                  * safety overkill.  If this is a fragmented packet chain
4111                  * with delayed TCP/UDP checksums, then only encapsulate
4112                  * it if we have enough descriptors to handle the entire
4113                  * chain at once.
4114                  * (paranoia -- may not actually be needed)
4115                  */
4116                 if (m_head->m_flags & M_FIRSTFRAG &&
4117                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
4118                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
4119                             m_head->m_pkthdr.csum_data + 16) {
4120                                 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4121                                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4122                                 break;
4123                         }
4124                 }
4125
4126                 /*
4127                  * Pack the data into the transmit ring. If we
4128                  * don't have room, set the OACTIVE flag and wait
4129                  * for the NIC to drain the ring.
4130                  */
4131                 if (bge_encap(sc, &m_head, &prodidx)) {
4132                         if (m_head == NULL)
4133                                 break;
4134                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4135                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4136                         break;
4137                 }
4138                 ++count;
4139
4140                 /*
4141                  * If there's a BPF listener, bounce a copy of this frame
4142                  * to him.
4143                  */
4144 #ifdef ETHER_BPF_MTAP
4145                 ETHER_BPF_MTAP(ifp, m_head);
4146 #else
4147                 BPF_MTAP(ifp, m_head);
4148 #endif
4149         }
4150
4151         if (count > 0) {
4152                 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4153                     sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
4154                 /* Transmit. */
4155                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4156                 /* 5700 b2 errata */
4157                 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
4158                         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4159
4160                 sc->bge_tx_prodidx = prodidx;
4161
4162                 /*
4163                  * Set a timeout in case the chip goes out to lunch.
4164                  */
4165                 sc->bge_timer = 5;
4166         }
4167 }
4168
4169 /*
4170  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4171  * to the mbuf data regions directly in the transmit descriptors.
4172  */
4173 static void
4174 bge_start(struct ifnet *ifp)
4175 {
4176         struct bge_softc *sc;
4177
4178         sc = ifp->if_softc;
4179         BGE_LOCK(sc);
4180         bge_start_locked(ifp);
4181         BGE_UNLOCK(sc);
4182 }
4183
4184 static void
4185 bge_init_locked(struct bge_softc *sc)
4186 {
4187         struct ifnet *ifp;
4188         uint16_t *m;
4189
4190         BGE_LOCK_ASSERT(sc);
4191
4192         ifp = sc->bge_ifp;
4193
4194         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4195                 return;
4196
4197         /* Cancel pending I/O and flush buffers. */
4198         bge_stop(sc);
4199
4200         bge_stop_fw(sc);
4201         bge_sig_pre_reset(sc, BGE_RESET_START);
4202         bge_reset(sc);
4203         bge_sig_legacy(sc, BGE_RESET_START);
4204         bge_sig_post_reset(sc, BGE_RESET_START);
4205
4206         bge_chipinit(sc);
4207
4208         /*
4209          * Init the various state machines, ring
4210          * control blocks and firmware.
4211          */
4212         if (bge_blockinit(sc)) {
4213                 device_printf(sc->bge_dev, "initialization failure\n");
4214                 return;
4215         }
4216
4217         ifp = sc->bge_ifp;
4218
4219         /* Specify MTU. */
4220         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
4221             ETHER_HDR_LEN + ETHER_CRC_LEN +
4222             (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
4223
4224         /* Load our MAC address. */
4225         m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
4226         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
4227         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
4228
4229         /* Program promiscuous mode. */
4230         bge_setpromisc(sc);
4231
4232         /* Program multicast filter. */
4233         bge_setmulti(sc);
4234
4235         /* Program VLAN tag stripping. */
4236         bge_setvlan(sc);
4237
4238         /* Init RX ring. */
4239         if (bge_init_rx_ring_std(sc) != 0) {
4240                 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
4241                 bge_stop(sc);
4242                 return;
4243         }
4244
4245         /*
4246          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
4247          * memory to insure that the chip has in fact read the first
4248          * entry of the ring.
4249          */
4250         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
4251                 uint32_t                v, i;
4252                 for (i = 0; i < 10; i++) {
4253                         DELAY(20);
4254                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
4255                         if (v == (MCLBYTES - ETHER_ALIGN))
4256                                 break;
4257                 }
4258                 if (i == 10)
4259                         device_printf (sc->bge_dev,
4260                             "5705 A0 chip failed to load RX ring\n");
4261         }
4262
4263         /* Init jumbo RX ring. */
4264         if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
4265             (MCLBYTES - ETHER_ALIGN)) {
4266                 if (bge_init_rx_ring_jumbo(sc) != 0) {
4267                         device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
4268                         bge_stop(sc);
4269                         return;
4270                 }
4271         }
4272
4273         /* Init our RX return ring index. */
4274         sc->bge_rx_saved_considx = 0;
4275
4276         /* Init our RX/TX stat counters. */
4277         sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
4278
4279         /* Init TX ring. */
4280         bge_init_tx_ring(sc);
4281
4282         /* Turn on transmitter. */
4283         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
4284
4285         /* Turn on receiver. */
4286         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4287
4288         /* Tell firmware we're alive. */
4289         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4290
4291 #ifdef DEVICE_POLLING
4292         /* Disable interrupts if we are polling. */
4293         if (ifp->if_capenable & IFCAP_POLLING) {
4294                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4295                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4296                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4297         } else
4298 #endif
4299
4300         /* Enable host interrupts. */
4301         {
4302         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
4303         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4304         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4305         }
4306
4307         bge_ifmedia_upd_locked(ifp);
4308
4309         ifp->if_drv_flags |= IFF_DRV_RUNNING;
4310         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4311
4312         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4313 }
4314
4315 static void
4316 bge_init(void *xsc)
4317 {
4318         struct bge_softc *sc = xsc;
4319
4320         BGE_LOCK(sc);
4321         bge_init_locked(sc);
4322         BGE_UNLOCK(sc);
4323 }
4324
4325 /*
4326  * Set media options.
4327  */
4328 static int
4329 bge_ifmedia_upd(struct ifnet *ifp)
4330 {
4331         struct bge_softc *sc = ifp->if_softc;
4332         int res;
4333
4334         BGE_LOCK(sc);
4335         res = bge_ifmedia_upd_locked(ifp);
4336         BGE_UNLOCK(sc);
4337
4338         return (res);
4339 }
4340
4341 static int
4342 bge_ifmedia_upd_locked(struct ifnet *ifp)
4343 {
4344         struct bge_softc *sc = ifp->if_softc;
4345         struct mii_data *mii;
4346         struct mii_softc *miisc;
4347         struct ifmedia *ifm;
4348
4349         BGE_LOCK_ASSERT(sc);
4350
4351         ifm = &sc->bge_ifmedia;
4352
4353         /* If this is a 1000baseX NIC, enable the TBI port. */
4354         if (sc->bge_flags & BGE_FLAG_TBI) {
4355                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
4356                         return (EINVAL);
4357                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
4358                 case IFM_AUTO:
4359                         /*
4360                          * The BCM5704 ASIC appears to have a special
4361                          * mechanism for programming the autoneg
4362                          * advertisement registers in TBI mode.
4363                          */
4364                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4365                                 uint32_t sgdig;
4366                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
4367                                 if (sgdig & BGE_SGDIGSTS_DONE) {
4368                                         CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
4369                                         sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
4370                                         sgdig |= BGE_SGDIGCFG_AUTO |
4371                                             BGE_SGDIGCFG_PAUSE_CAP |
4372                                             BGE_SGDIGCFG_ASYM_PAUSE;
4373                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG,
4374                                             sgdig | BGE_SGDIGCFG_SEND);
4375                                         DELAY(5);
4376                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
4377                                 }
4378                         }
4379                         break;
4380                 case IFM_1000_SX:
4381                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
4382                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
4383                                     BGE_MACMODE_HALF_DUPLEX);
4384                         } else {
4385                                 BGE_SETBIT(sc, BGE_MAC_MODE,
4386                                     BGE_MACMODE_HALF_DUPLEX);
4387                         }
4388                         break;
4389                 default:
4390                         return (EINVAL);
4391                 }
4392                 return (0);
4393         }
4394
4395         sc->bge_link_evt++;
4396         mii = device_get_softc(sc->bge_miibus);
4397         if (mii->mii_instance)
4398                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4399                         mii_phy_reset(miisc);
4400         mii_mediachg(mii);
4401
4402         /*
4403          * Force an interrupt so that we will call bge_link_upd
4404          * if needed and clear any pending link state attention.
4405          * Without this we are not getting any further interrupts
4406          * for link state changes and thus will not UP the link and
4407          * not be able to send in bge_start_locked. The only
4408          * way to get things working was to receive a packet and
4409          * get an RX intr.
4410          * bge_tick should help for fiber cards and we might not
4411          * need to do this here if BGE_FLAG_TBI is set but as
4412          * we poll for fiber anyway it should not harm.
4413          */
4414         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4415             sc->bge_flags & BGE_FLAG_5788)
4416                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4417         else
4418                 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4419
4420         return (0);
4421 }
4422
4423 /*
4424  * Report current media status.
4425  */
4426 static void
4427 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4428 {
4429         struct bge_softc *sc = ifp->if_softc;
4430         struct mii_data *mii;
4431
4432         BGE_LOCK(sc);
4433
4434         if (sc->bge_flags & BGE_FLAG_TBI) {
4435                 ifmr->ifm_status = IFM_AVALID;
4436                 ifmr->ifm_active = IFM_ETHER;
4437                 if (CSR_READ_4(sc, BGE_MAC_STS) &
4438                     BGE_MACSTAT_TBI_PCS_SYNCHED)
4439                         ifmr->ifm_status |= IFM_ACTIVE;
4440                 else {
4441                         ifmr->ifm_active |= IFM_NONE;
4442                         BGE_UNLOCK(sc);
4443                         return;
4444                 }
4445                 ifmr->ifm_active |= IFM_1000_SX;
4446                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
4447                         ifmr->ifm_active |= IFM_HDX;
4448                 else
4449                         ifmr->ifm_active |= IFM_FDX;
4450                 BGE_UNLOCK(sc);
4451                 return;
4452         }
4453
4454         mii = device_get_softc(sc->bge_miibus);
4455         mii_pollstat(mii);
4456         ifmr->ifm_active = mii->mii_media_active;
4457         ifmr->ifm_status = mii->mii_media_status;
4458
4459         BGE_UNLOCK(sc);
4460 }
4461
4462 static int
4463 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
4464 {
4465         struct bge_softc *sc = ifp->if_softc;
4466         struct ifreq *ifr = (struct ifreq *) data;
4467         struct mii_data *mii;
4468         int flags, mask, error = 0;
4469
4470         switch (command) {
4471         case SIOCSIFMTU:
4472                 if (ifr->ifr_mtu < ETHERMIN ||
4473                     ((BGE_IS_JUMBO_CAPABLE(sc)) &&
4474                     ifr->ifr_mtu > BGE_JUMBO_MTU) ||
4475                     ((!BGE_IS_JUMBO_CAPABLE(sc)) &&
4476                     ifr->ifr_mtu > ETHERMTU))
4477                         error = EINVAL;
4478                 else if (ifp->if_mtu != ifr->ifr_mtu) {
4479                         ifp->if_mtu = ifr->ifr_mtu;
4480                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4481                         bge_init(sc);
4482                 }
4483                 break;
4484         case SIOCSIFFLAGS:
4485                 BGE_LOCK(sc);
4486                 if (ifp->if_flags & IFF_UP) {
4487                         /*
4488                          * If only the state of the PROMISC flag changed,
4489                          * then just use the 'set promisc mode' command
4490                          * instead of reinitializing the entire NIC. Doing
4491                          * a full re-init means reloading the firmware and
4492                          * waiting for it to start up, which may take a
4493                          * second or two.  Similarly for ALLMULTI.
4494                          */
4495                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4496                                 flags = ifp->if_flags ^ sc->bge_if_flags;
4497                                 if (flags & IFF_PROMISC)
4498                                         bge_setpromisc(sc);
4499                                 if (flags & IFF_ALLMULTI)
4500                                         bge_setmulti(sc);
4501                         } else
4502                                 bge_init_locked(sc);
4503                 } else {
4504                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4505                                 bge_stop(sc);
4506                         }
4507                 }
4508                 sc->bge_if_flags = ifp->if_flags;
4509                 BGE_UNLOCK(sc);
4510                 error = 0;
4511                 break;
4512         case SIOCADDMULTI:
4513         case SIOCDELMULTI:
4514                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4515                         BGE_LOCK(sc);
4516                         bge_setmulti(sc);
4517                         BGE_UNLOCK(sc);
4518                         error = 0;
4519                 }
4520                 break;
4521         case SIOCSIFMEDIA:
4522         case SIOCGIFMEDIA:
4523                 if (sc->bge_flags & BGE_FLAG_TBI) {
4524                         error = ifmedia_ioctl(ifp, ifr,
4525                             &sc->bge_ifmedia, command);
4526                 } else {
4527                         mii = device_get_softc(sc->bge_miibus);
4528                         error = ifmedia_ioctl(ifp, ifr,
4529                             &mii->mii_media, command);
4530                 }
4531                 break;
4532         case SIOCSIFCAP:
4533                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
4534 #ifdef DEVICE_POLLING
4535                 if (mask & IFCAP_POLLING) {
4536                         if (ifr->ifr_reqcap & IFCAP_POLLING) {
4537                                 error = ether_poll_register(bge_poll, ifp);
4538                                 if (error)
4539                                         return (error);
4540                                 BGE_LOCK(sc);
4541                                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4542                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4543                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4544                                 ifp->if_capenable |= IFCAP_POLLING;
4545                                 BGE_UNLOCK(sc);
4546                         } else {
4547                                 error = ether_poll_deregister(ifp);
4548                                 /* Enable interrupt even in error case */
4549                                 BGE_LOCK(sc);
4550                                 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
4551                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4552                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4553                                 ifp->if_capenable &= ~IFCAP_POLLING;
4554                                 BGE_UNLOCK(sc);
4555                         }
4556                 }
4557 #endif
4558                 if (mask & IFCAP_HWCSUM) {
4559                         ifp->if_capenable ^= IFCAP_HWCSUM;
4560                         if (IFCAP_HWCSUM & ifp->if_capenable &&
4561                             IFCAP_HWCSUM & ifp->if_capabilities)
4562                                 ifp->if_hwassist |= BGE_CSUM_FEATURES;
4563                         else
4564                                 ifp->if_hwassist &= ~BGE_CSUM_FEATURES;
4565                 }
4566
4567                 if ((mask & IFCAP_TSO4) != 0 &&
4568                     (ifp->if_capabilities & IFCAP_TSO4) != 0) {
4569                         ifp->if_capenable ^= IFCAP_TSO4;
4570                         if ((ifp->if_capenable & IFCAP_TSO4) != 0)
4571                                 ifp->if_hwassist |= CSUM_TSO;
4572                         else
4573                                 ifp->if_hwassist &= ~CSUM_TSO;
4574                 }
4575
4576                 if (mask & IFCAP_VLAN_MTU) {
4577                         ifp->if_capenable ^= IFCAP_VLAN_MTU;
4578                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4579                         bge_init(sc);
4580                 }
4581
4582                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
4583                     (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
4584                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
4585                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
4586                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
4587                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
4588                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
4589                                 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
4590                         BGE_LOCK(sc);
4591                         bge_setvlan(sc);
4592                         BGE_UNLOCK(sc);
4593                 }
4594 #ifdef VLAN_CAPABILITIES
4595                 VLAN_CAPABILITIES(ifp);
4596 #endif
4597                 break;
4598         default:
4599                 error = ether_ioctl(ifp, command, data);
4600                 break;
4601         }
4602
4603         return (error);
4604 }
4605
4606 static void
4607 bge_watchdog(struct bge_softc *sc)
4608 {
4609         struct ifnet *ifp;
4610
4611         BGE_LOCK_ASSERT(sc);
4612
4613         if (sc->bge_timer == 0 || --sc->bge_timer)
4614                 return;
4615
4616         ifp = sc->bge_ifp;
4617
4618         if_printf(ifp, "watchdog timeout -- resetting\n");
4619
4620         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4621         bge_init_locked(sc);
4622
4623         ifp->if_oerrors++;
4624 }
4625
4626 /*
4627  * Stop the adapter and free any mbufs allocated to the
4628  * RX and TX lists.
4629  */
4630 static void
4631 bge_stop(struct bge_softc *sc)
4632 {
4633         struct ifnet *ifp;
4634
4635         BGE_LOCK_ASSERT(sc);
4636
4637         ifp = sc->bge_ifp;
4638
4639         callout_stop(&sc->bge_stat_ch);
4640
4641         /* Disable host interrupts. */
4642         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4643         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4644
4645         /*
4646          * Tell firmware we're shutting down.
4647          */
4648         bge_stop_fw(sc);
4649         bge_sig_pre_reset(sc, BGE_RESET_STOP);
4650
4651         /*
4652          * Disable all of the receiver blocks.
4653          */
4654         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4655         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
4656         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
4657         if (!(BGE_IS_5705_PLUS(sc)))
4658                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
4659         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
4660         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
4661         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
4662
4663         /*
4664          * Disable all of the transmit blocks.
4665          */
4666         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
4667         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
4668         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
4669         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
4670         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
4671         if (!(BGE_IS_5705_PLUS(sc)))
4672                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
4673         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
4674
4675         /*
4676          * Shut down all of the memory managers and related
4677          * state machines.
4678          */
4679         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
4680         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
4681         if (!(BGE_IS_5705_PLUS(sc)))
4682                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
4683         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
4684         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
4685         if (!(BGE_IS_5705_PLUS(sc))) {
4686                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
4687                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4688         }
4689
4690         bge_reset(sc);
4691         bge_sig_legacy(sc, BGE_RESET_STOP);
4692         bge_sig_post_reset(sc, BGE_RESET_STOP);
4693
4694         /*
4695          * Keep the ASF firmware running if up.
4696          */
4697         if (sc->bge_asf_mode & ASF_STACKUP)
4698                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4699         else
4700                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4701
4702         /* Free the RX lists. */
4703         bge_free_rx_ring_std(sc);
4704
4705         /* Free jumbo RX list. */
4706         if (BGE_IS_JUMBO_CAPABLE(sc))
4707                 bge_free_rx_ring_jumbo(sc);
4708
4709         /* Free TX buffers. */
4710         bge_free_tx_ring(sc);
4711
4712         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
4713
4714         /* Clear MAC's link state (PHY may still have link UP). */
4715         if (bootverbose && sc->bge_link)
4716                 if_printf(sc->bge_ifp, "link DOWN\n");
4717         sc->bge_link = 0;
4718
4719         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4720 }
4721
4722 /*
4723  * Stop all chip I/O so that the kernel's probe routines don't
4724  * get confused by errant DMAs when rebooting.
4725  */
4726 static int
4727 bge_shutdown(device_t dev)
4728 {
4729         struct bge_softc *sc;
4730
4731         sc = device_get_softc(dev);
4732         BGE_LOCK(sc);
4733         bge_stop(sc);
4734         bge_reset(sc);
4735         BGE_UNLOCK(sc);
4736
4737         return (0);
4738 }
4739
4740 static int
4741 bge_suspend(device_t dev)
4742 {
4743         struct bge_softc *sc;
4744
4745         sc = device_get_softc(dev);
4746         BGE_LOCK(sc);
4747         bge_stop(sc);
4748         BGE_UNLOCK(sc);
4749
4750         return (0);
4751 }
4752
4753 static int
4754 bge_resume(device_t dev)
4755 {
4756         struct bge_softc *sc;
4757         struct ifnet *ifp;
4758
4759         sc = device_get_softc(dev);
4760         BGE_LOCK(sc);
4761         ifp = sc->bge_ifp;
4762         if (ifp->if_flags & IFF_UP) {
4763                 bge_init_locked(sc);
4764                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4765                         bge_start_locked(ifp);
4766         }
4767         BGE_UNLOCK(sc);
4768
4769         return (0);
4770 }
4771
4772 static void
4773 bge_link_upd(struct bge_softc *sc)
4774 {
4775         struct mii_data *mii;
4776         uint32_t link, status;
4777
4778         BGE_LOCK_ASSERT(sc);
4779
4780         /* Clear 'pending link event' flag. */
4781         sc->bge_link_evt = 0;
4782
4783         /*
4784          * Process link state changes.
4785          * Grrr. The link status word in the status block does
4786          * not work correctly on the BCM5700 rev AX and BX chips,
4787          * according to all available information. Hence, we have
4788          * to enable MII interrupts in order to properly obtain
4789          * async link changes. Unfortunately, this also means that
4790          * we have to read the MAC status register to detect link
4791          * changes, thereby adding an additional register access to
4792          * the interrupt handler.
4793          *
4794          * XXX: perhaps link state detection procedure used for
4795          * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
4796          */
4797
4798         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4799             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
4800                 status = CSR_READ_4(sc, BGE_MAC_STS);
4801                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
4802                         mii = device_get_softc(sc->bge_miibus);
4803                         mii_pollstat(mii);
4804                         if (!sc->bge_link &&
4805                             mii->mii_media_status & IFM_ACTIVE &&
4806                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4807                                 sc->bge_link++;
4808                                 if (bootverbose)
4809                                         if_printf(sc->bge_ifp, "link UP\n");
4810                         } else if (sc->bge_link &&
4811                             (!(mii->mii_media_status & IFM_ACTIVE) ||
4812                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4813                                 sc->bge_link = 0;
4814                                 if (bootverbose)
4815                                         if_printf(sc->bge_ifp, "link DOWN\n");
4816                         }
4817
4818                         /* Clear the interrupt. */
4819                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
4820                             BGE_EVTENB_MI_INTERRUPT);
4821                         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4822                         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
4823                             BRGPHY_INTRS);
4824                 }
4825                 return;
4826         }
4827
4828         if (sc->bge_flags & BGE_FLAG_TBI) {
4829                 status = CSR_READ_4(sc, BGE_MAC_STS);
4830                 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4831                         if (!sc->bge_link) {
4832                                 sc->bge_link++;
4833                                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
4834                                         BGE_CLRBIT(sc, BGE_MAC_MODE,
4835                                             BGE_MACMODE_TBI_SEND_CFGS);
4836                                 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4837                                 if (bootverbose)
4838                                         if_printf(sc->bge_ifp, "link UP\n");
4839                                 if_link_state_change(sc->bge_ifp,
4840                                     LINK_STATE_UP);
4841                         }
4842                 } else if (sc->bge_link) {
4843                         sc->bge_link = 0;
4844                         if (bootverbose)
4845                                 if_printf(sc->bge_ifp, "link DOWN\n");
4846                         if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
4847                 }
4848         } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
4849                 /*
4850                  * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
4851                  * in status word always set. Workaround this bug by reading
4852                  * PHY link status directly.
4853                  */
4854                 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
4855
4856                 if (link != sc->bge_link ||
4857                     sc->bge_asicrev == BGE_ASICREV_BCM5700) {
4858                         mii = device_get_softc(sc->bge_miibus);
4859                         mii_pollstat(mii);
4860                         if (!sc->bge_link &&
4861                             mii->mii_media_status & IFM_ACTIVE &&
4862                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4863                                 sc->bge_link++;
4864                                 if (bootverbose)
4865                                         if_printf(sc->bge_ifp, "link UP\n");
4866                         } else if (sc->bge_link &&
4867                             (!(mii->mii_media_status & IFM_ACTIVE) ||
4868                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4869                                 sc->bge_link = 0;
4870                                 if (bootverbose)
4871                                         if_printf(sc->bge_ifp, "link DOWN\n");
4872                         }
4873                 }
4874         } else {
4875                 /*
4876                  * Discard link events for MII/GMII controllers
4877                  * if MI auto-polling is disabled.
4878                  */
4879         }
4880
4881         /* Clear the attention. */
4882         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4883             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4884             BGE_MACSTAT_LINK_CHANGED);
4885 }
4886
4887 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
4888         SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
4889             sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
4890             desc)
4891
4892 static void
4893 bge_add_sysctls(struct bge_softc *sc)
4894 {
4895         struct sysctl_ctx_list *ctx;
4896         struct sysctl_oid_list *children, *schildren;
4897         struct sysctl_oid *tree;
4898
4899         ctx = device_get_sysctl_ctx(sc->bge_dev);
4900         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
4901
4902 #ifdef BGE_REGISTER_DEBUG
4903         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
4904             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
4905             "Debug Information");
4906
4907         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
4908             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
4909             "Register Read");
4910
4911         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
4912             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
4913             "Memory Read");
4914
4915 #endif
4916
4917         /*
4918          * A common design characteristic for many Broadcom client controllers
4919          * is that they only support a single outstanding DMA read operation
4920          * on the PCIe bus. This means that it will take twice as long to fetch
4921          * a TX frame that is split into header and payload buffers as it does
4922          * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
4923          * these controllers, coalescing buffers to reduce the number of memory
4924          * reads is effective way to get maximum performance(about 940Mbps).
4925          * Without collapsing TX buffers the maximum TCP bulk transfer
4926          * performance is about 850Mbps. However forcing coalescing mbufs
4927          * consumes a lot of CPU cycles, so leave it off by default.
4928          */
4929         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
4930             CTLFLAG_RW, &sc->bge_forced_collapse, 0,
4931             "Number of fragmented TX buffers of a frame allowed before "
4932             "forced collapsing");
4933         resource_int_value(device_get_name(sc->bge_dev),
4934             device_get_unit(sc->bge_dev), "forced_collapse",
4935             &sc->bge_forced_collapse);
4936
4937         if (BGE_IS_5705_PLUS(sc))
4938                 return;
4939
4940         tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
4941             NULL, "BGE Statistics");
4942         schildren = children = SYSCTL_CHILDREN(tree);
4943         BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
4944             children, COSFramesDroppedDueToFilters,
4945             "FramesDroppedDueToFilters");
4946         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
4947             children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
4948         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
4949             children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
4950         BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
4951             children, nicNoMoreRxBDs, "NoMoreRxBDs");
4952         BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
4953             children, ifInDiscards, "InputDiscards");
4954         BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
4955             children, ifInErrors, "InputErrors");
4956         BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
4957             children, nicRecvThresholdHit, "RecvThresholdHit");
4958         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
4959             children, nicDmaReadQueueFull, "DmaReadQueueFull");
4960         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
4961             children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
4962         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
4963             children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
4964         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
4965             children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
4966         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
4967             children, nicRingStatusUpdate, "RingStatusUpdate");
4968         BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
4969             children, nicInterrupts, "Interrupts");
4970         BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
4971             children, nicAvoidedInterrupts, "AvoidedInterrupts");
4972         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
4973             children, nicSendThresholdHit, "SendThresholdHit");
4974
4975         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
4976             NULL, "BGE RX Statistics");
4977         children = SYSCTL_CHILDREN(tree);
4978         BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
4979             children, rxstats.ifHCInOctets, "Octets");
4980         BGE_SYSCTL_STAT(sc, ctx, "Fragments",
4981             children, rxstats.etherStatsFragments, "Fragments");
4982         BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
4983             children, rxstats.ifHCInUcastPkts, "UcastPkts");
4984         BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
4985             children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
4986         BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
4987             children, rxstats.dot3StatsFCSErrors, "FCSErrors");
4988         BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
4989             children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
4990         BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
4991             children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
4992         BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
4993             children, rxstats.xoffPauseFramesReceived,
4994             "xoffPauseFramesReceived");
4995         BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
4996             children, rxstats.macControlFramesReceived,
4997             "ControlFramesReceived");
4998         BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
4999             children, rxstats.xoffStateEntered, "xoffStateEntered");
5000         BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
5001             children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
5002         BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
5003             children, rxstats.etherStatsJabbers, "Jabbers");
5004         BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
5005             children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
5006         BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
5007             children, rxstats.inRangeLengthError, "inRangeLengthError");
5008         BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
5009             children, rxstats.outRangeLengthError, "outRangeLengthError");
5010
5011         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
5012             NULL, "BGE TX Statistics");
5013         children = SYSCTL_CHILDREN(tree);
5014         BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
5015             children, txstats.ifHCOutOctets, "Octets");
5016         BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
5017             children, txstats.etherStatsCollisions, "Collisions");
5018         BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
5019             children, txstats.outXonSent, "XonSent");
5020         BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
5021             children, txstats.outXoffSent, "XoffSent");
5022         BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
5023             children, txstats.flowControlDone, "flowControlDone");
5024         BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
5025             children, txstats.dot3StatsInternalMacTransmitErrors,
5026             "InternalMacTransmitErrors");
5027         BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
5028             children, txstats.dot3StatsSingleCollisionFrames,
5029             "SingleCollisionFrames");
5030         BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
5031             children, txstats.dot3StatsMultipleCollisionFrames,
5032             "MultipleCollisionFrames");
5033         BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
5034             children, txstats.dot3StatsDeferredTransmissions,
5035             "DeferredTransmissions");
5036         BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
5037             children, txstats.dot3StatsExcessiveCollisions,
5038             "ExcessiveCollisions");
5039         BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
5040             children, txstats.dot3StatsLateCollisions,
5041             "LateCollisions");
5042         BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
5043             children, txstats.ifHCOutUcastPkts, "UcastPkts");
5044         BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
5045             children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
5046         BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
5047             children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
5048         BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
5049             children, txstats.dot3StatsCarrierSenseErrors,
5050             "CarrierSenseErrors");
5051         BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
5052             children, txstats.ifOutDiscards, "Discards");
5053         BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
5054             children, txstats.ifOutErrors, "Errors");
5055 }
5056
5057 static int
5058 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
5059 {
5060         struct bge_softc *sc;
5061         uint32_t result;
5062         int offset;
5063
5064         sc = (struct bge_softc *)arg1;
5065         offset = arg2;
5066         result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
5067             offsetof(bge_hostaddr, bge_addr_lo));
5068         return (sysctl_handle_int(oidp, &result, 0, req));
5069 }
5070
5071 #ifdef BGE_REGISTER_DEBUG
5072 static int
5073 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
5074 {
5075         struct bge_softc *sc;
5076         uint16_t *sbdata;
5077         int error;
5078         int result;
5079         int i, j;
5080
5081         result = -1;
5082         error = sysctl_handle_int(oidp, &result, 0, req);
5083         if (error || (req->newptr == NULL))
5084                 return (error);
5085
5086         if (result == 1) {
5087                 sc = (struct bge_softc *)arg1;
5088
5089                 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
5090                 printf("Status Block:\n");
5091                 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) {
5092                         printf("%06x:", i);
5093                         for (j = 0; j < 8; j++) {
5094                                 printf(" %04x", sbdata[i]);
5095                                 i += 4;
5096                         }
5097                         printf("\n");
5098                 }
5099
5100                 printf("Registers:\n");
5101                 for (i = 0x800; i < 0xA00; ) {
5102                         printf("%06x:", i);
5103                         for (j = 0; j < 8; j++) {
5104                                 printf(" %08x", CSR_READ_4(sc, i));
5105                                 i += 4;
5106                         }
5107                         printf("\n");
5108                 }
5109
5110                 printf("Hardware Flags:\n");
5111                 if (BGE_IS_5755_PLUS(sc))
5112                         printf(" - 5755 Plus\n");
5113                 if (BGE_IS_575X_PLUS(sc))
5114                         printf(" - 575X Plus\n");
5115                 if (BGE_IS_5705_PLUS(sc))
5116                         printf(" - 5705 Plus\n");
5117                 if (BGE_IS_5714_FAMILY(sc))
5118                         printf(" - 5714 Family\n");
5119                 if (BGE_IS_5700_FAMILY(sc))
5120                         printf(" - 5700 Family\n");
5121                 if (sc->bge_flags & BGE_FLAG_JUMBO)
5122                         printf(" - Supports Jumbo Frames\n");
5123                 if (sc->bge_flags & BGE_FLAG_PCIX)
5124                         printf(" - PCI-X Bus\n");
5125                 if (sc->bge_flags & BGE_FLAG_PCIE)
5126                         printf(" - PCI Express Bus\n");
5127                 if (sc->bge_flags & BGE_FLAG_NO_3LED)
5128                         printf(" - No 3 LEDs\n");
5129                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
5130                         printf(" - RX Alignment Bug\n");
5131         }
5132
5133         return (error);
5134 }
5135
5136 static int
5137 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5138 {
5139         struct bge_softc *sc;
5140         int error;
5141         uint16_t result;
5142         uint32_t val;
5143
5144         result = -1;
5145         error = sysctl_handle_int(oidp, &result, 0, req);
5146         if (error || (req->newptr == NULL))
5147                 return (error);
5148
5149         if (result < 0x8000) {
5150                 sc = (struct bge_softc *)arg1;
5151                 val = CSR_READ_4(sc, result);
5152                 printf("reg 0x%06X = 0x%08X\n", result, val);
5153         }
5154
5155         return (error);
5156 }
5157
5158 static int
5159 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
5160 {
5161         struct bge_softc *sc;
5162         int error;
5163         uint16_t result;
5164         uint32_t val;
5165
5166         result = -1;
5167         error = sysctl_handle_int(oidp, &result, 0, req);
5168         if (error || (req->newptr == NULL))
5169                 return (error);
5170
5171         if (result < 0x8000) {
5172                 sc = (struct bge_softc *)arg1;
5173                 val = bge_readmem_ind(sc, result);
5174                 printf("mem 0x%06X = 0x%08X\n", result, val);
5175         }
5176
5177         return (error);
5178 }
5179 #endif
5180
5181 static int
5182 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
5183 {
5184
5185         if (sc->bge_flags & BGE_FLAG_EADDR)
5186                 return (1);
5187
5188 #ifdef __sparc64__
5189         OF_getetheraddr(sc->bge_dev, ether_addr);
5190         return (0);
5191 #endif
5192         return (1);
5193 }
5194
5195 static int
5196 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
5197 {
5198         uint32_t mac_addr;
5199
5200         mac_addr = bge_readmem_ind(sc, 0x0c14);
5201         if ((mac_addr >> 16) == 0x484b) {
5202                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
5203                 ether_addr[1] = (uint8_t)mac_addr;
5204                 mac_addr = bge_readmem_ind(sc, 0x0c18);
5205                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
5206                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
5207                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
5208                 ether_addr[5] = (uint8_t)mac_addr;
5209                 return (0);
5210         }
5211         return (1);
5212 }
5213
5214 static int
5215 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
5216 {
5217         int mac_offset = BGE_EE_MAC_OFFSET;
5218
5219         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
5220                 mac_offset = BGE_EE_MAC_OFFSET_5906;
5221
5222         return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
5223             ETHER_ADDR_LEN));
5224 }
5225
5226 static int
5227 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
5228 {
5229
5230         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
5231                 return (1);
5232
5233         return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
5234            ETHER_ADDR_LEN));
5235 }
5236
5237 static int
5238 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
5239 {
5240         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
5241                 /* NOTE: Order is critical */
5242                 bge_get_eaddr_fw,
5243                 bge_get_eaddr_mem,
5244                 bge_get_eaddr_nvram,
5245                 bge_get_eaddr_eeprom,
5246                 NULL
5247         };
5248         const bge_eaddr_fcn_t *func;
5249
5250         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
5251                 if ((*func)(sc, eaddr) == 0)
5252                         break;
5253         }
5254         return (*func == NULL ? ENXIO : 0);
5255 }