sys/dev/bge/if_bge.c

   1 /*-
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/cdefs.h>
  35 __FBSDID("$FreeBSD$");
  36
  37 /*
  38  * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver
  39  *
  40  * The Broadcom BCM5700 is based on technology originally developed by
  41  * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet
  42  * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
  43  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  44  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  45  * frames, highly configurable RX filtering, and 16 RX and TX queues
  46  * (which, along with RX filter rules, can be used for QOS applications).
  47  * Other features, such as TCP segmentation, may be available as part
  48  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  49  * firmware images can be stored in hardware and need not be compiled
  50  * into the driver.
  51  *
  52  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  53  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  54  *
  55  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  56  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  57  * does not support external SSRAM.
  58  *
  59  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  60  * brand name, which is functionally similar but lacks PCI-X support.
  61  *
  62  * Without external SSRAM, you can only have at most 4 TX rings,
  63  * and the use of the mini RX ring is disabled. This seems to imply
  64  * that these features are simply not available on the BCM5701. As a
  65  * result, this driver does not implement any support for the mini RX
  66  * ring.
  67  */
  68
  69 #ifdef HAVE_KERNEL_OPTION_HEADERS
  70 #include "opt_device_polling.h"
  71 #endif
  72
  73 #include <sys/param.h>
  74 #include <sys/endian.h>
  75 #include <sys/systm.h>
  76 #include <sys/sockio.h>
  77 #include <sys/mbuf.h>
  78 #include <sys/malloc.h>
  79 #include <sys/kernel.h>
  80 #include <sys/module.h>
  81 #include <sys/socket.h>
  82 #include <sys/sysctl.h>
  83 #include <sys/taskqueue.h>
  84
  85 #include <net/if.h>
  86 #include <net/if_var.h>
  87 #include <net/if_arp.h>
  88 #include <net/ethernet.h>
  89 #include <net/if_dl.h>
  90 #include <net/if_media.h>
  91
  92 #include <net/bpf.h>
  93
  94 #include <net/if_types.h>
  95 #include <net/if_vlan_var.h>
  96
  97 #include <netinet/in_systm.h>
  98 #include <netinet/in.h>
  99 #include <netinet/ip.h>
 100 #include <netinet/tcp.h>
 101
 102 #include <machine/bus.h>
 103 #include <machine/resource.h>
 104 #include <sys/bus.h>
 105 #include <sys/rman.h>
 106
 107 #include <dev/mii/mii.h>
 108 #include <dev/mii/miivar.h>
 109 #include "miidevs.h"
 110 #include <dev/mii/brgphyreg.h>
 111
 112 #ifdef __sparc64__
 113 #include <dev/ofw/ofw_bus.h>
 114 #include <dev/ofw/openfirm.h>
 115 #include <machine/ofw_machdep.h>
 116 #include <machine/ver.h>
 117 #endif
 118
 119 #include <dev/pci/pcireg.h>
 120 #include <dev/pci/pcivar.h>
 121
 122 #include <dev/bge/if_bgereg.h>
 123
 124 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP)
 125 #define ETHER_MIN_NOPAD         (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
 126
 127 MODULE_DEPEND(bge, pci, 1, 1, 1);
 128 MODULE_DEPEND(bge, ether, 1, 1, 1);
 129 MODULE_DEPEND(bge, miibus, 1, 1, 1);
 130
 131 /* "device miibus" required.  See GENERIC if you get errors here. */
 132 #include "miibus_if.h"
 133
 134 /*
 135  * Various supported device vendors/types and their names. Note: the
 136  * spec seems to indicate that the hardware still has Alteon's vendor
 137  * ID burned into it, though it will always be overriden by the vendor
 138  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 139  */
 140 static const struct bge_type {
 141         uint16_t        bge_vid;
 142         uint16_t        bge_did;
 143 } bge_devs[] = {
 144         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5700 },
 145         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5701 },
 146
 147         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1000 },
 148         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1002 },
 149         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC9100 },
 150
 151         { APPLE_VENDORID,       APPLE_DEVICE_BCM5701 },
 152
 153         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5700 },
 154         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5701 },
 155         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702 },
 156         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702_ALT },
 157         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702X },
 158         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703 },
 159         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703_ALT },
 160         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703X },
 161         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704C },
 162         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S },
 163         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S_ALT },
 164         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705 },
 165         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705F },
 166         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705K },
 167         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M },
 168         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M_ALT },
 169         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714C },
 170         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714S },
 171         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715 },
 172         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715S },
 173         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5717 },
 174         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5717C },
 175         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5718 },
 176         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5719 },
 177         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5720 },
 178         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5721 },
 179         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5722 },
 180         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5723 },
 181         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5725 },
 182         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5727 },
 183         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750 },
 184         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750M },
 185         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751 },
 186         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751F },
 187         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751M },
 188         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752 },
 189         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752M },
 190         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753 },
 191         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753F },
 192         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753M },
 193         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754 },
 194         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754M },
 195         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755 },
 196         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755M },
 197         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5756 },
 198         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761 },
 199         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761E },
 200         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761S },
 201         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761SE },
 202         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5762 },
 203         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5764 },
 204         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780 },
 205         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780S },
 206         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5781 },
 207         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5782 },
 208         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5784 },
 209         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785F },
 210         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785G },
 211         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5786 },
 212         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787 },
 213         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787F },
 214         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787M },
 215         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5788 },
 216         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5789 },
 217         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901 },
 218         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901A2 },
 219         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5903M },
 220         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906 },
 221         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906M },
 222         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57760 },
 223         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57761 },
 224         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57762 },
 225         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57764 },
 226         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57765 },
 227         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57766 },
 228         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57767 },
 229         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57780 },
 230         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57781 },
 231         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57782 },
 232         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57785 },
 233         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57786 },
 234         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57787 },
 235         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57788 },
 236         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57790 },
 237         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57791 },
 238         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57795 },
 239
 240         { SK_VENDORID,          SK_DEVICEID_ALTIMA },
 241
 242         { TC_VENDORID,          TC_DEVICEID_3C996 },
 243
 244         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE4 },
 245         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE5 },
 246         { FJTSU_VENDORID,       FJTSU_DEVICEID_PP250450 },
 247
 248         { 0, 0 }
 249 };
 250
 251 static const struct bge_vendor {
 252         uint16_t        v_id;
 253         const char      *v_name;
 254 } bge_vendors[] = {
 255         { ALTEON_VENDORID,      "Alteon" },
 256         { ALTIMA_VENDORID,      "Altima" },
 257         { APPLE_VENDORID,       "Apple" },
 258         { BCOM_VENDORID,        "Broadcom" },
 259         { SK_VENDORID,          "SysKonnect" },
 260         { TC_VENDORID,          "3Com" },
 261         { FJTSU_VENDORID,       "Fujitsu" },
 262
 263         { 0, NULL }
 264 };
 265
 266 static const struct bge_revision {
 267         uint32_t        br_chipid;
 268         const char      *br_name;
 269 } bge_revisions[] = {
 270         { BGE_CHIPID_BCM5700_A0,        "BCM5700 A0" },
 271         { BGE_CHIPID_BCM5700_A1,        "BCM5700 A1" },
 272         { BGE_CHIPID_BCM5700_B0,        "BCM5700 B0" },
 273         { BGE_CHIPID_BCM5700_B1,        "BCM5700 B1" },
 274         { BGE_CHIPID_BCM5700_B2,        "BCM5700 B2" },
 275         { BGE_CHIPID_BCM5700_B3,        "BCM5700 B3" },
 276         { BGE_CHIPID_BCM5700_ALTIMA,    "BCM5700 Altima" },
 277         { BGE_CHIPID_BCM5700_C0,        "BCM5700 C0" },
 278         { BGE_CHIPID_BCM5701_A0,        "BCM5701 A0" },
 279         { BGE_CHIPID_BCM5701_B0,        "BCM5701 B0" },
 280         { BGE_CHIPID_BCM5701_B2,        "BCM5701 B2" },
 281         { BGE_CHIPID_BCM5701_B5,        "BCM5701 B5" },
 282         { BGE_CHIPID_BCM5703_A0,        "BCM5703 A0" },
 283         { BGE_CHIPID_BCM5703_A1,        "BCM5703 A1" },
 284         { BGE_CHIPID_BCM5703_A2,        "BCM5703 A2" },
 285         { BGE_CHIPID_BCM5703_A3,        "BCM5703 A3" },
 286         { BGE_CHIPID_BCM5703_B0,        "BCM5703 B0" },
 287         { BGE_CHIPID_BCM5704_A0,        "BCM5704 A0" },
 288         { BGE_CHIPID_BCM5704_A1,        "BCM5704 A1" },
 289         { BGE_CHIPID_BCM5704_A2,        "BCM5704 A2" },
 290         { BGE_CHIPID_BCM5704_A3,        "BCM5704 A3" },
 291         { BGE_CHIPID_BCM5704_B0,        "BCM5704 B0" },
 292         { BGE_CHIPID_BCM5705_A0,        "BCM5705 A0" },
 293         { BGE_CHIPID_BCM5705_A1,        "BCM5705 A1" },
 294         { BGE_CHIPID_BCM5705_A2,        "BCM5705 A2" },
 295         { BGE_CHIPID_BCM5705_A3,        "BCM5705 A3" },
 296         { BGE_CHIPID_BCM5750_A0,        "BCM5750 A0" },
 297         { BGE_CHIPID_BCM5750_A1,        "BCM5750 A1" },
 298         { BGE_CHIPID_BCM5750_A3,        "BCM5750 A3" },
 299         { BGE_CHIPID_BCM5750_B0,        "BCM5750 B0" },
 300         { BGE_CHIPID_BCM5750_B1,        "BCM5750 B1" },
 301         { BGE_CHIPID_BCM5750_C0,        "BCM5750 C0" },
 302         { BGE_CHIPID_BCM5750_C1,        "BCM5750 C1" },
 303         { BGE_CHIPID_BCM5750_C2,        "BCM5750 C2" },
 304         { BGE_CHIPID_BCM5714_A0,        "BCM5714 A0" },
 305         { BGE_CHIPID_BCM5752_A0,        "BCM5752 A0" },
 306         { BGE_CHIPID_BCM5752_A1,        "BCM5752 A1" },
 307         { BGE_CHIPID_BCM5752_A2,        "BCM5752 A2" },
 308         { BGE_CHIPID_BCM5714_B0,        "BCM5714 B0" },
 309         { BGE_CHIPID_BCM5714_B3,        "BCM5714 B3" },
 310         { BGE_CHIPID_BCM5715_A0,        "BCM5715 A0" },
 311         { BGE_CHIPID_BCM5715_A1,        "BCM5715 A1" },
 312         { BGE_CHIPID_BCM5715_A3,        "BCM5715 A3" },
 313         { BGE_CHIPID_BCM5717_A0,        "BCM5717 A0" },
 314         { BGE_CHIPID_BCM5717_B0,        "BCM5717 B0" },
 315         { BGE_CHIPID_BCM5717_C0,        "BCM5717 C0" },
 316         { BGE_CHIPID_BCM5719_A0,        "BCM5719 A0" },
 317         { BGE_CHIPID_BCM5720_A0,        "BCM5720 A0" },
 318         { BGE_CHIPID_BCM5755_A0,        "BCM5755 A0" },
 319         { BGE_CHIPID_BCM5755_A1,        "BCM5755 A1" },
 320         { BGE_CHIPID_BCM5755_A2,        "BCM5755 A2" },
 321         { BGE_CHIPID_BCM5722_A0,        "BCM5722 A0" },
 322         { BGE_CHIPID_BCM5761_A0,        "BCM5761 A0" },
 323         { BGE_CHIPID_BCM5761_A1,        "BCM5761 A1" },
 324         { BGE_CHIPID_BCM5762_A0,        "BCM5762 A0" },
 325         { BGE_CHIPID_BCM5784_A0,        "BCM5784 A0" },
 326         { BGE_CHIPID_BCM5784_A1,        "BCM5784 A1" },
 327         /* 5754 and 5787 share the same ASIC ID */
 328         { BGE_CHIPID_BCM5787_A0,        "BCM5754/5787 A0" },
 329         { BGE_CHIPID_BCM5787_A1,        "BCM5754/5787 A1" },
 330         { BGE_CHIPID_BCM5787_A2,        "BCM5754/5787 A2" },
 331         { BGE_CHIPID_BCM5906_A1,        "BCM5906 A1" },
 332         { BGE_CHIPID_BCM5906_A2,        "BCM5906 A2" },
 333         { BGE_CHIPID_BCM57765_A0,       "BCM57765 A0" },
 334         { BGE_CHIPID_BCM57765_B0,       "BCM57765 B0" },
 335         { BGE_CHIPID_BCM57780_A0,       "BCM57780 A0" },
 336         { BGE_CHIPID_BCM57780_A1,       "BCM57780 A1" },
 337
 338         { 0, NULL }
 339 };
 340
 341 /*
 342  * Some defaults for major revisions, so that newer steppings
 343  * that we don't know about have a shot at working.
 344  */
 345 static const struct bge_revision bge_majorrevs[] = {
 346         { BGE_ASICREV_BCM5700,          "unknown BCM5700" },
 347         { BGE_ASICREV_BCM5701,          "unknown BCM5701" },
 348         { BGE_ASICREV_BCM5703,          "unknown BCM5703" },
 349         { BGE_ASICREV_BCM5704,          "unknown BCM5704" },
 350         { BGE_ASICREV_BCM5705,          "unknown BCM5705" },
 351         { BGE_ASICREV_BCM5750,          "unknown BCM5750" },
 352         { BGE_ASICREV_BCM5714_A0,       "unknown BCM5714" },
 353         { BGE_ASICREV_BCM5752,          "unknown BCM5752" },
 354         { BGE_ASICREV_BCM5780,          "unknown BCM5780" },
 355         { BGE_ASICREV_BCM5714,          "unknown BCM5714" },
 356         { BGE_ASICREV_BCM5755,          "unknown BCM5755" },
 357         { BGE_ASICREV_BCM5761,          "unknown BCM5761" },
 358         { BGE_ASICREV_BCM5784,          "unknown BCM5784" },
 359         { BGE_ASICREV_BCM5785,          "unknown BCM5785" },
 360         /* 5754 and 5787 share the same ASIC ID */
 361         { BGE_ASICREV_BCM5787,          "unknown BCM5754/5787" },
 362         { BGE_ASICREV_BCM5906,          "unknown BCM5906" },
 363         { BGE_ASICREV_BCM57765,         "unknown BCM57765" },
 364         { BGE_ASICREV_BCM57766,         "unknown BCM57766" },
 365         { BGE_ASICREV_BCM57780,         "unknown BCM57780" },
 366         { BGE_ASICREV_BCM5717,          "unknown BCM5717" },
 367         { BGE_ASICREV_BCM5719,          "unknown BCM5719" },
 368         { BGE_ASICREV_BCM5720,          "unknown BCM5720" },
 369         { BGE_ASICREV_BCM5762,          "unknown BCM5762" },
 370
 371         { 0, NULL }
 372 };
 373
 374 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 375 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 376 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 377 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 378 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 379 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 380 #define BGE_IS_5717_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5717_PLUS)
 381 #define BGE_IS_57765_PLUS(sc)           ((sc)->bge_flags & BGE_FLAG_57765_PLUS)
 382
 383 static uint32_t bge_chipid(device_t);
 384 static const struct bge_vendor * bge_lookup_vendor(uint16_t);
 385 static const struct bge_revision * bge_lookup_rev(uint32_t);
 386
 387 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 388
 389 static int bge_probe(device_t);
 390 static int bge_attach(device_t);
 391 static int bge_detach(device_t);
 392 static int bge_suspend(device_t);
 393 static int bge_resume(device_t);
 394 static void bge_release_resources(struct bge_softc *);
 395 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 396 static int bge_dma_alloc(struct bge_softc *);
 397 static void bge_dma_free(struct bge_softc *);
 398 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t,
 399     bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
 400
 401 static void bge_devinfo(struct bge_softc *);
 402 static int bge_mbox_reorder(struct bge_softc *);
 403
 404 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
 405 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 406 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 407 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 408 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
 409
 410 static void bge_txeof(struct bge_softc *, uint16_t);
 411 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
 412 static int bge_rxeof(struct bge_softc *, uint16_t, int);
 413
 414 static void bge_asf_driver_up (struct bge_softc *);
 415 static void bge_tick(void *);
 416 static void bge_stats_clear_regs(struct bge_softc *);
 417 static void bge_stats_update(struct bge_softc *);
 418 static void bge_stats_update_regs(struct bge_softc *);
 419 static struct mbuf *bge_check_short_dma(struct mbuf *);
 420 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
 421     uint16_t *, uint16_t *);
 422 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 423
 424 static void bge_intr(void *);
 425 static int bge_msi_intr(void *);
 426 static void bge_intr_task(void *, int);
 427 static void bge_start_locked(if_t);
 428 static void bge_start(if_t);
 429 static int bge_ioctl(if_t, u_long, caddr_t);
 430 static void bge_init_locked(struct bge_softc *);
 431 static void bge_init(void *);
 432 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
 433 static void bge_stop(struct bge_softc *);
 434 static void bge_watchdog(struct bge_softc *);
 435 static int bge_shutdown(device_t);
 436 static int bge_ifmedia_upd_locked(if_t);
 437 static int bge_ifmedia_upd(if_t);
 438 static void bge_ifmedia_sts(if_t, struct ifmediareq *);
 439 static uint64_t bge_get_counter(if_t, ift_counter);
 440
 441 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 442 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 443
 444 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
 445 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
 446
 447 static void bge_setpromisc(struct bge_softc *);
 448 static void bge_setmulti(struct bge_softc *);
 449 static void bge_setvlan(struct bge_softc *);
 450
 451 static __inline void bge_rxreuse_std(struct bge_softc *, int);
 452 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
 453 static int bge_newbuf_std(struct bge_softc *, int);
 454 static int bge_newbuf_jumbo(struct bge_softc *, int);
 455 static int bge_init_rx_ring_std(struct bge_softc *);
 456 static void bge_free_rx_ring_std(struct bge_softc *);
 457 static int bge_init_rx_ring_jumbo(struct bge_softc *);
 458 static void bge_free_rx_ring_jumbo(struct bge_softc *);
 459 static void bge_free_tx_ring(struct bge_softc *);
 460 static int bge_init_tx_ring(struct bge_softc *);
 461
 462 static int bge_chipinit(struct bge_softc *);
 463 static int bge_blockinit(struct bge_softc *);
 464 static uint32_t bge_dma_swap_options(struct bge_softc *);
 465
 466 static int bge_has_eaddr(struct bge_softc *);
 467 static uint32_t bge_readmem_ind(struct bge_softc *, int);
 468 static void bge_writemem_ind(struct bge_softc *, int, int);
 469 static void bge_writembx(struct bge_softc *, int, int);
 470 #ifdef notdef
 471 static uint32_t bge_readreg_ind(struct bge_softc *, int);
 472 #endif
 473 static void bge_writemem_direct(struct bge_softc *, int, int);
 474 static void bge_writereg_ind(struct bge_softc *, int, int);
 475
 476 static int bge_miibus_readreg(device_t, int, int);
 477 static int bge_miibus_writereg(device_t, int, int, int);
 478 static void bge_miibus_statchg(device_t);
 479 #ifdef DEVICE_POLLING
 480 static int bge_poll(if_t ifp, enum poll_cmd cmd, int count);
 481 #endif
 482
 483 #define BGE_RESET_SHUTDOWN      0
 484 #define BGE_RESET_START         1
 485 #define BGE_RESET_SUSPEND       2
 486 static void bge_sig_post_reset(struct bge_softc *, int);
 487 static void bge_sig_legacy(struct bge_softc *, int);
 488 static void bge_sig_pre_reset(struct bge_softc *, int);
 489 static void bge_stop_fw(struct bge_softc *);
 490 static int bge_reset(struct bge_softc *);
 491 static void bge_link_upd(struct bge_softc *);
 492
 493 static void bge_ape_lock_init(struct bge_softc *);
 494 static void bge_ape_read_fw_ver(struct bge_softc *);
 495 static int bge_ape_lock(struct bge_softc *, int);
 496 static void bge_ape_unlock(struct bge_softc *, int);
 497 static void bge_ape_send_event(struct bge_softc *, uint32_t);
 498 static void bge_ape_driver_state_change(struct bge_softc *, int);
 499
 500 /*
 501  * The BGE_REGISTER_DEBUG option is only for low-level debugging.  It may
 502  * leak information to untrusted users.  It is also known to cause alignment
 503  * traps on certain architectures.
 504  */
 505 #ifdef BGE_REGISTER_DEBUG
 506 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 507 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
 508 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS);
 509 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
 510 #endif
 511 static void bge_add_sysctls(struct bge_softc *);
 512 static void bge_add_sysctl_stats_regs(struct bge_softc *,
 513     struct sysctl_ctx_list *, struct sysctl_oid_list *);
 514 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *,
 515     struct sysctl_oid_list *);
 516 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
 517
 518 static device_method_t bge_methods[] = {
 519         /* Device interface */
 520         DEVMETHOD(device_probe,         bge_probe),
 521         DEVMETHOD(device_attach,        bge_attach),
 522         DEVMETHOD(device_detach,        bge_detach),
 523         DEVMETHOD(device_shutdown,      bge_shutdown),
 524         DEVMETHOD(device_suspend,       bge_suspend),
 525         DEVMETHOD(device_resume,        bge_resume),
 526
 527         /* MII interface */
 528         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 529         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 530         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 531
 532         DEVMETHOD_END
 533 };
 534
 535 static driver_t bge_driver = {
 536         "bge",
 537         bge_methods,
 538         sizeof(struct bge_softc)
 539 };
 540
 541 static devclass_t bge_devclass;
 542
 543 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
 544 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 545
 546 static int bge_allow_asf = 1;
 547
 548 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
 549 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RDTUN, &bge_allow_asf, 0,
 550         "Allow ASF mode if available");
 551
 552 #define SPARC64_BLADE_1500_MODEL        "SUNW,Sun-Blade-1500"
 553 #define SPARC64_BLADE_1500_PATH_BGE     "/pci@1f,700000/network@2"
 554 #define SPARC64_BLADE_2500_MODEL        "SUNW,Sun-Blade-2500"
 555 #define SPARC64_BLADE_2500_PATH_BGE     "/pci@1c,600000/network@3"
 556 #define SPARC64_OFW_SUBVENDOR           "subsystem-vendor-id"
 557
 558 static int
 559 bge_has_eaddr(struct bge_softc *sc)
 560 {
 561 #ifdef __sparc64__
 562         char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
 563         device_t dev;
 564         uint32_t subvendor;
 565
 566         dev = sc->bge_dev;
 567
 568         /*
 569          * The on-board BGEs found in sun4u machines aren't fitted with
 570          * an EEPROM which means that we have to obtain the MAC address
 571          * via OFW and that some tests will always fail.  We distinguish
 572          * such BGEs by the subvendor ID, which also has to be obtained
 573          * from OFW instead of the PCI configuration space as the latter
 574          * indicates Broadcom as the subvendor of the netboot interface.
 575          * For early Blade 1500 and 2500 we even have to check the OFW
 576          * device path as the subvendor ID always defaults to Broadcom
 577          * there.
 578          */
 579         if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
 580             &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
 581             (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID))
 582                 return (0);
 583         memset(buf, 0, sizeof(buf));
 584         if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
 585                 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
 586                     strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
 587                         return (0);
 588                 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
 589                     strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
 590                         return (0);
 591         }
 592 #endif
 593         return (1);
 594 }
 595
 596 static uint32_t
 597 bge_readmem_ind(struct bge_softc *sc, int off)
 598 {
 599         device_t dev;
 600         uint32_t val;
 601
 602         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 603             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 604                 return (0);
 605
 606         dev = sc->bge_dev;
 607
 608         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 609         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 610         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 611         return (val);
 612 }
 613
 614 static void
 615 bge_writemem_ind(struct bge_softc *sc, int off, int val)
 616 {
 617         device_t dev;
 618
 619         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 620             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 621                 return;
 622
 623         dev = sc->bge_dev;
 624
 625         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 626         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 627         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 628 }
 629
 630 #ifdef notdef
 631 static uint32_t
 632 bge_readreg_ind(struct bge_softc *sc, int off)
 633 {
 634         device_t dev;
 635
 636         dev = sc->bge_dev;
 637
 638         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 639         return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 640 }
 641 #endif
 642
 643 static void
 644 bge_writereg_ind(struct bge_softc *sc, int off, int val)
 645 {
 646         device_t dev;
 647
 648         dev = sc->bge_dev;
 649
 650         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 651         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 652 }
 653
 654 static void
 655 bge_writemem_direct(struct bge_softc *sc, int off, int val)
 656 {
 657         CSR_WRITE_4(sc, off, val);
 658 }
 659
 660 static void
 661 bge_writembx(struct bge_softc *sc, int off, int val)
 662 {
 663         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 664                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 665
 666         CSR_WRITE_4(sc, off, val);
 667         if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0)
 668                 CSR_READ_4(sc, off);
 669 }
 670
 671 /*
 672  * Clear all stale locks and select the lock for this driver instance.
 673  */
 674 static void
 675 bge_ape_lock_init(struct bge_softc *sc)
 676 {
 677         uint32_t bit, regbase;
 678         int i;
 679
 680         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 681                 regbase = BGE_APE_LOCK_GRANT;
 682         else
 683                 regbase = BGE_APE_PER_LOCK_GRANT;
 684
 685         /* Clear any stale locks. */
 686         for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
 687                 switch (i) {
 688                 case BGE_APE_LOCK_PHY0:
 689                 case BGE_APE_LOCK_PHY1:
 690                 case BGE_APE_LOCK_PHY2:
 691                 case BGE_APE_LOCK_PHY3:
 692                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
 693                         break;
 694                 default:
 695                         if (sc->bge_func_addr == 0)
 696                                 bit = BGE_APE_LOCK_GRANT_DRIVER0;
 697                         else
 698                                 bit = (1 << sc->bge_func_addr);
 699                 }
 700                 APE_WRITE_4(sc, regbase + 4 * i, bit);
 701         }
 702
 703         /* Select the PHY lock based on the device's function number. */
 704         switch (sc->bge_func_addr) {
 705         case 0:
 706                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
 707                 break;
 708         case 1:
 709                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
 710                 break;
 711         case 2:
 712                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
 713                 break;
 714         case 3:
 715                 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
 716                 break;
 717         default:
 718                 device_printf(sc->bge_dev,
 719                     "PHY lock not supported on this function\n");
 720         }
 721 }
 722
 723 /*
 724  * Check for APE firmware, set flags, and print version info.
 725  */
 726 static void
 727 bge_ape_read_fw_ver(struct bge_softc *sc)
 728 {
 729         const char *fwtype;
 730         uint32_t apedata, features;
 731
 732         /* Check for a valid APE signature in shared memory. */
 733         apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
 734         if (apedata != BGE_APE_SEG_SIG_MAGIC) {
 735                 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE;
 736                 return;
 737         }
 738
 739         /* Check if APE firmware is running. */
 740         apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
 741         if ((apedata & BGE_APE_FW_STATUS_READY) == 0) {
 742                 device_printf(sc->bge_dev, "APE signature found "
 743                     "but FW status not ready! 0x%08x\n", apedata);
 744                 return;
 745         }
 746
 747         sc->bge_mfw_flags |= BGE_MFW_ON_APE;
 748
 749         /* Fetch the APE firwmare type and version. */
 750         apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
 751         features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
 752         if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) {
 753                 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
 754                 fwtype = "NCSI";
 755         } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) {
 756                 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
 757                 fwtype = "DASH";
 758         } else
 759                 fwtype = "UNKN";
 760
 761         /* Print the APE firmware version. */
 762         device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n",
 763             fwtype,
 764             (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT,
 765             (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT,
 766             (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT,
 767             (apedata & BGE_APE_FW_VERSION_BLDMSK));
 768 }
 769
 770 static int
 771 bge_ape_lock(struct bge_softc *sc, int locknum)
 772 {
 773         uint32_t bit, gnt, req, status;
 774         int i, off;
 775
 776         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
 777                 return (0);
 778
 779         /* Lock request/grant registers have different bases. */
 780         if (sc->bge_asicrev == BGE_ASICREV_BCM5761) {
 781                 req = BGE_APE_LOCK_REQ;
 782                 gnt = BGE_APE_LOCK_GRANT;
 783         } else {
 784                 req = BGE_APE_PER_LOCK_REQ;
 785                 gnt = BGE_APE_PER_LOCK_GRANT;
 786         }
 787
 788         off = 4 * locknum;
 789
 790         switch (locknum) {
 791         case BGE_APE_LOCK_GPIO:
 792                 /* Lock required when using GPIO. */
 793                 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 794                         return (0);
 795                 if (sc->bge_func_addr == 0)
 796                         bit = BGE_APE_LOCK_REQ_DRIVER0;
 797                 else
 798                         bit = (1 << sc->bge_func_addr);
 799                 break;
 800         case BGE_APE_LOCK_GRC:
 801                 /* Lock required to reset the device. */
 802                 if (sc->bge_func_addr == 0)
 803                         bit = BGE_APE_LOCK_REQ_DRIVER0;
 804                 else
 805                         bit = (1 << sc->bge_func_addr);
 806                 break;
 807         case BGE_APE_LOCK_MEM:
 808                 /* Lock required when accessing certain APE memory. */
 809                 if (sc->bge_func_addr == 0)
 810                         bit = BGE_APE_LOCK_REQ_DRIVER0;
 811                 else
 812                         bit = (1 << sc->bge_func_addr);
 813                 break;
 814         case BGE_APE_LOCK_PHY0:
 815         case BGE_APE_LOCK_PHY1:
 816         case BGE_APE_LOCK_PHY2:
 817         case BGE_APE_LOCK_PHY3:
 818                 /* Lock required when accessing PHYs. */
 819                 bit = BGE_APE_LOCK_REQ_DRIVER0;
 820                 break;
 821         default:
 822                 return (EINVAL);
 823         }
 824
 825         /* Request a lock. */
 826         APE_WRITE_4(sc, req + off, bit);
 827
 828         /* Wait up to 1 second to acquire lock. */
 829         for (i = 0; i < 20000; i++) {
 830                 status = APE_READ_4(sc, gnt + off);
 831                 if (status == bit)
 832                         break;
 833                 DELAY(50);
 834         }
 835
 836         /* Handle any errors. */
 837         if (status != bit) {
 838                 device_printf(sc->bge_dev, "APE lock %d request failed! "
 839                     "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
 840                     locknum, req + off, bit & 0xFFFF, gnt + off,
 841                     status & 0xFFFF);
 842                 /* Revoke the lock request. */
 843                 APE_WRITE_4(sc, gnt + off, bit);
 844                 return (EBUSY);
 845         }
 846
 847         return (0);
 848 }
 849
 850 static void
 851 bge_ape_unlock(struct bge_softc *sc, int locknum)
 852 {
 853         uint32_t bit, gnt;
 854         int off;
 855
 856         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
 857                 return;
 858
 859         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 860                 gnt = BGE_APE_LOCK_GRANT;
 861         else
 862                 gnt = BGE_APE_PER_LOCK_GRANT;
 863
 864         off = 4 * locknum;
 865
 866         switch (locknum) {
 867         case BGE_APE_LOCK_GPIO:
 868                 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 869                         return;
 870                 if (sc->bge_func_addr == 0)
 871                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
 872                 else
 873                         bit = (1 << sc->bge_func_addr);
 874                 break;
 875         case BGE_APE_LOCK_GRC:
 876                 if (sc->bge_func_addr == 0)
 877                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
 878                 else
 879                         bit = (1 << sc->bge_func_addr);
 880                 break;
 881         case BGE_APE_LOCK_MEM:
 882                 if (sc->bge_func_addr == 0)
 883                         bit = BGE_APE_LOCK_GRANT_DRIVER0;
 884                 else
 885                         bit = (1 << sc->bge_func_addr);
 886                 break;
 887         case BGE_APE_LOCK_PHY0:
 888         case BGE_APE_LOCK_PHY1:
 889         case BGE_APE_LOCK_PHY2:
 890         case BGE_APE_LOCK_PHY3:
 891                 bit = BGE_APE_LOCK_GRANT_DRIVER0;
 892                 break;
 893         default:
 894                 return;
 895         }
 896
 897         APE_WRITE_4(sc, gnt + off, bit);
 898 }
 899
 900 /*
 901  * Send an event to the APE firmware.
 902  */
 903 static void
 904 bge_ape_send_event(struct bge_softc *sc, uint32_t event)
 905 {
 906         uint32_t apedata;
 907         int i;
 908
 909         /* NCSI does not support APE events. */
 910         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
 911                 return;
 912
 913         /* Wait up to 1ms for APE to service previous event. */
 914         for (i = 10; i > 0; i--) {
 915                 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
 916                         break;
 917                 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
 918                 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) {
 919                         APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
 920                             BGE_APE_EVENT_STATUS_EVENT_PENDING);
 921                         bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
 922                         APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
 923                         break;
 924                 }
 925                 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
 926                 DELAY(100);
 927         }
 928         if (i == 0)
 929                 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n",
 930                     event);
 931 }
 932
 933 static void
 934 bge_ape_driver_state_change(struct bge_softc *sc, int kind)
 935 {
 936         uint32_t apedata, event;
 937
 938         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
 939                 return;
 940
 941         switch (kind) {
 942         case BGE_RESET_START:
 943                 /* If this is the first load, clear the load counter. */
 944                 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
 945                 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC)
 946                         APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
 947                 else {
 948                         apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
 949                         APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
 950                 }
 951                 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
 952                     BGE_APE_HOST_SEG_SIG_MAGIC);
 953                 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
 954                     BGE_APE_HOST_SEG_LEN_MAGIC);
 955
 956                 /* Add some version info if bge(4) supports it. */
 957                 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
 958                     BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0));
 959                 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
 960                     BGE_APE_HOST_BEHAV_NO_PHYLOCK);
 961                 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
 962                     BGE_APE_HOST_HEARTBEAT_INT_DISABLE);
 963                 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
 964                     BGE_APE_HOST_DRVR_STATE_START);
 965                 event = BGE_APE_EVENT_STATUS_STATE_START;
 966                 break;
 967         case BGE_RESET_SHUTDOWN:
 968                 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
 969                     BGE_APE_HOST_DRVR_STATE_UNLOAD);
 970                 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
 971                 break;
 972         case BGE_RESET_SUSPEND:
 973                 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
 974                 break;
 975         default:
 976                 return;
 977         }
 978
 979         bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
 980             BGE_APE_EVENT_STATUS_STATE_CHNGE);
 981 }
 982
 983 /*
 984  * Map a single buffer address.
 985  */
 986
 987 static void
 988 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 989 {
 990         struct bge_dmamap_arg *ctx;
 991
 992         if (error)
 993                 return;
 994
 995         KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
 996
 997         ctx = arg;
 998         ctx->bge_busaddr = segs->ds_addr;
 999 }
1000
1001 static uint8_t
1002 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1003 {
1004         uint32_t access, byte = 0;
1005         int i;
1006
1007         /* Lock. */
1008         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
1009         for (i = 0; i < 8000; i++) {
1010                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
1011                         break;
1012                 DELAY(20);
1013         }
1014         if (i == 8000)
1015                 return (1);
1016
1017         /* Enable access. */
1018         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
1019         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
1020
1021         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
1022         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
1023         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
1024                 DELAY(10);
1025                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
1026                         DELAY(10);
1027                         break;
1028                 }
1029         }
1030
1031         if (i == BGE_TIMEOUT * 10) {
1032                 if_printf(sc->bge_ifp, "nvram read timed out\n");
1033                 return (1);
1034         }
1035
1036         /* Get result. */
1037         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
1038
1039         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
1040
1041         /* Disable access. */
1042         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
1043
1044         /* Unlock. */
1045         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
1046         CSR_READ_4(sc, BGE_NVRAM_SWARB);
1047
1048         return (0);
1049 }
1050
1051 /*
1052  * Read a sequence of bytes from NVRAM.
1053  */
1054 static int
1055 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1056 {
1057         int err = 0, i;
1058         uint8_t byte = 0;
1059
1060         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1061                 return (1);
1062
1063         for (i = 0; i < cnt; i++) {
1064                 err = bge_nvram_getbyte(sc, off + i, &byte);
1065                 if (err)
1066                         break;
1067                 *(dest + i) = byte;
1068         }
1069
1070         return (err ? 1 : 0);
1071 }
1072
1073 /*
1074  * Read a byte of data stored in the EEPROM at address 'addr.' The
1075  * BCM570x supports both the traditional bitbang interface and an
1076  * auto access interface for reading the EEPROM. We use the auto
1077  * access method.
1078  */
1079 static uint8_t
1080 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1081 {
1082         int i;
1083         uint32_t byte = 0;
1084
1085         /*
1086          * Enable use of auto EEPROM access so we can avoid
1087          * having to use the bitbang method.
1088          */
1089         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
1090
1091         /* Reset the EEPROM, load the clock period. */
1092         CSR_WRITE_4(sc, BGE_EE_ADDR,
1093             BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
1094         DELAY(20);
1095
1096         /* Issue the read EEPROM command. */
1097         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
1098
1099         /* Wait for completion */
1100         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
1101                 DELAY(10);
1102                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1103                         break;
1104         }
1105
1106         if (i == BGE_TIMEOUT * 10) {
1107                 device_printf(sc->bge_dev, "EEPROM read timed out\n");
1108                 return (1);
1109         }
1110
1111         /* Get result. */
1112         byte = CSR_READ_4(sc, BGE_EE_DATA);
1113
1114         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
1115
1116         return (0);
1117 }
1118
1119 /*
1120  * Read a sequence of bytes from the EEPROM.
1121  */
1122 static int
1123 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1124 {
1125         int i, error = 0;
1126         uint8_t byte = 0;
1127
1128         for (i = 0; i < cnt; i++) {
1129                 error = bge_eeprom_getbyte(sc, off + i, &byte);
1130                 if (error)
1131                         break;
1132                 *(dest + i) = byte;
1133         }
1134
1135         return (error ? 1 : 0);
1136 }
1137
1138 static int
1139 bge_miibus_readreg(device_t dev, int phy, int reg)
1140 {
1141         struct bge_softc *sc;
1142         uint32_t val;
1143         int i;
1144
1145         sc = device_get_softc(dev);
1146
1147         if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1148                 return (0);
1149
1150         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1151         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1152                 CSR_WRITE_4(sc, BGE_MI_MODE,
1153                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1154                 DELAY(80);
1155         }
1156
1157         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
1158             BGE_MIPHY(phy) | BGE_MIREG(reg));
1159
1160         /* Poll for the PHY register access to complete. */
1161         for (i = 0; i < BGE_TIMEOUT; i++) {
1162                 DELAY(10);
1163                 val = CSR_READ_4(sc, BGE_MI_COMM);
1164                 if ((val & BGE_MICOMM_BUSY) == 0) {
1165                         DELAY(5);
1166                         val = CSR_READ_4(sc, BGE_MI_COMM);
1167                         break;
1168                 }
1169         }
1170
1171         if (i == BGE_TIMEOUT) {
1172                 device_printf(sc->bge_dev,
1173                     "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
1174                     phy, reg, val);
1175                 val = 0;
1176         }
1177
1178         /* Restore the autopoll bit if necessary. */
1179         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1180                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1181                 DELAY(80);
1182         }
1183
1184         bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1185
1186         if (val & BGE_MICOMM_READFAIL)
1187                 return (0);
1188
1189         return (val & 0xFFFF);
1190 }
1191
1192 static int
1193 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
1194 {
1195         struct bge_softc *sc;
1196         int i;
1197
1198         sc = device_get_softc(dev);
1199
1200         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1201             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
1202                 return (0);
1203
1204         if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1205                 return (0);
1206
1207         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1208         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1209                 CSR_WRITE_4(sc, BGE_MI_MODE,
1210                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1211                 DELAY(80);
1212         }
1213
1214         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
1215             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
1216
1217         for (i = 0; i < BGE_TIMEOUT; i++) {
1218                 DELAY(10);
1219                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
1220                         DELAY(5);
1221                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
1222                         break;
1223                 }
1224         }
1225
1226         /* Restore the autopoll bit if necessary. */
1227         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1228                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1229                 DELAY(80);
1230         }
1231
1232         bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1233
1234         if (i == BGE_TIMEOUT)
1235                 device_printf(sc->bge_dev,
1236                     "PHY write timed out (phy %d, reg %d, val 0x%04x)\n",
1237                     phy, reg, val);
1238
1239         return (0);
1240 }
1241
1242 static void
1243 bge_miibus_statchg(device_t dev)
1244 {
1245         struct bge_softc *sc;
1246         struct mii_data *mii;
1247         uint32_t mac_mode, rx_mode, tx_mode;
1248
1249         sc = device_get_softc(dev);
1250         if ((if_getdrvflags(sc->bge_ifp) & IFF_DRV_RUNNING) == 0)
1251                 return;
1252         mii = device_get_softc(sc->bge_miibus);
1253
1254         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1255             (IFM_ACTIVE | IFM_AVALID)) {
1256                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1257                 case IFM_10_T:
1258                 case IFM_100_TX:
1259                         sc->bge_link = 1;
1260                         break;
1261                 case IFM_1000_T:
1262                 case IFM_1000_SX:
1263                 case IFM_2500_SX:
1264                         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1265                                 sc->bge_link = 1;
1266                         else
1267                                 sc->bge_link = 0;
1268                         break;
1269                 default:
1270                         sc->bge_link = 0;
1271                         break;
1272                 }
1273         } else
1274                 sc->bge_link = 0;
1275         if (sc->bge_link == 0)
1276                 return;
1277
1278         /*
1279          * APE firmware touches these registers to keep the MAC
1280          * connected to the outside world.  Try to keep the
1281          * accesses atomic.
1282          */
1283
1284         /* Set the port mode (MII/GMII) to match the link speed. */
1285         mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
1286             ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
1287         tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
1288         rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
1289
1290         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1291             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
1292                 mac_mode |= BGE_PORTMODE_GMII;
1293         else
1294                 mac_mode |= BGE_PORTMODE_MII;
1295
1296         /* Set MAC flow control behavior to match link flow control settings. */
1297         tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE;
1298         rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE;
1299         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1300                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1301                         tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE;
1302                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1303                         rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE;
1304         } else
1305                 mac_mode |= BGE_MACMODE_HALF_DUPLEX;
1306
1307         CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
1308         DELAY(40);
1309         CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
1310         CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
1311 }
1312
1313 /*
1314  * Intialize a standard receive ring descriptor.
1315  */
1316 static int
1317 bge_newbuf_std(struct bge_softc *sc, int i)
1318 {
1319         struct mbuf *m;
1320         struct bge_rx_bd *r;
1321         bus_dma_segment_t segs[1];
1322         bus_dmamap_t map;
1323         int error, nsegs;
1324
1325         if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
1326             (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
1327             ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) {
1328                 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1329                 if (m == NULL)
1330                         return (ENOBUFS);
1331                 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1332         } else {
1333                 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1334                 if (m == NULL)
1335                         return (ENOBUFS);
1336                 m->m_len = m->m_pkthdr.len = MCLBYTES;
1337         }
1338         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1339                 m_adj(m, ETHER_ALIGN);
1340
1341         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
1342             sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
1343         if (error != 0) {
1344                 m_freem(m);
1345                 return (error);
1346         }
1347         if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1348                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1349                     sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
1350                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1351                     sc->bge_cdata.bge_rx_std_dmamap[i]);
1352         }
1353         map = sc->bge_cdata.bge_rx_std_dmamap[i];
1354         sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
1355         sc->bge_cdata.bge_rx_std_sparemap = map;
1356         sc->bge_cdata.bge_rx_std_chain[i] = m;
1357         sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
1358         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
1359         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1360         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1361         r->bge_flags = BGE_RXBDFLAG_END;
1362         r->bge_len = segs[0].ds_len;
1363         r->bge_idx = i;
1364
1365         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1366             sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
1367
1368         return (0);
1369 }
1370
1371 /*
1372  * Initialize a jumbo receive ring descriptor. This allocates
1373  * a jumbo buffer from the pool managed internally by the driver.
1374  */
1375 static int
1376 bge_newbuf_jumbo(struct bge_softc *sc, int i)
1377 {
1378         bus_dma_segment_t segs[BGE_NSEG_JUMBO];
1379         bus_dmamap_t map;
1380         struct bge_extrx_bd *r;
1381         struct mbuf *m;
1382         int error, nsegs;
1383
1384         MGETHDR(m, M_NOWAIT, MT_DATA);
1385         if (m == NULL)
1386                 return (ENOBUFS);
1387
1388         if (m_cljget(m, M_NOWAIT, MJUM9BYTES) == NULL) {
1389                 m_freem(m);
1390                 return (ENOBUFS);
1391         }
1392         m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1393         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1394                 m_adj(m, ETHER_ALIGN);
1395
1396         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1397             sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1398         if (error != 0) {
1399                 m_freem(m);
1400                 return (error);
1401         }
1402
1403         if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1404                 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1405                     sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1406                 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1407                     sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1408         }
1409         map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1410         sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1411             sc->bge_cdata.bge_rx_jumbo_sparemap;
1412         sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1413         sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1414         sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1415         sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1416         sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1417         sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1418
1419         /*
1420          * Fill in the extended RX buffer descriptor.
1421          */
1422         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1423         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1424         r->bge_idx = i;
1425         r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1426         switch (nsegs) {
1427         case 4:
1428                 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1429                 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1430                 r->bge_len3 = segs[3].ds_len;
1431                 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1432         case 3:
1433                 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1434                 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1435                 r->bge_len2 = segs[2].ds_len;
1436                 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1437         case 2:
1438                 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1439                 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1440                 r->bge_len1 = segs[1].ds_len;
1441                 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1442         case 1:
1443                 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1444                 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1445                 r->bge_len0 = segs[0].ds_len;
1446                 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1447                 break;
1448         default:
1449                 panic("%s: %d segments\n", __func__, nsegs);
1450         }
1451
1452         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1453             sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1454
1455         return (0);
1456 }
1457
1458 static int
1459 bge_init_rx_ring_std(struct bge_softc *sc)
1460 {
1461         int error, i;
1462
1463         bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1464         sc->bge_std = 0;
1465         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1466                 if ((error = bge_newbuf_std(sc, i)) != 0)
1467                         return (error);
1468                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1469         }
1470
1471         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1472             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1473
1474         sc->bge_std = 0;
1475         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1476
1477         return (0);
1478 }
1479
1480 static void
1481 bge_free_rx_ring_std(struct bge_softc *sc)
1482 {
1483         int i;
1484
1485         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1486                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1487                         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1488                             sc->bge_cdata.bge_rx_std_dmamap[i],
1489                             BUS_DMASYNC_POSTREAD);
1490                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1491                             sc->bge_cdata.bge_rx_std_dmamap[i]);
1492                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1493                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1494                 }
1495                 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1496                     sizeof(struct bge_rx_bd));
1497         }
1498 }
1499
1500 static int
1501 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1502 {
1503         struct bge_rcb *rcb;
1504         int error, i;
1505
1506         bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1507         sc->bge_jumbo = 0;
1508         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1509                 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1510                         return (error);
1511                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1512         }
1513
1514         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1515             sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1516
1517         sc->bge_jumbo = 0;
1518
1519         /* Enable the jumbo receive producer ring. */
1520         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1521         rcb->bge_maxlen_flags =
1522             BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD);
1523         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1524
1525         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1526
1527         return (0);
1528 }
1529
1530 static void
1531 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1532 {
1533         int i;
1534
1535         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1536                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1537                         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1538                             sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1539                             BUS_DMASYNC_POSTREAD);
1540                         bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1541                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1542                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1543                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1544                 }
1545                 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1546                     sizeof(struct bge_extrx_bd));
1547         }
1548 }
1549
1550 static void
1551 bge_free_tx_ring(struct bge_softc *sc)
1552 {
1553         int i;
1554
1555         if (sc->bge_ldata.bge_tx_ring == NULL)
1556                 return;
1557
1558         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1559                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1560                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1561                             sc->bge_cdata.bge_tx_dmamap[i],
1562                             BUS_DMASYNC_POSTWRITE);
1563                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1564                             sc->bge_cdata.bge_tx_dmamap[i]);
1565                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1566                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1567                 }
1568                 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1569                     sizeof(struct bge_tx_bd));
1570         }
1571 }
1572
1573 static int
1574 bge_init_tx_ring(struct bge_softc *sc)
1575 {
1576         sc->bge_txcnt = 0;
1577         sc->bge_tx_saved_considx = 0;
1578
1579         bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1580         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1581             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1582
1583         /* Initialize transmit producer index for host-memory send ring. */
1584         sc->bge_tx_prodidx = 0;
1585         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1586
1587         /* 5700 b2 errata */
1588         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1589                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1590
1591         /* NIC-memory send ring not used; initialize to zero. */
1592         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1593         /* 5700 b2 errata */
1594         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1595                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1596
1597         return (0);
1598 }
1599
1600 static void
1601 bge_setpromisc(struct bge_softc *sc)
1602 {
1603         if_t ifp;
1604
1605         BGE_LOCK_ASSERT(sc);
1606
1607         ifp = sc->bge_ifp;
1608
1609         /* Enable or disable promiscuous mode as needed. */
1610         if (if_getflags(ifp) & IFF_PROMISC)
1611                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1612         else
1613                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1614 }
1615
1616 static void
1617 bge_setmulti(struct bge_softc *sc)
1618 {
1619         if_t ifp;
1620         int mc_count = 0;
1621         uint32_t hashes[4] = { 0, 0, 0, 0 };
1622         int h, i, mcnt;
1623         unsigned char *mta;
1624
1625         BGE_LOCK_ASSERT(sc);
1626
1627         ifp = sc->bge_ifp;
1628
1629         mc_count = if_multiaddr_count(ifp, -1);
1630         mta = malloc(sizeof(unsigned char) *  ETHER_ADDR_LEN *
1631             mc_count, M_DEVBUF, M_NOWAIT);
1632
1633         if(mta == NULL) {
1634                 device_printf(sc->bge_dev,
1635                     "Failed to allocated temp mcast list\n");
1636                 return;
1637         }
1638
1639         if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) {
1640                 for (i = 0; i < 4; i++)
1641                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1642                 free(mta, M_DEVBUF);
1643                 return;
1644         }
1645
1646         /* First, zot all the existing filters. */
1647         for (i = 0; i < 4; i++)
1648                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1649
1650         if_multiaddr_array(ifp, mta, &mcnt, mc_count);
1651         for(i = 0; i < mcnt; i++) {
1652                 h = ether_crc32_le(mta + (i * ETHER_ADDR_LEN),
1653                     ETHER_ADDR_LEN) & 0x7F;
1654                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1655         }
1656
1657         for (i = 0; i < 4; i++)
1658                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1659
1660         free(mta, M_DEVBUF);
1661 }
1662
1663 static void
1664 bge_setvlan(struct bge_softc *sc)
1665 {
1666         if_t ifp;
1667
1668         BGE_LOCK_ASSERT(sc);
1669
1670         ifp = sc->bge_ifp;
1671
1672         /* Enable or disable VLAN tag stripping as needed. */
1673         if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING)
1674                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1675         else
1676                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1677 }
1678
1679 static void
1680 bge_sig_pre_reset(struct bge_softc *sc, int type)
1681 {
1682
1683         /*
1684          * Some chips don't like this so only do this if ASF is enabled
1685          */
1686         if (sc->bge_asf_mode)
1687                 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
1688
1689         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1690                 switch (type) {
1691                 case BGE_RESET_START:
1692                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1693                             BGE_FW_DRV_STATE_START);
1694                         break;
1695                 case BGE_RESET_SHUTDOWN:
1696                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1697                             BGE_FW_DRV_STATE_UNLOAD);
1698                         break;
1699                 case BGE_RESET_SUSPEND:
1700                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1701                             BGE_FW_DRV_STATE_SUSPEND);
1702                         break;
1703                 }
1704         }
1705
1706         if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
1707                 bge_ape_driver_state_change(sc, type);
1708 }
1709
1710 static void
1711 bge_sig_post_reset(struct bge_softc *sc, int type)
1712 {
1713
1714         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1715                 switch (type) {
1716                 case BGE_RESET_START:
1717                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1718                             BGE_FW_DRV_STATE_START_DONE);
1719                         /* START DONE */
1720                         break;
1721                 case BGE_RESET_SHUTDOWN:
1722                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1723                             BGE_FW_DRV_STATE_UNLOAD_DONE);
1724                         break;
1725                 }
1726         }
1727         if (type == BGE_RESET_SHUTDOWN)
1728                 bge_ape_driver_state_change(sc, type);
1729 }
1730
1731 static void
1732 bge_sig_legacy(struct bge_softc *sc, int type)
1733 {
1734
1735         if (sc->bge_asf_mode) {
1736                 switch (type) {
1737                 case BGE_RESET_START:
1738                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1739                             BGE_FW_DRV_STATE_START);
1740                         break;
1741                 case BGE_RESET_SHUTDOWN:
1742                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1743                             BGE_FW_DRV_STATE_UNLOAD);
1744                         break;
1745                 }
1746         }
1747 }
1748
1749 static void
1750 bge_stop_fw(struct bge_softc *sc)
1751 {
1752         int i;
1753
1754         if (sc->bge_asf_mode) {
1755                 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
1756                 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
1757                     CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
1758
1759                 for (i = 0; i < 100; i++ ) {
1760                         if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1761                             BGE_RX_CPU_DRV_EVENT))
1762                                 break;
1763                         DELAY(10);
1764                 }
1765         }
1766 }
1767
1768 static uint32_t
1769 bge_dma_swap_options(struct bge_softc *sc)
1770 {
1771         uint32_t dma_options;
1772
1773         dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
1774             BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
1775 #if BYTE_ORDER == BIG_ENDIAN
1776         dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
1777 #endif
1778         return (dma_options);
1779 }
1780
1781 /*
1782  * Do endian, PCI and DMA initialization.
1783  */
1784 static int
1785 bge_chipinit(struct bge_softc *sc)
1786 {
1787         uint32_t dma_rw_ctl, misc_ctl, mode_ctl;
1788         uint16_t val;
1789         int i;
1790
1791         /* Set endianness before we access any non-PCI registers. */
1792         misc_ctl = BGE_INIT;
1793         if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1794                 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1795         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1796
1797         /*
1798          * Clear the MAC statistics block in the NIC's
1799          * internal memory.
1800          */
1801         for (i = BGE_STATS_BLOCK;
1802             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1803                 BGE_MEMWIN_WRITE(sc, i, 0);
1804
1805         for (i = BGE_STATUS_BLOCK;
1806             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1807                 BGE_MEMWIN_WRITE(sc, i, 0);
1808
1809         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1810                 /*
1811                  *  Fix data corruption caused by non-qword write with WB.
1812                  *  Fix master abort in PCI mode.
1813                  *  Fix PCI latency timer.
1814                  */
1815                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1816                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1817                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1818         }
1819
1820         if (sc->bge_asicrev == BGE_ASICREV_BCM57765 ||
1821             sc->bge_asicrev == BGE_ASICREV_BCM57766) {
1822                 /*
1823                  * For the 57766 and non Ax versions of 57765, bootcode
1824                  * needs to setup the PCIE Fast Training Sequence (FTS)
1825                  * value to prevent transmit hangs.
1826                  */
1827                 if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) {
1828                         CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL,
1829                             CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) |
1830                             BGE_CPMU_PADRNG_CTL_RDIV2);
1831                 }
1832         }
1833
1834         /*
1835          * Set up the PCI DMA control register.
1836          */
1837         dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1838             BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1839         if (sc->bge_flags & BGE_FLAG_PCIE) {
1840                 if (sc->bge_mps >= 256)
1841                         dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1842                 else
1843                         dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1844         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1845                 if (BGE_IS_5714_FAMILY(sc)) {
1846                         /* 256 bytes for read and write. */
1847                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1848                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1849                         dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1850                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1851                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1852                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1853                         /*
1854                          * In the BCM5703, the DMA read watermark should
1855                          * be set to less than or equal to the maximum
1856                          * memory read byte count of the PCI-X command
1857                          * register.
1858                          */
1859                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1860                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1861                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1862                         /* 1536 bytes for read, 384 bytes for write. */
1863                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1864                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1865                 } else {
1866                         /* 384 bytes for read and write. */
1867                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1868                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1869                             0x0F;
1870                 }
1871                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1872                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1873                         uint32_t tmp;
1874
1875                         /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1876                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1877                         if (tmp == 6 || tmp == 7)
1878                                 dma_rw_ctl |=
1879                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1880
1881                         /* Set PCI-X DMA write workaround. */
1882                         dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1883                 }
1884         } else {
1885                 /* Conventional PCI bus: 256 bytes for read and write. */
1886                 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1887                     BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1888
1889                 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1890                     sc->bge_asicrev != BGE_ASICREV_BCM5750)
1891                         dma_rw_ctl |= 0x0F;
1892         }
1893         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1894             sc->bge_asicrev == BGE_ASICREV_BCM5701)
1895                 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1896                     BGE_PCIDMARWCTL_ASRT_ALL_BE;
1897         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1898             sc->bge_asicrev == BGE_ASICREV_BCM5704)
1899                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1900         if (BGE_IS_5717_PLUS(sc)) {
1901                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1902                 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
1903                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1904                 /*
1905                  * Enable HW workaround for controllers that misinterpret
1906                  * a status tag update and leave interrupts permanently
1907                  * disabled.
1908                  */
1909                 if (!BGE_IS_57765_PLUS(sc) &&
1910                     sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
1911                     sc->bge_asicrev != BGE_ASICREV_BCM5762)
1912                         dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1913         }
1914         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1915
1916         /*
1917          * Set up general mode register.
1918          */
1919         mode_ctl = bge_dma_swap_options(sc);
1920         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
1921             sc->bge_asicrev == BGE_ASICREV_BCM5762) {
1922                 /* Retain Host-2-BMC settings written by APE firmware. */
1923                 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
1924                     (BGE_MODECTL_BYTESWAP_B2HRX_DATA |
1925                     BGE_MODECTL_WORDSWAP_B2HRX_DATA |
1926                     BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE);
1927         }
1928         mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1929             BGE_MODECTL_TX_NO_PHDR_CSUM;
1930
1931         /*
1932          * BCM5701 B5 have a bug causing data corruption when using
1933          * 64-bit DMA reads, which can be terminated early and then
1934          * completed later as 32-bit accesses, in combination with
1935          * certain bridges.
1936          */
1937         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1938             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1939                 mode_ctl |= BGE_MODECTL_FORCE_PCI32;
1940
1941         /*
1942          * Tell the firmware the driver is running
1943          */
1944         if (sc->bge_asf_mode & ASF_STACKUP)
1945                 mode_ctl |= BGE_MODECTL_STACKUP;
1946
1947         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1948
1949         /*
1950          * Disable memory write invalidate.  Apparently it is not supported
1951          * properly by these devices.
1952          */
1953         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1954
1955         /* Set the timer prescaler (always 66 MHz). */
1956         CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1957
1958         /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1959         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1960                 DELAY(40);      /* XXX */
1961
1962                 /* Put PHY into ready state */
1963                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1964                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1965                 DELAY(40);
1966         }
1967
1968         return (0);
1969 }
1970
1971 static int
1972 bge_blockinit(struct bge_softc *sc)
1973 {
1974         struct bge_rcb *rcb;
1975         bus_size_t vrcb;
1976         bge_hostaddr taddr;
1977         uint32_t dmactl, rdmareg, val;
1978         int i, limit;
1979
1980         /*
1981          * Initialize the memory window pointer register so that
1982          * we can access the first 32K of internal NIC RAM. This will
1983          * allow us to set up the TX send ring RCBs and the RX return
1984          * ring RCBs, plus other things which live in NIC memory.
1985          */
1986         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1987
1988         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1989
1990         if (!(BGE_IS_5705_PLUS(sc))) {
1991                 /* Configure mbuf memory pool */
1992                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1993                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1994                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1995                 else
1996                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1997
1998                 /* Configure DMA resource pool */
1999                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
2000                     BGE_DMA_DESCRIPTORS);
2001                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
2002         }
2003
2004         /* Configure mbuf pool watermarks */
2005         if (BGE_IS_5717_PLUS(sc)) {
2006                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2007                 if (if_getmtu(sc->bge_ifp) > ETHERMTU) {
2008                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
2009                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
2010                 } else {
2011                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
2012                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
2013                 }
2014         } else if (!BGE_IS_5705_PLUS(sc)) {
2015                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
2016                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
2017                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2018         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2019                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2020                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
2021                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
2022         } else {
2023                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2024                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
2025                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2026         }
2027
2028         /* Configure DMA resource watermarks */
2029         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
2030         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
2031
2032         /* Enable buffer manager */
2033         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
2034         /*
2035          * Change the arbitration algorithm of TXMBUF read request to
2036          * round-robin instead of priority based for BCM5719.  When
2037          * TXFIFO is almost empty, RDMA will hold its request until
2038          * TXFIFO is not almost empty.
2039          */
2040         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2041                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
2042         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
2043
2044         /* Poll for buffer manager start indication */
2045         for (i = 0; i < BGE_TIMEOUT; i++) {
2046                 DELAY(10);
2047                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
2048                         break;
2049         }
2050
2051         if (i == BGE_TIMEOUT) {
2052                 device_printf(sc->bge_dev, "buffer manager failed to start\n");
2053                 return (ENXIO);
2054         }
2055
2056         /* Enable flow-through queues */
2057         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2058         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2059
2060         /* Wait until queue initialization is complete */
2061         for (i = 0; i < BGE_TIMEOUT; i++) {
2062                 DELAY(10);
2063                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
2064                         break;
2065         }
2066
2067         if (i == BGE_TIMEOUT) {
2068                 device_printf(sc->bge_dev, "flow-through queue init failed\n");
2069                 return (ENXIO);
2070         }
2071
2072         /*
2073          * Summary of rings supported by the controller:
2074          *
2075          * Standard Receive Producer Ring
2076          * - This ring is used to feed receive buffers for "standard"
2077          *   sized frames (typically 1536 bytes) to the controller.
2078          *
2079          * Jumbo Receive Producer Ring
2080          * - This ring is used to feed receive buffers for jumbo sized
2081          *   frames (i.e. anything bigger than the "standard" frames)
2082          *   to the controller.
2083          *
2084          * Mini Receive Producer Ring
2085          * - This ring is used to feed receive buffers for "mini"
2086          *   sized frames to the controller.
2087          * - This feature required external memory for the controller
2088          *   but was never used in a production system.  Should always
2089          *   be disabled.
2090          *
2091          * Receive Return Ring
2092          * - After the controller has placed an incoming frame into a
2093          *   receive buffer that buffer is moved into a receive return
2094          *   ring.  The driver is then responsible to passing the
2095          *   buffer up to the stack.  Many versions of the controller
2096          *   support multiple RR rings.
2097          *
2098          * Send Ring
2099          * - This ring is used for outgoing frames.  Many versions of
2100          *   the controller support multiple send rings.
2101          */
2102
2103         /* Initialize the standard receive producer ring control block. */
2104         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
2105         rcb->bge_hostaddr.bge_addr_lo =
2106             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
2107         rcb->bge_hostaddr.bge_addr_hi =
2108             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
2109         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2110             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
2111         if (BGE_IS_5717_PLUS(sc)) {
2112                 /*
2113                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
2114                  * Bits 15-2 : Maximum RX frame size
2115                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
2116                  * Bit 0     : Reserved
2117                  */
2118                 rcb->bge_maxlen_flags =
2119                     BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
2120         } else if (BGE_IS_5705_PLUS(sc)) {
2121                 /*
2122                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
2123                  * Bits 15-2 : Reserved (should be 0)
2124                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
2125                  * Bit 0     : Reserved
2126                  */
2127                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
2128         } else {
2129                 /*
2130                  * Ring size is always XXX entries
2131                  * Bits 31-16: Maximum RX frame size
2132                  * Bits 15-2 : Reserved (should be 0)
2133                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
2134                  * Bit 0     : Reserved
2135                  */
2136                 rcb->bge_maxlen_flags =
2137                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
2138         }
2139         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2140             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2141             sc->bge_asicrev == BGE_ASICREV_BCM5720)
2142                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
2143         else
2144                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
2145         /* Write the standard receive producer ring control block. */
2146         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
2147         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
2148         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
2149         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
2150
2151         /* Reset the standard receive producer ring producer index. */
2152         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
2153
2154         /*
2155          * Initialize the jumbo RX producer ring control
2156          * block.  We set the 'ring disabled' bit in the
2157          * flags field until we're actually ready to start
2158          * using this ring (i.e. once we set the MTU
2159          * high enough to require it).
2160          */
2161         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2162                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
2163                 /* Get the jumbo receive producer ring RCB parameters. */
2164                 rcb->bge_hostaddr.bge_addr_lo =
2165                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2166                 rcb->bge_hostaddr.bge_addr_hi =
2167                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2168                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2169                     sc->bge_cdata.bge_rx_jumbo_ring_map,
2170                     BUS_DMASYNC_PREREAD);
2171                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
2172                     BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
2173                 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2174                     sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2175                     sc->bge_asicrev == BGE_ASICREV_BCM5720)
2176                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
2177                 else
2178                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
2179                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
2180                     rcb->bge_hostaddr.bge_addr_hi);
2181                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
2182                     rcb->bge_hostaddr.bge_addr_lo);
2183                 /* Program the jumbo receive producer ring RCB parameters. */
2184                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
2185                     rcb->bge_maxlen_flags);
2186                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
2187                 /* Reset the jumbo receive producer ring producer index. */
2188                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
2189         }
2190
2191         /* Disable the mini receive producer ring RCB. */
2192         if (BGE_IS_5700_FAMILY(sc)) {
2193                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
2194                 rcb->bge_maxlen_flags =
2195                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
2196                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
2197                     rcb->bge_maxlen_flags);
2198                 /* Reset the mini receive producer ring producer index. */
2199                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
2200         }
2201
2202         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
2203         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2204                 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
2205                     sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
2206                     sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
2207                         CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
2208                             (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
2209         }
2210         /*
2211          * The BD ring replenish thresholds control how often the
2212          * hardware fetches new BD's from the producer rings in host
2213          * memory.  Setting the value too low on a busy system can
2214          * starve the hardware and recue the throughpout.
2215          *
2216          * Set the BD ring replentish thresholds. The recommended
2217          * values are 1/8th the number of descriptors allocated to
2218          * each ring.
2219          * XXX The 5754 requires a lower threshold, so it might be a
2220          * requirement of all 575x family chips.  The Linux driver sets
2221          * the lower threshold for all 5705 family chips as well, but there
2222          * are reports that it might not need to be so strict.
2223          *
2224          * XXX Linux does some extra fiddling here for the 5906 parts as
2225          * well.
2226          */
2227         if (BGE_IS_5705_PLUS(sc))
2228                 val = 8;
2229         else
2230                 val = BGE_STD_RX_RING_CNT / 8;
2231         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
2232         if (BGE_IS_JUMBO_CAPABLE(sc))
2233                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
2234                     BGE_JUMBO_RX_RING_CNT/8);
2235         if (BGE_IS_5717_PLUS(sc)) {
2236                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
2237                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
2238         }
2239
2240         /*
2241          * Disable all send rings by setting the 'ring disabled' bit
2242          * in the flags field of all the TX send ring control blocks,
2243          * located in NIC memory.
2244          */
2245         if (!BGE_IS_5705_PLUS(sc))
2246                 /* 5700 to 5704 had 16 send rings. */
2247                 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
2248         else if (BGE_IS_57765_PLUS(sc) ||
2249             sc->bge_asicrev == BGE_ASICREV_BCM5762)
2250                 limit = 2;
2251         else if (BGE_IS_5717_PLUS(sc))
2252                 limit = 4;
2253         else
2254                 limit = 1;
2255         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2256         for (i = 0; i < limit; i++) {
2257                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2258                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
2259                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2260                 vrcb += sizeof(struct bge_rcb);
2261         }
2262
2263         /* Configure send ring RCB 0 (we use only the first ring) */
2264         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2265         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
2266         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2267         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2268         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2269             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2270             sc->bge_asicrev == BGE_ASICREV_BCM5720)
2271                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
2272         else
2273                 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
2274                     BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
2275         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2276             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
2277
2278         /*
2279          * Disable all receive return rings by setting the
2280          * 'ring diabled' bit in the flags field of all the receive
2281          * return ring control blocks, located in NIC memory.
2282          */
2283         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2284             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2285             sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2286                 /* Should be 17, use 16 until we get an SRAM map. */
2287                 limit = 16;
2288         } else if (!BGE_IS_5705_PLUS(sc))
2289                 limit = BGE_RX_RINGS_MAX;
2290         else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2291             sc->bge_asicrev == BGE_ASICREV_BCM5762 ||
2292             BGE_IS_57765_PLUS(sc))
2293                 limit = 4;
2294         else
2295                 limit = 1;
2296         /* Disable all receive return rings. */
2297         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2298         for (i = 0; i < limit; i++) {
2299                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
2300                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
2301                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2302                     BGE_RCB_FLAG_RING_DISABLED);
2303                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2304                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
2305                     (i * (sizeof(uint64_t))), 0);
2306                 vrcb += sizeof(struct bge_rcb);
2307         }
2308
2309         /*
2310          * Set up receive return ring 0.  Note that the NIC address
2311          * for RX return rings is 0x0.  The return rings live entirely
2312          * within the host, so the nicaddr field in the RCB isn't used.
2313          */
2314         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2315         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
2316         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2317         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2318         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2319         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2320             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
2321
2322         /* Set random backoff seed for TX */
2323         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
2324             (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
2325             IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
2326             IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) &
2327             BGE_TX_BACKOFF_SEED_MASK);
2328
2329         /* Set inter-packet gap */
2330         val = 0x2620;
2331         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2332             sc->bge_asicrev == BGE_ASICREV_BCM5762)
2333                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
2334                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
2335         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
2336
2337         /*
2338          * Specify which ring to use for packets that don't match
2339          * any RX rules.
2340          */
2341         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
2342
2343         /*
2344          * Configure number of RX lists. One interrupt distribution
2345          * list, sixteen active lists, one bad frames class.
2346          */
2347         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
2348
2349         /* Inialize RX list placement stats mask. */
2350         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
2351         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
2352
2353         /* Disable host coalescing until we get it set up */
2354         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
2355
2356         /* Poll to make sure it's shut down. */
2357         for (i = 0; i < BGE_TIMEOUT; i++) {
2358                 DELAY(10);
2359                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
2360                         break;
2361         }
2362
2363         if (i == BGE_TIMEOUT) {
2364                 device_printf(sc->bge_dev,
2365                     "host coalescing engine failed to idle\n");
2366                 return (ENXIO);
2367         }
2368
2369         /* Set up host coalescing defaults */
2370         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
2371         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
2372         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
2373         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
2374         if (!(BGE_IS_5705_PLUS(sc))) {
2375                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
2376                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
2377         }
2378         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
2379         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
2380
2381         /* Set up address of statistics block */
2382         if (!(BGE_IS_5705_PLUS(sc))) {
2383                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
2384                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
2385                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
2386                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
2387                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
2388                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
2389                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
2390         }
2391
2392         /* Set up address of status block */
2393         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
2394             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
2395         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
2396             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
2397
2398         /* Set up status block size. */
2399         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2400             sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
2401                 val = BGE_STATBLKSZ_FULL;
2402                 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2403         } else {
2404                 val = BGE_STATBLKSZ_32BYTE;
2405                 bzero(sc->bge_ldata.bge_status_block, 32);
2406         }
2407         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2408             sc->bge_cdata.bge_status_map,
2409             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2410
2411         /* Turn on host coalescing state machine */
2412         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2413
2414         /* Turn on RX BD completion state machine and enable attentions */
2415         CSR_WRITE_4(sc, BGE_RBDC_MODE,
2416             BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
2417
2418         /* Turn on RX list placement state machine */
2419         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2420
2421         /* Turn on RX list selector state machine. */
2422         if (!(BGE_IS_5705_PLUS(sc)))
2423                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2424
2425         /* Turn on DMA, clear stats. */
2426         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
2427             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
2428             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
2429             BGE_MACMODE_FRMHDR_DMA_ENB;
2430
2431         if (sc->bge_flags & BGE_FLAG_TBI)
2432                 val |= BGE_PORTMODE_TBI;
2433         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
2434                 val |= BGE_PORTMODE_GMII;
2435         else
2436                 val |= BGE_PORTMODE_MII;
2437
2438         /* Allow APE to send/receive frames. */
2439         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
2440                 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
2441
2442         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
2443         DELAY(40);
2444
2445         /* Set misc. local control, enable interrupts on attentions */
2446         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2447
2448 #ifdef notdef
2449         /* Assert GPIO pins for PHY reset */
2450         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
2451             BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
2452         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
2453             BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
2454 #endif
2455
2456         /* Turn on DMA completion state machine */
2457         if (!(BGE_IS_5705_PLUS(sc)))
2458                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2459
2460         val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
2461
2462         /* Enable host coalescing bug fix. */
2463         if (BGE_IS_5755_PLUS(sc))
2464                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
2465
2466         /* Request larger DMA burst size to get better performance. */
2467         if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
2468                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
2469
2470         /* Turn on write DMA state machine */
2471         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
2472         DELAY(40);
2473
2474         /* Turn on read DMA state machine */
2475         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
2476
2477         if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
2478                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
2479
2480         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2481             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2482             sc->bge_asicrev == BGE_ASICREV_BCM57780)
2483                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
2484                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
2485                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
2486         if (sc->bge_flags & BGE_FLAG_PCIE)
2487                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2488         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2489                 val |= BGE_RDMAMODE_TSO4_ENABLE;
2490                 if (sc->bge_flags & BGE_FLAG_TSO3 ||
2491                     sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2492                     sc->bge_asicrev == BGE_ASICREV_BCM57780)
2493                         val |= BGE_RDMAMODE_TSO6_ENABLE;
2494         }
2495
2496         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2497             sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2498                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
2499                         BGE_RDMAMODE_H2BNC_VLAN_DET;
2500                 /*
2501                  * Allow multiple outstanding read requests from
2502                  * non-LSO read DMA engine.
2503                  */
2504                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
2505         }
2506
2507         if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2508             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2509             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2510             sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2511             BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) {
2512                 if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
2513                         rdmareg = BGE_RDMA_RSRVCTRL_REG2;
2514                 else
2515                         rdmareg = BGE_RDMA_RSRVCTRL;
2516                 dmactl = CSR_READ_4(sc, rdmareg);
2517                 /*
2518                  * Adjust tx margin to prevent TX data corruption and
2519                  * fix internal FIFO overflow.
2520                  */
2521                 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 ||
2522                     sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2523                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2524                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2525                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2526                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2527                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2528                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2529                 }
2530                 /*
2531                  * Enable fix for read DMA FIFO overruns.
2532                  * The fix is to limit the number of RX BDs
2533                  * the hardware would fetch at a fime.
2534                  */
2535                 CSR_WRITE_4(sc, rdmareg, dmactl |
2536                     BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2537         }
2538
2539         if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2540                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2541                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2542                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2543                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2544         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2545                 /*
2546                  * Allow 4KB burst length reads for non-LSO frames.
2547                  * Enable 512B burst length reads for buffer descriptors.
2548                  */
2549                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2550                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2551                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
2552                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2553         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2554                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2,
2555                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |
2556                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2557                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2558         }
2559
2560         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2561         DELAY(40);
2562
2563         if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
2564                 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) {
2565                         val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);
2566                         if ((val & 0xFFFF) > BGE_FRAMELEN)
2567                                 break;
2568                         if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN)
2569                                 break;
2570                 }
2571                 if (i != BGE_NUM_RDMA_CHANNELS / 2) {
2572                         val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
2573                         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2574                                 val |= BGE_RDMA_TX_LENGTH_WA_5719;
2575                         else
2576                                 val |= BGE_RDMA_TX_LENGTH_WA_5720;
2577                         CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
2578                 }
2579         }
2580
2581         /* Turn on RX data completion state machine */
2582         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2583
2584         /* Turn on RX BD initiator state machine */
2585         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2586
2587         /* Turn on RX data and RX BD initiator state machine */
2588         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2589
2590         /* Turn on Mbuf cluster free state machine */
2591         if (!(BGE_IS_5705_PLUS(sc)))
2592                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2593
2594         /* Turn on send BD completion state machine */
2595         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2596
2597         /* Turn on send data completion state machine */
2598         val = BGE_SDCMODE_ENABLE;
2599         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2600                 val |= BGE_SDCMODE_CDELAY;
2601         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2602
2603         /* Turn on send data initiator state machine */
2604         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2605                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2606                     BGE_SDIMODE_HW_LSO_PRE_DMA);
2607         else
2608                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2609
2610         /* Turn on send BD initiator state machine */
2611         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2612
2613         /* Turn on send BD selector state machine */
2614         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2615
2616         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
2617         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
2618             BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
2619
2620         /* ack/clear link change events */
2621         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2622             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2623             BGE_MACSTAT_LINK_CHANGED);
2624         CSR_WRITE_4(sc, BGE_MI_STS, 0);
2625
2626         /*
2627          * Enable attention when the link has changed state for
2628          * devices that use auto polling.
2629          */
2630         if (sc->bge_flags & BGE_FLAG_TBI) {
2631                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
2632         } else {
2633                 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2634                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
2635                         DELAY(80);
2636                 }
2637                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2638                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
2639                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2640                             BGE_EVTENB_MI_INTERRUPT);
2641         }
2642
2643         /*
2644          * Clear any pending link state attention.
2645          * Otherwise some link state change events may be lost until attention
2646          * is cleared by bge_intr() -> bge_link_upd() sequence.
2647          * It's not necessary on newer BCM chips - perhaps enabling link
2648          * state change attentions implies clearing pending attention.
2649          */
2650         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2651             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2652             BGE_MACSTAT_LINK_CHANGED);
2653
2654         /* Enable link state change attentions. */
2655         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2656
2657         return (0);
2658 }
2659
2660 static const struct bge_revision *
2661 bge_lookup_rev(uint32_t chipid)
2662 {
2663         const struct bge_revision *br;
2664
2665         for (br = bge_revisions; br->br_name != NULL; br++) {
2666                 if (br->br_chipid == chipid)
2667                         return (br);
2668         }
2669
2670         for (br = bge_majorrevs; br->br_name != NULL; br++) {
2671                 if (br->br_chipid == BGE_ASICREV(chipid))
2672                         return (br);
2673         }
2674
2675         return (NULL);
2676 }
2677
2678 static const struct bge_vendor *
2679 bge_lookup_vendor(uint16_t vid)
2680 {
2681         const struct bge_vendor *v;
2682
2683         for (v = bge_vendors; v->v_name != NULL; v++)
2684                 if (v->v_id == vid)
2685                         return (v);
2686
2687         return (NULL);
2688 }
2689
2690 static uint32_t
2691 bge_chipid(device_t dev)
2692 {
2693         uint32_t id;
2694
2695         id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2696             BGE_PCIMISCCTL_ASICREV_SHIFT;
2697         if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
2698                 /*
2699                  * Find the ASCI revision.  Different chips use different
2700                  * registers.
2701                  */
2702                 switch (pci_get_device(dev)) {
2703                 case BCOM_DEVICEID_BCM5717C:
2704                         /* 5717 C0 seems to belong to 5720 line. */
2705                         id = BGE_CHIPID_BCM5720_A0;
2706                         break;
2707                 case BCOM_DEVICEID_BCM5717:
2708                 case BCOM_DEVICEID_BCM5718:
2709                 case BCOM_DEVICEID_BCM5719:
2710                 case BCOM_DEVICEID_BCM5720:
2711                 case BCOM_DEVICEID_BCM5725:
2712                 case BCOM_DEVICEID_BCM5727:
2713                 case BCOM_DEVICEID_BCM5762:
2714                 case BCOM_DEVICEID_BCM57764:
2715                 case BCOM_DEVICEID_BCM57767:
2716                 case BCOM_DEVICEID_BCM57787:
2717                         id = pci_read_config(dev,
2718                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
2719                         break;
2720                 case BCOM_DEVICEID_BCM57761:
2721                 case BCOM_DEVICEID_BCM57762:
2722                 case BCOM_DEVICEID_BCM57765:
2723                 case BCOM_DEVICEID_BCM57766:
2724                 case BCOM_DEVICEID_BCM57781:
2725                 case BCOM_DEVICEID_BCM57782:
2726                 case BCOM_DEVICEID_BCM57785:
2727                 case BCOM_DEVICEID_BCM57786:
2728                 case BCOM_DEVICEID_BCM57791:
2729                 case BCOM_DEVICEID_BCM57795:
2730                         id = pci_read_config(dev,
2731                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
2732                         break;
2733                 default:
2734                         id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
2735                 }
2736         }
2737         return (id);
2738 }
2739
2740 /*
2741  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
2742  * against our list and return its name if we find a match.
2743  *
2744  * Note that since the Broadcom controller contains VPD support, we
2745  * try to get the device name string from the controller itself instead
2746  * of the compiled-in string. It guarantees we'll always announce the
2747  * right product name. We fall back to the compiled-in string when
2748  * VPD is unavailable or corrupt.
2749  */
2750 static int
2751 bge_probe(device_t dev)
2752 {
2753         char buf[96];
2754         char model[64];
2755         const struct bge_revision *br;
2756         const char *pname;
2757         struct bge_softc *sc;
2758         const struct bge_type *t = bge_devs;
2759         const struct bge_vendor *v;
2760         uint32_t id;
2761         uint16_t did, vid;
2762
2763         sc = device_get_softc(dev);
2764         sc->bge_dev = dev;
2765         vid = pci_get_vendor(dev);
2766         did = pci_get_device(dev);
2767         while(t->bge_vid != 0) {
2768                 if ((vid == t->bge_vid) && (did == t->bge_did)) {
2769                         id = bge_chipid(dev);
2770                         br = bge_lookup_rev(id);
2771                         if (bge_has_eaddr(sc) &&
2772                             pci_get_vpd_ident(dev, &pname) == 0)
2773                                 snprintf(model, sizeof(model), "%s", pname);
2774                         else {
2775                                 v = bge_lookup_vendor(vid);
2776                                 snprintf(model, sizeof(model), "%s %s",
2777                                     v != NULL ? v->v_name : "Unknown",
2778                                     br != NULL ? br->br_name :
2779                                     "NetXtreme/NetLink Ethernet Controller");
2780                         }
2781                         snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x",
2782                             model, br != NULL ? "" : "unknown ", id);
2783                         device_set_desc_copy(dev, buf);
2784                         return (BUS_PROBE_DEFAULT);
2785                 }
2786                 t++;
2787         }
2788
2789         return (ENXIO);
2790 }
2791
2792 static void
2793 bge_dma_free(struct bge_softc *sc)
2794 {
2795         int i;
2796
2797         /* Destroy DMA maps for RX buffers. */
2798         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2799                 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2800                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2801                             sc->bge_cdata.bge_rx_std_dmamap[i]);
2802         }
2803         if (sc->bge_cdata.bge_rx_std_sparemap)
2804                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2805                     sc->bge_cdata.bge_rx_std_sparemap);
2806
2807         /* Destroy DMA maps for jumbo RX buffers. */
2808         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2809                 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2810                         bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2811                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2812         }
2813         if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2814                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2815                     sc->bge_cdata.bge_rx_jumbo_sparemap);
2816
2817         /* Destroy DMA maps for TX buffers. */
2818         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2819                 if (sc->bge_cdata.bge_tx_dmamap[i])
2820                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2821                             sc->bge_cdata.bge_tx_dmamap[i]);
2822         }
2823
2824         if (sc->bge_cdata.bge_rx_mtag)
2825                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2826         if (sc->bge_cdata.bge_mtag_jumbo)
2827                 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
2828         if (sc->bge_cdata.bge_tx_mtag)
2829                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2830
2831         /* Destroy standard RX ring. */
2832         if (sc->bge_ldata.bge_rx_std_ring_paddr)
2833                 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2834                     sc->bge_cdata.bge_rx_std_ring_map);
2835         if (sc->bge_ldata.bge_rx_std_ring)
2836                 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2837                     sc->bge_ldata.bge_rx_std_ring,
2838                     sc->bge_cdata.bge_rx_std_ring_map);
2839
2840         if (sc->bge_cdata.bge_rx_std_ring_tag)
2841                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2842
2843         /* Destroy jumbo RX ring. */
2844         if (sc->bge_ldata.bge_rx_jumbo_ring_paddr)
2845                 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2846                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2847
2848         if (sc->bge_ldata.bge_rx_jumbo_ring)
2849                 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2850                     sc->bge_ldata.bge_rx_jumbo_ring,
2851                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2852
2853         if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2854                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2855
2856         /* Destroy RX return ring. */
2857         if (sc->bge_ldata.bge_rx_return_ring_paddr)
2858                 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2859                     sc->bge_cdata.bge_rx_return_ring_map);
2860
2861         if (sc->bge_ldata.bge_rx_return_ring)
2862                 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2863                     sc->bge_ldata.bge_rx_return_ring,
2864                     sc->bge_cdata.bge_rx_return_ring_map);
2865
2866         if (sc->bge_cdata.bge_rx_return_ring_tag)
2867                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2868
2869         /* Destroy TX ring. */
2870         if (sc->bge_ldata.bge_tx_ring_paddr)
2871                 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2872                     sc->bge_cdata.bge_tx_ring_map);
2873
2874         if (sc->bge_ldata.bge_tx_ring)
2875                 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2876                     sc->bge_ldata.bge_tx_ring,
2877                     sc->bge_cdata.bge_tx_ring_map);
2878
2879         if (sc->bge_cdata.bge_tx_ring_tag)
2880                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2881
2882         /* Destroy status block. */
2883         if (sc->bge_ldata.bge_status_block_paddr)
2884                 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2885                     sc->bge_cdata.bge_status_map);
2886
2887         if (sc->bge_ldata.bge_status_block)
2888                 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2889                     sc->bge_ldata.bge_status_block,
2890                     sc->bge_cdata.bge_status_map);
2891
2892         if (sc->bge_cdata.bge_status_tag)
2893                 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2894
2895         /* Destroy statistics block. */
2896         if (sc->bge_ldata.bge_stats_paddr)
2897                 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2898                     sc->bge_cdata.bge_stats_map);
2899
2900         if (sc->bge_ldata.bge_stats)
2901                 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2902                     sc->bge_ldata.bge_stats,
2903                     sc->bge_cdata.bge_stats_map);
2904
2905         if (sc->bge_cdata.bge_stats_tag)
2906                 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2907
2908         if (sc->bge_cdata.bge_buffer_tag)
2909                 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
2910
2911         /* Destroy the parent tag. */
2912         if (sc->bge_cdata.bge_parent_tag)
2913                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2914 }
2915
2916 static int
2917 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
2918     bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
2919     bus_addr_t *paddr, const char *msg)
2920 {
2921         struct bge_dmamap_arg ctx;
2922         int error;
2923
2924         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2925             alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2926             NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
2927         if (error != 0) {
2928                 device_printf(sc->bge_dev,
2929                     "could not create %s dma tag\n", msg);
2930                 return (ENOMEM);
2931         }
2932         /* Allocate DMA'able memory for ring. */
2933         error = bus_dmamem_alloc(*tag, (void **)ring,
2934             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
2935         if (error != 0) {
2936                 device_printf(sc->bge_dev,
2937                     "could not allocate DMA'able memory for %s\n", msg);
2938                 return (ENOMEM);
2939         }
2940         /* Load the address of the ring. */
2941         ctx.bge_busaddr = 0;
2942         error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr,
2943             &ctx, BUS_DMA_NOWAIT);
2944         if (error != 0) {
2945                 device_printf(sc->bge_dev,
2946                     "could not load DMA'able memory for %s\n", msg);
2947                 return (ENOMEM);
2948         }
2949         *paddr = ctx.bge_busaddr;
2950         return (0);
2951 }
2952
2953 static int
2954 bge_dma_alloc(struct bge_softc *sc)
2955 {
2956         bus_addr_t lowaddr;
2957         bus_size_t rxmaxsegsz, sbsz, txsegsz, txmaxsegsz;
2958         int i, error;
2959
2960         lowaddr = BUS_SPACE_MAXADDR;
2961         if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2962                 lowaddr = BGE_DMA_MAXADDR;
2963         /*
2964          * Allocate the parent bus DMA tag appropriate for PCI.
2965          */
2966         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2967             1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2968             NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2969             0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2970         if (error != 0) {
2971                 device_printf(sc->bge_dev,
2972                     "could not allocate parent dma tag\n");
2973                 return (ENOMEM);
2974         }
2975
2976         /* Create tag for standard RX ring. */
2977         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
2978             &sc->bge_cdata.bge_rx_std_ring_tag,
2979             (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
2980             &sc->bge_cdata.bge_rx_std_ring_map,
2981             &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
2982         if (error)
2983                 return (error);
2984
2985         /* Create tag for RX return ring. */
2986         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
2987             &sc->bge_cdata.bge_rx_return_ring_tag,
2988             (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
2989             &sc->bge_cdata.bge_rx_return_ring_map,
2990             &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
2991         if (error)
2992                 return (error);
2993
2994         /* Create tag for TX ring. */
2995         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
2996             &sc->bge_cdata.bge_tx_ring_tag,
2997             (uint8_t **)&sc->bge_ldata.bge_tx_ring,
2998             &sc->bge_cdata.bge_tx_ring_map,
2999             &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
3000         if (error)
3001                 return (error);
3002
3003         /*
3004          * Create tag for status block.
3005          * Because we only use single Tx/Rx/Rx return ring, use
3006          * minimum status block size except BCM5700 AX/BX which
3007          * seems to want to see full status block size regardless
3008          * of configured number of ring.
3009          */
3010         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3011             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
3012                 sbsz = BGE_STATUS_BLK_SZ;
3013         else
3014                 sbsz = 32;
3015         error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
3016             &sc->bge_cdata.bge_status_tag,
3017             (uint8_t **)&sc->bge_ldata.bge_status_block,
3018             &sc->bge_cdata.bge_status_map,
3019             &sc->bge_ldata.bge_status_block_paddr, "status block");
3020         if (error)
3021                 return (error);
3022
3023         /* Create tag for statistics block. */
3024         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
3025             &sc->bge_cdata.bge_stats_tag,
3026             (uint8_t **)&sc->bge_ldata.bge_stats,
3027             &sc->bge_cdata.bge_stats_map,
3028             &sc->bge_ldata.bge_stats_paddr, "statistics block");
3029         if (error)
3030                 return (error);
3031
3032         /* Create tag for jumbo RX ring. */
3033         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3034                 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
3035                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
3036                     (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
3037                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
3038                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
3039                 if (error)
3040                         return (error);
3041         }
3042
3043         /* Create parent tag for buffers. */
3044         if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
3045                 /*
3046                  * XXX
3047                  * watchdog timeout issue was observed on BCM5704 which
3048                  * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge).
3049                  * Both limiting DMA address space to 32bits and flushing
3050                  * mailbox write seem to address the issue.
3051                  */
3052                 if (sc->bge_pcixcap != 0)
3053                         lowaddr = BUS_SPACE_MAXADDR_32BIT;
3054         }
3055         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 1, 0, lowaddr,
3056             BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0,
3057             BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
3058             &sc->bge_cdata.bge_buffer_tag);
3059         if (error != 0) {
3060                 device_printf(sc->bge_dev,
3061                     "could not allocate buffer dma tag\n");
3062                 return (ENOMEM);
3063         }
3064         /* Create tag for Tx mbufs. */
3065         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
3066                 txsegsz = BGE_TSOSEG_SZ;
3067                 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
3068         } else {
3069                 txsegsz = MCLBYTES;
3070                 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
3071         }
3072         error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
3073             0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
3074             txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
3075             &sc->bge_cdata.bge_tx_mtag);
3076
3077         if (error) {
3078                 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
3079                 return (ENOMEM);
3080         }
3081
3082         /* Create tag for Rx mbufs. */
3083         if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
3084                 rxmaxsegsz = MJUM9BYTES;
3085         else
3086                 rxmaxsegsz = MCLBYTES;
3087         error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
3088             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1,
3089             rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
3090
3091         if (error) {
3092                 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
3093                 return (ENOMEM);
3094         }
3095
3096         /* Create DMA maps for RX buffers. */
3097         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3098             &sc->bge_cdata.bge_rx_std_sparemap);
3099         if (error) {
3100                 device_printf(sc->bge_dev,
3101                     "can't create spare DMA map for RX\n");
3102                 return (ENOMEM);
3103         }
3104         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3105                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3106                             &sc->bge_cdata.bge_rx_std_dmamap[i]);
3107                 if (error) {
3108                         device_printf(sc->bge_dev,
3109                             "can't create DMA map for RX\n");
3110                         return (ENOMEM);
3111                 }
3112         }
3113
3114         /* Create DMA maps for TX buffers. */
3115         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3116                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
3117                             &sc->bge_cdata.bge_tx_dmamap[i]);
3118                 if (error) {
3119                         device_printf(sc->bge_dev,
3120                             "can't create DMA map for TX\n");
3121                         return (ENOMEM);
3122                 }
3123         }
3124
3125         /* Create tags for jumbo RX buffers. */
3126         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3127                 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
3128                     1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
3129                     NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
3130                     0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
3131                 if (error) {
3132                         device_printf(sc->bge_dev,
3133                             "could not allocate jumbo dma tag\n");
3134                         return (ENOMEM);
3135                 }
3136                 /* Create DMA maps for jumbo RX buffers. */
3137                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3138                     0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
3139                 if (error) {
3140                         device_printf(sc->bge_dev,
3141                             "can't create spare DMA map for jumbo RX\n");
3142                         return (ENOMEM);
3143                 }
3144                 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
3145                         error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3146                                     0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
3147                         if (error) {
3148                                 device_printf(sc->bge_dev,
3149                                     "can't create DMA map for jumbo RX\n");
3150                                 return (ENOMEM);
3151                         }
3152                 }
3153         }
3154
3155         return (0);
3156 }
3157
3158 /*
3159  * Return true if this device has more than one port.
3160  */
3161 static int
3162 bge_has_multiple_ports(struct bge_softc *sc)
3163 {
3164         device_t dev = sc->bge_dev;
3165         u_int b, d, f, fscan, s;
3166
3167         d = pci_get_domain(dev);
3168         b = pci_get_bus(dev);
3169         s = pci_get_slot(dev);
3170         f = pci_get_function(dev);
3171         for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
3172                 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
3173                         return (1);
3174         return (0);
3175 }
3176
3177 /*
3178  * Return true if MSI can be used with this device.
3179  */
3180 static int
3181 bge_can_use_msi(struct bge_softc *sc)
3182 {
3183         int can_use_msi = 0;
3184
3185         if (sc->bge_msi == 0)
3186                 return (0);
3187
3188         /* Disable MSI for polling(4). */
3189 #ifdef DEVICE_POLLING
3190         return (0);
3191 #endif
3192         switch (sc->bge_asicrev) {
3193         case BGE_ASICREV_BCM5714_A0:
3194         case BGE_ASICREV_BCM5714:
3195                 /*
3196                  * Apparently, MSI doesn't work when these chips are
3197                  * configured in single-port mode.
3198                  */
3199                 if (bge_has_multiple_ports(sc))
3200                         can_use_msi = 1;
3201                 break;
3202         case BGE_ASICREV_BCM5750:
3203                 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
3204                     sc->bge_chiprev != BGE_CHIPREV_5750_BX)
3205                         can_use_msi = 1;
3206                 break;
3207         default:
3208                 if (BGE_IS_575X_PLUS(sc))
3209                         can_use_msi = 1;
3210         }
3211         return (can_use_msi);
3212 }
3213
3214 static int
3215 bge_mbox_reorder(struct bge_softc *sc)
3216 {
3217         /* Lists of PCI bridges that are known to reorder mailbox writes. */
3218         static const struct mbox_reorder {
3219                 const uint16_t vendor;
3220                 const uint16_t device;
3221                 const char *desc;
3222         } mbox_reorder_lists[] = {
3223                 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" },
3224         };
3225         devclass_t pci, pcib;
3226         device_t bus, dev;
3227         int i;
3228
3229         pci = devclass_find("pci");
3230         pcib = devclass_find("pcib");
3231         dev = sc->bge_dev;
3232         bus = device_get_parent(dev);
3233         for (;;) {
3234                 dev = device_get_parent(bus);
3235                 bus = device_get_parent(dev);
3236                 if (device_get_devclass(dev) != pcib)
3237                         break;
3238                 for (i = 0; i < nitems(mbox_reorder_lists); i++) {
3239                         if (pci_get_vendor(dev) ==
3240                             mbox_reorder_lists[i].vendor &&
3241                             pci_get_device(dev) ==
3242                             mbox_reorder_lists[i].device) {
3243                                 device_printf(sc->bge_dev,
3244                                     "enabling MBOX workaround for %s\n",
3245                                     mbox_reorder_lists[i].desc);
3246                                 return (1);
3247                         }
3248                 }
3249                 if (device_get_devclass(bus) != pci)
3250                         break;
3251         }
3252         return (0);
3253 }
3254
3255 static void
3256 bge_devinfo(struct bge_softc *sc)
3257 {
3258         uint32_t cfg, clk;
3259
3260         device_printf(sc->bge_dev,
3261             "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ",
3262             sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev);
3263         if (sc->bge_flags & BGE_FLAG_PCIE)
3264                 printf("PCI-E\n");
3265         else if (sc->bge_flags & BGE_FLAG_PCIX) {
3266                 printf("PCI-X ");
3267                 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3268                 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE)
3269                         clk = 133;
3270                 else {
3271                         clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
3272                         switch (clk) {
3273                         case 0:
3274                                 clk = 33;
3275                                 break;
3276                         case 2:
3277                                 clk = 50;
3278                                 break;
3279                         case 4:
3280                                 clk = 66;
3281                                 break;
3282                         case 6:
3283                                 clk = 100;
3284                                 break;
3285                         case 7:
3286                                 clk = 133;
3287                                 break;
3288                         }
3289                 }
3290                 printf("%u MHz\n", clk);
3291         } else {
3292                 if (sc->bge_pcixcap != 0)
3293                         printf("PCI on PCI-X ");
3294                 else
3295                         printf("PCI ");
3296                 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3297                 if (cfg & BGE_PCISTATE_PCI_BUSSPEED)
3298                         clk = 66;
3299                 else
3300                         clk = 33;
3301                 if (cfg & BGE_PCISTATE_32BIT_BUS)
3302                         printf("%u MHz; 32bit\n", clk);
3303                 else
3304                         printf("%u MHz; 64bit\n", clk);
3305         }
3306 }
3307
3308 static int
3309 bge_attach(device_t dev)
3310 {
3311         if_t ifp;
3312         struct bge_softc *sc;
3313         uint32_t hwcfg = 0, misccfg, pcistate;
3314         u_char eaddr[ETHER_ADDR_LEN];
3315         int capmask, error, reg, rid, trys;
3316
3317         sc = device_get_softc(dev);
3318         sc->bge_dev = dev;
3319
3320         BGE_LOCK_INIT(sc, device_get_nameunit(dev));
3321         TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
3322         callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
3323
3324         pci_enable_busmaster(dev);
3325
3326         /*
3327          * Allocate control/status registers.
3328          */
3329         rid = PCIR_BAR(0);
3330         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3331             RF_ACTIVE);
3332
3333         if (sc->bge_res == NULL) {
3334                 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n");
3335                 error = ENXIO;
3336                 goto fail;
3337         }
3338
3339         /* Save various chip information. */
3340         sc->bge_func_addr = pci_get_function(dev);
3341         sc->bge_chipid = bge_chipid(dev);
3342         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
3343         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
3344
3345         /* Set default PHY address. */
3346         sc->bge_phy_addr = 1;
3347          /*
3348           * PHY address mapping for various devices.
3349           *
3350           *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
3351           * ---------+-------+-------+-------+-------+
3352           * BCM57XX  |   1   |   X   |   X   |   X   |
3353           * BCM5704  |   1   |   X   |   1   |   X   |
3354           * BCM5717  |   1   |   8   |   2   |   9   |
3355           * BCM5719  |   1   |   8   |   2   |   9   |
3356           * BCM5720  |   1   |   8   |   2   |   9   |
3357           *
3358           *          | F2 Cu | F2 Sr | F3 Cu | F3 Sr |
3359           * ---------+-------+-------+-------+-------+
3360           * BCM57XX  |   X   |   X   |   X   |   X   |
3361           * BCM5704  |   X   |   X   |   X   |   X   |
3362           * BCM5717  |   X   |   X   |   X   |   X   |
3363           * BCM5719  |   3   |   10  |   4   |   11  |
3364           * BCM5720  |   X   |   X   |   X   |   X   |
3365           *
3366           * Other addresses may respond but they are not
3367           * IEEE compliant PHYs and should be ignored.
3368           */
3369         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
3370             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3371             sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3372                 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) {
3373                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
3374                             BGE_SGDIGSTS_IS_SERDES)
3375                                 sc->bge_phy_addr = sc->bge_func_addr + 8;
3376                         else
3377                                 sc->bge_phy_addr = sc->bge_func_addr + 1;
3378                 } else {
3379                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
3380                             BGE_CPMU_PHY_STRAP_IS_SERDES)
3381                                 sc->bge_phy_addr = sc->bge_func_addr + 8;
3382                         else
3383                                 sc->bge_phy_addr = sc->bge_func_addr + 1;
3384                 }
3385         }
3386
3387         if (bge_has_eaddr(sc))
3388                 sc->bge_flags |= BGE_FLAG_EADDR;
3389
3390         /* Save chipset family. */
3391         switch (sc->bge_asicrev) {
3392         case BGE_ASICREV_BCM5762:
3393         case BGE_ASICREV_BCM57765:
3394         case BGE_ASICREV_BCM57766:
3395                 sc->bge_flags |= BGE_FLAG_57765_PLUS;
3396                 /* FALLTHROUGH */
3397         case BGE_ASICREV_BCM5717:
3398         case BGE_ASICREV_BCM5719:
3399         case BGE_ASICREV_BCM5720:
3400                 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
3401                     BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
3402                     BGE_FLAG_JUMBO_FRAME;
3403                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3404                     sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3405                         /*
3406                          * Enable work around for DMA engine miscalculation
3407                          * of TXMBUF available space.
3408                          */
3409                         sc->bge_flags |= BGE_FLAG_RDMA_BUG;
3410                         if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3411                             sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3412                                 /* Jumbo frame on BCM5719 A0 does not work. */
3413                                 sc->bge_flags &= ~BGE_FLAG_JUMBO;
3414                         }
3415                 }
3416                 break;
3417         case BGE_ASICREV_BCM5755:
3418         case BGE_ASICREV_BCM5761:
3419         case BGE_ASICREV_BCM5784:
3420         case BGE_ASICREV_BCM5785:
3421         case BGE_ASICREV_BCM5787:
3422         case BGE_ASICREV_BCM57780:
3423                 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
3424                     BGE_FLAG_5705_PLUS;
3425                 break;
3426         case BGE_ASICREV_BCM5700:
3427         case BGE_ASICREV_BCM5701:
3428         case BGE_ASICREV_BCM5703:
3429         case BGE_ASICREV_BCM5704:
3430                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
3431                 break;
3432         case BGE_ASICREV_BCM5714_A0:
3433         case BGE_ASICREV_BCM5780:
3434         case BGE_ASICREV_BCM5714:
3435                 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
3436                 /* FALLTHROUGH */
3437         case BGE_ASICREV_BCM5750:
3438         case BGE_ASICREV_BCM5752:
3439         case BGE_ASICREV_BCM5906:
3440                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
3441                 /* FALLTHROUGH */
3442         case BGE_ASICREV_BCM5705:
3443                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
3444                 break;
3445         }
3446
3447         /* Identify chips with APE processor. */
3448         switch (sc->bge_asicrev) {
3449         case BGE_ASICREV_BCM5717:
3450         case BGE_ASICREV_BCM5719:
3451         case BGE_ASICREV_BCM5720:
3452         case BGE_ASICREV_BCM5761:
3453         case BGE_ASICREV_BCM5762:
3454                 sc->bge_flags |= BGE_FLAG_APE;
3455                 break;
3456         }
3457
3458         /* Chips with APE need BAR2 access for APE registers/memory. */
3459         if ((sc->bge_flags & BGE_FLAG_APE) != 0) {
3460                 rid = PCIR_BAR(2);
3461                 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3462                     RF_ACTIVE);
3463                 if (sc->bge_res2 == NULL) {
3464                         device_printf (sc->bge_dev,
3465                             "couldn't map BAR2 memory\n");
3466                         error = ENXIO;
3467                         goto fail;
3468                 }
3469
3470                 /* Enable APE register/memory access by host driver. */
3471                 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3472                 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
3473                     BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
3474                     BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
3475                 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4);
3476
3477                 bge_ape_lock_init(sc);
3478                 bge_ape_read_fw_ver(sc);
3479         }
3480
3481         /* Add SYSCTLs, requires the chipset family to be set. */
3482         bge_add_sysctls(sc);
3483
3484         /* Identify the chips that use an CPMU. */
3485         if (BGE_IS_5717_PLUS(sc) ||
3486             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3487             sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3488             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
3489             sc->bge_asicrev == BGE_ASICREV_BCM57780)
3490                 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
3491         if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
3492                 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
3493         else
3494                 sc->bge_mi_mode = BGE_MIMODE_BASE;
3495         /* Enable auto polling for BCM570[0-5]. */
3496         if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
3497                 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
3498
3499         /*
3500          * All Broadcom controllers have 4GB boundary DMA bug.
3501          * Whenever an address crosses a multiple of the 4GB boundary
3502          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3503          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3504          * state machine will lockup and cause the device to hang.
3505          */
3506         sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
3507
3508         /* BCM5755 or higher and BCM5906 have short DMA bug. */
3509         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3510                 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
3511
3512         /*
3513          * BCM5719 cannot handle DMA requests for DMA segments that
3514          * have larger than 4KB in size.  However the maximum DMA
3515          * segment size created in DMA tag is 4KB for TSO, so we
3516          * wouldn't encounter the issue here.
3517          */
3518         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
3519                 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG;
3520
3521         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3522         if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
3523                 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
3524                     misccfg == BGE_MISCCFG_BOARD_ID_5788M)
3525                         sc->bge_flags |= BGE_FLAG_5788;
3526         }
3527
3528         capmask = BMSR_DEFCAPMASK;
3529         if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
3530             (misccfg == 0x4000 || misccfg == 0x8000)) ||
3531             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3532             pci_get_vendor(dev) == BCOM_VENDORID &&
3533             (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 ||
3534             pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 ||
3535             pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) ||
3536             (pci_get_vendor(dev) == BCOM_VENDORID &&
3537             (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F ||
3538             pci_get_device(dev) == BCOM_DEVICEID_BCM5753F ||
3539             pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) ||
3540             pci_get_device(dev) == BCOM_DEVICEID_BCM57790 ||
3541             pci_get_device(dev) == BCOM_DEVICEID_BCM57791 ||
3542             pci_get_device(dev) == BCOM_DEVICEID_BCM57795 ||
3543             sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3544                 /* These chips are 10/100 only. */
3545                 capmask &= ~BMSR_EXTSTAT;
3546                 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3547         }
3548
3549         /*
3550          * Some controllers seem to require a special firmware to use
3551          * TSO. But the firmware is not available to FreeBSD and Linux
3552          * claims that the TSO performed by the firmware is slower than
3553          * hardware based TSO. Moreover the firmware based TSO has one
3554          * known bug which can't handle TSO if Ethernet header + IP/TCP
3555          * header is greater than 80 bytes. A workaround for the TSO
3556          * bug exist but it seems it's too expensive than not using
3557          * TSO at all. Some hardwares also have the TSO bug so limit
3558          * the TSO to the controllers that are not affected TSO issues
3559          * (e.g. 5755 or higher).
3560          */
3561         if (BGE_IS_5717_PLUS(sc)) {
3562                 /* BCM5717 requires different TSO configuration. */
3563                 sc->bge_flags |= BGE_FLAG_TSO3;
3564                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3565                     sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3566                         /* TSO on BCM5719 A0 does not work. */
3567                         sc->bge_flags &= ~BGE_FLAG_TSO3;
3568                 }
3569         } else if (BGE_IS_5755_PLUS(sc)) {
3570                 /*
3571                  * BCM5754 and BCM5787 shares the same ASIC id so
3572                  * explicit device id check is required.
3573                  * Due to unknown reason TSO does not work on BCM5755M.
3574                  */
3575                 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
3576                     pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
3577                     pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
3578                         sc->bge_flags |= BGE_FLAG_TSO;
3579         }
3580
3581         /*
3582          * Check if this is a PCI-X or PCI Express device.
3583          */
3584         if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
3585                 /*
3586                  * Found a PCI Express capabilities register, this
3587                  * must be a PCI Express device.
3588                  */
3589                 sc->bge_flags |= BGE_FLAG_PCIE;
3590                 sc->bge_expcap = reg;
3591                 /* Extract supported maximum payload size. */
3592                 sc->bge_mps = pci_read_config(dev, sc->bge_expcap +
3593                     PCIER_DEVICE_CAP, 2);
3594                 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD);
3595                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3596                     sc->bge_asicrev == BGE_ASICREV_BCM5720)
3597                         sc->bge_expmrq = 2048;
3598                 else
3599                         sc->bge_expmrq = 4096;
3600                 pci_set_max_read_req(dev, sc->bge_expmrq);
3601         } else {
3602                 /*
3603                  * Check if the device is in PCI-X Mode.
3604                  * (This bit is not valid on PCI Express controllers.)
3605                  */
3606                 if (pci_find_cap(dev, PCIY_PCIX, &reg) == 0)
3607                         sc->bge_pcixcap = reg;
3608                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
3609                     BGE_PCISTATE_PCI_BUSMODE) == 0)
3610                         sc->bge_flags |= BGE_FLAG_PCIX;
3611         }
3612
3613         /*
3614          * The 40bit DMA bug applies to the 5714/5715 controllers and is
3615          * not actually a MAC controller bug but an issue with the embedded
3616          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
3617          */
3618         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
3619                 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
3620         /*
3621          * Some PCI-X bridges are known to trigger write reordering to
3622          * the mailbox registers. Typical phenomena is watchdog timeouts
3623          * caused by out-of-order TX completions.  Enable workaround for
3624          * PCI-X devices that live behind these bridges.
3625          * Note, PCI-X controllers can run in PCI mode so we can't use
3626          * BGE_FLAG_PCIX flag to detect PCI-X controllers.
3627          */
3628         if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0)
3629                 sc->bge_flags |= BGE_FLAG_MBOX_REORDER;
3630         /*
3631          * Allocate the interrupt, using MSI if possible.  These devices
3632          * support 8 MSI messages, but only the first one is used in
3633          * normal operation.
3634          */
3635         rid = 0;
3636         if (pci_find_cap(sc->bge_dev, PCIY_MSI, &reg) == 0) {
3637                 sc->bge_msicap = reg;
3638                 reg = 1;
3639                 if (bge_can_use_msi(sc) && pci_alloc_msi(dev, &reg) == 0) {
3640                         rid = 1;
3641                         sc->bge_flags |= BGE_FLAG_MSI;
3642                 }
3643         }
3644
3645         /*
3646          * All controllers except BCM5700 supports tagged status but
3647          * we use tagged status only for MSI case on BCM5717. Otherwise
3648          * MSI on BCM5717 does not work.
3649          */
3650 #ifndef DEVICE_POLLING
3651         if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
3652                 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
3653 #endif
3654
3655         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3656             RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
3657
3658         if (sc->bge_irq == NULL) {
3659                 device_printf(sc->bge_dev, "couldn't map interrupt\n");
3660                 error = ENXIO;
3661                 goto fail;
3662         }
3663
3664         bge_devinfo(sc);
3665
3666         sc->bge_asf_mode = 0;
3667         /* No ASF if APE present. */
3668         if ((sc->bge_flags & BGE_FLAG_APE) == 0) {
3669                 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3670                     BGE_SRAM_DATA_SIG_MAGIC)) {
3671                         if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
3672                             BGE_HWCFG_ASF) {
3673                                 sc->bge_asf_mode |= ASF_ENABLE;
3674                                 sc->bge_asf_mode |= ASF_STACKUP;
3675                                 if (BGE_IS_575X_PLUS(sc))
3676                                         sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3677                         }
3678                 }
3679         }
3680
3681         bge_stop_fw(sc);
3682         bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
3683         if (bge_reset(sc)) {
3684                 device_printf(sc->bge_dev, "chip reset failed\n");
3685                 error = ENXIO;
3686                 goto fail;
3687         }
3688
3689         bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
3690         bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
3691
3692         if (bge_chipinit(sc)) {
3693                 device_printf(sc->bge_dev, "chip initialization failed\n");
3694                 error = ENXIO;
3695                 goto fail;
3696         }
3697
3698         error = bge_get_eaddr(sc, eaddr);
3699         if (error) {
3700                 device_printf(sc->bge_dev,
3701                     "failed to read station address\n");
3702                 error = ENXIO;
3703                 goto fail;
3704         }
3705
3706         /* 5705 limits RX return ring to 512 entries. */
3707         if (BGE_IS_5717_PLUS(sc))
3708                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3709         else if (BGE_IS_5705_PLUS(sc))
3710                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3711         else
3712                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3713
3714         if (bge_dma_alloc(sc)) {
3715                 device_printf(sc->bge_dev,
3716                     "failed to allocate DMA resources\n");
3717                 error = ENXIO;
3718                 goto fail;
3719         }
3720
3721         /* Set default tuneable values. */
3722         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3723         sc->bge_rx_coal_ticks = 150;
3724         sc->bge_tx_coal_ticks = 150;
3725         sc->bge_rx_max_coal_bds = 10;
3726         sc->bge_tx_max_coal_bds = 10;
3727
3728         /* Initialize checksum features to use. */
3729         sc->bge_csum_features = BGE_CSUM_FEATURES;
3730         if (sc->bge_forced_udpcsum != 0)
3731                 sc->bge_csum_features |= CSUM_UDP;
3732
3733         /* Set up ifnet structure */
3734         ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
3735         if (ifp == NULL) {
3736                 device_printf(sc->bge_dev, "failed to if_alloc()\n");
3737                 error = ENXIO;
3738                 goto fail;
3739         }
3740         if_setsoftc(ifp, sc);
3741         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3742         if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
3743         if_setioctlfn(ifp, bge_ioctl);
3744         if_setstartfn(ifp, bge_start);
3745         if_setinitfn(ifp, bge_init);
3746         if_setgetcounterfn(ifp, bge_get_counter);
3747         if_setsendqlen(ifp, BGE_TX_RING_CNT - 1);
3748         if_setsendqready(ifp);
3749         if_sethwassist(ifp, sc->bge_csum_features);
3750         if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3751             IFCAP_VLAN_MTU);
3752         if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3753                 if_sethwassistbits(ifp, CSUM_TSO, 0);
3754                 if_setcapabilitiesbit(ifp, IFCAP_TSO4 | IFCAP_VLAN_HWTSO, 0);
3755         }
3756 #ifdef IFCAP_VLAN_HWCSUM
3757         if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0);
3758 #endif
3759         if_setcapenable(ifp, if_getcapabilities(ifp));
3760 #ifdef DEVICE_POLLING
3761         if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
3762 #endif
3763
3764         /*
3765          * 5700 B0 chips do not support checksumming correctly due
3766          * to hardware bugs.
3767          */
3768         if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
3769                 if_setcapabilitiesbit(ifp, 0, IFCAP_HWCSUM);
3770                 if_setcapenablebit(ifp, 0, IFCAP_HWCSUM);
3771                 if_sethwassist(ifp, 0);
3772         }
3773
3774         /*
3775          * Figure out what sort of media we have by checking the
3776          * hardware config word in the first 32k of NIC internal memory,
3777          * or fall back to examining the EEPROM if necessary.
3778          * Note: on some BCM5700 cards, this value appears to be unset.
3779          * If that's the case, we have to rely on identifying the NIC
3780          * by its PCI subsystem ID, as we do below for the SysKonnect
3781          * SK-9D41.
3782          */
3783         if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
3784                 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3785         else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
3786             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3787                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
3788                     sizeof(hwcfg))) {
3789                         device_printf(sc->bge_dev, "failed to read EEPROM\n");
3790                         error = ENXIO;
3791                         goto fail;
3792                 }
3793                 hwcfg = ntohl(hwcfg);
3794         }
3795
3796         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
3797         if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
3798             SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
3799                 if (BGE_IS_5705_PLUS(sc)) {
3800                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
3801                         sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3802                 } else
3803                         sc->bge_flags |= BGE_FLAG_TBI;
3804         }
3805
3806         /* Set various PHY bug flags. */
3807         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
3808             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
3809                 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
3810         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
3811             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
3812                 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
3813         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
3814                 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
3815         if (pci_get_subvendor(dev) == DELL_VENDORID)
3816                 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
3817         if ((BGE_IS_5705_PLUS(sc)) &&
3818             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
3819             sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
3820             sc->bge_asicrev != BGE_ASICREV_BCM57780 &&
3821             !BGE_IS_5717_PLUS(sc)) {
3822                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
3823                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3824                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3825                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
3826                         if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
3827                             pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
3828                                 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
3829                         if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
3830                                 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
3831                 } else
3832                         sc->bge_phy_flags |= BGE_PHY_BER_BUG;
3833         }
3834
3835         /*
3836          * Don't enable Ethernet@WireSpeed for the 5700 or the
3837          * 5705 A0 and A1 chips.
3838          */
3839         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3840             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3841             (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
3842             sc->bge_chipid != BGE_CHIPID_BCM5705_A1)))
3843                 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3844
3845         if (sc->bge_flags & BGE_FLAG_TBI) {
3846                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3847                     bge_ifmedia_sts);
3848                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
3849                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
3850                     0, NULL);
3851                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3852                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3853                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3854         } else {
3855                 /*
3856                  * Do transceiver setup and tell the firmware the
3857                  * driver is down so we can try to get access the
3858                  * probe if ASF is running.  Retry a couple of times
3859                  * if we get a conflict with the ASF firmware accessing
3860                  * the PHY.
3861                  */
3862                 trys = 0;
3863                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3864 again:
3865                 bge_asf_driver_up(sc);
3866
3867                 error = mii_attach(dev, &sc->bge_miibus, ifp,
3868                     (ifm_change_cb_t)bge_ifmedia_upd,
3869                     (ifm_stat_cb_t)bge_ifmedia_sts, capmask, sc->bge_phy_addr,
3870                     MII_OFFSET_ANY, MIIF_DOPAUSE);
3871                 if (error != 0) {
3872                         if (trys++ < 4) {
3873                                 device_printf(sc->bge_dev, "Try again\n");
3874                                 bge_miibus_writereg(sc->bge_dev,
3875                                     sc->bge_phy_addr, MII_BMCR, BMCR_RESET);
3876                                 goto again;
3877                         }
3878                         device_printf(sc->bge_dev, "attaching PHYs failed\n");
3879                         goto fail;
3880                 }
3881
3882                 /*
3883                  * Now tell the firmware we are going up after probing the PHY
3884                  */
3885                 if (sc->bge_asf_mode & ASF_STACKUP)
3886                         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3887         }
3888
3889         /*
3890          * When using the BCM5701 in PCI-X mode, data corruption has
3891          * been observed in the first few bytes of some received packets.
3892          * Aligning the packet buffer in memory eliminates the corruption.
3893          * Unfortunately, this misaligns the packet payloads.  On platforms
3894          * which do not support unaligned accesses, we will realign the
3895          * payloads by copying the received packets.
3896          */
3897         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
3898             sc->bge_flags & BGE_FLAG_PCIX)
3899                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
3900
3901         /*
3902          * Call MI attach routine.
3903          */
3904         ether_ifattach(ifp, eaddr);
3905
3906         /* Tell upper layer we support long frames. */
3907         if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
3908
3909         /*
3910          * Hookup IRQ last.
3911          */
3912         if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
3913                 /* Take advantage of single-shot MSI. */
3914                 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
3915                     ~BGE_MSIMODE_ONE_SHOT_DISABLE);
3916                 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
3917                     taskqueue_thread_enqueue, &sc->bge_tq);
3918                 if (sc->bge_tq == NULL) {
3919                         device_printf(dev, "could not create taskqueue.\n");
3920                         ether_ifdetach(ifp);
3921                         error = ENOMEM;
3922                         goto fail;
3923                 }
3924                 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET,
3925                     "%s taskq", device_get_nameunit(sc->bge_dev));
3926                 if (error != 0) {
3927                         device_printf(dev, "could not start threads.\n");
3928                         ether_ifdetach(ifp);
3929                         goto fail;
3930                 }
3931                 error = bus_setup_intr(dev, sc->bge_irq,
3932                     INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
3933                     &sc->bge_intrhand);
3934         } else
3935                 error = bus_setup_intr(dev, sc->bge_irq,
3936                     INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
3937                     &sc->bge_intrhand);
3938
3939         if (error) {
3940                 ether_ifdetach(ifp);
3941                 device_printf(sc->bge_dev, "couldn't set up irq\n");
3942         }
3943
3944 fail:
3945         if (error)
3946                 bge_detach(dev);
3947         return (error);
3948 }
3949
3950 static int
3951 bge_detach(device_t dev)
3952 {
3953         struct bge_softc *sc;
3954         if_t ifp;
3955
3956         sc = device_get_softc(dev);
3957         ifp = sc->bge_ifp;
3958
3959 #ifdef DEVICE_POLLING
3960         if (if_getcapenable(ifp) & IFCAP_POLLING)
3961                 ether_poll_deregister(ifp);
3962 #endif
3963
3964         if (device_is_attached(dev)) {
3965                 ether_ifdetach(ifp);
3966                 BGE_LOCK(sc);
3967                 bge_stop(sc);
3968                 BGE_UNLOCK(sc);
3969                 callout_drain(&sc->bge_stat_ch);
3970         }
3971
3972         if (sc->bge_tq)
3973                 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3974
3975         if (sc->bge_flags & BGE_FLAG_TBI)
3976                 ifmedia_removeall(&sc->bge_ifmedia);
3977         else if (sc->bge_miibus != NULL) {
3978                 bus_generic_detach(dev);
3979                 device_delete_child(dev, sc->bge_miibus);
3980         }
3981
3982         bge_release_resources(sc);
3983
3984         return (0);
3985 }
3986
3987 static void
3988 bge_release_resources(struct bge_softc *sc)
3989 {
3990         device_t dev;
3991
3992         dev = sc->bge_dev;
3993
3994         if (sc->bge_tq != NULL)
3995                 taskqueue_free(sc->bge_tq);
3996
3997         if (sc->bge_intrhand != NULL)
3998                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3999
4000         if (sc->bge_irq != NULL) {
4001                 bus_release_resource(dev, SYS_RES_IRQ,
4002                     rman_get_rid(sc->bge_irq), sc->bge_irq);
4003                 pci_release_msi(dev);
4004         }
4005
4006         if (sc->bge_res != NULL)
4007                 bus_release_resource(dev, SYS_RES_MEMORY,
4008                     rman_get_rid(sc->bge_res), sc->bge_res);
4009
4010         if (sc->bge_res2 != NULL)
4011                 bus_release_resource(dev, SYS_RES_MEMORY,
4012                     rman_get_rid(sc->bge_res2), sc->bge_res2);
4013
4014         if (sc->bge_ifp != NULL)
4015                 if_free(sc->bge_ifp);
4016
4017         bge_dma_free(sc);
4018
4019         if (mtx_initialized(&sc->bge_mtx))      /* XXX */
4020                 BGE_LOCK_DESTROY(sc);
4021 }
4022
4023 static int
4024 bge_reset(struct bge_softc *sc)
4025 {
4026         device_t dev;
4027         uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val;
4028         void (*write_op)(struct bge_softc *, int, int);
4029         uint16_t devctl;
4030         int i;
4031
4032         dev = sc->bge_dev;
4033
4034         mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
4035         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4036                 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
4037         mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
4038
4039         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
4040             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
4041                 if (sc->bge_flags & BGE_FLAG_PCIE)
4042                         write_op = bge_writemem_direct;
4043                 else
4044                         write_op = bge_writemem_ind;
4045         } else
4046                 write_op = bge_writereg_ind;
4047
4048         if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
4049             sc->bge_asicrev != BGE_ASICREV_BCM5701) {
4050                 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
4051                 for (i = 0; i < 8000; i++) {
4052                         if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
4053                             BGE_NVRAMSWARB_GNT1)
4054                                 break;
4055                         DELAY(20);
4056                 }
4057                 if (i == 8000) {
4058                         if (bootverbose)
4059                                 device_printf(dev, "NVRAM lock timedout!\n");
4060                 }
4061         }
4062         /* Take APE lock when performing reset. */
4063         bge_ape_lock(sc, BGE_APE_LOCK_GRC);
4064
4065         /* Save some important PCI state. */
4066         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
4067         command = pci_read_config(dev, BGE_PCI_CMD, 4);
4068
4069         pci_write_config(dev, BGE_PCI_MISC_CTL,
4070             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4071             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4072
4073         /* Disable fastboot on controllers that support it. */
4074         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
4075             BGE_IS_5755_PLUS(sc)) {
4076                 if (bootverbose)
4077                         device_printf(dev, "Disabling fastboot\n");
4078                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
4079         }
4080
4081         /*
4082          * Write the magic number to SRAM at offset 0xB50.
4083          * When firmware finishes its initialization it will
4084          * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
4085          */
4086         bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
4087
4088         reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
4089
4090         /* XXX: Broadcom Linux driver. */
4091         if (sc->bge_flags & BGE_FLAG_PCIE) {
4092                 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
4093                     (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) {
4094                         if (CSR_READ_4(sc, 0x7E2C) == 0x60)     /* PCIE 1.0 */
4095                                 CSR_WRITE_4(sc, 0x7E2C, 0x20);
4096                 }
4097                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
4098                         /* Prevent PCIE link training during global reset */
4099                         CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
4100                         reset |= 1 << 29;
4101                 }
4102         }
4103
4104         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4105                 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4106                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
4107                     val | BGE_VCPU_STATUS_DRV_RESET);
4108                 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
4109                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
4110                     val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
4111         }
4112
4113         /*
4114          * Set GPHY Power Down Override to leave GPHY
4115          * powered up in D0 uninitialized.
4116          */
4117         if (BGE_IS_5705_PLUS(sc) &&
4118             (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0)
4119                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
4120
4121         /* Issue global reset */
4122         write_op(sc, BGE_MISC_CFG, reset);
4123
4124         if (sc->bge_flags & BGE_FLAG_PCIE)
4125                 DELAY(100 * 1000);
4126         else
4127                 DELAY(1000);
4128
4129         /* XXX: Broadcom Linux driver. */
4130         if (sc->bge_flags & BGE_FLAG_PCIE) {
4131                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
4132                         DELAY(500000); /* wait for link training to complete */
4133                         val = pci_read_config(dev, 0xC4, 4);
4134                         pci_write_config(dev, 0xC4, val | (1 << 15), 4);
4135                 }
4136                 devctl = pci_read_config(dev,
4137                     sc->bge_expcap + PCIER_DEVICE_CTL, 2);
4138                 /* Clear enable no snoop and disable relaxed ordering. */
4139                 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE |
4140                     PCIEM_CTL_NOSNOOP_ENABLE);
4141                 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL,
4142                     devctl, 2);
4143                 pci_set_max_read_req(dev, sc->bge_expmrq);
4144                 /* Clear error status. */
4145                 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA,
4146                     PCIEM_STA_CORRECTABLE_ERROR |
4147                     PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
4148                     PCIEM_STA_UNSUPPORTED_REQ, 2);
4149         }
4150
4151         /* Reset some of the PCI state that got zapped by reset. */
4152         pci_write_config(dev, BGE_PCI_MISC_CTL,
4153             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4154             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4155         val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
4156         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
4157             (sc->bge_flags & BGE_FLAG_PCIX) != 0)
4158                 val |= BGE_PCISTATE_RETRY_SAME_DMA;
4159         if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4160                 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
4161                     BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
4162                     BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
4163         pci_write_config(dev, BGE_PCI_PCISTATE, val, 4);
4164         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
4165         pci_write_config(dev, BGE_PCI_CMD, command, 4);
4166         /*
4167          * Disable PCI-X relaxed ordering to ensure status block update
4168          * comes first then packet buffer DMA. Otherwise driver may
4169          * read stale status block.
4170          */
4171         if (sc->bge_flags & BGE_FLAG_PCIX) {
4172                 devctl = pci_read_config(dev,
4173                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
4174                 devctl &= ~PCIXM_COMMAND_ERO;
4175                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
4176                         devctl &= ~PCIXM_COMMAND_MAX_READ;
4177                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
4178                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4179                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
4180                             PCIXM_COMMAND_MAX_READ);
4181                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
4182                 }
4183                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
4184                     devctl, 2);
4185         }
4186         /* Re-enable MSI, if necessary, and enable the memory arbiter. */
4187         if (BGE_IS_5714_FAMILY(sc)) {
4188                 /* This chip disables MSI on reset. */
4189                 if (sc->bge_flags & BGE_FLAG_MSI) {
4190                         val = pci_read_config(dev,
4191                             sc->bge_msicap + PCIR_MSI_CTRL, 2);
4192                         pci_write_config(dev,
4193                             sc->bge_msicap + PCIR_MSI_CTRL,
4194                             val | PCIM_MSICTRL_MSI_ENABLE, 2);
4195                         val = CSR_READ_4(sc, BGE_MSI_MODE);
4196                         CSR_WRITE_4(sc, BGE_MSI_MODE,
4197                             val | BGE_MSIMODE_ENABLE);
4198                 }
4199                 val = CSR_READ_4(sc, BGE_MARB_MODE);
4200                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
4201         } else
4202                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4203
4204         /* Fix up byte swapping. */
4205         CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
4206
4207         val = CSR_READ_4(sc, BGE_MAC_MODE);
4208         val = (val & ~mac_mode_mask) | mac_mode;
4209         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
4210         DELAY(40);
4211
4212         bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
4213
4214         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4215                 for (i = 0; i < BGE_TIMEOUT; i++) {
4216                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4217                         if (val & BGE_VCPU_STATUS_INIT_DONE)
4218                                 break;
4219                         DELAY(100);
4220                 }
4221                 if (i == BGE_TIMEOUT) {
4222                         device_printf(dev, "reset timed out\n");
4223                         return (1);
4224                 }
4225         } else {
4226                 /*
4227                  * Poll until we see the 1's complement of the magic number.
4228                  * This indicates that the firmware initialization is complete.
4229                  * We expect this to fail if no chip containing the Ethernet
4230                  * address is fitted though.
4231                  */
4232                 for (i = 0; i < BGE_TIMEOUT; i++) {
4233                         DELAY(10);
4234                         val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
4235                         if (val == ~BGE_SRAM_FW_MB_MAGIC)
4236                                 break;
4237                 }
4238
4239                 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
4240                         device_printf(dev,
4241                             "firmware handshake timed out, found 0x%08x\n",
4242                             val);
4243                 /* BCM57765 A0 needs additional time before accessing. */
4244                 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
4245                         DELAY(10 * 1000);       /* XXX */
4246         }
4247
4248         /*
4249          * The 5704 in TBI mode apparently needs some special
4250          * adjustment to insure the SERDES drive level is set
4251          * to 1.2V.
4252          */
4253         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
4254             sc->bge_flags & BGE_FLAG_TBI) {
4255                 val = CSR_READ_4(sc, BGE_SERDES_CFG);
4256                 val = (val & ~0xFFF) | 0x880;
4257                 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
4258         }
4259
4260         /* XXX: Broadcom Linux driver. */
4261         if (sc->bge_flags & BGE_FLAG_PCIE &&
4262             !BGE_IS_5717_PLUS(sc) &&
4263             sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
4264             sc->bge_asicrev != BGE_ASICREV_BCM5785) {
4265                 /* Enable Data FIFO protection. */
4266                 val = CSR_READ_4(sc, 0x7C00);
4267                 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
4268         }
4269
4270         if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
4271                 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
4272                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
4273
4274         return (0);
4275 }
4276
4277 static __inline void
4278 bge_rxreuse_std(struct bge_softc *sc, int i)
4279 {
4280         struct bge_rx_bd *r;
4281
4282         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
4283         r->bge_flags = BGE_RXBDFLAG_END;
4284         r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
4285         r->bge_idx = i;
4286         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4287 }
4288
4289 static __inline void
4290 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
4291 {
4292         struct bge_extrx_bd *r;
4293
4294         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
4295         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
4296         r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
4297         r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
4298         r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
4299         r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
4300         r->bge_idx = i;
4301         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4302 }
4303
4304 /*
4305  * Frame reception handling. This is called if there's a frame
4306  * on the receive return list.
4307  *
4308  * Note: we have to be able to handle two possibilities here:
4309  * 1) the frame is from the jumbo receive ring
4310  * 2) the frame is from the standard receive ring
4311  */
4312
4313 static int
4314 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
4315 {
4316         if_t ifp;
4317         int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
4318         uint16_t rx_cons;
4319
4320         rx_cons = sc->bge_rx_saved_considx;
4321
4322         /* Nothing to do. */
4323         if (rx_cons == rx_prod)
4324                 return (rx_npkts);
4325
4326         ifp = sc->bge_ifp;
4327
4328         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4329             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
4330         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4331             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
4332         if (BGE_IS_JUMBO_CAPABLE(sc) &&
4333             if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
4334             ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))
4335                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4336                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
4337
4338         while (rx_cons != rx_prod) {
4339                 struct bge_rx_bd        *cur_rx;
4340                 uint32_t                rxidx;
4341                 struct mbuf             *m = NULL;
4342                 uint16_t                vlan_tag = 0;
4343                 int                     have_tag = 0;
4344
4345 #ifdef DEVICE_POLLING
4346                 if (if_getcapenable(ifp) & IFCAP_POLLING) {
4347                         if (sc->rxcycles <= 0)
4348                                 break;
4349                         sc->rxcycles--;
4350                 }
4351 #endif
4352
4353                 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
4354
4355                 rxidx = cur_rx->bge_idx;
4356                 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
4357
4358                 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING &&
4359                     cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
4360                         have_tag = 1;
4361                         vlan_tag = cur_rx->bge_vlan_tag;
4362                 }
4363
4364                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
4365                         jumbocnt++;
4366                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
4367                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4368                                 bge_rxreuse_jumbo(sc, rxidx);
4369                                 continue;
4370                         }
4371                         if (bge_newbuf_jumbo(sc, rxidx) != 0) {
4372                                 bge_rxreuse_jumbo(sc, rxidx);
4373                                 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
4374                                 continue;
4375                         }
4376                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4377                 } else {
4378                         stdcnt++;
4379                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
4380                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4381                                 bge_rxreuse_std(sc, rxidx);
4382                                 continue;
4383                         }
4384                         if (bge_newbuf_std(sc, rxidx) != 0) {
4385                                 bge_rxreuse_std(sc, rxidx);
4386                                 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
4387                                 continue;
4388                         }
4389                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4390                 }
4391
4392                 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
4393 #ifndef __NO_STRICT_ALIGNMENT
4394                 /*
4395                  * For architectures with strict alignment we must make sure
4396                  * the payload is aligned.
4397                  */
4398                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
4399                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
4400                             cur_rx->bge_len);
4401                         m->m_data += ETHER_ALIGN;
4402                 }
4403 #endif
4404                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
4405                 m->m_pkthdr.rcvif = ifp;
4406
4407                 if (if_getcapenable(ifp) & IFCAP_RXCSUM)
4408                         bge_rxcsum(sc, cur_rx, m);
4409
4410                 /*
4411                  * If we received a packet with a vlan tag,
4412                  * attach that information to the packet.
4413                  */
4414                 if (have_tag) {
4415                         m->m_pkthdr.ether_vtag = vlan_tag;
4416                         m->m_flags |= M_VLANTAG;
4417                 }
4418
4419                 if (holdlck != 0) {
4420                         BGE_UNLOCK(sc);
4421                         if_input(ifp, m);
4422                         BGE_LOCK(sc);
4423                 } else
4424                         if_input(ifp, m);
4425                 rx_npkts++;
4426
4427                 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4428                         return (rx_npkts);
4429         }
4430
4431         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4432             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
4433         if (stdcnt > 0)
4434                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4435                     sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
4436
4437         if (jumbocnt > 0)
4438                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4439                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
4440
4441         sc->bge_rx_saved_considx = rx_cons;
4442         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
4443         if (stdcnt)
4444                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
4445                     BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT);
4446         if (jumbocnt)
4447                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
4448                     BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT);
4449 #ifdef notyet
4450         /*
4451          * This register wraps very quickly under heavy packet drops.
4452          * If you need correct statistics, you can enable this check.
4453          */
4454         if (BGE_IS_5705_PLUS(sc))
4455                 if_incierrors(ifp, CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS));
4456 #endif
4457         return (rx_npkts);
4458 }
4459
4460 static void
4461 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
4462 {
4463
4464         if (BGE_IS_5717_PLUS(sc)) {
4465                 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
4466                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4467                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4468                                 if ((cur_rx->bge_error_flag &
4469                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
4470                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4471                         }
4472                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
4473                                 m->m_pkthdr.csum_data =
4474                                     cur_rx->bge_tcp_udp_csum;
4475                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4476                                     CSUM_PSEUDO_HDR;
4477                         }
4478                 }
4479         } else {
4480                 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4481                         m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4482                         if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
4483                                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4484                 }
4485                 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
4486                     m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
4487                         m->m_pkthdr.csum_data =
4488                             cur_rx->bge_tcp_udp_csum;
4489                         m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4490                             CSUM_PSEUDO_HDR;
4491                 }
4492         }
4493 }
4494
4495 static void
4496 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
4497 {
4498         struct bge_tx_bd *cur_tx;
4499         if_t ifp;
4500
4501         BGE_LOCK_ASSERT(sc);
4502
4503         /* Nothing to do. */
4504         if (sc->bge_tx_saved_considx == tx_cons)
4505                 return;
4506
4507         ifp = sc->bge_ifp;
4508
4509         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4510             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
4511         /*
4512          * Go through our tx ring and free mbufs for those
4513          * frames that have been sent.
4514          */
4515         while (sc->bge_tx_saved_considx != tx_cons) {
4516                 uint32_t                idx;
4517
4518                 idx = sc->bge_tx_saved_considx;
4519                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
4520                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
4521                         if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
4522                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
4523                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
4524                             sc->bge_cdata.bge_tx_dmamap[idx],
4525                             BUS_DMASYNC_POSTWRITE);
4526                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
4527                             sc->bge_cdata.bge_tx_dmamap[idx]);
4528                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
4529                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
4530                 }
4531                 sc->bge_txcnt--;
4532                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
4533         }
4534
4535         if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
4536         if (sc->bge_txcnt == 0)
4537                 sc->bge_timer = 0;
4538 }
4539
4540 #ifdef DEVICE_POLLING
4541 static int
4542 bge_poll(if_t ifp, enum poll_cmd cmd, int count)
4543 {
4544         struct bge_softc *sc = if_getsoftc(ifp);
4545         uint16_t rx_prod, tx_cons;
4546         uint32_t statusword;
4547         int rx_npkts = 0;
4548
4549         BGE_LOCK(sc);
4550         if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
4551                 BGE_UNLOCK(sc);
4552                 return (rx_npkts);
4553         }
4554
4555         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4556             sc->bge_cdata.bge_status_map,
4557             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4558         /* Fetch updates from the status block. */
4559         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4560         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4561
4562         statusword = sc->bge_ldata.bge_status_block->bge_status;
4563         /* Clear the status so the next pass only sees the changes. */
4564         sc->bge_ldata.bge_status_block->bge_status = 0;
4565
4566         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4567             sc->bge_cdata.bge_status_map,
4568             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4569
4570         /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
4571         if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
4572                 sc->bge_link_evt++;
4573
4574         if (cmd == POLL_AND_CHECK_STATUS)
4575                 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4576                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4577                     sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
4578                         bge_link_upd(sc);
4579
4580         sc->rxcycles = count;
4581         rx_npkts = bge_rxeof(sc, rx_prod, 1);
4582         if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
4583                 BGE_UNLOCK(sc);
4584                 return (rx_npkts);
4585         }
4586         bge_txeof(sc, tx_cons);
4587         if (!if_sendq_empty(ifp))
4588                 bge_start_locked(ifp);
4589
4590         BGE_UNLOCK(sc);
4591         return (rx_npkts);
4592 }
4593 #endif /* DEVICE_POLLING */
4594
4595 static int
4596 bge_msi_intr(void *arg)
4597 {
4598         struct bge_softc *sc;
4599
4600         sc = (struct bge_softc *)arg;
4601         /*
4602          * This interrupt is not shared and controller already
4603          * disabled further interrupt.
4604          */
4605         taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
4606         return (FILTER_HANDLED);
4607 }
4608
4609 static void
4610 bge_intr_task(void *arg, int pending)
4611 {
4612         struct bge_softc *sc;
4613         if_t ifp;
4614         uint32_t status, status_tag;
4615         uint16_t rx_prod, tx_cons;
4616
4617         sc = (struct bge_softc *)arg;
4618         ifp = sc->bge_ifp;
4619
4620         BGE_LOCK(sc);
4621         if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
4622                 BGE_UNLOCK(sc);
4623                 return;
4624         }
4625
4626         /* Get updated status block. */
4627         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4628             sc->bge_cdata.bge_status_map,
4629             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4630
4631         /* Save producer/consumer indices. */
4632         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4633         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4634         status = sc->bge_ldata.bge_status_block->bge_status;
4635         status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
4636         /* Dirty the status flag. */
4637         sc->bge_ldata.bge_status_block->bge_status = 0;
4638         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4639             sc->bge_cdata.bge_status_map,
4640             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4641         if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
4642                 status_tag = 0;
4643
4644         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
4645                 bge_link_upd(sc);
4646
4647         /* Let controller work. */
4648         bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
4649
4650         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
4651             sc->bge_rx_saved_considx != rx_prod) {
4652                 /* Check RX return ring producer/consumer. */
4653                 BGE_UNLOCK(sc);
4654                 bge_rxeof(sc, rx_prod, 0);
4655                 BGE_LOCK(sc);
4656         }
4657         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4658                 /* Check TX ring producer/consumer. */
4659                 bge_txeof(sc, tx_cons);
4660                 if (!if_sendq_empty(ifp))
4661                         bge_start_locked(ifp);
4662         }
4663         BGE_UNLOCK(sc);
4664 }
4665
4666 static void
4667 bge_intr(void *xsc)
4668 {
4669         struct bge_softc *sc;
4670         if_t ifp;
4671         uint32_t statusword;
4672         uint16_t rx_prod, tx_cons;
4673
4674         sc = xsc;
4675
4676         BGE_LOCK(sc);
4677
4678         ifp = sc->bge_ifp;
4679
4680 #ifdef DEVICE_POLLING
4681         if (if_getcapenable(ifp) & IFCAP_POLLING) {
4682                 BGE_UNLOCK(sc);
4683                 return;
4684         }
4685 #endif
4686
4687         /*
4688          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
4689          * disable interrupts by writing nonzero like we used to, since with
4690          * our current organization this just gives complications and
4691          * pessimizations for re-enabling interrupts.  We used to have races
4692          * instead of the necessary complications.  Disabling interrupts
4693          * would just reduce the chance of a status update while we are
4694          * running (by switching to the interrupt-mode coalescence
4695          * parameters), but this chance is already very low so it is more
4696          * efficient to get another interrupt than prevent it.
4697          *
4698          * We do the ack first to ensure another interrupt if there is a
4699          * status update after the ack.  We don't check for the status
4700          * changing later because it is more efficient to get another
4701          * interrupt than prevent it, not quite as above (not checking is
4702          * a smaller optimization than not toggling the interrupt enable,
4703          * since checking doesn't involve PCI accesses and toggling require
4704          * the status check).  So toggling would probably be a pessimization
4705          * even with MSI.  It would only be needed for using a task queue.
4706          */
4707         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4708
4709         /*
4710          * Do the mandatory PCI flush as well as get the link status.
4711          */
4712         statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
4713
4714         /* Make sure the descriptor ring indexes are coherent. */
4715         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4716             sc->bge_cdata.bge_status_map,
4717             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4718         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4719         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4720         sc->bge_ldata.bge_status_block->bge_status = 0;
4721         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4722             sc->bge_cdata.bge_status_map,
4723             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4724
4725         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4726             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4727             statusword || sc->bge_link_evt)
4728                 bge_link_upd(sc);
4729
4730         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4731                 /* Check RX return ring producer/consumer. */
4732                 bge_rxeof(sc, rx_prod, 1);
4733         }
4734
4735         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4736                 /* Check TX ring producer/consumer. */
4737                 bge_txeof(sc, tx_cons);
4738         }
4739
4740         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
4741             !if_sendq_empty(ifp))
4742                 bge_start_locked(ifp);
4743
4744         BGE_UNLOCK(sc);
4745 }
4746
4747 static void
4748 bge_asf_driver_up(struct bge_softc *sc)
4749 {
4750         if (sc->bge_asf_mode & ASF_STACKUP) {
4751                 /* Send ASF heartbeat aprox. every 2s */
4752                 if (sc->bge_asf_count)
4753                         sc->bge_asf_count --;
4754                 else {
4755                         sc->bge_asf_count = 2;
4756                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4757                             BGE_FW_CMD_DRV_ALIVE);
4758                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4759                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
4760                             BGE_FW_HB_TIMEOUT_SEC);
4761                         CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
4762                             CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4763                             BGE_RX_CPU_DRV_EVENT);
4764                 }
4765         }
4766 }
4767
4768 static void
4769 bge_tick(void *xsc)
4770 {
4771         struct bge_softc *sc = xsc;
4772         struct mii_data *mii = NULL;
4773
4774         BGE_LOCK_ASSERT(sc);
4775
4776         /* Synchronize with possible callout reset/stop. */
4777         if (callout_pending(&sc->bge_stat_ch) ||
4778             !callout_active(&sc->bge_stat_ch))
4779                 return;
4780
4781         if (BGE_IS_5705_PLUS(sc))
4782                 bge_stats_update_regs(sc);
4783         else
4784                 bge_stats_update(sc);
4785
4786         /* XXX Add APE heartbeat check here? */
4787
4788         if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4789                 mii = device_get_softc(sc->bge_miibus);
4790                 /*
4791                  * Do not touch PHY if we have link up. This could break
4792                  * IPMI/ASF mode or produce extra input errors
4793                  * (extra errors was reported for bcm5701 & bcm5704).
4794                  */
4795                 if (!sc->bge_link)
4796                         mii_tick(mii);
4797         } else {
4798                 /*
4799                  * Since in TBI mode auto-polling can't be used we should poll
4800                  * link status manually. Here we register pending link event
4801                  * and trigger interrupt.
4802                  */
4803 #ifdef DEVICE_POLLING
4804                 /* In polling mode we poll link state in bge_poll(). */
4805                 if (!(if_getcapenable(sc->bge_ifp) & IFCAP_POLLING))
4806 #endif
4807                 {
4808                 sc->bge_link_evt++;
4809                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4810                     sc->bge_flags & BGE_FLAG_5788)
4811                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4812                 else
4813                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4814                 }
4815         }
4816
4817         bge_asf_driver_up(sc);
4818         bge_watchdog(sc);
4819
4820         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4821 }
4822
4823 static void
4824 bge_stats_update_regs(struct bge_softc *sc)
4825 {
4826         if_t ifp;
4827         struct bge_mac_stats *stats;
4828         uint32_t val;
4829
4830         ifp = sc->bge_ifp;
4831         stats = &sc->bge_mac_stats;
4832
4833         stats->ifHCOutOctets +=
4834             CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4835         stats->etherStatsCollisions +=
4836             CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4837         stats->outXonSent +=
4838             CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4839         stats->outXoffSent +=
4840             CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4841         stats->dot3StatsInternalMacTransmitErrors +=
4842             CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4843         stats->dot3StatsSingleCollisionFrames +=
4844             CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4845         stats->dot3StatsMultipleCollisionFrames +=
4846             CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4847         stats->dot3StatsDeferredTransmissions +=
4848             CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4849         stats->dot3StatsExcessiveCollisions +=
4850             CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4851         stats->dot3StatsLateCollisions +=
4852             CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4853         stats->ifHCOutUcastPkts +=
4854             CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4855         stats->ifHCOutMulticastPkts +=
4856             CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4857         stats->ifHCOutBroadcastPkts +=
4858             CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4859
4860         stats->ifHCInOctets +=
4861             CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4862         stats->etherStatsFragments +=
4863             CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4864         stats->ifHCInUcastPkts +=
4865             CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4866         stats->ifHCInMulticastPkts +=
4867             CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4868         stats->ifHCInBroadcastPkts +=
4869             CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4870         stats->dot3StatsFCSErrors +=
4871             CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4872         stats->dot3StatsAlignmentErrors +=
4873             CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4874         stats->xonPauseFramesReceived +=
4875             CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4876         stats->xoffPauseFramesReceived +=
4877             CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4878         stats->macControlFramesReceived +=
4879             CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4880         stats->xoffStateEntered +=
4881             CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4882         stats->dot3StatsFramesTooLong +=
4883             CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4884         stats->etherStatsJabbers +=
4885             CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4886         stats->etherStatsUndersizePkts +=
4887             CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4888
4889         stats->FramesDroppedDueToFilters +=
4890             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4891         stats->DmaWriteQueueFull +=
4892             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4893         stats->DmaWriteHighPriQueueFull +=
4894             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4895         stats->NoMoreRxBDs +=
4896             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4897         /*
4898          * XXX
4899          * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS
4900          * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0
4901          * includes number of unwanted multicast frames.  This comes
4902          * from silicon bug and known workaround to get rough(not
4903          * exact) counter is to enable interrupt on MBUF low water
4904          * attention.  This can be accomplished by setting
4905          * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE,
4906          * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and
4907          * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL.
4908          * However that change would generate more interrupts and
4909          * there are still possibilities of losing multiple frames
4910          * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling.
4911          * Given that the workaround still would not get correct
4912          * counter I don't think it's worth to implement it.  So
4913          * ignore reading the counter on controllers that have the
4914          * silicon bug.
4915          */
4916         if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
4917             sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
4918             sc->bge_chipid != BGE_CHIPID_BCM5720_A0)
4919                 stats->InputDiscards +=
4920                     CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4921         stats->InputErrors +=
4922             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4923         stats->RecvThresholdHit +=
4924             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4925
4926         if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
4927                 /*
4928                  * If controller transmitted more than BGE_NUM_RDMA_CHANNELS
4929                  * frames, it's safe to disable workaround for DMA engine's
4930                  * miscalculation of TXMBUF space.
4931                  */
4932                 if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts +
4933                     stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) {
4934                         val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
4935                         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
4936                                 val &= ~BGE_RDMA_TX_LENGTH_WA_5719;
4937                         else
4938                                 val &= ~BGE_RDMA_TX_LENGTH_WA_5720;
4939                         CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
4940                         sc->bge_flags &= ~BGE_FLAG_RDMA_BUG;
4941                 }
4942         }
4943 }
4944
4945 static void
4946 bge_stats_clear_regs(struct bge_softc *sc)
4947 {
4948
4949         CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4950         CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4951         CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4952         CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4953         CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4954         CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4955         CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4956         CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4957         CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4958         CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4959         CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4960         CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4961         CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4962
4963         CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4964         CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4965         CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4966         CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4967         CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4968         CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4969         CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4970         CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4971         CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4972         CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4973         CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4974         CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4975         CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4976         CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4977
4978         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4979         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4980         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4981         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4982         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4983         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4984         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4985 }
4986
4987 static void
4988 bge_stats_update(struct bge_softc *sc)
4989 {
4990         if_t ifp;
4991         bus_size_t stats;
4992         uint32_t cnt;   /* current register value */
4993
4994         ifp = sc->bge_ifp;
4995
4996         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
4997
4998 #define READ_STAT(sc, stats, stat) \
4999         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
5000
5001         cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
5002         if_inc_counter(ifp, IFCOUNTER_COLLISIONS, cnt - sc->bge_tx_collisions);
5003         sc->bge_tx_collisions = cnt;
5004
5005         cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo);
5006         if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_nobds);
5007         sc->bge_rx_nobds = cnt;
5008         cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo);
5009         if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_inerrs);
5010         sc->bge_rx_inerrs = cnt;
5011         cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
5012         if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_discards);
5013         sc->bge_rx_discards = cnt;
5014
5015         cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
5016         if_inc_counter(ifp, IFCOUNTER_OERRORS, cnt - sc->bge_tx_discards);
5017         sc->bge_tx_discards = cnt;
5018
5019 #undef  READ_STAT
5020 }
5021
5022 /*
5023  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
5024  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
5025  * but when such padded frames employ the bge IP/TCP checksum offload,
5026  * the hardware checksum assist gives incorrect results (possibly
5027  * from incorporating its own padding into the UDP/TCP checksum; who knows).
5028  * If we pad such runts with zeros, the onboard checksum comes out correct.
5029  */
5030 static __inline int
5031 bge_cksum_pad(struct mbuf *m)
5032 {
5033         int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
5034         struct mbuf *last;
5035
5036         /* If there's only the packet-header and we can pad there, use it. */
5037         if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
5038             M_TRAILINGSPACE(m) >= padlen) {
5039                 last = m;
5040         } else {
5041                 /*
5042                  * Walk packet chain to find last mbuf. We will either
5043                  * pad there, or append a new mbuf and pad it.
5044                  */
5045                 for (last = m; last->m_next != NULL; last = last->m_next);
5046                 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
5047                         /* Allocate new empty mbuf, pad it. Compact later. */
5048                         struct mbuf *n;
5049
5050                         MGET(n, M_NOWAIT, MT_DATA);
5051                         if (n == NULL)
5052                                 return (ENOBUFS);
5053                         n->m_len = 0;
5054                         last->m_next = n;
5055                         last = n;
5056                 }
5057         }
5058
5059         /* Now zero the pad area, to avoid the bge cksum-assist bug. */
5060         memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
5061         last->m_len += padlen;
5062         m->m_pkthdr.len += padlen;
5063
5064         return (0);
5065 }
5066
5067 static struct mbuf *
5068 bge_check_short_dma(struct mbuf *m)
5069 {
5070         struct mbuf *n;
5071         int found;
5072
5073         /*
5074          * If device receive two back-to-back send BDs with less than
5075          * or equal to 8 total bytes then the device may hang.  The two
5076          * back-to-back send BDs must in the same frame for this failure
5077          * to occur.  Scan mbuf chains and see whether two back-to-back
5078          * send BDs are there. If this is the case, allocate new mbuf
5079          * and copy the frame to workaround the silicon bug.
5080          */
5081         for (n = m, found = 0; n != NULL; n = n->m_next) {
5082                 if (n->m_len < 8) {
5083                         found++;
5084                         if (found > 1)
5085                                 break;
5086                         continue;
5087                 }
5088                 found = 0;
5089         }
5090
5091         if (found > 1) {
5092                 n = m_defrag(m, M_NOWAIT);
5093                 if (n == NULL)
5094                         m_freem(m);
5095         } else
5096                 n = m;
5097         return (n);
5098 }
5099
5100 static struct mbuf *
5101 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
5102     uint16_t *flags)
5103 {
5104         struct ip *ip;
5105         struct tcphdr *tcp;
5106         struct mbuf *n;
5107         uint16_t hlen;
5108         uint32_t poff;
5109
5110         if (M_WRITABLE(m) == 0) {
5111                 /* Get a writable copy. */
5112                 n = m_dup(m, M_NOWAIT);
5113                 m_freem(m);
5114                 if (n == NULL)
5115                         return (NULL);
5116                 m = n;
5117         }
5118         m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
5119         if (m == NULL)
5120                 return (NULL);
5121         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5122         poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
5123         m = m_pullup(m, poff + sizeof(struct tcphdr));
5124         if (m == NULL)
5125                 return (NULL);
5126         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5127         m = m_pullup(m, poff + (tcp->th_off << 2));
5128         if (m == NULL)
5129                 return (NULL);
5130         /*
5131          * It seems controller doesn't modify IP length and TCP pseudo
5132          * checksum. These checksum computed by upper stack should be 0.
5133          */
5134         *mss = m->m_pkthdr.tso_segsz;
5135         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5136         ip->ip_sum = 0;
5137         ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
5138         /* Clear pseudo checksum computed by TCP stack. */
5139         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5140         tcp->th_sum = 0;
5141         /*
5142          * Broadcom controllers uses different descriptor format for
5143          * TSO depending on ASIC revision. Due to TSO-capable firmware
5144          * license issue and lower performance of firmware based TSO
5145          * we only support hardware based TSO.
5146          */
5147         /* Calculate header length, incl. TCP/IP options, in 32 bit units. */
5148         hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
5149         if (sc->bge_flags & BGE_FLAG_TSO3) {
5150                 /*
5151                  * For BCM5717 and newer controllers, hardware based TSO
5152                  * uses the 14 lower bits of the bge_mss field to store the
5153                  * MSS and the upper 2 bits to store the lowest 2 bits of
5154                  * the IP/TCP header length.  The upper 6 bits of the header
5155                  * length are stored in the bge_flags[14:10,4] field.  Jumbo
5156                  * frames are supported.
5157                  */
5158                 *mss |= ((hlen & 0x3) << 14);
5159                 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2);
5160         } else {
5161                 /*
5162                  * For BCM5755 and newer controllers, hardware based TSO uses
5163                  * the lower 11 bits to store the MSS and the upper 5 bits to
5164                  * store the IP/TCP header length. Jumbo frames are not
5165                  * supported.
5166                  */
5167                 *mss |= (hlen << 11);
5168         }
5169         return (m);
5170 }
5171
5172 /*
5173  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
5174  * pointers to descriptors.
5175  */
5176 static int
5177 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
5178 {
5179         bus_dma_segment_t       segs[BGE_NSEG_NEW];
5180         bus_dmamap_t            map;
5181         struct bge_tx_bd        *d;
5182         struct mbuf             *m = *m_head;
5183         uint32_t                idx = *txidx;
5184         uint16_t                csum_flags, mss, vlan_tag;
5185         int                     nsegs, i, error;
5186
5187         csum_flags = 0;
5188         mss = 0;
5189         vlan_tag = 0;
5190         if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
5191             m->m_next != NULL) {
5192                 *m_head = bge_check_short_dma(m);
5193                 if (*m_head == NULL)
5194                         return (ENOBUFS);
5195                 m = *m_head;
5196         }
5197         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5198                 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
5199                 if (*m_head == NULL)
5200                         return (ENOBUFS);
5201                 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
5202                     BGE_TXBDFLAG_CPU_POST_DMA;
5203         } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
5204                 if (m->m_pkthdr.csum_flags & CSUM_IP)
5205                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
5206                 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
5207                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
5208                         if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
5209                             (error = bge_cksum_pad(m)) != 0) {
5210                                 m_freem(m);
5211                                 *m_head = NULL;
5212                                 return (error);
5213                         }
5214                 }
5215         }
5216
5217         if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
5218                 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
5219                     m->m_pkthdr.len > ETHER_MAX_LEN)
5220                         csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME;
5221                 if (sc->bge_forced_collapse > 0 &&
5222                     (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
5223                         /*
5224                          * Forcedly collapse mbuf chains to overcome hardware
5225                          * limitation which only support a single outstanding
5226                          * DMA read operation.
5227                          */
5228                         if (sc->bge_forced_collapse == 1)
5229                                 m = m_defrag(m, M_NOWAIT);
5230                         else
5231                                 m = m_collapse(m, M_NOWAIT,
5232                                     sc->bge_forced_collapse);
5233                         if (m == NULL)
5234                                 m = *m_head;
5235                         *m_head = m;
5236                 }
5237         }
5238
5239         map = sc->bge_cdata.bge_tx_dmamap[idx];
5240         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
5241             &nsegs, BUS_DMA_NOWAIT);
5242         if (error == EFBIG) {
5243                 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW);
5244                 if (m == NULL) {
5245                         m_freem(*m_head);
5246                         *m_head = NULL;
5247                         return (ENOBUFS);
5248                 }
5249                 *m_head = m;
5250                 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
5251                     m, segs, &nsegs, BUS_DMA_NOWAIT);
5252                 if (error) {
5253                         m_freem(m);
5254                         *m_head = NULL;
5255                         return (error);
5256                 }
5257         } else if (error != 0)
5258                 return (error);
5259
5260         /* Check if we have enough free send BDs. */
5261         if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
5262                 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5263                 return (ENOBUFS);
5264         }
5265
5266         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
5267
5268         if (m->m_flags & M_VLANTAG) {
5269                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
5270                 vlan_tag = m->m_pkthdr.ether_vtag;
5271         }
5272
5273         if (sc->bge_asicrev == BGE_ASICREV_BCM5762 &&
5274             (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5275                 /*
5276                  * 5725 family of devices corrupts TSO packets when TSO DMA
5277                  * buffers cross into regions which are within MSS bytes of
5278                  * a 4GB boundary.  If we encounter the condition, drop the
5279                  * packet.
5280                  */
5281                 for (i = 0; ; i++) {
5282                         d = &sc->bge_ldata.bge_tx_ring[idx];
5283                         d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5284                         d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5285                         d->bge_len = segs[i].ds_len;
5286                         if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss <
5287                             d->bge_addr.bge_addr_lo)
5288                                 break;
5289                         d->bge_flags = csum_flags;
5290                         d->bge_vlan_tag = vlan_tag;
5291                         d->bge_mss = mss;
5292                         if (i == nsegs - 1)
5293                                 break;
5294                         BGE_INC(idx, BGE_TX_RING_CNT);
5295                 }
5296                 if (i != nsegs - 1) {
5297                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map,
5298                             BUS_DMASYNC_POSTWRITE);
5299                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5300                         m_freem(*m_head);
5301                         *m_head = NULL;
5302                         return (EIO);
5303                 }
5304         } else {
5305                 for (i = 0; ; i++) {
5306                         d = &sc->bge_ldata.bge_tx_ring[idx];
5307                         d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5308                         d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5309                         d->bge_len = segs[i].ds_len;
5310                         d->bge_flags = csum_flags;
5311                         d->bge_vlan_tag = vlan_tag;
5312                         d->bge_mss = mss;
5313                         if (i == nsegs - 1)
5314                                 break;
5315                         BGE_INC(idx, BGE_TX_RING_CNT);
5316                 }
5317         }
5318
5319         /* Mark the last segment as end of packet... */
5320         d->bge_flags |= BGE_TXBDFLAG_END;
5321
5322         /*
5323          * Insure that the map for this transmission
5324          * is placed at the array index of the last descriptor
5325          * in this chain.
5326          */
5327         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
5328         sc->bge_cdata.bge_tx_dmamap[idx] = map;
5329         sc->bge_cdata.bge_tx_chain[idx] = m;
5330         sc->bge_txcnt += nsegs;
5331
5332         BGE_INC(idx, BGE_TX_RING_CNT);
5333         *txidx = idx;
5334
5335         return (0);
5336 }
5337
5338 /*
5339  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5340  * to the mbuf data regions directly in the transmit descriptors.
5341  */
5342 static void
5343 bge_start_locked(if_t ifp)
5344 {
5345         struct bge_softc *sc;
5346         struct mbuf *m_head;
5347         uint32_t prodidx;
5348         int count;
5349
5350         sc = if_getsoftc(ifp);
5351         BGE_LOCK_ASSERT(sc);
5352
5353         if (!sc->bge_link ||
5354             (if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
5355             IFF_DRV_RUNNING)
5356                 return;
5357
5358         prodidx = sc->bge_tx_prodidx;
5359
5360         for (count = 0; !if_sendq_empty(ifp);) {
5361                 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
5362                         if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5363                         break;
5364                 }
5365                 m_head = if_dequeue(ifp);
5366                 if (m_head == NULL)
5367                         break;
5368
5369                 /*
5370                  * Pack the data into the transmit ring. If we
5371                  * don't have room, set the OACTIVE flag and wait
5372                  * for the NIC to drain the ring.
5373                  */
5374                 if (bge_encap(sc, &m_head, &prodidx)) {
5375                         if (m_head == NULL)
5376                                 break;
5377                         if_sendq_prepend(ifp, m_head);
5378                         if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5379                         break;
5380                 }
5381                 ++count;
5382
5383                 /*
5384                  * If there's a BPF listener, bounce a copy of this frame
5385                  * to him.
5386                  */
5387                 if_bpfmtap(ifp, m_head);
5388         }
5389
5390         if (count > 0) {
5391                 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
5392                     sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
5393                 /* Transmit. */
5394                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5395                 /* 5700 b2 errata */
5396                 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
5397                         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5398
5399                 sc->bge_tx_prodidx = prodidx;
5400
5401                 /*
5402                  * Set a timeout in case the chip goes out to lunch.
5403                  */
5404                 sc->bge_timer = BGE_TX_TIMEOUT;
5405         }
5406 }
5407
5408 /*
5409  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5410  * to the mbuf data regions directly in the transmit descriptors.
5411  */
5412 static void
5413 bge_start(if_t ifp)
5414 {
5415         struct bge_softc *sc;
5416
5417         sc = if_getsoftc(ifp);
5418         BGE_LOCK(sc);
5419         bge_start_locked(ifp);
5420         BGE_UNLOCK(sc);
5421 }
5422
5423 static void
5424 bge_init_locked(struct bge_softc *sc)
5425 {
5426         if_t ifp;
5427         uint16_t *m;
5428         uint32_t mode;
5429
5430         BGE_LOCK_ASSERT(sc);
5431
5432         ifp = sc->bge_ifp;
5433
5434         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
5435                 return;
5436
5437         /* Cancel pending I/O and flush buffers. */
5438         bge_stop(sc);
5439
5440         bge_stop_fw(sc);
5441         bge_sig_pre_reset(sc, BGE_RESET_START);
5442         bge_reset(sc);
5443         bge_sig_legacy(sc, BGE_RESET_START);
5444         bge_sig_post_reset(sc, BGE_RESET_START);
5445
5446         bge_chipinit(sc);
5447
5448         /*
5449          * Init the various state machines, ring
5450          * control blocks and firmware.
5451          */
5452         if (bge_blockinit(sc)) {
5453                 device_printf(sc->bge_dev, "initialization failure\n");
5454                 return;
5455         }
5456
5457         ifp = sc->bge_ifp;
5458
5459         /* Specify MTU. */
5460         CSR_WRITE_4(sc, BGE_RX_MTU, if_getmtu(ifp) +
5461             ETHER_HDR_LEN + ETHER_CRC_LEN +
5462             (if_getcapenable(ifp) & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
5463
5464         /* Load our MAC address. */
5465         m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
5466         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
5467         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
5468
5469         /* Program promiscuous mode. */
5470         bge_setpromisc(sc);
5471
5472         /* Program multicast filter. */
5473         bge_setmulti(sc);
5474
5475         /* Program VLAN tag stripping. */
5476         bge_setvlan(sc);
5477
5478         /* Override UDP checksum offloading. */
5479         if (sc->bge_forced_udpcsum == 0)
5480                 sc->bge_csum_features &= ~CSUM_UDP;
5481         else
5482                 sc->bge_csum_features |= CSUM_UDP;
5483         if (if_getcapabilities(ifp) & IFCAP_TXCSUM &&
5484             if_getcapenable(ifp) & IFCAP_TXCSUM) {
5485                 if_sethwassistbits(ifp, 0, (BGE_CSUM_FEATURES | CSUM_UDP));
5486                 if_sethwassistbits(ifp, sc->bge_csum_features, 0);
5487         }
5488
5489         /* Init RX ring. */
5490         if (bge_init_rx_ring_std(sc) != 0) {
5491                 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
5492                 bge_stop(sc);
5493                 return;
5494         }
5495
5496         /*
5497          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
5498          * memory to insure that the chip has in fact read the first
5499          * entry of the ring.
5500          */
5501         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
5502                 uint32_t                v, i;
5503                 for (i = 0; i < 10; i++) {
5504                         DELAY(20);
5505                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
5506                         if (v == (MCLBYTES - ETHER_ALIGN))
5507                                 break;
5508                 }
5509                 if (i == 10)
5510                         device_printf (sc->bge_dev,
5511                             "5705 A0 chip failed to load RX ring\n");
5512         }
5513
5514         /* Init jumbo RX ring. */
5515         if (BGE_IS_JUMBO_CAPABLE(sc) &&
5516             if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
5517             ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) {
5518                 if (bge_init_rx_ring_jumbo(sc) != 0) {
5519                         device_printf(sc->bge_dev,
5520                             "no memory for jumbo Rx buffers.\n");
5521                         bge_stop(sc);
5522                         return;
5523                 }
5524         }
5525
5526         /* Init our RX return ring index. */
5527         sc->bge_rx_saved_considx = 0;
5528
5529         /* Init our RX/TX stat counters. */
5530         sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
5531
5532         /* Init TX ring. */
5533         bge_init_tx_ring(sc);
5534
5535         /* Enable TX MAC state machine lockup fix. */
5536         mode = CSR_READ_4(sc, BGE_TX_MODE);
5537         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
5538                 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
5539         if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
5540             sc->bge_asicrev == BGE_ASICREV_BCM5762) {
5541                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5542                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
5543                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5544         }
5545         /* Turn on transmitter. */
5546         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
5547         DELAY(100);
5548
5549         /* Turn on receiver. */
5550         mode = CSR_READ_4(sc, BGE_RX_MODE);
5551         if (BGE_IS_5755_PLUS(sc))
5552                 mode |= BGE_RXMODE_IPV6_ENABLE;
5553         if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
5554                 mode |= BGE_RXMODE_IPV4_FRAG_FIX;
5555         CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
5556         DELAY(10);
5557
5558         /*
5559          * Set the number of good frames to receive after RX MBUF
5560          * Low Watermark has been reached. After the RX MAC receives
5561          * this number of frames, it will drop subsequent incoming
5562          * frames until the MBUF High Watermark is reached.
5563          */
5564         if (BGE_IS_57765_PLUS(sc))
5565                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
5566         else
5567                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
5568
5569         /* Clear MAC statistics. */
5570         if (BGE_IS_5705_PLUS(sc))
5571                 bge_stats_clear_regs(sc);
5572
5573         /* Tell firmware we're alive. */
5574         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5575
5576 #ifdef DEVICE_POLLING
5577         /* Disable interrupts if we are polling. */
5578         if (if_getcapenable(ifp) & IFCAP_POLLING) {
5579                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5580                     BGE_PCIMISCCTL_MASK_PCI_INTR);
5581                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5582         } else
5583 #endif
5584
5585         /* Enable host interrupts. */
5586         {
5587         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
5588         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5589         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5590         }
5591
5592         if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
5593         if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
5594
5595         bge_ifmedia_upd_locked(ifp);
5596
5597         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
5598 }
5599
5600 static void
5601 bge_init(void *xsc)
5602 {
5603         struct bge_softc *sc = xsc;
5604
5605         BGE_LOCK(sc);
5606         bge_init_locked(sc);
5607         BGE_UNLOCK(sc);
5608 }
5609
5610 /*
5611  * Set media options.
5612  */
5613 static int
5614 bge_ifmedia_upd(if_t ifp)
5615 {
5616         struct bge_softc *sc = if_getsoftc(ifp);
5617         int res;
5618
5619         BGE_LOCK(sc);
5620         res = bge_ifmedia_upd_locked(ifp);
5621         BGE_UNLOCK(sc);
5622
5623         return (res);
5624 }
5625
5626 static int
5627 bge_ifmedia_upd_locked(if_t ifp)
5628 {
5629         struct bge_softc *sc = if_getsoftc(ifp);
5630         struct mii_data *mii;
5631         struct mii_softc *miisc;
5632         struct ifmedia *ifm;
5633
5634         BGE_LOCK_ASSERT(sc);
5635
5636         ifm = &sc->bge_ifmedia;
5637
5638         /* If this is a 1000baseX NIC, enable the TBI port. */
5639         if (sc->bge_flags & BGE_FLAG_TBI) {
5640                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
5641                         return (EINVAL);
5642                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
5643                 case IFM_AUTO:
5644                         /*
5645                          * The BCM5704 ASIC appears to have a special
5646                          * mechanism for programming the autoneg
5647                          * advertisement registers in TBI mode.
5648                          */
5649                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
5650                                 uint32_t sgdig;
5651                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5652                                 if (sgdig & BGE_SGDIGSTS_DONE) {
5653                                         CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5654                                         sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5655                                         sgdig |= BGE_SGDIGCFG_AUTO |
5656                                             BGE_SGDIGCFG_PAUSE_CAP |
5657                                             BGE_SGDIGCFG_ASYM_PAUSE;
5658                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG,
5659                                             sgdig | BGE_SGDIGCFG_SEND);
5660                                         DELAY(5);
5661                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
5662                                 }
5663                         }
5664                         break;
5665                 case IFM_1000_SX:
5666                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
5667                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
5668                                     BGE_MACMODE_HALF_DUPLEX);
5669                         } else {
5670                                 BGE_SETBIT(sc, BGE_MAC_MODE,
5671                                     BGE_MACMODE_HALF_DUPLEX);
5672                         }
5673                         DELAY(40);
5674                         break;
5675                 default:
5676                         return (EINVAL);
5677                 }
5678                 return (0);
5679         }
5680
5681         sc->bge_link_evt++;
5682         mii = device_get_softc(sc->bge_miibus);
5683         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
5684                 PHY_RESET(miisc);
5685         mii_mediachg(mii);
5686
5687         /*
5688          * Force an interrupt so that we will call bge_link_upd
5689          * if needed and clear any pending link state attention.
5690          * Without this we are not getting any further interrupts
5691          * for link state changes and thus will not UP the link and
5692          * not be able to send in bge_start_locked. The only
5693          * way to get things working was to receive a packet and
5694          * get an RX intr.
5695          * bge_tick should help for fiber cards and we might not
5696          * need to do this here if BGE_FLAG_TBI is set but as
5697          * we poll for fiber anyway it should not harm.
5698          */
5699         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
5700             sc->bge_flags & BGE_FLAG_5788)
5701                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
5702         else
5703                 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
5704
5705         return (0);
5706 }
5707
5708 /*
5709  * Report current media status.
5710  */
5711 static void
5712 bge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
5713 {
5714         struct bge_softc *sc = if_getsoftc(ifp);
5715         struct mii_data *mii;
5716
5717         BGE_LOCK(sc);
5718
5719         if ((if_getflags(ifp) & IFF_UP) == 0) {
5720                 BGE_UNLOCK(sc);
5721                 return;
5722         }
5723         if (sc->bge_flags & BGE_FLAG_TBI) {
5724                 ifmr->ifm_status = IFM_AVALID;
5725                 ifmr->ifm_active = IFM_ETHER;
5726                 if (CSR_READ_4(sc, BGE_MAC_STS) &
5727                     BGE_MACSTAT_TBI_PCS_SYNCHED)
5728                         ifmr->ifm_status |= IFM_ACTIVE;
5729                 else {
5730                         ifmr->ifm_active |= IFM_NONE;
5731                         BGE_UNLOCK(sc);
5732                         return;
5733                 }
5734                 ifmr->ifm_active |= IFM_1000_SX;
5735                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5736                         ifmr->ifm_active |= IFM_HDX;
5737                 else
5738                         ifmr->ifm_active |= IFM_FDX;
5739                 BGE_UNLOCK(sc);
5740                 return;
5741         }
5742
5743         mii = device_get_softc(sc->bge_miibus);
5744         mii_pollstat(mii);
5745         ifmr->ifm_active = mii->mii_media_active;
5746         ifmr->ifm_status = mii->mii_media_status;
5747
5748         BGE_UNLOCK(sc);
5749 }
5750
5751 static int
5752 bge_ioctl(if_t ifp, u_long command, caddr_t data)
5753 {
5754         struct bge_softc *sc = if_getsoftc(ifp);
5755         struct ifreq *ifr = (struct ifreq *) data;
5756         struct mii_data *mii;
5757         int flags, mask, error = 0;
5758
5759         switch (command) {
5760         case SIOCSIFMTU:
5761                 if (BGE_IS_JUMBO_CAPABLE(sc) ||
5762                     (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
5763                         if (ifr->ifr_mtu < ETHERMIN ||
5764                             ifr->ifr_mtu > BGE_JUMBO_MTU) {
5765                                 error = EINVAL;
5766                                 break;
5767                         }
5768                 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) {
5769                         error = EINVAL;
5770                         break;
5771                 }
5772                 BGE_LOCK(sc);
5773                 if (if_getmtu(ifp) != ifr->ifr_mtu) {
5774                         if_setmtu(ifp, ifr->ifr_mtu);
5775                         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5776                                 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5777                                 bge_init_locked(sc);
5778                         }
5779                 }
5780                 BGE_UNLOCK(sc);
5781                 break;
5782         case SIOCSIFFLAGS:
5783                 BGE_LOCK(sc);
5784                 if (if_getflags(ifp) & IFF_UP) {
5785                         /*
5786                          * If only the state of the PROMISC flag changed,
5787                          * then just use the 'set promisc mode' command
5788                          * instead of reinitializing the entire NIC. Doing
5789                          * a full re-init means reloading the firmware and
5790                          * waiting for it to start up, which may take a
5791                          * second or two.  Similarly for ALLMULTI.
5792                          */
5793                         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5794                                 flags = if_getflags(ifp) ^ sc->bge_if_flags;
5795                                 if (flags & IFF_PROMISC)
5796                                         bge_setpromisc(sc);
5797                                 if (flags & IFF_ALLMULTI)
5798                                         bge_setmulti(sc);
5799                         } else
5800                                 bge_init_locked(sc);
5801                 } else {
5802                         if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5803                                 bge_stop(sc);
5804                         }
5805                 }
5806                 sc->bge_if_flags = if_getflags(ifp);
5807                 BGE_UNLOCK(sc);
5808                 error = 0;
5809                 break;
5810         case SIOCADDMULTI:
5811         case SIOCDELMULTI:
5812                 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5813                         BGE_LOCK(sc);
5814                         bge_setmulti(sc);
5815                         BGE_UNLOCK(sc);
5816                         error = 0;
5817                 }
5818                 break;
5819         case SIOCSIFMEDIA:
5820         case SIOCGIFMEDIA:
5821                 if (sc->bge_flags & BGE_FLAG_TBI) {
5822                         error = ifmedia_ioctl(ifp, ifr,
5823                             &sc->bge_ifmedia, command);
5824                 } else {
5825                         mii = device_get_softc(sc->bge_miibus);
5826                         error = ifmedia_ioctl(ifp, ifr,
5827                             &mii->mii_media, command);
5828                 }
5829                 break;
5830         case SIOCSIFCAP:
5831                 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
5832 #ifdef DEVICE_POLLING
5833                 if (mask & IFCAP_POLLING) {
5834                         if (ifr->ifr_reqcap & IFCAP_POLLING) {
5835                                 error = ether_poll_register(bge_poll, ifp);
5836                                 if (error)
5837                                         return (error);
5838                                 BGE_LOCK(sc);
5839                                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5840                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
5841                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5842                                 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
5843                                 BGE_UNLOCK(sc);
5844                         } else {
5845                                 error = ether_poll_deregister(ifp);
5846                                 /* Enable interrupt even in error case */
5847                                 BGE_LOCK(sc);
5848                                 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
5849                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
5850                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5851                                 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
5852                                 BGE_UNLOCK(sc);
5853                         }
5854                 }
5855 #endif
5856                 if ((mask & IFCAP_TXCSUM) != 0 &&
5857                     (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
5858                         if_togglecapenable(ifp, IFCAP_TXCSUM);
5859                         if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
5860                                 if_sethwassistbits(ifp,
5861                                     sc->bge_csum_features, 0);
5862                         else
5863                                 if_sethwassistbits(ifp, 0,
5864                                     sc->bge_csum_features);
5865                 }
5866
5867                 if ((mask & IFCAP_RXCSUM) != 0 &&
5868                     (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0)
5869                         if_togglecapenable(ifp, IFCAP_RXCSUM);
5870
5871                 if ((mask & IFCAP_TSO4) != 0 &&
5872                     (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
5873                         if_togglecapenable(ifp, IFCAP_TSO4);
5874                         if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
5875                                 if_sethwassistbits(ifp, CSUM_TSO, 0);
5876                         else
5877                                 if_sethwassistbits(ifp, 0, CSUM_TSO);
5878                 }
5879
5880                 if (mask & IFCAP_VLAN_MTU) {
5881                         if_togglecapenable(ifp, IFCAP_VLAN_MTU);
5882                         if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5883                         bge_init(sc);
5884                 }
5885
5886                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
5887                     (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
5888                         if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
5889                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
5890                     (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
5891                         if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
5892                         if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
5893                                 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO);
5894                         BGE_LOCK(sc);
5895                         bge_setvlan(sc);
5896                         BGE_UNLOCK(sc);
5897                 }
5898 #ifdef VLAN_CAPABILITIES
5899                 if_vlancap(ifp);
5900 #endif
5901                 break;
5902         default:
5903                 error = ether_ioctl(ifp, command, data);
5904                 break;
5905         }
5906
5907         return (error);
5908 }
5909
5910 static void
5911 bge_watchdog(struct bge_softc *sc)
5912 {
5913         if_t ifp;
5914         uint32_t status;
5915
5916         BGE_LOCK_ASSERT(sc);
5917
5918         if (sc->bge_timer == 0 || --sc->bge_timer)
5919                 return;
5920
5921         /* If pause frames are active then don't reset the hardware. */
5922         if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) {
5923                 status = CSR_READ_4(sc, BGE_RX_STS);
5924                 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) {
5925                         /*
5926                          * If link partner has us in XOFF state then wait for
5927                          * the condition to clear.
5928                          */
5929                         CSR_WRITE_4(sc, BGE_RX_STS, status);
5930                         sc->bge_timer = BGE_TX_TIMEOUT;
5931                         return;
5932                 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 &&
5933                     (status & BGE_RXSTAT_RCVD_XON) != 0) {
5934                         /*
5935                          * If link partner has us in XOFF state then wait for
5936                          * the condition to clear.
5937                          */
5938                         CSR_WRITE_4(sc, BGE_RX_STS, status);
5939                         sc->bge_timer = BGE_TX_TIMEOUT;
5940                         return;
5941                 }
5942                 /*
5943                  * Any other condition is unexpected and the controller
5944                  * should be reset.
5945                  */
5946         }
5947
5948         ifp = sc->bge_ifp;
5949
5950         if_printf(ifp, "watchdog timeout -- resetting\n");
5951
5952         if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5953         bge_init_locked(sc);
5954
5955         if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
5956 }
5957
5958 static void
5959 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
5960 {
5961         int i;
5962
5963         BGE_CLRBIT(sc, reg, bit);
5964
5965         for (i = 0; i < BGE_TIMEOUT; i++) {
5966                 if ((CSR_READ_4(sc, reg) & bit) == 0)
5967                         return;
5968                 DELAY(100);
5969         }
5970 }
5971
5972 /*
5973  * Stop the adapter and free any mbufs allocated to the
5974  * RX and TX lists.
5975  */
5976 static void
5977 bge_stop(struct bge_softc *sc)
5978 {
5979         if_t ifp;
5980
5981         BGE_LOCK_ASSERT(sc);
5982
5983         ifp = sc->bge_ifp;
5984
5985         callout_stop(&sc->bge_stat_ch);
5986
5987         /* Disable host interrupts. */
5988         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5989         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5990
5991         /*
5992          * Tell firmware we're shutting down.
5993          */
5994         bge_stop_fw(sc);
5995         bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
5996
5997         /*
5998          * Disable all of the receiver blocks.
5999          */
6000         bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
6001         bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
6002         bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
6003         if (BGE_IS_5700_FAMILY(sc))
6004                 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
6005         bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
6006         bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
6007         bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
6008
6009         /*
6010          * Disable all of the transmit blocks.
6011          */
6012         bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
6013         bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
6014         bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
6015         bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
6016         bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
6017         if (BGE_IS_5700_FAMILY(sc))
6018                 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
6019         bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
6020
6021         /*
6022          * Shut down all of the memory managers and related
6023          * state machines.
6024          */
6025         bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
6026         bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
6027         if (BGE_IS_5700_FAMILY(sc))
6028                 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
6029
6030         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
6031         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
6032         if (!(BGE_IS_5705_PLUS(sc))) {
6033                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
6034                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
6035         }
6036         /* Update MAC statistics. */
6037         if (BGE_IS_5705_PLUS(sc))
6038                 bge_stats_update_regs(sc);
6039
6040         bge_reset(sc);
6041         bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
6042         bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
6043
6044         /*
6045          * Keep the ASF firmware running if up.
6046          */
6047         if (sc->bge_asf_mode & ASF_STACKUP)
6048                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6049         else
6050                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6051
6052         /* Free the RX lists. */
6053         bge_free_rx_ring_std(sc);
6054
6055         /* Free jumbo RX list. */
6056         if (BGE_IS_JUMBO_CAPABLE(sc))
6057                 bge_free_rx_ring_jumbo(sc);
6058
6059         /* Free TX buffers. */
6060         bge_free_tx_ring(sc);
6061
6062         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
6063
6064         /* Clear MAC's link state (PHY may still have link UP). */
6065         if (bootverbose && sc->bge_link)
6066                 if_printf(sc->bge_ifp, "link DOWN\n");
6067         sc->bge_link = 0;
6068
6069         if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
6070 }
6071
6072 /*
6073  * Stop all chip I/O so that the kernel's probe routines don't
6074  * get confused by errant DMAs when rebooting.
6075  */
6076 static int
6077 bge_shutdown(device_t dev)
6078 {
6079         struct bge_softc *sc;
6080
6081         sc = device_get_softc(dev);
6082         BGE_LOCK(sc);
6083         bge_stop(sc);
6084         BGE_UNLOCK(sc);
6085
6086         return (0);
6087 }
6088
6089 static int
6090 bge_suspend(device_t dev)
6091 {
6092         struct bge_softc *sc;
6093
6094         sc = device_get_softc(dev);
6095         BGE_LOCK(sc);
6096         bge_stop(sc);
6097         BGE_UNLOCK(sc);
6098
6099         return (0);
6100 }
6101
6102 static int
6103 bge_resume(device_t dev)
6104 {
6105         struct bge_softc *sc;
6106         if_t ifp;
6107
6108         sc = device_get_softc(dev);
6109         BGE_LOCK(sc);
6110         ifp = sc->bge_ifp;
6111         if (if_getflags(ifp) & IFF_UP) {
6112                 bge_init_locked(sc);
6113                 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
6114                         bge_start_locked(ifp);
6115         }
6116         BGE_UNLOCK(sc);
6117
6118         return (0);
6119 }
6120
6121 static void
6122 bge_link_upd(struct bge_softc *sc)
6123 {
6124         struct mii_data *mii;
6125         uint32_t link, status;
6126
6127         BGE_LOCK_ASSERT(sc);
6128
6129         /* Clear 'pending link event' flag. */
6130         sc->bge_link_evt = 0;
6131
6132         /*
6133          * Process link state changes.
6134          * Grrr. The link status word in the status block does
6135          * not work correctly on the BCM5700 rev AX and BX chips,
6136          * according to all available information. Hence, we have
6137          * to enable MII interrupts in order to properly obtain
6138          * async link changes. Unfortunately, this also means that
6139          * we have to read the MAC status register to detect link
6140          * changes, thereby adding an additional register access to
6141          * the interrupt handler.
6142          *
6143          * XXX: perhaps link state detection procedure used for
6144          * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
6145          */
6146
6147         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6148             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
6149                 status = CSR_READ_4(sc, BGE_MAC_STS);
6150                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
6151                         mii = device_get_softc(sc->bge_miibus);
6152                         mii_pollstat(mii);
6153                         if (!sc->bge_link &&
6154                             mii->mii_media_status & IFM_ACTIVE &&
6155                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6156                                 sc->bge_link++;
6157                                 if (bootverbose)
6158                                         if_printf(sc->bge_ifp, "link UP\n");
6159                         } else if (sc->bge_link &&
6160                             (!(mii->mii_media_status & IFM_ACTIVE) ||
6161                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6162                                 sc->bge_link = 0;
6163                                 if (bootverbose)
6164                                         if_printf(sc->bge_ifp, "link DOWN\n");
6165                         }
6166
6167                         /* Clear the interrupt. */
6168                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
6169                             BGE_EVTENB_MI_INTERRUPT);
6170                         bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
6171                             BRGPHY_MII_ISR);
6172                         bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
6173                             BRGPHY_MII_IMR, BRGPHY_INTRS);
6174                 }
6175                 return;
6176         }
6177
6178         if (sc->bge_flags & BGE_FLAG_TBI) {
6179                 status = CSR_READ_4(sc, BGE_MAC_STS);
6180                 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
6181                         if (!sc->bge_link) {
6182                                 sc->bge_link++;
6183                                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
6184                                         BGE_CLRBIT(sc, BGE_MAC_MODE,
6185                                             BGE_MACMODE_TBI_SEND_CFGS);
6186                                         DELAY(40);
6187                                 }
6188                                 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
6189                                 if (bootverbose)
6190                                         if_printf(sc->bge_ifp, "link UP\n");
6191                                 if_link_state_change(sc->bge_ifp,
6192                                     LINK_STATE_UP);
6193                         }
6194                 } else if (sc->bge_link) {
6195                         sc->bge_link = 0;
6196                         if (bootverbose)
6197                                 if_printf(sc->bge_ifp, "link DOWN\n");
6198                         if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
6199                 }
6200         } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
6201                 /*
6202                  * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
6203                  * in status word always set. Workaround this bug by reading
6204                  * PHY link status directly.
6205                  */
6206                 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
6207
6208                 if (link != sc->bge_link ||
6209                     sc->bge_asicrev == BGE_ASICREV_BCM5700) {
6210                         mii = device_get_softc(sc->bge_miibus);
6211                         mii_pollstat(mii);
6212                         if (!sc->bge_link &&
6213                             mii->mii_media_status & IFM_ACTIVE &&
6214                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6215                                 sc->bge_link++;
6216                                 if (bootverbose)
6217                                         if_printf(sc->bge_ifp, "link UP\n");
6218                         } else if (sc->bge_link &&
6219                             (!(mii->mii_media_status & IFM_ACTIVE) ||
6220                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6221                                 sc->bge_link = 0;
6222                                 if (bootverbose)
6223                                         if_printf(sc->bge_ifp, "link DOWN\n");
6224                         }
6225                 }
6226         } else {
6227                 /*
6228                  * For controllers that call mii_tick, we have to poll
6229                  * link status.
6230                  */
6231                 mii = device_get_softc(sc->bge_miibus);
6232                 mii_pollstat(mii);
6233                 bge_miibus_statchg(sc->bge_dev);
6234         }
6235
6236         /* Disable MAC attention when link is up. */
6237         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
6238             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
6239             BGE_MACSTAT_LINK_CHANGED);
6240 }
6241
6242 static void
6243 bge_add_sysctls(struct bge_softc *sc)
6244 {
6245         struct sysctl_ctx_list *ctx;
6246         struct sysctl_oid_list *children;
6247         int unit;
6248
6249         ctx = device_get_sysctl_ctx(sc->bge_dev);
6250         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
6251
6252 #ifdef BGE_REGISTER_DEBUG
6253         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
6254             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
6255             "Debug Information");
6256
6257         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
6258             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
6259             "MAC Register Read");
6260
6261         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read",
6262             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I",
6263             "APE Register Read");
6264
6265         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
6266             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
6267             "Memory Read");
6268
6269 #endif
6270
6271         unit = device_get_unit(sc->bge_dev);
6272         /*
6273          * A common design characteristic for many Broadcom client controllers
6274          * is that they only support a single outstanding DMA read operation
6275          * on the PCIe bus. This means that it will take twice as long to fetch
6276          * a TX frame that is split into header and payload buffers as it does
6277          * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
6278          * these controllers, coalescing buffers to reduce the number of memory
6279          * reads is effective way to get maximum performance(about 940Mbps).
6280          * Without collapsing TX buffers the maximum TCP bulk transfer
6281          * performance is about 850Mbps. However forcing coalescing mbufs
6282          * consumes a lot of CPU cycles, so leave it off by default.
6283          */
6284         sc->bge_forced_collapse = 0;
6285         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
6286             CTLFLAG_RWTUN, &sc->bge_forced_collapse, 0,
6287             "Number of fragmented TX buffers of a frame allowed before "
6288             "forced collapsing");
6289
6290         sc->bge_msi = 1;
6291         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi",
6292             CTLFLAG_RDTUN, &sc->bge_msi, 0, "Enable MSI");
6293
6294         /*
6295          * It seems all Broadcom controllers have a bug that can generate UDP
6296          * datagrams with checksum value 0 when TX UDP checksum offloading is
6297          * enabled.  Generating UDP checksum value 0 is RFC 768 violation.
6298          * Even though the probability of generating such UDP datagrams is
6299          * low, I don't want to see FreeBSD boxes to inject such datagrams
6300          * into network so disable UDP checksum offloading by default.  Users
6301          * still override this behavior by setting a sysctl variable,
6302          * dev.bge.0.forced_udpcsum.
6303          */
6304         sc->bge_forced_udpcsum = 0;
6305         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum",
6306             CTLFLAG_RWTUN, &sc->bge_forced_udpcsum, 0,
6307             "Enable UDP checksum offloading even if controller can "
6308             "generate UDP checksum value 0");
6309
6310         if (BGE_IS_5705_PLUS(sc))
6311                 bge_add_sysctl_stats_regs(sc, ctx, children);
6312         else
6313                 bge_add_sysctl_stats(sc, ctx, children);
6314 }
6315
6316 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
6317         SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
6318             sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
6319             desc)
6320
6321 static void
6322 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6323     struct sysctl_oid_list *parent)
6324 {
6325         struct sysctl_oid *tree;
6326         struct sysctl_oid_list *children, *schildren;
6327
6328         tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6329             NULL, "BGE Statistics");
6330         schildren = children = SYSCTL_CHILDREN(tree);
6331         BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
6332             children, COSFramesDroppedDueToFilters,
6333             "FramesDroppedDueToFilters");
6334         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
6335             children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
6336         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
6337             children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
6338         BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
6339             children, nicNoMoreRxBDs, "NoMoreRxBDs");
6340         BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
6341             children, ifInDiscards, "InputDiscards");
6342         BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
6343             children, ifInErrors, "InputErrors");
6344         BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
6345             children, nicRecvThresholdHit, "RecvThresholdHit");
6346         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
6347             children, nicDmaReadQueueFull, "DmaReadQueueFull");
6348         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
6349             children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
6350         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
6351             children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
6352         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
6353             children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
6354         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
6355             children, nicRingStatusUpdate, "RingStatusUpdate");
6356         BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
6357             children, nicInterrupts, "Interrupts");
6358         BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
6359             children, nicAvoidedInterrupts, "AvoidedInterrupts");
6360         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
6361             children, nicSendThresholdHit, "SendThresholdHit");
6362
6363         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
6364             NULL, "BGE RX Statistics");
6365         children = SYSCTL_CHILDREN(tree);
6366         BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
6367             children, rxstats.ifHCInOctets, "ifHCInOctets");
6368         BGE_SYSCTL_STAT(sc, ctx, "Fragments",
6369             children, rxstats.etherStatsFragments, "Fragments");
6370         BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
6371             children, rxstats.ifHCInUcastPkts, "UnicastPkts");
6372         BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
6373             children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
6374         BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
6375             children, rxstats.dot3StatsFCSErrors, "FCSErrors");
6376         BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
6377             children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
6378         BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
6379             children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
6380         BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
6381             children, rxstats.xoffPauseFramesReceived,
6382             "xoffPauseFramesReceived");
6383         BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
6384             children, rxstats.macControlFramesReceived,
6385             "ControlFramesReceived");
6386         BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
6387             children, rxstats.xoffStateEntered, "xoffStateEntered");
6388         BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
6389             children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
6390         BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
6391             children, rxstats.etherStatsJabbers, "Jabbers");
6392         BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
6393             children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
6394         BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
6395             children, rxstats.inRangeLengthError, "inRangeLengthError");
6396         BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
6397             children, rxstats.outRangeLengthError, "outRangeLengthError");
6398
6399         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
6400             NULL, "BGE TX Statistics");
6401         children = SYSCTL_CHILDREN(tree);
6402         BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
6403             children, txstats.ifHCOutOctets, "ifHCOutOctets");
6404         BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
6405             children, txstats.etherStatsCollisions, "Collisions");
6406         BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
6407             children, txstats.outXonSent, "XonSent");
6408         BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
6409             children, txstats.outXoffSent, "XoffSent");
6410         BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
6411             children, txstats.flowControlDone, "flowControlDone");
6412         BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
6413             children, txstats.dot3StatsInternalMacTransmitErrors,
6414             "InternalMacTransmitErrors");
6415         BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
6416             children, txstats.dot3StatsSingleCollisionFrames,
6417             "SingleCollisionFrames");
6418         BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
6419             children, txstats.dot3StatsMultipleCollisionFrames,
6420             "MultipleCollisionFrames");
6421         BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
6422             children, txstats.dot3StatsDeferredTransmissions,
6423             "DeferredTransmissions");
6424         BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
6425             children, txstats.dot3StatsExcessiveCollisions,
6426             "ExcessiveCollisions");
6427         BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
6428             children, txstats.dot3StatsLateCollisions,
6429             "LateCollisions");
6430         BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
6431             children, txstats.ifHCOutUcastPkts, "UnicastPkts");
6432         BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
6433             children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
6434         BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
6435             children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
6436         BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
6437             children, txstats.dot3StatsCarrierSenseErrors,
6438             "CarrierSenseErrors");
6439         BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
6440             children, txstats.ifOutDiscards, "Discards");
6441         BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
6442             children, txstats.ifOutErrors, "Errors");
6443 }
6444
6445 #undef BGE_SYSCTL_STAT
6446
6447 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d)    \
6448             SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
6449
6450 static void
6451 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6452     struct sysctl_oid_list *parent)
6453 {
6454         struct sysctl_oid *tree;
6455         struct sysctl_oid_list *child, *schild;
6456         struct bge_mac_stats *stats;
6457
6458         stats = &sc->bge_mac_stats;
6459         tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6460             NULL, "BGE Statistics");
6461         schild = child = SYSCTL_CHILDREN(tree);
6462         BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters",
6463             &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters");
6464         BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull",
6465             &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full");
6466         BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull",
6467             &stats->DmaWriteHighPriQueueFull,
6468             "NIC DMA Write High Priority Queue Full");
6469         BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs",
6470             &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors");
6471         BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards",
6472             &stats->InputDiscards, "Discarded Input Frames");
6473         BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors",
6474             &stats->InputErrors, "Input Errors");
6475         BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit",
6476             &stats->RecvThresholdHit, "NIC Recv Threshold Hit");
6477
6478         tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD,
6479             NULL, "BGE RX Statistics");
6480         child = SYSCTL_CHILDREN(tree);
6481         BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets",
6482             &stats->ifHCInOctets, "Inbound Octets");
6483         BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments",
6484             &stats->etherStatsFragments, "Fragments");
6485         BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6486             &stats->ifHCInUcastPkts, "Inbound Unicast Packets");
6487         BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6488             &stats->ifHCInMulticastPkts, "Inbound Multicast Packets");
6489         BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6490             &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets");
6491         BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors",
6492             &stats->dot3StatsFCSErrors, "FCS Errors");
6493         BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors",
6494             &stats->dot3StatsAlignmentErrors, "Alignment Errors");
6495         BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived",
6496             &stats->xonPauseFramesReceived, "XON Pause Frames Received");
6497         BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived",
6498             &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received");
6499         BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived",
6500             &stats->macControlFramesReceived, "MAC Control Frames Received");
6501         BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered",
6502             &stats->xoffStateEntered, "XOFF State Entered");
6503         BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong",
6504             &stats->dot3StatsFramesTooLong, "Frames Too Long");
6505         BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers",
6506             &stats->etherStatsJabbers, "Jabbers");
6507         BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts",
6508             &stats->etherStatsUndersizePkts, "Undersized Packets");
6509
6510         tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD,
6511             NULL, "BGE TX Statistics");
6512         child = SYSCTL_CHILDREN(tree);
6513         BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets",
6514             &stats->ifHCOutOctets, "Outbound Octets");
6515         BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions",
6516             &stats->etherStatsCollisions, "TX Collisions");
6517         BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent",
6518             &stats->outXonSent, "XON Sent");
6519         BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent",
6520             &stats->outXoffSent, "XOFF Sent");
6521         BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors",
6522             &stats->dot3StatsInternalMacTransmitErrors,
6523             "Internal MAC TX Errors");
6524         BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames",
6525             &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames");
6526         BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames",
6527             &stats->dot3StatsMultipleCollisionFrames,
6528             "Multiple Collision Frames");
6529         BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions",
6530             &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions");
6531         BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions",
6532             &stats->dot3StatsExcessiveCollisions, "Excessive Collisions");
6533         BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions",
6534             &stats->dot3StatsLateCollisions, "Late Collisions");
6535         BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6536             &stats->ifHCOutUcastPkts, "Outbound Unicast Packets");
6537         BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6538             &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets");
6539         BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6540             &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets");
6541 }
6542
6543 #undef  BGE_SYSCTL_STAT_ADD64
6544
6545 static int
6546 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
6547 {
6548         struct bge_softc *sc;
6549         uint32_t result;
6550         int offset;
6551
6552         sc = (struct bge_softc *)arg1;
6553         offset = arg2;
6554         result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
6555             offsetof(bge_hostaddr, bge_addr_lo));
6556         return (sysctl_handle_int(oidp, &result, 0, req));
6557 }
6558
6559 #ifdef BGE_REGISTER_DEBUG
6560 static int
6561 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
6562 {
6563         struct bge_softc *sc;
6564         uint16_t *sbdata;
6565         int error, result, sbsz;
6566         int i, j;
6567
6568         result = -1;
6569         error = sysctl_handle_int(oidp, &result, 0, req);
6570         if (error || (req->newptr == NULL))
6571                 return (error);
6572
6573         if (result == 1) {
6574                 sc = (struct bge_softc *)arg1;
6575
6576                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6577                     sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
6578                         sbsz = BGE_STATUS_BLK_SZ;
6579                 else
6580                         sbsz = 32;
6581                 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
6582                 printf("Status Block:\n");
6583                 BGE_LOCK(sc);
6584                 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6585                     sc->bge_cdata.bge_status_map,
6586                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6587                 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) {
6588                         printf("%06x:", i);
6589                         for (j = 0; j < 8; j++)
6590                                 printf(" %04x", sbdata[i++]);
6591                         printf("\n");
6592                 }
6593
6594                 printf("Registers:\n");
6595                 for (i = 0x800; i < 0xA00; ) {
6596                         printf("%06x:", i);
6597                         for (j = 0; j < 8; j++) {
6598                                 printf(" %08x", CSR_READ_4(sc, i));
6599                                 i += 4;
6600                         }
6601                         printf("\n");
6602                 }
6603                 BGE_UNLOCK(sc);
6604
6605                 printf("Hardware Flags:\n");
6606                 if (BGE_IS_5717_PLUS(sc))
6607                         printf(" - 5717 Plus\n");
6608                 if (BGE_IS_5755_PLUS(sc))
6609                         printf(" - 5755 Plus\n");
6610                 if (BGE_IS_575X_PLUS(sc))
6611                         printf(" - 575X Plus\n");
6612                 if (BGE_IS_5705_PLUS(sc))
6613                         printf(" - 5705 Plus\n");
6614                 if (BGE_IS_5714_FAMILY(sc))
6615                         printf(" - 5714 Family\n");
6616                 if (BGE_IS_5700_FAMILY(sc))
6617                         printf(" - 5700 Family\n");
6618                 if (sc->bge_flags & BGE_FLAG_JUMBO)
6619                         printf(" - Supports Jumbo Frames\n");
6620                 if (sc->bge_flags & BGE_FLAG_PCIX)
6621                         printf(" - PCI-X Bus\n");
6622                 if (sc->bge_flags & BGE_FLAG_PCIE)
6623                         printf(" - PCI Express Bus\n");
6624                 if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
6625                         printf(" - No 3 LEDs\n");
6626                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
6627                         printf(" - RX Alignment Bug\n");
6628         }
6629
6630         return (error);
6631 }
6632
6633 static int
6634 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6635 {
6636         struct bge_softc *sc;
6637         int error;
6638         uint16_t result;
6639         uint32_t val;
6640
6641         result = -1;
6642         error = sysctl_handle_int(oidp, &result, 0, req);
6643         if (error || (req->newptr == NULL))
6644                 return (error);
6645
6646         if (result < 0x8000) {
6647                 sc = (struct bge_softc *)arg1;
6648                 val = CSR_READ_4(sc, result);
6649                 printf("reg 0x%06X = 0x%08X\n", result, val);
6650         }
6651
6652         return (error);
6653 }
6654
6655 static int
6656 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS)
6657 {
6658         struct bge_softc *sc;
6659         int error;
6660         uint16_t result;
6661         uint32_t val;
6662
6663         result = -1;
6664         error = sysctl_handle_int(oidp, &result, 0, req);
6665         if (error || (req->newptr == NULL))
6666                 return (error);
6667
6668         if (result < 0x8000) {
6669                 sc = (struct bge_softc *)arg1;
6670                 val = APE_READ_4(sc, result);
6671                 printf("reg 0x%06X = 0x%08X\n", result, val);
6672         }
6673
6674         return (error);
6675 }
6676
6677 static int
6678 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
6679 {
6680         struct bge_softc *sc;
6681         int error;
6682         uint16_t result;
6683         uint32_t val;
6684
6685         result = -1;
6686         error = sysctl_handle_int(oidp, &result, 0, req);
6687         if (error || (req->newptr == NULL))
6688                 return (error);
6689
6690         if (result < 0x8000) {
6691                 sc = (struct bge_softc *)arg1;
6692                 val = bge_readmem_ind(sc, result);
6693                 printf("mem 0x%06X = 0x%08X\n", result, val);
6694         }
6695
6696         return (error);
6697 }
6698 #endif
6699
6700 static int
6701 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
6702 {
6703
6704         if (sc->bge_flags & BGE_FLAG_EADDR)
6705                 return (1);
6706
6707 #ifdef __sparc64__
6708         OF_getetheraddr(sc->bge_dev, ether_addr);
6709         return (0);
6710 #endif
6711         return (1);
6712 }
6713
6714 static int
6715 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
6716 {
6717         uint32_t mac_addr;
6718
6719         mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
6720         if ((mac_addr >> 16) == 0x484b) {
6721                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
6722                 ether_addr[1] = (uint8_t)mac_addr;
6723                 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
6724                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
6725                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
6726                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
6727                 ether_addr[5] = (uint8_t)mac_addr;
6728                 return (0);
6729         }
6730         return (1);
6731 }
6732
6733 static int
6734 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
6735 {
6736         int mac_offset = BGE_EE_MAC_OFFSET;
6737
6738         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6739                 mac_offset = BGE_EE_MAC_OFFSET_5906;
6740
6741         return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
6742             ETHER_ADDR_LEN));
6743 }
6744
6745 static int
6746 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
6747 {
6748
6749         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6750                 return (1);
6751
6752         return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
6753            ETHER_ADDR_LEN));
6754 }
6755
6756 static int
6757 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
6758 {
6759         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
6760                 /* NOTE: Order is critical */
6761                 bge_get_eaddr_fw,
6762                 bge_get_eaddr_mem,
6763                 bge_get_eaddr_nvram,
6764                 bge_get_eaddr_eeprom,
6765                 NULL
6766         };
6767         const bge_eaddr_fcn_t *func;
6768
6769         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
6770                 if ((*func)(sc, eaddr) == 0)
6771                         break;
6772         }
6773         return (*func == NULL ? ENXIO : 0);
6774 }
6775
6776 static uint64_t
6777 bge_get_counter(if_t ifp, ift_counter cnt)
6778 {
6779         struct bge_softc *sc;
6780         struct bge_mac_stats *stats;
6781
6782         sc = if_getsoftc(ifp);
6783         if (!BGE_IS_5705_PLUS(sc))
6784                 return (if_get_counter_default(ifp, cnt));
6785         stats = &sc->bge_mac_stats;
6786
6787         switch (cnt) {
6788         case IFCOUNTER_IERRORS:
6789                 return (stats->NoMoreRxBDs + stats->InputDiscards +
6790                     stats->InputErrors);
6791         case IFCOUNTER_COLLISIONS:
6792                 return (stats->etherStatsCollisions);
6793         default:
6794                 return (if_get_counter_default(ifp, cnt));
6795         }
6796 }