2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
42 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
45 * frames, highly configurable RX filtering, and 16 RX and TX queues
46 * (which, along with RX filter rules, can be used for QOS applications).
47 * Other features, such as TCP segmentation, may be available as part
48 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
49 * firmware images can be stored in hardware and need not be compiled
52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
55 * The BCM5701 is a single-chip solution incorporating both the BCM5700
56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
57 * does not support external SSRAM.
59 * Broadcom also produces a variation of the BCM5700 under the "Altima"
60 * brand name, which is functionally similar but lacks PCI-X support.
62 * Without external SSRAM, you can only have at most 4 TX rings,
63 * and the use of the mini RX ring is disabled. This seems to imply
64 * that these features are simply not available on the BCM5701. As a
65 * result, this driver does not implement any support for the mini RX
69 #ifdef HAVE_KERNEL_OPTION_HEADERS
70 #include "opt_device_polling.h"
73 #include <sys/param.h>
74 #include <sys/endian.h>
75 #include <sys/systm.h>
76 #include <sys/sockio.h>
78 #include <sys/malloc.h>
79 #include <sys/kernel.h>
80 #include <sys/module.h>
81 #include <sys/socket.h>
82 #include <sys/sysctl.h>
83 #include <sys/taskqueue.h>
86 #include <net/if_arp.h>
87 #include <net/ethernet.h>
88 #include <net/if_dl.h>
89 #include <net/if_media.h>
93 #include <net/if_types.h>
94 #include <net/if_vlan_var.h>
96 #include <netinet/in_systm.h>
97 #include <netinet/in.h>
98 #include <netinet/ip.h>
99 #include <netinet/tcp.h>
101 #include <machine/bus.h>
102 #include <machine/resource.h>
104 #include <sys/rman.h>
106 #include <dev/mii/mii.h>
107 #include <dev/mii/miivar.h>
109 #include <dev/mii/brgphyreg.h>
112 #include <dev/ofw/ofw_bus.h>
113 #include <dev/ofw/openfirm.h>
114 #include <machine/ofw_machdep.h>
115 #include <machine/ver.h>
118 #include <dev/pci/pcireg.h>
119 #include <dev/pci/pcivar.h>
121 #include <dev/bge/if_bgereg.h>
123 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP)
124 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
126 MODULE_DEPEND(bge, pci, 1, 1, 1);
127 MODULE_DEPEND(bge, ether, 1, 1, 1);
128 MODULE_DEPEND(bge, miibus, 1, 1, 1);
130 /* "device miibus" required. See GENERIC if you get errors here. */
131 #include "miibus_if.h"
134 * Various supported device vendors/types and their names. Note: the
135 * spec seems to indicate that the hardware still has Alteon's vendor
136 * ID burned into it, though it will always be overriden by the vendor
137 * ID in the EEPROM. Just to be safe, we cover all possibilities.
139 static const struct bge_type {
142 } const bge_devs[] = {
143 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 },
144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 },
146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 },
147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 },
148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 },
150 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 },
152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 },
153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 },
154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 },
155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT },
156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X },
157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 },
158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT },
159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X },
160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C },
161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S },
162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT },
163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 },
164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F },
165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K },
166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M },
167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT },
168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C },
169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S },
170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 },
171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S },
172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 },
173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 },
174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 },
175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 },
176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 },
177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 },
178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 },
179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 },
180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M },
181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 },
182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F },
183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M },
184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 },
185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M },
186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 },
187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F },
188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M },
189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 },
190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M },
191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 },
192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M },
193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 },
194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 },
195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E },
196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S },
197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE },
198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 },
199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 },
200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S },
201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 },
202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 },
203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 },
204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F },
205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G },
206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 },
207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 },
208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F },
209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M },
210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 },
211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 },
212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 },
213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 },
214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M },
215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 },
216 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M },
217 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 },
218 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 },
219 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 },
220 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 },
221 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 },
222 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 },
223 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 },
224 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 },
225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 },
226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 },
228 { SK_VENDORID, SK_DEVICEID_ALTIMA },
230 { TC_VENDORID, TC_DEVICEID_3C996 },
232 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 },
233 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 },
234 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 },
239 static const struct bge_vendor {
242 } const bge_vendors[] = {
243 { ALTEON_VENDORID, "Alteon" },
244 { ALTIMA_VENDORID, "Altima" },
245 { APPLE_VENDORID, "Apple" },
246 { BCOM_VENDORID, "Broadcom" },
247 { SK_VENDORID, "SysKonnect" },
248 { TC_VENDORID, "3Com" },
249 { FJTSU_VENDORID, "Fujitsu" },
254 static const struct bge_revision {
257 } const bge_revisions[] = {
258 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" },
259 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" },
260 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" },
261 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" },
262 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" },
263 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" },
264 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" },
265 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" },
266 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" },
267 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" },
268 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" },
269 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" },
270 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" },
271 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" },
272 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" },
273 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" },
274 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" },
275 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" },
276 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" },
277 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" },
278 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" },
279 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" },
280 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" },
281 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" },
282 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" },
283 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" },
284 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" },
285 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" },
286 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" },
287 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" },
288 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" },
289 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" },
290 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" },
291 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" },
292 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
293 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
294 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
295 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
296 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
297 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
298 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
299 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
300 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
301 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" },
302 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" },
303 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" },
304 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
305 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
306 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
307 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" },
308 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" },
309 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" },
310 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" },
311 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" },
312 /* 5754 and 5787 share the same ASIC ID */
313 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
314 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
315 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
316 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" },
317 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" },
318 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" },
319 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" },
320 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" },
321 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" },
327 * Some defaults for major revisions, so that newer steppings
328 * that we don't know about have a shot at working.
330 static const struct bge_revision const bge_majorrevs[] = {
331 { BGE_ASICREV_BCM5700, "unknown BCM5700" },
332 { BGE_ASICREV_BCM5701, "unknown BCM5701" },
333 { BGE_ASICREV_BCM5703, "unknown BCM5703" },
334 { BGE_ASICREV_BCM5704, "unknown BCM5704" },
335 { BGE_ASICREV_BCM5705, "unknown BCM5705" },
336 { BGE_ASICREV_BCM5750, "unknown BCM5750" },
337 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
338 { BGE_ASICREV_BCM5752, "unknown BCM5752" },
339 { BGE_ASICREV_BCM5780, "unknown BCM5780" },
340 { BGE_ASICREV_BCM5714, "unknown BCM5714" },
341 { BGE_ASICREV_BCM5755, "unknown BCM5755" },
342 { BGE_ASICREV_BCM5761, "unknown BCM5761" },
343 { BGE_ASICREV_BCM5784, "unknown BCM5784" },
344 { BGE_ASICREV_BCM5785, "unknown BCM5785" },
345 /* 5754 and 5787 share the same ASIC ID */
346 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
347 { BGE_ASICREV_BCM5906, "unknown BCM5906" },
348 { BGE_ASICREV_BCM57765, "unknown BCM57765" },
349 { BGE_ASICREV_BCM57780, "unknown BCM57780" },
350 { BGE_ASICREV_BCM5717, "unknown BCM5717" },
351 { BGE_ASICREV_BCM5719, "unknown BCM5719" },
356 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
357 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
358 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
359 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
360 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
361 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
362 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS)
364 const struct bge_revision * bge_lookup_rev(uint32_t);
365 const struct bge_vendor * bge_lookup_vendor(uint16_t);
367 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
369 static int bge_probe(device_t);
370 static int bge_attach(device_t);
371 static int bge_detach(device_t);
372 static int bge_suspend(device_t);
373 static int bge_resume(device_t);
374 static void bge_release_resources(struct bge_softc *);
375 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
376 static int bge_dma_alloc(struct bge_softc *);
377 static void bge_dma_free(struct bge_softc *);
378 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t,
379 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
381 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
382 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
383 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
384 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
385 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
387 static void bge_txeof(struct bge_softc *, uint16_t);
388 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
389 static int bge_rxeof(struct bge_softc *, uint16_t, int);
391 static void bge_asf_driver_up (struct bge_softc *);
392 static void bge_tick(void *);
393 static void bge_stats_clear_regs(struct bge_softc *);
394 static void bge_stats_update(struct bge_softc *);
395 static void bge_stats_update_regs(struct bge_softc *);
396 static struct mbuf *bge_check_short_dma(struct mbuf *);
397 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
398 uint16_t *, uint16_t *);
399 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
401 static void bge_intr(void *);
402 static int bge_msi_intr(void *);
403 static void bge_intr_task(void *, int);
404 static void bge_start_locked(struct ifnet *);
405 static void bge_start(struct ifnet *);
406 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
407 static void bge_init_locked(struct bge_softc *);
408 static void bge_init(void *);
409 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
410 static void bge_stop(struct bge_softc *);
411 static void bge_watchdog(struct bge_softc *);
412 static int bge_shutdown(device_t);
413 static int bge_ifmedia_upd_locked(struct ifnet *);
414 static int bge_ifmedia_upd(struct ifnet *);
415 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
417 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
418 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
420 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
421 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
423 static void bge_setpromisc(struct bge_softc *);
424 static void bge_setmulti(struct bge_softc *);
425 static void bge_setvlan(struct bge_softc *);
427 static __inline void bge_rxreuse_std(struct bge_softc *, int);
428 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
429 static int bge_newbuf_std(struct bge_softc *, int);
430 static int bge_newbuf_jumbo(struct bge_softc *, int);
431 static int bge_init_rx_ring_std(struct bge_softc *);
432 static void bge_free_rx_ring_std(struct bge_softc *);
433 static int bge_init_rx_ring_jumbo(struct bge_softc *);
434 static void bge_free_rx_ring_jumbo(struct bge_softc *);
435 static void bge_free_tx_ring(struct bge_softc *);
436 static int bge_init_tx_ring(struct bge_softc *);
438 static int bge_chipinit(struct bge_softc *);
439 static int bge_blockinit(struct bge_softc *);
441 static int bge_has_eaddr(struct bge_softc *);
442 static uint32_t bge_readmem_ind(struct bge_softc *, int);
443 static void bge_writemem_ind(struct bge_softc *, int, int);
444 static void bge_writembx(struct bge_softc *, int, int);
446 static uint32_t bge_readreg_ind(struct bge_softc *, int);
448 static void bge_writemem_direct(struct bge_softc *, int, int);
449 static void bge_writereg_ind(struct bge_softc *, int, int);
451 static int bge_miibus_readreg(device_t, int, int);
452 static int bge_miibus_writereg(device_t, int, int, int);
453 static void bge_miibus_statchg(device_t);
454 #ifdef DEVICE_POLLING
455 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
458 #define BGE_RESET_START 1
459 #define BGE_RESET_STOP 2
460 static void bge_sig_post_reset(struct bge_softc *, int);
461 static void bge_sig_legacy(struct bge_softc *, int);
462 static void bge_sig_pre_reset(struct bge_softc *, int);
463 static void bge_stop_fw(struct bge_softc *);
464 static int bge_reset(struct bge_softc *);
465 static void bge_link_upd(struct bge_softc *);
468 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may
469 * leak information to untrusted users. It is also known to cause alignment
470 * traps on certain architectures.
472 #ifdef BGE_REGISTER_DEBUG
473 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
474 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
475 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
477 static void bge_add_sysctls(struct bge_softc *);
478 static void bge_add_sysctl_stats_regs(struct bge_softc *,
479 struct sysctl_ctx_list *, struct sysctl_oid_list *);
480 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *,
481 struct sysctl_oid_list *);
482 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
484 static device_method_t bge_methods[] = {
485 /* Device interface */
486 DEVMETHOD(device_probe, bge_probe),
487 DEVMETHOD(device_attach, bge_attach),
488 DEVMETHOD(device_detach, bge_detach),
489 DEVMETHOD(device_shutdown, bge_shutdown),
490 DEVMETHOD(device_suspend, bge_suspend),
491 DEVMETHOD(device_resume, bge_resume),
494 DEVMETHOD(bus_print_child, bus_generic_print_child),
495 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
498 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
499 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
500 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
505 static driver_t bge_driver = {
508 sizeof(struct bge_softc)
511 static devclass_t bge_devclass;
513 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
514 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
516 static int bge_allow_asf = 1;
518 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
520 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
521 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
522 "Allow ASF mode if available");
524 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500"
525 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2"
526 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500"
527 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3"
528 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id"
531 bge_has_eaddr(struct bge_softc *sc)
534 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
541 * The on-board BGEs found in sun4u machines aren't fitted with
542 * an EEPROM which means that we have to obtain the MAC address
543 * via OFW and that some tests will always fail. We distinguish
544 * such BGEs by the subvendor ID, which also has to be obtained
545 * from OFW instead of the PCI configuration space as the latter
546 * indicates Broadcom as the subvendor of the netboot interface.
547 * For early Blade 1500 and 2500 we even have to check the OFW
548 * device path as the subvendor ID always defaults to Broadcom
551 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
552 &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
553 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID))
555 memset(buf, 0, sizeof(buf));
556 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
557 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
558 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
560 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
561 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
569 bge_readmem_ind(struct bge_softc *sc, int off)
574 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
575 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
580 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
581 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
582 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
587 bge_writemem_ind(struct bge_softc *sc, int off, int val)
591 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
592 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
597 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
598 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
599 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
604 bge_readreg_ind(struct bge_softc *sc, int off)
610 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
611 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
616 bge_writereg_ind(struct bge_softc *sc, int off, int val)
622 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
623 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
627 bge_writemem_direct(struct bge_softc *sc, int off, int val)
629 CSR_WRITE_4(sc, off, val);
633 bge_writembx(struct bge_softc *sc, int off, int val)
635 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
636 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
638 CSR_WRITE_4(sc, off, val);
642 * Map a single buffer address.
646 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
648 struct bge_dmamap_arg *ctx;
653 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
656 ctx->bge_busaddr = segs->ds_addr;
660 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
662 uint32_t access, byte = 0;
666 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
667 for (i = 0; i < 8000; i++) {
668 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
676 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
677 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
679 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
680 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
681 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
683 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
689 if (i == BGE_TIMEOUT * 10) {
690 if_printf(sc->bge_ifp, "nvram read timed out\n");
695 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
697 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
699 /* Disable access. */
700 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
703 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
704 CSR_READ_4(sc, BGE_NVRAM_SWARB);
710 * Read a sequence of bytes from NVRAM.
713 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
718 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
721 for (i = 0; i < cnt; i++) {
722 err = bge_nvram_getbyte(sc, off + i, &byte);
728 return (err ? 1 : 0);
732 * Read a byte of data stored in the EEPROM at address 'addr.' The
733 * BCM570x supports both the traditional bitbang interface and an
734 * auto access interface for reading the EEPROM. We use the auto
738 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
744 * Enable use of auto EEPROM access so we can avoid
745 * having to use the bitbang method.
747 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
749 /* Reset the EEPROM, load the clock period. */
750 CSR_WRITE_4(sc, BGE_EE_ADDR,
751 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
754 /* Issue the read EEPROM command. */
755 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
757 /* Wait for completion */
758 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
760 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
764 if (i == BGE_TIMEOUT * 10) {
765 device_printf(sc->bge_dev, "EEPROM read timed out\n");
770 byte = CSR_READ_4(sc, BGE_EE_DATA);
772 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
778 * Read a sequence of bytes from the EEPROM.
781 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
786 for (i = 0; i < cnt; i++) {
787 error = bge_eeprom_getbyte(sc, off + i, &byte);
793 return (error ? 1 : 0);
797 bge_miibus_readreg(device_t dev, int phy, int reg)
799 struct bge_softc *sc;
803 sc = device_get_softc(dev);
805 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
806 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
807 CSR_WRITE_4(sc, BGE_MI_MODE,
808 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
812 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
813 BGE_MIPHY(phy) | BGE_MIREG(reg));
815 /* Poll for the PHY register access to complete. */
816 for (i = 0; i < BGE_TIMEOUT; i++) {
818 val = CSR_READ_4(sc, BGE_MI_COMM);
819 if ((val & BGE_MICOMM_BUSY) == 0) {
821 val = CSR_READ_4(sc, BGE_MI_COMM);
826 if (i == BGE_TIMEOUT) {
827 device_printf(sc->bge_dev,
828 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
833 /* Restore the autopoll bit if necessary. */
834 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
835 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
839 if (val & BGE_MICOMM_READFAIL)
842 return (val & 0xFFFF);
846 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
848 struct bge_softc *sc;
851 sc = device_get_softc(dev);
853 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
854 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
857 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
858 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
859 CSR_WRITE_4(sc, BGE_MI_MODE,
860 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
864 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
865 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
867 for (i = 0; i < BGE_TIMEOUT; i++) {
869 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
871 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
876 /* Restore the autopoll bit if necessary. */
877 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
878 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
882 if (i == BGE_TIMEOUT)
883 device_printf(sc->bge_dev,
884 "PHY write timed out (phy %d, reg %d, val %d)\n",
891 bge_miibus_statchg(device_t dev)
893 struct bge_softc *sc;
894 struct mii_data *mii;
895 sc = device_get_softc(dev);
896 mii = device_get_softc(sc->bge_miibus);
898 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
899 (IFM_ACTIVE | IFM_AVALID)) {
900 switch (IFM_SUBTYPE(mii->mii_media_active)) {
908 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
919 if (sc->bge_link == 0)
921 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
922 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
923 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
924 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
926 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
928 if (IFM_OPTIONS(mii->mii_media_active & IFM_FDX) != 0) {
929 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
930 if ((IFM_OPTIONS(mii->mii_media_active) &
931 IFM_ETH_TXPAUSE) != 0)
932 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
934 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
935 if ((IFM_OPTIONS(mii->mii_media_active) &
936 IFM_ETH_RXPAUSE) != 0)
937 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
939 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
941 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
942 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
943 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
948 * Intialize a standard receive ring descriptor.
951 bge_newbuf_std(struct bge_softc *sc, int i)
955 bus_dma_segment_t segs[1];
959 if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
960 (sc->bge_ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN +
961 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) {
962 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
965 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
967 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
970 m->m_len = m->m_pkthdr.len = MCLBYTES;
972 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
973 m_adj(m, ETHER_ALIGN);
975 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
976 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
981 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
982 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
983 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
984 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
985 sc->bge_cdata.bge_rx_std_dmamap[i]);
987 map = sc->bge_cdata.bge_rx_std_dmamap[i];
988 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
989 sc->bge_cdata.bge_rx_std_sparemap = map;
990 sc->bge_cdata.bge_rx_std_chain[i] = m;
991 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
992 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
993 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
994 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
995 r->bge_flags = BGE_RXBDFLAG_END;
996 r->bge_len = segs[0].ds_len;
999 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1000 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
1006 * Initialize a jumbo receive ring descriptor. This allocates
1007 * a jumbo buffer from the pool managed internally by the driver.
1010 bge_newbuf_jumbo(struct bge_softc *sc, int i)
1012 bus_dma_segment_t segs[BGE_NSEG_JUMBO];
1014 struct bge_extrx_bd *r;
1018 MGETHDR(m, M_DONTWAIT, MT_DATA);
1022 m_cljget(m, M_DONTWAIT, MJUM9BYTES);
1023 if (!(m->m_flags & M_EXT)) {
1027 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1028 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1029 m_adj(m, ETHER_ALIGN);
1031 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1032 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1038 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1039 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1040 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1041 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1042 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1044 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1045 sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1046 sc->bge_cdata.bge_rx_jumbo_sparemap;
1047 sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1048 sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1049 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1050 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1051 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1052 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1055 * Fill in the extended RX buffer descriptor.
1057 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1058 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1060 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1063 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1064 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1065 r->bge_len3 = segs[3].ds_len;
1066 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1068 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1069 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1070 r->bge_len2 = segs[2].ds_len;
1071 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1073 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1074 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1075 r->bge_len1 = segs[1].ds_len;
1076 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1078 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1079 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1080 r->bge_len0 = segs[0].ds_len;
1081 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1084 panic("%s: %d segments\n", __func__, nsegs);
1087 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1088 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1094 bge_init_rx_ring_std(struct bge_softc *sc)
1098 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1100 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1101 if ((error = bge_newbuf_std(sc, i)) != 0)
1103 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1106 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1107 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1110 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1116 bge_free_rx_ring_std(struct bge_softc *sc)
1120 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1121 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1122 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1123 sc->bge_cdata.bge_rx_std_dmamap[i],
1124 BUS_DMASYNC_POSTREAD);
1125 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1126 sc->bge_cdata.bge_rx_std_dmamap[i]);
1127 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1128 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1130 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1131 sizeof(struct bge_rx_bd));
1136 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1138 struct bge_rcb *rcb;
1141 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1143 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1144 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1146 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1149 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1150 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1154 /* Enable the jumbo receive producer ring. */
1155 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1156 rcb->bge_maxlen_flags =
1157 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD);
1158 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1160 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1166 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1170 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1171 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1172 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1173 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1174 BUS_DMASYNC_POSTREAD);
1175 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1176 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1177 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1178 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1180 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1181 sizeof(struct bge_extrx_bd));
1186 bge_free_tx_ring(struct bge_softc *sc)
1190 if (sc->bge_ldata.bge_tx_ring == NULL)
1193 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1194 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1195 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1196 sc->bge_cdata.bge_tx_dmamap[i],
1197 BUS_DMASYNC_POSTWRITE);
1198 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1199 sc->bge_cdata.bge_tx_dmamap[i]);
1200 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1201 sc->bge_cdata.bge_tx_chain[i] = NULL;
1203 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1204 sizeof(struct bge_tx_bd));
1209 bge_init_tx_ring(struct bge_softc *sc)
1212 sc->bge_tx_saved_considx = 0;
1214 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1215 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1216 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1218 /* Initialize transmit producer index for host-memory send ring. */
1219 sc->bge_tx_prodidx = 0;
1220 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1222 /* 5700 b2 errata */
1223 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1224 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1226 /* NIC-memory send ring not used; initialize to zero. */
1227 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1228 /* 5700 b2 errata */
1229 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1230 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1236 bge_setpromisc(struct bge_softc *sc)
1240 BGE_LOCK_ASSERT(sc);
1244 /* Enable or disable promiscuous mode as needed. */
1245 if (ifp->if_flags & IFF_PROMISC)
1246 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1248 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1252 bge_setmulti(struct bge_softc *sc)
1255 struct ifmultiaddr *ifma;
1256 uint32_t hashes[4] = { 0, 0, 0, 0 };
1259 BGE_LOCK_ASSERT(sc);
1263 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1264 for (i = 0; i < 4; i++)
1265 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1269 /* First, zot all the existing filters. */
1270 for (i = 0; i < 4; i++)
1271 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1273 /* Now program new ones. */
1274 if_maddr_rlock(ifp);
1275 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1276 if (ifma->ifma_addr->sa_family != AF_LINK)
1278 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1279 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1280 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1282 if_maddr_runlock(ifp);
1284 for (i = 0; i < 4; i++)
1285 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1289 bge_setvlan(struct bge_softc *sc)
1293 BGE_LOCK_ASSERT(sc);
1297 /* Enable or disable VLAN tag stripping as needed. */
1298 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1299 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1301 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1305 bge_sig_pre_reset(struct bge_softc *sc, int type)
1309 * Some chips don't like this so only do this if ASF is enabled
1311 if (sc->bge_asf_mode)
1312 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
1314 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1316 case BGE_RESET_START:
1317 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1319 case BGE_RESET_STOP:
1320 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1327 bge_sig_post_reset(struct bge_softc *sc, int type)
1330 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1332 case BGE_RESET_START:
1333 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001);
1336 case BGE_RESET_STOP:
1337 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002);
1344 bge_sig_legacy(struct bge_softc *sc, int type)
1347 if (sc->bge_asf_mode) {
1349 case BGE_RESET_START:
1350 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1352 case BGE_RESET_STOP:
1353 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1360 bge_stop_fw(struct bge_softc *sc)
1364 if (sc->bge_asf_mode) {
1365 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_PAUSE);
1366 CSR_WRITE_4(sc, BGE_CPU_EVENT,
1367 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
1369 for (i = 0; i < 100; i++ ) {
1370 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14)))
1378 * Do endian, PCI and DMA initialization.
1381 bge_chipinit(struct bge_softc *sc)
1383 uint32_t dma_rw_ctl, misc_ctl;
1387 /* Set endianness before we access any non-PCI registers. */
1388 misc_ctl = BGE_INIT;
1389 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1390 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1391 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1393 /* Clear the MAC control register */
1394 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1397 * Clear the MAC statistics block in the NIC's
1400 for (i = BGE_STATS_BLOCK;
1401 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1402 BGE_MEMWIN_WRITE(sc, i, 0);
1404 for (i = BGE_STATUS_BLOCK;
1405 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1406 BGE_MEMWIN_WRITE(sc, i, 0);
1408 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1410 * Fix data corruption caused by non-qword write with WB.
1411 * Fix master abort in PCI mode.
1412 * Fix PCI latency timer.
1414 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1415 val |= (1 << 10) | (1 << 12) | (1 << 13);
1416 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1420 * Set up the PCI DMA control register.
1422 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1423 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1424 if (sc->bge_flags & BGE_FLAG_PCIE) {
1425 /* Read watermark not used, 128 bytes for write. */
1426 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1427 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1428 if (BGE_IS_5714_FAMILY(sc)) {
1429 /* 256 bytes for read and write. */
1430 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1431 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1432 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1433 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1434 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1435 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1437 * In the BCM5703, the DMA read watermark should
1438 * be set to less than or equal to the maximum
1439 * memory read byte count of the PCI-X command
1442 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1443 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1444 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1445 /* 1536 bytes for read, 384 bytes for write. */
1446 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1447 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1449 /* 384 bytes for read and write. */
1450 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1451 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1454 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1455 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1458 /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1459 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1460 if (tmp == 6 || tmp == 7)
1462 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1464 /* Set PCI-X DMA write workaround. */
1465 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1468 /* Conventional PCI bus: 256 bytes for read and write. */
1469 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1470 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1472 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1473 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1476 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1477 sc->bge_asicrev == BGE_ASICREV_BCM5701)
1478 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1479 BGE_PCIDMARWCTL_ASRT_ALL_BE;
1480 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1481 sc->bge_asicrev == BGE_ASICREV_BCM5704)
1482 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1483 if (BGE_IS_5717_PLUS(sc)) {
1484 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1485 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
1486 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1488 * Enable HW workaround for controllers that misinterpret
1489 * a status tag update and leave interrupts permanently
1492 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
1493 sc->bge_asicrev != BGE_ASICREV_BCM57765)
1494 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1496 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1499 * Set up general mode register.
1501 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
1502 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1503 BGE_MODECTL_TX_NO_PHDR_CSUM);
1506 * BCM5701 B5 have a bug causing data corruption when using
1507 * 64-bit DMA reads, which can be terminated early and then
1508 * completed later as 32-bit accesses, in combination with
1511 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1512 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1513 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1516 * Tell the firmware the driver is running
1518 if (sc->bge_asf_mode & ASF_STACKUP)
1519 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
1522 * Disable memory write invalidate. Apparently it is not supported
1523 * properly by these devices. Also ensure that INTx isn't disabled,
1524 * as these chips need it even when using MSI.
1526 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1527 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
1529 /* Set the timer prescaler (always 66Mhz) */
1530 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1532 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1533 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1534 DELAY(40); /* XXX */
1536 /* Put PHY into ready state */
1537 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1538 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1546 bge_blockinit(struct bge_softc *sc)
1548 struct bge_rcb *rcb;
1551 uint32_t dmactl, val;
1555 * Initialize the memory window pointer register so that
1556 * we can access the first 32K of internal NIC RAM. This will
1557 * allow us to set up the TX send ring RCBs and the RX return
1558 * ring RCBs, plus other things which live in NIC memory.
1560 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1562 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1564 if (!(BGE_IS_5705_PLUS(sc))) {
1565 /* Configure mbuf memory pool */
1566 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1567 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1568 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1570 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1572 /* Configure DMA resource pool */
1573 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1574 BGE_DMA_DESCRIPTORS);
1575 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1578 /* Configure mbuf pool watermarks */
1579 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1580 sc->bge_asicrev == BGE_ASICREV_BCM57765) {
1581 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1582 if (sc->bge_ifp->if_mtu > ETHERMTU) {
1583 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1584 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1586 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1587 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1589 } else if (!BGE_IS_5705_PLUS(sc)) {
1590 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1591 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1592 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1593 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1594 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1595 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1596 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1598 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1599 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1600 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1603 /* Configure DMA resource watermarks */
1604 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1605 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1607 /* Enable buffer manager */
1608 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1610 * Change the arbitration algorithm of TXMBUF read request to
1611 * round-robin instead of priority based for BCM5719. When
1612 * TXFIFO is almost empty, RDMA will hold its request until
1613 * TXFIFO is not almost empty.
1615 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
1616 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1617 CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1619 /* Poll for buffer manager start indication */
1620 for (i = 0; i < BGE_TIMEOUT; i++) {
1622 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1626 if (i == BGE_TIMEOUT) {
1627 device_printf(sc->bge_dev, "buffer manager failed to start\n");
1631 /* Enable flow-through queues */
1632 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1633 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1635 /* Wait until queue initialization is complete */
1636 for (i = 0; i < BGE_TIMEOUT; i++) {
1638 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1642 if (i == BGE_TIMEOUT) {
1643 device_printf(sc->bge_dev, "flow-through queue init failed\n");
1648 * Summary of rings supported by the controller:
1650 * Standard Receive Producer Ring
1651 * - This ring is used to feed receive buffers for "standard"
1652 * sized frames (typically 1536 bytes) to the controller.
1654 * Jumbo Receive Producer Ring
1655 * - This ring is used to feed receive buffers for jumbo sized
1656 * frames (i.e. anything bigger than the "standard" frames)
1657 * to the controller.
1659 * Mini Receive Producer Ring
1660 * - This ring is used to feed receive buffers for "mini"
1661 * sized frames to the controller.
1662 * - This feature required external memory for the controller
1663 * but was never used in a production system. Should always
1666 * Receive Return Ring
1667 * - After the controller has placed an incoming frame into a
1668 * receive buffer that buffer is moved into a receive return
1669 * ring. The driver is then responsible to passing the
1670 * buffer up to the stack. Many versions of the controller
1671 * support multiple RR rings.
1674 * - This ring is used for outgoing frames. Many versions of
1675 * the controller support multiple send rings.
1678 /* Initialize the standard receive producer ring control block. */
1679 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1680 rcb->bge_hostaddr.bge_addr_lo =
1681 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1682 rcb->bge_hostaddr.bge_addr_hi =
1683 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1684 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1685 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1686 if (BGE_IS_5717_PLUS(sc)) {
1688 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1689 * Bits 15-2 : Maximum RX frame size
1690 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled
1693 rcb->bge_maxlen_flags =
1694 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
1695 } else if (BGE_IS_5705_PLUS(sc)) {
1697 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1698 * Bits 15-2 : Reserved (should be 0)
1699 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
1702 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1705 * Ring size is always XXX entries
1706 * Bits 31-16: Maximum RX frame size
1707 * Bits 15-2 : Reserved (should be 0)
1708 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
1711 rcb->bge_maxlen_flags =
1712 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1714 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1715 sc->bge_asicrev == BGE_ASICREV_BCM5719)
1716 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1718 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1719 /* Write the standard receive producer ring control block. */
1720 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1721 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1722 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1723 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1725 /* Reset the standard receive producer ring producer index. */
1726 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1729 * Initialize the jumbo RX producer ring control
1730 * block. We set the 'ring disabled' bit in the
1731 * flags field until we're actually ready to start
1732 * using this ring (i.e. once we set the MTU
1733 * high enough to require it).
1735 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1736 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1737 /* Get the jumbo receive producer ring RCB parameters. */
1738 rcb->bge_hostaddr.bge_addr_lo =
1739 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1740 rcb->bge_hostaddr.bge_addr_hi =
1741 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1742 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1743 sc->bge_cdata.bge_rx_jumbo_ring_map,
1744 BUS_DMASYNC_PREREAD);
1745 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1746 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1747 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1748 sc->bge_asicrev == BGE_ASICREV_BCM5719)
1749 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1751 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1752 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1753 rcb->bge_hostaddr.bge_addr_hi);
1754 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1755 rcb->bge_hostaddr.bge_addr_lo);
1756 /* Program the jumbo receive producer ring RCB parameters. */
1757 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1758 rcb->bge_maxlen_flags);
1759 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1760 /* Reset the jumbo receive producer ring producer index. */
1761 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1764 /* Disable the mini receive producer ring RCB. */
1765 if (BGE_IS_5700_FAMILY(sc)) {
1766 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1767 rcb->bge_maxlen_flags =
1768 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1769 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1770 rcb->bge_maxlen_flags);
1771 /* Reset the mini receive producer ring producer index. */
1772 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1775 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1776 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1777 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
1778 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
1779 sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
1780 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1781 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1784 * The BD ring replenish thresholds control how often the
1785 * hardware fetches new BD's from the producer rings in host
1786 * memory. Setting the value too low on a busy system can
1787 * starve the hardware and recue the throughpout.
1789 * Set the BD ring replentish thresholds. The recommended
1790 * values are 1/8th the number of descriptors allocated to
1792 * XXX The 5754 requires a lower threshold, so it might be a
1793 * requirement of all 575x family chips. The Linux driver sets
1794 * the lower threshold for all 5705 family chips as well, but there
1795 * are reports that it might not need to be so strict.
1797 * XXX Linux does some extra fiddling here for the 5906 parts as
1800 if (BGE_IS_5705_PLUS(sc))
1803 val = BGE_STD_RX_RING_CNT / 8;
1804 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1805 if (BGE_IS_JUMBO_CAPABLE(sc))
1806 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1807 BGE_JUMBO_RX_RING_CNT/8);
1808 if (BGE_IS_5717_PLUS(sc)) {
1809 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1810 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1814 * Disable all send rings by setting the 'ring disabled' bit
1815 * in the flags field of all the TX send ring control blocks,
1816 * located in NIC memory.
1818 if (!BGE_IS_5705_PLUS(sc))
1819 /* 5700 to 5704 had 16 send rings. */
1820 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
1823 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1824 for (i = 0; i < limit; i++) {
1825 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1826 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1827 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1828 vrcb += sizeof(struct bge_rcb);
1831 /* Configure send ring RCB 0 (we use only the first ring) */
1832 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1833 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1834 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1835 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1836 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1837 sc->bge_asicrev == BGE_ASICREV_BCM5719)
1838 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1840 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1841 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1842 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1843 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1846 * Disable all receive return rings by setting the
1847 * 'ring diabled' bit in the flags field of all the receive
1848 * return ring control blocks, located in NIC memory.
1850 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1851 sc->bge_asicrev == BGE_ASICREV_BCM5719) {
1852 /* Should be 17, use 16 until we get an SRAM map. */
1854 } else if (!BGE_IS_5705_PLUS(sc))
1855 limit = BGE_RX_RINGS_MAX;
1856 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1857 sc->bge_asicrev == BGE_ASICREV_BCM57765)
1861 /* Disable all receive return rings. */
1862 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1863 for (i = 0; i < limit; i++) {
1864 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1865 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1866 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1867 BGE_RCB_FLAG_RING_DISABLED);
1868 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1869 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1870 (i * (sizeof(uint64_t))), 0);
1871 vrcb += sizeof(struct bge_rcb);
1875 * Set up receive return ring 0. Note that the NIC address
1876 * for RX return rings is 0x0. The return rings live entirely
1877 * within the host, so the nicaddr field in the RCB isn't used.
1879 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1880 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1881 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1882 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1883 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1884 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1885 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1887 /* Set random backoff seed for TX */
1888 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1889 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1890 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1891 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1892 BGE_TX_BACKOFF_SEED_MASK);
1894 /* Set inter-packet gap */
1895 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1898 * Specify which ring to use for packets that don't match
1901 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1904 * Configure number of RX lists. One interrupt distribution
1905 * list, sixteen active lists, one bad frames class.
1907 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1909 /* Inialize RX list placement stats mask. */
1910 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1911 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1913 /* Disable host coalescing until we get it set up */
1914 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1916 /* Poll to make sure it's shut down. */
1917 for (i = 0; i < BGE_TIMEOUT; i++) {
1919 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1923 if (i == BGE_TIMEOUT) {
1924 device_printf(sc->bge_dev,
1925 "host coalescing engine failed to idle\n");
1929 /* Set up host coalescing defaults */
1930 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1931 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1932 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1933 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1934 if (!(BGE_IS_5705_PLUS(sc))) {
1935 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1936 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1938 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1939 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1941 /* Set up address of statistics block */
1942 if (!(BGE_IS_5705_PLUS(sc))) {
1943 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1944 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1945 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1946 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1947 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1948 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1949 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1952 /* Set up address of status block */
1953 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1954 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1955 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1956 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1958 /* Set up status block size. */
1959 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1960 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
1961 val = BGE_STATBLKSZ_FULL;
1962 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
1964 val = BGE_STATBLKSZ_32BYTE;
1965 bzero(sc->bge_ldata.bge_status_block, 32);
1967 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
1968 sc->bge_cdata.bge_status_map,
1969 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1971 /* Turn on host coalescing state machine */
1972 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1974 /* Turn on RX BD completion state machine and enable attentions */
1975 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1976 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
1978 /* Turn on RX list placement state machine */
1979 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1981 /* Turn on RX list selector state machine. */
1982 if (!(BGE_IS_5705_PLUS(sc)))
1983 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1985 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1986 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1987 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1988 BGE_MACMODE_FRMHDR_DMA_ENB;
1990 if (sc->bge_flags & BGE_FLAG_TBI)
1991 val |= BGE_PORTMODE_TBI;
1992 else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1993 val |= BGE_PORTMODE_GMII;
1995 val |= BGE_PORTMODE_MII;
1997 /* Turn on DMA, clear stats */
1998 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
2000 /* Set misc. local control, enable interrupts on attentions */
2001 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2004 /* Assert GPIO pins for PHY reset */
2005 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
2006 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
2007 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
2008 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
2011 /* Turn on DMA completion state machine */
2012 if (!(BGE_IS_5705_PLUS(sc)))
2013 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2015 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
2017 /* Enable host coalescing bug fix. */
2018 if (BGE_IS_5755_PLUS(sc))
2019 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
2021 /* Request larger DMA burst size to get better performance. */
2022 if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
2023 val |= BGE_WDMAMODE_BURST_ALL_DATA;
2025 /* Turn on write DMA state machine */
2026 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
2029 /* Turn on read DMA state machine */
2030 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
2032 if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
2033 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
2035 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2036 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2037 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2038 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
2039 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
2040 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
2041 if (sc->bge_flags & BGE_FLAG_PCIE)
2042 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2043 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2044 val |= BGE_RDMAMODE_TSO4_ENABLE;
2045 if (sc->bge_flags & BGE_FLAG_TSO3 ||
2046 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2047 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2048 val |= BGE_RDMAMODE_TSO6_ENABLE;
2050 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2051 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2052 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2053 sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2054 BGE_IS_5717_PLUS(sc)) {
2055 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
2057 * Adjust tx margin to prevent TX data corruption and
2058 * fix internal FIFO overflow.
2060 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2061 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2062 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2063 BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2064 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2065 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2066 BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2069 * Enable fix for read DMA FIFO overruns.
2070 * The fix is to limit the number of RX BDs
2071 * the hardware would fetch at a fime.
2073 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl |
2074 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2077 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2078 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2079 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2080 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2081 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2084 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2087 /* Turn on RX data completion state machine */
2088 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2090 /* Turn on RX BD initiator state machine */
2091 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2093 /* Turn on RX data and RX BD initiator state machine */
2094 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2096 /* Turn on Mbuf cluster free state machine */
2097 if (!(BGE_IS_5705_PLUS(sc)))
2098 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2100 /* Turn on send BD completion state machine */
2101 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2103 /* Turn on send data completion state machine */
2104 val = BGE_SDCMODE_ENABLE;
2105 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2106 val |= BGE_SDCMODE_CDELAY;
2107 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2109 /* Turn on send data initiator state machine */
2110 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2111 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2112 BGE_SDIMODE_HW_LSO_PRE_DMA);
2114 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2116 /* Turn on send BD initiator state machine */
2117 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2119 /* Turn on send BD selector state machine */
2120 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2122 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
2123 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
2124 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
2126 /* ack/clear link change events */
2127 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2128 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2129 BGE_MACSTAT_LINK_CHANGED);
2130 CSR_WRITE_4(sc, BGE_MI_STS, 0);
2133 * Enable attention when the link has changed state for
2134 * devices that use auto polling.
2136 if (sc->bge_flags & BGE_FLAG_TBI) {
2137 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
2139 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2140 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
2143 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2144 sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
2145 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2146 BGE_EVTENB_MI_INTERRUPT);
2150 * Clear any pending link state attention.
2151 * Otherwise some link state change events may be lost until attention
2152 * is cleared by bge_intr() -> bge_link_upd() sequence.
2153 * It's not necessary on newer BCM chips - perhaps enabling link
2154 * state change attentions implies clearing pending attention.
2156 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2157 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2158 BGE_MACSTAT_LINK_CHANGED);
2160 /* Enable link state change attentions. */
2161 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2166 const struct bge_revision *
2167 bge_lookup_rev(uint32_t chipid)
2169 const struct bge_revision *br;
2171 for (br = bge_revisions; br->br_name != NULL; br++) {
2172 if (br->br_chipid == chipid)
2176 for (br = bge_majorrevs; br->br_name != NULL; br++) {
2177 if (br->br_chipid == BGE_ASICREV(chipid))
2184 const struct bge_vendor *
2185 bge_lookup_vendor(uint16_t vid)
2187 const struct bge_vendor *v;
2189 for (v = bge_vendors; v->v_name != NULL; v++)
2193 panic("%s: unknown vendor %d", __func__, vid);
2198 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
2199 * against our list and return its name if we find a match.
2201 * Note that since the Broadcom controller contains VPD support, we
2202 * try to get the device name string from the controller itself instead
2203 * of the compiled-in string. It guarantees we'll always announce the
2204 * right product name. We fall back to the compiled-in string when
2205 * VPD is unavailable or corrupt.
2208 bge_probe(device_t dev)
2212 const struct bge_revision *br;
2214 struct bge_softc *sc = device_get_softc(dev);
2215 const struct bge_type *t = bge_devs;
2216 const struct bge_vendor *v;
2221 vid = pci_get_vendor(dev);
2222 did = pci_get_device(dev);
2223 while(t->bge_vid != 0) {
2224 if ((vid == t->bge_vid) && (did == t->bge_did)) {
2225 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2226 BGE_PCIMISCCTL_ASICREV_SHIFT;
2227 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
2229 * Find the ASCI revision. Different chips
2230 * use different registers.
2232 switch (pci_get_device(dev)) {
2233 case BCOM_DEVICEID_BCM5717:
2234 case BCOM_DEVICEID_BCM5718:
2235 case BCOM_DEVICEID_BCM5719:
2236 id = pci_read_config(dev,
2237 BGE_PCI_GEN2_PRODID_ASICREV, 4);
2239 case BCOM_DEVICEID_BCM57761:
2240 case BCOM_DEVICEID_BCM57765:
2241 case BCOM_DEVICEID_BCM57781:
2242 case BCOM_DEVICEID_BCM57785:
2243 case BCOM_DEVICEID_BCM57791:
2244 case BCOM_DEVICEID_BCM57795:
2245 id = pci_read_config(dev,
2246 BGE_PCI_GEN15_PRODID_ASICREV, 4);
2249 id = pci_read_config(dev,
2250 BGE_PCI_PRODID_ASICREV, 4);
2253 br = bge_lookup_rev(id);
2254 v = bge_lookup_vendor(vid);
2255 if (bge_has_eaddr(sc) &&
2256 pci_get_vpd_ident(dev, &pname) == 0)
2257 snprintf(model, 64, "%s", pname);
2259 snprintf(model, 64, "%s %s", v->v_name,
2260 br != NULL ? br->br_name :
2261 "NetXtreme Ethernet Controller");
2262 snprintf(buf, 96, "%s, %sASIC rev. %#08x", model,
2263 br != NULL ? "" : "unknown ", id);
2264 device_set_desc_copy(dev, buf);
2274 bge_dma_free(struct bge_softc *sc)
2278 /* Destroy DMA maps for RX buffers. */
2279 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2280 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2281 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2282 sc->bge_cdata.bge_rx_std_dmamap[i]);
2284 if (sc->bge_cdata.bge_rx_std_sparemap)
2285 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2286 sc->bge_cdata.bge_rx_std_sparemap);
2288 /* Destroy DMA maps for jumbo RX buffers. */
2289 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2290 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2291 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2292 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2294 if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2295 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2296 sc->bge_cdata.bge_rx_jumbo_sparemap);
2298 /* Destroy DMA maps for TX buffers. */
2299 for (i = 0; i < BGE_TX_RING_CNT; i++) {
2300 if (sc->bge_cdata.bge_tx_dmamap[i])
2301 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2302 sc->bge_cdata.bge_tx_dmamap[i]);
2305 if (sc->bge_cdata.bge_rx_mtag)
2306 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2307 if (sc->bge_cdata.bge_tx_mtag)
2308 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2311 /* Destroy standard RX ring. */
2312 if (sc->bge_cdata.bge_rx_std_ring_map)
2313 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2314 sc->bge_cdata.bge_rx_std_ring_map);
2315 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
2316 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2317 sc->bge_ldata.bge_rx_std_ring,
2318 sc->bge_cdata.bge_rx_std_ring_map);
2320 if (sc->bge_cdata.bge_rx_std_ring_tag)
2321 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2323 /* Destroy jumbo RX ring. */
2324 if (sc->bge_cdata.bge_rx_jumbo_ring_map)
2325 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2326 sc->bge_cdata.bge_rx_jumbo_ring_map);
2328 if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
2329 sc->bge_ldata.bge_rx_jumbo_ring)
2330 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2331 sc->bge_ldata.bge_rx_jumbo_ring,
2332 sc->bge_cdata.bge_rx_jumbo_ring_map);
2334 if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2335 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2337 /* Destroy RX return ring. */
2338 if (sc->bge_cdata.bge_rx_return_ring_map)
2339 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2340 sc->bge_cdata.bge_rx_return_ring_map);
2342 if (sc->bge_cdata.bge_rx_return_ring_map &&
2343 sc->bge_ldata.bge_rx_return_ring)
2344 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2345 sc->bge_ldata.bge_rx_return_ring,
2346 sc->bge_cdata.bge_rx_return_ring_map);
2348 if (sc->bge_cdata.bge_rx_return_ring_tag)
2349 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2351 /* Destroy TX ring. */
2352 if (sc->bge_cdata.bge_tx_ring_map)
2353 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2354 sc->bge_cdata.bge_tx_ring_map);
2356 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
2357 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2358 sc->bge_ldata.bge_tx_ring,
2359 sc->bge_cdata.bge_tx_ring_map);
2361 if (sc->bge_cdata.bge_tx_ring_tag)
2362 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2364 /* Destroy status block. */
2365 if (sc->bge_cdata.bge_status_map)
2366 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2367 sc->bge_cdata.bge_status_map);
2369 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
2370 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2371 sc->bge_ldata.bge_status_block,
2372 sc->bge_cdata.bge_status_map);
2374 if (sc->bge_cdata.bge_status_tag)
2375 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2377 /* Destroy statistics block. */
2378 if (sc->bge_cdata.bge_stats_map)
2379 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2380 sc->bge_cdata.bge_stats_map);
2382 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2383 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2384 sc->bge_ldata.bge_stats,
2385 sc->bge_cdata.bge_stats_map);
2387 if (sc->bge_cdata.bge_stats_tag)
2388 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2390 if (sc->bge_cdata.bge_buffer_tag)
2391 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
2393 /* Destroy the parent tag. */
2394 if (sc->bge_cdata.bge_parent_tag)
2395 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2399 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
2400 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
2401 bus_addr_t *paddr, const char *msg)
2403 struct bge_dmamap_arg ctx;
2405 bus_size_t ring_end;
2408 lowaddr = BUS_SPACE_MAXADDR;
2410 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2411 alignment, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2412 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
2414 device_printf(sc->bge_dev,
2415 "could not create %s dma tag\n", msg);
2418 /* Allocate DMA'able memory for ring. */
2419 error = bus_dmamem_alloc(*tag, (void **)ring,
2420 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
2422 device_printf(sc->bge_dev,
2423 "could not allocate DMA'able memory for %s\n", msg);
2426 /* Load the address of the ring. */
2427 ctx.bge_busaddr = 0;
2428 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr,
2429 &ctx, BUS_DMA_NOWAIT);
2431 device_printf(sc->bge_dev,
2432 "could not load DMA'able memory for %s\n", msg);
2435 *paddr = ctx.bge_busaddr;
2436 ring_end = *paddr + maxsize;
2437 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0 &&
2438 BGE_ADDR_HI(*paddr) != BGE_ADDR_HI(ring_end)) {
2440 * 4GB boundary crossed. Limit maximum allowable DMA
2441 * address space to 32bit and try again.
2443 bus_dmamap_unload(*tag, *map);
2444 bus_dmamem_free(*tag, *ring, *map);
2445 bus_dma_tag_destroy(*tag);
2447 device_printf(sc->bge_dev, "4GB boundary crossed, "
2448 "limit DMA address space to 32bit for %s\n", msg);
2452 lowaddr = BUS_SPACE_MAXADDR_32BIT;
2459 bge_dma_alloc(struct bge_softc *sc)
2462 bus_size_t boundary, sbsz, rxmaxsegsz, txsegsz, txmaxsegsz;
2465 lowaddr = BUS_SPACE_MAXADDR;
2466 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2467 lowaddr = BGE_DMA_MAXADDR;
2469 * Allocate the parent bus DMA tag appropriate for PCI.
2471 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2472 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2473 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2474 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2476 device_printf(sc->bge_dev,
2477 "could not allocate parent dma tag\n");
2481 /* Create tag for standard RX ring. */
2482 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
2483 &sc->bge_cdata.bge_rx_std_ring_tag,
2484 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
2485 &sc->bge_cdata.bge_rx_std_ring_map,
2486 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
2490 /* Create tag for RX return ring. */
2491 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
2492 &sc->bge_cdata.bge_rx_return_ring_tag,
2493 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
2494 &sc->bge_cdata.bge_rx_return_ring_map,
2495 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
2499 /* Create tag for TX ring. */
2500 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
2501 &sc->bge_cdata.bge_tx_ring_tag,
2502 (uint8_t **)&sc->bge_ldata.bge_tx_ring,
2503 &sc->bge_cdata.bge_tx_ring_map,
2504 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
2509 * Create tag for status block.
2510 * Because we only use single Tx/Rx/Rx return ring, use
2511 * minimum status block size except BCM5700 AX/BX which
2512 * seems to want to see full status block size regardless
2513 * of configured number of ring.
2515 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2516 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
2517 sbsz = BGE_STATUS_BLK_SZ;
2520 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
2521 &sc->bge_cdata.bge_status_tag,
2522 (uint8_t **)&sc->bge_ldata.bge_status_block,
2523 &sc->bge_cdata.bge_status_map,
2524 &sc->bge_ldata.bge_status_block_paddr, "status block");
2528 /* Create tag for statistics block. */
2529 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
2530 &sc->bge_cdata.bge_stats_tag,
2531 (uint8_t **)&sc->bge_ldata.bge_stats,
2532 &sc->bge_cdata.bge_stats_map,
2533 &sc->bge_ldata.bge_stats_paddr, "statistics block");
2537 /* Create tag for jumbo RX ring. */
2538 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2539 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
2540 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
2541 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
2542 &sc->bge_cdata.bge_rx_jumbo_ring_map,
2543 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
2548 /* Create parent tag for buffers. */
2550 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
2551 boundary = BGE_DMA_BNDRY;
2554 * watchdog timeout issue was observed on BCM5704 which
2555 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge).
2556 * Limiting DMA address space to 32bits seems to address
2559 if (sc->bge_flags & BGE_FLAG_PCIX)
2560 lowaddr = BUS_SPACE_MAXADDR_32BIT;
2562 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2563 1, boundary, lowaddr, BUS_SPACE_MAXADDR, NULL,
2564 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2565 0, NULL, NULL, &sc->bge_cdata.bge_buffer_tag);
2567 device_printf(sc->bge_dev,
2568 "could not allocate buffer dma tag\n");
2571 /* Create tag for Tx mbufs. */
2572 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2573 txsegsz = BGE_TSOSEG_SZ;
2574 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
2577 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
2579 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
2580 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2581 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
2582 &sc->bge_cdata.bge_tx_mtag);
2585 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
2589 /* Create tag for Rx mbufs. */
2590 if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
2591 rxmaxsegsz = MJUM9BYTES;
2593 rxmaxsegsz = MCLBYTES;
2594 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
2595 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1,
2596 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
2599 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
2603 /* Create DMA maps for RX buffers. */
2604 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2605 &sc->bge_cdata.bge_rx_std_sparemap);
2607 device_printf(sc->bge_dev,
2608 "can't create spare DMA map for RX\n");
2611 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2612 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2613 &sc->bge_cdata.bge_rx_std_dmamap[i]);
2615 device_printf(sc->bge_dev,
2616 "can't create DMA map for RX\n");
2621 /* Create DMA maps for TX buffers. */
2622 for (i = 0; i < BGE_TX_RING_CNT; i++) {
2623 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
2624 &sc->bge_cdata.bge_tx_dmamap[i]);
2626 device_printf(sc->bge_dev,
2627 "can't create DMA map for TX\n");
2632 /* Create tags for jumbo RX buffers. */
2633 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2634 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
2635 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2636 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
2637 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
2639 device_printf(sc->bge_dev,
2640 "could not allocate jumbo dma tag\n");
2643 /* Create DMA maps for jumbo RX buffers. */
2644 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2645 0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
2647 device_printf(sc->bge_dev,
2648 "can't create spare DMA map for jumbo RX\n");
2651 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2652 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2653 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2655 device_printf(sc->bge_dev,
2656 "can't create DMA map for jumbo RX\n");
2666 * Return true if this device has more than one port.
2669 bge_has_multiple_ports(struct bge_softc *sc)
2671 device_t dev = sc->bge_dev;
2672 u_int b, d, f, fscan, s;
2674 d = pci_get_domain(dev);
2675 b = pci_get_bus(dev);
2676 s = pci_get_slot(dev);
2677 f = pci_get_function(dev);
2678 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
2679 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
2685 * Return true if MSI can be used with this device.
2688 bge_can_use_msi(struct bge_softc *sc)
2690 int can_use_msi = 0;
2692 /* Disable MSI for polling(4). */
2693 #ifdef DEVICE_POLLING
2696 switch (sc->bge_asicrev) {
2697 case BGE_ASICREV_BCM5714_A0:
2698 case BGE_ASICREV_BCM5714:
2700 * Apparently, MSI doesn't work when these chips are
2701 * configured in single-port mode.
2703 if (bge_has_multiple_ports(sc))
2706 case BGE_ASICREV_BCM5750:
2707 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
2708 sc->bge_chiprev != BGE_CHIPREV_5750_BX)
2712 if (BGE_IS_575X_PLUS(sc))
2715 return (can_use_msi);
2719 bge_attach(device_t dev)
2722 struct bge_softc *sc;
2723 uint32_t hwcfg = 0, misccfg;
2724 u_char eaddr[ETHER_ADDR_LEN];
2725 int capmask, error, f, msicount, phy_addr, reg, rid, trys;
2727 sc = device_get_softc(dev);
2730 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
2733 * Map control/status registers.
2735 pci_enable_busmaster(dev);
2738 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2741 if (sc->bge_res == NULL) {
2742 device_printf (sc->bge_dev, "couldn't map memory\n");
2747 /* Save various chip information. */
2749 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2750 BGE_PCIMISCCTL_ASICREV_SHIFT;
2751 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) {
2753 * Find the ASCI revision. Different chips use different
2756 switch (pci_get_device(dev)) {
2757 case BCOM_DEVICEID_BCM5717:
2758 case BCOM_DEVICEID_BCM5718:
2759 case BCOM_DEVICEID_BCM5719:
2760 sc->bge_chipid = pci_read_config(dev,
2761 BGE_PCI_GEN2_PRODID_ASICREV, 4);
2763 case BCOM_DEVICEID_BCM57761:
2764 case BCOM_DEVICEID_BCM57765:
2765 case BCOM_DEVICEID_BCM57781:
2766 case BCOM_DEVICEID_BCM57785:
2767 case BCOM_DEVICEID_BCM57791:
2768 case BCOM_DEVICEID_BCM57795:
2769 sc->bge_chipid = pci_read_config(dev,
2770 BGE_PCI_GEN15_PRODID_ASICREV, 4);
2773 sc->bge_chipid = pci_read_config(dev,
2774 BGE_PCI_PRODID_ASICREV, 4);
2777 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2778 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2780 /* Set default PHY address. */
2783 * PHY address mapping for various devices.
2785 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
2786 * ---------+-------+-------+-------+-------+
2787 * BCM57XX | 1 | X | X | X |
2788 * BCM5704 | 1 | X | 1 | X |
2789 * BCM5717 | 1 | 8 | 2 | 9 |
2790 * BCM5719 | 1 | 8 | 2 | 9 |
2792 * Other addresses may respond but they are not
2793 * IEEE compliant PHYs and should be ignored.
2795 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2796 sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2797 f = pci_get_function(dev);
2798 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) {
2799 if (CSR_READ_4(sc, BGE_SGDIG_STS) &
2800 BGE_SGDIGSTS_IS_SERDES)
2805 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
2806 BGE_CPMU_PHY_STRAP_IS_SERDES)
2814 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the
2815 * 5705 A0 and A1 chips.
2817 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2818 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2819 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2820 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
2821 sc->bge_asicrev == BGE_ASICREV_BCM5906)
2822 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
2824 if (bge_has_eaddr(sc))
2825 sc->bge_flags |= BGE_FLAG_EADDR;
2827 /* Save chipset family. */
2828 switch (sc->bge_asicrev) {
2829 case BGE_ASICREV_BCM5717:
2830 case BGE_ASICREV_BCM5719:
2831 case BGE_ASICREV_BCM57765:
2832 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
2833 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
2834 BGE_FLAG_JUMBO_FRAME;
2835 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
2836 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
2837 /* Jumbo frame on BCM5719 A0 does not work. */
2838 sc->bge_flags &= ~BGE_FLAG_JUMBO;
2841 case BGE_ASICREV_BCM5755:
2842 case BGE_ASICREV_BCM5761:
2843 case BGE_ASICREV_BCM5784:
2844 case BGE_ASICREV_BCM5785:
2845 case BGE_ASICREV_BCM5787:
2846 case BGE_ASICREV_BCM57780:
2847 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2850 case BGE_ASICREV_BCM5700:
2851 case BGE_ASICREV_BCM5701:
2852 case BGE_ASICREV_BCM5703:
2853 case BGE_ASICREV_BCM5704:
2854 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2856 case BGE_ASICREV_BCM5714_A0:
2857 case BGE_ASICREV_BCM5780:
2858 case BGE_ASICREV_BCM5714:
2859 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
2861 case BGE_ASICREV_BCM5750:
2862 case BGE_ASICREV_BCM5752:
2863 case BGE_ASICREV_BCM5906:
2864 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2866 case BGE_ASICREV_BCM5705:
2867 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2871 /* Set various PHY bug flags. */
2872 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2873 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2874 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
2875 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2876 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2877 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
2878 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2879 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
2880 if (pci_get_subvendor(dev) == DELL_VENDORID)
2881 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
2882 if ((BGE_IS_5705_PLUS(sc)) &&
2883 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2884 sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
2885 sc->bge_asicrev != BGE_ASICREV_BCM5719 &&
2886 sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2887 sc->bge_asicrev != BGE_ASICREV_BCM57765 &&
2888 sc->bge_asicrev != BGE_ASICREV_BCM57780) {
2889 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2890 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2891 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2892 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2893 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
2894 pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
2895 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
2896 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
2897 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
2899 sc->bge_phy_flags |= BGE_PHY_BER_BUG;
2902 /* Identify the chips that use an CPMU. */
2903 if (BGE_IS_5717_PLUS(sc) ||
2904 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2905 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2906 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2907 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2908 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
2909 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
2910 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
2912 sc->bge_mi_mode = BGE_MIMODE_BASE;
2913 /* Enable auto polling for BCM570[0-5]. */
2914 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
2915 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
2918 * All Broadcom controllers have 4GB boundary DMA bug.
2919 * Whenever an address crosses a multiple of the 4GB boundary
2920 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
2921 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
2922 * state machine will lockup and cause the device to hang.
2924 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
2926 /* BCM5755 or higher and BCM5906 have short DMA bug. */
2927 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
2928 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
2931 * BCM5719 cannot handle DMA requests for DMA segments that
2932 * have larger than 4KB in size. However the maximum DMA
2933 * segment size created in DMA tag is 4KB for TSO, so we
2934 * wouldn't encounter the issue here.
2936 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2937 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG;
2939 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID;
2940 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
2941 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2942 misccfg == BGE_MISCCFG_BOARD_ID_5788M)
2943 sc->bge_flags |= BGE_FLAG_5788;
2946 capmask = BMSR_DEFCAPMASK;
2947 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
2948 (misccfg == 0x4000 || misccfg == 0x8000)) ||
2949 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2950 pci_get_vendor(dev) == BCOM_VENDORID &&
2951 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 ||
2952 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 ||
2953 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) ||
2954 (pci_get_vendor(dev) == BCOM_VENDORID &&
2955 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F ||
2956 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F ||
2957 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) ||
2958 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 ||
2959 sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2960 /* These chips are 10/100 only. */
2961 capmask &= ~BMSR_EXTSTAT;
2965 * Some controllers seem to require a special firmware to use
2966 * TSO. But the firmware is not available to FreeBSD and Linux
2967 * claims that the TSO performed by the firmware is slower than
2968 * hardware based TSO. Moreover the firmware based TSO has one
2969 * known bug which can't handle TSO if ethernet header + IP/TCP
2970 * header is greater than 80 bytes. The workaround for the TSO
2971 * bug exist but it seems it's too expensive than not using
2972 * TSO at all. Some hardwares also have the TSO bug so limit
2973 * the TSO to the controllers that are not affected TSO issues
2974 * (e.g. 5755 or higher).
2976 if (BGE_IS_5717_PLUS(sc)) {
2977 /* BCM5717 requires different TSO configuration. */
2978 sc->bge_flags |= BGE_FLAG_TSO3;
2979 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
2980 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
2981 /* TSO on BCM5719 A0 does not work. */
2982 sc->bge_flags &= ~BGE_FLAG_TSO3;
2984 } else if (BGE_IS_5755_PLUS(sc)) {
2986 * BCM5754 and BCM5787 shares the same ASIC id so
2987 * explicit device id check is required.
2988 * Due to unknown reason TSO does not work on BCM5755M.
2990 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
2991 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
2992 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
2993 sc->bge_flags |= BGE_FLAG_TSO;
2997 * Check if this is a PCI-X or PCI Express device.
2999 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
3001 * Found a PCI Express capabilities register, this
3002 * must be a PCI Express device.
3004 sc->bge_flags |= BGE_FLAG_PCIE;
3005 sc->bge_expcap = reg;
3006 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
3007 pci_set_max_read_req(dev, 2048);
3008 else if (pci_get_max_read_req(dev) != 4096)
3009 pci_set_max_read_req(dev, 4096);
3012 * Check if the device is in PCI-X Mode.
3013 * (This bit is not valid on PCI Express controllers.)
3015 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0)
3016 sc->bge_pcixcap = reg;
3017 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
3018 BGE_PCISTATE_PCI_BUSMODE) == 0)
3019 sc->bge_flags |= BGE_FLAG_PCIX;
3023 * The 40bit DMA bug applies to the 5714/5715 controllers and is
3024 * not actually a MAC controller bug but an issue with the embedded
3025 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
3027 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
3028 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
3030 * Allocate the interrupt, using MSI if possible. These devices
3031 * support 8 MSI messages, but only the first one is used in
3035 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) {
3036 sc->bge_msicap = reg;
3037 if (bge_can_use_msi(sc)) {
3038 msicount = pci_msi_count(dev);
3043 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
3045 sc->bge_flags |= BGE_FLAG_MSI;
3050 * All controllers except BCM5700 supports tagged status but
3051 * we use tagged status only for MSI case on BCM5717. Otherwise
3052 * MSI on BCM5717 does not work.
3054 #ifndef DEVICE_POLLING
3055 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
3056 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
3059 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3060 RF_SHAREABLE | RF_ACTIVE);
3062 if (sc->bge_irq == NULL) {
3063 device_printf(sc->bge_dev, "couldn't map interrupt\n");
3069 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
3070 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
3071 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" :
3072 ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI"));
3074 BGE_LOCK_INIT(sc, device_get_nameunit(dev));
3076 /* Try to reset the chip. */
3077 if (bge_reset(sc)) {
3078 device_printf(sc->bge_dev, "chip reset failed\n");
3083 sc->bge_asf_mode = 0;
3084 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3085 BGE_SRAM_DATA_SIG_MAGIC)) {
3086 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG)
3088 sc->bge_asf_mode |= ASF_ENABLE;
3089 sc->bge_asf_mode |= ASF_STACKUP;
3090 if (BGE_IS_575X_PLUS(sc))
3091 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3095 /* Try to reset the chip again the nice way. */
3097 bge_sig_pre_reset(sc, BGE_RESET_STOP);
3098 if (bge_reset(sc)) {
3099 device_printf(sc->bge_dev, "chip reset failed\n");
3104 bge_sig_legacy(sc, BGE_RESET_STOP);
3105 bge_sig_post_reset(sc, BGE_RESET_STOP);
3107 if (bge_chipinit(sc)) {
3108 device_printf(sc->bge_dev, "chip initialization failed\n");
3113 error = bge_get_eaddr(sc, eaddr);
3115 device_printf(sc->bge_dev,
3116 "failed to read station address\n");
3121 /* 5705 limits RX return ring to 512 entries. */
3122 if (BGE_IS_5717_PLUS(sc))
3123 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3124 else if (BGE_IS_5705_PLUS(sc))
3125 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3127 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3129 if (bge_dma_alloc(sc)) {
3130 device_printf(sc->bge_dev,
3131 "failed to allocate DMA resources\n");
3136 bge_add_sysctls(sc);
3138 /* Set default tuneable values. */
3139 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3140 sc->bge_rx_coal_ticks = 150;
3141 sc->bge_tx_coal_ticks = 150;
3142 sc->bge_rx_max_coal_bds = 10;
3143 sc->bge_tx_max_coal_bds = 10;
3145 /* Initialize checksum features to use. */
3146 sc->bge_csum_features = BGE_CSUM_FEATURES;
3147 if (sc->bge_forced_udpcsum != 0)
3148 sc->bge_csum_features |= CSUM_UDP;
3150 /* Set up ifnet structure */
3151 ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
3153 device_printf(sc->bge_dev, "failed to if_alloc()\n");
3158 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3159 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3160 ifp->if_ioctl = bge_ioctl;
3161 ifp->if_start = bge_start;
3162 ifp->if_init = bge_init;
3163 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
3164 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
3165 IFQ_SET_READY(&ifp->if_snd);
3166 ifp->if_hwassist = sc->bge_csum_features;
3167 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3169 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3170 ifp->if_hwassist |= CSUM_TSO;
3171 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO;
3173 #ifdef IFCAP_VLAN_HWCSUM
3174 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
3176 ifp->if_capenable = ifp->if_capabilities;
3177 #ifdef DEVICE_POLLING
3178 ifp->if_capabilities |= IFCAP_POLLING;
3182 * 5700 B0 chips do not support checksumming correctly due
3185 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
3186 ifp->if_capabilities &= ~IFCAP_HWCSUM;
3187 ifp->if_capenable &= ~IFCAP_HWCSUM;
3188 ifp->if_hwassist = 0;
3192 * Figure out what sort of media we have by checking the
3193 * hardware config word in the first 32k of NIC internal memory,
3194 * or fall back to examining the EEPROM if necessary.
3195 * Note: on some BCM5700 cards, this value appears to be unset.
3196 * If that's the case, we have to rely on identifying the NIC
3197 * by its PCI subsystem ID, as we do below for the SysKonnect
3200 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
3201 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3202 else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
3203 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3204 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
3206 device_printf(sc->bge_dev, "failed to read EEPROM\n");
3210 hwcfg = ntohl(hwcfg);
3213 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
3214 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
3215 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
3216 if (BGE_IS_5714_FAMILY(sc))
3217 sc->bge_flags |= BGE_FLAG_MII_SERDES;
3219 sc->bge_flags |= BGE_FLAG_TBI;
3222 if (sc->bge_flags & BGE_FLAG_TBI) {
3223 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3225 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
3226 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
3228 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3229 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3230 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3233 * Do transceiver setup and tell the firmware the
3234 * driver is down so we can try to get access the
3235 * probe if ASF is running. Retry a couple of times
3236 * if we get a conflict with the ASF firmware accessing
3240 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3242 bge_asf_driver_up(sc);
3244 error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd,
3245 bge_ifmedia_sts, capmask, phy_addr, MII_OFFSET_ANY,
3249 device_printf(sc->bge_dev, "Try again\n");
3250 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR,
3254 device_printf(sc->bge_dev, "attaching PHYs failed\n");
3259 * Now tell the firmware we are going up after probing the PHY
3261 if (sc->bge_asf_mode & ASF_STACKUP)
3262 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3266 * When using the BCM5701 in PCI-X mode, data corruption has
3267 * been observed in the first few bytes of some received packets.
3268 * Aligning the packet buffer in memory eliminates the corruption.
3269 * Unfortunately, this misaligns the packet payloads. On platforms
3270 * which do not support unaligned accesses, we will realign the
3271 * payloads by copying the received packets.
3273 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
3274 sc->bge_flags & BGE_FLAG_PCIX)
3275 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
3278 * Call MI attach routine.
3280 ether_ifattach(ifp, eaddr);
3281 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
3283 /* Tell upper layer we support long frames. */
3284 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
3289 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
3290 /* Take advantage of single-shot MSI. */
3291 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
3292 ~BGE_MSIMODE_ONE_SHOT_DISABLE);
3293 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
3294 taskqueue_thread_enqueue, &sc->bge_tq);
3295 if (sc->bge_tq == NULL) {
3296 device_printf(dev, "could not create taskqueue.\n");
3297 ether_ifdetach(ifp);
3301 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq",
3302 device_get_nameunit(sc->bge_dev));
3303 error = bus_setup_intr(dev, sc->bge_irq,
3304 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
3307 ether_ifdetach(ifp);
3309 error = bus_setup_intr(dev, sc->bge_irq,
3310 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
3315 device_printf(sc->bge_dev, "couldn't set up irq\n");
3321 bge_release_resources(sc);
3327 bge_detach(device_t dev)
3329 struct bge_softc *sc;
3332 sc = device_get_softc(dev);
3335 #ifdef DEVICE_POLLING
3336 if (ifp->if_capenable & IFCAP_POLLING)
3337 ether_poll_deregister(ifp);
3345 callout_drain(&sc->bge_stat_ch);
3348 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3349 ether_ifdetach(ifp);
3351 if (sc->bge_flags & BGE_FLAG_TBI) {
3352 ifmedia_removeall(&sc->bge_ifmedia);
3354 bus_generic_detach(dev);
3355 device_delete_child(dev, sc->bge_miibus);
3358 bge_release_resources(sc);
3364 bge_release_resources(struct bge_softc *sc)
3370 if (sc->bge_tq != NULL)
3371 taskqueue_free(sc->bge_tq);
3373 if (sc->bge_intrhand != NULL)
3374 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3376 if (sc->bge_irq != NULL)
3377 bus_release_resource(dev, SYS_RES_IRQ,
3378 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
3380 if (sc->bge_flags & BGE_FLAG_MSI)
3381 pci_release_msi(dev);
3383 if (sc->bge_res != NULL)
3384 bus_release_resource(dev, SYS_RES_MEMORY,
3385 PCIR_BAR(0), sc->bge_res);
3387 if (sc->bge_ifp != NULL)
3388 if_free(sc->bge_ifp);
3392 if (mtx_initialized(&sc->bge_mtx)) /* XXX */
3393 BGE_LOCK_DESTROY(sc);
3397 bge_reset(struct bge_softc *sc)
3400 uint32_t cachesize, command, pcistate, reset, val;
3401 void (*write_op)(struct bge_softc *, int, int);
3407 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
3408 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3409 if (sc->bge_flags & BGE_FLAG_PCIE)
3410 write_op = bge_writemem_direct;
3412 write_op = bge_writemem_ind;
3414 write_op = bge_writereg_ind;
3416 /* Save some important PCI state. */
3417 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
3418 command = pci_read_config(dev, BGE_PCI_CMD, 4);
3419 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3421 pci_write_config(dev, BGE_PCI_MISC_CTL,
3422 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3423 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3425 /* Disable fastboot on controllers that support it. */
3426 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
3427 BGE_IS_5755_PLUS(sc)) {
3429 device_printf(dev, "Disabling fastboot\n");
3430 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
3434 * Write the magic number to SRAM at offset 0xB50.
3435 * When firmware finishes its initialization it will
3436 * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
3438 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
3440 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
3442 /* XXX: Broadcom Linux driver. */
3443 if (sc->bge_flags & BGE_FLAG_PCIE) {
3444 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */
3445 CSR_WRITE_4(sc, 0x7E2C, 0x20);
3446 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3447 /* Prevent PCIE link training during global reset */
3448 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
3454 * Set GPHY Power Down Override to leave GPHY
3455 * powered up in D0 uninitialized.
3457 if (BGE_IS_5705_PLUS(sc) &&
3458 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0)
3459 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
3461 /* Issue global reset */
3462 write_op(sc, BGE_MISC_CFG, reset);
3464 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3465 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3466 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
3467 val | BGE_VCPU_STATUS_DRV_RESET);
3468 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
3469 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
3470 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
3475 /* XXX: Broadcom Linux driver. */
3476 if (sc->bge_flags & BGE_FLAG_PCIE) {
3477 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
3478 DELAY(500000); /* wait for link training to complete */
3479 val = pci_read_config(dev, 0xC4, 4);
3480 pci_write_config(dev, 0xC4, val | (1 << 15), 4);
3482 devctl = pci_read_config(dev,
3483 sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
3484 /* Clear enable no snoop and disable relaxed ordering. */
3485 devctl &= ~(PCIM_EXP_CTL_RELAXED_ORD_ENABLE |
3486 PCIM_EXP_CTL_NOSNOOP_ENABLE);
3487 /* Set PCIE max payload size to 128. */
3488 devctl &= ~PCIM_EXP_CTL_MAX_PAYLOAD;
3489 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL,
3491 /* Clear error status. */
3492 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA,
3493 PCIM_EXP_STA_CORRECTABLE_ERROR |
3494 PCIM_EXP_STA_NON_FATAL_ERROR | PCIM_EXP_STA_FATAL_ERROR |
3495 PCIM_EXP_STA_UNSUPPORTED_REQ, 2);
3498 /* Reset some of the PCI state that got zapped by reset. */
3499 pci_write_config(dev, BGE_PCI_MISC_CTL,
3500 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3501 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3502 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
3503 pci_write_config(dev, BGE_PCI_CMD, command, 4);
3504 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
3506 * Disable PCI-X relaxed ordering to ensure status block update
3507 * comes first then packet buffer DMA. Otherwise driver may
3508 * read stale status block.
3510 if (sc->bge_flags & BGE_FLAG_PCIX) {
3511 devctl = pci_read_config(dev,
3512 sc->bge_pcixcap + PCIXR_COMMAND, 2);
3513 devctl &= ~PCIXM_COMMAND_ERO;
3514 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
3515 devctl &= ~PCIXM_COMMAND_MAX_READ;
3516 devctl |= PCIXM_COMMAND_MAX_READ_2048;
3517 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3518 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
3519 PCIXM_COMMAND_MAX_READ);
3520 devctl |= PCIXM_COMMAND_MAX_READ_2048;
3522 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
3525 /* Re-enable MSI, if necessary, and enable the memory arbiter. */
3526 if (BGE_IS_5714_FAMILY(sc)) {
3527 /* This chip disables MSI on reset. */
3528 if (sc->bge_flags & BGE_FLAG_MSI) {
3529 val = pci_read_config(dev,
3530 sc->bge_msicap + PCIR_MSI_CTRL, 2);
3531 pci_write_config(dev,
3532 sc->bge_msicap + PCIR_MSI_CTRL,
3533 val | PCIM_MSICTRL_MSI_ENABLE, 2);
3534 val = CSR_READ_4(sc, BGE_MSI_MODE);
3535 CSR_WRITE_4(sc, BGE_MSI_MODE,
3536 val | BGE_MSIMODE_ENABLE);
3538 val = CSR_READ_4(sc, BGE_MARB_MODE);
3539 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
3541 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3543 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3544 for (i = 0; i < BGE_TIMEOUT; i++) {
3545 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3546 if (val & BGE_VCPU_STATUS_INIT_DONE)
3550 if (i == BGE_TIMEOUT) {
3551 device_printf(dev, "reset timed out\n");
3556 * Poll until we see the 1's complement of the magic number.
3557 * This indicates that the firmware initialization is complete.
3558 * We expect this to fail if no chip containing the Ethernet
3559 * address is fitted though.
3561 for (i = 0; i < BGE_TIMEOUT; i++) {
3563 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
3564 if (val == ~BGE_SRAM_FW_MB_MAGIC)
3568 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
3570 "firmware handshake timed out, found 0x%08x\n",
3572 /* BCM57765 A0 needs additional time before accessing. */
3573 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
3574 DELAY(10 * 1000); /* XXX */
3578 * XXX Wait for the value of the PCISTATE register to
3579 * return to its original pre-reset state. This is a
3580 * fairly good indicator of reset completion. If we don't
3581 * wait for the reset to fully complete, trying to read
3582 * from the device's non-PCI registers may yield garbage
3585 for (i = 0; i < BGE_TIMEOUT; i++) {
3586 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
3591 /* Fix up byte swapping. */
3592 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
3593 BGE_MODECTL_BYTESWAP_DATA);
3595 /* Tell the ASF firmware we are up */
3596 if (sc->bge_asf_mode & ASF_STACKUP)
3597 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3599 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
3602 * The 5704 in TBI mode apparently needs some special
3603 * adjustment to insure the SERDES drive level is set
3606 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
3607 sc->bge_flags & BGE_FLAG_TBI) {
3608 val = CSR_READ_4(sc, BGE_SERDES_CFG);
3609 val = (val & ~0xFFF) | 0x880;
3610 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
3613 /* XXX: Broadcom Linux driver. */
3614 if (sc->bge_flags & BGE_FLAG_PCIE &&
3615 !BGE_IS_5717_PLUS(sc) &&
3616 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
3617 sc->bge_asicrev != BGE_ASICREV_BCM5785) {
3618 /* Enable Data FIFO protection. */
3619 val = CSR_READ_4(sc, 0x7C00);
3620 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
3627 static __inline void
3628 bge_rxreuse_std(struct bge_softc *sc, int i)
3630 struct bge_rx_bd *r;
3632 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
3633 r->bge_flags = BGE_RXBDFLAG_END;
3634 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
3636 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3639 static __inline void
3640 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
3642 struct bge_extrx_bd *r;
3644 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
3645 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
3646 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
3647 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
3648 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
3649 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
3651 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3655 * Frame reception handling. This is called if there's a frame
3656 * on the receive return list.
3658 * Note: we have to be able to handle two possibilities here:
3659 * 1) the frame is from the jumbo receive ring
3660 * 2) the frame is from the standard receive ring
3664 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
3667 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
3670 rx_cons = sc->bge_rx_saved_considx;
3672 /* Nothing to do. */
3673 if (rx_cons == rx_prod)
3678 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3679 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
3680 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3681 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
3682 if (BGE_IS_JUMBO_CAPABLE(sc) &&
3683 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
3684 (MCLBYTES - ETHER_ALIGN))
3685 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3686 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
3688 while (rx_cons != rx_prod) {
3689 struct bge_rx_bd *cur_rx;
3691 struct mbuf *m = NULL;
3692 uint16_t vlan_tag = 0;
3695 #ifdef DEVICE_POLLING
3696 if (ifp->if_capenable & IFCAP_POLLING) {
3697 if (sc->rxcycles <= 0)
3703 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
3705 rxidx = cur_rx->bge_idx;
3706 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
3708 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
3709 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
3711 vlan_tag = cur_rx->bge_vlan_tag;
3714 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
3716 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
3717 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3718 bge_rxreuse_jumbo(sc, rxidx);
3721 if (bge_newbuf_jumbo(sc, rxidx) != 0) {
3722 bge_rxreuse_jumbo(sc, rxidx);
3726 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3729 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
3730 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3731 bge_rxreuse_std(sc, rxidx);
3734 if (bge_newbuf_std(sc, rxidx) != 0) {
3735 bge_rxreuse_std(sc, rxidx);
3739 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3743 #ifndef __NO_STRICT_ALIGNMENT
3745 * For architectures with strict alignment we must make sure
3746 * the payload is aligned.
3748 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
3749 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
3751 m->m_data += ETHER_ALIGN;
3754 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3755 m->m_pkthdr.rcvif = ifp;
3757 if (ifp->if_capenable & IFCAP_RXCSUM)
3758 bge_rxcsum(sc, cur_rx, m);
3761 * If we received a packet with a vlan tag,
3762 * attach that information to the packet.
3765 m->m_pkthdr.ether_vtag = vlan_tag;
3766 m->m_flags |= M_VLANTAG;
3771 (*ifp->if_input)(ifp, m);
3774 (*ifp->if_input)(ifp, m);
3777 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
3781 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3782 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
3784 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3785 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
3788 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3789 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
3791 sc->bge_rx_saved_considx = rx_cons;
3792 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3794 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
3795 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT);
3797 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
3798 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT);
3801 * This register wraps very quickly under heavy packet drops.
3802 * If you need correct statistics, you can enable this check.
3804 if (BGE_IS_5705_PLUS(sc))
3805 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3811 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
3814 if (BGE_IS_5717_PLUS(sc)) {
3815 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
3816 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3817 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3818 if ((cur_rx->bge_error_flag &
3819 BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
3820 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3822 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
3823 m->m_pkthdr.csum_data =
3824 cur_rx->bge_tcp_udp_csum;
3825 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
3830 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3831 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3832 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
3833 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3835 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
3836 m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
3837 m->m_pkthdr.csum_data =
3838 cur_rx->bge_tcp_udp_csum;
3839 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
3846 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
3848 struct bge_tx_bd *cur_tx;
3851 BGE_LOCK_ASSERT(sc);
3853 /* Nothing to do. */
3854 if (sc->bge_tx_saved_considx == tx_cons)
3859 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
3860 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
3862 * Go through our tx ring and free mbufs for those
3863 * frames that have been sent.
3865 while (sc->bge_tx_saved_considx != tx_cons) {
3868 idx = sc->bge_tx_saved_considx;
3869 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
3870 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
3872 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
3873 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
3874 sc->bge_cdata.bge_tx_dmamap[idx],
3875 BUS_DMASYNC_POSTWRITE);
3876 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
3877 sc->bge_cdata.bge_tx_dmamap[idx]);
3878 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
3879 sc->bge_cdata.bge_tx_chain[idx] = NULL;
3882 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3885 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3886 if (sc->bge_txcnt == 0)
3890 #ifdef DEVICE_POLLING
3892 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3894 struct bge_softc *sc = ifp->if_softc;
3895 uint16_t rx_prod, tx_cons;
3896 uint32_t statusword;
3900 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3905 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3906 sc->bge_cdata.bge_status_map,
3907 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3908 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3909 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3911 statusword = sc->bge_ldata.bge_status_block->bge_status;
3912 sc->bge_ldata.bge_status_block->bge_status = 0;
3914 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3915 sc->bge_cdata.bge_status_map,
3916 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3918 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
3919 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
3922 if (cmd == POLL_AND_CHECK_STATUS)
3923 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3924 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3925 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
3928 sc->rxcycles = count;
3929 rx_npkts = bge_rxeof(sc, rx_prod, 1);
3930 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3934 bge_txeof(sc, tx_cons);
3935 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3936 bge_start_locked(ifp);
3941 #endif /* DEVICE_POLLING */
3944 bge_msi_intr(void *arg)
3946 struct bge_softc *sc;
3948 sc = (struct bge_softc *)arg;
3950 * This interrupt is not shared and controller already
3951 * disabled further interrupt.
3953 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
3954 return (FILTER_HANDLED);
3958 bge_intr_task(void *arg, int pending)
3960 struct bge_softc *sc;
3962 uint32_t status, status_tag;
3963 uint16_t rx_prod, tx_cons;
3965 sc = (struct bge_softc *)arg;
3969 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3974 /* Get updated status block. */
3975 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3976 sc->bge_cdata.bge_status_map,
3977 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3979 /* Save producer/consumer indexess. */
3980 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3981 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3982 status = sc->bge_ldata.bge_status_block->bge_status;
3983 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
3984 sc->bge_ldata.bge_status_block->bge_status = 0;
3985 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3986 sc->bge_cdata.bge_status_map,
3987 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3988 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
3991 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
3994 /* Let controller work. */
3995 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
3997 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3998 sc->bge_rx_saved_considx != rx_prod) {
3999 /* Check RX return ring producer/consumer. */
4001 bge_rxeof(sc, rx_prod, 0);
4004 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4005 /* Check TX ring producer/consumer. */
4006 bge_txeof(sc, tx_cons);
4007 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4008 bge_start_locked(ifp);
4016 struct bge_softc *sc;
4018 uint32_t statusword;
4019 uint16_t rx_prod, tx_cons;
4027 #ifdef DEVICE_POLLING
4028 if (ifp->if_capenable & IFCAP_POLLING) {
4035 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
4036 * disable interrupts by writing nonzero like we used to, since with
4037 * our current organization this just gives complications and
4038 * pessimizations for re-enabling interrupts. We used to have races
4039 * instead of the necessary complications. Disabling interrupts
4040 * would just reduce the chance of a status update while we are
4041 * running (by switching to the interrupt-mode coalescence
4042 * parameters), but this chance is already very low so it is more
4043 * efficient to get another interrupt than prevent it.
4045 * We do the ack first to ensure another interrupt if there is a
4046 * status update after the ack. We don't check for the status
4047 * changing later because it is more efficient to get another
4048 * interrupt than prevent it, not quite as above (not checking is
4049 * a smaller optimization than not toggling the interrupt enable,
4050 * since checking doesn't involve PCI accesses and toggling require
4051 * the status check). So toggling would probably be a pessimization
4052 * even with MSI. It would only be needed for using a task queue.
4054 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4057 * Do the mandatory PCI flush as well as get the link status.
4059 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
4061 /* Make sure the descriptor ring indexes are coherent. */
4062 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4063 sc->bge_cdata.bge_status_map,
4064 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4065 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4066 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4067 sc->bge_ldata.bge_status_block->bge_status = 0;
4068 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4069 sc->bge_cdata.bge_status_map,
4070 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4072 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4073 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4074 statusword || sc->bge_link_evt)
4077 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4078 /* Check RX return ring producer/consumer. */
4079 bge_rxeof(sc, rx_prod, 1);
4082 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4083 /* Check TX ring producer/consumer. */
4084 bge_txeof(sc, tx_cons);
4087 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
4088 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4089 bge_start_locked(ifp);
4095 bge_asf_driver_up(struct bge_softc *sc)
4097 if (sc->bge_asf_mode & ASF_STACKUP) {
4098 /* Send ASF heartbeat aprox. every 2s */
4099 if (sc->bge_asf_count)
4100 sc->bge_asf_count --;
4102 sc->bge_asf_count = 2;
4103 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4105 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4106 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 3);
4107 CSR_WRITE_4(sc, BGE_CPU_EVENT,
4108 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
4116 struct bge_softc *sc = xsc;
4117 struct mii_data *mii = NULL;
4119 BGE_LOCK_ASSERT(sc);
4121 /* Synchronize with possible callout reset/stop. */
4122 if (callout_pending(&sc->bge_stat_ch) ||
4123 !callout_active(&sc->bge_stat_ch))
4126 if (BGE_IS_5705_PLUS(sc))
4127 bge_stats_update_regs(sc);
4129 bge_stats_update(sc);
4131 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4132 mii = device_get_softc(sc->bge_miibus);
4134 * Do not touch PHY if we have link up. This could break
4135 * IPMI/ASF mode or produce extra input errors
4136 * (extra errors was reported for bcm5701 & bcm5704).
4142 * Since in TBI mode auto-polling can't be used we should poll
4143 * link status manually. Here we register pending link event
4144 * and trigger interrupt.
4146 #ifdef DEVICE_POLLING
4147 /* In polling mode we poll link state in bge_poll(). */
4148 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
4152 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4153 sc->bge_flags & BGE_FLAG_5788)
4154 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4156 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4160 bge_asf_driver_up(sc);
4163 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4167 bge_stats_update_regs(struct bge_softc *sc)
4170 struct bge_mac_stats *stats;
4173 stats = &sc->bge_mac_stats;
4175 stats->ifHCOutOctets +=
4176 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4177 stats->etherStatsCollisions +=
4178 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4179 stats->outXonSent +=
4180 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4181 stats->outXoffSent +=
4182 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4183 stats->dot3StatsInternalMacTransmitErrors +=
4184 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4185 stats->dot3StatsSingleCollisionFrames +=
4186 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4187 stats->dot3StatsMultipleCollisionFrames +=
4188 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4189 stats->dot3StatsDeferredTransmissions +=
4190 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4191 stats->dot3StatsExcessiveCollisions +=
4192 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4193 stats->dot3StatsLateCollisions +=
4194 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4195 stats->ifHCOutUcastPkts +=
4196 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4197 stats->ifHCOutMulticastPkts +=
4198 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4199 stats->ifHCOutBroadcastPkts +=
4200 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4202 stats->ifHCInOctets +=
4203 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4204 stats->etherStatsFragments +=
4205 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4206 stats->ifHCInUcastPkts +=
4207 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4208 stats->ifHCInMulticastPkts +=
4209 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4210 stats->ifHCInBroadcastPkts +=
4211 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4212 stats->dot3StatsFCSErrors +=
4213 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4214 stats->dot3StatsAlignmentErrors +=
4215 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4216 stats->xonPauseFramesReceived +=
4217 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4218 stats->xoffPauseFramesReceived +=
4219 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4220 stats->macControlFramesReceived +=
4221 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4222 stats->xoffStateEntered +=
4223 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4224 stats->dot3StatsFramesTooLong +=
4225 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4226 stats->etherStatsJabbers +=
4227 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4228 stats->etherStatsUndersizePkts +=
4229 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4231 stats->FramesDroppedDueToFilters +=
4232 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4233 stats->DmaWriteQueueFull +=
4234 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4235 stats->DmaWriteHighPriQueueFull +=
4236 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4237 stats->NoMoreRxBDs +=
4238 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4239 stats->InputDiscards +=
4240 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4241 stats->InputErrors +=
4242 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4243 stats->RecvThresholdHit +=
4244 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4246 ifp->if_collisions = (u_long)stats->etherStatsCollisions;
4247 ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards +
4248 stats->InputErrors);
4252 bge_stats_clear_regs(struct bge_softc *sc)
4255 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4256 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4257 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4258 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4259 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4260 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4261 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4262 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4263 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4264 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4265 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4266 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4267 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4269 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4270 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4271 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4272 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4273 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4274 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4275 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4276 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4277 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4278 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4279 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4280 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4281 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4282 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4284 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4285 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4286 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4287 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4288 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4289 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4290 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4294 bge_stats_update(struct bge_softc *sc)
4298 uint32_t cnt; /* current register value */
4302 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
4304 #define READ_STAT(sc, stats, stat) \
4305 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
4307 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
4308 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
4309 sc->bge_tx_collisions = cnt;
4311 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
4312 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
4313 sc->bge_rx_discards = cnt;
4315 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
4316 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
4317 sc->bge_tx_discards = cnt;
4323 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
4324 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
4325 * but when such padded frames employ the bge IP/TCP checksum offload,
4326 * the hardware checksum assist gives incorrect results (possibly
4327 * from incorporating its own padding into the UDP/TCP checksum; who knows).
4328 * If we pad such runts with zeros, the onboard checksum comes out correct.
4331 bge_cksum_pad(struct mbuf *m)
4333 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
4336 /* If there's only the packet-header and we can pad there, use it. */
4337 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
4338 M_TRAILINGSPACE(m) >= padlen) {
4342 * Walk packet chain to find last mbuf. We will either
4343 * pad there, or append a new mbuf and pad it.
4345 for (last = m; last->m_next != NULL; last = last->m_next);
4346 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
4347 /* Allocate new empty mbuf, pad it. Compact later. */
4350 MGET(n, M_DONTWAIT, MT_DATA);
4359 /* Now zero the pad area, to avoid the bge cksum-assist bug. */
4360 memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
4361 last->m_len += padlen;
4362 m->m_pkthdr.len += padlen;
4367 static struct mbuf *
4368 bge_check_short_dma(struct mbuf *m)
4374 * If device receive two back-to-back send BDs with less than
4375 * or equal to 8 total bytes then the device may hang. The two
4376 * back-to-back send BDs must in the same frame for this failure
4377 * to occur. Scan mbuf chains and see whether two back-to-back
4378 * send BDs are there. If this is the case, allocate new mbuf
4379 * and copy the frame to workaround the silicon bug.
4381 for (n = m, found = 0; n != NULL; n = n->m_next) {
4392 n = m_defrag(m, M_DONTWAIT);
4400 static struct mbuf *
4401 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
4410 if (M_WRITABLE(m) == 0) {
4411 /* Get a writable copy. */
4412 n = m_dup(m, M_DONTWAIT);
4418 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
4421 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
4422 poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
4423 m = m_pullup(m, poff + sizeof(struct tcphdr));
4426 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
4427 m = m_pullup(m, poff + (tcp->th_off << 2));
4431 * It seems controller doesn't modify IP length and TCP pseudo
4432 * checksum. These checksum computed by upper stack should be 0.
4434 *mss = m->m_pkthdr.tso_segsz;
4435 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
4437 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
4438 /* Clear pseudo checksum computed by TCP stack. */
4439 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
4442 * Broadcom controllers uses different descriptor format for
4443 * TSO depending on ASIC revision. Due to TSO-capable firmware
4444 * license issue and lower performance of firmware based TSO
4445 * we only support hardware based TSO.
4447 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */
4448 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
4449 if (sc->bge_flags & BGE_FLAG_TSO3) {
4451 * For BCM5717 and newer controllers, hardware based TSO
4452 * uses the 14 lower bits of the bge_mss field to store the
4453 * MSS and the upper 2 bits to store the lowest 2 bits of
4454 * the IP/TCP header length. The upper 6 bits of the header
4455 * length are stored in the bge_flags[14:10,4] field. Jumbo
4456 * frames are supported.
4458 *mss |= ((hlen & 0x3) << 14);
4459 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2);
4462 * For BCM5755 and newer controllers, hardware based TSO uses
4463 * the lower 11 bits to store the MSS and the upper 5 bits to
4464 * store the IP/TCP header length. Jumbo frames are not
4467 *mss |= (hlen << 11);
4473 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
4474 * pointers to descriptors.
4477 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
4479 bus_dma_segment_t segs[BGE_NSEG_NEW];
4481 struct bge_tx_bd *d;
4482 struct mbuf *m = *m_head;
4483 uint32_t idx = *txidx;
4484 uint16_t csum_flags, mss, vlan_tag;
4485 int nsegs, i, error;
4490 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
4491 m->m_next != NULL) {
4492 *m_head = bge_check_short_dma(m);
4493 if (*m_head == NULL)
4497 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
4498 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
4499 if (*m_head == NULL)
4501 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
4502 BGE_TXBDFLAG_CPU_POST_DMA;
4503 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
4504 if (m->m_pkthdr.csum_flags & CSUM_IP)
4505 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
4506 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
4507 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
4508 if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
4509 (error = bge_cksum_pad(m)) != 0) {
4515 if (m->m_flags & M_LASTFRAG)
4516 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
4517 else if (m->m_flags & M_FRAG)
4518 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
4521 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
4522 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
4523 m->m_pkthdr.len > ETHER_MAX_LEN)
4524 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME;
4525 if (sc->bge_forced_collapse > 0 &&
4526 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
4528 * Forcedly collapse mbuf chains to overcome hardware
4529 * limitation which only support a single outstanding
4530 * DMA read operation.
4532 if (sc->bge_forced_collapse == 1)
4533 m = m_defrag(m, M_DONTWAIT);
4535 m = m_collapse(m, M_DONTWAIT,
4536 sc->bge_forced_collapse);
4543 map = sc->bge_cdata.bge_tx_dmamap[idx];
4544 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
4545 &nsegs, BUS_DMA_NOWAIT);
4546 if (error == EFBIG) {
4547 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW);
4554 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
4555 m, segs, &nsegs, BUS_DMA_NOWAIT);
4561 } else if (error != 0)
4564 /* Check if we have enough free send BDs. */
4565 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
4566 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
4570 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
4572 if (m->m_flags & M_VLANTAG) {
4573 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
4574 vlan_tag = m->m_pkthdr.ether_vtag;
4576 for (i = 0; ; i++) {
4577 d = &sc->bge_ldata.bge_tx_ring[idx];
4578 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
4579 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
4580 d->bge_len = segs[i].ds_len;
4581 d->bge_flags = csum_flags;
4582 d->bge_vlan_tag = vlan_tag;
4586 BGE_INC(idx, BGE_TX_RING_CNT);
4589 /* Mark the last segment as end of packet... */
4590 d->bge_flags |= BGE_TXBDFLAG_END;
4593 * Insure that the map for this transmission
4594 * is placed at the array index of the last descriptor
4597 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
4598 sc->bge_cdata.bge_tx_dmamap[idx] = map;
4599 sc->bge_cdata.bge_tx_chain[idx] = m;
4600 sc->bge_txcnt += nsegs;
4602 BGE_INC(idx, BGE_TX_RING_CNT);
4609 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4610 * to the mbuf data regions directly in the transmit descriptors.
4613 bge_start_locked(struct ifnet *ifp)
4615 struct bge_softc *sc;
4616 struct mbuf *m_head;
4621 BGE_LOCK_ASSERT(sc);
4623 if (!sc->bge_link ||
4624 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4628 prodidx = sc->bge_tx_prodidx;
4630 for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
4631 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
4632 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4635 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
4641 * The code inside the if() block is never reached since we
4642 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
4643 * requests to checksum TCP/UDP in a fragmented packet.
4646 * safety overkill. If this is a fragmented packet chain
4647 * with delayed TCP/UDP checksums, then only encapsulate
4648 * it if we have enough descriptors to handle the entire
4650 * (paranoia -- may not actually be needed)
4652 if (m_head->m_flags & M_FIRSTFRAG &&
4653 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
4654 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
4655 m_head->m_pkthdr.csum_data + 16) {
4656 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4657 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4663 * Pack the data into the transmit ring. If we
4664 * don't have room, set the OACTIVE flag and wait
4665 * for the NIC to drain the ring.
4667 if (bge_encap(sc, &m_head, &prodidx)) {
4670 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4671 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4677 * If there's a BPF listener, bounce a copy of this frame
4680 #ifdef ETHER_BPF_MTAP
4681 ETHER_BPF_MTAP(ifp, m_head);
4683 BPF_MTAP(ifp, m_head);
4688 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4689 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
4691 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4692 /* 5700 b2 errata */
4693 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
4694 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4696 sc->bge_tx_prodidx = prodidx;
4699 * Set a timeout in case the chip goes out to lunch.
4706 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4707 * to the mbuf data regions directly in the transmit descriptors.
4710 bge_start(struct ifnet *ifp)
4712 struct bge_softc *sc;
4716 bge_start_locked(ifp);
4721 bge_init_locked(struct bge_softc *sc)
4727 BGE_LOCK_ASSERT(sc);
4731 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4734 /* Cancel pending I/O and flush buffers. */
4738 bge_sig_pre_reset(sc, BGE_RESET_START);
4740 bge_sig_legacy(sc, BGE_RESET_START);
4741 bge_sig_post_reset(sc, BGE_RESET_START);
4746 * Init the various state machines, ring
4747 * control blocks and firmware.
4749 if (bge_blockinit(sc)) {
4750 device_printf(sc->bge_dev, "initialization failure\n");
4757 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
4758 ETHER_HDR_LEN + ETHER_CRC_LEN +
4759 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
4761 /* Load our MAC address. */
4762 m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
4763 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
4764 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
4766 /* Program promiscuous mode. */
4769 /* Program multicast filter. */
4772 /* Program VLAN tag stripping. */
4775 /* Override UDP checksum offloading. */
4776 if (sc->bge_forced_udpcsum == 0)
4777 sc->bge_csum_features &= ~CSUM_UDP;
4779 sc->bge_csum_features |= CSUM_UDP;
4780 if (ifp->if_capabilities & IFCAP_TXCSUM &&
4781 ifp->if_capenable & IFCAP_TXCSUM) {
4782 ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP);
4783 ifp->if_hwassist |= sc->bge_csum_features;
4787 if (bge_init_rx_ring_std(sc) != 0) {
4788 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
4794 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
4795 * memory to insure that the chip has in fact read the first
4796 * entry of the ring.
4798 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
4800 for (i = 0; i < 10; i++) {
4802 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
4803 if (v == (MCLBYTES - ETHER_ALIGN))
4807 device_printf (sc->bge_dev,
4808 "5705 A0 chip failed to load RX ring\n");
4811 /* Init jumbo RX ring. */
4812 if (BGE_IS_JUMBO_CAPABLE(sc) &&
4813 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
4814 (MCLBYTES - ETHER_ALIGN)) {
4815 if (bge_init_rx_ring_jumbo(sc) != 0) {
4816 device_printf(sc->bge_dev,
4817 "no memory for jumbo Rx buffers.\n");
4823 /* Init our RX return ring index. */
4824 sc->bge_rx_saved_considx = 0;
4826 /* Init our RX/TX stat counters. */
4827 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
4830 bge_init_tx_ring(sc);
4832 /* Enable TX MAC state machine lockup fix. */
4833 mode = CSR_READ_4(sc, BGE_TX_MODE);
4834 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
4835 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
4836 /* Turn on transmitter. */
4837 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
4839 /* Turn on receiver. */
4840 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4843 * Set the number of good frames to receive after RX MBUF
4844 * Low Watermark has been reached. After the RX MAC receives
4845 * this number of frames, it will drop subsequent incoming
4846 * frames until the MBUF High Watermark is reached.
4848 if (sc->bge_asicrev == BGE_ASICREV_BCM57765)
4849 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
4851 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
4853 /* Clear MAC statistics. */
4854 if (BGE_IS_5705_PLUS(sc))
4855 bge_stats_clear_regs(sc);
4857 /* Tell firmware we're alive. */
4858 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4860 #ifdef DEVICE_POLLING
4861 /* Disable interrupts if we are polling. */
4862 if (ifp->if_capenable & IFCAP_POLLING) {
4863 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4864 BGE_PCIMISCCTL_MASK_PCI_INTR);
4865 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4869 /* Enable host interrupts. */
4871 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
4872 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4873 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4876 bge_ifmedia_upd_locked(ifp);
4878 ifp->if_drv_flags |= IFF_DRV_RUNNING;
4879 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4881 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4887 struct bge_softc *sc = xsc;
4890 bge_init_locked(sc);
4895 * Set media options.
4898 bge_ifmedia_upd(struct ifnet *ifp)
4900 struct bge_softc *sc = ifp->if_softc;
4904 res = bge_ifmedia_upd_locked(ifp);
4911 bge_ifmedia_upd_locked(struct ifnet *ifp)
4913 struct bge_softc *sc = ifp->if_softc;
4914 struct mii_data *mii;
4915 struct mii_softc *miisc;
4916 struct ifmedia *ifm;
4918 BGE_LOCK_ASSERT(sc);
4920 ifm = &sc->bge_ifmedia;
4922 /* If this is a 1000baseX NIC, enable the TBI port. */
4923 if (sc->bge_flags & BGE_FLAG_TBI) {
4924 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
4926 switch(IFM_SUBTYPE(ifm->ifm_media)) {
4929 * The BCM5704 ASIC appears to have a special
4930 * mechanism for programming the autoneg
4931 * advertisement registers in TBI mode.
4933 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4935 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
4936 if (sgdig & BGE_SGDIGSTS_DONE) {
4937 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
4938 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
4939 sgdig |= BGE_SGDIGCFG_AUTO |
4940 BGE_SGDIGCFG_PAUSE_CAP |
4941 BGE_SGDIGCFG_ASYM_PAUSE;
4942 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
4943 sgdig | BGE_SGDIGCFG_SEND);
4945 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
4950 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
4951 BGE_CLRBIT(sc, BGE_MAC_MODE,
4952 BGE_MACMODE_HALF_DUPLEX);
4954 BGE_SETBIT(sc, BGE_MAC_MODE,
4955 BGE_MACMODE_HALF_DUPLEX);
4965 mii = device_get_softc(sc->bge_miibus);
4966 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4971 * Force an interrupt so that we will call bge_link_upd
4972 * if needed and clear any pending link state attention.
4973 * Without this we are not getting any further interrupts
4974 * for link state changes and thus will not UP the link and
4975 * not be able to send in bge_start_locked. The only
4976 * way to get things working was to receive a packet and
4978 * bge_tick should help for fiber cards and we might not
4979 * need to do this here if BGE_FLAG_TBI is set but as
4980 * we poll for fiber anyway it should not harm.
4982 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4983 sc->bge_flags & BGE_FLAG_5788)
4984 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4986 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4992 * Report current media status.
4995 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4997 struct bge_softc *sc = ifp->if_softc;
4998 struct mii_data *mii;
5002 if (sc->bge_flags & BGE_FLAG_TBI) {
5003 ifmr->ifm_status = IFM_AVALID;
5004 ifmr->ifm_active = IFM_ETHER;
5005 if (CSR_READ_4(sc, BGE_MAC_STS) &
5006 BGE_MACSTAT_TBI_PCS_SYNCHED)
5007 ifmr->ifm_status |= IFM_ACTIVE;
5009 ifmr->ifm_active |= IFM_NONE;
5013 ifmr->ifm_active |= IFM_1000_SX;
5014 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5015 ifmr->ifm_active |= IFM_HDX;
5017 ifmr->ifm_active |= IFM_FDX;
5022 mii = device_get_softc(sc->bge_miibus);
5024 ifmr->ifm_active = mii->mii_media_active;
5025 ifmr->ifm_status = mii->mii_media_status;
5031 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
5033 struct bge_softc *sc = ifp->if_softc;
5034 struct ifreq *ifr = (struct ifreq *) data;
5035 struct mii_data *mii;
5036 int flags, mask, error = 0;
5040 if (BGE_IS_JUMBO_CAPABLE(sc) ||
5041 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
5042 if (ifr->ifr_mtu < ETHERMIN ||
5043 ifr->ifr_mtu > BGE_JUMBO_MTU) {
5047 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) {
5052 if (ifp->if_mtu != ifr->ifr_mtu) {
5053 ifp->if_mtu = ifr->ifr_mtu;
5054 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5055 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5056 bge_init_locked(sc);
5063 if (ifp->if_flags & IFF_UP) {
5065 * If only the state of the PROMISC flag changed,
5066 * then just use the 'set promisc mode' command
5067 * instead of reinitializing the entire NIC. Doing
5068 * a full re-init means reloading the firmware and
5069 * waiting for it to start up, which may take a
5070 * second or two. Similarly for ALLMULTI.
5072 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5073 flags = ifp->if_flags ^ sc->bge_if_flags;
5074 if (flags & IFF_PROMISC)
5076 if (flags & IFF_ALLMULTI)
5079 bge_init_locked(sc);
5081 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5085 sc->bge_if_flags = ifp->if_flags;
5091 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5100 if (sc->bge_flags & BGE_FLAG_TBI) {
5101 error = ifmedia_ioctl(ifp, ifr,
5102 &sc->bge_ifmedia, command);
5104 mii = device_get_softc(sc->bge_miibus);
5105 error = ifmedia_ioctl(ifp, ifr,
5106 &mii->mii_media, command);
5110 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5111 #ifdef DEVICE_POLLING
5112 if (mask & IFCAP_POLLING) {
5113 if (ifr->ifr_reqcap & IFCAP_POLLING) {
5114 error = ether_poll_register(bge_poll, ifp);
5118 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5119 BGE_PCIMISCCTL_MASK_PCI_INTR);
5120 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5121 ifp->if_capenable |= IFCAP_POLLING;
5124 error = ether_poll_deregister(ifp);
5125 /* Enable interrupt even in error case */
5127 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
5128 BGE_PCIMISCCTL_MASK_PCI_INTR);
5129 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5130 ifp->if_capenable &= ~IFCAP_POLLING;
5135 if ((mask & IFCAP_TXCSUM) != 0 &&
5136 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
5137 ifp->if_capenable ^= IFCAP_TXCSUM;
5138 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
5139 ifp->if_hwassist |= sc->bge_csum_features;
5141 ifp->if_hwassist &= ~sc->bge_csum_features;
5144 if ((mask & IFCAP_RXCSUM) != 0 &&
5145 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
5146 ifp->if_capenable ^= IFCAP_RXCSUM;
5148 if ((mask & IFCAP_TSO4) != 0 &&
5149 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
5150 ifp->if_capenable ^= IFCAP_TSO4;
5151 if ((ifp->if_capenable & IFCAP_TSO4) != 0)
5152 ifp->if_hwassist |= CSUM_TSO;
5154 ifp->if_hwassist &= ~CSUM_TSO;
5157 if (mask & IFCAP_VLAN_MTU) {
5158 ifp->if_capenable ^= IFCAP_VLAN_MTU;
5159 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5163 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
5164 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
5165 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
5166 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
5167 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
5168 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
5169 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
5170 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
5175 #ifdef VLAN_CAPABILITIES
5176 VLAN_CAPABILITIES(ifp);
5180 error = ether_ioctl(ifp, command, data);
5188 bge_watchdog(struct bge_softc *sc)
5192 BGE_LOCK_ASSERT(sc);
5194 if (sc->bge_timer == 0 || --sc->bge_timer)
5199 if_printf(ifp, "watchdog timeout -- resetting\n");
5201 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5202 bge_init_locked(sc);
5208 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
5212 BGE_CLRBIT(sc, reg, bit);
5214 for (i = 0; i < BGE_TIMEOUT; i++) {
5215 if ((CSR_READ_4(sc, reg) & bit) == 0)
5222 * Stop the adapter and free any mbufs allocated to the
5226 bge_stop(struct bge_softc *sc)
5230 BGE_LOCK_ASSERT(sc);
5234 callout_stop(&sc->bge_stat_ch);
5236 /* Disable host interrupts. */
5237 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5238 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5241 * Tell firmware we're shutting down.
5244 bge_sig_pre_reset(sc, BGE_RESET_STOP);
5247 * Disable all of the receiver blocks.
5249 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
5250 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
5251 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
5252 if (BGE_IS_5700_FAMILY(sc))
5253 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
5254 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
5255 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
5256 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
5259 * Disable all of the transmit blocks.
5261 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
5262 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
5263 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
5264 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
5265 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
5266 if (BGE_IS_5700_FAMILY(sc))
5267 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
5268 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
5271 * Shut down all of the memory managers and related
5274 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
5275 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
5276 if (BGE_IS_5700_FAMILY(sc))
5277 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
5279 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
5280 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
5281 if (!(BGE_IS_5705_PLUS(sc))) {
5282 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
5283 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
5285 /* Update MAC statistics. */
5286 if (BGE_IS_5705_PLUS(sc))
5287 bge_stats_update_regs(sc);
5290 bge_sig_legacy(sc, BGE_RESET_STOP);
5291 bge_sig_post_reset(sc, BGE_RESET_STOP);
5294 * Keep the ASF firmware running if up.
5296 if (sc->bge_asf_mode & ASF_STACKUP)
5297 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5299 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5301 /* Free the RX lists. */
5302 bge_free_rx_ring_std(sc);
5304 /* Free jumbo RX list. */
5305 if (BGE_IS_JUMBO_CAPABLE(sc))
5306 bge_free_rx_ring_jumbo(sc);
5308 /* Free TX buffers. */
5309 bge_free_tx_ring(sc);
5311 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
5313 /* Clear MAC's link state (PHY may still have link UP). */
5314 if (bootverbose && sc->bge_link)
5315 if_printf(sc->bge_ifp, "link DOWN\n");
5318 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
5322 * Stop all chip I/O so that the kernel's probe routines don't
5323 * get confused by errant DMAs when rebooting.
5326 bge_shutdown(device_t dev)
5328 struct bge_softc *sc;
5330 sc = device_get_softc(dev);
5340 bge_suspend(device_t dev)
5342 struct bge_softc *sc;
5344 sc = device_get_softc(dev);
5353 bge_resume(device_t dev)
5355 struct bge_softc *sc;
5358 sc = device_get_softc(dev);
5361 if (ifp->if_flags & IFF_UP) {
5362 bge_init_locked(sc);
5363 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
5364 bge_start_locked(ifp);
5372 bge_link_upd(struct bge_softc *sc)
5374 struct mii_data *mii;
5375 uint32_t link, status;
5377 BGE_LOCK_ASSERT(sc);
5379 /* Clear 'pending link event' flag. */
5380 sc->bge_link_evt = 0;
5383 * Process link state changes.
5384 * Grrr. The link status word in the status block does
5385 * not work correctly on the BCM5700 rev AX and BX chips,
5386 * according to all available information. Hence, we have
5387 * to enable MII interrupts in order to properly obtain
5388 * async link changes. Unfortunately, this also means that
5389 * we have to read the MAC status register to detect link
5390 * changes, thereby adding an additional register access to
5391 * the interrupt handler.
5393 * XXX: perhaps link state detection procedure used for
5394 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
5397 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
5398 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
5399 status = CSR_READ_4(sc, BGE_MAC_STS);
5400 if (status & BGE_MACSTAT_MI_INTERRUPT) {
5401 mii = device_get_softc(sc->bge_miibus);
5403 if (!sc->bge_link &&
5404 mii->mii_media_status & IFM_ACTIVE &&
5405 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5408 if_printf(sc->bge_ifp, "link UP\n");
5409 } else if (sc->bge_link &&
5410 (!(mii->mii_media_status & IFM_ACTIVE) ||
5411 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
5414 if_printf(sc->bge_ifp, "link DOWN\n");
5417 /* Clear the interrupt. */
5418 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
5419 BGE_EVTENB_MI_INTERRUPT);
5420 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
5421 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
5427 if (sc->bge_flags & BGE_FLAG_TBI) {
5428 status = CSR_READ_4(sc, BGE_MAC_STS);
5429 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
5430 if (!sc->bge_link) {
5432 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
5433 BGE_CLRBIT(sc, BGE_MAC_MODE,
5434 BGE_MACMODE_TBI_SEND_CFGS);
5435 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
5437 if_printf(sc->bge_ifp, "link UP\n");
5438 if_link_state_change(sc->bge_ifp,
5441 } else if (sc->bge_link) {
5444 if_printf(sc->bge_ifp, "link DOWN\n");
5445 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
5447 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
5449 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
5450 * in status word always set. Workaround this bug by reading
5451 * PHY link status directly.
5453 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
5455 if (link != sc->bge_link ||
5456 sc->bge_asicrev == BGE_ASICREV_BCM5700) {
5457 mii = device_get_softc(sc->bge_miibus);
5459 if (!sc->bge_link &&
5460 mii->mii_media_status & IFM_ACTIVE &&
5461 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5464 if_printf(sc->bge_ifp, "link UP\n");
5465 } else if (sc->bge_link &&
5466 (!(mii->mii_media_status & IFM_ACTIVE) ||
5467 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
5470 if_printf(sc->bge_ifp, "link DOWN\n");
5475 * For controllers that call mii_tick, we have to poll
5478 mii = device_get_softc(sc->bge_miibus);
5480 bge_miibus_statchg(sc->bge_dev);
5483 /* Clear the attention. */
5484 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
5485 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
5486 BGE_MACSTAT_LINK_CHANGED);
5490 bge_add_sysctls(struct bge_softc *sc)
5492 struct sysctl_ctx_list *ctx;
5493 struct sysctl_oid_list *children;
5497 ctx = device_get_sysctl_ctx(sc->bge_dev);
5498 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
5500 #ifdef BGE_REGISTER_DEBUG
5501 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
5502 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
5503 "Debug Information");
5505 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
5506 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
5509 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
5510 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
5515 unit = device_get_unit(sc->bge_dev);
5517 * A common design characteristic for many Broadcom client controllers
5518 * is that they only support a single outstanding DMA read operation
5519 * on the PCIe bus. This means that it will take twice as long to fetch
5520 * a TX frame that is split into header and payload buffers as it does
5521 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
5522 * these controllers, coalescing buffers to reduce the number of memory
5523 * reads is effective way to get maximum performance(about 940Mbps).
5524 * Without collapsing TX buffers the maximum TCP bulk transfer
5525 * performance is about 850Mbps. However forcing coalescing mbufs
5526 * consumes a lot of CPU cycles, so leave it off by default.
5528 sc->bge_forced_collapse = 0;
5529 snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit);
5530 TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse);
5531 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
5532 CTLFLAG_RW, &sc->bge_forced_collapse, 0,
5533 "Number of fragmented TX buffers of a frame allowed before "
5534 "forced collapsing");
5537 * It seems all Broadcom controllers have a bug that can generate UDP
5538 * datagrams with checksum value 0 when TX UDP checksum offloading is
5539 * enabled. Generating UDP checksum value 0 is RFC 768 violation.
5540 * Even though the probability of generating such UDP datagrams is
5541 * low, I don't want to see FreeBSD boxes to inject such datagrams
5542 * into network so disable UDP checksum offloading by default. Users
5543 * still override this behavior by setting a sysctl variable,
5544 * dev.bge.0.forced_udpcsum.
5546 sc->bge_forced_udpcsum = 0;
5547 snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit);
5548 TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum);
5549 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum",
5550 CTLFLAG_RW, &sc->bge_forced_udpcsum, 0,
5551 "Enable UDP checksum offloading even if controller can "
5552 "generate UDP checksum value 0");
5554 if (BGE_IS_5705_PLUS(sc))
5555 bge_add_sysctl_stats_regs(sc, ctx, children);
5557 bge_add_sysctl_stats(sc, ctx, children);
5560 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
5561 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
5562 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
5566 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
5567 struct sysctl_oid_list *parent)
5569 struct sysctl_oid *tree;
5570 struct sysctl_oid_list *children, *schildren;
5572 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
5573 NULL, "BGE Statistics");
5574 schildren = children = SYSCTL_CHILDREN(tree);
5575 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
5576 children, COSFramesDroppedDueToFilters,
5577 "FramesDroppedDueToFilters");
5578 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
5579 children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
5580 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
5581 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
5582 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
5583 children, nicNoMoreRxBDs, "NoMoreRxBDs");
5584 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
5585 children, ifInDiscards, "InputDiscards");
5586 BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
5587 children, ifInErrors, "InputErrors");
5588 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
5589 children, nicRecvThresholdHit, "RecvThresholdHit");
5590 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
5591 children, nicDmaReadQueueFull, "DmaReadQueueFull");
5592 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
5593 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
5594 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
5595 children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
5596 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
5597 children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
5598 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
5599 children, nicRingStatusUpdate, "RingStatusUpdate");
5600 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
5601 children, nicInterrupts, "Interrupts");
5602 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
5603 children, nicAvoidedInterrupts, "AvoidedInterrupts");
5604 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
5605 children, nicSendThresholdHit, "SendThresholdHit");
5607 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
5608 NULL, "BGE RX Statistics");
5609 children = SYSCTL_CHILDREN(tree);
5610 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
5611 children, rxstats.ifHCInOctets, "ifHCInOctets");
5612 BGE_SYSCTL_STAT(sc, ctx, "Fragments",
5613 children, rxstats.etherStatsFragments, "Fragments");
5614 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
5615 children, rxstats.ifHCInUcastPkts, "UnicastPkts");
5616 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
5617 children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
5618 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
5619 children, rxstats.dot3StatsFCSErrors, "FCSErrors");
5620 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
5621 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
5622 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
5623 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
5624 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
5625 children, rxstats.xoffPauseFramesReceived,
5626 "xoffPauseFramesReceived");
5627 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
5628 children, rxstats.macControlFramesReceived,
5629 "ControlFramesReceived");
5630 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
5631 children, rxstats.xoffStateEntered, "xoffStateEntered");
5632 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
5633 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
5634 BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
5635 children, rxstats.etherStatsJabbers, "Jabbers");
5636 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
5637 children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
5638 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
5639 children, rxstats.inRangeLengthError, "inRangeLengthError");
5640 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
5641 children, rxstats.outRangeLengthError, "outRangeLengthError");
5643 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
5644 NULL, "BGE TX Statistics");
5645 children = SYSCTL_CHILDREN(tree);
5646 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
5647 children, txstats.ifHCOutOctets, "ifHCOutOctets");
5648 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
5649 children, txstats.etherStatsCollisions, "Collisions");
5650 BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
5651 children, txstats.outXonSent, "XonSent");
5652 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
5653 children, txstats.outXoffSent, "XoffSent");
5654 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
5655 children, txstats.flowControlDone, "flowControlDone");
5656 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
5657 children, txstats.dot3StatsInternalMacTransmitErrors,
5658 "InternalMacTransmitErrors");
5659 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
5660 children, txstats.dot3StatsSingleCollisionFrames,
5661 "SingleCollisionFrames");
5662 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
5663 children, txstats.dot3StatsMultipleCollisionFrames,
5664 "MultipleCollisionFrames");
5665 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
5666 children, txstats.dot3StatsDeferredTransmissions,
5667 "DeferredTransmissions");
5668 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
5669 children, txstats.dot3StatsExcessiveCollisions,
5670 "ExcessiveCollisions");
5671 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
5672 children, txstats.dot3StatsLateCollisions,
5674 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
5675 children, txstats.ifHCOutUcastPkts, "UnicastPkts");
5676 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
5677 children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
5678 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
5679 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
5680 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
5681 children, txstats.dot3StatsCarrierSenseErrors,
5682 "CarrierSenseErrors");
5683 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
5684 children, txstats.ifOutDiscards, "Discards");
5685 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
5686 children, txstats.ifOutErrors, "Errors");
5689 #undef BGE_SYSCTL_STAT
5691 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
5692 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
5695 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
5696 struct sysctl_oid_list *parent)
5698 struct sysctl_oid *tree;
5699 struct sysctl_oid_list *child, *schild;
5700 struct bge_mac_stats *stats;
5702 stats = &sc->bge_mac_stats;
5703 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
5704 NULL, "BGE Statistics");
5705 schild = child = SYSCTL_CHILDREN(tree);
5706 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters",
5707 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters");
5708 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull",
5709 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full");
5710 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull",
5711 &stats->DmaWriteHighPriQueueFull,
5712 "NIC DMA Write High Priority Queue Full");
5713 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs",
5714 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors");
5715 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards",
5716 &stats->InputDiscards, "Discarded Input Frames");
5717 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors",
5718 &stats->InputErrors, "Input Errors");
5719 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit",
5720 &stats->RecvThresholdHit, "NIC Recv Threshold Hit");
5722 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD,
5723 NULL, "BGE RX Statistics");
5724 child = SYSCTL_CHILDREN(tree);
5725 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets",
5726 &stats->ifHCInOctets, "Inbound Octets");
5727 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments",
5728 &stats->etherStatsFragments, "Fragments");
5729 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
5730 &stats->ifHCInUcastPkts, "Inbound Unicast Packets");
5731 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
5732 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets");
5733 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
5734 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets");
5735 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors",
5736 &stats->dot3StatsFCSErrors, "FCS Errors");
5737 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors",
5738 &stats->dot3StatsAlignmentErrors, "Alignment Errors");
5739 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived",
5740 &stats->xonPauseFramesReceived, "XON Pause Frames Received");
5741 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived",
5742 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received");
5743 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived",
5744 &stats->macControlFramesReceived, "MAC Control Frames Received");
5745 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered",
5746 &stats->xoffStateEntered, "XOFF State Entered");
5747 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong",
5748 &stats->dot3StatsFramesTooLong, "Frames Too Long");
5749 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers",
5750 &stats->etherStatsJabbers, "Jabbers");
5751 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts",
5752 &stats->etherStatsUndersizePkts, "Undersized Packets");
5754 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD,
5755 NULL, "BGE TX Statistics");
5756 child = SYSCTL_CHILDREN(tree);
5757 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets",
5758 &stats->ifHCOutOctets, "Outbound Octets");
5759 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions",
5760 &stats->etherStatsCollisions, "TX Collisions");
5761 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent",
5762 &stats->outXonSent, "XON Sent");
5763 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent",
5764 &stats->outXoffSent, "XOFF Sent");
5765 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors",
5766 &stats->dot3StatsInternalMacTransmitErrors,
5767 "Internal MAC TX Errors");
5768 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames",
5769 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames");
5770 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames",
5771 &stats->dot3StatsMultipleCollisionFrames,
5772 "Multiple Collision Frames");
5773 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions",
5774 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions");
5775 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions",
5776 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions");
5777 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions",
5778 &stats->dot3StatsLateCollisions, "Late Collisions");
5779 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
5780 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets");
5781 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
5782 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets");
5783 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
5784 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets");
5787 #undef BGE_SYSCTL_STAT_ADD64
5790 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
5792 struct bge_softc *sc;
5796 sc = (struct bge_softc *)arg1;
5798 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
5799 offsetof(bge_hostaddr, bge_addr_lo));
5800 return (sysctl_handle_int(oidp, &result, 0, req));
5803 #ifdef BGE_REGISTER_DEBUG
5805 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
5807 struct bge_softc *sc;
5809 int error, result, sbsz;
5813 error = sysctl_handle_int(oidp, &result, 0, req);
5814 if (error || (req->newptr == NULL))
5818 sc = (struct bge_softc *)arg1;
5820 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
5821 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
5822 sbsz = BGE_STATUS_BLK_SZ;
5825 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
5826 printf("Status Block:\n");
5828 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
5829 sc->bge_cdata.bge_status_map,
5830 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
5831 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) {
5833 for (j = 0; j < 8; j++)
5834 printf(" %04x", sbdata[i++]);
5838 printf("Registers:\n");
5839 for (i = 0x800; i < 0xA00; ) {
5841 for (j = 0; j < 8; j++) {
5842 printf(" %08x", CSR_READ_4(sc, i));
5849 printf("Hardware Flags:\n");
5850 if (BGE_IS_5717_PLUS(sc))
5851 printf(" - 5717 Plus\n");
5852 if (BGE_IS_5755_PLUS(sc))
5853 printf(" - 5755 Plus\n");
5854 if (BGE_IS_575X_PLUS(sc))
5855 printf(" - 575X Plus\n");
5856 if (BGE_IS_5705_PLUS(sc))
5857 printf(" - 5705 Plus\n");
5858 if (BGE_IS_5714_FAMILY(sc))
5859 printf(" - 5714 Family\n");
5860 if (BGE_IS_5700_FAMILY(sc))
5861 printf(" - 5700 Family\n");
5862 if (sc->bge_flags & BGE_FLAG_JUMBO)
5863 printf(" - Supports Jumbo Frames\n");
5864 if (sc->bge_flags & BGE_FLAG_PCIX)
5865 printf(" - PCI-X Bus\n");
5866 if (sc->bge_flags & BGE_FLAG_PCIE)
5867 printf(" - PCI Express Bus\n");
5868 if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
5869 printf(" - No 3 LEDs\n");
5870 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
5871 printf(" - RX Alignment Bug\n");
5878 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5880 struct bge_softc *sc;
5886 error = sysctl_handle_int(oidp, &result, 0, req);
5887 if (error || (req->newptr == NULL))
5890 if (result < 0x8000) {
5891 sc = (struct bge_softc *)arg1;
5892 val = CSR_READ_4(sc, result);
5893 printf("reg 0x%06X = 0x%08X\n", result, val);
5900 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
5902 struct bge_softc *sc;
5908 error = sysctl_handle_int(oidp, &result, 0, req);
5909 if (error || (req->newptr == NULL))
5912 if (result < 0x8000) {
5913 sc = (struct bge_softc *)arg1;
5914 val = bge_readmem_ind(sc, result);
5915 printf("mem 0x%06X = 0x%08X\n", result, val);
5923 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
5926 if (sc->bge_flags & BGE_FLAG_EADDR)
5930 OF_getetheraddr(sc->bge_dev, ether_addr);
5937 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
5941 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
5942 if ((mac_addr >> 16) == 0x484b) {
5943 ether_addr[0] = (uint8_t)(mac_addr >> 8);
5944 ether_addr[1] = (uint8_t)mac_addr;
5945 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
5946 ether_addr[2] = (uint8_t)(mac_addr >> 24);
5947 ether_addr[3] = (uint8_t)(mac_addr >> 16);
5948 ether_addr[4] = (uint8_t)(mac_addr >> 8);
5949 ether_addr[5] = (uint8_t)mac_addr;
5956 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
5958 int mac_offset = BGE_EE_MAC_OFFSET;
5960 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
5961 mac_offset = BGE_EE_MAC_OFFSET_5906;
5963 return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
5968 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
5971 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
5974 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
5979 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
5981 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
5982 /* NOTE: Order is critical */
5985 bge_get_eaddr_nvram,
5986 bge_get_eaddr_eeprom,
5989 const bge_eaddr_fcn_t *func;
5991 for (func = bge_eaddr_funcs; *func != NULL; ++func) {
5992 if ((*func)(sc, eaddr) == 0)
5995 return (*func == NULL ? ENXIO : 0);