sys/dev/bge/if_bge.c

   1 /*-
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/cdefs.h>
  35 __FBSDID("$FreeBSD$");
  36
  37 /*
  38  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  39  *
  40  * The Broadcom BCM5700 is based on technology originally developed by
  41  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  42  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  43  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  44  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  45  * frames, highly configurable RX filtering, and 16 RX and TX queues
  46  * (which, along with RX filter rules, can be used for QOS applications).
  47  * Other features, such as TCP segmentation, may be available as part
  48  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  49  * firmware images can be stored in hardware and need not be compiled
  50  * into the driver.
  51  *
  52  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  53  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  54  *
  55  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  56  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  57  * does not support external SSRAM.
  58  *
  59  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  60  * brand name, which is functionally similar but lacks PCI-X support.
  61  *
  62  * Without external SSRAM, you can only have at most 4 TX rings,
  63  * and the use of the mini RX ring is disabled. This seems to imply
  64  * that these features are simply not available on the BCM5701. As a
  65  * result, this driver does not implement any support for the mini RX
  66  * ring.
  67  */
  68
  69 #ifdef HAVE_KERNEL_OPTION_HEADERS
  70 #include "opt_device_polling.h"
  71 #endif
  72
  73 #include <sys/param.h>
  74 #include <sys/endian.h>
  75 #include <sys/systm.h>
  76 #include <sys/sockio.h>
  77 #include <sys/mbuf.h>
  78 #include <sys/malloc.h>
  79 #include <sys/kernel.h>
  80 #include <sys/module.h>
  81 #include <sys/socket.h>
  82 #include <sys/sysctl.h>
  83 #include <sys/taskqueue.h>
  84
  85 #include <net/if.h>
  86 #include <net/if_arp.h>
  87 #include <net/ethernet.h>
  88 #include <net/if_dl.h>
  89 #include <net/if_media.h>
  90
  91 #include <net/bpf.h>
  92
  93 #include <net/if_types.h>
  94 #include <net/if_vlan_var.h>
  95
  96 #include <netinet/in_systm.h>
  97 #include <netinet/in.h>
  98 #include <netinet/ip.h>
  99 #include <netinet/tcp.h>
 100
 101 #include <machine/bus.h>
 102 #include <machine/resource.h>
 103 #include <sys/bus.h>
 104 #include <sys/rman.h>
 105
 106 #include <dev/mii/mii.h>
 107 #include <dev/mii/miivar.h>
 108 #include "miidevs.h"
 109 #include <dev/mii/brgphyreg.h>
 110
 111 #ifdef __sparc64__
 112 #include <dev/ofw/ofw_bus.h>
 113 #include <dev/ofw/openfirm.h>
 114 #include <machine/ofw_machdep.h>
 115 #include <machine/ver.h>
 116 #endif
 117
 118 #include <dev/pci/pcireg.h>
 119 #include <dev/pci/pcivar.h>
 120
 121 #include <dev/bge/if_bgereg.h>
 122
 123 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 124 #define ETHER_MIN_NOPAD         (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
 125
 126 MODULE_DEPEND(bge, pci, 1, 1, 1);
 127 MODULE_DEPEND(bge, ether, 1, 1, 1);
 128 MODULE_DEPEND(bge, miibus, 1, 1, 1);
 129
 130 /* "device miibus" required.  See GENERIC if you get errors here. */
 131 #include "miibus_if.h"
 132
 133 /*
 134  * Various supported device vendors/types and their names. Note: the
 135  * spec seems to indicate that the hardware still has Alteon's vendor
 136  * ID burned into it, though it will always be overriden by the vendor
 137  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 138  */
 139 static const struct bge_type {
 140         uint16_t        bge_vid;
 141         uint16_t        bge_did;
 142 } bge_devs[] = {
 143         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5700 },
 144         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5701 },
 145
 146         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1000 },
 147         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1002 },
 148         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC9100 },
 149
 150         { APPLE_VENDORID,       APPLE_DEVICE_BCM5701 },
 151
 152         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5700 },
 153         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5701 },
 154         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702 },
 155         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702_ALT },
 156         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702X },
 157         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703 },
 158         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703_ALT },
 159         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703X },
 160         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704C },
 161         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S },
 162         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S_ALT },
 163         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705 },
 164         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705F },
 165         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705K },
 166         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M },
 167         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M_ALT },
 168         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714C },
 169         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714S },
 170         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715 },
 171         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715S },
 172         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5720 },
 173         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5721 },
 174         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5722 },
 175         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5723 },
 176         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750 },
 177         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750M },
 178         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751 },
 179         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751F },
 180         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751M },
 181         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752 },
 182         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752M },
 183         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753 },
 184         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753F },
 185         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753M },
 186         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754 },
 187         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754M },
 188         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755 },
 189         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755M },
 190         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5756 },
 191         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761 },
 192         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761E },
 193         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761S },
 194         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761SE },
 195         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5764 },
 196         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780 },
 197         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780S },
 198         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5781 },
 199         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5782 },
 200         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5784 },
 201         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785F },
 202         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785G },
 203         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5786 },
 204         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787 },
 205         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787F },
 206         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787M },
 207         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5788 },
 208         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5789 },
 209         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901 },
 210         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901A2 },
 211         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5903M },
 212         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906 },
 213         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906M },
 214         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57760 },
 215         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57780 },
 216         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57788 },
 217         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57790 },
 218
 219         { SK_VENDORID,          SK_DEVICEID_ALTIMA },
 220
 221         { TC_VENDORID,          TC_DEVICEID_3C996 },
 222
 223         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE4 },
 224         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE5 },
 225         { FJTSU_VENDORID,       FJTSU_DEVICEID_PP250450 },
 226
 227         { 0, 0 }
 228 };
 229
 230 static const struct bge_vendor {
 231         uint16_t        v_id;
 232         const char      *v_name;
 233 } bge_vendors[] = {
 234         { ALTEON_VENDORID,      "Alteon" },
 235         { ALTIMA_VENDORID,      "Altima" },
 236         { APPLE_VENDORID,       "Apple" },
 237         { BCOM_VENDORID,        "Broadcom" },
 238         { SK_VENDORID,          "SysKonnect" },
 239         { TC_VENDORID,          "3Com" },
 240         { FJTSU_VENDORID,       "Fujitsu" },
 241
 242         { 0, NULL }
 243 };
 244
 245 static const struct bge_revision {
 246         uint32_t        br_chipid;
 247         const char      *br_name;
 248 } bge_revisions[] = {
 249         { BGE_CHIPID_BCM5700_A0,        "BCM5700 A0" },
 250         { BGE_CHIPID_BCM5700_A1,        "BCM5700 A1" },
 251         { BGE_CHIPID_BCM5700_B0,        "BCM5700 B0" },
 252         { BGE_CHIPID_BCM5700_B1,        "BCM5700 B1" },
 253         { BGE_CHIPID_BCM5700_B2,        "BCM5700 B2" },
 254         { BGE_CHIPID_BCM5700_B3,        "BCM5700 B3" },
 255         { BGE_CHIPID_BCM5700_ALTIMA,    "BCM5700 Altima" },
 256         { BGE_CHIPID_BCM5700_C0,        "BCM5700 C0" },
 257         { BGE_CHIPID_BCM5701_A0,        "BCM5701 A0" },
 258         { BGE_CHIPID_BCM5701_B0,        "BCM5701 B0" },
 259         { BGE_CHIPID_BCM5701_B2,        "BCM5701 B2" },
 260         { BGE_CHIPID_BCM5701_B5,        "BCM5701 B5" },
 261         { BGE_CHIPID_BCM5703_A0,        "BCM5703 A0" },
 262         { BGE_CHIPID_BCM5703_A1,        "BCM5703 A1" },
 263         { BGE_CHIPID_BCM5703_A2,        "BCM5703 A2" },
 264         { BGE_CHIPID_BCM5703_A3,        "BCM5703 A3" },
 265         { BGE_CHIPID_BCM5703_B0,        "BCM5703 B0" },
 266         { BGE_CHIPID_BCM5704_A0,        "BCM5704 A0" },
 267         { BGE_CHIPID_BCM5704_A1,        "BCM5704 A1" },
 268         { BGE_CHIPID_BCM5704_A2,        "BCM5704 A2" },
 269         { BGE_CHIPID_BCM5704_A3,        "BCM5704 A3" },
 270         { BGE_CHIPID_BCM5704_B0,        "BCM5704 B0" },
 271         { BGE_CHIPID_BCM5705_A0,        "BCM5705 A0" },
 272         { BGE_CHIPID_BCM5705_A1,        "BCM5705 A1" },
 273         { BGE_CHIPID_BCM5705_A2,        "BCM5705 A2" },
 274         { BGE_CHIPID_BCM5705_A3,        "BCM5705 A3" },
 275         { BGE_CHIPID_BCM5750_A0,        "BCM5750 A0" },
 276         { BGE_CHIPID_BCM5750_A1,        "BCM5750 A1" },
 277         { BGE_CHIPID_BCM5750_A3,        "BCM5750 A3" },
 278         { BGE_CHIPID_BCM5750_B0,        "BCM5750 B0" },
 279         { BGE_CHIPID_BCM5750_B1,        "BCM5750 B1" },
 280         { BGE_CHIPID_BCM5750_C0,        "BCM5750 C0" },
 281         { BGE_CHIPID_BCM5750_C1,        "BCM5750 C1" },
 282         { BGE_CHIPID_BCM5750_C2,        "BCM5750 C2" },
 283         { BGE_CHIPID_BCM5714_A0,        "BCM5714 A0" },
 284         { BGE_CHIPID_BCM5752_A0,        "BCM5752 A0" },
 285         { BGE_CHIPID_BCM5752_A1,        "BCM5752 A1" },
 286         { BGE_CHIPID_BCM5752_A2,        "BCM5752 A2" },
 287         { BGE_CHIPID_BCM5714_B0,        "BCM5714 B0" },
 288         { BGE_CHIPID_BCM5714_B3,        "BCM5714 B3" },
 289         { BGE_CHIPID_BCM5715_A0,        "BCM5715 A0" },
 290         { BGE_CHIPID_BCM5715_A1,        "BCM5715 A1" },
 291         { BGE_CHIPID_BCM5715_A3,        "BCM5715 A3" },
 292         { BGE_CHIPID_BCM5755_A0,        "BCM5755 A0" },
 293         { BGE_CHIPID_BCM5755_A1,        "BCM5755 A1" },
 294         { BGE_CHIPID_BCM5755_A2,        "BCM5755 A2" },
 295         { BGE_CHIPID_BCM5722_A0,        "BCM5722 A0" },
 296         { BGE_CHIPID_BCM5761_A0,        "BCM5761 A0" },
 297         { BGE_CHIPID_BCM5761_A1,        "BCM5761 A1" },
 298         { BGE_CHIPID_BCM5784_A0,        "BCM5784 A0" },
 299         { BGE_CHIPID_BCM5784_A1,        "BCM5784 A1" },
 300         /* 5754 and 5787 share the same ASIC ID */
 301         { BGE_CHIPID_BCM5787_A0,        "BCM5754/5787 A0" },
 302         { BGE_CHIPID_BCM5787_A1,        "BCM5754/5787 A1" },
 303         { BGE_CHIPID_BCM5787_A2,        "BCM5754/5787 A2" },
 304         { BGE_CHIPID_BCM5906_A1,        "BCM5906 A1" },
 305         { BGE_CHIPID_BCM5906_A2,        "BCM5906 A2" },
 306         { BGE_CHIPID_BCM57780_A0,       "BCM57780 A0" },
 307         { BGE_CHIPID_BCM57780_A1,       "BCM57780 A1" },
 308
 309         { 0, NULL }
 310 };
 311
 312 /*
 313  * Some defaults for major revisions, so that newer steppings
 314  * that we don't know about have a shot at working.
 315  */
 316 static const struct bge_revision bge_majorrevs[] = {
 317         { BGE_ASICREV_BCM5700,          "unknown BCM5700" },
 318         { BGE_ASICREV_BCM5701,          "unknown BCM5701" },
 319         { BGE_ASICREV_BCM5703,          "unknown BCM5703" },
 320         { BGE_ASICREV_BCM5704,          "unknown BCM5704" },
 321         { BGE_ASICREV_BCM5705,          "unknown BCM5705" },
 322         { BGE_ASICREV_BCM5750,          "unknown BCM5750" },
 323         { BGE_ASICREV_BCM5714_A0,       "unknown BCM5714" },
 324         { BGE_ASICREV_BCM5752,          "unknown BCM5752" },
 325         { BGE_ASICREV_BCM5780,          "unknown BCM5780" },
 326         { BGE_ASICREV_BCM5714,          "unknown BCM5714" },
 327         { BGE_ASICREV_BCM5755,          "unknown BCM5755" },
 328         { BGE_ASICREV_BCM5761,          "unknown BCM5761" },
 329         { BGE_ASICREV_BCM5784,          "unknown BCM5784" },
 330         { BGE_ASICREV_BCM5785,          "unknown BCM5785" },
 331         /* 5754 and 5787 share the same ASIC ID */
 332         { BGE_ASICREV_BCM5787,          "unknown BCM5754/5787" },
 333         { BGE_ASICREV_BCM5906,          "unknown BCM5906" },
 334         { BGE_ASICREV_BCM57780,         "unknown BCM57780" },
 335
 336         { 0, NULL }
 337 };
 338
 339 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 340 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 341 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 342 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 343 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 344 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 345
 346 const struct bge_revision * bge_lookup_rev(uint32_t);
 347 const struct bge_vendor * bge_lookup_vendor(uint16_t);
 348
 349 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 350
 351 static int bge_probe(device_t);
 352 static int bge_attach(device_t);
 353 static int bge_detach(device_t);
 354 static int bge_suspend(device_t);
 355 static int bge_resume(device_t);
 356 static void bge_release_resources(struct bge_softc *);
 357 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 358 static int bge_dma_alloc(device_t);
 359 static void bge_dma_free(struct bge_softc *);
 360
 361 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
 362 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 363 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 364 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 365 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
 366
 367 static void bge_txeof(struct bge_softc *, uint16_t);
 368 static int bge_rxeof(struct bge_softc *, uint16_t, int);
 369
 370 static void bge_asf_driver_up (struct bge_softc *);
 371 static void bge_tick(void *);
 372 static void bge_stats_update(struct bge_softc *);
 373 static void bge_stats_update_regs(struct bge_softc *);
 374 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
 375     uint16_t *);
 376 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 377
 378 static void bge_intr(void *);
 379 static int bge_msi_intr(void *);
 380 static void bge_intr_task(void *, int);
 381 static void bge_start_locked(struct ifnet *);
 382 static void bge_start(struct ifnet *);
 383 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
 384 static void bge_init_locked(struct bge_softc *);
 385 static void bge_init(void *);
 386 static void bge_stop(struct bge_softc *);
 387 static void bge_watchdog(struct bge_softc *);
 388 static int bge_shutdown(device_t);
 389 static int bge_ifmedia_upd_locked(struct ifnet *);
 390 static int bge_ifmedia_upd(struct ifnet *);
 391 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 392
 393 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 394 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 395
 396 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
 397 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
 398
 399 static void bge_setpromisc(struct bge_softc *);
 400 static void bge_setmulti(struct bge_softc *);
 401 static void bge_setvlan(struct bge_softc *);
 402
 403 static int bge_newbuf_std(struct bge_softc *, int);
 404 static int bge_newbuf_jumbo(struct bge_softc *, int);
 405 static int bge_init_rx_ring_std(struct bge_softc *);
 406 static void bge_free_rx_ring_std(struct bge_softc *);
 407 static int bge_init_rx_ring_jumbo(struct bge_softc *);
 408 static void bge_free_rx_ring_jumbo(struct bge_softc *);
 409 static void bge_free_tx_ring(struct bge_softc *);
 410 static int bge_init_tx_ring(struct bge_softc *);
 411
 412 static int bge_chipinit(struct bge_softc *);
 413 static int bge_blockinit(struct bge_softc *);
 414
 415 static int bge_has_eaddr(struct bge_softc *);
 416 static uint32_t bge_readmem_ind(struct bge_softc *, int);
 417 static void bge_writemem_ind(struct bge_softc *, int, int);
 418 static void bge_writembx(struct bge_softc *, int, int);
 419 #ifdef notdef
 420 static uint32_t bge_readreg_ind(struct bge_softc *, int);
 421 #endif
 422 static void bge_writemem_direct(struct bge_softc *, int, int);
 423 static void bge_writereg_ind(struct bge_softc *, int, int);
 424
 425 static int bge_miibus_readreg(device_t, int, int);
 426 static int bge_miibus_writereg(device_t, int, int, int);
 427 static void bge_miibus_statchg(device_t);
 428 #ifdef DEVICE_POLLING
 429 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 430 #endif
 431
 432 #define BGE_RESET_START 1
 433 #define BGE_RESET_STOP  2
 434 static void bge_sig_post_reset(struct bge_softc *, int);
 435 static void bge_sig_legacy(struct bge_softc *, int);
 436 static void bge_sig_pre_reset(struct bge_softc *, int);
 437 static int bge_reset(struct bge_softc *);
 438 static void bge_link_upd(struct bge_softc *);
 439
 440 /*
 441  * The BGE_REGISTER_DEBUG option is only for low-level debugging.  It may
 442  * leak information to untrusted users.  It is also known to cause alignment
 443  * traps on certain architectures.
 444  */
 445 #ifdef BGE_REGISTER_DEBUG
 446 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 447 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
 448 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
 449 #endif
 450 static void bge_add_sysctls(struct bge_softc *);
 451 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
 452
 453 static device_method_t bge_methods[] = {
 454         /* Device interface */
 455         DEVMETHOD(device_probe,         bge_probe),
 456         DEVMETHOD(device_attach,        bge_attach),
 457         DEVMETHOD(device_detach,        bge_detach),
 458         DEVMETHOD(device_shutdown,      bge_shutdown),
 459         DEVMETHOD(device_suspend,       bge_suspend),
 460         DEVMETHOD(device_resume,        bge_resume),
 461
 462         /* bus interface */
 463         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 464         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 465
 466         /* MII interface */
 467         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 468         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 469         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 470
 471         { 0, 0 }
 472 };
 473
 474 static driver_t bge_driver = {
 475         "bge",
 476         bge_methods,
 477         sizeof(struct bge_softc)
 478 };
 479
 480 static devclass_t bge_devclass;
 481
 482 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
 483 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 484
 485 static int bge_allow_asf = 1;
 486
 487 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
 488
 489 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
 490 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
 491         "Allow ASF mode if available");
 492
 493 #define SPARC64_BLADE_1500_MODEL        "SUNW,Sun-Blade-1500"
 494 #define SPARC64_BLADE_1500_PATH_BGE     "/pci@1f,700000/network@2"
 495 #define SPARC64_BLADE_2500_MODEL        "SUNW,Sun-Blade-2500"
 496 #define SPARC64_BLADE_2500_PATH_BGE     "/pci@1c,600000/network@3"
 497 #define SPARC64_OFW_SUBVENDOR           "subsystem-vendor-id"
 498
 499 static int
 500 bge_has_eaddr(struct bge_softc *sc)
 501 {
 502 #ifdef __sparc64__
 503         char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
 504         device_t dev;
 505         uint32_t subvendor;
 506
 507         dev = sc->bge_dev;
 508
 509         /*
 510          * The on-board BGEs found in sun4u machines aren't fitted with
 511          * an EEPROM which means that we have to obtain the MAC address
 512          * via OFW and that some tests will always fail.  We distinguish
 513          * such BGEs by the subvendor ID, which also has to be obtained
 514          * from OFW instead of the PCI configuration space as the latter
 515          * indicates Broadcom as the subvendor of the netboot interface.
 516          * For early Blade 1500 and 2500 we even have to check the OFW
 517          * device path as the subvendor ID always defaults to Broadcom
 518          * there.
 519          */
 520         if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
 521             &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
 522             (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID))
 523                 return (0);
 524         memset(buf, 0, sizeof(buf));
 525         if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
 526                 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
 527                     strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
 528                         return (0);
 529                 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
 530                     strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
 531                         return (0);
 532         }
 533 #endif
 534         return (1);
 535 }
 536
 537 static uint32_t
 538 bge_readmem_ind(struct bge_softc *sc, int off)
 539 {
 540         device_t dev;
 541         uint32_t val;
 542
 543         dev = sc->bge_dev;
 544
 545         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 546         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 547         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 548         return (val);
 549 }
 550
 551 static void
 552 bge_writemem_ind(struct bge_softc *sc, int off, int val)
 553 {
 554         device_t dev;
 555
 556         dev = sc->bge_dev;
 557
 558         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 559         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 560         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 561 }
 562
 563 #ifdef notdef
 564 static uint32_t
 565 bge_readreg_ind(struct bge_softc *sc, int off)
 566 {
 567         device_t dev;
 568
 569         dev = sc->bge_dev;
 570
 571         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 572         return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 573 }
 574 #endif
 575
 576 static void
 577 bge_writereg_ind(struct bge_softc *sc, int off, int val)
 578 {
 579         device_t dev;
 580
 581         dev = sc->bge_dev;
 582
 583         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 584         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 585 }
 586
 587 static void
 588 bge_writemem_direct(struct bge_softc *sc, int off, int val)
 589 {
 590         CSR_WRITE_4(sc, off, val);
 591 }
 592
 593 static void
 594 bge_writembx(struct bge_softc *sc, int off, int val)
 595 {
 596         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 597                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 598
 599         CSR_WRITE_4(sc, off, val);
 600 }
 601
 602 /*
 603  * Map a single buffer address.
 604  */
 605
 606 static void
 607 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 608 {
 609         struct bge_dmamap_arg *ctx;
 610
 611         if (error)
 612                 return;
 613
 614         ctx = arg;
 615
 616         if (nseg > ctx->bge_maxsegs) {
 617                 ctx->bge_maxsegs = 0;
 618                 return;
 619         }
 620
 621         ctx->bge_busaddr = segs->ds_addr;
 622 }
 623
 624 static uint8_t
 625 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 626 {
 627         uint32_t access, byte = 0;
 628         int i;
 629
 630         /* Lock. */
 631         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 632         for (i = 0; i < 8000; i++) {
 633                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 634                         break;
 635                 DELAY(20);
 636         }
 637         if (i == 8000)
 638                 return (1);
 639
 640         /* Enable access. */
 641         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 642         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 643
 644         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 645         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 646         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 647                 DELAY(10);
 648                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 649                         DELAY(10);
 650                         break;
 651                 }
 652         }
 653
 654         if (i == BGE_TIMEOUT * 10) {
 655                 if_printf(sc->bge_ifp, "nvram read timed out\n");
 656                 return (1);
 657         }
 658
 659         /* Get result. */
 660         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 661
 662         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 663
 664         /* Disable access. */
 665         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 666
 667         /* Unlock. */
 668         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 669         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 670
 671         return (0);
 672 }
 673
 674 /*
 675  * Read a sequence of bytes from NVRAM.
 676  */
 677 static int
 678 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 679 {
 680         int err = 0, i;
 681         uint8_t byte = 0;
 682
 683         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 684                 return (1);
 685
 686         for (i = 0; i < cnt; i++) {
 687                 err = bge_nvram_getbyte(sc, off + i, &byte);
 688                 if (err)
 689                         break;
 690                 *(dest + i) = byte;
 691         }
 692
 693         return (err ? 1 : 0);
 694 }
 695
 696 /*
 697  * Read a byte of data stored in the EEPROM at address 'addr.' The
 698  * BCM570x supports both the traditional bitbang interface and an
 699  * auto access interface for reading the EEPROM. We use the auto
 700  * access method.
 701  */
 702 static uint8_t
 703 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 704 {
 705         int i;
 706         uint32_t byte = 0;
 707
 708         /*
 709          * Enable use of auto EEPROM access so we can avoid
 710          * having to use the bitbang method.
 711          */
 712         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 713
 714         /* Reset the EEPROM, load the clock period. */
 715         CSR_WRITE_4(sc, BGE_EE_ADDR,
 716             BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 717         DELAY(20);
 718
 719         /* Issue the read EEPROM command. */
 720         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 721
 722         /* Wait for completion */
 723         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 724                 DELAY(10);
 725                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 726                         break;
 727         }
 728
 729         if (i == BGE_TIMEOUT * 10) {
 730                 device_printf(sc->bge_dev, "EEPROM read timed out\n");
 731                 return (1);
 732         }
 733
 734         /* Get result. */
 735         byte = CSR_READ_4(sc, BGE_EE_DATA);
 736
 737         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 738
 739         return (0);
 740 }
 741
 742 /*
 743  * Read a sequence of bytes from the EEPROM.
 744  */
 745 static int
 746 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 747 {
 748         int i, error = 0;
 749         uint8_t byte = 0;
 750
 751         for (i = 0; i < cnt; i++) {
 752                 error = bge_eeprom_getbyte(sc, off + i, &byte);
 753                 if (error)
 754                         break;
 755                 *(dest + i) = byte;
 756         }
 757
 758         return (error ? 1 : 0);
 759 }
 760
 761 static int
 762 bge_miibus_readreg(device_t dev, int phy, int reg)
 763 {
 764         struct bge_softc *sc;
 765         uint32_t val, autopoll;
 766         int i;
 767
 768         sc = device_get_softc(dev);
 769
 770         /*
 771          * Broadcom's own driver always assumes the internal
 772          * PHY is at GMII address 1. On some chips, the PHY responds
 773          * to accesses at all addresses, which could cause us to
 774          * bogusly attach the PHY 32 times at probe type. Always
 775          * restricting the lookup to address 1 is simpler than
 776          * trying to figure out which chips revisions should be
 777          * special-cased.
 778          */
 779         if (phy != 1)
 780                 return (0);
 781
 782         /* Reading with autopolling on may trigger PCI errors */
 783         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 784         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 785                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 786                 DELAY(40);
 787         }
 788
 789         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 790             BGE_MIPHY(phy) | BGE_MIREG(reg));
 791
 792         for (i = 0; i < BGE_TIMEOUT; i++) {
 793                 DELAY(10);
 794                 val = CSR_READ_4(sc, BGE_MI_COMM);
 795                 if (!(val & BGE_MICOMM_BUSY))
 796                         break;
 797         }
 798
 799         if (i == BGE_TIMEOUT) {
 800                 device_printf(sc->bge_dev,
 801                     "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
 802                     phy, reg, val);
 803                 val = 0;
 804                 goto done;
 805         }
 806
 807         DELAY(5);
 808         val = CSR_READ_4(sc, BGE_MI_COMM);
 809
 810 done:
 811         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 812                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 813                 DELAY(40);
 814         }
 815
 816         if (val & BGE_MICOMM_READFAIL)
 817                 return (0);
 818
 819         return (val & 0xFFFF);
 820 }
 821
 822 static int
 823 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 824 {
 825         struct bge_softc *sc;
 826         uint32_t autopoll;
 827         int i;
 828
 829         sc = device_get_softc(dev);
 830
 831         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 832             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 833                 return(0);
 834
 835         /* Reading with autopolling on may trigger PCI errors */
 836         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 837         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 838                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 839                 DELAY(40);
 840         }
 841
 842         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 843             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 844
 845         for (i = 0; i < BGE_TIMEOUT; i++) {
 846                 DELAY(10);
 847                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 848                         DELAY(5);
 849                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 850                         break;
 851                 }
 852         }
 853
 854         if (i == BGE_TIMEOUT) {
 855                 device_printf(sc->bge_dev,
 856                     "PHY write timed out (phy %d, reg %d, val %d)\n",
 857                     phy, reg, val);
 858                 return (0);
 859         }
 860
 861         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 862                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 863                 DELAY(40);
 864         }
 865
 866         return (0);
 867 }
 868
 869 static void
 870 bge_miibus_statchg(device_t dev)
 871 {
 872         struct bge_softc *sc;
 873         struct mii_data *mii;
 874         sc = device_get_softc(dev);
 875         mii = device_get_softc(sc->bge_miibus);
 876
 877         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 878         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 879             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
 880                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 881         else
 882                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 883
 884         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
 885                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 886         else
 887                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 888 }
 889
 890 /*
 891  * Intialize a standard receive ring descriptor.
 892  */
 893 static int
 894 bge_newbuf_std(struct bge_softc *sc, int i)
 895 {
 896         struct mbuf *m;
 897         struct bge_rx_bd *r;
 898         bus_dma_segment_t segs[1];
 899         bus_dmamap_t map;
 900         int error, nsegs;
 901
 902         m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
 903         if (m == NULL)
 904                 return (ENOBUFS);
 905         m->m_len = m->m_pkthdr.len = MCLBYTES;
 906         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 907                 m_adj(m, ETHER_ALIGN);
 908
 909         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
 910             sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
 911         if (error != 0) {
 912                 m_freem(m);
 913                 return (error);
 914         }
 915         if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 916                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 917                     sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
 918                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 919                     sc->bge_cdata.bge_rx_std_dmamap[i]);
 920         }
 921         map = sc->bge_cdata.bge_rx_std_dmamap[i];
 922         sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
 923         sc->bge_cdata.bge_rx_std_sparemap = map;
 924         sc->bge_cdata.bge_rx_std_chain[i] = m;
 925         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
 926         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
 927         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
 928         r->bge_flags = BGE_RXBDFLAG_END;
 929         r->bge_len = segs[0].ds_len;
 930         r->bge_idx = i;
 931
 932         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 933             sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
 934
 935         return (0);
 936 }
 937
 938 /*
 939  * Initialize a jumbo receive ring descriptor. This allocates
 940  * a jumbo buffer from the pool managed internally by the driver.
 941  */
 942 static int
 943 bge_newbuf_jumbo(struct bge_softc *sc, int i)
 944 {
 945         bus_dma_segment_t segs[BGE_NSEG_JUMBO];
 946         bus_dmamap_t map;
 947         struct bge_extrx_bd *r;
 948         struct mbuf *m;
 949         int error, nsegs;
 950
 951         MGETHDR(m, M_DONTWAIT, MT_DATA);
 952         if (m == NULL)
 953                 return (ENOBUFS);
 954
 955         m_cljget(m, M_DONTWAIT, MJUM9BYTES);
 956         if (!(m->m_flags & M_EXT)) {
 957                 m_freem(m);
 958                 return (ENOBUFS);
 959         }
 960         m->m_len = m->m_pkthdr.len = MJUM9BYTES;
 961         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 962                 m_adj(m, ETHER_ALIGN);
 963
 964         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
 965             sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
 966         if (error != 0) {
 967                 m_freem(m);
 968                 return (error);
 969         }
 970
 971         if (sc->bge_cdata.bge_rx_jumbo_chain[i] == NULL) {
 972                 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
 973                     sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
 974                 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
 975                     sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
 976         }
 977         map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
 978         sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
 979             sc->bge_cdata.bge_rx_jumbo_sparemap;
 980         sc->bge_cdata.bge_rx_jumbo_sparemap = map;
 981         sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
 982         /*
 983          * Fill in the extended RX buffer descriptor.
 984          */
 985         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
 986         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
 987         r->bge_idx = i;
 988         r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
 989         switch (nsegs) {
 990         case 4:
 991                 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
 992                 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
 993                 r->bge_len3 = segs[3].ds_len;
 994         case 3:
 995                 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
 996                 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
 997                 r->bge_len2 = segs[2].ds_len;
 998         case 2:
 999                 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1000                 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1001                 r->bge_len1 = segs[1].ds_len;
1002         case 1:
1003                 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1004                 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1005                 r->bge_len0 = segs[0].ds_len;
1006                 break;
1007         default:
1008                 panic("%s: %d segments\n", __func__, nsegs);
1009         }
1010
1011         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1012             sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1013
1014         return (0);
1015 }
1016
1017 /*
1018  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1019  * that's 1MB or memory, which is a lot. For now, we fill only the first
1020  * 256 ring entries and hope that our CPU is fast enough to keep up with
1021  * the NIC.
1022  */
1023 static int
1024 bge_init_rx_ring_std(struct bge_softc *sc)
1025 {
1026         int error, i;
1027
1028         bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1029         sc->bge_std = 0;
1030         for (i = 0; i < BGE_SSLOTS; i++) {
1031                 if ((error = bge_newbuf_std(sc, i)) != 0)
1032                         return (error);
1033                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1034         };
1035
1036         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1037             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1038
1039         sc->bge_std = i - 1;
1040         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1041
1042         return (0);
1043 }
1044
1045 static void
1046 bge_free_rx_ring_std(struct bge_softc *sc)
1047 {
1048         int i;
1049
1050         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1051                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1052                         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1053                             sc->bge_cdata.bge_rx_std_dmamap[i],
1054                             BUS_DMASYNC_POSTREAD);
1055                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1056                             sc->bge_cdata.bge_rx_std_dmamap[i]);
1057                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1058                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1059                 }
1060                 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1061                     sizeof(struct bge_rx_bd));
1062         }
1063 }
1064
1065 static int
1066 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1067 {
1068         struct bge_rcb *rcb;
1069         int error, i;
1070
1071         bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1072         sc->bge_jumbo = 0;
1073         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1074                 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1075                         return (error);
1076                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1077         };
1078
1079         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1080             sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1081
1082         sc->bge_jumbo = i - 1;
1083
1084         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1085         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1086                                     BGE_RCB_FLAG_USE_EXT_RX_BD);
1087         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1088
1089         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1090
1091         return (0);
1092 }
1093
1094 static void
1095 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1096 {
1097         int i;
1098
1099         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1100                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1101                         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1102                             sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1103                             BUS_DMASYNC_POSTREAD);
1104                         bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1105                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1106                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1107                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1108                 }
1109                 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1110                     sizeof(struct bge_extrx_bd));
1111         }
1112 }
1113
1114 static void
1115 bge_free_tx_ring(struct bge_softc *sc)
1116 {
1117         int i;
1118
1119         if (sc->bge_ldata.bge_tx_ring == NULL)
1120                 return;
1121
1122         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1123                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1124                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1125                             sc->bge_cdata.bge_tx_dmamap[i],
1126                             BUS_DMASYNC_POSTWRITE);
1127                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1128                             sc->bge_cdata.bge_tx_dmamap[i]);
1129                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1130                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1131                 }
1132                 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1133                     sizeof(struct bge_tx_bd));
1134         }
1135 }
1136
1137 static int
1138 bge_init_tx_ring(struct bge_softc *sc)
1139 {
1140         sc->bge_txcnt = 0;
1141         sc->bge_tx_saved_considx = 0;
1142
1143         bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1144         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1145             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1146
1147         /* Initialize transmit producer index for host-memory send ring. */
1148         sc->bge_tx_prodidx = 0;
1149         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1150
1151         /* 5700 b2 errata */
1152         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1153                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1154
1155         /* NIC-memory send ring not used; initialize to zero. */
1156         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1157         /* 5700 b2 errata */
1158         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1159                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1160
1161         return (0);
1162 }
1163
1164 static void
1165 bge_setpromisc(struct bge_softc *sc)
1166 {
1167         struct ifnet *ifp;
1168
1169         BGE_LOCK_ASSERT(sc);
1170
1171         ifp = sc->bge_ifp;
1172
1173         /* Enable or disable promiscuous mode as needed. */
1174         if (ifp->if_flags & IFF_PROMISC)
1175                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1176         else
1177                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1178 }
1179
1180 static void
1181 bge_setmulti(struct bge_softc *sc)
1182 {
1183         struct ifnet *ifp;
1184         struct ifmultiaddr *ifma;
1185         uint32_t hashes[4] = { 0, 0, 0, 0 };
1186         int h, i;
1187
1188         BGE_LOCK_ASSERT(sc);
1189
1190         ifp = sc->bge_ifp;
1191
1192         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1193                 for (i = 0; i < 4; i++)
1194                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1195                 return;
1196         }
1197
1198         /* First, zot all the existing filters. */
1199         for (i = 0; i < 4; i++)
1200                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1201
1202         /* Now program new ones. */
1203         if_maddr_rlock(ifp);
1204         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1205                 if (ifma->ifma_addr->sa_family != AF_LINK)
1206                         continue;
1207                 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1208                     ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1209                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1210         }
1211         if_maddr_runlock(ifp);
1212
1213         for (i = 0; i < 4; i++)
1214                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1215 }
1216
1217 static void
1218 bge_setvlan(struct bge_softc *sc)
1219 {
1220         struct ifnet *ifp;
1221
1222         BGE_LOCK_ASSERT(sc);
1223
1224         ifp = sc->bge_ifp;
1225
1226         /* Enable or disable VLAN tag stripping as needed. */
1227         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1228                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1229         else
1230                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1231 }
1232
1233 static void
1234 bge_sig_pre_reset(sc, type)
1235         struct bge_softc *sc;
1236         int type;
1237 {
1238         /*
1239          * Some chips don't like this so only do this if ASF is enabled
1240          */
1241         if (sc->bge_asf_mode)
1242                 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1243
1244         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1245                 switch (type) {
1246                 case BGE_RESET_START:
1247                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1248                         break;
1249                 case BGE_RESET_STOP:
1250                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1251                         break;
1252                 }
1253         }
1254 }
1255
1256 static void
1257 bge_sig_post_reset(sc, type)
1258         struct bge_softc *sc;
1259         int type;
1260 {
1261         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1262                 switch (type) {
1263                 case BGE_RESET_START:
1264                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001);
1265                         /* START DONE */
1266                         break;
1267                 case BGE_RESET_STOP:
1268                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002);
1269                         break;
1270                 }
1271         }
1272 }
1273
1274 static void
1275 bge_sig_legacy(sc, type)
1276         struct bge_softc *sc;
1277         int type;
1278 {
1279         if (sc->bge_asf_mode) {
1280                 switch (type) {
1281                 case BGE_RESET_START:
1282                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1283                         break;
1284                 case BGE_RESET_STOP:
1285                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1286                         break;
1287                 }
1288         }
1289 }
1290
1291 void bge_stop_fw(struct bge_softc *);
1292 void
1293 bge_stop_fw(sc)
1294         struct bge_softc *sc;
1295 {
1296         int i;
1297
1298         if (sc->bge_asf_mode) {
1299                 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE);
1300                 CSR_WRITE_4(sc, BGE_CPU_EVENT,
1301                     CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
1302
1303                 for (i = 0; i < 100; i++ ) {
1304                         if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14)))
1305                                 break;
1306                         DELAY(10);
1307                 }
1308         }
1309 }
1310
1311 /*
1312  * Do endian, PCI and DMA initialization.
1313  */
1314 static int
1315 bge_chipinit(struct bge_softc *sc)
1316 {
1317         uint32_t dma_rw_ctl;
1318         uint16_t val;
1319         int i;
1320
1321         /* Set endianness before we access any non-PCI registers. */
1322         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1323
1324         /* Clear the MAC control register */
1325         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1326
1327         /*
1328          * Clear the MAC statistics block in the NIC's
1329          * internal memory.
1330          */
1331         for (i = BGE_STATS_BLOCK;
1332             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1333                 BGE_MEMWIN_WRITE(sc, i, 0);
1334
1335         for (i = BGE_STATUS_BLOCK;
1336             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1337                 BGE_MEMWIN_WRITE(sc, i, 0);
1338
1339         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1340                 /*
1341                  *  Fix data corruption caused by non-qword write with WB.
1342                  *  Fix master abort in PCI mode.
1343                  *  Fix PCI latency timer.
1344                  */
1345                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1346                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1347                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1348         }
1349
1350         /*
1351          * Set up the PCI DMA control register.
1352          */
1353         dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1354             BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1355         if (sc->bge_flags & BGE_FLAG_PCIE) {
1356                 /* Read watermark not used, 128 bytes for write. */
1357                 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1358         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1359                 if (BGE_IS_5714_FAMILY(sc)) {
1360                         /* 256 bytes for read and write. */
1361                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1362                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1363                         dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1364                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1365                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1366                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1367                         /*
1368                          * In the BCM5703, the DMA read watermark should
1369                          * be set to less than or equal to the maximum
1370                          * memory read byte count of the PCI-X command
1371                          * register.
1372                          */
1373                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1374                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1375                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1376                         /* 1536 bytes for read, 384 bytes for write. */
1377                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1378                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1379                 } else {
1380                         /* 384 bytes for read and write. */
1381                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1382                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1383                             0x0F;
1384                 }
1385                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1386                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1387                         uint32_t tmp;
1388
1389                         /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1390                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1391                         if (tmp == 6 || tmp == 7)
1392                                 dma_rw_ctl |=
1393                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1394
1395                         /* Set PCI-X DMA write workaround. */
1396                         dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1397                 }
1398         } else {
1399                 /* Conventional PCI bus: 256 bytes for read and write. */
1400                 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1401                     BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1402
1403                 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1404                     sc->bge_asicrev != BGE_ASICREV_BCM5750)
1405                         dma_rw_ctl |= 0x0F;
1406         }
1407         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1408             sc->bge_asicrev == BGE_ASICREV_BCM5701)
1409                 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1410                     BGE_PCIDMARWCTL_ASRT_ALL_BE;
1411         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1412             sc->bge_asicrev == BGE_ASICREV_BCM5704)
1413                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1414         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1415
1416         /*
1417          * Set up general mode register.
1418          */
1419         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
1420             BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1421             BGE_MODECTL_TX_NO_PHDR_CSUM);
1422
1423         /*
1424          * BCM5701 B5 have a bug causing data corruption when using
1425          * 64-bit DMA reads, which can be terminated early and then
1426          * completed later as 32-bit accesses, in combination with
1427          * certain bridges.
1428          */
1429         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1430             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1431                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1432
1433         /*
1434          * Tell the firmware the driver is running
1435          */
1436         if (sc->bge_asf_mode & ASF_STACKUP)
1437                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
1438
1439         /*
1440          * Disable memory write invalidate.  Apparently it is not supported
1441          * properly by these devices.  Also ensure that INTx isn't disabled,
1442          * as these chips need it even when using MSI.
1443          */
1444         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1445             PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
1446
1447         /* Set the timer prescaler (always 66Mhz) */
1448         CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1449
1450         /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1451         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1452                 DELAY(40);      /* XXX */
1453
1454                 /* Put PHY into ready state */
1455                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1456                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1457                 DELAY(40);
1458         }
1459
1460         return (0);
1461 }
1462
1463 static int
1464 bge_blockinit(struct bge_softc *sc)
1465 {
1466         struct bge_rcb *rcb;
1467         bus_size_t vrcb;
1468         bge_hostaddr taddr;
1469         uint32_t val;
1470         int i;
1471
1472         /*
1473          * Initialize the memory window pointer register so that
1474          * we can access the first 32K of internal NIC RAM. This will
1475          * allow us to set up the TX send ring RCBs and the RX return
1476          * ring RCBs, plus other things which live in NIC memory.
1477          */
1478         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1479
1480         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1481
1482         if (!(BGE_IS_5705_PLUS(sc))) {
1483                 /* Configure mbuf memory pool */
1484                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1485                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1486                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1487                 else
1488                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1489
1490                 /* Configure DMA resource pool */
1491                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1492                     BGE_DMA_DESCRIPTORS);
1493                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1494         }
1495
1496         /* Configure mbuf pool watermarks */
1497         if (!BGE_IS_5705_PLUS(sc)) {
1498                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1499                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1500                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1501         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1502                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1503                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1504                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1505         } else {
1506                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1507                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1508                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1509         }
1510
1511         /* Configure DMA resource watermarks */
1512         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1513         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1514
1515         /* Enable buffer manager */
1516         if (!(BGE_IS_5705_PLUS(sc))) {
1517                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1518                     BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN);
1519
1520                 /* Poll for buffer manager start indication */
1521                 for (i = 0; i < BGE_TIMEOUT; i++) {
1522                         DELAY(10);
1523                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1524                                 break;
1525                 }
1526
1527                 if (i == BGE_TIMEOUT) {
1528                         device_printf(sc->bge_dev,
1529                             "buffer manager failed to start\n");
1530                         return (ENXIO);
1531                 }
1532         }
1533
1534         /* Enable flow-through queues */
1535         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1536         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1537
1538         /* Wait until queue initialization is complete */
1539         for (i = 0; i < BGE_TIMEOUT; i++) {
1540                 DELAY(10);
1541                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1542                         break;
1543         }
1544
1545         if (i == BGE_TIMEOUT) {
1546                 device_printf(sc->bge_dev, "flow-through queue init failed\n");
1547                 return (ENXIO);
1548         }
1549
1550         /* Initialize the standard RX ring control block */
1551         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1552         rcb->bge_hostaddr.bge_addr_lo =
1553             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1554         rcb->bge_hostaddr.bge_addr_hi =
1555             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1556         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1557             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1558         if (BGE_IS_5705_PLUS(sc))
1559                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1560         else
1561                 rcb->bge_maxlen_flags =
1562                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1563         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1564         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1565         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1566
1567         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1568         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1569
1570         /*
1571          * Initialize the jumbo RX ring control block
1572          * We set the 'ring disabled' bit in the flags
1573          * field until we're actually ready to start
1574          * using this ring (i.e. once we set the MTU
1575          * high enough to require it).
1576          */
1577         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1578                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1579
1580                 rcb->bge_hostaddr.bge_addr_lo =
1581                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1582                 rcb->bge_hostaddr.bge_addr_hi =
1583                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1584                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1585                     sc->bge_cdata.bge_rx_jumbo_ring_map,
1586                     BUS_DMASYNC_PREREAD);
1587                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1588                     BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1589                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1590                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1591                     rcb->bge_hostaddr.bge_addr_hi);
1592                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1593                     rcb->bge_hostaddr.bge_addr_lo);
1594
1595                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1596                     rcb->bge_maxlen_flags);
1597                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1598
1599                 /* Set up dummy disabled mini ring RCB */
1600                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1601                 rcb->bge_maxlen_flags =
1602                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1603                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1604                     rcb->bge_maxlen_flags);
1605         }
1606
1607         /*
1608          * Set the BD ring replentish thresholds. The recommended
1609          * values are 1/8th the number of descriptors allocated to
1610          * each ring.
1611          * XXX The 5754 requires a lower threshold, so it might be a
1612          * requirement of all 575x family chips.  The Linux driver sets
1613          * the lower threshold for all 5705 family chips as well, but there
1614          * are reports that it might not need to be so strict.
1615          *
1616          * XXX Linux does some extra fiddling here for the 5906 parts as
1617          * well.
1618          */
1619         if (BGE_IS_5705_PLUS(sc))
1620                 val = 8;
1621         else
1622                 val = BGE_STD_RX_RING_CNT / 8;
1623         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1624         if (BGE_IS_JUMBO_CAPABLE(sc))
1625                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1626                     BGE_JUMBO_RX_RING_CNT/8);
1627
1628         /*
1629          * Disable all unused send rings by setting the 'ring disabled'
1630          * bit in the flags field of all the TX send ring control blocks.
1631          * These are located in NIC memory.
1632          */
1633         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1634         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1635                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1636                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1637                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1638                 vrcb += sizeof(struct bge_rcb);
1639         }
1640
1641         /* Configure TX RCB 0 (we use only the first ring) */
1642         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1643         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1644         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1645         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1646         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1647             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1648         if (!(BGE_IS_5705_PLUS(sc)))
1649                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1650                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1651
1652         /* Disable all unused RX return rings */
1653         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1654         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1655                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1656                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1657                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1658                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1659                     BGE_RCB_FLAG_RING_DISABLED));
1660                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1661                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1662                     (i * (sizeof(uint64_t))), 0);
1663                 vrcb += sizeof(struct bge_rcb);
1664         }
1665
1666         /* Initialize RX ring indexes */
1667         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1668         if (BGE_IS_JUMBO_CAPABLE(sc))
1669                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1670         if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1671                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1672
1673         /*
1674          * Set up RX return ring 0
1675          * Note that the NIC address for RX return rings is 0x00000000.
1676          * The return rings live entirely within the host, so the
1677          * nicaddr field in the RCB isn't used.
1678          */
1679         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1680         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1681         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1682         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1683         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1684         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1685             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1686
1687         /* Set random backoff seed for TX */
1688         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1689             IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1690             IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1691             IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1692             BGE_TX_BACKOFF_SEED_MASK);
1693
1694         /* Set inter-packet gap */
1695         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1696
1697         /*
1698          * Specify which ring to use for packets that don't match
1699          * any RX rules.
1700          */
1701         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1702
1703         /*
1704          * Configure number of RX lists. One interrupt distribution
1705          * list, sixteen active lists, one bad frames class.
1706          */
1707         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1708
1709         /* Inialize RX list placement stats mask. */
1710         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1711         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1712
1713         /* Disable host coalescing until we get it set up */
1714         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1715
1716         /* Poll to make sure it's shut down. */
1717         for (i = 0; i < BGE_TIMEOUT; i++) {
1718                 DELAY(10);
1719                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1720                         break;
1721         }
1722
1723         if (i == BGE_TIMEOUT) {
1724                 device_printf(sc->bge_dev,
1725                     "host coalescing engine failed to idle\n");
1726                 return (ENXIO);
1727         }
1728
1729         /* Set up host coalescing defaults */
1730         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1731         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1732         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1733         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1734         if (!(BGE_IS_5705_PLUS(sc))) {
1735                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1736                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1737         }
1738         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1739         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1740
1741         /* Set up address of statistics block */
1742         if (!(BGE_IS_5705_PLUS(sc))) {
1743                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1744                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1745                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1746                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1747                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1748                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1749                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1750         }
1751
1752         /* Set up address of status block */
1753         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1754             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1755         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1756             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1757         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1758         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1759
1760         /* Set up status block size. */
1761         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1762             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
1763                 val = BGE_STATBLKSZ_FULL;
1764         else
1765                 val = BGE_STATBLKSZ_32BYTE;
1766
1767         /* Turn on host coalescing state machine */
1768         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1769
1770         /* Turn on RX BD completion state machine and enable attentions */
1771         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1772             BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
1773
1774         /* Turn on RX list placement state machine */
1775         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1776
1777         /* Turn on RX list selector state machine. */
1778         if (!(BGE_IS_5705_PLUS(sc)))
1779                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1780
1781         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1782             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1783             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1784             BGE_MACMODE_FRMHDR_DMA_ENB;
1785
1786         if (sc->bge_flags & BGE_FLAG_TBI)
1787                 val |= BGE_PORTMODE_TBI;
1788         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1789                 val |= BGE_PORTMODE_GMII;
1790         else
1791                 val |= BGE_PORTMODE_MII;
1792
1793         /* Turn on DMA, clear stats */
1794         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1795
1796         /* Set misc. local control, enable interrupts on attentions */
1797         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1798
1799 #ifdef notdef
1800         /* Assert GPIO pins for PHY reset */
1801         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
1802             BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
1803         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
1804             BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
1805 #endif
1806
1807         /* Turn on DMA completion state machine */
1808         if (!(BGE_IS_5705_PLUS(sc)))
1809                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1810
1811         val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
1812
1813         /* Enable host coalescing bug fix. */
1814         if (BGE_IS_5755_PLUS(sc))
1815                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1816
1817         /* Turn on write DMA state machine */
1818         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1819         DELAY(40);
1820
1821         /* Turn on read DMA state machine */
1822         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1823         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1824             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1825             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1826                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1827                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1828                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1829         if (sc->bge_flags & BGE_FLAG_PCIE)
1830                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1831         if (sc->bge_flags & BGE_FLAG_TSO)
1832                 val |= BGE_RDMAMODE_TSO4_ENABLE;
1833         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1834         DELAY(40);
1835
1836         /* Turn on RX data completion state machine */
1837         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1838
1839         /* Turn on RX BD initiator state machine */
1840         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1841
1842         /* Turn on RX data and RX BD initiator state machine */
1843         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1844
1845         /* Turn on Mbuf cluster free state machine */
1846         if (!(BGE_IS_5705_PLUS(sc)))
1847                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1848
1849         /* Turn on send BD completion state machine */
1850         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1851
1852         /* Turn on send data completion state machine */
1853         val = BGE_SDCMODE_ENABLE;
1854         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1855                 val |= BGE_SDCMODE_CDELAY;
1856         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1857
1858         /* Turn on send data initiator state machine */
1859         if (sc->bge_flags & BGE_FLAG_TSO)
1860                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08);
1861         else
1862                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1863
1864         /* Turn on send BD initiator state machine */
1865         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1866
1867         /* Turn on send BD selector state machine */
1868         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1869
1870         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1871         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1872             BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
1873
1874         /* ack/clear link change events */
1875         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1876             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1877             BGE_MACSTAT_LINK_CHANGED);
1878         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1879
1880         /* Enable PHY auto polling (for MII/GMII only) */
1881         if (sc->bge_flags & BGE_FLAG_TBI) {
1882                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1883         } else {
1884                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16));
1885                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1886                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
1887                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1888                             BGE_EVTENB_MI_INTERRUPT);
1889         }
1890
1891         /*
1892          * Clear any pending link state attention.
1893          * Otherwise some link state change events may be lost until attention
1894          * is cleared by bge_intr() -> bge_link_upd() sequence.
1895          * It's not necessary on newer BCM chips - perhaps enabling link
1896          * state change attentions implies clearing pending attention.
1897          */
1898         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1899             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1900             BGE_MACSTAT_LINK_CHANGED);
1901
1902         /* Enable link state change attentions. */
1903         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1904
1905         return (0);
1906 }
1907
1908 const struct bge_revision *
1909 bge_lookup_rev(uint32_t chipid)
1910 {
1911         const struct bge_revision *br;
1912
1913         for (br = bge_revisions; br->br_name != NULL; br++) {
1914                 if (br->br_chipid == chipid)
1915                         return (br);
1916         }
1917
1918         for (br = bge_majorrevs; br->br_name != NULL; br++) {
1919                 if (br->br_chipid == BGE_ASICREV(chipid))
1920                         return (br);
1921         }
1922
1923         return (NULL);
1924 }
1925
1926 const struct bge_vendor *
1927 bge_lookup_vendor(uint16_t vid)
1928 {
1929         const struct bge_vendor *v;
1930
1931         for (v = bge_vendors; v->v_name != NULL; v++)
1932                 if (v->v_id == vid)
1933                         return (v);
1934
1935         panic("%s: unknown vendor %d", __func__, vid);
1936         return (NULL);
1937 }
1938
1939 /*
1940  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1941  * against our list and return its name if we find a match.
1942  *
1943  * Note that since the Broadcom controller contains VPD support, we
1944  * try to get the device name string from the controller itself instead
1945  * of the compiled-in string. It guarantees we'll always announce the
1946  * right product name. We fall back to the compiled-in string when
1947  * VPD is unavailable or corrupt.
1948  */
1949 static int
1950 bge_probe(device_t dev)
1951 {
1952         const struct bge_type *t = bge_devs;
1953         struct bge_softc *sc = device_get_softc(dev);
1954         uint16_t vid, did;
1955
1956         sc->bge_dev = dev;
1957         vid = pci_get_vendor(dev);
1958         did = pci_get_device(dev);
1959         while(t->bge_vid != 0) {
1960                 if ((vid == t->bge_vid) && (did == t->bge_did)) {
1961                         char model[64], buf[96];
1962                         const struct bge_revision *br;
1963                         const struct bge_vendor *v;
1964                         uint32_t id;
1965
1966                         id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1967                             BGE_PCIMISCCTL_ASICREV_SHIFT;
1968                         if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG)
1969                                 id = pci_read_config(dev,
1970                                     BGE_PCI_PRODID_ASICREV, 4);
1971                         br = bge_lookup_rev(id);
1972                         v = bge_lookup_vendor(vid);
1973                         {
1974 #if __FreeBSD_version > 700024
1975                                 const char *pname;
1976
1977                                 if (bge_has_eaddr(sc) &&
1978                                     pci_get_vpd_ident(dev, &pname) == 0)
1979                                         snprintf(model, 64, "%s", pname);
1980                                 else
1981 #endif
1982                                         snprintf(model, 64, "%s %s",
1983                                             v->v_name,
1984                                             br != NULL ? br->br_name :
1985                                             "NetXtreme Ethernet Controller");
1986                         }
1987                         snprintf(buf, 96, "%s, %sASIC rev. %#08x", model,
1988                             br != NULL ? "" : "unknown ", id);
1989                         device_set_desc_copy(dev, buf);
1990                         return (0);
1991                 }
1992                 t++;
1993         }
1994
1995         return (ENXIO);
1996 }
1997
1998 static void
1999 bge_dma_free(struct bge_softc *sc)
2000 {
2001         int i;
2002
2003         /* Destroy DMA maps for RX buffers. */
2004         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2005                 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2006                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2007                             sc->bge_cdata.bge_rx_std_dmamap[i]);
2008         }
2009         if (sc->bge_cdata.bge_rx_std_sparemap)
2010                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2011                     sc->bge_cdata.bge_rx_std_sparemap);
2012
2013         /* Destroy DMA maps for jumbo RX buffers. */
2014         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2015                 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2016                         bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2017                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2018         }
2019         if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2020                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2021                     sc->bge_cdata.bge_rx_jumbo_sparemap);
2022
2023         /* Destroy DMA maps for TX buffers. */
2024         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2025                 if (sc->bge_cdata.bge_tx_dmamap[i])
2026                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2027                             sc->bge_cdata.bge_tx_dmamap[i]);
2028         }
2029
2030         if (sc->bge_cdata.bge_rx_mtag)
2031                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2032         if (sc->bge_cdata.bge_tx_mtag)
2033                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2034
2035
2036         /* Destroy standard RX ring. */
2037         if (sc->bge_cdata.bge_rx_std_ring_map)
2038                 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2039                     sc->bge_cdata.bge_rx_std_ring_map);
2040         if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
2041                 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2042                     sc->bge_ldata.bge_rx_std_ring,
2043                     sc->bge_cdata.bge_rx_std_ring_map);
2044
2045         if (sc->bge_cdata.bge_rx_std_ring_tag)
2046                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2047
2048         /* Destroy jumbo RX ring. */
2049         if (sc->bge_cdata.bge_rx_jumbo_ring_map)
2050                 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2051                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2052
2053         if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
2054             sc->bge_ldata.bge_rx_jumbo_ring)
2055                 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2056                     sc->bge_ldata.bge_rx_jumbo_ring,
2057                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2058
2059         if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2060                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2061
2062         /* Destroy RX return ring. */
2063         if (sc->bge_cdata.bge_rx_return_ring_map)
2064                 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2065                     sc->bge_cdata.bge_rx_return_ring_map);
2066
2067         if (sc->bge_cdata.bge_rx_return_ring_map &&
2068             sc->bge_ldata.bge_rx_return_ring)
2069                 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2070                     sc->bge_ldata.bge_rx_return_ring,
2071                     sc->bge_cdata.bge_rx_return_ring_map);
2072
2073         if (sc->bge_cdata.bge_rx_return_ring_tag)
2074                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2075
2076         /* Destroy TX ring. */
2077         if (sc->bge_cdata.bge_tx_ring_map)
2078                 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2079                     sc->bge_cdata.bge_tx_ring_map);
2080
2081         if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
2082                 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2083                     sc->bge_ldata.bge_tx_ring,
2084                     sc->bge_cdata.bge_tx_ring_map);
2085
2086         if (sc->bge_cdata.bge_tx_ring_tag)
2087                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2088
2089         /* Destroy status block. */
2090         if (sc->bge_cdata.bge_status_map)
2091                 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2092                     sc->bge_cdata.bge_status_map);
2093
2094         if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
2095                 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2096                     sc->bge_ldata.bge_status_block,
2097                     sc->bge_cdata.bge_status_map);
2098
2099         if (sc->bge_cdata.bge_status_tag)
2100                 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2101
2102         /* Destroy statistics block. */
2103         if (sc->bge_cdata.bge_stats_map)
2104                 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2105                     sc->bge_cdata.bge_stats_map);
2106
2107         if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2108                 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2109                     sc->bge_ldata.bge_stats,
2110                     sc->bge_cdata.bge_stats_map);
2111
2112         if (sc->bge_cdata.bge_stats_tag)
2113                 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2114
2115         /* Destroy the parent tag. */
2116         if (sc->bge_cdata.bge_parent_tag)
2117                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2118 }
2119
2120 static int
2121 bge_dma_alloc(device_t dev)
2122 {
2123         struct bge_dmamap_arg ctx;
2124         struct bge_softc *sc;
2125         bus_addr_t lowaddr;
2126         bus_size_t sbsz, txsegsz, txmaxsegsz;
2127         int i, error;
2128
2129         sc = device_get_softc(dev);
2130
2131         lowaddr = BUS_SPACE_MAXADDR;
2132         if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2133                 lowaddr = BGE_DMA_MAXADDR;
2134         if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0)
2135                 lowaddr = BUS_SPACE_MAXADDR_32BIT;
2136         /*
2137          * Allocate the parent bus DMA tag appropriate for PCI.
2138          */
2139         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2140             1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2141             NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2142             0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2143
2144         if (error != 0) {
2145                 device_printf(sc->bge_dev,
2146                     "could not allocate parent dma tag\n");
2147                 return (ENOMEM);
2148         }
2149
2150         /*
2151          * Create tag for Tx mbufs.
2152          */
2153         if (sc->bge_flags & BGE_FLAG_TSO) {
2154                 txsegsz = BGE_TSOSEG_SZ;
2155                 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
2156         } else {
2157                 txsegsz = MCLBYTES;
2158                 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
2159         }
2160         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1,
2161             0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2162             txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
2163             &sc->bge_cdata.bge_tx_mtag);
2164
2165         if (error) {
2166                 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
2167                 return (ENOMEM);
2168         }
2169
2170         /*
2171          * Create tag for Rx mbufs.
2172          */
2173         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
2174             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
2175             MCLBYTES, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
2176
2177         if (error) {
2178                 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
2179                 return (ENOMEM);
2180         }
2181
2182         /* Create DMA maps for RX buffers. */
2183         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2184             &sc->bge_cdata.bge_rx_std_sparemap);
2185         if (error) {
2186                 device_printf(sc->bge_dev,
2187                     "can't create spare DMA map for RX\n");
2188                 return (ENOMEM);
2189         }
2190         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2191                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2192                             &sc->bge_cdata.bge_rx_std_dmamap[i]);
2193                 if (error) {
2194                         device_printf(sc->bge_dev,
2195                             "can't create DMA map for RX\n");
2196                         return (ENOMEM);
2197                 }
2198         }
2199
2200         /* Create DMA maps for TX buffers. */
2201         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2202                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
2203                             &sc->bge_cdata.bge_tx_dmamap[i]);
2204                 if (error) {
2205                         device_printf(sc->bge_dev,
2206                             "can't create DMA map for TX\n");
2207                         return (ENOMEM);
2208                 }
2209         }
2210
2211         /* Create tag for standard RX ring. */
2212         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2213             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2214             NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0,
2215             NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag);
2216
2217         if (error) {
2218                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2219                 return (ENOMEM);
2220         }
2221
2222         /* Allocate DMA'able memory for standard RX ring. */
2223         error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag,
2224             (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT,
2225             &sc->bge_cdata.bge_rx_std_ring_map);
2226         if (error)
2227                 return (ENOMEM);
2228
2229         bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
2230
2231         /* Load the address of the standard RX ring. */
2232         ctx.bge_maxsegs = 1;
2233         ctx.sc = sc;
2234
2235         error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag,
2236             sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring,
2237             BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2238
2239         if (error)
2240                 return (ENOMEM);
2241
2242         sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr;
2243
2244         /* Create tags for jumbo mbufs. */
2245         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2246                 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2247                     1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2248                     NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
2249                     0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
2250                 if (error) {
2251                         device_printf(sc->bge_dev,
2252                             "could not allocate jumbo dma tag\n");
2253                         return (ENOMEM);
2254                 }
2255
2256                 /* Create tag for jumbo RX ring. */
2257                 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2258                     PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2259                     NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0,
2260                     NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag);
2261
2262                 if (error) {
2263                         device_printf(sc->bge_dev,
2264                             "could not allocate jumbo ring dma tag\n");
2265                         return (ENOMEM);
2266                 }
2267
2268                 /* Allocate DMA'able memory for jumbo RX ring. */
2269                 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2270                     (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
2271                     BUS_DMA_NOWAIT | BUS_DMA_ZERO,
2272                     &sc->bge_cdata.bge_rx_jumbo_ring_map);
2273                 if (error)
2274                         return (ENOMEM);
2275
2276                 /* Load the address of the jumbo RX ring. */
2277                 ctx.bge_maxsegs = 1;
2278                 ctx.sc = sc;
2279
2280                 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2281                     sc->bge_cdata.bge_rx_jumbo_ring_map,
2282                     sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ,
2283                     bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2284
2285                 if (error)
2286                         return (ENOMEM);
2287
2288                 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr;
2289
2290                 /* Create DMA maps for jumbo RX buffers. */
2291                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2292                     0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
2293                 if (error) {
2294                         device_printf(sc->bge_dev,
2295                             "can't create spare DMA map for jumbo RX\n");
2296                         return (ENOMEM);
2297                 }
2298                 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2299                         error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2300                                     0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2301                         if (error) {
2302                                 device_printf(sc->bge_dev,
2303                                     "can't create DMA map for jumbo RX\n");
2304                                 return (ENOMEM);
2305                         }
2306                 }
2307
2308         }
2309
2310         /* Create tag for RX return ring. */
2311         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2312             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2313             NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0,
2314             NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag);
2315
2316         if (error) {
2317                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2318                 return (ENOMEM);
2319         }
2320
2321         /* Allocate DMA'able memory for RX return ring. */
2322         error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag,
2323             (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT,
2324             &sc->bge_cdata.bge_rx_return_ring_map);
2325         if (error)
2326                 return (ENOMEM);
2327
2328         bzero((char *)sc->bge_ldata.bge_rx_return_ring,
2329             BGE_RX_RTN_RING_SZ(sc));
2330
2331         /* Load the address of the RX return ring. */
2332         ctx.bge_maxsegs = 1;
2333         ctx.sc = sc;
2334
2335         error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag,
2336             sc->bge_cdata.bge_rx_return_ring_map,
2337             sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc),
2338             bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2339
2340         if (error)
2341                 return (ENOMEM);
2342
2343         sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr;
2344
2345         /* Create tag for TX ring. */
2346         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2347             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2348             NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL,
2349             &sc->bge_cdata.bge_tx_ring_tag);
2350
2351         if (error) {
2352                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2353                 return (ENOMEM);
2354         }
2355
2356         /* Allocate DMA'able memory for TX ring. */
2357         error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag,
2358             (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT,
2359             &sc->bge_cdata.bge_tx_ring_map);
2360         if (error)
2361                 return (ENOMEM);
2362
2363         bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
2364
2365         /* Load the address of the TX ring. */
2366         ctx.bge_maxsegs = 1;
2367         ctx.sc = sc;
2368
2369         error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag,
2370             sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring,
2371             BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2372
2373         if (error)
2374                 return (ENOMEM);
2375
2376         sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr;
2377
2378         /*
2379          * Create tag for status block.
2380          * Because we only use single Tx/Rx/Rx return ring, use
2381          * minimum status block size except BCM5700 AX/BX which
2382          * seems to want to see full status block size regardless
2383          * of configured number of ring.
2384          */
2385         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2386             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
2387                 sbsz = BGE_STATUS_BLK_SZ;
2388         else
2389                 sbsz = 32;
2390         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2391             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2392             NULL, sbsz, 1, sbsz, 0, NULL, NULL, &sc->bge_cdata.bge_status_tag);
2393
2394         if (error) {
2395                 device_printf(sc->bge_dev,
2396                     "could not allocate status dma tag\n");
2397                 return (ENOMEM);
2398         }
2399
2400         /* Allocate DMA'able memory for status block. */
2401         error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag,
2402             (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT,
2403             &sc->bge_cdata.bge_status_map);
2404         if (error)
2405                 return (ENOMEM);
2406
2407         bzero((char *)sc->bge_ldata.bge_status_block, sbsz);
2408
2409         /* Load the address of the status block. */
2410         ctx.sc = sc;
2411         ctx.bge_maxsegs = 1;
2412
2413         error = bus_dmamap_load(sc->bge_cdata.bge_status_tag,
2414             sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block,
2415             sbsz, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2416
2417         if (error)
2418                 return (ENOMEM);
2419
2420         sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr;
2421
2422         /* Create tag for statistics block. */
2423         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2424             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2425             NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL,
2426             &sc->bge_cdata.bge_stats_tag);
2427
2428         if (error) {
2429                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2430                 return (ENOMEM);
2431         }
2432
2433         /* Allocate DMA'able memory for statistics block. */
2434         error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag,
2435             (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT,
2436             &sc->bge_cdata.bge_stats_map);
2437         if (error)
2438                 return (ENOMEM);
2439
2440         bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ);
2441
2442         /* Load the address of the statstics block. */
2443         ctx.sc = sc;
2444         ctx.bge_maxsegs = 1;
2445
2446         error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag,
2447             sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats,
2448             BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2449
2450         if (error)
2451                 return (ENOMEM);
2452
2453         sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr;
2454
2455         return (0);
2456 }
2457
2458 /*
2459  * Return true if this device has more than one port.
2460  */
2461 static int
2462 bge_has_multiple_ports(struct bge_softc *sc)
2463 {
2464         device_t dev = sc->bge_dev;
2465         u_int b, d, f, fscan, s;
2466
2467         d = pci_get_domain(dev);
2468         b = pci_get_bus(dev);
2469         s = pci_get_slot(dev);
2470         f = pci_get_function(dev);
2471         for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
2472                 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
2473                         return (1);
2474         return (0);
2475 }
2476
2477 /*
2478  * Return true if MSI can be used with this device.
2479  */
2480 static int
2481 bge_can_use_msi(struct bge_softc *sc)
2482 {
2483         int can_use_msi = 0;
2484
2485         switch (sc->bge_asicrev) {
2486         case BGE_ASICREV_BCM5714_A0:
2487         case BGE_ASICREV_BCM5714:
2488                 /*
2489                  * Apparently, MSI doesn't work when these chips are
2490                  * configured in single-port mode.
2491                  */
2492                 if (bge_has_multiple_ports(sc))
2493                         can_use_msi = 1;
2494                 break;
2495         case BGE_ASICREV_BCM5750:
2496                 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
2497                     sc->bge_chiprev != BGE_CHIPREV_5750_BX)
2498                         can_use_msi = 1;
2499                 break;
2500         default:
2501                 if (BGE_IS_575X_PLUS(sc))
2502                         can_use_msi = 1;
2503         }
2504         return (can_use_msi);
2505 }
2506
2507 static int
2508 bge_attach(device_t dev)
2509 {
2510         struct ifnet *ifp;
2511         struct bge_softc *sc;
2512         uint32_t hwcfg = 0, misccfg;
2513         u_char eaddr[ETHER_ADDR_LEN];
2514         int error, msicount, reg, rid, trys;
2515
2516         sc = device_get_softc(dev);
2517         sc->bge_dev = dev;
2518
2519         TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
2520
2521         /*
2522          * Map control/status registers.
2523          */
2524         pci_enable_busmaster(dev);
2525
2526         rid = BGE_PCI_BAR0;
2527         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2528             RF_ACTIVE);
2529
2530         if (sc->bge_res == NULL) {
2531                 device_printf (sc->bge_dev, "couldn't map memory\n");
2532                 error = ENXIO;
2533                 goto fail;
2534         }
2535
2536         /* Save various chip information. */
2537         sc->bge_chipid =
2538             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2539             BGE_PCIMISCCTL_ASICREV_SHIFT;
2540         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
2541                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV,
2542                     4);
2543         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2544         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2545
2546         /*
2547          * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the
2548          * 5705 A0 and A1 chips.
2549          */
2550         if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
2551             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2552             sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2553             sc->bge_chipid != BGE_CHIPID_BCM5705_A1)
2554                 sc->bge_flags |= BGE_FLAG_WIRESPEED;
2555
2556         if (bge_has_eaddr(sc))
2557                 sc->bge_flags |= BGE_FLAG_EADDR;
2558
2559         /* Save chipset family. */
2560         switch (sc->bge_asicrev) {
2561         case BGE_ASICREV_BCM5755:
2562         case BGE_ASICREV_BCM5761:
2563         case BGE_ASICREV_BCM5784:
2564         case BGE_ASICREV_BCM5785:
2565         case BGE_ASICREV_BCM5787:
2566         case BGE_ASICREV_BCM57780:
2567                 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2568                     BGE_FLAG_5705_PLUS;
2569                 break;
2570         case BGE_ASICREV_BCM5700:
2571         case BGE_ASICREV_BCM5701:
2572         case BGE_ASICREV_BCM5703:
2573         case BGE_ASICREV_BCM5704:
2574                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2575                 break;
2576         case BGE_ASICREV_BCM5714_A0:
2577         case BGE_ASICREV_BCM5780:
2578         case BGE_ASICREV_BCM5714:
2579                 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */;
2580                 /* FALLTHROUGH */
2581         case BGE_ASICREV_BCM5750:
2582         case BGE_ASICREV_BCM5752:
2583         case BGE_ASICREV_BCM5906:
2584                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2585                 /* FALLTHROUGH */
2586         case BGE_ASICREV_BCM5705:
2587                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2588                 break;
2589         }
2590
2591         /* Set various bug flags. */
2592         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2593             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2594                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
2595         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2596             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2597                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
2598         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2599                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
2600         if (pci_get_subvendor(dev) == DELL_VENDORID)
2601                 sc->bge_flags |= BGE_FLAG_NO_3LED;
2602         if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
2603                 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
2604         if (BGE_IS_5705_PLUS(sc) &&
2605             !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) {
2606                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2607                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2608                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2609                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2610                         if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
2611                             pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
2612                                 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
2613                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
2614                         sc->bge_flags |= BGE_FLAG_BER_BUG;
2615         }
2616
2617         /*
2618          * All controllers that are not 5755 or higher have 4GB
2619          * boundary DMA bug.
2620          * Whenever an address crosses a multiple of the 4GB boundary
2621          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
2622          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
2623          * state machine will lockup and cause the device to hang.
2624          */
2625         if (BGE_IS_5755_PLUS(sc) == 0)
2626                 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
2627
2628         /*
2629          * We could possibly check for BCOM_DEVICEID_BCM5788 in bge_probe()
2630          * but I do not know the DEVICEID for the 5788M.
2631          */
2632         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID;
2633         if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2634             misccfg == BGE_MISCCFG_BOARD_ID_5788M)
2635                 sc->bge_flags |= BGE_FLAG_5788;
2636
2637         /*
2638          * Some controllers seem to require a special firmware to use
2639          * TSO. But the firmware is not available to FreeBSD and Linux
2640          * claims that the TSO performed by the firmware is slower than
2641          * hardware based TSO. Moreover the firmware based TSO has one
2642          * known bug which can't handle TSO if ethernet header + IP/TCP
2643          * header is greater than 80 bytes. The workaround for the TSO
2644          * bug exist but it seems it's too expensive than not using
2645          * TSO at all. Some hardwares also have the TSO bug so limit
2646          * the TSO to the controllers that are not affected TSO issues
2647          * (e.g. 5755 or higher).
2648          */
2649         if (BGE_IS_5755_PLUS(sc)) {
2650                 /*
2651                  * BCM5754 and BCM5787 shares the same ASIC id so
2652                  * explicit device id check is required.
2653                  * Due to unknown reason TSO does not work on BCM5755M.
2654                  */
2655                 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
2656                     pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
2657                     pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
2658                         sc->bge_flags |= BGE_FLAG_TSO;
2659         }
2660
2661         /*
2662          * Check if this is a PCI-X or PCI Express device.
2663          */
2664         if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {
2665                 /*
2666                  * Found a PCI Express capabilities register, this
2667                  * must be a PCI Express device.
2668                  */
2669                 sc->bge_flags |= BGE_FLAG_PCIE;
2670                 sc->bge_expcap = reg;
2671                 if (pci_get_max_read_req(dev) != 4096)
2672                         pci_set_max_read_req(dev, 4096);
2673         } else {
2674                 /*
2675                  * Check if the device is in PCI-X Mode.
2676                  * (This bit is not valid on PCI Express controllers.)
2677                  */
2678                 if (pci_find_extcap(dev, PCIY_PCIX, &reg) == 0)
2679                         sc->bge_pcixcap = reg;
2680                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
2681                     BGE_PCISTATE_PCI_BUSMODE) == 0)
2682                         sc->bge_flags |= BGE_FLAG_PCIX;
2683         }
2684
2685         /*
2686          * The 40bit DMA bug applies to the 5714/5715 controllers and is
2687          * not actually a MAC controller bug but an issue with the embedded
2688          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2689          */
2690         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
2691                 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
2692         /*
2693          * Allocate the interrupt, using MSI if possible.  These devices
2694          * support 8 MSI messages, but only the first one is used in
2695          * normal operation.
2696          */
2697         rid = 0;
2698         if (pci_find_extcap(sc->bge_dev, PCIY_MSI, &reg) == 0) {
2699                 sc->bge_msicap = reg;
2700                 if (bge_can_use_msi(sc)) {
2701                         msicount = pci_msi_count(dev);
2702                         if (msicount > 1)
2703                                 msicount = 1;
2704                 } else
2705                         msicount = 0;
2706                 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
2707                         rid = 1;
2708                         sc->bge_flags |= BGE_FLAG_MSI;
2709                 }
2710         }
2711
2712         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2713             RF_SHAREABLE | RF_ACTIVE);
2714
2715         if (sc->bge_irq == NULL) {
2716                 device_printf(sc->bge_dev, "couldn't map interrupt\n");
2717                 error = ENXIO;
2718                 goto fail;
2719         }
2720
2721         if (bootverbose)
2722                 device_printf(dev,
2723                     "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2724                     sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2725                     (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" :
2726                     ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI"));
2727
2728         BGE_LOCK_INIT(sc, device_get_nameunit(dev));
2729
2730         /* Try to reset the chip. */
2731         if (bge_reset(sc)) {
2732                 device_printf(sc->bge_dev, "chip reset failed\n");
2733                 error = ENXIO;
2734                 goto fail;
2735         }
2736
2737         sc->bge_asf_mode = 0;
2738         if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG)
2739             == BGE_MAGIC_NUMBER)) {
2740                 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG)
2741                     & BGE_HWCFG_ASF) {
2742                         sc->bge_asf_mode |= ASF_ENABLE;
2743                         sc->bge_asf_mode |= ASF_STACKUP;
2744                         if (BGE_IS_575X_PLUS(sc))
2745                                 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
2746                 }
2747         }
2748
2749         /* Try to reset the chip again the nice way. */
2750         bge_stop_fw(sc);
2751         bge_sig_pre_reset(sc, BGE_RESET_STOP);
2752         if (bge_reset(sc)) {
2753                 device_printf(sc->bge_dev, "chip reset failed\n");
2754                 error = ENXIO;
2755                 goto fail;
2756         }
2757
2758         bge_sig_legacy(sc, BGE_RESET_STOP);
2759         bge_sig_post_reset(sc, BGE_RESET_STOP);
2760
2761         if (bge_chipinit(sc)) {
2762                 device_printf(sc->bge_dev, "chip initialization failed\n");
2763                 error = ENXIO;
2764                 goto fail;
2765         }
2766
2767         error = bge_get_eaddr(sc, eaddr);
2768         if (error) {
2769                 device_printf(sc->bge_dev,
2770                     "failed to read station address\n");
2771                 error = ENXIO;
2772                 goto fail;
2773         }
2774
2775         /* 5705 limits RX return ring to 512 entries. */
2776         if (BGE_IS_5705_PLUS(sc))
2777                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2778         else
2779                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2780
2781         if (bge_dma_alloc(dev)) {
2782                 device_printf(sc->bge_dev,
2783                     "failed to allocate DMA resources\n");
2784                 error = ENXIO;
2785                 goto fail;
2786         }
2787
2788         /* Set default tuneable values. */
2789         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2790         sc->bge_rx_coal_ticks = 150;
2791         sc->bge_tx_coal_ticks = 150;
2792         sc->bge_rx_max_coal_bds = 10;
2793         sc->bge_tx_max_coal_bds = 10;
2794
2795         /* Set up ifnet structure */
2796         ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
2797         if (ifp == NULL) {
2798                 device_printf(sc->bge_dev, "failed to if_alloc()\n");
2799                 error = ENXIO;
2800                 goto fail;
2801         }
2802         ifp->if_softc = sc;
2803         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2804         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2805         ifp->if_ioctl = bge_ioctl;
2806         ifp->if_start = bge_start;
2807         ifp->if_init = bge_init;
2808         ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
2809         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2810         IFQ_SET_READY(&ifp->if_snd);
2811         ifp->if_hwassist = BGE_CSUM_FEATURES;
2812         ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
2813             IFCAP_VLAN_MTU;
2814         if ((sc->bge_flags & BGE_FLAG_TSO) != 0) {
2815                 ifp->if_hwassist |= CSUM_TSO;
2816                 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO;
2817         }
2818 #ifdef IFCAP_VLAN_HWCSUM
2819         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
2820 #endif
2821         ifp->if_capenable = ifp->if_capabilities;
2822 #ifdef DEVICE_POLLING
2823         ifp->if_capabilities |= IFCAP_POLLING;
2824 #endif
2825
2826         /*
2827          * 5700 B0 chips do not support checksumming correctly due
2828          * to hardware bugs.
2829          */
2830         if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
2831                 ifp->if_capabilities &= ~IFCAP_HWCSUM;
2832                 ifp->if_capenable &= ~IFCAP_HWCSUM;
2833                 ifp->if_hwassist = 0;
2834         }
2835
2836         /*
2837          * Figure out what sort of media we have by checking the
2838          * hardware config word in the first 32k of NIC internal memory,
2839          * or fall back to examining the EEPROM if necessary.
2840          * Note: on some BCM5700 cards, this value appears to be unset.
2841          * If that's the case, we have to rely on identifying the NIC
2842          * by its PCI subsystem ID, as we do below for the SysKonnect
2843          * SK-9D41.
2844          */
2845         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2846                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2847         else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
2848             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
2849                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2850                     sizeof(hwcfg))) {
2851                         device_printf(sc->bge_dev, "failed to read EEPROM\n");
2852                         error = ENXIO;
2853                         goto fail;
2854                 }
2855                 hwcfg = ntohl(hwcfg);
2856         }
2857
2858         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2859         if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
2860             SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2861                 if (BGE_IS_5714_FAMILY(sc))
2862                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
2863                 else
2864                         sc->bge_flags |= BGE_FLAG_TBI;
2865         }
2866
2867         if (sc->bge_flags & BGE_FLAG_TBI) {
2868                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
2869                     bge_ifmedia_sts);
2870                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
2871                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2872                     0, NULL);
2873                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
2874                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
2875                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2876         } else {
2877                 /*
2878                  * Do transceiver setup and tell the firmware the
2879                  * driver is down so we can try to get access the
2880                  * probe if ASF is running.  Retry a couple of times
2881                  * if we get a conflict with the ASF firmware accessing
2882                  * the PHY.
2883                  */
2884                 trys = 0;
2885                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2886 again:
2887                 bge_asf_driver_up(sc);
2888
2889                 if (mii_phy_probe(dev, &sc->bge_miibus,
2890                     bge_ifmedia_upd, bge_ifmedia_sts)) {
2891                         if (trys++ < 4) {
2892                                 device_printf(sc->bge_dev, "Try again\n");
2893                                 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR,
2894                                     BMCR_RESET);
2895                                 goto again;
2896                         }
2897
2898                         device_printf(sc->bge_dev, "MII without any PHY!\n");
2899                         error = ENXIO;
2900                         goto fail;
2901                 }
2902
2903                 /*
2904                  * Now tell the firmware we are going up after probing the PHY
2905                  */
2906                 if (sc->bge_asf_mode & ASF_STACKUP)
2907                         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2908         }
2909
2910         /*
2911          * When using the BCM5701 in PCI-X mode, data corruption has
2912          * been observed in the first few bytes of some received packets.
2913          * Aligning the packet buffer in memory eliminates the corruption.
2914          * Unfortunately, this misaligns the packet payloads.  On platforms
2915          * which do not support unaligned accesses, we will realign the
2916          * payloads by copying the received packets.
2917          */
2918         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2919             sc->bge_flags & BGE_FLAG_PCIX)
2920                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2921
2922         /*
2923          * Call MI attach routine.
2924          */
2925         ether_ifattach(ifp, eaddr);
2926         callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
2927
2928         /* Tell upper layer we support long frames. */
2929         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2930
2931         /*
2932          * Hookup IRQ last.
2933          */
2934 #if __FreeBSD_version > 700030
2935         if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
2936                 /* Take advantage of single-shot MSI. */
2937                 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
2938                     ~BGE_MSIMODE_ONE_SHOT_DISABLE);
2939                 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
2940                     taskqueue_thread_enqueue, &sc->bge_tq);
2941                 if (sc->bge_tq == NULL) {
2942                         device_printf(dev, "could not create taskqueue.\n");
2943                         ether_ifdetach(ifp);
2944                         error = ENXIO;
2945                         goto fail;
2946                 }
2947                 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq",
2948                     device_get_nameunit(sc->bge_dev));
2949                 error = bus_setup_intr(dev, sc->bge_irq,
2950                     INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
2951                     &sc->bge_intrhand);
2952                 if (error)
2953                         ether_ifdetach(ifp);
2954         } else
2955                 error = bus_setup_intr(dev, sc->bge_irq,
2956                     INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
2957                     &sc->bge_intrhand);
2958 #else
2959         error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2960            bge_intr, sc, &sc->bge_intrhand);
2961 #endif
2962
2963         if (error) {
2964                 bge_detach(dev);
2965                 device_printf(sc->bge_dev, "couldn't set up irq\n");
2966         }
2967
2968         bge_add_sysctls(sc);
2969
2970         return (0);
2971
2972 fail:
2973         bge_release_resources(sc);
2974
2975         return (error);
2976 }
2977
2978 static int
2979 bge_detach(device_t dev)
2980 {
2981         struct bge_softc *sc;
2982         struct ifnet *ifp;
2983
2984         sc = device_get_softc(dev);
2985         ifp = sc->bge_ifp;
2986
2987 #ifdef DEVICE_POLLING
2988         if (ifp->if_capenable & IFCAP_POLLING)
2989                 ether_poll_deregister(ifp);
2990 #endif
2991
2992         BGE_LOCK(sc);
2993         bge_stop(sc);
2994         bge_reset(sc);
2995         BGE_UNLOCK(sc);
2996
2997         callout_drain(&sc->bge_stat_ch);
2998
2999         if (sc->bge_tq)
3000                 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3001         ether_ifdetach(ifp);
3002
3003         if (sc->bge_flags & BGE_FLAG_TBI) {
3004                 ifmedia_removeall(&sc->bge_ifmedia);
3005         } else {
3006                 bus_generic_detach(dev);
3007                 device_delete_child(dev, sc->bge_miibus);
3008         }
3009
3010         bge_release_resources(sc);
3011
3012         return (0);
3013 }
3014
3015 static void
3016 bge_release_resources(struct bge_softc *sc)
3017 {
3018         device_t dev;
3019
3020         dev = sc->bge_dev;
3021
3022         if (sc->bge_tq != NULL)
3023                 taskqueue_free(sc->bge_tq);
3024
3025         if (sc->bge_intrhand != NULL)
3026                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3027
3028         if (sc->bge_irq != NULL)
3029                 bus_release_resource(dev, SYS_RES_IRQ,
3030                     sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
3031
3032         if (sc->bge_flags & BGE_FLAG_MSI)
3033                 pci_release_msi(dev);
3034
3035         if (sc->bge_res != NULL)
3036                 bus_release_resource(dev, SYS_RES_MEMORY,
3037                     BGE_PCI_BAR0, sc->bge_res);
3038
3039         if (sc->bge_ifp != NULL)
3040                 if_free(sc->bge_ifp);
3041
3042         bge_dma_free(sc);
3043
3044         if (mtx_initialized(&sc->bge_mtx))      /* XXX */
3045                 BGE_LOCK_DESTROY(sc);
3046 }
3047
3048 static int
3049 bge_reset(struct bge_softc *sc)
3050 {
3051         device_t dev;
3052         uint32_t cachesize, command, pcistate, reset, val;
3053         void (*write_op)(struct bge_softc *, int, int);
3054         uint16_t devctl;
3055         int i;
3056
3057         dev = sc->bge_dev;
3058
3059         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
3060             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3061                 if (sc->bge_flags & BGE_FLAG_PCIE)
3062                         write_op = bge_writemem_direct;
3063                 else
3064                         write_op = bge_writemem_ind;
3065         } else
3066                 write_op = bge_writereg_ind;
3067
3068         /* Save some important PCI state. */
3069         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
3070         command = pci_read_config(dev, BGE_PCI_CMD, 4);
3071         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3072
3073         pci_write_config(dev, BGE_PCI_MISC_CTL,
3074             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3075             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3076
3077         /* Disable fastboot on controllers that support it. */
3078         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
3079             BGE_IS_5755_PLUS(sc)) {
3080                 if (bootverbose)
3081                         device_printf(sc->bge_dev, "Disabling fastboot\n");
3082                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
3083         }
3084
3085         /*
3086          * Write the magic number to SRAM at offset 0xB50.
3087          * When firmware finishes its initialization it will
3088          * write ~BGE_MAGIC_NUMBER to the same location.
3089          */
3090         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
3091
3092         reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
3093
3094         /* XXX: Broadcom Linux driver. */
3095         if (sc->bge_flags & BGE_FLAG_PCIE) {
3096                 if (CSR_READ_4(sc, 0x7E2C) == 0x60)     /* PCIE 1.0 */
3097                         CSR_WRITE_4(sc, 0x7E2C, 0x20);
3098                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3099                         /* Prevent PCIE link training during global reset */
3100                         CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
3101                         reset |= 1 << 29;
3102                 }
3103         }
3104
3105         /*
3106          * Set GPHY Power Down Override to leave GPHY
3107          * powered up in D0 uninitialized.
3108          */
3109         if (BGE_IS_5705_PLUS(sc))
3110                 reset |= 0x04000000;
3111
3112         /* Issue global reset */
3113         write_op(sc, BGE_MISC_CFG, reset);
3114
3115         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3116                 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3117                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
3118                     val | BGE_VCPU_STATUS_DRV_RESET);
3119                 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
3120                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
3121                     val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
3122         }
3123
3124         DELAY(1000);
3125
3126         /* XXX: Broadcom Linux driver. */
3127         if (sc->bge_flags & BGE_FLAG_PCIE) {
3128                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
3129                         DELAY(500000); /* wait for link training to complete */
3130                         val = pci_read_config(dev, 0xC4, 4);
3131                         pci_write_config(dev, 0xC4, val | (1 << 15), 4);
3132                 }
3133                 devctl = pci_read_config(dev,
3134                     sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
3135                 /* Clear enable no snoop and disable relaxed ordering. */
3136                 devctl &= ~(PCIM_EXP_CTL_RELAXED_ORD_ENABLE |
3137                     PCIM_EXP_CTL_NOSNOOP_ENABLE);
3138                 /* Set PCIE max payload size to 128. */
3139                 devctl &= ~PCIM_EXP_CTL_MAX_PAYLOAD;
3140                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL,
3141                     devctl, 2);
3142                 /* Clear error status. */
3143                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA,
3144                     PCIM_EXP_STA_CORRECTABLE_ERROR |
3145                     PCIM_EXP_STA_NON_FATAL_ERROR | PCIM_EXP_STA_FATAL_ERROR |
3146                     PCIM_EXP_STA_UNSUPPORTED_REQ, 2);
3147         }
3148
3149         /* Reset some of the PCI state that got zapped by reset. */
3150         pci_write_config(dev, BGE_PCI_MISC_CTL,
3151             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3152             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3153         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
3154         pci_write_config(dev, BGE_PCI_CMD, command, 4);
3155         write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
3156         /*
3157          * Disable PCI-X relaxed ordering to ensure status block update
3158          * comes first then packet buffer DMA. Otherwise driver may
3159          * read stale status block.
3160          */
3161         if (sc->bge_flags & BGE_FLAG_PCIX) {
3162                 devctl = pci_read_config(dev,
3163                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
3164                 devctl &= ~PCIXM_COMMAND_ERO;
3165                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
3166                         devctl &= ~PCIXM_COMMAND_MAX_READ;
3167                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
3168                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3169                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
3170                             PCIXM_COMMAND_MAX_READ);
3171                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
3172                 }
3173                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
3174                     devctl, 2);
3175         }
3176         /* Re-enable MSI, if neccesary, and enable the memory arbiter. */
3177         if (BGE_IS_5714_FAMILY(sc)) {
3178                 /* This chip disables MSI on reset. */
3179                 if (sc->bge_flags & BGE_FLAG_MSI) {
3180                         val = pci_read_config(dev,
3181                             sc->bge_msicap + PCIR_MSI_CTRL, 2);
3182                         pci_write_config(dev,
3183                             sc->bge_msicap + PCIR_MSI_CTRL,
3184                             val | PCIM_MSICTRL_MSI_ENABLE, 2);
3185                         val = CSR_READ_4(sc, BGE_MSI_MODE);
3186                         CSR_WRITE_4(sc, BGE_MSI_MODE,
3187                             val | BGE_MSIMODE_ENABLE);
3188                 }
3189                 val = CSR_READ_4(sc, BGE_MARB_MODE);
3190                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
3191         } else
3192                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3193
3194         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3195                 for (i = 0; i < BGE_TIMEOUT; i++) {
3196                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3197                         if (val & BGE_VCPU_STATUS_INIT_DONE)
3198                                 break;
3199                         DELAY(100);
3200                 }
3201                 if (i == BGE_TIMEOUT) {
3202                         device_printf(sc->bge_dev, "reset timed out\n");
3203                         return (1);
3204                 }
3205         } else {
3206                 /*
3207                  * Poll until we see the 1's complement of the magic number.
3208                  * This indicates that the firmware initialization is complete.
3209                  * We expect this to fail if no chip containing the Ethernet
3210                  * address is fitted though.
3211                  */
3212                 for (i = 0; i < BGE_TIMEOUT; i++) {
3213                         DELAY(10);
3214                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
3215                         if (val == ~BGE_MAGIC_NUMBER)
3216                                 break;
3217                 }
3218
3219                 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
3220                         device_printf(sc->bge_dev, "firmware handshake timed out, "
3221                             "found 0x%08x\n", val);
3222         }
3223
3224         /*
3225          * XXX Wait for the value of the PCISTATE register to
3226          * return to its original pre-reset state. This is a
3227          * fairly good indicator of reset completion. If we don't
3228          * wait for the reset to fully complete, trying to read
3229          * from the device's non-PCI registers may yield garbage
3230          * results.
3231          */
3232         for (i = 0; i < BGE_TIMEOUT; i++) {
3233                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
3234                         break;
3235                 DELAY(10);
3236         }
3237
3238         if (sc->bge_flags & BGE_FLAG_PCIE) {
3239                 reset = bge_readmem_ind(sc, 0x7C00);
3240                 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25));
3241         }
3242
3243         /* Fix up byte swapping. */
3244         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
3245             BGE_MODECTL_BYTESWAP_DATA);
3246
3247         /* Tell the ASF firmware we are up */
3248         if (sc->bge_asf_mode & ASF_STACKUP)
3249                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3250
3251         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
3252
3253         /*
3254          * The 5704 in TBI mode apparently needs some special
3255          * adjustment to insure the SERDES drive level is set
3256          * to 1.2V.
3257          */
3258         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
3259             sc->bge_flags & BGE_FLAG_TBI) {
3260                 val = CSR_READ_4(sc, BGE_SERDES_CFG);
3261                 val = (val & ~0xFFF) | 0x880;
3262                 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
3263         }
3264
3265         /* XXX: Broadcom Linux driver. */
3266         if (sc->bge_flags & BGE_FLAG_PCIE &&
3267             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3268                 val = CSR_READ_4(sc, 0x7C00);
3269                 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
3270         }
3271         DELAY(10000);
3272
3273         return(0);
3274 }
3275
3276 /*
3277  * Frame reception handling. This is called if there's a frame
3278  * on the receive return list.
3279  *
3280  * Note: we have to be able to handle two possibilities here:
3281  * 1) the frame is from the jumbo receive ring
3282  * 2) the frame is from the standard receive ring
3283  */
3284
3285 static int
3286 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
3287 {
3288         struct ifnet *ifp;
3289         int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
3290         uint16_t rx_cons;
3291
3292         rx_cons = sc->bge_rx_saved_considx;
3293
3294         /* Nothing to do. */
3295         if (rx_cons == rx_prod)
3296                 return (rx_npkts);
3297
3298         ifp = sc->bge_ifp;
3299
3300         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3301             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
3302         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3303             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
3304         if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
3305             (MCLBYTES - ETHER_ALIGN))
3306                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3307                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
3308
3309         while (rx_cons != rx_prod) {
3310                 struct bge_rx_bd        *cur_rx;
3311                 uint32_t                rxidx;
3312                 struct mbuf             *m = NULL;
3313                 uint16_t                vlan_tag = 0;
3314                 int                     have_tag = 0;
3315
3316 #ifdef DEVICE_POLLING
3317                 if (ifp->if_capenable & IFCAP_POLLING) {
3318                         if (sc->rxcycles <= 0)
3319                                 break;
3320                         sc->rxcycles--;
3321                 }
3322 #endif
3323
3324                 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
3325
3326                 rxidx = cur_rx->bge_idx;
3327                 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
3328
3329                 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
3330                     cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
3331                         have_tag = 1;
3332                         vlan_tag = cur_rx->bge_vlan_tag;
3333                 }
3334
3335                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
3336                         jumbocnt++;
3337                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
3338                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3339                                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3340                                 continue;
3341                         }
3342                         if (bge_newbuf_jumbo(sc, rxidx) != 0) {
3343                                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3344                                 ifp->if_iqdrops++;
3345                                 continue;
3346                         }
3347                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3348                 } else {
3349                         stdcnt++;
3350                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3351                                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3352                                 continue;
3353                         }
3354                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
3355                         if (bge_newbuf_std(sc, rxidx) != 0) {
3356                                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3357                                 ifp->if_iqdrops++;
3358                                 continue;
3359                         }
3360                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3361                 }
3362
3363                 ifp->if_ipackets++;
3364 #ifndef __NO_STRICT_ALIGNMENT
3365                 /*
3366                  * For architectures with strict alignment we must make sure
3367                  * the payload is aligned.
3368                  */
3369                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
3370                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
3371                             cur_rx->bge_len);
3372                         m->m_data += ETHER_ALIGN;
3373                 }
3374 #endif
3375                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3376                 m->m_pkthdr.rcvif = ifp;
3377
3378                 if (ifp->if_capenable & IFCAP_RXCSUM) {
3379                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3380                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3381                                 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
3382                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3383                         }
3384                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
3385                             m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
3386                                 m->m_pkthdr.csum_data =
3387                                     cur_rx->bge_tcp_udp_csum;
3388                                 m->m_pkthdr.csum_flags |=
3389                                     CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
3390                         }
3391                 }
3392
3393                 /*
3394                  * If we received a packet with a vlan tag,
3395                  * attach that information to the packet.
3396                  */
3397                 if (have_tag) {
3398 #if __FreeBSD_version > 700022
3399                         m->m_pkthdr.ether_vtag = vlan_tag;
3400                         m->m_flags |= M_VLANTAG;
3401 #else
3402                         VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag);
3403                         if (m == NULL)
3404                                 continue;
3405 #endif
3406                 }
3407
3408                 if (holdlck != 0) {
3409                         BGE_UNLOCK(sc);
3410                         (*ifp->if_input)(ifp, m);
3411                         BGE_LOCK(sc);
3412                 } else
3413                         (*ifp->if_input)(ifp, m);
3414                 rx_npkts++;
3415
3416                 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
3417                         return (rx_npkts);
3418         }
3419
3420         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3421             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
3422         if (stdcnt > 0)
3423                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3424                     sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
3425
3426         if (jumbocnt > 0)
3427                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3428                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
3429
3430         sc->bge_rx_saved_considx = rx_cons;
3431         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3432         if (stdcnt)
3433                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
3434         if (jumbocnt)
3435                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
3436 #ifdef notyet
3437         /*
3438          * This register wraps very quickly under heavy packet drops.
3439          * If you need correct statistics, you can enable this check.
3440          */
3441         if (BGE_IS_5705_PLUS(sc))
3442                 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3443 #endif
3444         return (rx_npkts);
3445 }
3446
3447 static void
3448 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
3449 {
3450         struct bge_tx_bd *cur_tx = NULL;
3451         struct ifnet *ifp;
3452
3453         BGE_LOCK_ASSERT(sc);
3454
3455         /* Nothing to do. */
3456         if (sc->bge_tx_saved_considx == tx_cons)
3457                 return;
3458
3459         ifp = sc->bge_ifp;
3460
3461         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
3462             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
3463         /*
3464          * Go through our tx ring and free mbufs for those
3465          * frames that have been sent.
3466          */
3467         while (sc->bge_tx_saved_considx != tx_cons) {
3468                 uint32_t                idx = 0;
3469
3470                 idx = sc->bge_tx_saved_considx;
3471                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
3472                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
3473                         ifp->if_opackets++;
3474                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
3475                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
3476                             sc->bge_cdata.bge_tx_dmamap[idx],
3477                             BUS_DMASYNC_POSTWRITE);
3478                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
3479                             sc->bge_cdata.bge_tx_dmamap[idx]);
3480                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
3481                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
3482                 }
3483                 sc->bge_txcnt--;
3484                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3485         }
3486
3487         if (cur_tx != NULL)
3488                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3489         if (sc->bge_txcnt == 0)
3490                 sc->bge_timer = 0;
3491 }
3492
3493 #ifdef DEVICE_POLLING
3494 static int
3495 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3496 {
3497         struct bge_softc *sc = ifp->if_softc;
3498         uint16_t rx_prod, tx_cons;
3499         uint32_t statusword;
3500         int rx_npkts = 0;
3501
3502         BGE_LOCK(sc);
3503         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3504                 BGE_UNLOCK(sc);
3505                 return (rx_npkts);
3506         }
3507
3508         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3509             sc->bge_cdata.bge_status_map,
3510             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3511         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3512         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3513
3514         statusword = atomic_readandclear_32(
3515             &sc->bge_ldata.bge_status_block->bge_status);
3516
3517         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3518             sc->bge_cdata.bge_status_map,
3519             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3520
3521         /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
3522         if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
3523                 sc->bge_link_evt++;
3524
3525         if (cmd == POLL_AND_CHECK_STATUS)
3526                 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3527                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3528                     sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
3529                         bge_link_upd(sc);
3530
3531         sc->rxcycles = count;
3532         rx_npkts = bge_rxeof(sc, rx_prod, 1);
3533         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3534                 BGE_UNLOCK(sc);
3535                 return (rx_npkts);
3536         }
3537         bge_txeof(sc, tx_cons);
3538         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3539                 bge_start_locked(ifp);
3540
3541         BGE_UNLOCK(sc);
3542         return (rx_npkts);
3543 }
3544 #endif /* DEVICE_POLLING */
3545
3546 static int
3547 bge_msi_intr(void *arg)
3548 {
3549         struct bge_softc *sc;
3550
3551         sc = (struct bge_softc *)arg;
3552         /*
3553          * This interrupt is not shared and controller already
3554          * disabled further interrupt.
3555          */
3556         taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
3557         return (FILTER_HANDLED);
3558 }
3559
3560 static void
3561 bge_intr_task(void *arg, int pending)
3562 {
3563         struct bge_softc *sc;
3564         struct ifnet *ifp;
3565         uint32_t status;
3566         uint16_t rx_prod, tx_cons;
3567
3568         sc = (struct bge_softc *)arg;
3569         ifp = sc->bge_ifp;
3570
3571         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3572                 return;
3573
3574         /* Get updated status block. */
3575         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3576             sc->bge_cdata.bge_status_map,
3577             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3578
3579         /* Save producer/consumer indexess. */
3580         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3581         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3582         status = sc->bge_ldata.bge_status_block->bge_status;
3583         sc->bge_ldata.bge_status_block->bge_status = 0;
3584         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3585             sc->bge_cdata.bge_status_map,
3586             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3587         /* Let controller work. */
3588         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3589
3590         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) {
3591                 BGE_LOCK(sc);
3592                 bge_link_upd(sc);
3593                 BGE_UNLOCK(sc);
3594         }
3595         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3596                 /* Check RX return ring producer/consumer. */
3597                 bge_rxeof(sc, rx_prod, 0);
3598         }
3599         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3600                 BGE_LOCK(sc);
3601                 /* Check TX ring producer/consumer. */
3602                 bge_txeof(sc, tx_cons);
3603                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3604                         bge_start_locked(ifp);
3605                 BGE_UNLOCK(sc);
3606         }
3607 }
3608
3609 static void
3610 bge_intr(void *xsc)
3611 {
3612         struct bge_softc *sc;
3613         struct ifnet *ifp;
3614         uint32_t statusword;
3615         uint16_t rx_prod, tx_cons;
3616
3617         sc = xsc;
3618
3619         BGE_LOCK(sc);
3620
3621         ifp = sc->bge_ifp;
3622
3623 #ifdef DEVICE_POLLING
3624         if (ifp->if_capenable & IFCAP_POLLING) {
3625                 BGE_UNLOCK(sc);
3626                 return;
3627         }
3628 #endif
3629
3630         /*
3631          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
3632          * disable interrupts by writing nonzero like we used to, since with
3633          * our current organization this just gives complications and
3634          * pessimizations for re-enabling interrupts.  We used to have races
3635          * instead of the necessary complications.  Disabling interrupts
3636          * would just reduce the chance of a status update while we are
3637          * running (by switching to the interrupt-mode coalescence
3638          * parameters), but this chance is already very low so it is more
3639          * efficient to get another interrupt than prevent it.
3640          *
3641          * We do the ack first to ensure another interrupt if there is a
3642          * status update after the ack.  We don't check for the status
3643          * changing later because it is more efficient to get another
3644          * interrupt than prevent it, not quite as above (not checking is
3645          * a smaller optimization than not toggling the interrupt enable,
3646          * since checking doesn't involve PCI accesses and toggling require
3647          * the status check).  So toggling would probably be a pessimization
3648          * even with MSI.  It would only be needed for using a task queue.
3649          */
3650         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3651
3652         /*
3653          * Do the mandatory PCI flush as well as get the link status.
3654          */
3655         statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
3656
3657         /* Make sure the descriptor ring indexes are coherent. */
3658         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3659             sc->bge_cdata.bge_status_map,
3660             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3661         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3662         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3663         sc->bge_ldata.bge_status_block->bge_status = 0;
3664         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3665             sc->bge_cdata.bge_status_map,
3666             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3667
3668         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3669             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3670             statusword || sc->bge_link_evt)
3671                 bge_link_upd(sc);
3672
3673         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3674                 /* Check RX return ring producer/consumer. */
3675                 bge_rxeof(sc, rx_prod, 1);
3676         }
3677
3678         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3679                 /* Check TX ring producer/consumer. */
3680                 bge_txeof(sc, tx_cons);
3681         }
3682
3683         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3684             !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3685                 bge_start_locked(ifp);
3686
3687         BGE_UNLOCK(sc);
3688 }
3689
3690 static void
3691 bge_asf_driver_up(struct bge_softc *sc)
3692 {
3693         if (sc->bge_asf_mode & ASF_STACKUP) {
3694                 /* Send ASF heartbeat aprox. every 2s */
3695                 if (sc->bge_asf_count)
3696                         sc->bge_asf_count --;
3697                 else {
3698                         sc->bge_asf_count = 2;
3699                         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW,
3700                             BGE_FW_DRV_ALIVE);
3701                         bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4);
3702                         bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3);
3703                         CSR_WRITE_4(sc, BGE_CPU_EVENT,
3704                             CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
3705                 }
3706         }
3707 }
3708
3709 static void
3710 bge_tick(void *xsc)
3711 {
3712         struct bge_softc *sc = xsc;
3713         struct mii_data *mii = NULL;
3714
3715         BGE_LOCK_ASSERT(sc);
3716
3717         /* Synchronize with possible callout reset/stop. */
3718         if (callout_pending(&sc->bge_stat_ch) ||
3719             !callout_active(&sc->bge_stat_ch))
3720                 return;
3721
3722         if (BGE_IS_5705_PLUS(sc))
3723                 bge_stats_update_regs(sc);
3724         else
3725                 bge_stats_update(sc);
3726
3727         if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
3728                 mii = device_get_softc(sc->bge_miibus);
3729                 /*
3730                  * Do not touch PHY if we have link up. This could break
3731                  * IPMI/ASF mode or produce extra input errors
3732                  * (extra errors was reported for bcm5701 & bcm5704).
3733                  */
3734                 if (!sc->bge_link)
3735                         mii_tick(mii);
3736         } else {
3737                 /*
3738                  * Since in TBI mode auto-polling can't be used we should poll
3739                  * link status manually. Here we register pending link event
3740                  * and trigger interrupt.
3741                  */
3742 #ifdef DEVICE_POLLING
3743                 /* In polling mode we poll link state in bge_poll(). */
3744                 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
3745 #endif
3746                 {
3747                 sc->bge_link_evt++;
3748                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3749                     sc->bge_flags & BGE_FLAG_5788)
3750                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3751                 else
3752                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3753                 }
3754         }
3755
3756         bge_asf_driver_up(sc);
3757         bge_watchdog(sc);
3758
3759         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
3760 }
3761
3762 static void
3763 bge_stats_update_regs(struct bge_softc *sc)
3764 {
3765         struct ifnet *ifp;
3766
3767         ifp = sc->bge_ifp;
3768
3769         ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS +
3770             offsetof(struct bge_mac_stats_regs, etherStatsCollisions));
3771
3772         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
3773         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3774         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
3775 }
3776
3777 static void
3778 bge_stats_update(struct bge_softc *sc)
3779 {
3780         struct ifnet *ifp;
3781         bus_size_t stats;
3782         uint32_t cnt;   /* current register value */
3783
3784         ifp = sc->bge_ifp;
3785
3786         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3787
3788 #define READ_STAT(sc, stats, stat) \
3789         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3790
3791         cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
3792         ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
3793         sc->bge_tx_collisions = cnt;
3794
3795         cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
3796         ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
3797         sc->bge_rx_discards = cnt;
3798
3799         cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
3800         ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
3801         sc->bge_tx_discards = cnt;
3802
3803 #undef  READ_STAT
3804 }
3805
3806 /*
3807  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
3808  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
3809  * but when such padded frames employ the bge IP/TCP checksum offload,
3810  * the hardware checksum assist gives incorrect results (possibly
3811  * from incorporating its own padding into the UDP/TCP checksum; who knows).
3812  * If we pad such runts with zeros, the onboard checksum comes out correct.
3813  */
3814 static __inline int
3815 bge_cksum_pad(struct mbuf *m)
3816 {
3817         int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
3818         struct mbuf *last;
3819
3820         /* If there's only the packet-header and we can pad there, use it. */
3821         if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
3822             M_TRAILINGSPACE(m) >= padlen) {
3823                 last = m;
3824         } else {
3825                 /*
3826                  * Walk packet chain to find last mbuf. We will either
3827                  * pad there, or append a new mbuf and pad it.
3828                  */
3829                 for (last = m; last->m_next != NULL; last = last->m_next);
3830                 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
3831                         /* Allocate new empty mbuf, pad it. Compact later. */
3832                         struct mbuf *n;
3833
3834                         MGET(n, M_DONTWAIT, MT_DATA);
3835                         if (n == NULL)
3836                                 return (ENOBUFS);
3837                         n->m_len = 0;
3838                         last->m_next = n;
3839                         last = n;
3840                 }
3841         }
3842
3843         /* Now zero the pad area, to avoid the bge cksum-assist bug. */
3844         memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
3845         last->m_len += padlen;
3846         m->m_pkthdr.len += padlen;
3847
3848         return (0);
3849 }
3850
3851 static struct mbuf *
3852 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss)
3853 {
3854         struct ip *ip;
3855         struct tcphdr *tcp;
3856         struct mbuf *n;
3857         uint16_t hlen;
3858         uint32_t poff;
3859
3860         if (M_WRITABLE(m) == 0) {
3861                 /* Get a writable copy. */
3862                 n = m_dup(m, M_DONTWAIT);
3863                 m_freem(m);
3864                 if (n == NULL)
3865                         return (NULL);
3866                 m = n;
3867         }
3868         m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
3869         if (m == NULL)
3870                 return (NULL);
3871         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
3872         poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
3873         m = m_pullup(m, poff + sizeof(struct tcphdr));
3874         if (m == NULL)
3875                 return (NULL);
3876         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
3877         m = m_pullup(m, poff + (tcp->th_off << 2));
3878         if (m == NULL)
3879                 return (NULL);
3880         /*
3881          * It seems controller doesn't modify IP length and TCP pseudo
3882          * checksum. These checksum computed by upper stack should be 0.
3883          */
3884         *mss = m->m_pkthdr.tso_segsz;
3885         ip->ip_sum = 0;
3886         ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
3887         /* Clear pseudo checksum computed by TCP stack. */
3888         tcp->th_sum = 0;
3889         /*
3890          * Broadcom controllers uses different descriptor format for
3891          * TSO depending on ASIC revision. Due to TSO-capable firmware
3892          * license issue and lower performance of firmware based TSO
3893          * we only support hardware based TSO which is applicable for
3894          * BCM5755 or newer controllers. Hardware based TSO uses 11
3895          * bits to store MSS and upper 5 bits are used to store IP/TCP
3896          * header length(including IP/TCP options). The header length
3897          * is expressed as 32 bits unit.
3898          */
3899         hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
3900         *mss |= (hlen << 11);
3901         return (m);
3902 }
3903
3904 /*
3905  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
3906  * pointers to descriptors.
3907  */
3908 static int
3909 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
3910 {
3911         bus_dma_segment_t       segs[BGE_NSEG_NEW];
3912         bus_dmamap_t            map;
3913         struct bge_tx_bd        *d;
3914         struct mbuf             *m = *m_head;
3915         uint32_t                idx = *txidx;
3916         uint16_t                csum_flags, mss, vlan_tag;
3917         int                     nsegs, i, error;
3918
3919         csum_flags = 0;
3920         mss = 0;
3921         vlan_tag = 0;
3922         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
3923                 *m_head = m = bge_setup_tso(sc, m, &mss);
3924                 if (*m_head == NULL)
3925                         return (ENOBUFS);
3926                 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
3927                     BGE_TXBDFLAG_CPU_POST_DMA;
3928         } else if ((m->m_pkthdr.csum_flags & BGE_CSUM_FEATURES) != 0) {
3929                 if (m->m_pkthdr.csum_flags & CSUM_IP)
3930                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3931                 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
3932                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3933                         if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
3934                             (error = bge_cksum_pad(m)) != 0) {
3935                                 m_freem(m);
3936                                 *m_head = NULL;
3937                                 return (error);
3938                         }
3939                 }
3940                 if (m->m_flags & M_LASTFRAG)
3941                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3942                 else if (m->m_flags & M_FRAG)
3943                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3944         }
3945
3946         if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
3947             sc->bge_forced_collapse > 0 &&
3948             (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
3949                 /*
3950                  * Forcedly collapse mbuf chains to overcome hardware
3951                  * limitation which only support a single outstanding
3952                  * DMA read operation.
3953                  */
3954                 if (sc->bge_forced_collapse == 1)
3955                         m = m_defrag(m, M_DONTWAIT);
3956                 else
3957                         m = m_collapse(m, M_DONTWAIT, sc->bge_forced_collapse);
3958                 if (m == NULL)
3959                         m = *m_head;
3960                 *m_head = m;
3961         }
3962
3963         map = sc->bge_cdata.bge_tx_dmamap[idx];
3964         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
3965             &nsegs, BUS_DMA_NOWAIT);
3966         if (error == EFBIG) {
3967                 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW);
3968                 if (m == NULL) {
3969                         m_freem(*m_head);
3970                         *m_head = NULL;
3971                         return (ENOBUFS);
3972                 }
3973                 *m_head = m;
3974                 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
3975                     m, segs, &nsegs, BUS_DMA_NOWAIT);
3976                 if (error) {
3977                         m_freem(m);
3978                         *m_head = NULL;
3979                         return (error);
3980                 }
3981         } else if (error != 0)
3982                 return (error);
3983
3984         /* Check if we have enough free send BDs. */
3985         if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
3986                 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
3987                 return (ENOBUFS);
3988         }
3989
3990         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3991
3992 #if __FreeBSD_version > 700022
3993         if (m->m_flags & M_VLANTAG) {
3994                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
3995                 vlan_tag = m->m_pkthdr.ether_vtag;
3996         }
3997 #else
3998         {
3999                 struct m_tag            *mtag;
4000
4001                 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) {
4002                         csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
4003                         vlan_tag = VLAN_TAG_VALUE(mtag);
4004                 }
4005         }
4006 #endif
4007         for (i = 0; ; i++) {
4008                 d = &sc->bge_ldata.bge_tx_ring[idx];
4009                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
4010                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
4011                 d->bge_len = segs[i].ds_len;
4012                 d->bge_flags = csum_flags;
4013                 d->bge_vlan_tag = vlan_tag;
4014                 d->bge_mss = mss;
4015                 if (i == nsegs - 1)
4016                         break;
4017                 BGE_INC(idx, BGE_TX_RING_CNT);
4018         }
4019
4020         /* Mark the last segment as end of packet... */
4021         d->bge_flags |= BGE_TXBDFLAG_END;
4022
4023         /*
4024          * Insure that the map for this transmission
4025          * is placed at the array index of the last descriptor
4026          * in this chain.
4027          */
4028         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
4029         sc->bge_cdata.bge_tx_dmamap[idx] = map;
4030         sc->bge_cdata.bge_tx_chain[idx] = m;
4031         sc->bge_txcnt += nsegs;
4032
4033         BGE_INC(idx, BGE_TX_RING_CNT);
4034         *txidx = idx;
4035
4036         return (0);
4037 }
4038
4039 /*
4040  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4041  * to the mbuf data regions directly in the transmit descriptors.
4042  */
4043 static void
4044 bge_start_locked(struct ifnet *ifp)
4045 {
4046         struct bge_softc *sc;
4047         struct mbuf *m_head;
4048         uint32_t prodidx;
4049         int count;
4050
4051         sc = ifp->if_softc;
4052         BGE_LOCK_ASSERT(sc);
4053
4054         if (!sc->bge_link ||
4055             (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4056             IFF_DRV_RUNNING)
4057                 return;
4058
4059         prodidx = sc->bge_tx_prodidx;
4060
4061         for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
4062                 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
4063                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4064                         break;
4065                 }
4066                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
4067                 if (m_head == NULL)
4068                         break;
4069
4070                 /*
4071                  * XXX
4072                  * The code inside the if() block is never reached since we
4073                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
4074                  * requests to checksum TCP/UDP in a fragmented packet.
4075                  *
4076                  * XXX
4077                  * safety overkill.  If this is a fragmented packet chain
4078                  * with delayed TCP/UDP checksums, then only encapsulate
4079                  * it if we have enough descriptors to handle the entire
4080                  * chain at once.
4081                  * (paranoia -- may not actually be needed)
4082                  */
4083                 if (m_head->m_flags & M_FIRSTFRAG &&
4084                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
4085                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
4086                             m_head->m_pkthdr.csum_data + 16) {
4087                                 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4088                                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4089                                 break;
4090                         }
4091                 }
4092
4093                 /*
4094                  * Pack the data into the transmit ring. If we
4095                  * don't have room, set the OACTIVE flag and wait
4096                  * for the NIC to drain the ring.
4097                  */
4098                 if (bge_encap(sc, &m_head, &prodidx)) {
4099                         if (m_head == NULL)
4100                                 break;
4101                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4102                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4103                         break;
4104                 }
4105                 ++count;
4106
4107                 /*
4108                  * If there's a BPF listener, bounce a copy of this frame
4109                  * to him.
4110                  */
4111 #ifdef ETHER_BPF_MTAP
4112                 ETHER_BPF_MTAP(ifp, m_head);
4113 #else
4114                 BPF_MTAP(ifp, m_head);
4115 #endif
4116         }
4117
4118         if (count > 0) {
4119                 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4120                     sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
4121                 /* Transmit. */
4122                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4123                 /* 5700 b2 errata */
4124                 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
4125                         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4126
4127                 sc->bge_tx_prodidx = prodidx;
4128
4129                 /*
4130                  * Set a timeout in case the chip goes out to lunch.
4131                  */
4132                 sc->bge_timer = 5;
4133         }
4134 }
4135
4136 /*
4137  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4138  * to the mbuf data regions directly in the transmit descriptors.
4139  */
4140 static void
4141 bge_start(struct ifnet *ifp)
4142 {
4143         struct bge_softc *sc;
4144
4145         sc = ifp->if_softc;
4146         BGE_LOCK(sc);
4147         bge_start_locked(ifp);
4148         BGE_UNLOCK(sc);
4149 }
4150
4151 static void
4152 bge_init_locked(struct bge_softc *sc)
4153 {
4154         struct ifnet *ifp;
4155         uint16_t *m;
4156
4157         BGE_LOCK_ASSERT(sc);
4158
4159         ifp = sc->bge_ifp;
4160
4161         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4162                 return;
4163
4164         /* Cancel pending I/O and flush buffers. */
4165         bge_stop(sc);
4166
4167         bge_stop_fw(sc);
4168         bge_sig_pre_reset(sc, BGE_RESET_START);
4169         bge_reset(sc);
4170         bge_sig_legacy(sc, BGE_RESET_START);
4171         bge_sig_post_reset(sc, BGE_RESET_START);
4172
4173         bge_chipinit(sc);
4174
4175         /*
4176          * Init the various state machines, ring
4177          * control blocks and firmware.
4178          */
4179         if (bge_blockinit(sc)) {
4180                 device_printf(sc->bge_dev, "initialization failure\n");
4181                 return;
4182         }
4183
4184         ifp = sc->bge_ifp;
4185
4186         /* Specify MTU. */
4187         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
4188             ETHER_HDR_LEN + ETHER_CRC_LEN +
4189             (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
4190
4191         /* Load our MAC address. */
4192         m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
4193         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
4194         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
4195
4196         /* Program promiscuous mode. */
4197         bge_setpromisc(sc);
4198
4199         /* Program multicast filter. */
4200         bge_setmulti(sc);
4201
4202         /* Program VLAN tag stripping. */
4203         bge_setvlan(sc);
4204
4205         /* Init RX ring. */
4206         if (bge_init_rx_ring_std(sc) != 0) {
4207                 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
4208                 bge_stop(sc);
4209                 return;
4210         }
4211
4212         /*
4213          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
4214          * memory to insure that the chip has in fact read the first
4215          * entry of the ring.
4216          */
4217         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
4218                 uint32_t                v, i;
4219                 for (i = 0; i < 10; i++) {
4220                         DELAY(20);
4221                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
4222                         if (v == (MCLBYTES - ETHER_ALIGN))
4223                                 break;
4224                 }
4225                 if (i == 10)
4226                         device_printf (sc->bge_dev,
4227                             "5705 A0 chip failed to load RX ring\n");
4228         }
4229
4230         /* Init jumbo RX ring. */
4231         if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
4232             (MCLBYTES - ETHER_ALIGN)) {
4233                 if (bge_init_rx_ring_jumbo(sc) != 0) {
4234                         device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
4235                         bge_stop(sc);
4236                         return;
4237                 }
4238         }
4239
4240         /* Init our RX return ring index. */
4241         sc->bge_rx_saved_considx = 0;
4242
4243         /* Init our RX/TX stat counters. */
4244         sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
4245
4246         /* Init TX ring. */
4247         bge_init_tx_ring(sc);
4248
4249         /* Turn on transmitter. */
4250         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
4251
4252         /* Turn on receiver. */
4253         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4254
4255         /* Tell firmware we're alive. */
4256         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4257
4258 #ifdef DEVICE_POLLING
4259         /* Disable interrupts if we are polling. */
4260         if (ifp->if_capenable & IFCAP_POLLING) {
4261                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4262                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4263                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4264         } else
4265 #endif
4266
4267         /* Enable host interrupts. */
4268         {
4269         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
4270         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4271         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4272         }
4273
4274         bge_ifmedia_upd_locked(ifp);
4275
4276         ifp->if_drv_flags |= IFF_DRV_RUNNING;
4277         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4278
4279         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4280 }
4281
4282 static void
4283 bge_init(void *xsc)
4284 {
4285         struct bge_softc *sc = xsc;
4286
4287         BGE_LOCK(sc);
4288         bge_init_locked(sc);
4289         BGE_UNLOCK(sc);
4290 }
4291
4292 /*
4293  * Set media options.
4294  */
4295 static int
4296 bge_ifmedia_upd(struct ifnet *ifp)
4297 {
4298         struct bge_softc *sc = ifp->if_softc;
4299         int res;
4300
4301         BGE_LOCK(sc);
4302         res = bge_ifmedia_upd_locked(ifp);
4303         BGE_UNLOCK(sc);
4304
4305         return (res);
4306 }
4307
4308 static int
4309 bge_ifmedia_upd_locked(struct ifnet *ifp)
4310 {
4311         struct bge_softc *sc = ifp->if_softc;
4312         struct mii_data *mii;
4313         struct mii_softc *miisc;
4314         struct ifmedia *ifm;
4315
4316         BGE_LOCK_ASSERT(sc);
4317
4318         ifm = &sc->bge_ifmedia;
4319
4320         /* If this is a 1000baseX NIC, enable the TBI port. */
4321         if (sc->bge_flags & BGE_FLAG_TBI) {
4322                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
4323                         return (EINVAL);
4324                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
4325                 case IFM_AUTO:
4326                         /*
4327                          * The BCM5704 ASIC appears to have a special
4328                          * mechanism for programming the autoneg
4329                          * advertisement registers in TBI mode.
4330                          */
4331                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4332                                 uint32_t sgdig;
4333                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
4334                                 if (sgdig & BGE_SGDIGSTS_DONE) {
4335                                         CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
4336                                         sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
4337                                         sgdig |= BGE_SGDIGCFG_AUTO |
4338                                             BGE_SGDIGCFG_PAUSE_CAP |
4339                                             BGE_SGDIGCFG_ASYM_PAUSE;
4340                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG,
4341                                             sgdig | BGE_SGDIGCFG_SEND);
4342                                         DELAY(5);
4343                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
4344                                 }
4345                         }
4346                         break;
4347                 case IFM_1000_SX:
4348                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
4349                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
4350                                     BGE_MACMODE_HALF_DUPLEX);
4351                         } else {
4352                                 BGE_SETBIT(sc, BGE_MAC_MODE,
4353                                     BGE_MACMODE_HALF_DUPLEX);
4354                         }
4355                         break;
4356                 default:
4357                         return (EINVAL);
4358                 }
4359                 return (0);
4360         }
4361
4362         sc->bge_link_evt++;
4363         mii = device_get_softc(sc->bge_miibus);
4364         if (mii->mii_instance)
4365                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4366                         mii_phy_reset(miisc);
4367         mii_mediachg(mii);
4368
4369         /*
4370          * Force an interrupt so that we will call bge_link_upd
4371          * if needed and clear any pending link state attention.
4372          * Without this we are not getting any further interrupts
4373          * for link state changes and thus will not UP the link and
4374          * not be able to send in bge_start_locked. The only
4375          * way to get things working was to receive a packet and
4376          * get an RX intr.
4377          * bge_tick should help for fiber cards and we might not
4378          * need to do this here if BGE_FLAG_TBI is set but as
4379          * we poll for fiber anyway it should not harm.
4380          */
4381         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4382             sc->bge_flags & BGE_FLAG_5788)
4383                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4384         else
4385                 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4386
4387         return (0);
4388 }
4389
4390 /*
4391  * Report current media status.
4392  */
4393 static void
4394 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4395 {
4396         struct bge_softc *sc = ifp->if_softc;
4397         struct mii_data *mii;
4398
4399         BGE_LOCK(sc);
4400
4401         if (sc->bge_flags & BGE_FLAG_TBI) {
4402                 ifmr->ifm_status = IFM_AVALID;
4403                 ifmr->ifm_active = IFM_ETHER;
4404                 if (CSR_READ_4(sc, BGE_MAC_STS) &
4405                     BGE_MACSTAT_TBI_PCS_SYNCHED)
4406                         ifmr->ifm_status |= IFM_ACTIVE;
4407                 else {
4408                         ifmr->ifm_active |= IFM_NONE;
4409                         BGE_UNLOCK(sc);
4410                         return;
4411                 }
4412                 ifmr->ifm_active |= IFM_1000_SX;
4413                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
4414                         ifmr->ifm_active |= IFM_HDX;
4415                 else
4416                         ifmr->ifm_active |= IFM_FDX;
4417                 BGE_UNLOCK(sc);
4418                 return;
4419         }
4420
4421         mii = device_get_softc(sc->bge_miibus);
4422         mii_pollstat(mii);
4423         ifmr->ifm_active = mii->mii_media_active;
4424         ifmr->ifm_status = mii->mii_media_status;
4425
4426         BGE_UNLOCK(sc);
4427 }
4428
4429 static int
4430 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
4431 {
4432         struct bge_softc *sc = ifp->if_softc;
4433         struct ifreq *ifr = (struct ifreq *) data;
4434         struct mii_data *mii;
4435         int flags, mask, error = 0;
4436
4437         switch (command) {
4438         case SIOCSIFMTU:
4439                 if (ifr->ifr_mtu < ETHERMIN ||
4440                     ((BGE_IS_JUMBO_CAPABLE(sc)) &&
4441                     ifr->ifr_mtu > BGE_JUMBO_MTU) ||
4442                     ((!BGE_IS_JUMBO_CAPABLE(sc)) &&
4443                     ifr->ifr_mtu > ETHERMTU))
4444                         error = EINVAL;
4445                 else if (ifp->if_mtu != ifr->ifr_mtu) {
4446                         ifp->if_mtu = ifr->ifr_mtu;
4447                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4448                         bge_init(sc);
4449                 }
4450                 break;
4451         case SIOCSIFFLAGS:
4452                 BGE_LOCK(sc);
4453                 if (ifp->if_flags & IFF_UP) {
4454                         /*
4455                          * If only the state of the PROMISC flag changed,
4456                          * then just use the 'set promisc mode' command
4457                          * instead of reinitializing the entire NIC. Doing
4458                          * a full re-init means reloading the firmware and
4459                          * waiting for it to start up, which may take a
4460                          * second or two.  Similarly for ALLMULTI.
4461                          */
4462                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4463                                 flags = ifp->if_flags ^ sc->bge_if_flags;
4464                                 if (flags & IFF_PROMISC)
4465                                         bge_setpromisc(sc);
4466                                 if (flags & IFF_ALLMULTI)
4467                                         bge_setmulti(sc);
4468                         } else
4469                                 bge_init_locked(sc);
4470                 } else {
4471                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4472                                 bge_stop(sc);
4473                         }
4474                 }
4475                 sc->bge_if_flags = ifp->if_flags;
4476                 BGE_UNLOCK(sc);
4477                 error = 0;
4478                 break;
4479         case SIOCADDMULTI:
4480         case SIOCDELMULTI:
4481                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4482                         BGE_LOCK(sc);
4483                         bge_setmulti(sc);
4484                         BGE_UNLOCK(sc);
4485                         error = 0;
4486                 }
4487                 break;
4488         case SIOCSIFMEDIA:
4489         case SIOCGIFMEDIA:
4490                 if (sc->bge_flags & BGE_FLAG_TBI) {
4491                         error = ifmedia_ioctl(ifp, ifr,
4492                             &sc->bge_ifmedia, command);
4493                 } else {
4494                         mii = device_get_softc(sc->bge_miibus);
4495                         error = ifmedia_ioctl(ifp, ifr,
4496                             &mii->mii_media, command);
4497                 }
4498                 break;
4499         case SIOCSIFCAP:
4500                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
4501 #ifdef DEVICE_POLLING
4502                 if (mask & IFCAP_POLLING) {
4503                         if (ifr->ifr_reqcap & IFCAP_POLLING) {
4504                                 error = ether_poll_register(bge_poll, ifp);
4505                                 if (error)
4506                                         return (error);
4507                                 BGE_LOCK(sc);
4508                                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4509                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4510                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4511                                 ifp->if_capenable |= IFCAP_POLLING;
4512                                 BGE_UNLOCK(sc);
4513                         } else {
4514                                 error = ether_poll_deregister(ifp);
4515                                 /* Enable interrupt even in error case */
4516                                 BGE_LOCK(sc);
4517                                 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
4518                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4519                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4520                                 ifp->if_capenable &= ~IFCAP_POLLING;
4521                                 BGE_UNLOCK(sc);
4522                         }
4523                 }
4524 #endif
4525                 if (mask & IFCAP_HWCSUM) {
4526                         ifp->if_capenable ^= IFCAP_HWCSUM;
4527                         if (IFCAP_HWCSUM & ifp->if_capenable &&
4528                             IFCAP_HWCSUM & ifp->if_capabilities)
4529                                 ifp->if_hwassist |= BGE_CSUM_FEATURES;
4530                         else
4531                                 ifp->if_hwassist &= ~BGE_CSUM_FEATURES;
4532                 }
4533
4534                 if ((mask & IFCAP_TSO4) != 0 &&
4535                     (ifp->if_capabilities & IFCAP_TSO4) != 0) {
4536                         ifp->if_capenable ^= IFCAP_TSO4;
4537                         if ((ifp->if_capenable & IFCAP_TSO4) != 0)
4538                                 ifp->if_hwassist |= CSUM_TSO;
4539                         else
4540                                 ifp->if_hwassist &= ~CSUM_TSO;
4541                 }
4542
4543                 if (mask & IFCAP_VLAN_MTU) {
4544                         ifp->if_capenable ^= IFCAP_VLAN_MTU;
4545                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4546                         bge_init(sc);
4547                 }
4548
4549                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
4550                     (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
4551                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
4552                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
4553                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
4554                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
4555                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
4556                                 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
4557                         BGE_LOCK(sc);
4558                         bge_setvlan(sc);
4559                         BGE_UNLOCK(sc);
4560                 }
4561 #ifdef VLAN_CAPABILITIES
4562                 VLAN_CAPABILITIES(ifp);
4563 #endif
4564                 break;
4565         default:
4566                 error = ether_ioctl(ifp, command, data);
4567                 break;
4568         }
4569
4570         return (error);
4571 }
4572
4573 static void
4574 bge_watchdog(struct bge_softc *sc)
4575 {
4576         struct ifnet *ifp;
4577
4578         BGE_LOCK_ASSERT(sc);
4579
4580         if (sc->bge_timer == 0 || --sc->bge_timer)
4581                 return;
4582
4583         ifp = sc->bge_ifp;
4584
4585         if_printf(ifp, "watchdog timeout -- resetting\n");
4586
4587         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4588         bge_init_locked(sc);
4589
4590         ifp->if_oerrors++;
4591 }
4592
4593 /*
4594  * Stop the adapter and free any mbufs allocated to the
4595  * RX and TX lists.
4596  */
4597 static void
4598 bge_stop(struct bge_softc *sc)
4599 {
4600         struct ifnet *ifp;
4601
4602         BGE_LOCK_ASSERT(sc);
4603
4604         ifp = sc->bge_ifp;
4605
4606         callout_stop(&sc->bge_stat_ch);
4607
4608         /* Disable host interrupts. */
4609         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4610         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4611
4612         /*
4613          * Tell firmware we're shutting down.
4614          */
4615         bge_stop_fw(sc);
4616         bge_sig_pre_reset(sc, BGE_RESET_STOP);
4617
4618         /*
4619          * Disable all of the receiver blocks.
4620          */
4621         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4622         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
4623         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
4624         if (!(BGE_IS_5705_PLUS(sc)))
4625                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
4626         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
4627         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
4628         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
4629
4630         /*
4631          * Disable all of the transmit blocks.
4632          */
4633         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
4634         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
4635         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
4636         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
4637         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
4638         if (!(BGE_IS_5705_PLUS(sc)))
4639                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
4640         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
4641
4642         /*
4643          * Shut down all of the memory managers and related
4644          * state machines.
4645          */
4646         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
4647         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
4648         if (!(BGE_IS_5705_PLUS(sc)))
4649                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
4650         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
4651         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
4652         if (!(BGE_IS_5705_PLUS(sc))) {
4653                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
4654                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4655         }
4656
4657         bge_reset(sc);
4658         bge_sig_legacy(sc, BGE_RESET_STOP);
4659         bge_sig_post_reset(sc, BGE_RESET_STOP);
4660
4661         /*
4662          * Keep the ASF firmware running if up.
4663          */
4664         if (sc->bge_asf_mode & ASF_STACKUP)
4665                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4666         else
4667                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4668
4669         /* Free the RX lists. */
4670         bge_free_rx_ring_std(sc);
4671
4672         /* Free jumbo RX list. */
4673         if (BGE_IS_JUMBO_CAPABLE(sc))
4674                 bge_free_rx_ring_jumbo(sc);
4675
4676         /* Free TX buffers. */
4677         bge_free_tx_ring(sc);
4678
4679         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
4680
4681         /* Clear MAC's link state (PHY may still have link UP). */
4682         if (bootverbose && sc->bge_link)
4683                 if_printf(sc->bge_ifp, "link DOWN\n");
4684         sc->bge_link = 0;
4685
4686         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4687 }
4688
4689 /*
4690  * Stop all chip I/O so that the kernel's probe routines don't
4691  * get confused by errant DMAs when rebooting.
4692  */
4693 static int
4694 bge_shutdown(device_t dev)
4695 {
4696         struct bge_softc *sc;
4697
4698         sc = device_get_softc(dev);
4699         BGE_LOCK(sc);
4700         bge_stop(sc);
4701         bge_reset(sc);
4702         BGE_UNLOCK(sc);
4703
4704         return (0);
4705 }
4706
4707 static int
4708 bge_suspend(device_t dev)
4709 {
4710         struct bge_softc *sc;
4711
4712         sc = device_get_softc(dev);
4713         BGE_LOCK(sc);
4714         bge_stop(sc);
4715         BGE_UNLOCK(sc);
4716
4717         return (0);
4718 }
4719
4720 static int
4721 bge_resume(device_t dev)
4722 {
4723         struct bge_softc *sc;
4724         struct ifnet *ifp;
4725
4726         sc = device_get_softc(dev);
4727         BGE_LOCK(sc);
4728         ifp = sc->bge_ifp;
4729         if (ifp->if_flags & IFF_UP) {
4730                 bge_init_locked(sc);
4731                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4732                         bge_start_locked(ifp);
4733         }
4734         BGE_UNLOCK(sc);
4735
4736         return (0);
4737 }
4738
4739 static void
4740 bge_link_upd(struct bge_softc *sc)
4741 {
4742         struct mii_data *mii;
4743         uint32_t link, status;
4744
4745         BGE_LOCK_ASSERT(sc);
4746
4747         /* Clear 'pending link event' flag. */
4748         sc->bge_link_evt = 0;
4749
4750         /*
4751          * Process link state changes.
4752          * Grrr. The link status word in the status block does
4753          * not work correctly on the BCM5700 rev AX and BX chips,
4754          * according to all available information. Hence, we have
4755          * to enable MII interrupts in order to properly obtain
4756          * async link changes. Unfortunately, this also means that
4757          * we have to read the MAC status register to detect link
4758          * changes, thereby adding an additional register access to
4759          * the interrupt handler.
4760          *
4761          * XXX: perhaps link state detection procedure used for
4762          * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
4763          */
4764
4765         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4766             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
4767                 status = CSR_READ_4(sc, BGE_MAC_STS);
4768                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
4769                         mii = device_get_softc(sc->bge_miibus);
4770                         mii_pollstat(mii);
4771                         if (!sc->bge_link &&
4772                             mii->mii_media_status & IFM_ACTIVE &&
4773                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4774                                 sc->bge_link++;
4775                                 if (bootverbose)
4776                                         if_printf(sc->bge_ifp, "link UP\n");
4777                         } else if (sc->bge_link &&
4778                             (!(mii->mii_media_status & IFM_ACTIVE) ||
4779                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4780                                 sc->bge_link = 0;
4781                                 if (bootverbose)
4782                                         if_printf(sc->bge_ifp, "link DOWN\n");
4783                         }
4784
4785                         /* Clear the interrupt. */
4786                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
4787                             BGE_EVTENB_MI_INTERRUPT);
4788                         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4789                         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
4790                             BRGPHY_INTRS);
4791                 }
4792                 return;
4793         }
4794
4795         if (sc->bge_flags & BGE_FLAG_TBI) {
4796                 status = CSR_READ_4(sc, BGE_MAC_STS);
4797                 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4798                         if (!sc->bge_link) {
4799                                 sc->bge_link++;
4800                                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
4801                                         BGE_CLRBIT(sc, BGE_MAC_MODE,
4802                                             BGE_MACMODE_TBI_SEND_CFGS);
4803                                 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4804                                 if (bootverbose)
4805                                         if_printf(sc->bge_ifp, "link UP\n");
4806                                 if_link_state_change(sc->bge_ifp,
4807                                     LINK_STATE_UP);
4808                         }
4809                 } else if (sc->bge_link) {
4810                         sc->bge_link = 0;
4811                         if (bootverbose)
4812                                 if_printf(sc->bge_ifp, "link DOWN\n");
4813                         if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
4814                 }
4815         } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
4816                 /*
4817                  * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
4818                  * in status word always set. Workaround this bug by reading
4819                  * PHY link status directly.
4820                  */
4821                 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
4822
4823                 if (link != sc->bge_link ||
4824                     sc->bge_asicrev == BGE_ASICREV_BCM5700) {
4825                         mii = device_get_softc(sc->bge_miibus);
4826                         mii_pollstat(mii);
4827                         if (!sc->bge_link &&
4828                             mii->mii_media_status & IFM_ACTIVE &&
4829                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4830                                 sc->bge_link++;
4831                                 if (bootverbose)
4832                                         if_printf(sc->bge_ifp, "link UP\n");
4833                         } else if (sc->bge_link &&
4834                             (!(mii->mii_media_status & IFM_ACTIVE) ||
4835                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4836                                 sc->bge_link = 0;
4837                                 if (bootverbose)
4838                                         if_printf(sc->bge_ifp, "link DOWN\n");
4839                         }
4840                 }
4841         } else {
4842                 /*
4843                  * Discard link events for MII/GMII controllers
4844                  * if MI auto-polling is disabled.
4845                  */
4846         }
4847
4848         /* Clear the attention. */
4849         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4850             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4851             BGE_MACSTAT_LINK_CHANGED);
4852 }
4853
4854 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
4855         SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
4856             sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
4857             desc)
4858
4859 static void
4860 bge_add_sysctls(struct bge_softc *sc)
4861 {
4862         struct sysctl_ctx_list *ctx;
4863         struct sysctl_oid_list *children, *schildren;
4864         struct sysctl_oid *tree;
4865
4866         ctx = device_get_sysctl_ctx(sc->bge_dev);
4867         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
4868
4869 #ifdef BGE_REGISTER_DEBUG
4870         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
4871             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
4872             "Debug Information");
4873
4874         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
4875             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
4876             "Register Read");
4877
4878         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
4879             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
4880             "Memory Read");
4881
4882 #endif
4883
4884         /*
4885          * A common design characteristic for many Broadcom client controllers
4886          * is that they only support a single outstanding DMA read operation
4887          * on the PCIe bus. This means that it will take twice as long to fetch
4888          * a TX frame that is split into header and payload buffers as it does
4889          * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
4890          * these controllers, coalescing buffers to reduce the number of memory
4891          * reads is effective way to get maximum performance(about 940Mbps).
4892          * Without collapsing TX buffers the maximum TCP bulk transfer
4893          * performance is about 850Mbps. However forcing coalescing mbufs
4894          * consumes a lot of CPU cycles, so leave it off by default.
4895          */
4896         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
4897             CTLFLAG_RW, &sc->bge_forced_collapse, 0,
4898             "Number of fragmented TX buffers of a frame allowed before "
4899             "forced collapsing");
4900         resource_int_value(device_get_name(sc->bge_dev),
4901             device_get_unit(sc->bge_dev), "forced_collapse",
4902             &sc->bge_forced_collapse);
4903
4904         if (BGE_IS_5705_PLUS(sc))
4905                 return;
4906
4907         tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
4908             NULL, "BGE Statistics");
4909         schildren = children = SYSCTL_CHILDREN(tree);
4910         BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
4911             children, COSFramesDroppedDueToFilters,
4912             "FramesDroppedDueToFilters");
4913         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
4914             children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
4915         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
4916             children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
4917         BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
4918             children, nicNoMoreRxBDs, "NoMoreRxBDs");
4919         BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
4920             children, ifInDiscards, "InputDiscards");
4921         BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
4922             children, ifInErrors, "InputErrors");
4923         BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
4924             children, nicRecvThresholdHit, "RecvThresholdHit");
4925         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
4926             children, nicDmaReadQueueFull, "DmaReadQueueFull");
4927         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
4928             children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
4929         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
4930             children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
4931         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
4932             children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
4933         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
4934             children, nicRingStatusUpdate, "RingStatusUpdate");
4935         BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
4936             children, nicInterrupts, "Interrupts");
4937         BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
4938             children, nicAvoidedInterrupts, "AvoidedInterrupts");
4939         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
4940             children, nicSendThresholdHit, "SendThresholdHit");
4941
4942         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
4943             NULL, "BGE RX Statistics");
4944         children = SYSCTL_CHILDREN(tree);
4945         BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
4946             children, rxstats.ifHCInOctets, "Octets");
4947         BGE_SYSCTL_STAT(sc, ctx, "Fragments",
4948             children, rxstats.etherStatsFragments, "Fragments");
4949         BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
4950             children, rxstats.ifHCInUcastPkts, "UcastPkts");
4951         BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
4952             children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
4953         BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
4954             children, rxstats.dot3StatsFCSErrors, "FCSErrors");
4955         BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
4956             children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
4957         BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
4958             children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
4959         BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
4960             children, rxstats.xoffPauseFramesReceived,
4961             "xoffPauseFramesReceived");
4962         BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
4963             children, rxstats.macControlFramesReceived,
4964             "ControlFramesReceived");
4965         BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
4966             children, rxstats.xoffStateEntered, "xoffStateEntered");
4967         BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
4968             children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
4969         BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
4970             children, rxstats.etherStatsJabbers, "Jabbers");
4971         BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
4972             children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
4973         BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
4974             children, rxstats.inRangeLengthError, "inRangeLengthError");
4975         BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
4976             children, rxstats.outRangeLengthError, "outRangeLengthError");
4977
4978         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
4979             NULL, "BGE TX Statistics");
4980         children = SYSCTL_CHILDREN(tree);
4981         BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
4982             children, txstats.ifHCOutOctets, "Octets");
4983         BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
4984             children, txstats.etherStatsCollisions, "Collisions");
4985         BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
4986             children, txstats.outXonSent, "XonSent");
4987         BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
4988             children, txstats.outXoffSent, "XoffSent");
4989         BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
4990             children, txstats.flowControlDone, "flowControlDone");
4991         BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
4992             children, txstats.dot3StatsInternalMacTransmitErrors,
4993             "InternalMacTransmitErrors");
4994         BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
4995             children, txstats.dot3StatsSingleCollisionFrames,
4996             "SingleCollisionFrames");
4997         BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
4998             children, txstats.dot3StatsMultipleCollisionFrames,
4999             "MultipleCollisionFrames");
5000         BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
5001             children, txstats.dot3StatsDeferredTransmissions,
5002             "DeferredTransmissions");
5003         BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
5004             children, txstats.dot3StatsExcessiveCollisions,
5005             "ExcessiveCollisions");
5006         BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
5007             children, txstats.dot3StatsLateCollisions,
5008             "LateCollisions");
5009         BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
5010             children, txstats.ifHCOutUcastPkts, "UcastPkts");
5011         BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
5012             children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
5013         BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
5014             children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
5015         BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
5016             children, txstats.dot3StatsCarrierSenseErrors,
5017             "CarrierSenseErrors");
5018         BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
5019             children, txstats.ifOutDiscards, "Discards");
5020         BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
5021             children, txstats.ifOutErrors, "Errors");
5022 }
5023
5024 static int
5025 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
5026 {
5027         struct bge_softc *sc;
5028         uint32_t result;
5029         int offset;
5030
5031         sc = (struct bge_softc *)arg1;
5032         offset = arg2;
5033         result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
5034             offsetof(bge_hostaddr, bge_addr_lo));
5035         return (sysctl_handle_int(oidp, &result, 0, req));
5036 }
5037
5038 #ifdef BGE_REGISTER_DEBUG
5039 static int
5040 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
5041 {
5042         struct bge_softc *sc;
5043         uint16_t *sbdata;
5044         int error;
5045         int result;
5046         int i, j;
5047
5048         result = -1;
5049         error = sysctl_handle_int(oidp, &result, 0, req);
5050         if (error || (req->newptr == NULL))
5051                 return (error);
5052
5053         if (result == 1) {
5054                 sc = (struct bge_softc *)arg1;
5055
5056                 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
5057                 printf("Status Block:\n");
5058                 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) {
5059                         printf("%06x:", i);
5060                         for (j = 0; j < 8; j++) {
5061                                 printf(" %04x", sbdata[i]);
5062                                 i += 4;
5063                         }
5064                         printf("\n");
5065                 }
5066
5067                 printf("Registers:\n");
5068                 for (i = 0x800; i < 0xA00; ) {
5069                         printf("%06x:", i);
5070                         for (j = 0; j < 8; j++) {
5071                                 printf(" %08x", CSR_READ_4(sc, i));
5072                                 i += 4;
5073                         }
5074                         printf("\n");
5075                 }
5076
5077                 printf("Hardware Flags:\n");
5078                 if (BGE_IS_5755_PLUS(sc))
5079                         printf(" - 5755 Plus\n");
5080                 if (BGE_IS_575X_PLUS(sc))
5081                         printf(" - 575X Plus\n");
5082                 if (BGE_IS_5705_PLUS(sc))
5083                         printf(" - 5705 Plus\n");
5084                 if (BGE_IS_5714_FAMILY(sc))
5085                         printf(" - 5714 Family\n");
5086                 if (BGE_IS_5700_FAMILY(sc))
5087                         printf(" - 5700 Family\n");
5088                 if (sc->bge_flags & BGE_FLAG_JUMBO)
5089                         printf(" - Supports Jumbo Frames\n");
5090                 if (sc->bge_flags & BGE_FLAG_PCIX)
5091                         printf(" - PCI-X Bus\n");
5092                 if (sc->bge_flags & BGE_FLAG_PCIE)
5093                         printf(" - PCI Express Bus\n");
5094                 if (sc->bge_flags & BGE_FLAG_NO_3LED)
5095                         printf(" - No 3 LEDs\n");
5096                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
5097                         printf(" - RX Alignment Bug\n");
5098         }
5099
5100         return (error);
5101 }
5102
5103 static int
5104 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5105 {
5106         struct bge_softc *sc;
5107         int error;
5108         uint16_t result;
5109         uint32_t val;
5110
5111         result = -1;
5112         error = sysctl_handle_int(oidp, &result, 0, req);
5113         if (error || (req->newptr == NULL))
5114                 return (error);
5115
5116         if (result < 0x8000) {
5117                 sc = (struct bge_softc *)arg1;
5118                 val = CSR_READ_4(sc, result);
5119                 printf("reg 0x%06X = 0x%08X\n", result, val);
5120         }
5121
5122         return (error);
5123 }
5124
5125 static int
5126 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
5127 {
5128         struct bge_softc *sc;
5129         int error;
5130         uint16_t result;
5131         uint32_t val;
5132
5133         result = -1;
5134         error = sysctl_handle_int(oidp, &result, 0, req);
5135         if (error || (req->newptr == NULL))
5136                 return (error);
5137
5138         if (result < 0x8000) {
5139                 sc = (struct bge_softc *)arg1;
5140                 val = bge_readmem_ind(sc, result);
5141                 printf("mem 0x%06X = 0x%08X\n", result, val);
5142         }
5143
5144         return (error);
5145 }
5146 #endif
5147
5148 static int
5149 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
5150 {
5151
5152         if (sc->bge_flags & BGE_FLAG_EADDR)
5153                 return (1);
5154
5155 #ifdef __sparc64__
5156         OF_getetheraddr(sc->bge_dev, ether_addr);
5157         return (0);
5158 #endif
5159         return (1);
5160 }
5161
5162 static int
5163 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
5164 {
5165         uint32_t mac_addr;
5166
5167         mac_addr = bge_readmem_ind(sc, 0x0c14);
5168         if ((mac_addr >> 16) == 0x484b) {
5169                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
5170                 ether_addr[1] = (uint8_t)mac_addr;
5171                 mac_addr = bge_readmem_ind(sc, 0x0c18);
5172                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
5173                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
5174                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
5175                 ether_addr[5] = (uint8_t)mac_addr;
5176                 return (0);
5177         }
5178         return (1);
5179 }
5180
5181 static int
5182 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
5183 {
5184         int mac_offset = BGE_EE_MAC_OFFSET;
5185
5186         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
5187                 mac_offset = BGE_EE_MAC_OFFSET_5906;
5188
5189         return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
5190             ETHER_ADDR_LEN));
5191 }
5192
5193 static int
5194 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
5195 {
5196
5197         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
5198                 return (1);
5199
5200         return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
5201            ETHER_ADDR_LEN));
5202 }
5203
5204 static int
5205 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
5206 {
5207         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
5208                 /* NOTE: Order is critical */
5209                 bge_get_eaddr_fw,
5210                 bge_get_eaddr_mem,
5211                 bge_get_eaddr_nvram,
5212                 bge_get_eaddr_eeprom,
5213                 NULL
5214         };
5215         const bge_eaddr_fcn_t *func;
5216
5217         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
5218                 if ((*func)(sc, eaddr) == 0)
5219                         break;
5220         }
5221         return (*func == NULL ? ENXIO : 0);
5222 }