sys/dev/bge/if_bge.c

   1 /*-
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/cdefs.h>
  35 __FBSDID("$FreeBSD$");
  36
  37 /*
  38  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  39  *
  40  * The Broadcom BCM5700 is based on technology originally developed by
  41  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  42  * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
  43  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  44  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  45  * frames, highly configurable RX filtering, and 16 RX and TX queues
  46  * (which, along with RX filter rules, can be used for QOS applications).
  47  * Other features, such as TCP segmentation, may be available as part
  48  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  49  * firmware images can be stored in hardware and need not be compiled
  50  * into the driver.
  51  *
  52  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  53  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  54  *
  55  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  56  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  57  * does not support external SSRAM.
  58  *
  59  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  60  * brand name, which is functionally similar but lacks PCI-X support.
  61  *
  62  * Without external SSRAM, you can only have at most 4 TX rings,
  63  * and the use of the mini RX ring is disabled. This seems to imply
  64  * that these features are simply not available on the BCM5701. As a
  65  * result, this driver does not implement any support for the mini RX
  66  * ring.
  67  */
  68
  69 #ifdef HAVE_KERNEL_OPTION_HEADERS
  70 #include "opt_device_polling.h"
  71 #endif
  72
  73 #include <sys/param.h>
  74 #include <sys/endian.h>
  75 #include <sys/systm.h>
  76 #include <sys/sockio.h>
  77 #include <sys/mbuf.h>
  78 #include <sys/malloc.h>
  79 #include <sys/kernel.h>
  80 #include <sys/module.h>
  81 #include <sys/socket.h>
  82 #include <sys/sysctl.h>
  83 #include <sys/taskqueue.h>
  84
  85 #include <net/if.h>
  86 #include <net/if_arp.h>
  87 #include <net/ethernet.h>
  88 #include <net/if_dl.h>
  89 #include <net/if_media.h>
  90
  91 #include <net/bpf.h>
  92
  93 #include <net/if_types.h>
  94 #include <net/if_vlan_var.h>
  95
  96 #include <netinet/in_systm.h>
  97 #include <netinet/in.h>
  98 #include <netinet/ip.h>
  99 #include <netinet/tcp.h>
 100
 101 #include <machine/bus.h>
 102 #include <machine/resource.h>
 103 #include <sys/bus.h>
 104 #include <sys/rman.h>
 105
 106 #include <dev/mii/mii.h>
 107 #include <dev/mii/miivar.h>
 108 #include "miidevs.h"
 109 #include <dev/mii/brgphyreg.h>
 110
 111 #ifdef __sparc64__
 112 #include <dev/ofw/ofw_bus.h>
 113 #include <dev/ofw/openfirm.h>
 114 #include <machine/ofw_machdep.h>
 115 #include <machine/ver.h>
 116 #endif
 117
 118 #include <dev/pci/pcireg.h>
 119 #include <dev/pci/pcivar.h>
 120
 121 #include <dev/bge/if_bgereg.h>
 122
 123 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP)
 124 #define ETHER_MIN_NOPAD         (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
 125
 126 MODULE_DEPEND(bge, pci, 1, 1, 1);
 127 MODULE_DEPEND(bge, ether, 1, 1, 1);
 128 MODULE_DEPEND(bge, miibus, 1, 1, 1);
 129
 130 /* "device miibus" required.  See GENERIC if you get errors here. */
 131 #include "miibus_if.h"
 132
 133 /*
 134  * Various supported device vendors/types and their names. Note: the
 135  * spec seems to indicate that the hardware still has Alteon's vendor
 136  * ID burned into it, though it will always be overriden by the vendor
 137  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 138  */
 139 static const struct bge_type {
 140         uint16_t        bge_vid;
 141         uint16_t        bge_did;
 142 } const bge_devs[] = {
 143         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5700 },
 144         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5701 },
 145
 146         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1000 },
 147         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1002 },
 148         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC9100 },
 149
 150         { APPLE_VENDORID,       APPLE_DEVICE_BCM5701 },
 151
 152         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5700 },
 153         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5701 },
 154         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702 },
 155         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702_ALT },
 156         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702X },
 157         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703 },
 158         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703_ALT },
 159         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703X },
 160         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704C },
 161         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S },
 162         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S_ALT },
 163         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705 },
 164         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705F },
 165         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705K },
 166         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M },
 167         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M_ALT },
 168         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714C },
 169         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714S },
 170         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715 },
 171         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715S },
 172         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5717 },
 173         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5718 },
 174         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5719 },
 175         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5720 },
 176         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5721 },
 177         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5722 },
 178         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5723 },
 179         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750 },
 180         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750M },
 181         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751 },
 182         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751F },
 183         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751M },
 184         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752 },
 185         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752M },
 186         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753 },
 187         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753F },
 188         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753M },
 189         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754 },
 190         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754M },
 191         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755 },
 192         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755M },
 193         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5756 },
 194         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761 },
 195         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761E },
 196         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761S },
 197         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761SE },
 198         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5764 },
 199         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780 },
 200         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780S },
 201         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5781 },
 202         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5782 },
 203         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5784 },
 204         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785F },
 205         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785G },
 206         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5786 },
 207         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787 },
 208         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787F },
 209         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787M },
 210         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5788 },
 211         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5789 },
 212         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901 },
 213         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901A2 },
 214         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5903M },
 215         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906 },
 216         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906M },
 217         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57760 },
 218         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57761 },
 219         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57765 },
 220         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57780 },
 221         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57781 },
 222         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57785 },
 223         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57788 },
 224         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57790 },
 225         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57791 },
 226         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57795 },
 227
 228         { SK_VENDORID,          SK_DEVICEID_ALTIMA },
 229
 230         { TC_VENDORID,          TC_DEVICEID_3C996 },
 231
 232         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE4 },
 233         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE5 },
 234         { FJTSU_VENDORID,       FJTSU_DEVICEID_PP250450 },
 235
 236         { 0, 0 }
 237 };
 238
 239 static const struct bge_vendor {
 240         uint16_t        v_id;
 241         const char      *v_name;
 242 } const bge_vendors[] = {
 243         { ALTEON_VENDORID,      "Alteon" },
 244         { ALTIMA_VENDORID,      "Altima" },
 245         { APPLE_VENDORID,       "Apple" },
 246         { BCOM_VENDORID,        "Broadcom" },
 247         { SK_VENDORID,          "SysKonnect" },
 248         { TC_VENDORID,          "3Com" },
 249         { FJTSU_VENDORID,       "Fujitsu" },
 250
 251         { 0, NULL }
 252 };
 253
 254 static const struct bge_revision {
 255         uint32_t        br_chipid;
 256         const char      *br_name;
 257 } const bge_revisions[] = {
 258         { BGE_CHIPID_BCM5700_A0,        "BCM5700 A0" },
 259         { BGE_CHIPID_BCM5700_A1,        "BCM5700 A1" },
 260         { BGE_CHIPID_BCM5700_B0,        "BCM5700 B0" },
 261         { BGE_CHIPID_BCM5700_B1,        "BCM5700 B1" },
 262         { BGE_CHIPID_BCM5700_B2,        "BCM5700 B2" },
 263         { BGE_CHIPID_BCM5700_B3,        "BCM5700 B3" },
 264         { BGE_CHIPID_BCM5700_ALTIMA,    "BCM5700 Altima" },
 265         { BGE_CHIPID_BCM5700_C0,        "BCM5700 C0" },
 266         { BGE_CHIPID_BCM5701_A0,        "BCM5701 A0" },
 267         { BGE_CHIPID_BCM5701_B0,        "BCM5701 B0" },
 268         { BGE_CHIPID_BCM5701_B2,        "BCM5701 B2" },
 269         { BGE_CHIPID_BCM5701_B5,        "BCM5701 B5" },
 270         { BGE_CHIPID_BCM5703_A0,        "BCM5703 A0" },
 271         { BGE_CHIPID_BCM5703_A1,        "BCM5703 A1" },
 272         { BGE_CHIPID_BCM5703_A2,        "BCM5703 A2" },
 273         { BGE_CHIPID_BCM5703_A3,        "BCM5703 A3" },
 274         { BGE_CHIPID_BCM5703_B0,        "BCM5703 B0" },
 275         { BGE_CHIPID_BCM5704_A0,        "BCM5704 A0" },
 276         { BGE_CHIPID_BCM5704_A1,        "BCM5704 A1" },
 277         { BGE_CHIPID_BCM5704_A2,        "BCM5704 A2" },
 278         { BGE_CHIPID_BCM5704_A3,        "BCM5704 A3" },
 279         { BGE_CHIPID_BCM5704_B0,        "BCM5704 B0" },
 280         { BGE_CHIPID_BCM5705_A0,        "BCM5705 A0" },
 281         { BGE_CHIPID_BCM5705_A1,        "BCM5705 A1" },
 282         { BGE_CHIPID_BCM5705_A2,        "BCM5705 A2" },
 283         { BGE_CHIPID_BCM5705_A3,        "BCM5705 A3" },
 284         { BGE_CHIPID_BCM5750_A0,        "BCM5750 A0" },
 285         { BGE_CHIPID_BCM5750_A1,        "BCM5750 A1" },
 286         { BGE_CHIPID_BCM5750_A3,        "BCM5750 A3" },
 287         { BGE_CHIPID_BCM5750_B0,        "BCM5750 B0" },
 288         { BGE_CHIPID_BCM5750_B1,        "BCM5750 B1" },
 289         { BGE_CHIPID_BCM5750_C0,        "BCM5750 C0" },
 290         { BGE_CHIPID_BCM5750_C1,        "BCM5750 C1" },
 291         { BGE_CHIPID_BCM5750_C2,        "BCM5750 C2" },
 292         { BGE_CHIPID_BCM5714_A0,        "BCM5714 A0" },
 293         { BGE_CHIPID_BCM5752_A0,        "BCM5752 A0" },
 294         { BGE_CHIPID_BCM5752_A1,        "BCM5752 A1" },
 295         { BGE_CHIPID_BCM5752_A2,        "BCM5752 A2" },
 296         { BGE_CHIPID_BCM5714_B0,        "BCM5714 B0" },
 297         { BGE_CHIPID_BCM5714_B3,        "BCM5714 B3" },
 298         { BGE_CHIPID_BCM5715_A0,        "BCM5715 A0" },
 299         { BGE_CHIPID_BCM5715_A1,        "BCM5715 A1" },
 300         { BGE_CHIPID_BCM5715_A3,        "BCM5715 A3" },
 301         { BGE_CHIPID_BCM5717_A0,        "BCM5717 A0" },
 302         { BGE_CHIPID_BCM5717_B0,        "BCM5717 B0" },
 303         { BGE_CHIPID_BCM5719_A0,        "BCM5719 A0" },
 304         { BGE_CHIPID_BCM5720_A0,        "BCM5720 A0" },
 305         { BGE_CHIPID_BCM5755_A0,        "BCM5755 A0" },
 306         { BGE_CHIPID_BCM5755_A1,        "BCM5755 A1" },
 307         { BGE_CHIPID_BCM5755_A2,        "BCM5755 A2" },
 308         { BGE_CHIPID_BCM5722_A0,        "BCM5722 A0" },
 309         { BGE_CHIPID_BCM5761_A0,        "BCM5761 A0" },
 310         { BGE_CHIPID_BCM5761_A1,        "BCM5761 A1" },
 311         { BGE_CHIPID_BCM5784_A0,        "BCM5784 A0" },
 312         { BGE_CHIPID_BCM5784_A1,        "BCM5784 A1" },
 313         /* 5754 and 5787 share the same ASIC ID */
 314         { BGE_CHIPID_BCM5787_A0,        "BCM5754/5787 A0" },
 315         { BGE_CHIPID_BCM5787_A1,        "BCM5754/5787 A1" },
 316         { BGE_CHIPID_BCM5787_A2,        "BCM5754/5787 A2" },
 317         { BGE_CHIPID_BCM5906_A1,        "BCM5906 A1" },
 318         { BGE_CHIPID_BCM5906_A2,        "BCM5906 A2" },
 319         { BGE_CHIPID_BCM57765_A0,       "BCM57765 A0" },
 320         { BGE_CHIPID_BCM57765_B0,       "BCM57765 B0" },
 321         { BGE_CHIPID_BCM57780_A0,       "BCM57780 A0" },
 322         { BGE_CHIPID_BCM57780_A1,       "BCM57780 A1" },
 323
 324         { 0, NULL }
 325 };
 326
 327 /*
 328  * Some defaults for major revisions, so that newer steppings
 329  * that we don't know about have a shot at working.
 330  */
 331 static const struct bge_revision const bge_majorrevs[] = {
 332         { BGE_ASICREV_BCM5700,          "unknown BCM5700" },
 333         { BGE_ASICREV_BCM5701,          "unknown BCM5701" },
 334         { BGE_ASICREV_BCM5703,          "unknown BCM5703" },
 335         { BGE_ASICREV_BCM5704,          "unknown BCM5704" },
 336         { BGE_ASICREV_BCM5705,          "unknown BCM5705" },
 337         { BGE_ASICREV_BCM5750,          "unknown BCM5750" },
 338         { BGE_ASICREV_BCM5714_A0,       "unknown BCM5714" },
 339         { BGE_ASICREV_BCM5752,          "unknown BCM5752" },
 340         { BGE_ASICREV_BCM5780,          "unknown BCM5780" },
 341         { BGE_ASICREV_BCM5714,          "unknown BCM5714" },
 342         { BGE_ASICREV_BCM5755,          "unknown BCM5755" },
 343         { BGE_ASICREV_BCM5761,          "unknown BCM5761" },
 344         { BGE_ASICREV_BCM5784,          "unknown BCM5784" },
 345         { BGE_ASICREV_BCM5785,          "unknown BCM5785" },
 346         /* 5754 and 5787 share the same ASIC ID */
 347         { BGE_ASICREV_BCM5787,          "unknown BCM5754/5787" },
 348         { BGE_ASICREV_BCM5906,          "unknown BCM5906" },
 349         { BGE_ASICREV_BCM57765,         "unknown BCM57765" },
 350         { BGE_ASICREV_BCM57780,         "unknown BCM57780" },
 351         { BGE_ASICREV_BCM5717,          "unknown BCM5717" },
 352         { BGE_ASICREV_BCM5719,          "unknown BCM5719" },
 353         { BGE_ASICREV_BCM5720,          "unknown BCM5720" },
 354
 355         { 0, NULL }
 356 };
 357
 358 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 359 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 360 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 361 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 362 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 363 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 364 #define BGE_IS_5717_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5717_PLUS)
 365
 366 const struct bge_revision * bge_lookup_rev(uint32_t);
 367 const struct bge_vendor * bge_lookup_vendor(uint16_t);
 368
 369 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 370
 371 static int bge_probe(device_t);
 372 static int bge_attach(device_t);
 373 static int bge_detach(device_t);
 374 static int bge_suspend(device_t);
 375 static int bge_resume(device_t);
 376 static void bge_release_resources(struct bge_softc *);
 377 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 378 static int bge_dma_alloc(struct bge_softc *);
 379 static void bge_dma_free(struct bge_softc *);
 380 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t,
 381     bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
 382
 383 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
 384 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 385 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 386 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 387 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
 388
 389 static void bge_txeof(struct bge_softc *, uint16_t);
 390 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
 391 static int bge_rxeof(struct bge_softc *, uint16_t, int);
 392
 393 static void bge_asf_driver_up (struct bge_softc *);
 394 static void bge_tick(void *);
 395 static void bge_stats_clear_regs(struct bge_softc *);
 396 static void bge_stats_update(struct bge_softc *);
 397 static void bge_stats_update_regs(struct bge_softc *);
 398 static struct mbuf *bge_check_short_dma(struct mbuf *);
 399 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
 400     uint16_t *, uint16_t *);
 401 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 402
 403 static void bge_intr(void *);
 404 static int bge_msi_intr(void *);
 405 static void bge_intr_task(void *, int);
 406 static void bge_start_locked(struct ifnet *);
 407 static void bge_start(struct ifnet *);
 408 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
 409 static void bge_init_locked(struct bge_softc *);
 410 static void bge_init(void *);
 411 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
 412 static void bge_stop(struct bge_softc *);
 413 static void bge_watchdog(struct bge_softc *);
 414 static int bge_shutdown(device_t);
 415 static int bge_ifmedia_upd_locked(struct ifnet *);
 416 static int bge_ifmedia_upd(struct ifnet *);
 417 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 418
 419 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 420 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 421
 422 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
 423 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
 424
 425 static void bge_setpromisc(struct bge_softc *);
 426 static void bge_setmulti(struct bge_softc *);
 427 static void bge_setvlan(struct bge_softc *);
 428
 429 static __inline void bge_rxreuse_std(struct bge_softc *, int);
 430 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
 431 static int bge_newbuf_std(struct bge_softc *, int);
 432 static int bge_newbuf_jumbo(struct bge_softc *, int);
 433 static int bge_init_rx_ring_std(struct bge_softc *);
 434 static void bge_free_rx_ring_std(struct bge_softc *);
 435 static int bge_init_rx_ring_jumbo(struct bge_softc *);
 436 static void bge_free_rx_ring_jumbo(struct bge_softc *);
 437 static void bge_free_tx_ring(struct bge_softc *);
 438 static int bge_init_tx_ring(struct bge_softc *);
 439
 440 static int bge_chipinit(struct bge_softc *);
 441 static int bge_blockinit(struct bge_softc *);
 442 static uint32_t bge_dma_swap_options(struct bge_softc *);
 443
 444 static int bge_has_eaddr(struct bge_softc *);
 445 static uint32_t bge_readmem_ind(struct bge_softc *, int);
 446 static void bge_writemem_ind(struct bge_softc *, int, int);
 447 static void bge_writembx(struct bge_softc *, int, int);
 448 #ifdef notdef
 449 static uint32_t bge_readreg_ind(struct bge_softc *, int);
 450 #endif
 451 static void bge_writemem_direct(struct bge_softc *, int, int);
 452 static void bge_writereg_ind(struct bge_softc *, int, int);
 453
 454 static int bge_miibus_readreg(device_t, int, int);
 455 static int bge_miibus_writereg(device_t, int, int, int);
 456 static void bge_miibus_statchg(device_t);
 457 #ifdef DEVICE_POLLING
 458 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 459 #endif
 460
 461 #define BGE_RESET_START 1
 462 #define BGE_RESET_STOP  2
 463 static void bge_sig_post_reset(struct bge_softc *, int);
 464 static void bge_sig_legacy(struct bge_softc *, int);
 465 static void bge_sig_pre_reset(struct bge_softc *, int);
 466 static void bge_stop_fw(struct bge_softc *);
 467 static int bge_reset(struct bge_softc *);
 468 static void bge_link_upd(struct bge_softc *);
 469
 470 /*
 471  * The BGE_REGISTER_DEBUG option is only for low-level debugging.  It may
 472  * leak information to untrusted users.  It is also known to cause alignment
 473  * traps on certain architectures.
 474  */
 475 #ifdef BGE_REGISTER_DEBUG
 476 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 477 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
 478 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
 479 #endif
 480 static void bge_add_sysctls(struct bge_softc *);
 481 static void bge_add_sysctl_stats_regs(struct bge_softc *,
 482     struct sysctl_ctx_list *, struct sysctl_oid_list *);
 483 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *,
 484     struct sysctl_oid_list *);
 485 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
 486
 487 static device_method_t bge_methods[] = {
 488         /* Device interface */
 489         DEVMETHOD(device_probe,         bge_probe),
 490         DEVMETHOD(device_attach,        bge_attach),
 491         DEVMETHOD(device_detach,        bge_detach),
 492         DEVMETHOD(device_shutdown,      bge_shutdown),
 493         DEVMETHOD(device_suspend,       bge_suspend),
 494         DEVMETHOD(device_resume,        bge_resume),
 495
 496         /* MII interface */
 497         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 498         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 499         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 500
 501         DEVMETHOD_END
 502 };
 503
 504 static driver_t bge_driver = {
 505         "bge",
 506         bge_methods,
 507         sizeof(struct bge_softc)
 508 };
 509
 510 static devclass_t bge_devclass;
 511
 512 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
 513 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 514
 515 static int bge_allow_asf = 1;
 516
 517 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
 518
 519 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
 520 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
 521         "Allow ASF mode if available");
 522
 523 #define SPARC64_BLADE_1500_MODEL        "SUNW,Sun-Blade-1500"
 524 #define SPARC64_BLADE_1500_PATH_BGE     "/pci@1f,700000/network@2"
 525 #define SPARC64_BLADE_2500_MODEL        "SUNW,Sun-Blade-2500"
 526 #define SPARC64_BLADE_2500_PATH_BGE     "/pci@1c,600000/network@3"
 527 #define SPARC64_OFW_SUBVENDOR           "subsystem-vendor-id"
 528
 529 static int
 530 bge_has_eaddr(struct bge_softc *sc)
 531 {
 532 #ifdef __sparc64__
 533         char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
 534         device_t dev;
 535         uint32_t subvendor;
 536
 537         dev = sc->bge_dev;
 538
 539         /*
 540          * The on-board BGEs found in sun4u machines aren't fitted with
 541          * an EEPROM which means that we have to obtain the MAC address
 542          * via OFW and that some tests will always fail.  We distinguish
 543          * such BGEs by the subvendor ID, which also has to be obtained
 544          * from OFW instead of the PCI configuration space as the latter
 545          * indicates Broadcom as the subvendor of the netboot interface.
 546          * For early Blade 1500 and 2500 we even have to check the OFW
 547          * device path as the subvendor ID always defaults to Broadcom
 548          * there.
 549          */
 550         if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
 551             &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
 552             (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID))
 553                 return (0);
 554         memset(buf, 0, sizeof(buf));
 555         if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
 556                 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
 557                     strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
 558                         return (0);
 559                 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
 560                     strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
 561                         return (0);
 562         }
 563 #endif
 564         return (1);
 565 }
 566
 567 static uint32_t
 568 bge_readmem_ind(struct bge_softc *sc, int off)
 569 {
 570         device_t dev;
 571         uint32_t val;
 572
 573         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 574             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 575                 return (0);
 576
 577         dev = sc->bge_dev;
 578
 579         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 580         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 581         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 582         return (val);
 583 }
 584
 585 static void
 586 bge_writemem_ind(struct bge_softc *sc, int off, int val)
 587 {
 588         device_t dev;
 589
 590         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 591             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 592                 return;
 593
 594         dev = sc->bge_dev;
 595
 596         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 597         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 598         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 599 }
 600
 601 #ifdef notdef
 602 static uint32_t
 603 bge_readreg_ind(struct bge_softc *sc, int off)
 604 {
 605         device_t dev;
 606
 607         dev = sc->bge_dev;
 608
 609         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 610         return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 611 }
 612 #endif
 613
 614 static void
 615 bge_writereg_ind(struct bge_softc *sc, int off, int val)
 616 {
 617         device_t dev;
 618
 619         dev = sc->bge_dev;
 620
 621         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 622         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 623 }
 624
 625 static void
 626 bge_writemem_direct(struct bge_softc *sc, int off, int val)
 627 {
 628         CSR_WRITE_4(sc, off, val);
 629 }
 630
 631 static void
 632 bge_writembx(struct bge_softc *sc, int off, int val)
 633 {
 634         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 635                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 636
 637         CSR_WRITE_4(sc, off, val);
 638 }
 639
 640 /*
 641  * Map a single buffer address.
 642  */
 643
 644 static void
 645 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 646 {
 647         struct bge_dmamap_arg *ctx;
 648
 649         if (error)
 650                 return;
 651
 652         KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
 653
 654         ctx = arg;
 655         ctx->bge_busaddr = segs->ds_addr;
 656 }
 657
 658 static uint8_t
 659 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 660 {
 661         uint32_t access, byte = 0;
 662         int i;
 663
 664         /* Lock. */
 665         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 666         for (i = 0; i < 8000; i++) {
 667                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 668                         break;
 669                 DELAY(20);
 670         }
 671         if (i == 8000)
 672                 return (1);
 673
 674         /* Enable access. */
 675         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 676         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 677
 678         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 679         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 680         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 681                 DELAY(10);
 682                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 683                         DELAY(10);
 684                         break;
 685                 }
 686         }
 687
 688         if (i == BGE_TIMEOUT * 10) {
 689                 if_printf(sc->bge_ifp, "nvram read timed out\n");
 690                 return (1);
 691         }
 692
 693         /* Get result. */
 694         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 695
 696         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 697
 698         /* Disable access. */
 699         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 700
 701         /* Unlock. */
 702         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 703         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 704
 705         return (0);
 706 }
 707
 708 /*
 709  * Read a sequence of bytes from NVRAM.
 710  */
 711 static int
 712 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 713 {
 714         int err = 0, i;
 715         uint8_t byte = 0;
 716
 717         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 718                 return (1);
 719
 720         for (i = 0; i < cnt; i++) {
 721                 err = bge_nvram_getbyte(sc, off + i, &byte);
 722                 if (err)
 723                         break;
 724                 *(dest + i) = byte;
 725         }
 726
 727         return (err ? 1 : 0);
 728 }
 729
 730 /*
 731  * Read a byte of data stored in the EEPROM at address 'addr.' The
 732  * BCM570x supports both the traditional bitbang interface and an
 733  * auto access interface for reading the EEPROM. We use the auto
 734  * access method.
 735  */
 736 static uint8_t
 737 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 738 {
 739         int i;
 740         uint32_t byte = 0;
 741
 742         /*
 743          * Enable use of auto EEPROM access so we can avoid
 744          * having to use the bitbang method.
 745          */
 746         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 747
 748         /* Reset the EEPROM, load the clock period. */
 749         CSR_WRITE_4(sc, BGE_EE_ADDR,
 750             BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 751         DELAY(20);
 752
 753         /* Issue the read EEPROM command. */
 754         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 755
 756         /* Wait for completion */
 757         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 758                 DELAY(10);
 759                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 760                         break;
 761         }
 762
 763         if (i == BGE_TIMEOUT * 10) {
 764                 device_printf(sc->bge_dev, "EEPROM read timed out\n");
 765                 return (1);
 766         }
 767
 768         /* Get result. */
 769         byte = CSR_READ_4(sc, BGE_EE_DATA);
 770
 771         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 772
 773         return (0);
 774 }
 775
 776 /*
 777  * Read a sequence of bytes from the EEPROM.
 778  */
 779 static int
 780 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 781 {
 782         int i, error = 0;
 783         uint8_t byte = 0;
 784
 785         for (i = 0; i < cnt; i++) {
 786                 error = bge_eeprom_getbyte(sc, off + i, &byte);
 787                 if (error)
 788                         break;
 789                 *(dest + i) = byte;
 790         }
 791
 792         return (error ? 1 : 0);
 793 }
 794
 795 static int
 796 bge_miibus_readreg(device_t dev, int phy, int reg)
 797 {
 798         struct bge_softc *sc;
 799         uint32_t val;
 800         int i;
 801
 802         sc = device_get_softc(dev);
 803
 804         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 805         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
 806                 CSR_WRITE_4(sc, BGE_MI_MODE,
 807                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 808                 DELAY(80);
 809         }
 810
 811         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 812             BGE_MIPHY(phy) | BGE_MIREG(reg));
 813
 814         /* Poll for the PHY register access to complete. */
 815         for (i = 0; i < BGE_TIMEOUT; i++) {
 816                 DELAY(10);
 817                 val = CSR_READ_4(sc, BGE_MI_COMM);
 818                 if ((val & BGE_MICOMM_BUSY) == 0) {
 819                         DELAY(5);
 820                         val = CSR_READ_4(sc, BGE_MI_COMM);
 821                         break;
 822                 }
 823         }
 824
 825         if (i == BGE_TIMEOUT) {
 826                 device_printf(sc->bge_dev,
 827                     "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
 828                     phy, reg, val);
 829                 val = 0;
 830         }
 831
 832         /* Restore the autopoll bit if necessary. */
 833         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
 834                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
 835                 DELAY(80);
 836         }
 837
 838         if (val & BGE_MICOMM_READFAIL)
 839                 return (0);
 840
 841         return (val & 0xFFFF);
 842 }
 843
 844 static int
 845 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 846 {
 847         struct bge_softc *sc;
 848         int i;
 849
 850         sc = device_get_softc(dev);
 851
 852         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 853             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 854                 return (0);
 855
 856         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 857         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
 858                 CSR_WRITE_4(sc, BGE_MI_MODE,
 859                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 860                 DELAY(80);
 861         }
 862
 863         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 864             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 865
 866         for (i = 0; i < BGE_TIMEOUT; i++) {
 867                 DELAY(10);
 868                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 869                         DELAY(5);
 870                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 871                         break;
 872                 }
 873         }
 874
 875         /* Restore the autopoll bit if necessary. */
 876         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
 877                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
 878                 DELAY(80);
 879         }
 880
 881         if (i == BGE_TIMEOUT)
 882                 device_printf(sc->bge_dev,
 883                     "PHY write timed out (phy %d, reg %d, val %d)\n",
 884                     phy, reg, val);
 885
 886         return (0);
 887 }
 888
 889 static void
 890 bge_miibus_statchg(device_t dev)
 891 {
 892         struct bge_softc *sc;
 893         struct mii_data *mii;
 894         sc = device_get_softc(dev);
 895         mii = device_get_softc(sc->bge_miibus);
 896
 897         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 898             (IFM_ACTIVE | IFM_AVALID)) {
 899                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 900                 case IFM_10_T:
 901                 case IFM_100_TX:
 902                         sc->bge_link = 1;
 903                         break;
 904                 case IFM_1000_T:
 905                 case IFM_1000_SX:
 906                 case IFM_2500_SX:
 907                         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 908                                 sc->bge_link = 1;
 909                         else
 910                                 sc->bge_link = 0;
 911                         break;
 912                 default:
 913                         sc->bge_link = 0;
 914                         break;
 915                 }
 916         } else
 917                 sc->bge_link = 0;
 918         if (sc->bge_link == 0)
 919                 return;
 920         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 921         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 922             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
 923                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 924         else
 925                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 926
 927         if (IFM_OPTIONS(mii->mii_media_active & IFM_FDX) != 0) {
 928                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 929                 if ((IFM_OPTIONS(mii->mii_media_active) &
 930                     IFM_ETH_TXPAUSE) != 0)
 931                         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
 932                 else
 933                         BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
 934                 if ((IFM_OPTIONS(mii->mii_media_active) &
 935                     IFM_ETH_RXPAUSE) != 0)
 936                         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
 937                 else
 938                         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
 939         } else {
 940                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 941                 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
 942                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
 943         }
 944 }
 945
 946 /*
 947  * Intialize a standard receive ring descriptor.
 948  */
 949 static int
 950 bge_newbuf_std(struct bge_softc *sc, int i)
 951 {
 952         struct mbuf *m;
 953         struct bge_rx_bd *r;
 954         bus_dma_segment_t segs[1];
 955         bus_dmamap_t map;
 956         int error, nsegs;
 957
 958         if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
 959             (sc->bge_ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN +
 960             ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) {
 961                 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
 962                 if (m == NULL)
 963                         return (ENOBUFS);
 964                 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
 965         } else {
 966                 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
 967                 if (m == NULL)
 968                         return (ENOBUFS);
 969                 m->m_len = m->m_pkthdr.len = MCLBYTES;
 970         }
 971         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 972                 m_adj(m, ETHER_ALIGN);
 973
 974         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
 975             sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
 976         if (error != 0) {
 977                 m_freem(m);
 978                 return (error);
 979         }
 980         if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 981                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 982                     sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
 983                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 984                     sc->bge_cdata.bge_rx_std_dmamap[i]);
 985         }
 986         map = sc->bge_cdata.bge_rx_std_dmamap[i];
 987         sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
 988         sc->bge_cdata.bge_rx_std_sparemap = map;
 989         sc->bge_cdata.bge_rx_std_chain[i] = m;
 990         sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
 991         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
 992         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
 993         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
 994         r->bge_flags = BGE_RXBDFLAG_END;
 995         r->bge_len = segs[0].ds_len;
 996         r->bge_idx = i;
 997
 998         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 999             sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
1000
1001         return (0);
1002 }
1003
1004 /*
1005  * Initialize a jumbo receive ring descriptor. This allocates
1006  * a jumbo buffer from the pool managed internally by the driver.
1007  */
1008 static int
1009 bge_newbuf_jumbo(struct bge_softc *sc, int i)
1010 {
1011         bus_dma_segment_t segs[BGE_NSEG_JUMBO];
1012         bus_dmamap_t map;
1013         struct bge_extrx_bd *r;
1014         struct mbuf *m;
1015         int error, nsegs;
1016
1017         MGETHDR(m, M_DONTWAIT, MT_DATA);
1018         if (m == NULL)
1019                 return (ENOBUFS);
1020
1021         m_cljget(m, M_DONTWAIT, MJUM9BYTES);
1022         if (!(m->m_flags & M_EXT)) {
1023                 m_freem(m);
1024                 return (ENOBUFS);
1025         }
1026         m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1027         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1028                 m_adj(m, ETHER_ALIGN);
1029
1030         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1031             sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1032         if (error != 0) {
1033                 m_freem(m);
1034                 return (error);
1035         }
1036
1037         if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1038                 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1039                     sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1040                 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1041                     sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1042         }
1043         map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1044         sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1045             sc->bge_cdata.bge_rx_jumbo_sparemap;
1046         sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1047         sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1048         sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1049         sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1050         sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1051         sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1052
1053         /*
1054          * Fill in the extended RX buffer descriptor.
1055          */
1056         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1057         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1058         r->bge_idx = i;
1059         r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1060         switch (nsegs) {
1061         case 4:
1062                 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1063                 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1064                 r->bge_len3 = segs[3].ds_len;
1065                 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1066         case 3:
1067                 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1068                 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1069                 r->bge_len2 = segs[2].ds_len;
1070                 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1071         case 2:
1072                 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1073                 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1074                 r->bge_len1 = segs[1].ds_len;
1075                 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1076         case 1:
1077                 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1078                 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1079                 r->bge_len0 = segs[0].ds_len;
1080                 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1081                 break;
1082         default:
1083                 panic("%s: %d segments\n", __func__, nsegs);
1084         }
1085
1086         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1087             sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1088
1089         return (0);
1090 }
1091
1092 static int
1093 bge_init_rx_ring_std(struct bge_softc *sc)
1094 {
1095         int error, i;
1096
1097         bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1098         sc->bge_std = 0;
1099         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1100                 if ((error = bge_newbuf_std(sc, i)) != 0)
1101                         return (error);
1102                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1103         }
1104
1105         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1106             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1107
1108         sc->bge_std = 0;
1109         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1110
1111         return (0);
1112 }
1113
1114 static void
1115 bge_free_rx_ring_std(struct bge_softc *sc)
1116 {
1117         int i;
1118
1119         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1120                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1121                         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1122                             sc->bge_cdata.bge_rx_std_dmamap[i],
1123                             BUS_DMASYNC_POSTREAD);
1124                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1125                             sc->bge_cdata.bge_rx_std_dmamap[i]);
1126                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1127                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1128                 }
1129                 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1130                     sizeof(struct bge_rx_bd));
1131         }
1132 }
1133
1134 static int
1135 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1136 {
1137         struct bge_rcb *rcb;
1138         int error, i;
1139
1140         bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1141         sc->bge_jumbo = 0;
1142         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1143                 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1144                         return (error);
1145                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1146         }
1147
1148         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1149             sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1150
1151         sc->bge_jumbo = 0;
1152
1153         /* Enable the jumbo receive producer ring. */
1154         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1155         rcb->bge_maxlen_flags =
1156             BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD);
1157         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1158
1159         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1160
1161         return (0);
1162 }
1163
1164 static void
1165 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1166 {
1167         int i;
1168
1169         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1170                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1171                         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1172                             sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1173                             BUS_DMASYNC_POSTREAD);
1174                         bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1175                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1176                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1177                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1178                 }
1179                 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1180                     sizeof(struct bge_extrx_bd));
1181         }
1182 }
1183
1184 static void
1185 bge_free_tx_ring(struct bge_softc *sc)
1186 {
1187         int i;
1188
1189         if (sc->bge_ldata.bge_tx_ring == NULL)
1190                 return;
1191
1192         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1193                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1194                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1195                             sc->bge_cdata.bge_tx_dmamap[i],
1196                             BUS_DMASYNC_POSTWRITE);
1197                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1198                             sc->bge_cdata.bge_tx_dmamap[i]);
1199                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1200                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1201                 }
1202                 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1203                     sizeof(struct bge_tx_bd));
1204         }
1205 }
1206
1207 static int
1208 bge_init_tx_ring(struct bge_softc *sc)
1209 {
1210         sc->bge_txcnt = 0;
1211         sc->bge_tx_saved_considx = 0;
1212
1213         bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1214         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1215             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1216
1217         /* Initialize transmit producer index for host-memory send ring. */
1218         sc->bge_tx_prodidx = 0;
1219         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1220
1221         /* 5700 b2 errata */
1222         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1223                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1224
1225         /* NIC-memory send ring not used; initialize to zero. */
1226         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1227         /* 5700 b2 errata */
1228         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1229                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1230
1231         return (0);
1232 }
1233
1234 static void
1235 bge_setpromisc(struct bge_softc *sc)
1236 {
1237         struct ifnet *ifp;
1238
1239         BGE_LOCK_ASSERT(sc);
1240
1241         ifp = sc->bge_ifp;
1242
1243         /* Enable or disable promiscuous mode as needed. */
1244         if (ifp->if_flags & IFF_PROMISC)
1245                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1246         else
1247                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1248 }
1249
1250 static void
1251 bge_setmulti(struct bge_softc *sc)
1252 {
1253         struct ifnet *ifp;
1254         struct ifmultiaddr *ifma;
1255         uint32_t hashes[4] = { 0, 0, 0, 0 };
1256         int h, i;
1257
1258         BGE_LOCK_ASSERT(sc);
1259
1260         ifp = sc->bge_ifp;
1261
1262         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1263                 for (i = 0; i < 4; i++)
1264                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1265                 return;
1266         }
1267
1268         /* First, zot all the existing filters. */
1269         for (i = 0; i < 4; i++)
1270                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1271
1272         /* Now program new ones. */
1273         if_maddr_rlock(ifp);
1274         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1275                 if (ifma->ifma_addr->sa_family != AF_LINK)
1276                         continue;
1277                 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1278                     ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1279                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1280         }
1281         if_maddr_runlock(ifp);
1282
1283         for (i = 0; i < 4; i++)
1284                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1285 }
1286
1287 static void
1288 bge_setvlan(struct bge_softc *sc)
1289 {
1290         struct ifnet *ifp;
1291
1292         BGE_LOCK_ASSERT(sc);
1293
1294         ifp = sc->bge_ifp;
1295
1296         /* Enable or disable VLAN tag stripping as needed. */
1297         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1298                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1299         else
1300                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1301 }
1302
1303 static void
1304 bge_sig_pre_reset(struct bge_softc *sc, int type)
1305 {
1306
1307         /*
1308          * Some chips don't like this so only do this if ASF is enabled
1309          */
1310         if (sc->bge_asf_mode)
1311                 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
1312
1313         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1314                 switch (type) {
1315                 case BGE_RESET_START:
1316                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1317                             BGE_FW_DRV_STATE_START);
1318                         break;
1319                 case BGE_RESET_STOP:
1320                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1321                             BGE_FW_DRV_STATE_UNLOAD);
1322                         break;
1323                 }
1324         }
1325 }
1326
1327 static void
1328 bge_sig_post_reset(struct bge_softc *sc, int type)
1329 {
1330
1331         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1332                 switch (type) {
1333                 case BGE_RESET_START:
1334                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1335                             BGE_FW_DRV_STATE_START_DONE);
1336                         /* START DONE */
1337                         break;
1338                 case BGE_RESET_STOP:
1339                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1340                             BGE_FW_DRV_STATE_UNLOAD_DONE);
1341                         break;
1342                 }
1343         }
1344 }
1345
1346 static void
1347 bge_sig_legacy(struct bge_softc *sc, int type)
1348 {
1349
1350         if (sc->bge_asf_mode) {
1351                 switch (type) {
1352                 case BGE_RESET_START:
1353                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1354                             BGE_FW_DRV_STATE_START);
1355                         break;
1356                 case BGE_RESET_STOP:
1357                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1358                             BGE_FW_DRV_STATE_UNLOAD);
1359                         break;
1360                 }
1361         }
1362 }
1363
1364 static void
1365 bge_stop_fw(struct bge_softc *sc)
1366 {
1367         int i;
1368
1369         if (sc->bge_asf_mode) {
1370                 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
1371                 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
1372                     CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
1373
1374                 for (i = 0; i < 100; i++ ) {
1375                         if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1376                             BGE_RX_CPU_DRV_EVENT))
1377                                 break;
1378                         DELAY(10);
1379                 }
1380         }
1381 }
1382
1383 static uint32_t
1384 bge_dma_swap_options(struct bge_softc *sc)
1385 {
1386         uint32_t dma_options;
1387
1388         dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
1389             BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
1390 #if BYTE_ORDER == BIG_ENDIAN
1391         dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
1392 #endif
1393         if ((sc)->bge_asicrev == BGE_ASICREV_BCM5720)
1394                 dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA |
1395                     BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE |
1396                     BGE_MODECTL_HTX2B_ENABLE;
1397
1398         return (dma_options);
1399 }
1400
1401 /*
1402  * Do endian, PCI and DMA initialization.
1403  */
1404 static int
1405 bge_chipinit(struct bge_softc *sc)
1406 {
1407         uint32_t dma_rw_ctl, misc_ctl, mode_ctl;
1408         uint16_t val;
1409         int i;
1410
1411         /* Set endianness before we access any non-PCI registers. */
1412         misc_ctl = BGE_INIT;
1413         if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1414                 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1415         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1416
1417         /* Clear the MAC control register */
1418         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1419
1420         /*
1421          * Clear the MAC statistics block in the NIC's
1422          * internal memory.
1423          */
1424         for (i = BGE_STATS_BLOCK;
1425             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1426                 BGE_MEMWIN_WRITE(sc, i, 0);
1427
1428         for (i = BGE_STATUS_BLOCK;
1429             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1430                 BGE_MEMWIN_WRITE(sc, i, 0);
1431
1432         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1433                 /*
1434                  *  Fix data corruption caused by non-qword write with WB.
1435                  *  Fix master abort in PCI mode.
1436                  *  Fix PCI latency timer.
1437                  */
1438                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1439                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1440                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1441         }
1442
1443         /*
1444          * Set up the PCI DMA control register.
1445          */
1446         dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1447             BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1448         if (sc->bge_flags & BGE_FLAG_PCIE) {
1449                 /* Read watermark not used, 128 bytes for write. */
1450                 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1451         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1452                 if (BGE_IS_5714_FAMILY(sc)) {
1453                         /* 256 bytes for read and write. */
1454                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1455                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1456                         dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1457                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1458                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1459                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1460                         /*
1461                          * In the BCM5703, the DMA read watermark should
1462                          * be set to less than or equal to the maximum
1463                          * memory read byte count of the PCI-X command
1464                          * register.
1465                          */
1466                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1467                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1468                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1469                         /* 1536 bytes for read, 384 bytes for write. */
1470                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1471                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1472                 } else {
1473                         /* 384 bytes for read and write. */
1474                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1475                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1476                             0x0F;
1477                 }
1478                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1479                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1480                         uint32_t tmp;
1481
1482                         /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1483                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1484                         if (tmp == 6 || tmp == 7)
1485                                 dma_rw_ctl |=
1486                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1487
1488                         /* Set PCI-X DMA write workaround. */
1489                         dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1490                 }
1491         } else {
1492                 /* Conventional PCI bus: 256 bytes for read and write. */
1493                 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1494                     BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1495
1496                 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1497                     sc->bge_asicrev != BGE_ASICREV_BCM5750)
1498                         dma_rw_ctl |= 0x0F;
1499         }
1500         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1501             sc->bge_asicrev == BGE_ASICREV_BCM5701)
1502                 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1503                     BGE_PCIDMARWCTL_ASRT_ALL_BE;
1504         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1505             sc->bge_asicrev == BGE_ASICREV_BCM5704)
1506                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1507         if (BGE_IS_5717_PLUS(sc)) {
1508                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1509                 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
1510                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1511                 /*
1512                  * Enable HW workaround for controllers that misinterpret
1513                  * a status tag update and leave interrupts permanently
1514                  * disabled.
1515                  */
1516                 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
1517                     sc->bge_asicrev != BGE_ASICREV_BCM57765)
1518                         dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1519         }
1520         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1521
1522         /*
1523          * Set up general mode register.
1524          */
1525         mode_ctl = bge_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1526             BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM;
1527
1528         /*
1529          * BCM5701 B5 have a bug causing data corruption when using
1530          * 64-bit DMA reads, which can be terminated early and then
1531          * completed later as 32-bit accesses, in combination with
1532          * certain bridges.
1533          */
1534         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1535             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1536                 mode_ctl |= BGE_MODECTL_FORCE_PCI32;
1537
1538         /*
1539          * Tell the firmware the driver is running
1540          */
1541         if (sc->bge_asf_mode & ASF_STACKUP)
1542                 mode_ctl |= BGE_MODECTL_STACKUP;
1543
1544         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1545
1546         /*
1547          * Disable memory write invalidate.  Apparently it is not supported
1548          * properly by these devices.  Also ensure that INTx isn't disabled,
1549          * as these chips need it even when using MSI.
1550          */
1551         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1552             PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
1553
1554         /* Set the timer prescaler (always 66Mhz) */
1555         CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1556
1557         /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1558         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1559                 DELAY(40);      /* XXX */
1560
1561                 /* Put PHY into ready state */
1562                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1563                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1564                 DELAY(40);
1565         }
1566
1567         return (0);
1568 }
1569
1570 static int
1571 bge_blockinit(struct bge_softc *sc)
1572 {
1573         struct bge_rcb *rcb;
1574         bus_size_t vrcb;
1575         bge_hostaddr taddr;
1576         uint32_t dmactl, val;
1577         int i, limit;
1578
1579         /*
1580          * Initialize the memory window pointer register so that
1581          * we can access the first 32K of internal NIC RAM. This will
1582          * allow us to set up the TX send ring RCBs and the RX return
1583          * ring RCBs, plus other things which live in NIC memory.
1584          */
1585         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1586
1587         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1588
1589         if (!(BGE_IS_5705_PLUS(sc))) {
1590                 /* Configure mbuf memory pool */
1591                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1592                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1593                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1594                 else
1595                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1596
1597                 /* Configure DMA resource pool */
1598                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1599                     BGE_DMA_DESCRIPTORS);
1600                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1601         }
1602
1603         /* Configure mbuf pool watermarks */
1604         if (BGE_IS_5717_PLUS(sc)) {
1605                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1606                 if (sc->bge_ifp->if_mtu > ETHERMTU) {
1607                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1608                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1609                 } else {
1610                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1611                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1612                 }
1613         } else if (!BGE_IS_5705_PLUS(sc)) {
1614                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1615                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1616                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1617         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1618                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1619                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1620                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1621         } else {
1622                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1623                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1624                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1625         }
1626
1627         /* Configure DMA resource watermarks */
1628         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1629         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1630
1631         /* Enable buffer manager */
1632         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1633         /*
1634          * Change the arbitration algorithm of TXMBUF read request to
1635          * round-robin instead of priority based for BCM5719.  When
1636          * TXFIFO is almost empty, RDMA will hold its request until
1637          * TXFIFO is not almost empty.
1638          */
1639         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
1640                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1641         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1642
1643         /* Poll for buffer manager start indication */
1644         for (i = 0; i < BGE_TIMEOUT; i++) {
1645                 DELAY(10);
1646                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1647                         break;
1648         }
1649
1650         if (i == BGE_TIMEOUT) {
1651                 device_printf(sc->bge_dev, "buffer manager failed to start\n");
1652                 return (ENXIO);
1653         }
1654
1655         /* Enable flow-through queues */
1656         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1657         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1658
1659         /* Wait until queue initialization is complete */
1660         for (i = 0; i < BGE_TIMEOUT; i++) {
1661                 DELAY(10);
1662                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1663                         break;
1664         }
1665
1666         if (i == BGE_TIMEOUT) {
1667                 device_printf(sc->bge_dev, "flow-through queue init failed\n");
1668                 return (ENXIO);
1669         }
1670
1671         /*
1672          * Summary of rings supported by the controller:
1673          *
1674          * Standard Receive Producer Ring
1675          * - This ring is used to feed receive buffers for "standard"
1676          *   sized frames (typically 1536 bytes) to the controller.
1677          *
1678          * Jumbo Receive Producer Ring
1679          * - This ring is used to feed receive buffers for jumbo sized
1680          *   frames (i.e. anything bigger than the "standard" frames)
1681          *   to the controller.
1682          *
1683          * Mini Receive Producer Ring
1684          * - This ring is used to feed receive buffers for "mini"
1685          *   sized frames to the controller.
1686          * - This feature required external memory for the controller
1687          *   but was never used in a production system.  Should always
1688          *   be disabled.
1689          *
1690          * Receive Return Ring
1691          * - After the controller has placed an incoming frame into a
1692          *   receive buffer that buffer is moved into a receive return
1693          *   ring.  The driver is then responsible to passing the
1694          *   buffer up to the stack.  Many versions of the controller
1695          *   support multiple RR rings.
1696          *
1697          * Send Ring
1698          * - This ring is used for outgoing frames.  Many versions of
1699          *   the controller support multiple send rings.
1700          */
1701
1702         /* Initialize the standard receive producer ring control block. */
1703         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1704         rcb->bge_hostaddr.bge_addr_lo =
1705             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1706         rcb->bge_hostaddr.bge_addr_hi =
1707             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1708         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1709             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1710         if (BGE_IS_5717_PLUS(sc)) {
1711                 /*
1712                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1713                  * Bits 15-2 : Maximum RX frame size
1714                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
1715                  * Bit 0     : Reserved
1716                  */
1717                 rcb->bge_maxlen_flags =
1718                     BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
1719         } else if (BGE_IS_5705_PLUS(sc)) {
1720                 /*
1721                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1722                  * Bits 15-2 : Reserved (should be 0)
1723                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1724                  * Bit 0     : Reserved
1725                  */
1726                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1727         } else {
1728                 /*
1729                  * Ring size is always XXX entries
1730                  * Bits 31-16: Maximum RX frame size
1731                  * Bits 15-2 : Reserved (should be 0)
1732                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1733                  * Bit 0     : Reserved
1734                  */
1735                 rcb->bge_maxlen_flags =
1736                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1737         }
1738         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1739             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
1740             sc->bge_asicrev == BGE_ASICREV_BCM5720)
1741                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1742         else
1743                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1744         /* Write the standard receive producer ring control block. */
1745         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1746         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1747         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1748         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1749
1750         /* Reset the standard receive producer ring producer index. */
1751         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1752
1753         /*
1754          * Initialize the jumbo RX producer ring control
1755          * block.  We set the 'ring disabled' bit in the
1756          * flags field until we're actually ready to start
1757          * using this ring (i.e. once we set the MTU
1758          * high enough to require it).
1759          */
1760         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1761                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1762                 /* Get the jumbo receive producer ring RCB parameters. */
1763                 rcb->bge_hostaddr.bge_addr_lo =
1764                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1765                 rcb->bge_hostaddr.bge_addr_hi =
1766                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1767                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1768                     sc->bge_cdata.bge_rx_jumbo_ring_map,
1769                     BUS_DMASYNC_PREREAD);
1770                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1771                     BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1772                 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1773                     sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
1774                     sc->bge_asicrev == BGE_ASICREV_BCM5720)
1775                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1776                 else
1777                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1778                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1779                     rcb->bge_hostaddr.bge_addr_hi);
1780                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1781                     rcb->bge_hostaddr.bge_addr_lo);
1782                 /* Program the jumbo receive producer ring RCB parameters. */
1783                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1784                     rcb->bge_maxlen_flags);
1785                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1786                 /* Reset the jumbo receive producer ring producer index. */
1787                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1788         }
1789
1790         /* Disable the mini receive producer ring RCB. */
1791         if (BGE_IS_5700_FAMILY(sc)) {
1792                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1793                 rcb->bge_maxlen_flags =
1794                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1795                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1796                     rcb->bge_maxlen_flags);
1797                 /* Reset the mini receive producer ring producer index. */
1798                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1799         }
1800
1801         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1802         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1803                 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
1804                     sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
1805                     sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
1806                         CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1807                             (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1808         }
1809         /*
1810          * The BD ring replenish thresholds control how often the
1811          * hardware fetches new BD's from the producer rings in host
1812          * memory.  Setting the value too low on a busy system can
1813          * starve the hardware and recue the throughpout.
1814          *
1815          * Set the BD ring replentish thresholds. The recommended
1816          * values are 1/8th the number of descriptors allocated to
1817          * each ring.
1818          * XXX The 5754 requires a lower threshold, so it might be a
1819          * requirement of all 575x family chips.  The Linux driver sets
1820          * the lower threshold for all 5705 family chips as well, but there
1821          * are reports that it might not need to be so strict.
1822          *
1823          * XXX Linux does some extra fiddling here for the 5906 parts as
1824          * well.
1825          */
1826         if (BGE_IS_5705_PLUS(sc))
1827                 val = 8;
1828         else
1829                 val = BGE_STD_RX_RING_CNT / 8;
1830         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1831         if (BGE_IS_JUMBO_CAPABLE(sc))
1832                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1833                     BGE_JUMBO_RX_RING_CNT/8);
1834         if (BGE_IS_5717_PLUS(sc)) {
1835                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1836                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1837         }
1838
1839         /*
1840          * Disable all send rings by setting the 'ring disabled' bit
1841          * in the flags field of all the TX send ring control blocks,
1842          * located in NIC memory.
1843          */
1844         if (!BGE_IS_5705_PLUS(sc))
1845                 /* 5700 to 5704 had 16 send rings. */
1846                 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
1847         else
1848                 limit = 1;
1849         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1850         for (i = 0; i < limit; i++) {
1851                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1852                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1853                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1854                 vrcb += sizeof(struct bge_rcb);
1855         }
1856
1857         /* Configure send ring RCB 0 (we use only the first ring) */
1858         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1859         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1860         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1861         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1862         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1863             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
1864             sc->bge_asicrev == BGE_ASICREV_BCM5720)
1865                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1866         else
1867                 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1868                     BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1869         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1870             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1871
1872         /*
1873          * Disable all receive return rings by setting the
1874          * 'ring diabled' bit in the flags field of all the receive
1875          * return ring control blocks, located in NIC memory.
1876          */
1877         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1878             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
1879             sc->bge_asicrev == BGE_ASICREV_BCM5720) {
1880                 /* Should be 17, use 16 until we get an SRAM map. */
1881                 limit = 16;
1882         } else if (!BGE_IS_5705_PLUS(sc))
1883                 limit = BGE_RX_RINGS_MAX;
1884         else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1885             sc->bge_asicrev == BGE_ASICREV_BCM57765)
1886                 limit = 4;
1887         else
1888                 limit = 1;
1889         /* Disable all receive return rings. */
1890         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1891         for (i = 0; i < limit; i++) {
1892                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1893                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1894                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1895                     BGE_RCB_FLAG_RING_DISABLED);
1896                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1897                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1898                     (i * (sizeof(uint64_t))), 0);
1899                 vrcb += sizeof(struct bge_rcb);
1900         }
1901
1902         /*
1903          * Set up receive return ring 0.  Note that the NIC address
1904          * for RX return rings is 0x0.  The return rings live entirely
1905          * within the host, so the nicaddr field in the RCB isn't used.
1906          */
1907         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1908         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1909         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1910         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1911         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1912         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1913             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1914
1915         /* Set random backoff seed for TX */
1916         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1917             IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1918             IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1919             IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1920             BGE_TX_BACKOFF_SEED_MASK);
1921
1922         /* Set inter-packet gap */
1923         val = 0x2620;
1924         if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
1925                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1926                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
1927         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1928
1929         /*
1930          * Specify which ring to use for packets that don't match
1931          * any RX rules.
1932          */
1933         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1934
1935         /*
1936          * Configure number of RX lists. One interrupt distribution
1937          * list, sixteen active lists, one bad frames class.
1938          */
1939         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1940
1941         /* Inialize RX list placement stats mask. */
1942         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1943         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1944
1945         /* Disable host coalescing until we get it set up */
1946         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1947
1948         /* Poll to make sure it's shut down. */
1949         for (i = 0; i < BGE_TIMEOUT; i++) {
1950                 DELAY(10);
1951                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1952                         break;
1953         }
1954
1955         if (i == BGE_TIMEOUT) {
1956                 device_printf(sc->bge_dev,
1957                     "host coalescing engine failed to idle\n");
1958                 return (ENXIO);
1959         }
1960
1961         /* Set up host coalescing defaults */
1962         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1963         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1964         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1965         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1966         if (!(BGE_IS_5705_PLUS(sc))) {
1967                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1968                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1969         }
1970         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1971         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1972
1973         /* Set up address of statistics block */
1974         if (!(BGE_IS_5705_PLUS(sc))) {
1975                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1976                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1977                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1978                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1979                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1980                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1981                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1982         }
1983
1984         /* Set up address of status block */
1985         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1986             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1987         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1988             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1989
1990         /* Set up status block size. */
1991         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1992             sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
1993                 val = BGE_STATBLKSZ_FULL;
1994                 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
1995         } else {
1996                 val = BGE_STATBLKSZ_32BYTE;
1997                 bzero(sc->bge_ldata.bge_status_block, 32);
1998         }
1999         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2000             sc->bge_cdata.bge_status_map,
2001             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2002
2003         /* Turn on host coalescing state machine */
2004         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2005
2006         /* Turn on RX BD completion state machine and enable attentions */
2007         CSR_WRITE_4(sc, BGE_RBDC_MODE,
2008             BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
2009
2010         /* Turn on RX list placement state machine */
2011         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2012
2013         /* Turn on RX list selector state machine. */
2014         if (!(BGE_IS_5705_PLUS(sc)))
2015                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2016
2017         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
2018             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
2019             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
2020             BGE_MACMODE_FRMHDR_DMA_ENB;
2021
2022         if (sc->bge_flags & BGE_FLAG_TBI)
2023                 val |= BGE_PORTMODE_TBI;
2024         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
2025                 val |= BGE_PORTMODE_GMII;
2026         else
2027                 val |= BGE_PORTMODE_MII;
2028
2029         /* Turn on DMA, clear stats */
2030         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
2031
2032         /* Set misc. local control, enable interrupts on attentions */
2033         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2034
2035 #ifdef notdef
2036         /* Assert GPIO pins for PHY reset */
2037         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
2038             BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
2039         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
2040             BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
2041 #endif
2042
2043         /* Turn on DMA completion state machine */
2044         if (!(BGE_IS_5705_PLUS(sc)))
2045                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2046
2047         val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
2048
2049         /* Enable host coalescing bug fix. */
2050         if (BGE_IS_5755_PLUS(sc))
2051                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
2052
2053         /* Request larger DMA burst size to get better performance. */
2054         if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
2055                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
2056
2057         /* Turn on write DMA state machine */
2058         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
2059         DELAY(40);
2060
2061         /* Turn on read DMA state machine */
2062         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
2063
2064         if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
2065                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
2066
2067         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2068             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2069             sc->bge_asicrev == BGE_ASICREV_BCM57780)
2070                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
2071                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
2072                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
2073         if (sc->bge_flags & BGE_FLAG_PCIE)
2074                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2075         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2076                 val |= BGE_RDMAMODE_TSO4_ENABLE;
2077                 if (sc->bge_flags & BGE_FLAG_TSO3 ||
2078                     sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2079                     sc->bge_asicrev == BGE_ASICREV_BCM57780)
2080                         val |= BGE_RDMAMODE_TSO6_ENABLE;
2081         }
2082
2083         if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2084                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
2085                         BGE_RDMAMODE_H2BNC_VLAN_DET;
2086                 /*
2087                  * Allow multiple outstanding read requests from
2088                  * non-LSO read DMA engine.
2089                  */
2090                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
2091         }
2092
2093         if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2094             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2095             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2096             sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2097             BGE_IS_5717_PLUS(sc)) {
2098                 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
2099                 /*
2100                  * Adjust tx margin to prevent TX data corruption and
2101                  * fix internal FIFO overflow.
2102                  */
2103                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2104                     sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2105                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2106                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2107                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2108                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2109                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2110                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2111                 }
2112                 /*
2113                  * Enable fix for read DMA FIFO overruns.
2114                  * The fix is to limit the number of RX BDs
2115                  * the hardware would fetch at a fime.
2116                  */
2117                 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl |
2118                     BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2119         }
2120
2121         if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2122                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2123                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2124                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2125                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2126         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2127                 /*
2128                  * Allow 4KB burst length reads for non-LSO frames.
2129                  * Enable 512B burst length reads for buffer descriptors.
2130                  */
2131                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2132                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2133                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
2134                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2135         }
2136
2137         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2138         DELAY(40);
2139
2140         /* Turn on RX data completion state machine */
2141         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2142
2143         /* Turn on RX BD initiator state machine */
2144         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2145
2146         /* Turn on RX data and RX BD initiator state machine */
2147         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2148
2149         /* Turn on Mbuf cluster free state machine */
2150         if (!(BGE_IS_5705_PLUS(sc)))
2151                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2152
2153         /* Turn on send BD completion state machine */
2154         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2155
2156         /* Turn on send data completion state machine */
2157         val = BGE_SDCMODE_ENABLE;
2158         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2159                 val |= BGE_SDCMODE_CDELAY;
2160         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2161
2162         /* Turn on send data initiator state machine */
2163         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2164                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2165                     BGE_SDIMODE_HW_LSO_PRE_DMA);
2166         else
2167                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2168
2169         /* Turn on send BD initiator state machine */
2170         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2171
2172         /* Turn on send BD selector state machine */
2173         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2174
2175         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
2176         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
2177             BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
2178
2179         /* ack/clear link change events */
2180         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2181             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2182             BGE_MACSTAT_LINK_CHANGED);
2183         CSR_WRITE_4(sc, BGE_MI_STS, 0);
2184
2185         /*
2186          * Enable attention when the link has changed state for
2187          * devices that use auto polling.
2188          */
2189         if (sc->bge_flags & BGE_FLAG_TBI) {
2190                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
2191         } else {
2192                 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2193                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
2194                         DELAY(80);
2195                 }
2196                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2197                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
2198                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2199                             BGE_EVTENB_MI_INTERRUPT);
2200         }
2201
2202         /*
2203          * Clear any pending link state attention.
2204          * Otherwise some link state change events may be lost until attention
2205          * is cleared by bge_intr() -> bge_link_upd() sequence.
2206          * It's not necessary on newer BCM chips - perhaps enabling link
2207          * state change attentions implies clearing pending attention.
2208          */
2209         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2210             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2211             BGE_MACSTAT_LINK_CHANGED);
2212
2213         /* Enable link state change attentions. */
2214         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2215
2216         return (0);
2217 }
2218
2219 const struct bge_revision *
2220 bge_lookup_rev(uint32_t chipid)
2221 {
2222         const struct bge_revision *br;
2223
2224         for (br = bge_revisions; br->br_name != NULL; br++) {
2225                 if (br->br_chipid == chipid)
2226                         return (br);
2227         }
2228
2229         for (br = bge_majorrevs; br->br_name != NULL; br++) {
2230                 if (br->br_chipid == BGE_ASICREV(chipid))
2231                         return (br);
2232         }
2233
2234         return (NULL);
2235 }
2236
2237 const struct bge_vendor *
2238 bge_lookup_vendor(uint16_t vid)
2239 {
2240         const struct bge_vendor *v;
2241
2242         for (v = bge_vendors; v->v_name != NULL; v++)
2243                 if (v->v_id == vid)
2244                         return (v);
2245
2246         panic("%s: unknown vendor %d", __func__, vid);
2247         return (NULL);
2248 }
2249
2250 /*
2251  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
2252  * against our list and return its name if we find a match.
2253  *
2254  * Note that since the Broadcom controller contains VPD support, we
2255  * try to get the device name string from the controller itself instead
2256  * of the compiled-in string. It guarantees we'll always announce the
2257  * right product name. We fall back to the compiled-in string when
2258  * VPD is unavailable or corrupt.
2259  */
2260 static int
2261 bge_probe(device_t dev)
2262 {
2263         char buf[96];
2264         char model[64];
2265         const struct bge_revision *br;
2266         const char *pname;
2267         struct bge_softc *sc = device_get_softc(dev);
2268         const struct bge_type *t = bge_devs;
2269         const struct bge_vendor *v;
2270         uint32_t id;
2271         uint16_t did, vid;
2272
2273         sc->bge_dev = dev;
2274         vid = pci_get_vendor(dev);
2275         did = pci_get_device(dev);
2276         while(t->bge_vid != 0) {
2277                 if ((vid == t->bge_vid) && (did == t->bge_did)) {
2278                         id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2279                             BGE_PCIMISCCTL_ASICREV_SHIFT;
2280                         if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
2281                                 /*
2282                                  * Find the ASCI revision.  Different chips
2283                                  * use different registers.
2284                                  */
2285                                 switch (pci_get_device(dev)) {
2286                                 case BCOM_DEVICEID_BCM5717:
2287                                 case BCOM_DEVICEID_BCM5718:
2288                                 case BCOM_DEVICEID_BCM5719:
2289                                 case BCOM_DEVICEID_BCM5720:
2290                                         id = pci_read_config(dev,
2291                                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
2292                                         break;
2293                                 case BCOM_DEVICEID_BCM57761:
2294                                 case BCOM_DEVICEID_BCM57765:
2295                                 case BCOM_DEVICEID_BCM57781:
2296                                 case BCOM_DEVICEID_BCM57785:
2297                                 case BCOM_DEVICEID_BCM57791:
2298                                 case BCOM_DEVICEID_BCM57795:
2299                                         id = pci_read_config(dev,
2300                                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
2301                                         break;
2302                                 default:
2303                                         id = pci_read_config(dev,
2304                                             BGE_PCI_PRODID_ASICREV, 4);
2305                                 }
2306                         }
2307                         br = bge_lookup_rev(id);
2308                         v = bge_lookup_vendor(vid);
2309                         if (bge_has_eaddr(sc) &&
2310                             pci_get_vpd_ident(dev, &pname) == 0)
2311                                 snprintf(model, 64, "%s", pname);
2312                         else
2313                                 snprintf(model, 64, "%s %s", v->v_name,
2314                                     br != NULL ? br->br_name :
2315                                     "NetXtreme Ethernet Controller");
2316                         snprintf(buf, 96, "%s, %sASIC rev. %#08x", model,
2317                             br != NULL ? "" : "unknown ", id);
2318                         device_set_desc_copy(dev, buf);
2319                         return (0);
2320                 }
2321                 t++;
2322         }
2323
2324         return (ENXIO);
2325 }
2326
2327 static void
2328 bge_dma_free(struct bge_softc *sc)
2329 {
2330         int i;
2331
2332         /* Destroy DMA maps for RX buffers. */
2333         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2334                 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2335                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2336                             sc->bge_cdata.bge_rx_std_dmamap[i]);
2337         }
2338         if (sc->bge_cdata.bge_rx_std_sparemap)
2339                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2340                     sc->bge_cdata.bge_rx_std_sparemap);
2341
2342         /* Destroy DMA maps for jumbo RX buffers. */
2343         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2344                 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2345                         bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2346                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2347         }
2348         if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2349                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2350                     sc->bge_cdata.bge_rx_jumbo_sparemap);
2351
2352         /* Destroy DMA maps for TX buffers. */
2353         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2354                 if (sc->bge_cdata.bge_tx_dmamap[i])
2355                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2356                             sc->bge_cdata.bge_tx_dmamap[i]);
2357         }
2358
2359         if (sc->bge_cdata.bge_rx_mtag)
2360                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2361         if (sc->bge_cdata.bge_mtag_jumbo)
2362                 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
2363         if (sc->bge_cdata.bge_tx_mtag)
2364                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2365
2366
2367         /* Destroy standard RX ring. */
2368         if (sc->bge_cdata.bge_rx_std_ring_map)
2369                 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2370                     sc->bge_cdata.bge_rx_std_ring_map);
2371         if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
2372                 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2373                     sc->bge_ldata.bge_rx_std_ring,
2374                     sc->bge_cdata.bge_rx_std_ring_map);
2375
2376         if (sc->bge_cdata.bge_rx_std_ring_tag)
2377                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2378
2379         /* Destroy jumbo RX ring. */
2380         if (sc->bge_cdata.bge_rx_jumbo_ring_map)
2381                 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2382                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2383
2384         if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
2385             sc->bge_ldata.bge_rx_jumbo_ring)
2386                 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2387                     sc->bge_ldata.bge_rx_jumbo_ring,
2388                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2389
2390         if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2391                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2392
2393         /* Destroy RX return ring. */
2394         if (sc->bge_cdata.bge_rx_return_ring_map)
2395                 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2396                     sc->bge_cdata.bge_rx_return_ring_map);
2397
2398         if (sc->bge_cdata.bge_rx_return_ring_map &&
2399             sc->bge_ldata.bge_rx_return_ring)
2400                 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2401                     sc->bge_ldata.bge_rx_return_ring,
2402                     sc->bge_cdata.bge_rx_return_ring_map);
2403
2404         if (sc->bge_cdata.bge_rx_return_ring_tag)
2405                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2406
2407         /* Destroy TX ring. */
2408         if (sc->bge_cdata.bge_tx_ring_map)
2409                 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2410                     sc->bge_cdata.bge_tx_ring_map);
2411
2412         if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
2413                 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2414                     sc->bge_ldata.bge_tx_ring,
2415                     sc->bge_cdata.bge_tx_ring_map);
2416
2417         if (sc->bge_cdata.bge_tx_ring_tag)
2418                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2419
2420         /* Destroy status block. */
2421         if (sc->bge_cdata.bge_status_map)
2422                 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2423                     sc->bge_cdata.bge_status_map);
2424
2425         if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
2426                 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2427                     sc->bge_ldata.bge_status_block,
2428                     sc->bge_cdata.bge_status_map);
2429
2430         if (sc->bge_cdata.bge_status_tag)
2431                 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2432
2433         /* Destroy statistics block. */
2434         if (sc->bge_cdata.bge_stats_map)
2435                 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2436                     sc->bge_cdata.bge_stats_map);
2437
2438         if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2439                 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2440                     sc->bge_ldata.bge_stats,
2441                     sc->bge_cdata.bge_stats_map);
2442
2443         if (sc->bge_cdata.bge_stats_tag)
2444                 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2445
2446         if (sc->bge_cdata.bge_buffer_tag)
2447                 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
2448
2449         /* Destroy the parent tag. */
2450         if (sc->bge_cdata.bge_parent_tag)
2451                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2452 }
2453
2454 static int
2455 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
2456     bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
2457     bus_addr_t *paddr, const char *msg)
2458 {
2459         struct bge_dmamap_arg ctx;
2460         int error;
2461
2462         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2463             alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2464             NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
2465         if (error != 0) {
2466                 device_printf(sc->bge_dev,
2467                     "could not create %s dma tag\n", msg);
2468                 return (ENOMEM);
2469         }
2470         /* Allocate DMA'able memory for ring. */
2471         error = bus_dmamem_alloc(*tag, (void **)ring,
2472             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
2473         if (error != 0) {
2474                 device_printf(sc->bge_dev,
2475                     "could not allocate DMA'able memory for %s\n", msg);
2476                 return (ENOMEM);
2477         }
2478         /* Load the address of the ring. */
2479         ctx.bge_busaddr = 0;
2480         error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr,
2481             &ctx, BUS_DMA_NOWAIT);
2482         if (error != 0) {
2483                 device_printf(sc->bge_dev,
2484                     "could not load DMA'able memory for %s\n", msg);
2485                 return (ENOMEM);
2486         }
2487         *paddr = ctx.bge_busaddr;
2488         return (0);
2489 }
2490
2491 static int
2492 bge_dma_alloc(struct bge_softc *sc)
2493 {
2494         bus_addr_t lowaddr;
2495         bus_size_t rxmaxsegsz, sbsz, txsegsz, txmaxsegsz;
2496         int i, error;
2497
2498         lowaddr = BUS_SPACE_MAXADDR;
2499         if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2500                 lowaddr = BGE_DMA_MAXADDR;
2501         /*
2502          * Allocate the parent bus DMA tag appropriate for PCI.
2503          */
2504         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2505             1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2506             NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2507             0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2508         if (error != 0) {
2509                 device_printf(sc->bge_dev,
2510                     "could not allocate parent dma tag\n");
2511                 return (ENOMEM);
2512         }
2513
2514         /* Create tag for standard RX ring. */
2515         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
2516             &sc->bge_cdata.bge_rx_std_ring_tag,
2517             (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
2518             &sc->bge_cdata.bge_rx_std_ring_map,
2519             &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
2520         if (error)
2521                 return (error);
2522
2523         /* Create tag for RX return ring. */
2524         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
2525             &sc->bge_cdata.bge_rx_return_ring_tag,
2526             (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
2527             &sc->bge_cdata.bge_rx_return_ring_map,
2528             &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
2529         if (error)
2530                 return (error);
2531
2532         /* Create tag for TX ring. */
2533         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
2534             &sc->bge_cdata.bge_tx_ring_tag,
2535             (uint8_t **)&sc->bge_ldata.bge_tx_ring,
2536             &sc->bge_cdata.bge_tx_ring_map,
2537             &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
2538         if (error)
2539                 return (error);
2540
2541         /*
2542          * Create tag for status block.
2543          * Because we only use single Tx/Rx/Rx return ring, use
2544          * minimum status block size except BCM5700 AX/BX which
2545          * seems to want to see full status block size regardless
2546          * of configured number of ring.
2547          */
2548         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2549             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
2550                 sbsz = BGE_STATUS_BLK_SZ;
2551         else
2552                 sbsz = 32;
2553         error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
2554             &sc->bge_cdata.bge_status_tag,
2555             (uint8_t **)&sc->bge_ldata.bge_status_block,
2556             &sc->bge_cdata.bge_status_map,
2557             &sc->bge_ldata.bge_status_block_paddr, "status block");
2558         if (error)
2559                 return (error);
2560
2561         /* Create tag for statistics block. */
2562         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
2563             &sc->bge_cdata.bge_stats_tag,
2564             (uint8_t **)&sc->bge_ldata.bge_stats,
2565             &sc->bge_cdata.bge_stats_map,
2566             &sc->bge_ldata.bge_stats_paddr, "statistics block");
2567         if (error)
2568                 return (error);
2569
2570         /* Create tag for jumbo RX ring. */
2571         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2572                 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
2573                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
2574                     (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
2575                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
2576                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
2577                 if (error)
2578                         return (error);
2579         }
2580
2581         /* Create parent tag for buffers. */
2582         if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
2583                 /*
2584                  * XXX
2585                  * watchdog timeout issue was observed on BCM5704 which
2586                  * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge).
2587                  * Limiting DMA address space to 32bits seems to address
2588                  * it.
2589                  */
2590                 if (sc->bge_flags & BGE_FLAG_PCIX)
2591                         lowaddr = BUS_SPACE_MAXADDR_32BIT;
2592         }
2593         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 1, 0, lowaddr,
2594             BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0,
2595             BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
2596             &sc->bge_cdata.bge_buffer_tag);
2597         if (error != 0) {
2598                 device_printf(sc->bge_dev,
2599                     "could not allocate buffer dma tag\n");
2600                 return (ENOMEM);
2601         }
2602         /* Create tag for Tx mbufs. */
2603         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2604                 txsegsz = BGE_TSOSEG_SZ;
2605                 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
2606         } else {
2607                 txsegsz = MCLBYTES;
2608                 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
2609         }
2610         error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
2611             0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2612             txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
2613             &sc->bge_cdata.bge_tx_mtag);
2614
2615         if (error) {
2616                 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
2617                 return (ENOMEM);
2618         }
2619
2620         /* Create tag for Rx mbufs. */
2621         if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
2622                 rxmaxsegsz = MJUM9BYTES;
2623         else
2624                 rxmaxsegsz = MCLBYTES;
2625         error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
2626             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1,
2627             rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
2628
2629         if (error) {
2630                 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
2631                 return (ENOMEM);
2632         }
2633
2634         /* Create DMA maps for RX buffers. */
2635         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2636             &sc->bge_cdata.bge_rx_std_sparemap);
2637         if (error) {
2638                 device_printf(sc->bge_dev,
2639                     "can't create spare DMA map for RX\n");
2640                 return (ENOMEM);
2641         }
2642         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2643                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2644                             &sc->bge_cdata.bge_rx_std_dmamap[i]);
2645                 if (error) {
2646                         device_printf(sc->bge_dev,
2647                             "can't create DMA map for RX\n");
2648                         return (ENOMEM);
2649                 }
2650         }
2651
2652         /* Create DMA maps for TX buffers. */
2653         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2654                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
2655                             &sc->bge_cdata.bge_tx_dmamap[i]);
2656                 if (error) {
2657                         device_printf(sc->bge_dev,
2658                             "can't create DMA map for TX\n");
2659                         return (ENOMEM);
2660                 }
2661         }
2662
2663         /* Create tags for jumbo RX buffers. */
2664         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2665                 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
2666                     1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2667                     NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
2668                     0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
2669                 if (error) {
2670                         device_printf(sc->bge_dev,
2671                             "could not allocate jumbo dma tag\n");
2672                         return (ENOMEM);
2673                 }
2674                 /* Create DMA maps for jumbo RX buffers. */
2675                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2676                     0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
2677                 if (error) {
2678                         device_printf(sc->bge_dev,
2679                             "can't create spare DMA map for jumbo RX\n");
2680                         return (ENOMEM);
2681                 }
2682                 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2683                         error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2684                                     0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2685                         if (error) {
2686                                 device_printf(sc->bge_dev,
2687                                     "can't create DMA map for jumbo RX\n");
2688                                 return (ENOMEM);
2689                         }
2690                 }
2691         }
2692
2693         return (0);
2694 }
2695
2696 /*
2697  * Return true if this device has more than one port.
2698  */
2699 static int
2700 bge_has_multiple_ports(struct bge_softc *sc)
2701 {
2702         device_t dev = sc->bge_dev;
2703         u_int b, d, f, fscan, s;
2704
2705         d = pci_get_domain(dev);
2706         b = pci_get_bus(dev);
2707         s = pci_get_slot(dev);
2708         f = pci_get_function(dev);
2709         for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
2710                 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
2711                         return (1);
2712         return (0);
2713 }
2714
2715 /*
2716  * Return true if MSI can be used with this device.
2717  */
2718 static int
2719 bge_can_use_msi(struct bge_softc *sc)
2720 {
2721         int can_use_msi = 0;
2722
2723         if (sc->bge_msi == 0)
2724                 return (0);
2725
2726         /* Disable MSI for polling(4). */
2727 #ifdef DEVICE_POLLING
2728         return (0);
2729 #endif
2730         switch (sc->bge_asicrev) {
2731         case BGE_ASICREV_BCM5714_A0:
2732         case BGE_ASICREV_BCM5714:
2733                 /*
2734                  * Apparently, MSI doesn't work when these chips are
2735                  * configured in single-port mode.
2736                  */
2737                 if (bge_has_multiple_ports(sc))
2738                         can_use_msi = 1;
2739                 break;
2740         case BGE_ASICREV_BCM5750:
2741                 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
2742                     sc->bge_chiprev != BGE_CHIPREV_5750_BX)
2743                         can_use_msi = 1;
2744                 break;
2745         default:
2746                 if (BGE_IS_575X_PLUS(sc))
2747                         can_use_msi = 1;
2748         }
2749         return (can_use_msi);
2750 }
2751
2752 static int
2753 bge_attach(device_t dev)
2754 {
2755         struct ifnet *ifp;
2756         struct bge_softc *sc;
2757         uint32_t hwcfg = 0, misccfg;
2758         u_char eaddr[ETHER_ADDR_LEN];
2759         int capmask, error, f, msicount, phy_addr, reg, rid, trys;
2760
2761         sc = device_get_softc(dev);
2762         sc->bge_dev = dev;
2763
2764         bge_add_sysctls(sc);
2765
2766         TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
2767
2768         /*
2769          * Map control/status registers.
2770          */
2771         pci_enable_busmaster(dev);
2772
2773         rid = PCIR_BAR(0);
2774         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2775             RF_ACTIVE);
2776
2777         if (sc->bge_res == NULL) {
2778                 device_printf (sc->bge_dev, "couldn't map memory\n");
2779                 error = ENXIO;
2780                 goto fail;
2781         }
2782
2783         /* Save various chip information. */
2784         sc->bge_chipid =
2785             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2786             BGE_PCIMISCCTL_ASICREV_SHIFT;
2787         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) {
2788                 /*
2789                  * Find the ASCI revision.  Different chips use different
2790                  * registers.
2791                  */
2792                 switch (pci_get_device(dev)) {
2793                 case BCOM_DEVICEID_BCM5717:
2794                 case BCOM_DEVICEID_BCM5718:
2795                 case BCOM_DEVICEID_BCM5719:
2796                 case BCOM_DEVICEID_BCM5720:
2797                         sc->bge_chipid = pci_read_config(dev,
2798                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
2799                         break;
2800                 case BCOM_DEVICEID_BCM57761:
2801                 case BCOM_DEVICEID_BCM57765:
2802                 case BCOM_DEVICEID_BCM57781:
2803                 case BCOM_DEVICEID_BCM57785:
2804                 case BCOM_DEVICEID_BCM57791:
2805                 case BCOM_DEVICEID_BCM57795:
2806                         sc->bge_chipid = pci_read_config(dev,
2807                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
2808                         break;
2809                 default:
2810                         sc->bge_chipid = pci_read_config(dev,
2811                             BGE_PCI_PRODID_ASICREV, 4);
2812                 }
2813         }
2814         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2815         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2816
2817         /* Set default PHY address. */
2818         phy_addr = 1;
2819          /*
2820           * PHY address mapping for various devices.
2821           *
2822           *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
2823           * ---------+-------+-------+-------+-------+
2824           * BCM57XX  |   1   |   X   |   X   |   X   |
2825           * BCM5704  |   1   |   X   |   1   |   X   |
2826           * BCM5717  |   1   |   8   |   2   |   9   |
2827           * BCM5719  |   1   |   8   |   2   |   9   |
2828           * BCM5720  |   1   |   8   |   2   |   9   |
2829           *
2830           * Other addresses may respond but they are not
2831           * IEEE compliant PHYs and should be ignored.
2832           */
2833         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2834             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2835             sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2836                 f = pci_get_function(dev);
2837                 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) {
2838                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
2839                             BGE_SGDIGSTS_IS_SERDES)
2840                                 phy_addr = f + 8;
2841                         else
2842                                 phy_addr = f + 1;
2843                 } else {
2844                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
2845                             BGE_CPMU_PHY_STRAP_IS_SERDES)
2846                                 phy_addr = f + 8;
2847                         else
2848                                 phy_addr = f + 1;
2849                 }
2850         }
2851
2852         /*
2853          * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the
2854          * 5705 A0 and A1 chips.
2855          */
2856         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2857             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2858             (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2859             sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
2860             sc->bge_asicrev == BGE_ASICREV_BCM5906)
2861                 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
2862
2863         if (bge_has_eaddr(sc))
2864                 sc->bge_flags |= BGE_FLAG_EADDR;
2865
2866         /* Save chipset family. */
2867         switch (sc->bge_asicrev) {
2868         case BGE_ASICREV_BCM5717:
2869         case BGE_ASICREV_BCM5719:
2870         case BGE_ASICREV_BCM5720:
2871         case BGE_ASICREV_BCM57765:
2872                 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
2873                     BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
2874                     BGE_FLAG_JUMBO_FRAME;
2875                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
2876                     sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
2877                         /* Jumbo frame on BCM5719 A0 does not work. */
2878                         sc->bge_flags &= ~BGE_FLAG_JUMBO;
2879                 }
2880                 break;
2881         case BGE_ASICREV_BCM5755:
2882         case BGE_ASICREV_BCM5761:
2883         case BGE_ASICREV_BCM5784:
2884         case BGE_ASICREV_BCM5785:
2885         case BGE_ASICREV_BCM5787:
2886         case BGE_ASICREV_BCM57780:
2887                 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2888                     BGE_FLAG_5705_PLUS;
2889                 break;
2890         case BGE_ASICREV_BCM5700:
2891         case BGE_ASICREV_BCM5701:
2892         case BGE_ASICREV_BCM5703:
2893         case BGE_ASICREV_BCM5704:
2894                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2895                 break;
2896         case BGE_ASICREV_BCM5714_A0:
2897         case BGE_ASICREV_BCM5780:
2898         case BGE_ASICREV_BCM5714:
2899                 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
2900                 /* FALLTHROUGH */
2901         case BGE_ASICREV_BCM5750:
2902         case BGE_ASICREV_BCM5752:
2903         case BGE_ASICREV_BCM5906:
2904                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2905                 /* FALLTHROUGH */
2906         case BGE_ASICREV_BCM5705:
2907                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2908                 break;
2909         }
2910
2911         /* Set various PHY bug flags. */
2912         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2913             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2914                 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
2915         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2916             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2917                 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
2918         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2919                 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
2920         if (pci_get_subvendor(dev) == DELL_VENDORID)
2921                 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
2922         if ((BGE_IS_5705_PLUS(sc)) &&
2923             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2924             sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
2925             sc->bge_asicrev != BGE_ASICREV_BCM5719 &&
2926             sc->bge_asicrev != BGE_ASICREV_BCM5720 &&
2927             sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2928             sc->bge_asicrev != BGE_ASICREV_BCM57765 &&
2929             sc->bge_asicrev != BGE_ASICREV_BCM57780) {
2930                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2931                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2932                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2933                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2934                         if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
2935                             pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
2936                                 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
2937                         if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
2938                                 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
2939                 } else
2940                         sc->bge_phy_flags |= BGE_PHY_BER_BUG;
2941         }
2942
2943         /* Identify the chips that use an CPMU. */
2944         if (BGE_IS_5717_PLUS(sc) ||
2945             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2946             sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2947             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2948             sc->bge_asicrev == BGE_ASICREV_BCM57780)
2949                 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
2950         if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
2951                 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
2952         else
2953                 sc->bge_mi_mode = BGE_MIMODE_BASE;
2954         /* Enable auto polling for BCM570[0-5]. */
2955         if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
2956                 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
2957
2958         /*
2959          * All Broadcom controllers have 4GB boundary DMA bug.
2960          * Whenever an address crosses a multiple of the 4GB boundary
2961          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
2962          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
2963          * state machine will lockup and cause the device to hang.
2964          */
2965         sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
2966
2967         /* BCM5755 or higher and BCM5906 have short DMA bug. */
2968         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
2969                 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
2970
2971         /*
2972          * BCM5719 cannot handle DMA requests for DMA segments that
2973          * have larger than 4KB in size.  However the maximum DMA
2974          * segment size created in DMA tag is 4KB for TSO, so we
2975          * wouldn't encounter the issue here.
2976          */
2977         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2978                 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG;
2979
2980         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID;
2981         if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
2982                 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2983                     misccfg == BGE_MISCCFG_BOARD_ID_5788M)
2984                         sc->bge_flags |= BGE_FLAG_5788;
2985         }
2986
2987         capmask = BMSR_DEFCAPMASK;
2988         if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
2989             (misccfg == 0x4000 || misccfg == 0x8000)) ||
2990             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2991             pci_get_vendor(dev) == BCOM_VENDORID &&
2992             (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 ||
2993             pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 ||
2994             pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) ||
2995             (pci_get_vendor(dev) == BCOM_VENDORID &&
2996             (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F ||
2997             pci_get_device(dev) == BCOM_DEVICEID_BCM5753F ||
2998             pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) ||
2999             pci_get_device(dev) == BCOM_DEVICEID_BCM57790 ||
3000             sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3001                 /* These chips are 10/100 only. */
3002                 capmask &= ~BMSR_EXTSTAT;
3003         }
3004
3005         /*
3006          * Some controllers seem to require a special firmware to use
3007          * TSO. But the firmware is not available to FreeBSD and Linux
3008          * claims that the TSO performed by the firmware is slower than
3009          * hardware based TSO. Moreover the firmware based TSO has one
3010          * known bug which can't handle TSO if ethernet header + IP/TCP
3011          * header is greater than 80 bytes. The workaround for the TSO
3012          * bug exist but it seems it's too expensive than not using
3013          * TSO at all. Some hardwares also have the TSO bug so limit
3014          * the TSO to the controllers that are not affected TSO issues
3015          * (e.g. 5755 or higher).
3016          */
3017         if (BGE_IS_5717_PLUS(sc)) {
3018                 /* BCM5717 requires different TSO configuration. */
3019                 sc->bge_flags |= BGE_FLAG_TSO3;
3020                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3021                     sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3022                         /* TSO on BCM5719 A0 does not work. */
3023                         sc->bge_flags &= ~BGE_FLAG_TSO3;
3024                 }
3025         } else if (BGE_IS_5755_PLUS(sc)) {
3026                 /*
3027                  * BCM5754 and BCM5787 shares the same ASIC id so
3028                  * explicit device id check is required.
3029                  * Due to unknown reason TSO does not work on BCM5755M.
3030                  */
3031                 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
3032                     pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
3033                     pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
3034                         sc->bge_flags |= BGE_FLAG_TSO;
3035         }
3036
3037         /*
3038          * Check if this is a PCI-X or PCI Express device.
3039          */
3040         if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
3041                 /*
3042                  * Found a PCI Express capabilities register, this
3043                  * must be a PCI Express device.
3044                  */
3045                 sc->bge_flags |= BGE_FLAG_PCIE;
3046                 sc->bge_expcap = reg;
3047                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3048                     sc->bge_asicrev == BGE_ASICREV_BCM5720)
3049                         pci_set_max_read_req(dev, 2048);
3050                 else if (pci_get_max_read_req(dev) != 4096)
3051                         pci_set_max_read_req(dev, 4096);
3052         } else {
3053                 /*
3054                  * Check if the device is in PCI-X Mode.
3055                  * (This bit is not valid on PCI Express controllers.)
3056                  */
3057                 if (pci_find_cap(dev, PCIY_PCIX, &reg) == 0)
3058                         sc->bge_pcixcap = reg;
3059                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
3060                     BGE_PCISTATE_PCI_BUSMODE) == 0)
3061                         sc->bge_flags |= BGE_FLAG_PCIX;
3062         }
3063
3064         /*
3065          * The 40bit DMA bug applies to the 5714/5715 controllers and is
3066          * not actually a MAC controller bug but an issue with the embedded
3067          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
3068          */
3069         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
3070                 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
3071         /*
3072          * Allocate the interrupt, using MSI if possible.  These devices
3073          * support 8 MSI messages, but only the first one is used in
3074          * normal operation.
3075          */
3076         rid = 0;
3077         if (pci_find_cap(sc->bge_dev, PCIY_MSI, &reg) == 0) {
3078                 sc->bge_msicap = reg;
3079                 if (bge_can_use_msi(sc)) {
3080                         msicount = pci_msi_count(dev);
3081                         if (msicount > 1)
3082                                 msicount = 1;
3083                 } else
3084                         msicount = 0;
3085                 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
3086                         rid = 1;
3087                         sc->bge_flags |= BGE_FLAG_MSI;
3088                 }
3089         }
3090
3091         /*
3092          * All controllers except BCM5700 supports tagged status but
3093          * we use tagged status only for MSI case on BCM5717. Otherwise
3094          * MSI on BCM5717 does not work.
3095          */
3096 #ifndef DEVICE_POLLING
3097         if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
3098                 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
3099 #endif
3100
3101         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3102             RF_SHAREABLE | RF_ACTIVE);
3103
3104         if (sc->bge_irq == NULL) {
3105                 device_printf(sc->bge_dev, "couldn't map interrupt\n");
3106                 error = ENXIO;
3107                 goto fail;
3108         }
3109
3110         device_printf(dev,
3111             "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
3112             sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
3113             (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" :
3114             ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI"));
3115
3116         BGE_LOCK_INIT(sc, device_get_nameunit(dev));
3117
3118         /* Try to reset the chip. */
3119         if (bge_reset(sc)) {
3120                 device_printf(sc->bge_dev, "chip reset failed\n");
3121                 error = ENXIO;
3122                 goto fail;
3123         }
3124
3125         sc->bge_asf_mode = 0;
3126         if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3127             BGE_SRAM_DATA_SIG_MAGIC)) {
3128                 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG)
3129                     & BGE_HWCFG_ASF) {
3130                         sc->bge_asf_mode |= ASF_ENABLE;
3131                         sc->bge_asf_mode |= ASF_STACKUP;
3132                         if (BGE_IS_575X_PLUS(sc))
3133                                 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3134                 }
3135         }
3136
3137         /* Try to reset the chip again the nice way. */
3138         bge_stop_fw(sc);
3139         bge_sig_pre_reset(sc, BGE_RESET_STOP);
3140         if (bge_reset(sc)) {
3141                 device_printf(sc->bge_dev, "chip reset failed\n");
3142                 error = ENXIO;
3143                 goto fail;
3144         }
3145
3146         bge_sig_legacy(sc, BGE_RESET_STOP);
3147         bge_sig_post_reset(sc, BGE_RESET_STOP);
3148
3149         if (bge_chipinit(sc)) {
3150                 device_printf(sc->bge_dev, "chip initialization failed\n");
3151                 error = ENXIO;
3152                 goto fail;
3153         }
3154
3155         error = bge_get_eaddr(sc, eaddr);
3156         if (error) {
3157                 device_printf(sc->bge_dev,
3158                     "failed to read station address\n");
3159                 error = ENXIO;
3160                 goto fail;
3161         }
3162
3163         /* 5705 limits RX return ring to 512 entries. */
3164         if (BGE_IS_5717_PLUS(sc))
3165                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3166         else if (BGE_IS_5705_PLUS(sc))
3167                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3168         else
3169                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3170
3171         if (bge_dma_alloc(sc)) {
3172                 device_printf(sc->bge_dev,
3173                     "failed to allocate DMA resources\n");
3174                 error = ENXIO;
3175                 goto fail;
3176         }
3177
3178         /* Set default tuneable values. */
3179         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3180         sc->bge_rx_coal_ticks = 150;
3181         sc->bge_tx_coal_ticks = 150;
3182         sc->bge_rx_max_coal_bds = 10;
3183         sc->bge_tx_max_coal_bds = 10;
3184
3185         /* Initialize checksum features to use. */
3186         sc->bge_csum_features = BGE_CSUM_FEATURES;
3187         if (sc->bge_forced_udpcsum != 0)
3188                 sc->bge_csum_features |= CSUM_UDP;
3189
3190         /* Set up ifnet structure */
3191         ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
3192         if (ifp == NULL) {
3193                 device_printf(sc->bge_dev, "failed to if_alloc()\n");
3194                 error = ENXIO;
3195                 goto fail;
3196         }
3197         ifp->if_softc = sc;
3198         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3199         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3200         ifp->if_ioctl = bge_ioctl;
3201         ifp->if_start = bge_start;
3202         ifp->if_init = bge_init;
3203         ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
3204         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
3205         IFQ_SET_READY(&ifp->if_snd);
3206         ifp->if_hwassist = sc->bge_csum_features;
3207         ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3208             IFCAP_VLAN_MTU;
3209         if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3210                 ifp->if_hwassist |= CSUM_TSO;
3211                 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO;
3212         }
3213 #ifdef IFCAP_VLAN_HWCSUM
3214         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
3215 #endif
3216         ifp->if_capenable = ifp->if_capabilities;
3217 #ifdef DEVICE_POLLING
3218         ifp->if_capabilities |= IFCAP_POLLING;
3219 #endif
3220
3221         /*
3222          * 5700 B0 chips do not support checksumming correctly due
3223          * to hardware bugs.
3224          */
3225         if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
3226                 ifp->if_capabilities &= ~IFCAP_HWCSUM;
3227                 ifp->if_capenable &= ~IFCAP_HWCSUM;
3228                 ifp->if_hwassist = 0;
3229         }
3230
3231         /*
3232          * Figure out what sort of media we have by checking the
3233          * hardware config word in the first 32k of NIC internal memory,
3234          * or fall back to examining the EEPROM if necessary.
3235          * Note: on some BCM5700 cards, this value appears to be unset.
3236          * If that's the case, we have to rely on identifying the NIC
3237          * by its PCI subsystem ID, as we do below for the SysKonnect
3238          * SK-9D41.
3239          */
3240         if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
3241                 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3242         else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
3243             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3244                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
3245                     sizeof(hwcfg))) {
3246                         device_printf(sc->bge_dev, "failed to read EEPROM\n");
3247                         error = ENXIO;
3248                         goto fail;
3249                 }
3250                 hwcfg = ntohl(hwcfg);
3251         }
3252
3253         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
3254         if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
3255             SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
3256                 if (BGE_IS_5714_FAMILY(sc))
3257                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
3258                 else
3259                         sc->bge_flags |= BGE_FLAG_TBI;
3260         }
3261
3262         if (sc->bge_flags & BGE_FLAG_TBI) {
3263                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3264                     bge_ifmedia_sts);
3265                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
3266                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
3267                     0, NULL);
3268                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3269                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3270                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3271         } else {
3272                 /*
3273                  * Do transceiver setup and tell the firmware the
3274                  * driver is down so we can try to get access the
3275                  * probe if ASF is running.  Retry a couple of times
3276                  * if we get a conflict with the ASF firmware accessing
3277                  * the PHY.
3278                  */
3279                 trys = 0;
3280                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3281 again:
3282                 bge_asf_driver_up(sc);
3283
3284                 error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd,
3285                     bge_ifmedia_sts, capmask, phy_addr, MII_OFFSET_ANY,
3286                     MIIF_DOPAUSE);
3287                 if (error != 0) {
3288                         if (trys++ < 4) {
3289                                 device_printf(sc->bge_dev, "Try again\n");
3290                                 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR,
3291                                     BMCR_RESET);
3292                                 goto again;
3293                         }
3294                         device_printf(sc->bge_dev, "attaching PHYs failed\n");
3295                         goto fail;
3296                 }
3297
3298                 /*
3299                  * Now tell the firmware we are going up after probing the PHY
3300                  */
3301                 if (sc->bge_asf_mode & ASF_STACKUP)
3302                         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3303         }
3304
3305         /*
3306          * When using the BCM5701 in PCI-X mode, data corruption has
3307          * been observed in the first few bytes of some received packets.
3308          * Aligning the packet buffer in memory eliminates the corruption.
3309          * Unfortunately, this misaligns the packet payloads.  On platforms
3310          * which do not support unaligned accesses, we will realign the
3311          * payloads by copying the received packets.
3312          */
3313         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
3314             sc->bge_flags & BGE_FLAG_PCIX)
3315                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
3316
3317         /*
3318          * Call MI attach routine.
3319          */
3320         ether_ifattach(ifp, eaddr);
3321         callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
3322
3323         /* Tell upper layer we support long frames. */
3324         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
3325
3326         /*
3327          * Hookup IRQ last.
3328          */
3329         if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
3330                 /* Take advantage of single-shot MSI. */
3331                 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
3332                     ~BGE_MSIMODE_ONE_SHOT_DISABLE);
3333                 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
3334                     taskqueue_thread_enqueue, &sc->bge_tq);
3335                 if (sc->bge_tq == NULL) {
3336                         device_printf(dev, "could not create taskqueue.\n");
3337                         ether_ifdetach(ifp);
3338                         error = ENXIO;
3339                         goto fail;
3340                 }
3341                 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq",
3342                     device_get_nameunit(sc->bge_dev));
3343                 error = bus_setup_intr(dev, sc->bge_irq,
3344                     INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
3345                     &sc->bge_intrhand);
3346                 if (error)
3347                         ether_ifdetach(ifp);
3348         } else
3349                 error = bus_setup_intr(dev, sc->bge_irq,
3350                     INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
3351                     &sc->bge_intrhand);
3352
3353         if (error) {
3354                 bge_detach(dev);
3355                 device_printf(sc->bge_dev, "couldn't set up irq\n");
3356         }
3357
3358         return (0);
3359
3360 fail:
3361         bge_release_resources(sc);
3362
3363         return (error);
3364 }
3365
3366 static int
3367 bge_detach(device_t dev)
3368 {
3369         struct bge_softc *sc;
3370         struct ifnet *ifp;
3371
3372         sc = device_get_softc(dev);
3373         ifp = sc->bge_ifp;
3374
3375 #ifdef DEVICE_POLLING
3376         if (ifp->if_capenable & IFCAP_POLLING)
3377                 ether_poll_deregister(ifp);
3378 #endif
3379
3380         BGE_LOCK(sc);
3381         bge_stop(sc);
3382         bge_reset(sc);
3383         BGE_UNLOCK(sc);
3384
3385         callout_drain(&sc->bge_stat_ch);
3386
3387         if (sc->bge_tq)
3388                 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3389         ether_ifdetach(ifp);
3390
3391         if (sc->bge_flags & BGE_FLAG_TBI) {
3392                 ifmedia_removeall(&sc->bge_ifmedia);
3393         } else {
3394                 bus_generic_detach(dev);
3395                 device_delete_child(dev, sc->bge_miibus);
3396         }
3397
3398         bge_release_resources(sc);
3399
3400         return (0);
3401 }
3402
3403 static void
3404 bge_release_resources(struct bge_softc *sc)
3405 {
3406         device_t dev;
3407
3408         dev = sc->bge_dev;
3409
3410         if (sc->bge_tq != NULL)
3411                 taskqueue_free(sc->bge_tq);
3412
3413         if (sc->bge_intrhand != NULL)
3414                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3415
3416         if (sc->bge_irq != NULL)
3417                 bus_release_resource(dev, SYS_RES_IRQ,
3418                     sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
3419
3420         if (sc->bge_flags & BGE_FLAG_MSI)
3421                 pci_release_msi(dev);
3422
3423         if (sc->bge_res != NULL)
3424                 bus_release_resource(dev, SYS_RES_MEMORY,
3425                     PCIR_BAR(0), sc->bge_res);
3426
3427         if (sc->bge_ifp != NULL)
3428                 if_free(sc->bge_ifp);
3429
3430         bge_dma_free(sc);
3431
3432         if (mtx_initialized(&sc->bge_mtx))      /* XXX */
3433                 BGE_LOCK_DESTROY(sc);
3434 }
3435
3436 static int
3437 bge_reset(struct bge_softc *sc)
3438 {
3439         device_t dev;
3440         uint32_t cachesize, command, pcistate, reset, val;
3441         void (*write_op)(struct bge_softc *, int, int);
3442         uint16_t devctl;
3443         int i;
3444
3445         dev = sc->bge_dev;
3446
3447         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
3448             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3449                 if (sc->bge_flags & BGE_FLAG_PCIE)
3450                         write_op = bge_writemem_direct;
3451                 else
3452                         write_op = bge_writemem_ind;
3453         } else
3454                 write_op = bge_writereg_ind;
3455
3456         /* Save some important PCI state. */
3457         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
3458         command = pci_read_config(dev, BGE_PCI_CMD, 4);
3459         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3460
3461         pci_write_config(dev, BGE_PCI_MISC_CTL,
3462             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3463             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3464
3465         /* Disable fastboot on controllers that support it. */
3466         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
3467             BGE_IS_5755_PLUS(sc)) {
3468                 if (bootverbose)
3469                         device_printf(dev, "Disabling fastboot\n");
3470                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
3471         }
3472
3473         /*
3474          * Write the magic number to SRAM at offset 0xB50.
3475          * When firmware finishes its initialization it will
3476          * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
3477          */
3478         bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
3479
3480         reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
3481
3482         /* XXX: Broadcom Linux driver. */
3483         if (sc->bge_flags & BGE_FLAG_PCIE) {
3484                 if (CSR_READ_4(sc, 0x7E2C) == 0x60)     /* PCIE 1.0 */
3485                         CSR_WRITE_4(sc, 0x7E2C, 0x20);
3486                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3487                         /* Prevent PCIE link training during global reset */
3488                         CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
3489                         reset |= 1 << 29;
3490                 }
3491         }
3492
3493         /*
3494          * Set GPHY Power Down Override to leave GPHY
3495          * powered up in D0 uninitialized.
3496          */
3497         if (BGE_IS_5705_PLUS(sc) &&
3498             (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0)
3499                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
3500
3501         /* Issue global reset */
3502         write_op(sc, BGE_MISC_CFG, reset);
3503
3504         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3505                 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3506                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
3507                     val | BGE_VCPU_STATUS_DRV_RESET);
3508                 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
3509                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
3510                     val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
3511         }
3512
3513         DELAY(1000);
3514
3515         /* XXX: Broadcom Linux driver. */
3516         if (sc->bge_flags & BGE_FLAG_PCIE) {
3517                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
3518                         DELAY(500000); /* wait for link training to complete */
3519                         val = pci_read_config(dev, 0xC4, 4);
3520                         pci_write_config(dev, 0xC4, val | (1 << 15), 4);
3521                 }
3522                 devctl = pci_read_config(dev,
3523                     sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
3524                 /* Clear enable no snoop and disable relaxed ordering. */
3525                 devctl &= ~(PCIM_EXP_CTL_RELAXED_ORD_ENABLE |
3526                     PCIM_EXP_CTL_NOSNOOP_ENABLE);
3527                 /* Set PCIE max payload size to 128. */
3528                 devctl &= ~PCIM_EXP_CTL_MAX_PAYLOAD;
3529                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL,
3530                     devctl, 2);
3531                 /* Clear error status. */
3532                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA,
3533                     PCIM_EXP_STA_CORRECTABLE_ERROR |
3534                     PCIM_EXP_STA_NON_FATAL_ERROR | PCIM_EXP_STA_FATAL_ERROR |
3535                     PCIM_EXP_STA_UNSUPPORTED_REQ, 2);
3536         }
3537
3538         /* Reset some of the PCI state that got zapped by reset. */
3539         pci_write_config(dev, BGE_PCI_MISC_CTL,
3540             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3541             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3542         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
3543         pci_write_config(dev, BGE_PCI_CMD, command, 4);
3544         write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
3545         /*
3546          * Disable PCI-X relaxed ordering to ensure status block update
3547          * comes first then packet buffer DMA. Otherwise driver may
3548          * read stale status block.
3549          */
3550         if (sc->bge_flags & BGE_FLAG_PCIX) {
3551                 devctl = pci_read_config(dev,
3552                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
3553                 devctl &= ~PCIXM_COMMAND_ERO;
3554                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
3555                         devctl &= ~PCIXM_COMMAND_MAX_READ;
3556                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
3557                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3558                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
3559                             PCIXM_COMMAND_MAX_READ);
3560                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
3561                 }
3562                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
3563                     devctl, 2);
3564         }
3565         /* Re-enable MSI, if necessary, and enable the memory arbiter. */
3566         if (BGE_IS_5714_FAMILY(sc)) {
3567                 /* This chip disables MSI on reset. */
3568                 if (sc->bge_flags & BGE_FLAG_MSI) {
3569                         val = pci_read_config(dev,
3570                             sc->bge_msicap + PCIR_MSI_CTRL, 2);
3571                         pci_write_config(dev,
3572                             sc->bge_msicap + PCIR_MSI_CTRL,
3573                             val | PCIM_MSICTRL_MSI_ENABLE, 2);
3574                         val = CSR_READ_4(sc, BGE_MSI_MODE);
3575                         CSR_WRITE_4(sc, BGE_MSI_MODE,
3576                             val | BGE_MSIMODE_ENABLE);
3577                 }
3578                 val = CSR_READ_4(sc, BGE_MARB_MODE);
3579                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
3580         } else
3581                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3582
3583         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3584                 for (i = 0; i < BGE_TIMEOUT; i++) {
3585                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3586                         if (val & BGE_VCPU_STATUS_INIT_DONE)
3587                                 break;
3588                         DELAY(100);
3589                 }
3590                 if (i == BGE_TIMEOUT) {
3591                         device_printf(dev, "reset timed out\n");
3592                         return (1);
3593                 }
3594         } else {
3595                 /*
3596                  * Poll until we see the 1's complement of the magic number.
3597                  * This indicates that the firmware initialization is complete.
3598                  * We expect this to fail if no chip containing the Ethernet
3599                  * address is fitted though.
3600                  */
3601                 for (i = 0; i < BGE_TIMEOUT; i++) {
3602                         DELAY(10);
3603                         val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
3604                         if (val == ~BGE_SRAM_FW_MB_MAGIC)
3605                                 break;
3606                 }
3607
3608                 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
3609                         device_printf(dev,
3610                             "firmware handshake timed out, found 0x%08x\n",
3611                             val);
3612                 /* BCM57765 A0 needs additional time before accessing. */
3613                 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
3614                         DELAY(10 * 1000);       /* XXX */
3615         }
3616
3617         /*
3618          * XXX Wait for the value of the PCISTATE register to
3619          * return to its original pre-reset state. This is a
3620          * fairly good indicator of reset completion. If we don't
3621          * wait for the reset to fully complete, trying to read
3622          * from the device's non-PCI registers may yield garbage
3623          * results.
3624          */
3625         for (i = 0; i < BGE_TIMEOUT; i++) {
3626                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
3627                         break;
3628                 DELAY(10);
3629         }
3630
3631         /* Fix up byte swapping. */
3632         CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
3633
3634         /* Tell the ASF firmware we are up */
3635         if (sc->bge_asf_mode & ASF_STACKUP)
3636                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3637
3638         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
3639
3640         /*
3641          * The 5704 in TBI mode apparently needs some special
3642          * adjustment to insure the SERDES drive level is set
3643          * to 1.2V.
3644          */
3645         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
3646             sc->bge_flags & BGE_FLAG_TBI) {
3647                 val = CSR_READ_4(sc, BGE_SERDES_CFG);
3648                 val = (val & ~0xFFF) | 0x880;
3649                 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
3650         }
3651
3652         /* XXX: Broadcom Linux driver. */
3653         if (sc->bge_flags & BGE_FLAG_PCIE &&
3654             !BGE_IS_5717_PLUS(sc) &&
3655             sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
3656             sc->bge_asicrev != BGE_ASICREV_BCM5785) {
3657                 /* Enable Data FIFO protection. */
3658                 val = CSR_READ_4(sc, 0x7C00);
3659                 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
3660         }
3661         DELAY(10000);
3662
3663         if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
3664                 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
3665                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
3666
3667         return (0);
3668 }
3669
3670 static __inline void
3671 bge_rxreuse_std(struct bge_softc *sc, int i)
3672 {
3673         struct bge_rx_bd *r;
3674
3675         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
3676         r->bge_flags = BGE_RXBDFLAG_END;
3677         r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
3678         r->bge_idx = i;
3679         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3680 }
3681
3682 static __inline void
3683 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
3684 {
3685         struct bge_extrx_bd *r;
3686
3687         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
3688         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
3689         r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
3690         r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
3691         r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
3692         r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
3693         r->bge_idx = i;
3694         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3695 }
3696
3697 /*
3698  * Frame reception handling. This is called if there's a frame
3699  * on the receive return list.
3700  *
3701  * Note: we have to be able to handle two possibilities here:
3702  * 1) the frame is from the jumbo receive ring
3703  * 2) the frame is from the standard receive ring
3704  */
3705
3706 static int
3707 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
3708 {
3709         struct ifnet *ifp;
3710         int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
3711         uint16_t rx_cons;
3712
3713         rx_cons = sc->bge_rx_saved_considx;
3714
3715         /* Nothing to do. */
3716         if (rx_cons == rx_prod)
3717                 return (rx_npkts);
3718
3719         ifp = sc->bge_ifp;
3720
3721         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3722             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
3723         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3724             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
3725         if (BGE_IS_JUMBO_CAPABLE(sc) &&
3726             ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
3727             (MCLBYTES - ETHER_ALIGN))
3728                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3729                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
3730
3731         while (rx_cons != rx_prod) {
3732                 struct bge_rx_bd        *cur_rx;
3733                 uint32_t                rxidx;
3734                 struct mbuf             *m = NULL;
3735                 uint16_t                vlan_tag = 0;
3736                 int                     have_tag = 0;
3737
3738 #ifdef DEVICE_POLLING
3739                 if (ifp->if_capenable & IFCAP_POLLING) {
3740                         if (sc->rxcycles <= 0)
3741                                 break;
3742                         sc->rxcycles--;
3743                 }
3744 #endif
3745
3746                 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
3747
3748                 rxidx = cur_rx->bge_idx;
3749                 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
3750
3751                 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
3752                     cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
3753                         have_tag = 1;
3754                         vlan_tag = cur_rx->bge_vlan_tag;
3755                 }
3756
3757                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
3758                         jumbocnt++;
3759                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
3760                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3761                                 bge_rxreuse_jumbo(sc, rxidx);
3762                                 continue;
3763                         }
3764                         if (bge_newbuf_jumbo(sc, rxidx) != 0) {
3765                                 bge_rxreuse_jumbo(sc, rxidx);
3766                                 ifp->if_iqdrops++;
3767                                 continue;
3768                         }
3769                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3770                 } else {
3771                         stdcnt++;
3772                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
3773                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3774                                 bge_rxreuse_std(sc, rxidx);
3775                                 continue;
3776                         }
3777                         if (bge_newbuf_std(sc, rxidx) != 0) {
3778                                 bge_rxreuse_std(sc, rxidx);
3779                                 ifp->if_iqdrops++;
3780                                 continue;
3781                         }
3782                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3783                 }
3784
3785                 ifp->if_ipackets++;
3786 #ifndef __NO_STRICT_ALIGNMENT
3787                 /*
3788                  * For architectures with strict alignment we must make sure
3789                  * the payload is aligned.
3790                  */
3791                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
3792                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
3793                             cur_rx->bge_len);
3794                         m->m_data += ETHER_ALIGN;
3795                 }
3796 #endif
3797                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3798                 m->m_pkthdr.rcvif = ifp;
3799
3800                 if (ifp->if_capenable & IFCAP_RXCSUM)
3801                         bge_rxcsum(sc, cur_rx, m);
3802
3803                 /*
3804                  * If we received a packet with a vlan tag,
3805                  * attach that information to the packet.
3806                  */
3807                 if (have_tag) {
3808                         m->m_pkthdr.ether_vtag = vlan_tag;
3809                         m->m_flags |= M_VLANTAG;
3810                 }
3811
3812                 if (holdlck != 0) {
3813                         BGE_UNLOCK(sc);
3814                         (*ifp->if_input)(ifp, m);
3815                         BGE_LOCK(sc);
3816                 } else
3817                         (*ifp->if_input)(ifp, m);
3818                 rx_npkts++;
3819
3820                 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
3821                         return (rx_npkts);
3822         }
3823
3824         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3825             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
3826         if (stdcnt > 0)
3827                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3828                     sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
3829
3830         if (jumbocnt > 0)
3831                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3832                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
3833
3834         sc->bge_rx_saved_considx = rx_cons;
3835         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3836         if (stdcnt)
3837                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
3838                     BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT);
3839         if (jumbocnt)
3840                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
3841                     BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT);
3842 #ifdef notyet
3843         /*
3844          * This register wraps very quickly under heavy packet drops.
3845          * If you need correct statistics, you can enable this check.
3846          */
3847         if (BGE_IS_5705_PLUS(sc))
3848                 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3849 #endif
3850         return (rx_npkts);
3851 }
3852
3853 static void
3854 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
3855 {
3856
3857         if (BGE_IS_5717_PLUS(sc)) {
3858                 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
3859                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3860                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3861                                 if ((cur_rx->bge_error_flag &
3862                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
3863                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3864                         }
3865                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
3866                                 m->m_pkthdr.csum_data =
3867                                     cur_rx->bge_tcp_udp_csum;
3868                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
3869                                     CSUM_PSEUDO_HDR;
3870                         }
3871                 }
3872         } else {
3873                 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3874                         m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3875                         if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
3876                                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3877                 }
3878                 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
3879                     m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
3880                         m->m_pkthdr.csum_data =
3881                             cur_rx->bge_tcp_udp_csum;
3882                         m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
3883                             CSUM_PSEUDO_HDR;
3884                 }
3885         }
3886 }
3887
3888 static void
3889 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
3890 {
3891         struct bge_tx_bd *cur_tx;
3892         struct ifnet *ifp;
3893
3894         BGE_LOCK_ASSERT(sc);
3895
3896         /* Nothing to do. */
3897         if (sc->bge_tx_saved_considx == tx_cons)
3898                 return;
3899
3900         ifp = sc->bge_ifp;
3901
3902         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
3903             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
3904         /*
3905          * Go through our tx ring and free mbufs for those
3906          * frames that have been sent.
3907          */
3908         while (sc->bge_tx_saved_considx != tx_cons) {
3909                 uint32_t                idx;
3910
3911                 idx = sc->bge_tx_saved_considx;
3912                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
3913                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
3914                         ifp->if_opackets++;
3915                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
3916                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
3917                             sc->bge_cdata.bge_tx_dmamap[idx],
3918                             BUS_DMASYNC_POSTWRITE);
3919                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
3920                             sc->bge_cdata.bge_tx_dmamap[idx]);
3921                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
3922                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
3923                 }
3924                 sc->bge_txcnt--;
3925                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3926         }
3927
3928         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3929         if (sc->bge_txcnt == 0)
3930                 sc->bge_timer = 0;
3931 }
3932
3933 #ifdef DEVICE_POLLING
3934 static int
3935 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3936 {
3937         struct bge_softc *sc = ifp->if_softc;
3938         uint16_t rx_prod, tx_cons;
3939         uint32_t statusword;
3940         int rx_npkts = 0;
3941
3942         BGE_LOCK(sc);
3943         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3944                 BGE_UNLOCK(sc);
3945                 return (rx_npkts);
3946         }
3947
3948         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3949             sc->bge_cdata.bge_status_map,
3950             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3951         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3952         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3953
3954         statusword = sc->bge_ldata.bge_status_block->bge_status;
3955         sc->bge_ldata.bge_status_block->bge_status = 0;
3956
3957         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3958             sc->bge_cdata.bge_status_map,
3959             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3960
3961         /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
3962         if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
3963                 sc->bge_link_evt++;
3964
3965         if (cmd == POLL_AND_CHECK_STATUS)
3966                 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3967                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3968                     sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
3969                         bge_link_upd(sc);
3970
3971         sc->rxcycles = count;
3972         rx_npkts = bge_rxeof(sc, rx_prod, 1);
3973         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3974                 BGE_UNLOCK(sc);
3975                 return (rx_npkts);
3976         }
3977         bge_txeof(sc, tx_cons);
3978         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3979                 bge_start_locked(ifp);
3980
3981         BGE_UNLOCK(sc);
3982         return (rx_npkts);
3983 }
3984 #endif /* DEVICE_POLLING */
3985
3986 static int
3987 bge_msi_intr(void *arg)
3988 {
3989         struct bge_softc *sc;
3990
3991         sc = (struct bge_softc *)arg;
3992         /*
3993          * This interrupt is not shared and controller already
3994          * disabled further interrupt.
3995          */
3996         taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
3997         return (FILTER_HANDLED);
3998 }
3999
4000 static void
4001 bge_intr_task(void *arg, int pending)
4002 {
4003         struct bge_softc *sc;
4004         struct ifnet *ifp;
4005         uint32_t status, status_tag;
4006         uint16_t rx_prod, tx_cons;
4007
4008         sc = (struct bge_softc *)arg;
4009         ifp = sc->bge_ifp;
4010
4011         BGE_LOCK(sc);
4012         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
4013                 BGE_UNLOCK(sc);
4014                 return;
4015         }
4016
4017         /* Get updated status block. */
4018         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4019             sc->bge_cdata.bge_status_map,
4020             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4021
4022         /* Save producer/consumer indexess. */
4023         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4024         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4025         status = sc->bge_ldata.bge_status_block->bge_status;
4026         status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
4027         sc->bge_ldata.bge_status_block->bge_status = 0;
4028         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4029             sc->bge_cdata.bge_status_map,
4030             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4031         if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
4032                 status_tag = 0;
4033
4034         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
4035                 bge_link_upd(sc);
4036
4037         /* Let controller work. */
4038         bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
4039
4040         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
4041             sc->bge_rx_saved_considx != rx_prod) {
4042                 /* Check RX return ring producer/consumer. */
4043                 BGE_UNLOCK(sc);
4044                 bge_rxeof(sc, rx_prod, 0);
4045                 BGE_LOCK(sc);
4046         }
4047         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4048                 /* Check TX ring producer/consumer. */
4049                 bge_txeof(sc, tx_cons);
4050                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4051                         bge_start_locked(ifp);
4052         }
4053         BGE_UNLOCK(sc);
4054 }
4055
4056 static void
4057 bge_intr(void *xsc)
4058 {
4059         struct bge_softc *sc;
4060         struct ifnet *ifp;
4061         uint32_t statusword;
4062         uint16_t rx_prod, tx_cons;
4063
4064         sc = xsc;
4065
4066         BGE_LOCK(sc);
4067
4068         ifp = sc->bge_ifp;
4069
4070 #ifdef DEVICE_POLLING
4071         if (ifp->if_capenable & IFCAP_POLLING) {
4072                 BGE_UNLOCK(sc);
4073                 return;
4074         }
4075 #endif
4076
4077         /*
4078          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
4079          * disable interrupts by writing nonzero like we used to, since with
4080          * our current organization this just gives complications and
4081          * pessimizations for re-enabling interrupts.  We used to have races
4082          * instead of the necessary complications.  Disabling interrupts
4083          * would just reduce the chance of a status update while we are
4084          * running (by switching to the interrupt-mode coalescence
4085          * parameters), but this chance is already very low so it is more
4086          * efficient to get another interrupt than prevent it.
4087          *
4088          * We do the ack first to ensure another interrupt if there is a
4089          * status update after the ack.  We don't check for the status
4090          * changing later because it is more efficient to get another
4091          * interrupt than prevent it, not quite as above (not checking is
4092          * a smaller optimization than not toggling the interrupt enable,
4093          * since checking doesn't involve PCI accesses and toggling require
4094          * the status check).  So toggling would probably be a pessimization
4095          * even with MSI.  It would only be needed for using a task queue.
4096          */
4097         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4098
4099         /*
4100          * Do the mandatory PCI flush as well as get the link status.
4101          */
4102         statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
4103
4104         /* Make sure the descriptor ring indexes are coherent. */
4105         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4106             sc->bge_cdata.bge_status_map,
4107             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4108         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4109         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4110         sc->bge_ldata.bge_status_block->bge_status = 0;
4111         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4112             sc->bge_cdata.bge_status_map,
4113             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4114
4115         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4116             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4117             statusword || sc->bge_link_evt)
4118                 bge_link_upd(sc);
4119
4120         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4121                 /* Check RX return ring producer/consumer. */
4122                 bge_rxeof(sc, rx_prod, 1);
4123         }
4124
4125         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4126                 /* Check TX ring producer/consumer. */
4127                 bge_txeof(sc, tx_cons);
4128         }
4129
4130         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
4131             !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4132                 bge_start_locked(ifp);
4133
4134         BGE_UNLOCK(sc);
4135 }
4136
4137 static void
4138 bge_asf_driver_up(struct bge_softc *sc)
4139 {
4140         if (sc->bge_asf_mode & ASF_STACKUP) {
4141                 /* Send ASF heartbeat aprox. every 2s */
4142                 if (sc->bge_asf_count)
4143                         sc->bge_asf_count --;
4144                 else {
4145                         sc->bge_asf_count = 2;
4146                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4147                             BGE_FW_CMD_DRV_ALIVE);
4148                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4149                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
4150                             BGE_FW_HB_TIMEOUT_SEC);
4151                         CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
4152                             CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4153                             BGE_RX_CPU_DRV_EVENT);
4154                 }
4155         }
4156 }
4157
4158 static void
4159 bge_tick(void *xsc)
4160 {
4161         struct bge_softc *sc = xsc;
4162         struct mii_data *mii = NULL;
4163
4164         BGE_LOCK_ASSERT(sc);
4165
4166         /* Synchronize with possible callout reset/stop. */
4167         if (callout_pending(&sc->bge_stat_ch) ||
4168             !callout_active(&sc->bge_stat_ch))
4169                 return;
4170
4171         if (BGE_IS_5705_PLUS(sc))
4172                 bge_stats_update_regs(sc);
4173         else
4174                 bge_stats_update(sc);
4175
4176         if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4177                 mii = device_get_softc(sc->bge_miibus);
4178                 /*
4179                  * Do not touch PHY if we have link up. This could break
4180                  * IPMI/ASF mode or produce extra input errors
4181                  * (extra errors was reported for bcm5701 & bcm5704).
4182                  */
4183                 if (!sc->bge_link)
4184                         mii_tick(mii);
4185         } else {
4186                 /*
4187                  * Since in TBI mode auto-polling can't be used we should poll
4188                  * link status manually. Here we register pending link event
4189                  * and trigger interrupt.
4190                  */
4191 #ifdef DEVICE_POLLING
4192                 /* In polling mode we poll link state in bge_poll(). */
4193                 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
4194 #endif
4195                 {
4196                 sc->bge_link_evt++;
4197                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4198                     sc->bge_flags & BGE_FLAG_5788)
4199                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4200                 else
4201                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4202                 }
4203         }
4204
4205         bge_asf_driver_up(sc);
4206         bge_watchdog(sc);
4207
4208         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4209 }
4210
4211 static void
4212 bge_stats_update_regs(struct bge_softc *sc)
4213 {
4214         struct ifnet *ifp;
4215         struct bge_mac_stats *stats;
4216
4217         ifp = sc->bge_ifp;
4218         stats = &sc->bge_mac_stats;
4219
4220         stats->ifHCOutOctets +=
4221             CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4222         stats->etherStatsCollisions +=
4223             CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4224         stats->outXonSent +=
4225             CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4226         stats->outXoffSent +=
4227             CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4228         stats->dot3StatsInternalMacTransmitErrors +=
4229             CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4230         stats->dot3StatsSingleCollisionFrames +=
4231             CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4232         stats->dot3StatsMultipleCollisionFrames +=
4233             CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4234         stats->dot3StatsDeferredTransmissions +=
4235             CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4236         stats->dot3StatsExcessiveCollisions +=
4237             CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4238         stats->dot3StatsLateCollisions +=
4239             CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4240         stats->ifHCOutUcastPkts +=
4241             CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4242         stats->ifHCOutMulticastPkts +=
4243             CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4244         stats->ifHCOutBroadcastPkts +=
4245             CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4246
4247         stats->ifHCInOctets +=
4248             CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4249         stats->etherStatsFragments +=
4250             CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4251         stats->ifHCInUcastPkts +=
4252             CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4253         stats->ifHCInMulticastPkts +=
4254             CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4255         stats->ifHCInBroadcastPkts +=
4256             CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4257         stats->dot3StatsFCSErrors +=
4258             CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4259         stats->dot3StatsAlignmentErrors +=
4260             CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4261         stats->xonPauseFramesReceived +=
4262             CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4263         stats->xoffPauseFramesReceived +=
4264             CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4265         stats->macControlFramesReceived +=
4266             CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4267         stats->xoffStateEntered +=
4268             CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4269         stats->dot3StatsFramesTooLong +=
4270             CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4271         stats->etherStatsJabbers +=
4272             CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4273         stats->etherStatsUndersizePkts +=
4274             CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4275
4276         stats->FramesDroppedDueToFilters +=
4277             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4278         stats->DmaWriteQueueFull +=
4279             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4280         stats->DmaWriteHighPriQueueFull +=
4281             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4282         stats->NoMoreRxBDs +=
4283             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4284         /*
4285          * XXX
4286          * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS
4287          * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0
4288          * includes number of unwanted multicast frames.  This comes
4289          * from silicon bug and known workaround to get rough(not
4290          * exact) counter is to enable interrupt on MBUF low water
4291          * attention.  This can be accomplished by setting
4292          * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE,
4293          * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and
4294          * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL.
4295          * However that change would generate more interrupts and
4296          * there are still possibilities of losing multiple frames
4297          * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling.
4298          * Given that the workaround still would not get correct
4299          * counter I don't think it's worth to implement it.  So
4300          * ignore reading the counter on controllers that have the
4301          * silicon bug.
4302          */
4303         if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
4304             sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
4305             sc->bge_chipid != BGE_CHIPID_BCM5720_A0)
4306                 stats->InputDiscards +=
4307                     CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4308         stats->InputErrors +=
4309             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4310         stats->RecvThresholdHit +=
4311             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4312
4313         ifp->if_collisions = (u_long)stats->etherStatsCollisions;
4314         ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards +
4315             stats->InputErrors);
4316 }
4317
4318 static void
4319 bge_stats_clear_regs(struct bge_softc *sc)
4320 {
4321
4322         CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4323         CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4324         CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4325         CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4326         CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4327         CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4328         CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4329         CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4330         CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4331         CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4332         CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4333         CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4334         CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4335
4336         CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4337         CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4338         CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4339         CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4340         CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4341         CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4342         CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4343         CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4344         CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4345         CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4346         CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4347         CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4348         CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4349         CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4350
4351         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4352         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4353         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4354         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4355         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4356         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4357         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4358 }
4359
4360 static void
4361 bge_stats_update(struct bge_softc *sc)
4362 {
4363         struct ifnet *ifp;
4364         bus_size_t stats;
4365         uint32_t cnt;   /* current register value */
4366
4367         ifp = sc->bge_ifp;
4368
4369         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
4370
4371 #define READ_STAT(sc, stats, stat) \
4372         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
4373
4374         cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
4375         ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
4376         sc->bge_tx_collisions = cnt;
4377
4378         cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
4379         ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
4380         sc->bge_rx_discards = cnt;
4381
4382         cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
4383         ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
4384         sc->bge_tx_discards = cnt;
4385
4386 #undef  READ_STAT
4387 }
4388
4389 /*
4390  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
4391  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
4392  * but when such padded frames employ the bge IP/TCP checksum offload,
4393  * the hardware checksum assist gives incorrect results (possibly
4394  * from incorporating its own padding into the UDP/TCP checksum; who knows).
4395  * If we pad such runts with zeros, the onboard checksum comes out correct.
4396  */
4397 static __inline int
4398 bge_cksum_pad(struct mbuf *m)
4399 {
4400         int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
4401         struct mbuf *last;
4402
4403         /* If there's only the packet-header and we can pad there, use it. */
4404         if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
4405             M_TRAILINGSPACE(m) >= padlen) {
4406                 last = m;
4407         } else {
4408                 /*
4409                  * Walk packet chain to find last mbuf. We will either
4410                  * pad there, or append a new mbuf and pad it.
4411                  */
4412                 for (last = m; last->m_next != NULL; last = last->m_next);
4413                 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
4414                         /* Allocate new empty mbuf, pad it. Compact later. */
4415                         struct mbuf *n;
4416
4417                         MGET(n, M_DONTWAIT, MT_DATA);
4418                         if (n == NULL)
4419                                 return (ENOBUFS);
4420                         n->m_len = 0;
4421                         last->m_next = n;
4422                         last = n;
4423                 }
4424         }
4425
4426         /* Now zero the pad area, to avoid the bge cksum-assist bug. */
4427         memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
4428         last->m_len += padlen;
4429         m->m_pkthdr.len += padlen;
4430
4431         return (0);
4432 }
4433
4434 static struct mbuf *
4435 bge_check_short_dma(struct mbuf *m)
4436 {
4437         struct mbuf *n;
4438         int found;
4439
4440         /*
4441          * If device receive two back-to-back send BDs with less than
4442          * or equal to 8 total bytes then the device may hang.  The two
4443          * back-to-back send BDs must in the same frame for this failure
4444          * to occur.  Scan mbuf chains and see whether two back-to-back
4445          * send BDs are there. If this is the case, allocate new mbuf
4446          * and copy the frame to workaround the silicon bug.
4447          */
4448         for (n = m, found = 0; n != NULL; n = n->m_next) {
4449                 if (n->m_len < 8) {
4450                         found++;
4451                         if (found > 1)
4452                                 break;
4453                         continue;
4454                 }
4455                 found = 0;
4456         }
4457
4458         if (found > 1) {
4459                 n = m_defrag(m, M_DONTWAIT);
4460                 if (n == NULL)
4461                         m_freem(m);
4462         } else
4463                 n = m;
4464         return (n);
4465 }
4466
4467 static struct mbuf *
4468 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
4469     uint16_t *flags)
4470 {
4471         struct ip *ip;
4472         struct tcphdr *tcp;
4473         struct mbuf *n;
4474         uint16_t hlen;
4475         uint32_t poff;
4476
4477         if (M_WRITABLE(m) == 0) {
4478                 /* Get a writable copy. */
4479                 n = m_dup(m, M_DONTWAIT);
4480                 m_freem(m);
4481                 if (n == NULL)
4482                         return (NULL);
4483                 m = n;
4484         }
4485         m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
4486         if (m == NULL)
4487                 return (NULL);
4488         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
4489         poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
4490         m = m_pullup(m, poff + sizeof(struct tcphdr));
4491         if (m == NULL)
4492                 return (NULL);
4493         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
4494         m = m_pullup(m, poff + (tcp->th_off << 2));
4495         if (m == NULL)
4496                 return (NULL);
4497         /*
4498          * It seems controller doesn't modify IP length and TCP pseudo
4499          * checksum. These checksum computed by upper stack should be 0.
4500          */
4501         *mss = m->m_pkthdr.tso_segsz;
4502         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
4503         ip->ip_sum = 0;
4504         ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
4505         /* Clear pseudo checksum computed by TCP stack. */
4506         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
4507         tcp->th_sum = 0;
4508         /*
4509          * Broadcom controllers uses different descriptor format for
4510          * TSO depending on ASIC revision. Due to TSO-capable firmware
4511          * license issue and lower performance of firmware based TSO
4512          * we only support hardware based TSO.
4513          */
4514         /* Calculate header length, incl. TCP/IP options, in 32 bit units. */
4515         hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
4516         if (sc->bge_flags & BGE_FLAG_TSO3) {
4517                 /*
4518                  * For BCM5717 and newer controllers, hardware based TSO
4519                  * uses the 14 lower bits of the bge_mss field to store the
4520                  * MSS and the upper 2 bits to store the lowest 2 bits of
4521                  * the IP/TCP header length.  The upper 6 bits of the header
4522                  * length are stored in the bge_flags[14:10,4] field.  Jumbo
4523                  * frames are supported.
4524                  */
4525                 *mss |= ((hlen & 0x3) << 14);
4526                 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2);
4527         } else {
4528                 /*
4529                  * For BCM5755 and newer controllers, hardware based TSO uses
4530                  * the lower 11 bits to store the MSS and the upper 5 bits to
4531                  * store the IP/TCP header length. Jumbo frames are not
4532                  * supported.
4533                  */
4534                 *mss |= (hlen << 11);
4535         }
4536         return (m);
4537 }
4538
4539 /*
4540  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
4541  * pointers to descriptors.
4542  */
4543 static int
4544 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
4545 {
4546         bus_dma_segment_t       segs[BGE_NSEG_NEW];
4547         bus_dmamap_t            map;
4548         struct bge_tx_bd        *d;
4549         struct mbuf             *m = *m_head;
4550         uint32_t                idx = *txidx;
4551         uint16_t                csum_flags, mss, vlan_tag;
4552         int                     nsegs, i, error;
4553
4554         csum_flags = 0;
4555         mss = 0;
4556         vlan_tag = 0;
4557         if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
4558             m->m_next != NULL) {
4559                 *m_head = bge_check_short_dma(m);
4560                 if (*m_head == NULL)
4561                         return (ENOBUFS);
4562                 m = *m_head;
4563         }
4564         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
4565                 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
4566                 if (*m_head == NULL)
4567                         return (ENOBUFS);
4568                 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
4569                     BGE_TXBDFLAG_CPU_POST_DMA;
4570         } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
4571                 if (m->m_pkthdr.csum_flags & CSUM_IP)
4572                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
4573                 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
4574                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
4575                         if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
4576                             (error = bge_cksum_pad(m)) != 0) {
4577                                 m_freem(m);
4578                                 *m_head = NULL;
4579                                 return (error);
4580                         }
4581                 }
4582                 if (m->m_flags & M_LASTFRAG)
4583                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
4584                 else if (m->m_flags & M_FRAG)
4585                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
4586         }
4587
4588         if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
4589                 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
4590                     m->m_pkthdr.len > ETHER_MAX_LEN)
4591                         csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME;
4592                 if (sc->bge_forced_collapse > 0 &&
4593                     (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
4594                         /*
4595                          * Forcedly collapse mbuf chains to overcome hardware
4596                          * limitation which only support a single outstanding
4597                          * DMA read operation.
4598                          */
4599                         if (sc->bge_forced_collapse == 1)
4600                                 m = m_defrag(m, M_DONTWAIT);
4601                         else
4602                                 m = m_collapse(m, M_DONTWAIT,
4603                                     sc->bge_forced_collapse);
4604                         if (m == NULL)
4605                                 m = *m_head;
4606                         *m_head = m;
4607                 }
4608         }
4609
4610         map = sc->bge_cdata.bge_tx_dmamap[idx];
4611         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
4612             &nsegs, BUS_DMA_NOWAIT);
4613         if (error == EFBIG) {
4614                 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW);
4615                 if (m == NULL) {
4616                         m_freem(*m_head);
4617                         *m_head = NULL;
4618                         return (ENOBUFS);
4619                 }
4620                 *m_head = m;
4621                 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
4622                     m, segs, &nsegs, BUS_DMA_NOWAIT);
4623                 if (error) {
4624                         m_freem(m);
4625                         *m_head = NULL;
4626                         return (error);
4627                 }
4628         } else if (error != 0)
4629                 return (error);
4630
4631         /* Check if we have enough free send BDs. */
4632         if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
4633                 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
4634                 return (ENOBUFS);
4635         }
4636
4637         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
4638
4639         if (m->m_flags & M_VLANTAG) {
4640                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
4641                 vlan_tag = m->m_pkthdr.ether_vtag;
4642         }
4643         for (i = 0; ; i++) {
4644                 d = &sc->bge_ldata.bge_tx_ring[idx];
4645                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
4646                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
4647                 d->bge_len = segs[i].ds_len;
4648                 d->bge_flags = csum_flags;
4649                 d->bge_vlan_tag = vlan_tag;
4650                 d->bge_mss = mss;
4651                 if (i == nsegs - 1)
4652                         break;
4653                 BGE_INC(idx, BGE_TX_RING_CNT);
4654         }
4655
4656         /* Mark the last segment as end of packet... */
4657         d->bge_flags |= BGE_TXBDFLAG_END;
4658
4659         /*
4660          * Insure that the map for this transmission
4661          * is placed at the array index of the last descriptor
4662          * in this chain.
4663          */
4664         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
4665         sc->bge_cdata.bge_tx_dmamap[idx] = map;
4666         sc->bge_cdata.bge_tx_chain[idx] = m;
4667         sc->bge_txcnt += nsegs;
4668
4669         BGE_INC(idx, BGE_TX_RING_CNT);
4670         *txidx = idx;
4671
4672         return (0);
4673 }
4674
4675 /*
4676  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4677  * to the mbuf data regions directly in the transmit descriptors.
4678  */
4679 static void
4680 bge_start_locked(struct ifnet *ifp)
4681 {
4682         struct bge_softc *sc;
4683         struct mbuf *m_head;
4684         uint32_t prodidx;
4685         int count;
4686
4687         sc = ifp->if_softc;
4688         BGE_LOCK_ASSERT(sc);
4689
4690         if (!sc->bge_link ||
4691             (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4692             IFF_DRV_RUNNING)
4693                 return;
4694
4695         prodidx = sc->bge_tx_prodidx;
4696
4697         for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
4698                 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
4699                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4700                         break;
4701                 }
4702                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
4703                 if (m_head == NULL)
4704                         break;
4705
4706                 /*
4707                  * XXX
4708                  * The code inside the if() block is never reached since we
4709                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
4710                  * requests to checksum TCP/UDP in a fragmented packet.
4711                  *
4712                  * XXX
4713                  * safety overkill.  If this is a fragmented packet chain
4714                  * with delayed TCP/UDP checksums, then only encapsulate
4715                  * it if we have enough descriptors to handle the entire
4716                  * chain at once.
4717                  * (paranoia -- may not actually be needed)
4718                  */
4719                 if (m_head->m_flags & M_FIRSTFRAG &&
4720                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
4721                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
4722                             m_head->m_pkthdr.csum_data + 16) {
4723                                 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4724                                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4725                                 break;
4726                         }
4727                 }
4728
4729                 /*
4730                  * Pack the data into the transmit ring. If we
4731                  * don't have room, set the OACTIVE flag and wait
4732                  * for the NIC to drain the ring.
4733                  */
4734                 if (bge_encap(sc, &m_head, &prodidx)) {
4735                         if (m_head == NULL)
4736                                 break;
4737                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4738                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4739                         break;
4740                 }
4741                 ++count;
4742
4743                 /*
4744                  * If there's a BPF listener, bounce a copy of this frame
4745                  * to him.
4746                  */
4747 #ifdef ETHER_BPF_MTAP
4748                 ETHER_BPF_MTAP(ifp, m_head);
4749 #else
4750                 BPF_MTAP(ifp, m_head);
4751 #endif
4752         }
4753
4754         if (count > 0) {
4755                 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4756                     sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
4757                 /* Transmit. */
4758                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4759                 /* 5700 b2 errata */
4760                 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
4761                         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4762
4763                 sc->bge_tx_prodidx = prodidx;
4764
4765                 /*
4766                  * Set a timeout in case the chip goes out to lunch.
4767                  */
4768                 sc->bge_timer = 5;
4769         }
4770 }
4771
4772 /*
4773  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4774  * to the mbuf data regions directly in the transmit descriptors.
4775  */
4776 static void
4777 bge_start(struct ifnet *ifp)
4778 {
4779         struct bge_softc *sc;
4780
4781         sc = ifp->if_softc;
4782         BGE_LOCK(sc);
4783         bge_start_locked(ifp);
4784         BGE_UNLOCK(sc);
4785 }
4786
4787 static void
4788 bge_init_locked(struct bge_softc *sc)
4789 {
4790         struct ifnet *ifp;
4791         uint16_t *m;
4792         uint32_t mode;
4793
4794         BGE_LOCK_ASSERT(sc);
4795
4796         ifp = sc->bge_ifp;
4797
4798         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4799                 return;
4800
4801         /* Cancel pending I/O and flush buffers. */
4802         bge_stop(sc);
4803
4804         bge_stop_fw(sc);
4805         bge_sig_pre_reset(sc, BGE_RESET_START);
4806         bge_reset(sc);
4807         bge_sig_legacy(sc, BGE_RESET_START);
4808         bge_sig_post_reset(sc, BGE_RESET_START);
4809
4810         bge_chipinit(sc);
4811
4812         /*
4813          * Init the various state machines, ring
4814          * control blocks and firmware.
4815          */
4816         if (bge_blockinit(sc)) {
4817                 device_printf(sc->bge_dev, "initialization failure\n");
4818                 return;
4819         }
4820
4821         ifp = sc->bge_ifp;
4822
4823         /* Specify MTU. */
4824         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
4825             ETHER_HDR_LEN + ETHER_CRC_LEN +
4826             (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
4827
4828         /* Load our MAC address. */
4829         m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
4830         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
4831         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
4832
4833         /* Program promiscuous mode. */
4834         bge_setpromisc(sc);
4835
4836         /* Program multicast filter. */
4837         bge_setmulti(sc);
4838
4839         /* Program VLAN tag stripping. */
4840         bge_setvlan(sc);
4841
4842         /* Override UDP checksum offloading. */
4843         if (sc->bge_forced_udpcsum == 0)
4844                 sc->bge_csum_features &= ~CSUM_UDP;
4845         else
4846                 sc->bge_csum_features |= CSUM_UDP;
4847         if (ifp->if_capabilities & IFCAP_TXCSUM &&
4848             ifp->if_capenable & IFCAP_TXCSUM) {
4849                 ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP);
4850                 ifp->if_hwassist |= sc->bge_csum_features;
4851         }
4852
4853         /* Init RX ring. */
4854         if (bge_init_rx_ring_std(sc) != 0) {
4855                 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
4856                 bge_stop(sc);
4857                 return;
4858         }
4859
4860         /*
4861          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
4862          * memory to insure that the chip has in fact read the first
4863          * entry of the ring.
4864          */
4865         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
4866                 uint32_t                v, i;
4867                 for (i = 0; i < 10; i++) {
4868                         DELAY(20);
4869                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
4870                         if (v == (MCLBYTES - ETHER_ALIGN))
4871                                 break;
4872                 }
4873                 if (i == 10)
4874                         device_printf (sc->bge_dev,
4875                             "5705 A0 chip failed to load RX ring\n");
4876         }
4877
4878         /* Init jumbo RX ring. */
4879         if (BGE_IS_JUMBO_CAPABLE(sc) &&
4880             ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
4881             (MCLBYTES - ETHER_ALIGN)) {
4882                 if (bge_init_rx_ring_jumbo(sc) != 0) {
4883                         device_printf(sc->bge_dev,
4884                             "no memory for jumbo Rx buffers.\n");
4885                         bge_stop(sc);
4886                         return;
4887                 }
4888         }
4889
4890         /* Init our RX return ring index. */
4891         sc->bge_rx_saved_considx = 0;
4892
4893         /* Init our RX/TX stat counters. */
4894         sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
4895
4896         /* Init TX ring. */
4897         bge_init_tx_ring(sc);
4898
4899         /* Enable TX MAC state machine lockup fix. */
4900         mode = CSR_READ_4(sc, BGE_TX_MODE);
4901         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
4902                 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
4903         if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
4904                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
4905                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
4906                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
4907         }
4908         /* Turn on transmitter. */
4909         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
4910
4911         /* Turn on receiver. */
4912         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4913
4914         /*
4915          * Set the number of good frames to receive after RX MBUF
4916          * Low Watermark has been reached. After the RX MAC receives
4917          * this number of frames, it will drop subsequent incoming
4918          * frames until the MBUF High Watermark is reached.
4919          */
4920         if (sc->bge_asicrev == BGE_ASICREV_BCM57765)
4921                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
4922         else
4923                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
4924
4925         /* Clear MAC statistics. */
4926         if (BGE_IS_5705_PLUS(sc))
4927                 bge_stats_clear_regs(sc);
4928
4929         /* Tell firmware we're alive. */
4930         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4931
4932 #ifdef DEVICE_POLLING
4933         /* Disable interrupts if we are polling. */
4934         if (ifp->if_capenable & IFCAP_POLLING) {
4935                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4936                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4937                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4938         } else
4939 #endif
4940
4941         /* Enable host interrupts. */
4942         {
4943         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
4944         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4945         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4946         }
4947
4948         bge_ifmedia_upd_locked(ifp);
4949
4950         ifp->if_drv_flags |= IFF_DRV_RUNNING;
4951         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4952
4953         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4954 }
4955
4956 static void
4957 bge_init(void *xsc)
4958 {
4959         struct bge_softc *sc = xsc;
4960
4961         BGE_LOCK(sc);
4962         bge_init_locked(sc);
4963         BGE_UNLOCK(sc);
4964 }
4965
4966 /*
4967  * Set media options.
4968  */
4969 static int
4970 bge_ifmedia_upd(struct ifnet *ifp)
4971 {
4972         struct bge_softc *sc = ifp->if_softc;
4973         int res;
4974
4975         BGE_LOCK(sc);
4976         res = bge_ifmedia_upd_locked(ifp);
4977         BGE_UNLOCK(sc);
4978
4979         return (res);
4980 }
4981
4982 static int
4983 bge_ifmedia_upd_locked(struct ifnet *ifp)
4984 {
4985         struct bge_softc *sc = ifp->if_softc;
4986         struct mii_data *mii;
4987         struct mii_softc *miisc;
4988         struct ifmedia *ifm;
4989
4990         BGE_LOCK_ASSERT(sc);
4991
4992         ifm = &sc->bge_ifmedia;
4993
4994         /* If this is a 1000baseX NIC, enable the TBI port. */
4995         if (sc->bge_flags & BGE_FLAG_TBI) {
4996                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
4997                         return (EINVAL);
4998                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
4999                 case IFM_AUTO:
5000                         /*
5001                          * The BCM5704 ASIC appears to have a special
5002                          * mechanism for programming the autoneg
5003                          * advertisement registers in TBI mode.
5004                          */
5005                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
5006                                 uint32_t sgdig;
5007                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5008                                 if (sgdig & BGE_SGDIGSTS_DONE) {
5009                                         CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5010                                         sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5011                                         sgdig |= BGE_SGDIGCFG_AUTO |
5012                                             BGE_SGDIGCFG_PAUSE_CAP |
5013                                             BGE_SGDIGCFG_ASYM_PAUSE;
5014                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG,
5015                                             sgdig | BGE_SGDIGCFG_SEND);
5016                                         DELAY(5);
5017                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
5018                                 }
5019                         }
5020                         break;
5021                 case IFM_1000_SX:
5022                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
5023                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
5024                                     BGE_MACMODE_HALF_DUPLEX);
5025                         } else {
5026                                 BGE_SETBIT(sc, BGE_MAC_MODE,
5027                                     BGE_MACMODE_HALF_DUPLEX);
5028                         }
5029                         break;
5030                 default:
5031                         return (EINVAL);
5032                 }
5033                 return (0);
5034         }
5035
5036         sc->bge_link_evt++;
5037         mii = device_get_softc(sc->bge_miibus);
5038         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
5039                 PHY_RESET(miisc);
5040         mii_mediachg(mii);
5041
5042         /*
5043          * Force an interrupt so that we will call bge_link_upd
5044          * if needed and clear any pending link state attention.
5045          * Without this we are not getting any further interrupts
5046          * for link state changes and thus will not UP the link and
5047          * not be able to send in bge_start_locked. The only
5048          * way to get things working was to receive a packet and
5049          * get an RX intr.
5050          * bge_tick should help for fiber cards and we might not
5051          * need to do this here if BGE_FLAG_TBI is set but as
5052          * we poll for fiber anyway it should not harm.
5053          */
5054         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
5055             sc->bge_flags & BGE_FLAG_5788)
5056                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
5057         else
5058                 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
5059
5060         return (0);
5061 }
5062
5063 /*
5064  * Report current media status.
5065  */
5066 static void
5067 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
5068 {
5069         struct bge_softc *sc = ifp->if_softc;
5070         struct mii_data *mii;
5071
5072         BGE_LOCK(sc);
5073
5074         if (sc->bge_flags & BGE_FLAG_TBI) {
5075                 ifmr->ifm_status = IFM_AVALID;
5076                 ifmr->ifm_active = IFM_ETHER;
5077                 if (CSR_READ_4(sc, BGE_MAC_STS) &
5078                     BGE_MACSTAT_TBI_PCS_SYNCHED)
5079                         ifmr->ifm_status |= IFM_ACTIVE;
5080                 else {
5081                         ifmr->ifm_active |= IFM_NONE;
5082                         BGE_UNLOCK(sc);
5083                         return;
5084                 }
5085                 ifmr->ifm_active |= IFM_1000_SX;
5086                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5087                         ifmr->ifm_active |= IFM_HDX;
5088                 else
5089                         ifmr->ifm_active |= IFM_FDX;
5090                 BGE_UNLOCK(sc);
5091                 return;
5092         }
5093
5094         mii = device_get_softc(sc->bge_miibus);
5095         mii_pollstat(mii);
5096         ifmr->ifm_active = mii->mii_media_active;
5097         ifmr->ifm_status = mii->mii_media_status;
5098
5099         BGE_UNLOCK(sc);
5100 }
5101
5102 static int
5103 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
5104 {
5105         struct bge_softc *sc = ifp->if_softc;
5106         struct ifreq *ifr = (struct ifreq *) data;
5107         struct mii_data *mii;
5108         int flags, mask, error = 0;
5109
5110         switch (command) {
5111         case SIOCSIFMTU:
5112                 if (BGE_IS_JUMBO_CAPABLE(sc) ||
5113                     (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
5114                         if (ifr->ifr_mtu < ETHERMIN ||
5115                             ifr->ifr_mtu > BGE_JUMBO_MTU) {
5116                                 error = EINVAL;
5117                                 break;
5118                         }
5119                 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) {
5120                         error = EINVAL;
5121                         break;
5122                 }
5123                 BGE_LOCK(sc);
5124                 if (ifp->if_mtu != ifr->ifr_mtu) {
5125                         ifp->if_mtu = ifr->ifr_mtu;
5126                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5127                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5128                                 bge_init_locked(sc);
5129                         }
5130                 }
5131                 BGE_UNLOCK(sc);
5132                 break;
5133         case SIOCSIFFLAGS:
5134                 BGE_LOCK(sc);
5135                 if (ifp->if_flags & IFF_UP) {
5136                         /*
5137                          * If only the state of the PROMISC flag changed,
5138                          * then just use the 'set promisc mode' command
5139                          * instead of reinitializing the entire NIC. Doing
5140                          * a full re-init means reloading the firmware and
5141                          * waiting for it to start up, which may take a
5142                          * second or two.  Similarly for ALLMULTI.
5143                          */
5144                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5145                                 flags = ifp->if_flags ^ sc->bge_if_flags;
5146                                 if (flags & IFF_PROMISC)
5147                                         bge_setpromisc(sc);
5148                                 if (flags & IFF_ALLMULTI)
5149                                         bge_setmulti(sc);
5150                         } else
5151                                 bge_init_locked(sc);
5152                 } else {
5153                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5154                                 bge_stop(sc);
5155                         }
5156                 }
5157                 sc->bge_if_flags = ifp->if_flags;
5158                 BGE_UNLOCK(sc);
5159                 error = 0;
5160                 break;
5161         case SIOCADDMULTI:
5162         case SIOCDELMULTI:
5163                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5164                         BGE_LOCK(sc);
5165                         bge_setmulti(sc);
5166                         BGE_UNLOCK(sc);
5167                         error = 0;
5168                 }
5169                 break;
5170         case SIOCSIFMEDIA:
5171         case SIOCGIFMEDIA:
5172                 if (sc->bge_flags & BGE_FLAG_TBI) {
5173                         error = ifmedia_ioctl(ifp, ifr,
5174                             &sc->bge_ifmedia, command);
5175                 } else {
5176                         mii = device_get_softc(sc->bge_miibus);
5177                         error = ifmedia_ioctl(ifp, ifr,
5178                             &mii->mii_media, command);
5179                 }
5180                 break;
5181         case SIOCSIFCAP:
5182                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5183 #ifdef DEVICE_POLLING
5184                 if (mask & IFCAP_POLLING) {
5185                         if (ifr->ifr_reqcap & IFCAP_POLLING) {
5186                                 error = ether_poll_register(bge_poll, ifp);
5187                                 if (error)
5188                                         return (error);
5189                                 BGE_LOCK(sc);
5190                                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5191                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
5192                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5193                                 ifp->if_capenable |= IFCAP_POLLING;
5194                                 BGE_UNLOCK(sc);
5195                         } else {
5196                                 error = ether_poll_deregister(ifp);
5197                                 /* Enable interrupt even in error case */
5198                                 BGE_LOCK(sc);
5199                                 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
5200                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
5201                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5202                                 ifp->if_capenable &= ~IFCAP_POLLING;
5203                                 BGE_UNLOCK(sc);
5204                         }
5205                 }
5206 #endif
5207                 if ((mask & IFCAP_TXCSUM) != 0 &&
5208                     (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
5209                         ifp->if_capenable ^= IFCAP_TXCSUM;
5210                         if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
5211                                 ifp->if_hwassist |= sc->bge_csum_features;
5212                         else
5213                                 ifp->if_hwassist &= ~sc->bge_csum_features;
5214                 }
5215
5216                 if ((mask & IFCAP_RXCSUM) != 0 &&
5217                     (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
5218                         ifp->if_capenable ^= IFCAP_RXCSUM;
5219
5220                 if ((mask & IFCAP_TSO4) != 0 &&
5221                     (ifp->if_capabilities & IFCAP_TSO4) != 0) {
5222                         ifp->if_capenable ^= IFCAP_TSO4;
5223                         if ((ifp->if_capenable & IFCAP_TSO4) != 0)
5224                                 ifp->if_hwassist |= CSUM_TSO;
5225                         else
5226                                 ifp->if_hwassist &= ~CSUM_TSO;
5227                 }
5228
5229                 if (mask & IFCAP_VLAN_MTU) {
5230                         ifp->if_capenable ^= IFCAP_VLAN_MTU;
5231                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5232                         bge_init(sc);
5233                 }
5234
5235                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
5236                     (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
5237                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
5238                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
5239                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
5240                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
5241                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
5242                                 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
5243                         BGE_LOCK(sc);
5244                         bge_setvlan(sc);
5245                         BGE_UNLOCK(sc);
5246                 }
5247 #ifdef VLAN_CAPABILITIES
5248                 VLAN_CAPABILITIES(ifp);
5249 #endif
5250                 break;
5251         default:
5252                 error = ether_ioctl(ifp, command, data);
5253                 break;
5254         }
5255
5256         return (error);
5257 }
5258
5259 static void
5260 bge_watchdog(struct bge_softc *sc)
5261 {
5262         struct ifnet *ifp;
5263
5264         BGE_LOCK_ASSERT(sc);
5265
5266         if (sc->bge_timer == 0 || --sc->bge_timer)
5267                 return;
5268
5269         ifp = sc->bge_ifp;
5270
5271         if_printf(ifp, "watchdog timeout -- resetting\n");
5272
5273         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5274         bge_init_locked(sc);
5275
5276         ifp->if_oerrors++;
5277 }
5278
5279 static void
5280 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
5281 {
5282         int i;
5283
5284         BGE_CLRBIT(sc, reg, bit);
5285
5286         for (i = 0; i < BGE_TIMEOUT; i++) {
5287                 if ((CSR_READ_4(sc, reg) & bit) == 0)
5288                         return;
5289                 DELAY(100);
5290         }
5291 }
5292
5293 /*
5294  * Stop the adapter and free any mbufs allocated to the
5295  * RX and TX lists.
5296  */
5297 static void
5298 bge_stop(struct bge_softc *sc)
5299 {
5300         struct ifnet *ifp;
5301
5302         BGE_LOCK_ASSERT(sc);
5303
5304         ifp = sc->bge_ifp;
5305
5306         callout_stop(&sc->bge_stat_ch);
5307
5308         /* Disable host interrupts. */
5309         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5310         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5311
5312         /*
5313          * Tell firmware we're shutting down.
5314          */
5315         bge_stop_fw(sc);
5316         bge_sig_pre_reset(sc, BGE_RESET_STOP);
5317
5318         /*
5319          * Disable all of the receiver blocks.
5320          */
5321         bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
5322         bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
5323         bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
5324         if (BGE_IS_5700_FAMILY(sc))
5325                 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
5326         bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
5327         bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
5328         bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
5329
5330         /*
5331          * Disable all of the transmit blocks.
5332          */
5333         bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
5334         bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
5335         bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
5336         bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
5337         bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
5338         if (BGE_IS_5700_FAMILY(sc))
5339                 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
5340         bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
5341
5342         /*
5343          * Shut down all of the memory managers and related
5344          * state machines.
5345          */
5346         bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
5347         bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
5348         if (BGE_IS_5700_FAMILY(sc))
5349                 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
5350
5351         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
5352         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
5353         if (!(BGE_IS_5705_PLUS(sc))) {
5354                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
5355                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
5356         }
5357         /* Update MAC statistics. */
5358         if (BGE_IS_5705_PLUS(sc))
5359                 bge_stats_update_regs(sc);
5360
5361         bge_reset(sc);
5362         bge_sig_legacy(sc, BGE_RESET_STOP);
5363         bge_sig_post_reset(sc, BGE_RESET_STOP);
5364
5365         /*
5366          * Keep the ASF firmware running if up.
5367          */
5368         if (sc->bge_asf_mode & ASF_STACKUP)
5369                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5370         else
5371                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5372
5373         /* Free the RX lists. */
5374         bge_free_rx_ring_std(sc);
5375
5376         /* Free jumbo RX list. */
5377         if (BGE_IS_JUMBO_CAPABLE(sc))
5378                 bge_free_rx_ring_jumbo(sc);
5379
5380         /* Free TX buffers. */
5381         bge_free_tx_ring(sc);
5382
5383         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
5384
5385         /* Clear MAC's link state (PHY may still have link UP). */
5386         if (bootverbose && sc->bge_link)
5387                 if_printf(sc->bge_ifp, "link DOWN\n");
5388         sc->bge_link = 0;
5389
5390         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
5391 }
5392
5393 /*
5394  * Stop all chip I/O so that the kernel's probe routines don't
5395  * get confused by errant DMAs when rebooting.
5396  */
5397 static int
5398 bge_shutdown(device_t dev)
5399 {
5400         struct bge_softc *sc;
5401
5402         sc = device_get_softc(dev);
5403         BGE_LOCK(sc);
5404         bge_stop(sc);
5405         bge_reset(sc);
5406         BGE_UNLOCK(sc);
5407
5408         return (0);
5409 }
5410
5411 static int
5412 bge_suspend(device_t dev)
5413 {
5414         struct bge_softc *sc;
5415
5416         sc = device_get_softc(dev);
5417         BGE_LOCK(sc);
5418         bge_stop(sc);
5419         BGE_UNLOCK(sc);
5420
5421         return (0);
5422 }
5423
5424 static int
5425 bge_resume(device_t dev)
5426 {
5427         struct bge_softc *sc;
5428         struct ifnet *ifp;
5429
5430         sc = device_get_softc(dev);
5431         BGE_LOCK(sc);
5432         ifp = sc->bge_ifp;
5433         if (ifp->if_flags & IFF_UP) {
5434                 bge_init_locked(sc);
5435                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
5436                         bge_start_locked(ifp);
5437         }
5438         BGE_UNLOCK(sc);
5439
5440         return (0);
5441 }
5442
5443 static void
5444 bge_link_upd(struct bge_softc *sc)
5445 {
5446         struct mii_data *mii;
5447         uint32_t link, status;
5448
5449         BGE_LOCK_ASSERT(sc);
5450
5451         /* Clear 'pending link event' flag. */
5452         sc->bge_link_evt = 0;
5453
5454         /*
5455          * Process link state changes.
5456          * Grrr. The link status word in the status block does
5457          * not work correctly on the BCM5700 rev AX and BX chips,
5458          * according to all available information. Hence, we have
5459          * to enable MII interrupts in order to properly obtain
5460          * async link changes. Unfortunately, this also means that
5461          * we have to read the MAC status register to detect link
5462          * changes, thereby adding an additional register access to
5463          * the interrupt handler.
5464          *
5465          * XXX: perhaps link state detection procedure used for
5466          * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
5467          */
5468
5469         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
5470             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
5471                 status = CSR_READ_4(sc, BGE_MAC_STS);
5472                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
5473                         mii = device_get_softc(sc->bge_miibus);
5474                         mii_pollstat(mii);
5475                         if (!sc->bge_link &&
5476                             mii->mii_media_status & IFM_ACTIVE &&
5477                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5478                                 sc->bge_link++;
5479                                 if (bootverbose)
5480                                         if_printf(sc->bge_ifp, "link UP\n");
5481                         } else if (sc->bge_link &&
5482                             (!(mii->mii_media_status & IFM_ACTIVE) ||
5483                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
5484                                 sc->bge_link = 0;
5485                                 if (bootverbose)
5486                                         if_printf(sc->bge_ifp, "link DOWN\n");
5487                         }
5488
5489                         /* Clear the interrupt. */
5490                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
5491                             BGE_EVTENB_MI_INTERRUPT);
5492                         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
5493                         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
5494                             BRGPHY_INTRS);
5495                 }
5496                 return;
5497         }
5498
5499         if (sc->bge_flags & BGE_FLAG_TBI) {
5500                 status = CSR_READ_4(sc, BGE_MAC_STS);
5501                 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
5502                         if (!sc->bge_link) {
5503                                 sc->bge_link++;
5504                                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
5505                                         BGE_CLRBIT(sc, BGE_MAC_MODE,
5506                                             BGE_MACMODE_TBI_SEND_CFGS);
5507                                 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
5508                                 if (bootverbose)
5509                                         if_printf(sc->bge_ifp, "link UP\n");
5510                                 if_link_state_change(sc->bge_ifp,
5511                                     LINK_STATE_UP);
5512                         }
5513                 } else if (sc->bge_link) {
5514                         sc->bge_link = 0;
5515                         if (bootverbose)
5516                                 if_printf(sc->bge_ifp, "link DOWN\n");
5517                         if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
5518                 }
5519         } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
5520                 /*
5521                  * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
5522                  * in status word always set. Workaround this bug by reading
5523                  * PHY link status directly.
5524                  */
5525                 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
5526
5527                 if (link != sc->bge_link ||
5528                     sc->bge_asicrev == BGE_ASICREV_BCM5700) {
5529                         mii = device_get_softc(sc->bge_miibus);
5530                         mii_pollstat(mii);
5531                         if (!sc->bge_link &&
5532                             mii->mii_media_status & IFM_ACTIVE &&
5533                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5534                                 sc->bge_link++;
5535                                 if (bootverbose)
5536                                         if_printf(sc->bge_ifp, "link UP\n");
5537                         } else if (sc->bge_link &&
5538                             (!(mii->mii_media_status & IFM_ACTIVE) ||
5539                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
5540                                 sc->bge_link = 0;
5541                                 if (bootverbose)
5542                                         if_printf(sc->bge_ifp, "link DOWN\n");
5543                         }
5544                 }
5545         } else {
5546                 /*
5547                  * For controllers that call mii_tick, we have to poll
5548                  * link status.
5549                  */
5550                 mii = device_get_softc(sc->bge_miibus);
5551                 mii_pollstat(mii);
5552                 bge_miibus_statchg(sc->bge_dev);
5553         }
5554
5555         /* Clear the attention. */
5556         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
5557             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
5558             BGE_MACSTAT_LINK_CHANGED);
5559 }
5560
5561 static void
5562 bge_add_sysctls(struct bge_softc *sc)
5563 {
5564         struct sysctl_ctx_list *ctx;
5565         struct sysctl_oid_list *children;
5566         char tn[32];
5567         int unit;
5568
5569         ctx = device_get_sysctl_ctx(sc->bge_dev);
5570         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
5571
5572 #ifdef BGE_REGISTER_DEBUG
5573         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
5574             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
5575             "Debug Information");
5576
5577         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
5578             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
5579             "Register Read");
5580
5581         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
5582             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
5583             "Memory Read");
5584
5585 #endif
5586
5587         unit = device_get_unit(sc->bge_dev);
5588         /*
5589          * A common design characteristic for many Broadcom client controllers
5590          * is that they only support a single outstanding DMA read operation
5591          * on the PCIe bus. This means that it will take twice as long to fetch
5592          * a TX frame that is split into header and payload buffers as it does
5593          * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
5594          * these controllers, coalescing buffers to reduce the number of memory
5595          * reads is effective way to get maximum performance(about 940Mbps).
5596          * Without collapsing TX buffers the maximum TCP bulk transfer
5597          * performance is about 850Mbps. However forcing coalescing mbufs
5598          * consumes a lot of CPU cycles, so leave it off by default.
5599          */
5600         sc->bge_forced_collapse = 0;
5601         snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit);
5602         TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse);
5603         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
5604             CTLFLAG_RW, &sc->bge_forced_collapse, 0,
5605             "Number of fragmented TX buffers of a frame allowed before "
5606             "forced collapsing");
5607
5608         sc->bge_msi = 1;
5609         snprintf(tn, sizeof(tn), "dev.bge.%d.msi", unit);
5610         TUNABLE_INT_FETCH(tn, &sc->bge_msi);
5611         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi",
5612             CTLFLAG_RD, &sc->bge_msi, 0, "Enable MSI");
5613
5614         /*
5615          * It seems all Broadcom controllers have a bug that can generate UDP
5616          * datagrams with checksum value 0 when TX UDP checksum offloading is
5617          * enabled.  Generating UDP checksum value 0 is RFC 768 violation.
5618          * Even though the probability of generating such UDP datagrams is
5619          * low, I don't want to see FreeBSD boxes to inject such datagrams
5620          * into network so disable UDP checksum offloading by default.  Users
5621          * still override this behavior by setting a sysctl variable,
5622          * dev.bge.0.forced_udpcsum.
5623          */
5624         sc->bge_forced_udpcsum = 0;
5625         snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit);
5626         TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum);
5627         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum",
5628             CTLFLAG_RW, &sc->bge_forced_udpcsum, 0,
5629             "Enable UDP checksum offloading even if controller can "
5630             "generate UDP checksum value 0");
5631
5632         if (BGE_IS_5705_PLUS(sc))
5633                 bge_add_sysctl_stats_regs(sc, ctx, children);
5634         else
5635                 bge_add_sysctl_stats(sc, ctx, children);
5636 }
5637
5638 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
5639         SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
5640             sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
5641             desc)
5642
5643 static void
5644 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
5645     struct sysctl_oid_list *parent)
5646 {
5647         struct sysctl_oid *tree;
5648         struct sysctl_oid_list *children, *schildren;
5649
5650         tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
5651             NULL, "BGE Statistics");
5652         schildren = children = SYSCTL_CHILDREN(tree);
5653         BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
5654             children, COSFramesDroppedDueToFilters,
5655             "FramesDroppedDueToFilters");
5656         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
5657             children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
5658         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
5659             children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
5660         BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
5661             children, nicNoMoreRxBDs, "NoMoreRxBDs");
5662         BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
5663             children, ifInDiscards, "InputDiscards");
5664         BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
5665             children, ifInErrors, "InputErrors");
5666         BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
5667             children, nicRecvThresholdHit, "RecvThresholdHit");
5668         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
5669             children, nicDmaReadQueueFull, "DmaReadQueueFull");
5670         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
5671             children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
5672         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
5673             children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
5674         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
5675             children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
5676         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
5677             children, nicRingStatusUpdate, "RingStatusUpdate");
5678         BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
5679             children, nicInterrupts, "Interrupts");
5680         BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
5681             children, nicAvoidedInterrupts, "AvoidedInterrupts");
5682         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
5683             children, nicSendThresholdHit, "SendThresholdHit");
5684
5685         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
5686             NULL, "BGE RX Statistics");
5687         children = SYSCTL_CHILDREN(tree);
5688         BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
5689             children, rxstats.ifHCInOctets, "ifHCInOctets");
5690         BGE_SYSCTL_STAT(sc, ctx, "Fragments",
5691             children, rxstats.etherStatsFragments, "Fragments");
5692         BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
5693             children, rxstats.ifHCInUcastPkts, "UnicastPkts");
5694         BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
5695             children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
5696         BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
5697             children, rxstats.dot3StatsFCSErrors, "FCSErrors");
5698         BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
5699             children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
5700         BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
5701             children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
5702         BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
5703             children, rxstats.xoffPauseFramesReceived,
5704             "xoffPauseFramesReceived");
5705         BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
5706             children, rxstats.macControlFramesReceived,
5707             "ControlFramesReceived");
5708         BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
5709             children, rxstats.xoffStateEntered, "xoffStateEntered");
5710         BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
5711             children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
5712         BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
5713             children, rxstats.etherStatsJabbers, "Jabbers");
5714         BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
5715             children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
5716         BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
5717             children, rxstats.inRangeLengthError, "inRangeLengthError");
5718         BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
5719             children, rxstats.outRangeLengthError, "outRangeLengthError");
5720
5721         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
5722             NULL, "BGE TX Statistics");
5723         children = SYSCTL_CHILDREN(tree);
5724         BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
5725             children, txstats.ifHCOutOctets, "ifHCOutOctets");
5726         BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
5727             children, txstats.etherStatsCollisions, "Collisions");
5728         BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
5729             children, txstats.outXonSent, "XonSent");
5730         BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
5731             children, txstats.outXoffSent, "XoffSent");
5732         BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
5733             children, txstats.flowControlDone, "flowControlDone");
5734         BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
5735             children, txstats.dot3StatsInternalMacTransmitErrors,
5736             "InternalMacTransmitErrors");
5737         BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
5738             children, txstats.dot3StatsSingleCollisionFrames,
5739             "SingleCollisionFrames");
5740         BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
5741             children, txstats.dot3StatsMultipleCollisionFrames,
5742             "MultipleCollisionFrames");
5743         BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
5744             children, txstats.dot3StatsDeferredTransmissions,
5745             "DeferredTransmissions");
5746         BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
5747             children, txstats.dot3StatsExcessiveCollisions,
5748             "ExcessiveCollisions");
5749         BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
5750             children, txstats.dot3StatsLateCollisions,
5751             "LateCollisions");
5752         BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
5753             children, txstats.ifHCOutUcastPkts, "UnicastPkts");
5754         BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
5755             children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
5756         BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
5757             children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
5758         BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
5759             children, txstats.dot3StatsCarrierSenseErrors,
5760             "CarrierSenseErrors");
5761         BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
5762             children, txstats.ifOutDiscards, "Discards");
5763         BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
5764             children, txstats.ifOutErrors, "Errors");
5765 }
5766
5767 #undef BGE_SYSCTL_STAT
5768
5769 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d)    \
5770             SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
5771
5772 static void
5773 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
5774     struct sysctl_oid_list *parent)
5775 {
5776         struct sysctl_oid *tree;
5777         struct sysctl_oid_list *child, *schild;
5778         struct bge_mac_stats *stats;
5779
5780         stats = &sc->bge_mac_stats;
5781         tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
5782             NULL, "BGE Statistics");
5783         schild = child = SYSCTL_CHILDREN(tree);
5784         BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters",
5785             &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters");
5786         BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull",
5787             &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full");
5788         BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull",
5789             &stats->DmaWriteHighPriQueueFull,
5790             "NIC DMA Write High Priority Queue Full");
5791         BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs",
5792             &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors");
5793         BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards",
5794             &stats->InputDiscards, "Discarded Input Frames");
5795         BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors",
5796             &stats->InputErrors, "Input Errors");
5797         BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit",
5798             &stats->RecvThresholdHit, "NIC Recv Threshold Hit");
5799
5800         tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD,
5801             NULL, "BGE RX Statistics");
5802         child = SYSCTL_CHILDREN(tree);
5803         BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets",
5804             &stats->ifHCInOctets, "Inbound Octets");
5805         BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments",
5806             &stats->etherStatsFragments, "Fragments");
5807         BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
5808             &stats->ifHCInUcastPkts, "Inbound Unicast Packets");
5809         BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
5810             &stats->ifHCInMulticastPkts, "Inbound Multicast Packets");
5811         BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
5812             &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets");
5813         BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors",
5814             &stats->dot3StatsFCSErrors, "FCS Errors");
5815         BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors",
5816             &stats->dot3StatsAlignmentErrors, "Alignment Errors");
5817         BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived",
5818             &stats->xonPauseFramesReceived, "XON Pause Frames Received");
5819         BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived",
5820             &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received");
5821         BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived",
5822             &stats->macControlFramesReceived, "MAC Control Frames Received");
5823         BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered",
5824             &stats->xoffStateEntered, "XOFF State Entered");
5825         BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong",
5826             &stats->dot3StatsFramesTooLong, "Frames Too Long");
5827         BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers",
5828             &stats->etherStatsJabbers, "Jabbers");
5829         BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts",
5830             &stats->etherStatsUndersizePkts, "Undersized Packets");
5831
5832         tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD,
5833             NULL, "BGE TX Statistics");
5834         child = SYSCTL_CHILDREN(tree);
5835         BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets",
5836             &stats->ifHCOutOctets, "Outbound Octets");
5837         BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions",
5838             &stats->etherStatsCollisions, "TX Collisions");
5839         BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent",
5840             &stats->outXonSent, "XON Sent");
5841         BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent",
5842             &stats->outXoffSent, "XOFF Sent");
5843         BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors",
5844             &stats->dot3StatsInternalMacTransmitErrors,
5845             "Internal MAC TX Errors");
5846         BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames",
5847             &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames");
5848         BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames",
5849             &stats->dot3StatsMultipleCollisionFrames,
5850             "Multiple Collision Frames");
5851         BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions",
5852             &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions");
5853         BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions",
5854             &stats->dot3StatsExcessiveCollisions, "Excessive Collisions");
5855         BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions",
5856             &stats->dot3StatsLateCollisions, "Late Collisions");
5857         BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
5858             &stats->ifHCOutUcastPkts, "Outbound Unicast Packets");
5859         BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
5860             &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets");
5861         BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
5862             &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets");
5863 }
5864
5865 #undef  BGE_SYSCTL_STAT_ADD64
5866
5867 static int
5868 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
5869 {
5870         struct bge_softc *sc;
5871         uint32_t result;
5872         int offset;
5873
5874         sc = (struct bge_softc *)arg1;
5875         offset = arg2;
5876         result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
5877             offsetof(bge_hostaddr, bge_addr_lo));
5878         return (sysctl_handle_int(oidp, &result, 0, req));
5879 }
5880
5881 #ifdef BGE_REGISTER_DEBUG
5882 static int
5883 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
5884 {
5885         struct bge_softc *sc;
5886         uint16_t *sbdata;
5887         int error, result, sbsz;
5888         int i, j;
5889
5890         result = -1;
5891         error = sysctl_handle_int(oidp, &result, 0, req);
5892         if (error || (req->newptr == NULL))
5893                 return (error);
5894
5895         if (result == 1) {
5896                 sc = (struct bge_softc *)arg1;
5897
5898                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
5899                     sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
5900                         sbsz = BGE_STATUS_BLK_SZ;
5901                 else
5902                         sbsz = 32;
5903                 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
5904                 printf("Status Block:\n");
5905                 BGE_LOCK(sc);
5906                 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
5907                     sc->bge_cdata.bge_status_map,
5908                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
5909                 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) {
5910                         printf("%06x:", i);
5911                         for (j = 0; j < 8; j++)
5912                                 printf(" %04x", sbdata[i++]);
5913                         printf("\n");
5914                 }
5915
5916                 printf("Registers:\n");
5917                 for (i = 0x800; i < 0xA00; ) {
5918                         printf("%06x:", i);
5919                         for (j = 0; j < 8; j++) {
5920                                 printf(" %08x", CSR_READ_4(sc, i));
5921                                 i += 4;
5922                         }
5923                         printf("\n");
5924                 }
5925                 BGE_UNLOCK(sc);
5926
5927                 printf("Hardware Flags:\n");
5928                 if (BGE_IS_5717_PLUS(sc))
5929                         printf(" - 5717 Plus\n");
5930                 if (BGE_IS_5755_PLUS(sc))
5931                         printf(" - 5755 Plus\n");
5932                 if (BGE_IS_575X_PLUS(sc))
5933                         printf(" - 575X Plus\n");
5934                 if (BGE_IS_5705_PLUS(sc))
5935                         printf(" - 5705 Plus\n");
5936                 if (BGE_IS_5714_FAMILY(sc))
5937                         printf(" - 5714 Family\n");
5938                 if (BGE_IS_5700_FAMILY(sc))
5939                         printf(" - 5700 Family\n");
5940                 if (sc->bge_flags & BGE_FLAG_JUMBO)
5941                         printf(" - Supports Jumbo Frames\n");
5942                 if (sc->bge_flags & BGE_FLAG_PCIX)
5943                         printf(" - PCI-X Bus\n");
5944                 if (sc->bge_flags & BGE_FLAG_PCIE)
5945                         printf(" - PCI Express Bus\n");
5946                 if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
5947                         printf(" - No 3 LEDs\n");
5948                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
5949                         printf(" - RX Alignment Bug\n");
5950         }
5951
5952         return (error);
5953 }
5954
5955 static int
5956 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5957 {
5958         struct bge_softc *sc;
5959         int error;
5960         uint16_t result;
5961         uint32_t val;
5962
5963         result = -1;
5964         error = sysctl_handle_int(oidp, &result, 0, req);
5965         if (error || (req->newptr == NULL))
5966                 return (error);
5967
5968         if (result < 0x8000) {
5969                 sc = (struct bge_softc *)arg1;
5970                 val = CSR_READ_4(sc, result);
5971                 printf("reg 0x%06X = 0x%08X\n", result, val);
5972         }
5973
5974         return (error);
5975 }
5976
5977 static int
5978 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
5979 {
5980         struct bge_softc *sc;
5981         int error;
5982         uint16_t result;
5983         uint32_t val;
5984
5985         result = -1;
5986         error = sysctl_handle_int(oidp, &result, 0, req);
5987         if (error || (req->newptr == NULL))
5988                 return (error);
5989
5990         if (result < 0x8000) {
5991                 sc = (struct bge_softc *)arg1;
5992                 val = bge_readmem_ind(sc, result);
5993                 printf("mem 0x%06X = 0x%08X\n", result, val);
5994         }
5995
5996         return (error);
5997 }
5998 #endif
5999
6000 static int
6001 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
6002 {
6003
6004         if (sc->bge_flags & BGE_FLAG_EADDR)
6005                 return (1);
6006
6007 #ifdef __sparc64__
6008         OF_getetheraddr(sc->bge_dev, ether_addr);
6009         return (0);
6010 #endif
6011         return (1);
6012 }
6013
6014 static int
6015 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
6016 {
6017         uint32_t mac_addr;
6018
6019         mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
6020         if ((mac_addr >> 16) == 0x484b) {
6021                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
6022                 ether_addr[1] = (uint8_t)mac_addr;
6023                 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
6024                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
6025                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
6026                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
6027                 ether_addr[5] = (uint8_t)mac_addr;
6028                 return (0);
6029         }
6030         return (1);
6031 }
6032
6033 static int
6034 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
6035 {
6036         int mac_offset = BGE_EE_MAC_OFFSET;
6037
6038         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6039                 mac_offset = BGE_EE_MAC_OFFSET_5906;
6040
6041         return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
6042             ETHER_ADDR_LEN));
6043 }
6044
6045 static int
6046 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
6047 {
6048
6049         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6050                 return (1);
6051
6052         return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
6053            ETHER_ADDR_LEN));
6054 }
6055
6056 static int
6057 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
6058 {
6059         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
6060                 /* NOTE: Order is critical */
6061                 bge_get_eaddr_fw,
6062                 bge_get_eaddr_mem,
6063                 bge_get_eaddr_nvram,
6064                 bge_get_eaddr_eeprom,
6065                 NULL
6066         };
6067         const bge_eaddr_fcn_t *func;
6068
6069         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
6070                 if ((*func)(sc, eaddr) == 0)
6071                         break;
6072         }
6073         return (*func == NULL ? ENXIO : 0);
6074 }