2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 2001 Wind River Systems
5 * Copyright (c) 1997, 1998, 1999, 2001
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
40 * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver
42 * The Broadcom BCM5700 is based on technology originally developed by
43 * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet
44 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
45 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
46 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
47 * frames, highly configurable RX filtering, and 16 RX and TX queues
48 * (which, along with RX filter rules, can be used for QOS applications).
49 * Other features, such as TCP segmentation, may be available as part
50 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
51 * firmware images can be stored in hardware and need not be compiled
54 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
55 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
57 * The BCM5701 is a single-chip solution incorporating both the BCM5700
58 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
59 * does not support external SSRAM.
61 * Broadcom also produces a variation of the BCM5700 under the "Altima"
62 * brand name, which is functionally similar but lacks PCI-X support.
64 * Without external SSRAM, you can only have at most 4 TX rings,
65 * and the use of the mini RX ring is disabled. This seems to imply
66 * that these features are simply not available on the BCM5701. As a
67 * result, this driver does not implement any support for the mini RX
71 #ifdef HAVE_KERNEL_OPTION_HEADERS
72 #include "opt_device_polling.h"
75 #include <sys/param.h>
76 #include <sys/endian.h>
77 #include <sys/systm.h>
78 #include <sys/sockio.h>
80 #include <sys/malloc.h>
81 #include <sys/kernel.h>
82 #include <sys/module.h>
83 #include <sys/socket.h>
84 #include <sys/sysctl.h>
85 #include <sys/taskqueue.h>
88 #include <net/if_var.h>
89 #include <net/if_arp.h>
90 #include <net/ethernet.h>
91 #include <net/if_dl.h>
92 #include <net/if_media.h>
96 #include <net/if_types.h>
97 #include <net/if_vlan_var.h>
99 #include <netinet/in_systm.h>
100 #include <netinet/in.h>
101 #include <netinet/ip.h>
102 #include <netinet/tcp.h>
103 #include <netinet/netdump/netdump.h>
105 #include <machine/bus.h>
106 #include <machine/resource.h>
108 #include <sys/rman.h>
110 #include <dev/mii/mii.h>
111 #include <dev/mii/miivar.h>
113 #include <dev/mii/brgphyreg.h>
116 #include <dev/ofw/ofw_bus.h>
117 #include <dev/ofw/openfirm.h>
118 #include <machine/ofw_machdep.h>
119 #include <machine/ver.h>
122 #include <dev/pci/pcireg.h>
123 #include <dev/pci/pcivar.h>
125 #include <dev/bge/if_bgereg.h>
127 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP)
128 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
130 MODULE_DEPEND(bge, pci, 1, 1, 1);
131 MODULE_DEPEND(bge, ether, 1, 1, 1);
132 MODULE_DEPEND(bge, miibus, 1, 1, 1);
134 /* "device miibus" required. See GENERIC if you get errors here. */
135 #include "miibus_if.h"
138 * Various supported device vendors/types and their names. Note: the
139 * spec seems to indicate that the hardware still has Alteon's vendor
140 * ID burned into it, though it will always be overriden by the vendor
141 * ID in the EEPROM. Just to be safe, we cover all possibilities.
143 static const struct bge_type {
147 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 },
148 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 },
150 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 },
151 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 },
152 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 },
154 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 },
156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 },
157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 },
158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 },
159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT },
160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X },
161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 },
162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT },
163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X },
164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C },
165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S },
166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT },
167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 },
168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F },
169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K },
170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M },
171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT },
172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C },
173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S },
174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 },
175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S },
176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 },
177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717C },
178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 },
179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 },
180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 },
181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 },
182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 },
183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 },
184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5725 },
185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5727 },
186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 },
187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M },
188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 },
189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F },
190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M },
191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 },
192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M },
193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 },
194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F },
195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M },
196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 },
197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M },
198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 },
199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M },
200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 },
201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 },
202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E },
203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S },
204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE },
205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5762 },
206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 },
207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 },
208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S },
209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 },
210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 },
211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 },
212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F },
213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G },
214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 },
215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 },
216 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F },
217 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M },
218 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 },
219 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 },
220 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 },
221 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 },
222 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M },
223 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 },
224 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M },
225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 },
226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 },
227 { BCOM_VENDORID, BCOM_DEVICEID_BCM57762 },
228 { BCOM_VENDORID, BCOM_DEVICEID_BCM57764 },
229 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 },
230 { BCOM_VENDORID, BCOM_DEVICEID_BCM57766 },
231 { BCOM_VENDORID, BCOM_DEVICEID_BCM57767 },
232 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 },
233 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 },
234 { BCOM_VENDORID, BCOM_DEVICEID_BCM57782 },
235 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 },
236 { BCOM_VENDORID, BCOM_DEVICEID_BCM57786 },
237 { BCOM_VENDORID, BCOM_DEVICEID_BCM57787 },
238 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 },
239 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 },
240 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 },
241 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 },
243 { SK_VENDORID, SK_DEVICEID_ALTIMA },
245 { TC_VENDORID, TC_DEVICEID_3C996 },
247 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 },
248 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 },
249 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 },
254 static const struct bge_vendor {
258 { ALTEON_VENDORID, "Alteon" },
259 { ALTIMA_VENDORID, "Altima" },
260 { APPLE_VENDORID, "Apple" },
261 { BCOM_VENDORID, "Broadcom" },
262 { SK_VENDORID, "SysKonnect" },
263 { TC_VENDORID, "3Com" },
264 { FJTSU_VENDORID, "Fujitsu" },
269 static const struct bge_revision {
272 } bge_revisions[] = {
273 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" },
274 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" },
275 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" },
276 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" },
277 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" },
278 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" },
279 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" },
280 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" },
281 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" },
282 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" },
283 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" },
284 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" },
285 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" },
286 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" },
287 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" },
288 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" },
289 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" },
290 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" },
291 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" },
292 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" },
293 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" },
294 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" },
295 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" },
296 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" },
297 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" },
298 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" },
299 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" },
300 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" },
301 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" },
302 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" },
303 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" },
304 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" },
305 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" },
306 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" },
307 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
308 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
309 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
310 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
311 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
312 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
313 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
314 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
315 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
316 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" },
317 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" },
318 { BGE_CHIPID_BCM5717_C0, "BCM5717 C0" },
319 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" },
320 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" },
321 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
322 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
323 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
324 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" },
325 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" },
326 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" },
327 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" },
328 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" },
329 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" },
330 /* 5754 and 5787 share the same ASIC ID */
331 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
332 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
333 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
334 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" },
335 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" },
336 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" },
337 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" },
338 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" },
339 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" },
345 * Some defaults for major revisions, so that newer steppings
346 * that we don't know about have a shot at working.
348 static const struct bge_revision bge_majorrevs[] = {
349 { BGE_ASICREV_BCM5700, "unknown BCM5700" },
350 { BGE_ASICREV_BCM5701, "unknown BCM5701" },
351 { BGE_ASICREV_BCM5703, "unknown BCM5703" },
352 { BGE_ASICREV_BCM5704, "unknown BCM5704" },
353 { BGE_ASICREV_BCM5705, "unknown BCM5705" },
354 { BGE_ASICREV_BCM5750, "unknown BCM5750" },
355 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
356 { BGE_ASICREV_BCM5752, "unknown BCM5752" },
357 { BGE_ASICREV_BCM5780, "unknown BCM5780" },
358 { BGE_ASICREV_BCM5714, "unknown BCM5714" },
359 { BGE_ASICREV_BCM5755, "unknown BCM5755" },
360 { BGE_ASICREV_BCM5761, "unknown BCM5761" },
361 { BGE_ASICREV_BCM5784, "unknown BCM5784" },
362 { BGE_ASICREV_BCM5785, "unknown BCM5785" },
363 /* 5754 and 5787 share the same ASIC ID */
364 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
365 { BGE_ASICREV_BCM5906, "unknown BCM5906" },
366 { BGE_ASICREV_BCM57765, "unknown BCM57765" },
367 { BGE_ASICREV_BCM57766, "unknown BCM57766" },
368 { BGE_ASICREV_BCM57780, "unknown BCM57780" },
369 { BGE_ASICREV_BCM5717, "unknown BCM5717" },
370 { BGE_ASICREV_BCM5719, "unknown BCM5719" },
371 { BGE_ASICREV_BCM5720, "unknown BCM5720" },
372 { BGE_ASICREV_BCM5762, "unknown BCM5762" },
377 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
378 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
379 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
380 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
381 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
382 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
383 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS)
384 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_57765_PLUS)
386 static uint32_t bge_chipid(device_t);
387 static const struct bge_vendor * bge_lookup_vendor(uint16_t);
388 static const struct bge_revision * bge_lookup_rev(uint32_t);
390 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
392 static int bge_probe(device_t);
393 static int bge_attach(device_t);
394 static int bge_detach(device_t);
395 static int bge_suspend(device_t);
396 static int bge_resume(device_t);
397 static void bge_release_resources(struct bge_softc *);
398 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
399 static int bge_dma_alloc(struct bge_softc *);
400 static void bge_dma_free(struct bge_softc *);
401 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t,
402 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
404 static void bge_devinfo(struct bge_softc *);
405 static int bge_mbox_reorder(struct bge_softc *);
407 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
408 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
409 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
410 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
411 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
413 static void bge_txeof(struct bge_softc *, uint16_t);
414 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
415 static int bge_rxeof(struct bge_softc *, uint16_t, int);
417 static void bge_asf_driver_up (struct bge_softc *);
418 static void bge_tick(void *);
419 static void bge_stats_clear_regs(struct bge_softc *);
420 static void bge_stats_update(struct bge_softc *);
421 static void bge_stats_update_regs(struct bge_softc *);
422 static struct mbuf *bge_check_short_dma(struct mbuf *);
423 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
424 uint16_t *, uint16_t *);
425 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
427 static void bge_intr(void *);
428 static int bge_msi_intr(void *);
429 static void bge_intr_task(void *, int);
430 static void bge_start(if_t);
431 static void bge_start_locked(if_t);
432 static void bge_start_tx(struct bge_softc *, uint32_t);
433 static int bge_ioctl(if_t, u_long, caddr_t);
434 static void bge_init_locked(struct bge_softc *);
435 static void bge_init(void *);
436 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
437 static void bge_stop(struct bge_softc *);
438 static void bge_watchdog(struct bge_softc *);
439 static int bge_shutdown(device_t);
440 static int bge_ifmedia_upd_locked(if_t);
441 static int bge_ifmedia_upd(if_t);
442 static void bge_ifmedia_sts(if_t, struct ifmediareq *);
443 static uint64_t bge_get_counter(if_t, ift_counter);
445 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
446 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
448 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
449 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
451 static void bge_setpromisc(struct bge_softc *);
452 static void bge_setmulti(struct bge_softc *);
453 static void bge_setvlan(struct bge_softc *);
455 static __inline void bge_rxreuse_std(struct bge_softc *, int);
456 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
457 static int bge_newbuf_std(struct bge_softc *, int);
458 static int bge_newbuf_jumbo(struct bge_softc *, int);
459 static int bge_init_rx_ring_std(struct bge_softc *);
460 static void bge_free_rx_ring_std(struct bge_softc *);
461 static int bge_init_rx_ring_jumbo(struct bge_softc *);
462 static void bge_free_rx_ring_jumbo(struct bge_softc *);
463 static void bge_free_tx_ring(struct bge_softc *);
464 static int bge_init_tx_ring(struct bge_softc *);
466 static int bge_chipinit(struct bge_softc *);
467 static int bge_blockinit(struct bge_softc *);
468 static uint32_t bge_dma_swap_options(struct bge_softc *);
470 static int bge_has_eaddr(struct bge_softc *);
471 static uint32_t bge_readmem_ind(struct bge_softc *, int);
472 static void bge_writemem_ind(struct bge_softc *, int, int);
473 static void bge_writembx(struct bge_softc *, int, int);
475 static uint32_t bge_readreg_ind(struct bge_softc *, int);
477 static void bge_writemem_direct(struct bge_softc *, int, int);
478 static void bge_writereg_ind(struct bge_softc *, int, int);
480 static int bge_miibus_readreg(device_t, int, int);
481 static int bge_miibus_writereg(device_t, int, int, int);
482 static void bge_miibus_statchg(device_t);
483 #ifdef DEVICE_POLLING
484 static int bge_poll(if_t ifp, enum poll_cmd cmd, int count);
487 #define BGE_RESET_SHUTDOWN 0
488 #define BGE_RESET_START 1
489 #define BGE_RESET_SUSPEND 2
490 static void bge_sig_post_reset(struct bge_softc *, int);
491 static void bge_sig_legacy(struct bge_softc *, int);
492 static void bge_sig_pre_reset(struct bge_softc *, int);
493 static void bge_stop_fw(struct bge_softc *);
494 static int bge_reset(struct bge_softc *);
495 static void bge_link_upd(struct bge_softc *);
497 static void bge_ape_lock_init(struct bge_softc *);
498 static void bge_ape_read_fw_ver(struct bge_softc *);
499 static int bge_ape_lock(struct bge_softc *, int);
500 static void bge_ape_unlock(struct bge_softc *, int);
501 static void bge_ape_send_event(struct bge_softc *, uint32_t);
502 static void bge_ape_driver_state_change(struct bge_softc *, int);
505 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may
506 * leak information to untrusted users. It is also known to cause alignment
507 * traps on certain architectures.
509 #ifdef BGE_REGISTER_DEBUG
510 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
511 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
512 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS);
513 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
515 static void bge_add_sysctls(struct bge_softc *);
516 static void bge_add_sysctl_stats_regs(struct bge_softc *,
517 struct sysctl_ctx_list *, struct sysctl_oid_list *);
518 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *,
519 struct sysctl_oid_list *);
520 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
524 static device_method_t bge_methods[] = {
525 /* Device interface */
526 DEVMETHOD(device_probe, bge_probe),
527 DEVMETHOD(device_attach, bge_attach),
528 DEVMETHOD(device_detach, bge_detach),
529 DEVMETHOD(device_shutdown, bge_shutdown),
530 DEVMETHOD(device_suspend, bge_suspend),
531 DEVMETHOD(device_resume, bge_resume),
534 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
535 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
536 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
541 static driver_t bge_driver = {
544 sizeof(struct bge_softc)
547 static devclass_t bge_devclass;
549 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
550 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
552 static int bge_allow_asf = 1;
554 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
555 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RDTUN, &bge_allow_asf, 0,
556 "Allow ASF mode if available");
558 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500"
559 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2"
560 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500"
561 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3"
562 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id"
565 bge_has_eaddr(struct bge_softc *sc)
568 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
575 * The on-board BGEs found in sun4u machines aren't fitted with
576 * an EEPROM which means that we have to obtain the MAC address
577 * via OFW and that some tests will always fail. We distinguish
578 * such BGEs by the subvendor ID, which also has to be obtained
579 * from OFW instead of the PCI configuration space as the latter
580 * indicates Broadcom as the subvendor of the netboot interface.
581 * For early Blade 1500 and 2500 we even have to check the OFW
582 * device path as the subvendor ID always defaults to Broadcom
585 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
586 &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
587 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID))
589 memset(buf, 0, sizeof(buf));
590 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
591 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
592 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
594 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
595 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
603 bge_readmem_ind(struct bge_softc *sc, int off)
608 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
609 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
614 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
615 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
616 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
621 bge_writemem_ind(struct bge_softc *sc, int off, int val)
625 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
626 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
631 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
632 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
633 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
638 bge_readreg_ind(struct bge_softc *sc, int off)
644 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
645 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
650 bge_writereg_ind(struct bge_softc *sc, int off, int val)
656 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
657 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
661 bge_writemem_direct(struct bge_softc *sc, int off, int val)
663 CSR_WRITE_4(sc, off, val);
667 bge_writembx(struct bge_softc *sc, int off, int val)
669 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
670 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
672 CSR_WRITE_4(sc, off, val);
673 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0)
678 * Clear all stale locks and select the lock for this driver instance.
681 bge_ape_lock_init(struct bge_softc *sc)
683 uint32_t bit, regbase;
686 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
687 regbase = BGE_APE_LOCK_GRANT;
689 regbase = BGE_APE_PER_LOCK_GRANT;
691 /* Clear any stale locks. */
692 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
694 case BGE_APE_LOCK_PHY0:
695 case BGE_APE_LOCK_PHY1:
696 case BGE_APE_LOCK_PHY2:
697 case BGE_APE_LOCK_PHY3:
698 bit = BGE_APE_LOCK_GRANT_DRIVER0;
701 if (sc->bge_func_addr == 0)
702 bit = BGE_APE_LOCK_GRANT_DRIVER0;
704 bit = (1 << sc->bge_func_addr);
706 APE_WRITE_4(sc, regbase + 4 * i, bit);
709 /* Select the PHY lock based on the device's function number. */
710 switch (sc->bge_func_addr) {
712 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
715 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
718 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
721 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
724 device_printf(sc->bge_dev,
725 "PHY lock not supported on this function\n");
730 * Check for APE firmware, set flags, and print version info.
733 bge_ape_read_fw_ver(struct bge_softc *sc)
736 uint32_t apedata, features;
738 /* Check for a valid APE signature in shared memory. */
739 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
740 if (apedata != BGE_APE_SEG_SIG_MAGIC) {
741 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE;
745 /* Check if APE firmware is running. */
746 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
747 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) {
748 device_printf(sc->bge_dev, "APE signature found "
749 "but FW status not ready! 0x%08x\n", apedata);
753 sc->bge_mfw_flags |= BGE_MFW_ON_APE;
755 /* Fetch the APE firwmare type and version. */
756 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
757 features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
758 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) {
759 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
761 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) {
762 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
767 /* Print the APE firmware version. */
768 device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n",
770 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT,
771 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT,
772 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT,
773 (apedata & BGE_APE_FW_VERSION_BLDMSK));
777 bge_ape_lock(struct bge_softc *sc, int locknum)
779 uint32_t bit, gnt, req, status;
782 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
785 /* Lock request/grant registers have different bases. */
786 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) {
787 req = BGE_APE_LOCK_REQ;
788 gnt = BGE_APE_LOCK_GRANT;
790 req = BGE_APE_PER_LOCK_REQ;
791 gnt = BGE_APE_PER_LOCK_GRANT;
797 case BGE_APE_LOCK_GPIO:
798 /* Lock required when using GPIO. */
799 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
801 if (sc->bge_func_addr == 0)
802 bit = BGE_APE_LOCK_REQ_DRIVER0;
804 bit = (1 << sc->bge_func_addr);
806 case BGE_APE_LOCK_GRC:
807 /* Lock required to reset the device. */
808 if (sc->bge_func_addr == 0)
809 bit = BGE_APE_LOCK_REQ_DRIVER0;
811 bit = (1 << sc->bge_func_addr);
813 case BGE_APE_LOCK_MEM:
814 /* Lock required when accessing certain APE memory. */
815 if (sc->bge_func_addr == 0)
816 bit = BGE_APE_LOCK_REQ_DRIVER0;
818 bit = (1 << sc->bge_func_addr);
820 case BGE_APE_LOCK_PHY0:
821 case BGE_APE_LOCK_PHY1:
822 case BGE_APE_LOCK_PHY2:
823 case BGE_APE_LOCK_PHY3:
824 /* Lock required when accessing PHYs. */
825 bit = BGE_APE_LOCK_REQ_DRIVER0;
831 /* Request a lock. */
832 APE_WRITE_4(sc, req + off, bit);
834 /* Wait up to 1 second to acquire lock. */
835 for (i = 0; i < 20000; i++) {
836 status = APE_READ_4(sc, gnt + off);
842 /* Handle any errors. */
844 device_printf(sc->bge_dev, "APE lock %d request failed! "
845 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
846 locknum, req + off, bit & 0xFFFF, gnt + off,
848 /* Revoke the lock request. */
849 APE_WRITE_4(sc, gnt + off, bit);
857 bge_ape_unlock(struct bge_softc *sc, int locknum)
862 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
865 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
866 gnt = BGE_APE_LOCK_GRANT;
868 gnt = BGE_APE_PER_LOCK_GRANT;
873 case BGE_APE_LOCK_GPIO:
874 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
876 if (sc->bge_func_addr == 0)
877 bit = BGE_APE_LOCK_GRANT_DRIVER0;
879 bit = (1 << sc->bge_func_addr);
881 case BGE_APE_LOCK_GRC:
882 if (sc->bge_func_addr == 0)
883 bit = BGE_APE_LOCK_GRANT_DRIVER0;
885 bit = (1 << sc->bge_func_addr);
887 case BGE_APE_LOCK_MEM:
888 if (sc->bge_func_addr == 0)
889 bit = BGE_APE_LOCK_GRANT_DRIVER0;
891 bit = (1 << sc->bge_func_addr);
893 case BGE_APE_LOCK_PHY0:
894 case BGE_APE_LOCK_PHY1:
895 case BGE_APE_LOCK_PHY2:
896 case BGE_APE_LOCK_PHY3:
897 bit = BGE_APE_LOCK_GRANT_DRIVER0;
903 APE_WRITE_4(sc, gnt + off, bit);
907 * Send an event to the APE firmware.
910 bge_ape_send_event(struct bge_softc *sc, uint32_t event)
915 /* NCSI does not support APE events. */
916 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
919 /* Wait up to 1ms for APE to service previous event. */
920 for (i = 10; i > 0; i--) {
921 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
923 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
924 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) {
925 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
926 BGE_APE_EVENT_STATUS_EVENT_PENDING);
927 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
928 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
931 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
935 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n",
940 bge_ape_driver_state_change(struct bge_softc *sc, int kind)
942 uint32_t apedata, event;
944 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
948 case BGE_RESET_START:
949 /* If this is the first load, clear the load counter. */
950 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
951 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC)
952 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
954 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
955 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
957 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
958 BGE_APE_HOST_SEG_SIG_MAGIC);
959 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
960 BGE_APE_HOST_SEG_LEN_MAGIC);
962 /* Add some version info if bge(4) supports it. */
963 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
964 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0));
965 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
966 BGE_APE_HOST_BEHAV_NO_PHYLOCK);
967 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
968 BGE_APE_HOST_HEARTBEAT_INT_DISABLE);
969 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
970 BGE_APE_HOST_DRVR_STATE_START);
971 event = BGE_APE_EVENT_STATUS_STATE_START;
973 case BGE_RESET_SHUTDOWN:
974 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
975 BGE_APE_HOST_DRVR_STATE_UNLOAD);
976 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
978 case BGE_RESET_SUSPEND:
979 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
985 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
986 BGE_APE_EVENT_STATUS_STATE_CHNGE);
990 * Map a single buffer address.
994 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
996 struct bge_dmamap_arg *ctx;
1001 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
1004 ctx->bge_busaddr = segs->ds_addr;
1008 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1010 uint32_t access, byte = 0;
1014 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
1015 for (i = 0; i < 8000; i++) {
1016 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
1023 /* Enable access. */
1024 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
1025 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
1027 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
1028 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
1029 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
1031 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
1037 if (i == BGE_TIMEOUT * 10) {
1038 if_printf(sc->bge_ifp, "nvram read timed out\n");
1043 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
1045 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
1047 /* Disable access. */
1048 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
1051 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
1052 CSR_READ_4(sc, BGE_NVRAM_SWARB);
1058 * Read a sequence of bytes from NVRAM.
1061 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1066 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1069 for (i = 0; i < cnt; i++) {
1070 err = bge_nvram_getbyte(sc, off + i, &byte);
1076 return (err ? 1 : 0);
1080 * Read a byte of data stored in the EEPROM at address 'addr.' The
1081 * BCM570x supports both the traditional bitbang interface and an
1082 * auto access interface for reading the EEPROM. We use the auto
1086 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1092 * Enable use of auto EEPROM access so we can avoid
1093 * having to use the bitbang method.
1095 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
1097 /* Reset the EEPROM, load the clock period. */
1098 CSR_WRITE_4(sc, BGE_EE_ADDR,
1099 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
1102 /* Issue the read EEPROM command. */
1103 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
1105 /* Wait for completion */
1106 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
1108 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1112 if (i == BGE_TIMEOUT * 10) {
1113 device_printf(sc->bge_dev, "EEPROM read timed out\n");
1118 byte = CSR_READ_4(sc, BGE_EE_DATA);
1120 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
1126 * Read a sequence of bytes from the EEPROM.
1129 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1134 for (i = 0; i < cnt; i++) {
1135 error = bge_eeprom_getbyte(sc, off + i, &byte);
1141 return (error ? 1 : 0);
1145 bge_miibus_readreg(device_t dev, int phy, int reg)
1147 struct bge_softc *sc;
1151 sc = device_get_softc(dev);
1153 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1156 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1157 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1158 CSR_WRITE_4(sc, BGE_MI_MODE,
1159 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1163 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
1164 BGE_MIPHY(phy) | BGE_MIREG(reg));
1166 /* Poll for the PHY register access to complete. */
1167 for (i = 0; i < BGE_TIMEOUT; i++) {
1169 val = CSR_READ_4(sc, BGE_MI_COMM);
1170 if ((val & BGE_MICOMM_BUSY) == 0) {
1172 val = CSR_READ_4(sc, BGE_MI_COMM);
1177 if (i == BGE_TIMEOUT) {
1178 device_printf(sc->bge_dev,
1179 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
1184 /* Restore the autopoll bit if necessary. */
1185 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1186 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1190 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1192 if (val & BGE_MICOMM_READFAIL)
1195 return (val & 0xFFFF);
1199 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
1201 struct bge_softc *sc;
1204 sc = device_get_softc(dev);
1206 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1207 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
1210 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1213 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1214 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1215 CSR_WRITE_4(sc, BGE_MI_MODE,
1216 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1220 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
1221 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
1223 for (i = 0; i < BGE_TIMEOUT; i++) {
1225 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
1227 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
1232 /* Restore the autopoll bit if necessary. */
1233 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1234 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1238 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1240 if (i == BGE_TIMEOUT)
1241 device_printf(sc->bge_dev,
1242 "PHY write timed out (phy %d, reg %d, val 0x%04x)\n",
1249 bge_miibus_statchg(device_t dev)
1251 struct bge_softc *sc;
1252 struct mii_data *mii;
1253 uint32_t mac_mode, rx_mode, tx_mode;
1255 sc = device_get_softc(dev);
1256 if ((if_getdrvflags(sc->bge_ifp) & IFF_DRV_RUNNING) == 0)
1258 mii = device_get_softc(sc->bge_miibus);
1260 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1261 (IFM_ACTIVE | IFM_AVALID)) {
1262 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1270 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1281 if (sc->bge_link == 0)
1285 * APE firmware touches these registers to keep the MAC
1286 * connected to the outside world. Try to keep the
1290 /* Set the port mode (MII/GMII) to match the link speed. */
1291 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
1292 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
1293 tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
1294 rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
1296 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1297 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
1298 mac_mode |= BGE_PORTMODE_GMII;
1300 mac_mode |= BGE_PORTMODE_MII;
1302 /* Set MAC flow control behavior to match link flow control settings. */
1303 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE;
1304 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE;
1305 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1306 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1307 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE;
1308 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1309 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE;
1311 mac_mode |= BGE_MACMODE_HALF_DUPLEX;
1313 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
1315 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
1316 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
1320 * Intialize a standard receive ring descriptor.
1323 bge_newbuf_std(struct bge_softc *sc, int i)
1326 struct bge_rx_bd *r;
1327 bus_dma_segment_t segs[1];
1331 if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
1332 (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
1333 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) {
1334 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1337 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1339 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1342 m->m_len = m->m_pkthdr.len = MCLBYTES;
1344 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1345 m_adj(m, ETHER_ALIGN);
1347 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
1348 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
1353 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1354 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1355 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
1356 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1357 sc->bge_cdata.bge_rx_std_dmamap[i]);
1359 map = sc->bge_cdata.bge_rx_std_dmamap[i];
1360 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
1361 sc->bge_cdata.bge_rx_std_sparemap = map;
1362 sc->bge_cdata.bge_rx_std_chain[i] = m;
1363 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
1364 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
1365 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1366 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1367 r->bge_flags = BGE_RXBDFLAG_END;
1368 r->bge_len = segs[0].ds_len;
1371 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1372 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
1378 * Initialize a jumbo receive ring descriptor. This allocates
1379 * a jumbo buffer from the pool managed internally by the driver.
1382 bge_newbuf_jumbo(struct bge_softc *sc, int i)
1384 bus_dma_segment_t segs[BGE_NSEG_JUMBO];
1386 struct bge_extrx_bd *r;
1390 MGETHDR(m, M_NOWAIT, MT_DATA);
1394 if (m_cljget(m, M_NOWAIT, MJUM9BYTES) == NULL) {
1398 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1399 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1400 m_adj(m, ETHER_ALIGN);
1402 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1403 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1409 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1410 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1411 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1412 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1413 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1415 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1416 sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1417 sc->bge_cdata.bge_rx_jumbo_sparemap;
1418 sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1419 sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1420 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1421 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1422 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1423 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1426 * Fill in the extended RX buffer descriptor.
1428 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1429 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1431 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1434 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1435 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1436 r->bge_len3 = segs[3].ds_len;
1437 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1439 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1440 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1441 r->bge_len2 = segs[2].ds_len;
1442 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1444 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1445 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1446 r->bge_len1 = segs[1].ds_len;
1447 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1449 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1450 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1451 r->bge_len0 = segs[0].ds_len;
1452 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1455 panic("%s: %d segments\n", __func__, nsegs);
1458 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1459 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1465 bge_init_rx_ring_std(struct bge_softc *sc)
1469 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1471 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1472 if ((error = bge_newbuf_std(sc, i)) != 0)
1474 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1477 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1478 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1481 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1487 bge_free_rx_ring_std(struct bge_softc *sc)
1491 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1492 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1493 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1494 sc->bge_cdata.bge_rx_std_dmamap[i],
1495 BUS_DMASYNC_POSTREAD);
1496 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1497 sc->bge_cdata.bge_rx_std_dmamap[i]);
1498 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1499 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1501 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1502 sizeof(struct bge_rx_bd));
1507 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1509 struct bge_rcb *rcb;
1512 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1514 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1515 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1517 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1520 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1521 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1525 /* Enable the jumbo receive producer ring. */
1526 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1527 rcb->bge_maxlen_flags =
1528 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD);
1529 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1531 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1537 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1541 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1542 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1543 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1544 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1545 BUS_DMASYNC_POSTREAD);
1546 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1547 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1548 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1549 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1551 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1552 sizeof(struct bge_extrx_bd));
1557 bge_free_tx_ring(struct bge_softc *sc)
1561 if (sc->bge_ldata.bge_tx_ring == NULL)
1564 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1565 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1566 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1567 sc->bge_cdata.bge_tx_dmamap[i],
1568 BUS_DMASYNC_POSTWRITE);
1569 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1570 sc->bge_cdata.bge_tx_dmamap[i]);
1571 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1572 sc->bge_cdata.bge_tx_chain[i] = NULL;
1574 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1575 sizeof(struct bge_tx_bd));
1580 bge_init_tx_ring(struct bge_softc *sc)
1583 sc->bge_tx_saved_considx = 0;
1585 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1586 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1587 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1589 /* Initialize transmit producer index for host-memory send ring. */
1590 sc->bge_tx_prodidx = 0;
1591 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1593 /* 5700 b2 errata */
1594 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1595 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1597 /* NIC-memory send ring not used; initialize to zero. */
1598 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1599 /* 5700 b2 errata */
1600 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1601 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1607 bge_setpromisc(struct bge_softc *sc)
1611 BGE_LOCK_ASSERT(sc);
1615 /* Enable or disable promiscuous mode as needed. */
1616 if (if_getflags(ifp) & IFF_PROMISC)
1617 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1619 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1623 bge_setmulti(struct bge_softc *sc)
1627 uint32_t hashes[4] = { 0, 0, 0, 0 };
1631 BGE_LOCK_ASSERT(sc);
1635 mc_count = if_multiaddr_count(ifp, -1);
1636 mta = malloc(sizeof(unsigned char) * ETHER_ADDR_LEN *
1637 mc_count, M_DEVBUF, M_NOWAIT);
1640 device_printf(sc->bge_dev,
1641 "Failed to allocated temp mcast list\n");
1645 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) {
1646 for (i = 0; i < 4; i++)
1647 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1648 free(mta, M_DEVBUF);
1652 /* First, zot all the existing filters. */
1653 for (i = 0; i < 4; i++)
1654 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1656 if_multiaddr_array(ifp, mta, &mcnt, mc_count);
1657 for(i = 0; i < mcnt; i++) {
1658 h = ether_crc32_le(mta + (i * ETHER_ADDR_LEN),
1659 ETHER_ADDR_LEN) & 0x7F;
1660 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1663 for (i = 0; i < 4; i++)
1664 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1666 free(mta, M_DEVBUF);
1670 bge_setvlan(struct bge_softc *sc)
1674 BGE_LOCK_ASSERT(sc);
1678 /* Enable or disable VLAN tag stripping as needed. */
1679 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING)
1680 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1682 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1686 bge_sig_pre_reset(struct bge_softc *sc, int type)
1690 * Some chips don't like this so only do this if ASF is enabled
1692 if (sc->bge_asf_mode)
1693 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
1695 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1697 case BGE_RESET_START:
1698 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1699 BGE_FW_DRV_STATE_START);
1701 case BGE_RESET_SHUTDOWN:
1702 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1703 BGE_FW_DRV_STATE_UNLOAD);
1705 case BGE_RESET_SUSPEND:
1706 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1707 BGE_FW_DRV_STATE_SUSPEND);
1712 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
1713 bge_ape_driver_state_change(sc, type);
1717 bge_sig_post_reset(struct bge_softc *sc, int type)
1720 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1722 case BGE_RESET_START:
1723 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1724 BGE_FW_DRV_STATE_START_DONE);
1727 case BGE_RESET_SHUTDOWN:
1728 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1729 BGE_FW_DRV_STATE_UNLOAD_DONE);
1733 if (type == BGE_RESET_SHUTDOWN)
1734 bge_ape_driver_state_change(sc, type);
1738 bge_sig_legacy(struct bge_softc *sc, int type)
1741 if (sc->bge_asf_mode) {
1743 case BGE_RESET_START:
1744 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1745 BGE_FW_DRV_STATE_START);
1747 case BGE_RESET_SHUTDOWN:
1748 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1749 BGE_FW_DRV_STATE_UNLOAD);
1756 bge_stop_fw(struct bge_softc *sc)
1760 if (sc->bge_asf_mode) {
1761 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
1762 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
1763 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
1765 for (i = 0; i < 100; i++ ) {
1766 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1767 BGE_RX_CPU_DRV_EVENT))
1775 bge_dma_swap_options(struct bge_softc *sc)
1777 uint32_t dma_options;
1779 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
1780 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
1781 #if BYTE_ORDER == BIG_ENDIAN
1782 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
1784 return (dma_options);
1788 * Do endian, PCI and DMA initialization.
1791 bge_chipinit(struct bge_softc *sc)
1793 uint32_t dma_rw_ctl, misc_ctl, mode_ctl;
1797 /* Set endianness before we access any non-PCI registers. */
1798 misc_ctl = BGE_INIT;
1799 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1800 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1801 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1804 * Clear the MAC statistics block in the NIC's
1807 for (i = BGE_STATS_BLOCK;
1808 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1809 BGE_MEMWIN_WRITE(sc, i, 0);
1811 for (i = BGE_STATUS_BLOCK;
1812 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1813 BGE_MEMWIN_WRITE(sc, i, 0);
1815 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1817 * Fix data corruption caused by non-qword write with WB.
1818 * Fix master abort in PCI mode.
1819 * Fix PCI latency timer.
1821 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1822 val |= (1 << 10) | (1 << 12) | (1 << 13);
1823 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1826 if (sc->bge_asicrev == BGE_ASICREV_BCM57765 ||
1827 sc->bge_asicrev == BGE_ASICREV_BCM57766) {
1829 * For the 57766 and non Ax versions of 57765, bootcode
1830 * needs to setup the PCIE Fast Training Sequence (FTS)
1831 * value to prevent transmit hangs.
1833 if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) {
1834 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL,
1835 CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) |
1836 BGE_CPMU_PADRNG_CTL_RDIV2);
1841 * Set up the PCI DMA control register.
1843 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1844 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1845 if (sc->bge_flags & BGE_FLAG_PCIE) {
1846 if (sc->bge_mps >= 256)
1847 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1849 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1850 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1851 if (BGE_IS_5714_FAMILY(sc)) {
1852 /* 256 bytes for read and write. */
1853 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1854 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1855 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1856 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1857 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1858 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1860 * In the BCM5703, the DMA read watermark should
1861 * be set to less than or equal to the maximum
1862 * memory read byte count of the PCI-X command
1865 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1866 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1867 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1868 /* 1536 bytes for read, 384 bytes for write. */
1869 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1870 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1872 /* 384 bytes for read and write. */
1873 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1874 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1877 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1878 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1881 /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1882 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1883 if (tmp == 6 || tmp == 7)
1885 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1887 /* Set PCI-X DMA write workaround. */
1888 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1891 /* Conventional PCI bus: 256 bytes for read and write. */
1892 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1893 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1895 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1896 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1899 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1900 sc->bge_asicrev == BGE_ASICREV_BCM5701)
1901 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1902 BGE_PCIDMARWCTL_ASRT_ALL_BE;
1903 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1904 sc->bge_asicrev == BGE_ASICREV_BCM5704)
1905 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1906 if (BGE_IS_5717_PLUS(sc)) {
1907 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1908 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
1909 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1911 * Enable HW workaround for controllers that misinterpret
1912 * a status tag update and leave interrupts permanently
1915 if (!BGE_IS_57765_PLUS(sc) &&
1916 sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
1917 sc->bge_asicrev != BGE_ASICREV_BCM5762)
1918 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1920 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1923 * Set up general mode register.
1925 mode_ctl = bge_dma_swap_options(sc);
1926 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
1927 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
1928 /* Retain Host-2-BMC settings written by APE firmware. */
1929 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
1930 (BGE_MODECTL_BYTESWAP_B2HRX_DATA |
1931 BGE_MODECTL_WORDSWAP_B2HRX_DATA |
1932 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE);
1934 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1935 BGE_MODECTL_TX_NO_PHDR_CSUM;
1938 * BCM5701 B5 have a bug causing data corruption when using
1939 * 64-bit DMA reads, which can be terminated early and then
1940 * completed later as 32-bit accesses, in combination with
1943 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1944 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1945 mode_ctl |= BGE_MODECTL_FORCE_PCI32;
1948 * Tell the firmware the driver is running
1950 if (sc->bge_asf_mode & ASF_STACKUP)
1951 mode_ctl |= BGE_MODECTL_STACKUP;
1953 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1956 * Disable memory write invalidate. Apparently it is not supported
1957 * properly by these devices.
1959 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1961 /* Set the timer prescaler (always 66 MHz). */
1962 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1964 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1965 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1966 DELAY(40); /* XXX */
1968 /* Put PHY into ready state */
1969 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1970 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1978 bge_blockinit(struct bge_softc *sc)
1980 struct bge_rcb *rcb;
1983 uint32_t dmactl, rdmareg, val;
1987 * Initialize the memory window pointer register so that
1988 * we can access the first 32K of internal NIC RAM. This will
1989 * allow us to set up the TX send ring RCBs and the RX return
1990 * ring RCBs, plus other things which live in NIC memory.
1992 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1994 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1996 if (!(BGE_IS_5705_PLUS(sc))) {
1997 /* Configure mbuf memory pool */
1998 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1999 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
2000 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
2002 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
2004 /* Configure DMA resource pool */
2005 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
2006 BGE_DMA_DESCRIPTORS);
2007 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
2010 /* Configure mbuf pool watermarks */
2011 if (BGE_IS_5717_PLUS(sc)) {
2012 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2013 if (if_getmtu(sc->bge_ifp) > ETHERMTU) {
2014 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
2015 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
2017 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
2018 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
2020 } else if (!BGE_IS_5705_PLUS(sc)) {
2021 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
2022 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
2023 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2024 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2025 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2026 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
2027 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
2029 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2030 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
2031 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2034 /* Configure DMA resource watermarks */
2035 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
2036 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
2038 /* Enable buffer manager */
2039 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
2041 * Change the arbitration algorithm of TXMBUF read request to
2042 * round-robin instead of priority based for BCM5719. When
2043 * TXFIFO is almost empty, RDMA will hold its request until
2044 * TXFIFO is not almost empty.
2046 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2047 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
2048 CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
2050 /* Poll for buffer manager start indication */
2051 for (i = 0; i < BGE_TIMEOUT; i++) {
2053 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
2057 if (i == BGE_TIMEOUT) {
2058 device_printf(sc->bge_dev, "buffer manager failed to start\n");
2062 /* Enable flow-through queues */
2063 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2064 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2066 /* Wait until queue initialization is complete */
2067 for (i = 0; i < BGE_TIMEOUT; i++) {
2069 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
2073 if (i == BGE_TIMEOUT) {
2074 device_printf(sc->bge_dev, "flow-through queue init failed\n");
2079 * Summary of rings supported by the controller:
2081 * Standard Receive Producer Ring
2082 * - This ring is used to feed receive buffers for "standard"
2083 * sized frames (typically 1536 bytes) to the controller.
2085 * Jumbo Receive Producer Ring
2086 * - This ring is used to feed receive buffers for jumbo sized
2087 * frames (i.e. anything bigger than the "standard" frames)
2088 * to the controller.
2090 * Mini Receive Producer Ring
2091 * - This ring is used to feed receive buffers for "mini"
2092 * sized frames to the controller.
2093 * - This feature required external memory for the controller
2094 * but was never used in a production system. Should always
2097 * Receive Return Ring
2098 * - After the controller has placed an incoming frame into a
2099 * receive buffer that buffer is moved into a receive return
2100 * ring. The driver is then responsible to passing the
2101 * buffer up to the stack. Many versions of the controller
2102 * support multiple RR rings.
2105 * - This ring is used for outgoing frames. Many versions of
2106 * the controller support multiple send rings.
2109 /* Initialize the standard receive producer ring control block. */
2110 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
2111 rcb->bge_hostaddr.bge_addr_lo =
2112 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
2113 rcb->bge_hostaddr.bge_addr_hi =
2114 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
2115 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2116 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
2117 if (BGE_IS_5717_PLUS(sc)) {
2119 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
2120 * Bits 15-2 : Maximum RX frame size
2121 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled
2124 rcb->bge_maxlen_flags =
2125 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
2126 } else if (BGE_IS_5705_PLUS(sc)) {
2128 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
2129 * Bits 15-2 : Reserved (should be 0)
2130 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
2133 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
2136 * Ring size is always XXX entries
2137 * Bits 31-16: Maximum RX frame size
2138 * Bits 15-2 : Reserved (should be 0)
2139 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
2142 rcb->bge_maxlen_flags =
2143 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
2145 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2146 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2147 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2148 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
2150 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
2151 /* Write the standard receive producer ring control block. */
2152 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
2153 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
2154 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
2155 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
2157 /* Reset the standard receive producer ring producer index. */
2158 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
2161 * Initialize the jumbo RX producer ring control
2162 * block. We set the 'ring disabled' bit in the
2163 * flags field until we're actually ready to start
2164 * using this ring (i.e. once we set the MTU
2165 * high enough to require it).
2167 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2168 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
2169 /* Get the jumbo receive producer ring RCB parameters. */
2170 rcb->bge_hostaddr.bge_addr_lo =
2171 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2172 rcb->bge_hostaddr.bge_addr_hi =
2173 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2174 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2175 sc->bge_cdata.bge_rx_jumbo_ring_map,
2176 BUS_DMASYNC_PREREAD);
2177 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
2178 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
2179 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2180 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2181 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2182 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
2184 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
2185 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
2186 rcb->bge_hostaddr.bge_addr_hi);
2187 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
2188 rcb->bge_hostaddr.bge_addr_lo);
2189 /* Program the jumbo receive producer ring RCB parameters. */
2190 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
2191 rcb->bge_maxlen_flags);
2192 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
2193 /* Reset the jumbo receive producer ring producer index. */
2194 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
2197 /* Disable the mini receive producer ring RCB. */
2198 if (BGE_IS_5700_FAMILY(sc)) {
2199 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
2200 rcb->bge_maxlen_flags =
2201 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
2202 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
2203 rcb->bge_maxlen_flags);
2204 /* Reset the mini receive producer ring producer index. */
2205 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
2208 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
2209 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2210 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
2211 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
2212 sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
2213 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
2214 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
2217 * The BD ring replenish thresholds control how often the
2218 * hardware fetches new BD's from the producer rings in host
2219 * memory. Setting the value too low on a busy system can
2220 * starve the hardware and recue the throughpout.
2222 * Set the BD ring replentish thresholds. The recommended
2223 * values are 1/8th the number of descriptors allocated to
2225 * XXX The 5754 requires a lower threshold, so it might be a
2226 * requirement of all 575x family chips. The Linux driver sets
2227 * the lower threshold for all 5705 family chips as well, but there
2228 * are reports that it might not need to be so strict.
2230 * XXX Linux does some extra fiddling here for the 5906 parts as
2233 if (BGE_IS_5705_PLUS(sc))
2236 val = BGE_STD_RX_RING_CNT / 8;
2237 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
2238 if (BGE_IS_JUMBO_CAPABLE(sc))
2239 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
2240 BGE_JUMBO_RX_RING_CNT/8);
2241 if (BGE_IS_5717_PLUS(sc)) {
2242 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
2243 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
2247 * Disable all send rings by setting the 'ring disabled' bit
2248 * in the flags field of all the TX send ring control blocks,
2249 * located in NIC memory.
2251 if (!BGE_IS_5705_PLUS(sc))
2252 /* 5700 to 5704 had 16 send rings. */
2253 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
2254 else if (BGE_IS_57765_PLUS(sc) ||
2255 sc->bge_asicrev == BGE_ASICREV_BCM5762)
2257 else if (BGE_IS_5717_PLUS(sc))
2261 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2262 for (i = 0; i < limit; i++) {
2263 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2264 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
2265 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2266 vrcb += sizeof(struct bge_rcb);
2269 /* Configure send ring RCB 0 (we use only the first ring) */
2270 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2271 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
2272 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2273 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2274 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2275 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2276 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2277 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
2279 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
2280 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
2281 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2282 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
2285 * Disable all receive return rings by setting the
2286 * 'ring diabled' bit in the flags field of all the receive
2287 * return ring control blocks, located in NIC memory.
2289 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2290 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2291 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2292 /* Should be 17, use 16 until we get an SRAM map. */
2294 } else if (!BGE_IS_5705_PLUS(sc))
2295 limit = BGE_RX_RINGS_MAX;
2296 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2297 sc->bge_asicrev == BGE_ASICREV_BCM5762 ||
2298 BGE_IS_57765_PLUS(sc))
2302 /* Disable all receive return rings. */
2303 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2304 for (i = 0; i < limit; i++) {
2305 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
2306 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
2307 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2308 BGE_RCB_FLAG_RING_DISABLED);
2309 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2310 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
2311 (i * (sizeof(uint64_t))), 0);
2312 vrcb += sizeof(struct bge_rcb);
2316 * Set up receive return ring 0. Note that the NIC address
2317 * for RX return rings is 0x0. The return rings live entirely
2318 * within the host, so the nicaddr field in the RCB isn't used.
2320 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2321 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
2322 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2323 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2324 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2325 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2326 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
2328 /* Set random backoff seed for TX */
2329 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
2330 (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
2331 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
2332 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) &
2333 BGE_TX_BACKOFF_SEED_MASK);
2335 /* Set inter-packet gap */
2337 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2338 sc->bge_asicrev == BGE_ASICREV_BCM5762)
2339 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
2340 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
2341 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
2344 * Specify which ring to use for packets that don't match
2347 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
2350 * Configure number of RX lists. One interrupt distribution
2351 * list, sixteen active lists, one bad frames class.
2353 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
2355 /* Inialize RX list placement stats mask. */
2356 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
2357 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
2359 /* Disable host coalescing until we get it set up */
2360 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
2362 /* Poll to make sure it's shut down. */
2363 for (i = 0; i < BGE_TIMEOUT; i++) {
2365 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
2369 if (i == BGE_TIMEOUT) {
2370 device_printf(sc->bge_dev,
2371 "host coalescing engine failed to idle\n");
2375 /* Set up host coalescing defaults */
2376 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
2377 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
2378 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
2379 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
2380 if (!(BGE_IS_5705_PLUS(sc))) {
2381 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
2382 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
2384 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
2385 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
2387 /* Set up address of statistics block */
2388 if (!(BGE_IS_5705_PLUS(sc))) {
2389 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
2390 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
2391 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
2392 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
2393 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
2394 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
2395 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
2398 /* Set up address of status block */
2399 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
2400 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
2401 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
2402 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
2404 /* Set up status block size. */
2405 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2406 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
2407 val = BGE_STATBLKSZ_FULL;
2408 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2410 val = BGE_STATBLKSZ_32BYTE;
2411 bzero(sc->bge_ldata.bge_status_block, 32);
2413 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2414 sc->bge_cdata.bge_status_map,
2415 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2417 /* Turn on host coalescing state machine */
2418 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2420 /* Turn on RX BD completion state machine and enable attentions */
2421 CSR_WRITE_4(sc, BGE_RBDC_MODE,
2422 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
2424 /* Turn on RX list placement state machine */
2425 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2427 /* Turn on RX list selector state machine. */
2428 if (!(BGE_IS_5705_PLUS(sc)))
2429 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2431 /* Turn on DMA, clear stats. */
2432 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
2433 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
2434 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
2435 BGE_MACMODE_FRMHDR_DMA_ENB;
2437 if (sc->bge_flags & BGE_FLAG_TBI)
2438 val |= BGE_PORTMODE_TBI;
2439 else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
2440 val |= BGE_PORTMODE_GMII;
2442 val |= BGE_PORTMODE_MII;
2444 /* Allow APE to send/receive frames. */
2445 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
2446 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
2448 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
2451 /* Set misc. local control, enable interrupts on attentions */
2452 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2455 /* Assert GPIO pins for PHY reset */
2456 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
2457 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
2458 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
2459 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
2462 /* Turn on DMA completion state machine */
2463 if (!(BGE_IS_5705_PLUS(sc)))
2464 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2466 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
2468 /* Enable host coalescing bug fix. */
2469 if (BGE_IS_5755_PLUS(sc))
2470 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
2472 /* Request larger DMA burst size to get better performance. */
2473 if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
2474 val |= BGE_WDMAMODE_BURST_ALL_DATA;
2476 /* Turn on write DMA state machine */
2477 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
2480 /* Turn on read DMA state machine */
2481 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
2483 if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
2484 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
2486 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2487 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2488 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2489 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
2490 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
2491 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
2492 if (sc->bge_flags & BGE_FLAG_PCIE)
2493 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2494 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2495 val |= BGE_RDMAMODE_TSO4_ENABLE;
2496 if (sc->bge_flags & BGE_FLAG_TSO3 ||
2497 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2498 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2499 val |= BGE_RDMAMODE_TSO6_ENABLE;
2502 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2503 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2504 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
2505 BGE_RDMAMODE_H2BNC_VLAN_DET;
2507 * Allow multiple outstanding read requests from
2508 * non-LSO read DMA engine.
2510 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
2513 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2514 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2515 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2516 sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2517 BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) {
2518 if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
2519 rdmareg = BGE_RDMA_RSRVCTRL_REG2;
2521 rdmareg = BGE_RDMA_RSRVCTRL;
2522 dmactl = CSR_READ_4(sc, rdmareg);
2524 * Adjust tx margin to prevent TX data corruption and
2525 * fix internal FIFO overflow.
2527 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 ||
2528 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2529 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2530 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2531 BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2532 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2533 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2534 BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2537 * Enable fix for read DMA FIFO overruns.
2538 * The fix is to limit the number of RX BDs
2539 * the hardware would fetch at a fime.
2541 CSR_WRITE_4(sc, rdmareg, dmactl |
2542 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2545 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2546 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2547 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2548 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2549 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2550 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2552 * Allow 4KB burst length reads for non-LSO frames.
2553 * Enable 512B burst length reads for buffer descriptors.
2555 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2556 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2557 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
2558 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2559 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2560 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2,
2561 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |
2562 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2563 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2566 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2569 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
2570 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) {
2571 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);
2572 if ((val & 0xFFFF) > BGE_FRAMELEN)
2574 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN)
2577 if (i != BGE_NUM_RDMA_CHANNELS / 2) {
2578 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
2579 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2580 val |= BGE_RDMA_TX_LENGTH_WA_5719;
2582 val |= BGE_RDMA_TX_LENGTH_WA_5720;
2583 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
2587 /* Turn on RX data completion state machine */
2588 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2590 /* Turn on RX BD initiator state machine */
2591 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2593 /* Turn on RX data and RX BD initiator state machine */
2594 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2596 /* Turn on Mbuf cluster free state machine */
2597 if (!(BGE_IS_5705_PLUS(sc)))
2598 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2600 /* Turn on send BD completion state machine */
2601 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2603 /* Turn on send data completion state machine */
2604 val = BGE_SDCMODE_ENABLE;
2605 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2606 val |= BGE_SDCMODE_CDELAY;
2607 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2609 /* Turn on send data initiator state machine */
2610 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2611 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2612 BGE_SDIMODE_HW_LSO_PRE_DMA);
2614 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2616 /* Turn on send BD initiator state machine */
2617 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2619 /* Turn on send BD selector state machine */
2620 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2622 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
2623 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
2624 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
2626 /* ack/clear link change events */
2627 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2628 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2629 BGE_MACSTAT_LINK_CHANGED);
2630 CSR_WRITE_4(sc, BGE_MI_STS, 0);
2633 * Enable attention when the link has changed state for
2634 * devices that use auto polling.
2636 if (sc->bge_flags & BGE_FLAG_TBI) {
2637 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
2639 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2640 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
2643 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2644 sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
2645 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2646 BGE_EVTENB_MI_INTERRUPT);
2650 * Clear any pending link state attention.
2651 * Otherwise some link state change events may be lost until attention
2652 * is cleared by bge_intr() -> bge_link_upd() sequence.
2653 * It's not necessary on newer BCM chips - perhaps enabling link
2654 * state change attentions implies clearing pending attention.
2656 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2657 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2658 BGE_MACSTAT_LINK_CHANGED);
2660 /* Enable link state change attentions. */
2661 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2666 static const struct bge_revision *
2667 bge_lookup_rev(uint32_t chipid)
2669 const struct bge_revision *br;
2671 for (br = bge_revisions; br->br_name != NULL; br++) {
2672 if (br->br_chipid == chipid)
2676 for (br = bge_majorrevs; br->br_name != NULL; br++) {
2677 if (br->br_chipid == BGE_ASICREV(chipid))
2684 static const struct bge_vendor *
2685 bge_lookup_vendor(uint16_t vid)
2687 const struct bge_vendor *v;
2689 for (v = bge_vendors; v->v_name != NULL; v++)
2697 bge_chipid(device_t dev)
2701 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2702 BGE_PCIMISCCTL_ASICREV_SHIFT;
2703 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
2705 * Find the ASCI revision. Different chips use different
2708 switch (pci_get_device(dev)) {
2709 case BCOM_DEVICEID_BCM5717C:
2710 /* 5717 C0 seems to belong to 5720 line. */
2711 id = BGE_CHIPID_BCM5720_A0;
2713 case BCOM_DEVICEID_BCM5717:
2714 case BCOM_DEVICEID_BCM5718:
2715 case BCOM_DEVICEID_BCM5719:
2716 case BCOM_DEVICEID_BCM5720:
2717 case BCOM_DEVICEID_BCM5725:
2718 case BCOM_DEVICEID_BCM5727:
2719 case BCOM_DEVICEID_BCM5762:
2720 case BCOM_DEVICEID_BCM57764:
2721 case BCOM_DEVICEID_BCM57767:
2722 case BCOM_DEVICEID_BCM57787:
2723 id = pci_read_config(dev,
2724 BGE_PCI_GEN2_PRODID_ASICREV, 4);
2726 case BCOM_DEVICEID_BCM57761:
2727 case BCOM_DEVICEID_BCM57762:
2728 case BCOM_DEVICEID_BCM57765:
2729 case BCOM_DEVICEID_BCM57766:
2730 case BCOM_DEVICEID_BCM57781:
2731 case BCOM_DEVICEID_BCM57782:
2732 case BCOM_DEVICEID_BCM57785:
2733 case BCOM_DEVICEID_BCM57786:
2734 case BCOM_DEVICEID_BCM57791:
2735 case BCOM_DEVICEID_BCM57795:
2736 id = pci_read_config(dev,
2737 BGE_PCI_GEN15_PRODID_ASICREV, 4);
2740 id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
2747 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
2748 * against our list and return its name if we find a match.
2750 * Note that since the Broadcom controller contains VPD support, we
2751 * try to get the device name string from the controller itself instead
2752 * of the compiled-in string. It guarantees we'll always announce the
2753 * right product name. We fall back to the compiled-in string when
2754 * VPD is unavailable or corrupt.
2757 bge_probe(device_t dev)
2761 const struct bge_revision *br;
2763 struct bge_softc *sc;
2764 const struct bge_type *t = bge_devs;
2765 const struct bge_vendor *v;
2769 sc = device_get_softc(dev);
2771 vid = pci_get_vendor(dev);
2772 did = pci_get_device(dev);
2773 while(t->bge_vid != 0) {
2774 if ((vid == t->bge_vid) && (did == t->bge_did)) {
2775 id = bge_chipid(dev);
2776 br = bge_lookup_rev(id);
2777 if (bge_has_eaddr(sc) &&
2778 pci_get_vpd_ident(dev, &pname) == 0)
2779 snprintf(model, sizeof(model), "%s", pname);
2781 v = bge_lookup_vendor(vid);
2782 snprintf(model, sizeof(model), "%s %s",
2783 v != NULL ? v->v_name : "Unknown",
2784 br != NULL ? br->br_name :
2785 "NetXtreme/NetLink Ethernet Controller");
2787 snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x",
2788 model, br != NULL ? "" : "unknown ", id);
2789 device_set_desc_copy(dev, buf);
2790 return (BUS_PROBE_DEFAULT);
2799 bge_dma_free(struct bge_softc *sc)
2803 /* Destroy DMA maps for RX buffers. */
2804 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2805 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2806 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2807 sc->bge_cdata.bge_rx_std_dmamap[i]);
2809 if (sc->bge_cdata.bge_rx_std_sparemap)
2810 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2811 sc->bge_cdata.bge_rx_std_sparemap);
2813 /* Destroy DMA maps for jumbo RX buffers. */
2814 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2815 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2816 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2817 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2819 if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2820 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2821 sc->bge_cdata.bge_rx_jumbo_sparemap);
2823 /* Destroy DMA maps for TX buffers. */
2824 for (i = 0; i < BGE_TX_RING_CNT; i++) {
2825 if (sc->bge_cdata.bge_tx_dmamap[i])
2826 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2827 sc->bge_cdata.bge_tx_dmamap[i]);
2830 if (sc->bge_cdata.bge_rx_mtag)
2831 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2832 if (sc->bge_cdata.bge_mtag_jumbo)
2833 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
2834 if (sc->bge_cdata.bge_tx_mtag)
2835 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2837 /* Destroy standard RX ring. */
2838 if (sc->bge_ldata.bge_rx_std_ring_paddr)
2839 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2840 sc->bge_cdata.bge_rx_std_ring_map);
2841 if (sc->bge_ldata.bge_rx_std_ring)
2842 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2843 sc->bge_ldata.bge_rx_std_ring,
2844 sc->bge_cdata.bge_rx_std_ring_map);
2846 if (sc->bge_cdata.bge_rx_std_ring_tag)
2847 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2849 /* Destroy jumbo RX ring. */
2850 if (sc->bge_ldata.bge_rx_jumbo_ring_paddr)
2851 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2852 sc->bge_cdata.bge_rx_jumbo_ring_map);
2854 if (sc->bge_ldata.bge_rx_jumbo_ring)
2855 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2856 sc->bge_ldata.bge_rx_jumbo_ring,
2857 sc->bge_cdata.bge_rx_jumbo_ring_map);
2859 if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2860 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2862 /* Destroy RX return ring. */
2863 if (sc->bge_ldata.bge_rx_return_ring_paddr)
2864 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2865 sc->bge_cdata.bge_rx_return_ring_map);
2867 if (sc->bge_ldata.bge_rx_return_ring)
2868 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2869 sc->bge_ldata.bge_rx_return_ring,
2870 sc->bge_cdata.bge_rx_return_ring_map);
2872 if (sc->bge_cdata.bge_rx_return_ring_tag)
2873 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2875 /* Destroy TX ring. */
2876 if (sc->bge_ldata.bge_tx_ring_paddr)
2877 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2878 sc->bge_cdata.bge_tx_ring_map);
2880 if (sc->bge_ldata.bge_tx_ring)
2881 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2882 sc->bge_ldata.bge_tx_ring,
2883 sc->bge_cdata.bge_tx_ring_map);
2885 if (sc->bge_cdata.bge_tx_ring_tag)
2886 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2888 /* Destroy status block. */
2889 if (sc->bge_ldata.bge_status_block_paddr)
2890 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2891 sc->bge_cdata.bge_status_map);
2893 if (sc->bge_ldata.bge_status_block)
2894 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2895 sc->bge_ldata.bge_status_block,
2896 sc->bge_cdata.bge_status_map);
2898 if (sc->bge_cdata.bge_status_tag)
2899 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2901 /* Destroy statistics block. */
2902 if (sc->bge_ldata.bge_stats_paddr)
2903 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2904 sc->bge_cdata.bge_stats_map);
2906 if (sc->bge_ldata.bge_stats)
2907 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2908 sc->bge_ldata.bge_stats,
2909 sc->bge_cdata.bge_stats_map);
2911 if (sc->bge_cdata.bge_stats_tag)
2912 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2914 if (sc->bge_cdata.bge_buffer_tag)
2915 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
2917 /* Destroy the parent tag. */
2918 if (sc->bge_cdata.bge_parent_tag)
2919 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2923 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
2924 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
2925 bus_addr_t *paddr, const char *msg)
2927 struct bge_dmamap_arg ctx;
2930 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2931 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2932 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
2934 device_printf(sc->bge_dev,
2935 "could not create %s dma tag\n", msg);
2938 /* Allocate DMA'able memory for ring. */
2939 error = bus_dmamem_alloc(*tag, (void **)ring,
2940 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
2942 device_printf(sc->bge_dev,
2943 "could not allocate DMA'able memory for %s\n", msg);
2946 /* Load the address of the ring. */
2947 ctx.bge_busaddr = 0;
2948 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr,
2949 &ctx, BUS_DMA_NOWAIT);
2951 device_printf(sc->bge_dev,
2952 "could not load DMA'able memory for %s\n", msg);
2955 *paddr = ctx.bge_busaddr;
2960 bge_dma_alloc(struct bge_softc *sc)
2963 bus_size_t rxmaxsegsz, sbsz, txsegsz, txmaxsegsz;
2966 lowaddr = BUS_SPACE_MAXADDR;
2967 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2968 lowaddr = BGE_DMA_MAXADDR;
2970 * Allocate the parent bus DMA tag appropriate for PCI.
2972 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2973 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2974 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2975 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2977 device_printf(sc->bge_dev,
2978 "could not allocate parent dma tag\n");
2982 /* Create tag for standard RX ring. */
2983 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
2984 &sc->bge_cdata.bge_rx_std_ring_tag,
2985 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
2986 &sc->bge_cdata.bge_rx_std_ring_map,
2987 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
2991 /* Create tag for RX return ring. */
2992 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
2993 &sc->bge_cdata.bge_rx_return_ring_tag,
2994 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
2995 &sc->bge_cdata.bge_rx_return_ring_map,
2996 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
3000 /* Create tag for TX ring. */
3001 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
3002 &sc->bge_cdata.bge_tx_ring_tag,
3003 (uint8_t **)&sc->bge_ldata.bge_tx_ring,
3004 &sc->bge_cdata.bge_tx_ring_map,
3005 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
3010 * Create tag for status block.
3011 * Because we only use single Tx/Rx/Rx return ring, use
3012 * minimum status block size except BCM5700 AX/BX which
3013 * seems to want to see full status block size regardless
3014 * of configured number of ring.
3016 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3017 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
3018 sbsz = BGE_STATUS_BLK_SZ;
3021 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
3022 &sc->bge_cdata.bge_status_tag,
3023 (uint8_t **)&sc->bge_ldata.bge_status_block,
3024 &sc->bge_cdata.bge_status_map,
3025 &sc->bge_ldata.bge_status_block_paddr, "status block");
3029 /* Create tag for statistics block. */
3030 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
3031 &sc->bge_cdata.bge_stats_tag,
3032 (uint8_t **)&sc->bge_ldata.bge_stats,
3033 &sc->bge_cdata.bge_stats_map,
3034 &sc->bge_ldata.bge_stats_paddr, "statistics block");
3038 /* Create tag for jumbo RX ring. */
3039 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3040 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
3041 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
3042 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
3043 &sc->bge_cdata.bge_rx_jumbo_ring_map,
3044 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
3049 /* Create parent tag for buffers. */
3050 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
3053 * watchdog timeout issue was observed on BCM5704 which
3054 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge).
3055 * Both limiting DMA address space to 32bits and flushing
3056 * mailbox write seem to address the issue.
3058 if (sc->bge_pcixcap != 0)
3059 lowaddr = BUS_SPACE_MAXADDR_32BIT;
3061 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 1, 0, lowaddr,
3062 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0,
3063 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
3064 &sc->bge_cdata.bge_buffer_tag);
3066 device_printf(sc->bge_dev,
3067 "could not allocate buffer dma tag\n");
3070 /* Create tag for Tx mbufs. */
3071 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
3072 txsegsz = BGE_TSOSEG_SZ;
3073 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
3076 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
3078 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
3079 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
3080 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
3081 &sc->bge_cdata.bge_tx_mtag);
3084 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
3088 /* Create tag for Rx mbufs. */
3089 if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
3090 rxmaxsegsz = MJUM9BYTES;
3092 rxmaxsegsz = MCLBYTES;
3093 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
3094 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1,
3095 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
3098 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
3102 /* Create DMA maps for RX buffers. */
3103 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3104 &sc->bge_cdata.bge_rx_std_sparemap);
3106 device_printf(sc->bge_dev,
3107 "can't create spare DMA map for RX\n");
3110 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3111 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3112 &sc->bge_cdata.bge_rx_std_dmamap[i]);
3114 device_printf(sc->bge_dev,
3115 "can't create DMA map for RX\n");
3120 /* Create DMA maps for TX buffers. */
3121 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3122 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
3123 &sc->bge_cdata.bge_tx_dmamap[i]);
3125 device_printf(sc->bge_dev,
3126 "can't create DMA map for TX\n");
3131 /* Create tags for jumbo RX buffers. */
3132 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3133 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
3134 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
3135 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
3136 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
3138 device_printf(sc->bge_dev,
3139 "could not allocate jumbo dma tag\n");
3142 /* Create DMA maps for jumbo RX buffers. */
3143 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3144 0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
3146 device_printf(sc->bge_dev,
3147 "can't create spare DMA map for jumbo RX\n");
3150 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
3151 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3152 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
3154 device_printf(sc->bge_dev,
3155 "can't create DMA map for jumbo RX\n");
3165 * Return true if this device has more than one port.
3168 bge_has_multiple_ports(struct bge_softc *sc)
3170 device_t dev = sc->bge_dev;
3171 u_int b, d, f, fscan, s;
3173 d = pci_get_domain(dev);
3174 b = pci_get_bus(dev);
3175 s = pci_get_slot(dev);
3176 f = pci_get_function(dev);
3177 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
3178 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
3184 * Return true if MSI can be used with this device.
3187 bge_can_use_msi(struct bge_softc *sc)
3189 int can_use_msi = 0;
3191 if (sc->bge_msi == 0)
3194 /* Disable MSI for polling(4). */
3195 #ifdef DEVICE_POLLING
3198 switch (sc->bge_asicrev) {
3199 case BGE_ASICREV_BCM5714_A0:
3200 case BGE_ASICREV_BCM5714:
3202 * Apparently, MSI doesn't work when these chips are
3203 * configured in single-port mode.
3205 if (bge_has_multiple_ports(sc))
3208 case BGE_ASICREV_BCM5750:
3209 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
3210 sc->bge_chiprev != BGE_CHIPREV_5750_BX)
3214 if (BGE_IS_575X_PLUS(sc))
3217 return (can_use_msi);
3221 bge_mbox_reorder(struct bge_softc *sc)
3223 /* Lists of PCI bridges that are known to reorder mailbox writes. */
3224 static const struct mbox_reorder {
3225 const uint16_t vendor;
3226 const uint16_t device;
3228 } mbox_reorder_lists[] = {
3229 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" },
3231 devclass_t pci, pcib;
3235 pci = devclass_find("pci");
3236 pcib = devclass_find("pcib");
3238 bus = device_get_parent(dev);
3240 dev = device_get_parent(bus);
3241 bus = device_get_parent(dev);
3242 if (device_get_devclass(dev) != pcib)
3244 for (i = 0; i < nitems(mbox_reorder_lists); i++) {
3245 if (pci_get_vendor(dev) ==
3246 mbox_reorder_lists[i].vendor &&
3247 pci_get_device(dev) ==
3248 mbox_reorder_lists[i].device) {
3249 device_printf(sc->bge_dev,
3250 "enabling MBOX workaround for %s\n",
3251 mbox_reorder_lists[i].desc);
3255 if (device_get_devclass(bus) != pci)
3262 bge_devinfo(struct bge_softc *sc)
3266 device_printf(sc->bge_dev,
3267 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ",
3268 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev);
3269 if (sc->bge_flags & BGE_FLAG_PCIE)
3271 else if (sc->bge_flags & BGE_FLAG_PCIX) {
3273 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3274 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE)
3277 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
3296 printf("%u MHz\n", clk);
3298 if (sc->bge_pcixcap != 0)
3299 printf("PCI on PCI-X ");
3302 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3303 if (cfg & BGE_PCISTATE_PCI_BUSSPEED)
3307 if (cfg & BGE_PCISTATE_32BIT_BUS)
3308 printf("%u MHz; 32bit\n", clk);
3310 printf("%u MHz; 64bit\n", clk);
3315 bge_attach(device_t dev)
3318 struct bge_softc *sc;
3319 uint32_t hwcfg = 0, misccfg, pcistate;
3320 u_char eaddr[ETHER_ADDR_LEN];
3321 int capmask, error, reg, rid, trys;
3323 sc = device_get_softc(dev);
3326 BGE_LOCK_INIT(sc, device_get_nameunit(dev));
3327 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
3328 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
3330 pci_enable_busmaster(dev);
3333 * Allocate control/status registers.
3336 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3339 if (sc->bge_res == NULL) {
3340 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n");
3345 /* Save various chip information. */
3346 sc->bge_func_addr = pci_get_function(dev);
3347 sc->bge_chipid = bge_chipid(dev);
3348 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
3349 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
3351 /* Set default PHY address. */
3352 sc->bge_phy_addr = 1;
3354 * PHY address mapping for various devices.
3356 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
3357 * ---------+-------+-------+-------+-------+
3358 * BCM57XX | 1 | X | X | X |
3359 * BCM5704 | 1 | X | 1 | X |
3360 * BCM5717 | 1 | 8 | 2 | 9 |
3361 * BCM5719 | 1 | 8 | 2 | 9 |
3362 * BCM5720 | 1 | 8 | 2 | 9 |
3364 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr |
3365 * ---------+-------+-------+-------+-------+
3366 * BCM57XX | X | X | X | X |
3367 * BCM5704 | X | X | X | X |
3368 * BCM5717 | X | X | X | X |
3369 * BCM5719 | 3 | 10 | 4 | 11 |
3370 * BCM5720 | X | X | X | X |
3372 * Other addresses may respond but they are not
3373 * IEEE compliant PHYs and should be ignored.
3375 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
3376 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3377 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3378 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) {
3379 if (CSR_READ_4(sc, BGE_SGDIG_STS) &
3380 BGE_SGDIGSTS_IS_SERDES)
3381 sc->bge_phy_addr = sc->bge_func_addr + 8;
3383 sc->bge_phy_addr = sc->bge_func_addr + 1;
3385 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
3386 BGE_CPMU_PHY_STRAP_IS_SERDES)
3387 sc->bge_phy_addr = sc->bge_func_addr + 8;
3389 sc->bge_phy_addr = sc->bge_func_addr + 1;
3393 if (bge_has_eaddr(sc))
3394 sc->bge_flags |= BGE_FLAG_EADDR;
3396 /* Save chipset family. */
3397 switch (sc->bge_asicrev) {
3398 case BGE_ASICREV_BCM5762:
3399 case BGE_ASICREV_BCM57765:
3400 case BGE_ASICREV_BCM57766:
3401 sc->bge_flags |= BGE_FLAG_57765_PLUS;
3403 case BGE_ASICREV_BCM5717:
3404 case BGE_ASICREV_BCM5719:
3405 case BGE_ASICREV_BCM5720:
3406 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
3407 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
3408 BGE_FLAG_JUMBO_FRAME;
3409 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3410 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3412 * Enable work around for DMA engine miscalculation
3413 * of TXMBUF available space.
3415 sc->bge_flags |= BGE_FLAG_RDMA_BUG;
3416 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3417 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3418 /* Jumbo frame on BCM5719 A0 does not work. */
3419 sc->bge_flags &= ~BGE_FLAG_JUMBO;
3423 case BGE_ASICREV_BCM5755:
3424 case BGE_ASICREV_BCM5761:
3425 case BGE_ASICREV_BCM5784:
3426 case BGE_ASICREV_BCM5785:
3427 case BGE_ASICREV_BCM5787:
3428 case BGE_ASICREV_BCM57780:
3429 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
3432 case BGE_ASICREV_BCM5700:
3433 case BGE_ASICREV_BCM5701:
3434 case BGE_ASICREV_BCM5703:
3435 case BGE_ASICREV_BCM5704:
3436 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
3438 case BGE_ASICREV_BCM5714_A0:
3439 case BGE_ASICREV_BCM5780:
3440 case BGE_ASICREV_BCM5714:
3441 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
3443 case BGE_ASICREV_BCM5750:
3444 case BGE_ASICREV_BCM5752:
3445 case BGE_ASICREV_BCM5906:
3446 sc->bge_flags |= BGE_FLAG_575X_PLUS;
3448 case BGE_ASICREV_BCM5705:
3449 sc->bge_flags |= BGE_FLAG_5705_PLUS;
3453 /* Identify chips with APE processor. */
3454 switch (sc->bge_asicrev) {
3455 case BGE_ASICREV_BCM5717:
3456 case BGE_ASICREV_BCM5719:
3457 case BGE_ASICREV_BCM5720:
3458 case BGE_ASICREV_BCM5761:
3459 case BGE_ASICREV_BCM5762:
3460 sc->bge_flags |= BGE_FLAG_APE;
3464 /* Chips with APE need BAR2 access for APE registers/memory. */
3465 if ((sc->bge_flags & BGE_FLAG_APE) != 0) {
3467 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3469 if (sc->bge_res2 == NULL) {
3470 device_printf (sc->bge_dev,
3471 "couldn't map BAR2 memory\n");
3476 /* Enable APE register/memory access by host driver. */
3477 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3478 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
3479 BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
3480 BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
3481 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4);
3483 bge_ape_lock_init(sc);
3484 bge_ape_read_fw_ver(sc);
3487 /* Add SYSCTLs, requires the chipset family to be set. */
3488 bge_add_sysctls(sc);
3490 /* Identify the chips that use an CPMU. */
3491 if (BGE_IS_5717_PLUS(sc) ||
3492 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3493 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3494 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
3495 sc->bge_asicrev == BGE_ASICREV_BCM57780)
3496 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
3497 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
3498 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
3500 sc->bge_mi_mode = BGE_MIMODE_BASE;
3501 /* Enable auto polling for BCM570[0-5]. */
3502 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
3503 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
3506 * All Broadcom controllers have 4GB boundary DMA bug.
3507 * Whenever an address crosses a multiple of the 4GB boundary
3508 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3509 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3510 * state machine will lockup and cause the device to hang.
3512 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
3514 /* BCM5755 or higher and BCM5906 have short DMA bug. */
3515 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3516 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
3519 * BCM5719 cannot handle DMA requests for DMA segments that
3520 * have larger than 4KB in size. However the maximum DMA
3521 * segment size created in DMA tag is 4KB for TSO, so we
3522 * wouldn't encounter the issue here.
3524 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
3525 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG;
3527 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3528 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
3529 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
3530 misccfg == BGE_MISCCFG_BOARD_ID_5788M)
3531 sc->bge_flags |= BGE_FLAG_5788;
3534 capmask = BMSR_DEFCAPMASK;
3535 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
3536 (misccfg == 0x4000 || misccfg == 0x8000)) ||
3537 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3538 pci_get_vendor(dev) == BCOM_VENDORID &&
3539 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 ||
3540 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 ||
3541 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) ||
3542 (pci_get_vendor(dev) == BCOM_VENDORID &&
3543 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F ||
3544 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F ||
3545 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) ||
3546 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 ||
3547 pci_get_device(dev) == BCOM_DEVICEID_BCM57791 ||
3548 pci_get_device(dev) == BCOM_DEVICEID_BCM57795 ||
3549 sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3550 /* These chips are 10/100 only. */
3551 capmask &= ~BMSR_EXTSTAT;
3552 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3556 * Some controllers seem to require a special firmware to use
3557 * TSO. But the firmware is not available to FreeBSD and Linux
3558 * claims that the TSO performed by the firmware is slower than
3559 * hardware based TSO. Moreover the firmware based TSO has one
3560 * known bug which can't handle TSO if Ethernet header + IP/TCP
3561 * header is greater than 80 bytes. A workaround for the TSO
3562 * bug exist but it seems it's too expensive than not using
3563 * TSO at all. Some hardwares also have the TSO bug so limit
3564 * the TSO to the controllers that are not affected TSO issues
3565 * (e.g. 5755 or higher).
3567 if (BGE_IS_5717_PLUS(sc)) {
3568 /* BCM5717 requires different TSO configuration. */
3569 sc->bge_flags |= BGE_FLAG_TSO3;
3570 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3571 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3572 /* TSO on BCM5719 A0 does not work. */
3573 sc->bge_flags &= ~BGE_FLAG_TSO3;
3575 } else if (BGE_IS_5755_PLUS(sc)) {
3577 * BCM5754 and BCM5787 shares the same ASIC id so
3578 * explicit device id check is required.
3579 * Due to unknown reason TSO does not work on BCM5755M.
3581 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
3582 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
3583 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
3584 sc->bge_flags |= BGE_FLAG_TSO;
3588 * Check if this is a PCI-X or PCI Express device.
3590 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
3592 * Found a PCI Express capabilities register, this
3593 * must be a PCI Express device.
3595 sc->bge_flags |= BGE_FLAG_PCIE;
3596 sc->bge_expcap = reg;
3597 /* Extract supported maximum payload size. */
3598 sc->bge_mps = pci_read_config(dev, sc->bge_expcap +
3599 PCIER_DEVICE_CAP, 2);
3600 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD);
3601 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3602 sc->bge_asicrev == BGE_ASICREV_BCM5720)
3603 sc->bge_expmrq = 2048;
3605 sc->bge_expmrq = 4096;
3606 pci_set_max_read_req(dev, sc->bge_expmrq);
3609 * Check if the device is in PCI-X Mode.
3610 * (This bit is not valid on PCI Express controllers.)
3612 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0)
3613 sc->bge_pcixcap = reg;
3614 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
3615 BGE_PCISTATE_PCI_BUSMODE) == 0)
3616 sc->bge_flags |= BGE_FLAG_PCIX;
3620 * The 40bit DMA bug applies to the 5714/5715 controllers and is
3621 * not actually a MAC controller bug but an issue with the embedded
3622 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
3624 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
3625 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
3627 * Some PCI-X bridges are known to trigger write reordering to
3628 * the mailbox registers. Typical phenomena is watchdog timeouts
3629 * caused by out-of-order TX completions. Enable workaround for
3630 * PCI-X devices that live behind these bridges.
3631 * Note, PCI-X controllers can run in PCI mode so we can't use
3632 * BGE_FLAG_PCIX flag to detect PCI-X controllers.
3634 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0)
3635 sc->bge_flags |= BGE_FLAG_MBOX_REORDER;
3637 * Allocate the interrupt, using MSI if possible. These devices
3638 * support 8 MSI messages, but only the first one is used in
3642 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) {
3643 sc->bge_msicap = reg;
3645 if (bge_can_use_msi(sc) && pci_alloc_msi(dev, ®) == 0) {
3647 sc->bge_flags |= BGE_FLAG_MSI;
3652 * All controllers except BCM5700 supports tagged status but
3653 * we use tagged status only for MSI case on BCM5717. Otherwise
3654 * MSI on BCM5717 does not work.
3656 #ifndef DEVICE_POLLING
3657 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
3658 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
3661 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3662 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
3664 if (sc->bge_irq == NULL) {
3665 device_printf(sc->bge_dev, "couldn't map interrupt\n");
3672 sc->bge_asf_mode = 0;
3673 /* No ASF if APE present. */
3674 if ((sc->bge_flags & BGE_FLAG_APE) == 0) {
3675 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3676 BGE_SRAM_DATA_SIG_MAGIC)) {
3677 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
3679 sc->bge_asf_mode |= ASF_ENABLE;
3680 sc->bge_asf_mode |= ASF_STACKUP;
3681 if (BGE_IS_575X_PLUS(sc))
3682 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3688 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
3689 if (bge_reset(sc)) {
3690 device_printf(sc->bge_dev, "chip reset failed\n");
3695 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
3696 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
3698 if (bge_chipinit(sc)) {
3699 device_printf(sc->bge_dev, "chip initialization failed\n");
3704 error = bge_get_eaddr(sc, eaddr);
3706 device_printf(sc->bge_dev,
3707 "failed to read station address\n");
3712 /* 5705 limits RX return ring to 512 entries. */
3713 if (BGE_IS_5717_PLUS(sc))
3714 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3715 else if (BGE_IS_5705_PLUS(sc))
3716 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3718 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3720 if (bge_dma_alloc(sc)) {
3721 device_printf(sc->bge_dev,
3722 "failed to allocate DMA resources\n");
3727 /* Set default tuneable values. */
3728 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3729 sc->bge_rx_coal_ticks = 150;
3730 sc->bge_tx_coal_ticks = 150;
3731 sc->bge_rx_max_coal_bds = 10;
3732 sc->bge_tx_max_coal_bds = 10;
3734 /* Initialize checksum features to use. */
3735 sc->bge_csum_features = BGE_CSUM_FEATURES;
3736 if (sc->bge_forced_udpcsum != 0)
3737 sc->bge_csum_features |= CSUM_UDP;
3739 /* Set up ifnet structure */
3740 ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
3742 device_printf(sc->bge_dev, "failed to if_alloc()\n");
3746 if_setsoftc(ifp, sc);
3747 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3748 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
3749 if_setioctlfn(ifp, bge_ioctl);
3750 if_setstartfn(ifp, bge_start);
3751 if_setinitfn(ifp, bge_init);
3752 if_setgetcounterfn(ifp, bge_get_counter);
3753 if_setsendqlen(ifp, BGE_TX_RING_CNT - 1);
3754 if_setsendqready(ifp);
3755 if_sethwassist(ifp, sc->bge_csum_features);
3756 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3758 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3759 if_sethwassistbits(ifp, CSUM_TSO, 0);
3760 if_setcapabilitiesbit(ifp, IFCAP_TSO4 | IFCAP_VLAN_HWTSO, 0);
3762 #ifdef IFCAP_VLAN_HWCSUM
3763 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0);
3765 if_setcapenable(ifp, if_getcapabilities(ifp));
3766 #ifdef DEVICE_POLLING
3767 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
3771 * 5700 B0 chips do not support checksumming correctly due
3774 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
3775 if_setcapabilitiesbit(ifp, 0, IFCAP_HWCSUM);
3776 if_setcapenablebit(ifp, 0, IFCAP_HWCSUM);
3777 if_sethwassist(ifp, 0);
3781 * Figure out what sort of media we have by checking the
3782 * hardware config word in the first 32k of NIC internal memory,
3783 * or fall back to examining the EEPROM if necessary.
3784 * Note: on some BCM5700 cards, this value appears to be unset.
3785 * If that's the case, we have to rely on identifying the NIC
3786 * by its PCI subsystem ID, as we do below for the SysKonnect
3789 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
3790 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3791 else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
3792 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3793 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
3795 device_printf(sc->bge_dev, "failed to read EEPROM\n");
3799 hwcfg = ntohl(hwcfg);
3802 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
3803 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
3804 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
3805 if (BGE_IS_5705_PLUS(sc)) {
3806 sc->bge_flags |= BGE_FLAG_MII_SERDES;
3807 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3809 sc->bge_flags |= BGE_FLAG_TBI;
3812 /* Set various PHY bug flags. */
3813 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
3814 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
3815 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
3816 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
3817 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
3818 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
3819 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
3820 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
3821 if (pci_get_subvendor(dev) == DELL_VENDORID)
3822 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
3823 if ((BGE_IS_5705_PLUS(sc)) &&
3824 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
3825 sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
3826 sc->bge_asicrev != BGE_ASICREV_BCM57780 &&
3827 !BGE_IS_5717_PLUS(sc)) {
3828 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
3829 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3830 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3831 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
3832 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
3833 pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
3834 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
3835 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
3836 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
3838 sc->bge_phy_flags |= BGE_PHY_BER_BUG;
3842 * Don't enable Ethernet@WireSpeed for the 5700 or the
3843 * 5705 A0 and A1 chips.
3845 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3846 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3847 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
3848 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)))
3849 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3851 if (sc->bge_flags & BGE_FLAG_TBI) {
3852 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3854 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
3855 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
3857 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3858 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3859 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3862 * Do transceiver setup and tell the firmware the
3863 * driver is down so we can try to get access the
3864 * probe if ASF is running. Retry a couple of times
3865 * if we get a conflict with the ASF firmware accessing
3869 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3871 bge_asf_driver_up(sc);
3873 error = mii_attach(dev, &sc->bge_miibus, ifp,
3874 (ifm_change_cb_t)bge_ifmedia_upd,
3875 (ifm_stat_cb_t)bge_ifmedia_sts, capmask, sc->bge_phy_addr,
3876 MII_OFFSET_ANY, MIIF_DOPAUSE);
3879 device_printf(sc->bge_dev, "Try again\n");
3880 bge_miibus_writereg(sc->bge_dev,
3881 sc->bge_phy_addr, MII_BMCR, BMCR_RESET);
3884 device_printf(sc->bge_dev, "attaching PHYs failed\n");
3889 * Now tell the firmware we are going up after probing the PHY
3891 if (sc->bge_asf_mode & ASF_STACKUP)
3892 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3896 * When using the BCM5701 in PCI-X mode, data corruption has
3897 * been observed in the first few bytes of some received packets.
3898 * Aligning the packet buffer in memory eliminates the corruption.
3899 * Unfortunately, this misaligns the packet payloads. On platforms
3900 * which do not support unaligned accesses, we will realign the
3901 * payloads by copying the received packets.
3903 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
3904 sc->bge_flags & BGE_FLAG_PCIX)
3905 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
3908 * Call MI attach routine.
3910 ether_ifattach(ifp, eaddr);
3912 /* Tell upper layer we support long frames. */
3913 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
3918 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
3919 /* Take advantage of single-shot MSI. */
3920 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
3921 ~BGE_MSIMODE_ONE_SHOT_DISABLE);
3922 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
3923 taskqueue_thread_enqueue, &sc->bge_tq);
3924 if (sc->bge_tq == NULL) {
3925 device_printf(dev, "could not create taskqueue.\n");
3926 ether_ifdetach(ifp);
3930 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET,
3931 "%s taskq", device_get_nameunit(sc->bge_dev));
3933 device_printf(dev, "could not start threads.\n");
3934 ether_ifdetach(ifp);
3937 error = bus_setup_intr(dev, sc->bge_irq,
3938 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
3941 error = bus_setup_intr(dev, sc->bge_irq,
3942 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
3946 ether_ifdetach(ifp);
3947 device_printf(sc->bge_dev, "couldn't set up irq\n");
3951 /* Attach driver netdump methods. */
3952 NETDUMP_SET(ifp, bge);
3961 bge_detach(device_t dev)
3963 struct bge_softc *sc;
3966 sc = device_get_softc(dev);
3969 #ifdef DEVICE_POLLING
3970 if (if_getcapenable(ifp) & IFCAP_POLLING)
3971 ether_poll_deregister(ifp);
3974 if (device_is_attached(dev)) {
3975 ether_ifdetach(ifp);
3979 callout_drain(&sc->bge_stat_ch);
3983 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3985 if (sc->bge_flags & BGE_FLAG_TBI)
3986 ifmedia_removeall(&sc->bge_ifmedia);
3987 else if (sc->bge_miibus != NULL) {
3988 bus_generic_detach(dev);
3989 device_delete_child(dev, sc->bge_miibus);
3992 bge_release_resources(sc);
3998 bge_release_resources(struct bge_softc *sc)
4004 if (sc->bge_tq != NULL)
4005 taskqueue_free(sc->bge_tq);
4007 if (sc->bge_intrhand != NULL)
4008 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
4010 if (sc->bge_irq != NULL) {
4011 bus_release_resource(dev, SYS_RES_IRQ,
4012 rman_get_rid(sc->bge_irq), sc->bge_irq);
4013 pci_release_msi(dev);
4016 if (sc->bge_res != NULL)
4017 bus_release_resource(dev, SYS_RES_MEMORY,
4018 rman_get_rid(sc->bge_res), sc->bge_res);
4020 if (sc->bge_res2 != NULL)
4021 bus_release_resource(dev, SYS_RES_MEMORY,
4022 rman_get_rid(sc->bge_res2), sc->bge_res2);
4024 if (sc->bge_ifp != NULL)
4025 if_free(sc->bge_ifp);
4029 if (mtx_initialized(&sc->bge_mtx)) /* XXX */
4030 BGE_LOCK_DESTROY(sc);
4034 bge_reset(struct bge_softc *sc)
4037 uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val;
4038 void (*write_op)(struct bge_softc *, int, int);
4044 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
4045 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4046 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
4047 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
4049 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
4050 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
4051 if (sc->bge_flags & BGE_FLAG_PCIE)
4052 write_op = bge_writemem_direct;
4054 write_op = bge_writemem_ind;
4056 write_op = bge_writereg_ind;
4058 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
4059 sc->bge_asicrev != BGE_ASICREV_BCM5701) {
4060 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
4061 for (i = 0; i < 8000; i++) {
4062 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
4063 BGE_NVRAMSWARB_GNT1)
4069 device_printf(dev, "NVRAM lock timedout!\n");
4072 /* Take APE lock when performing reset. */
4073 bge_ape_lock(sc, BGE_APE_LOCK_GRC);
4075 /* Save some important PCI state. */
4076 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
4077 command = pci_read_config(dev, BGE_PCI_CMD, 4);
4079 pci_write_config(dev, BGE_PCI_MISC_CTL,
4080 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4081 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4083 /* Disable fastboot on controllers that support it. */
4084 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
4085 BGE_IS_5755_PLUS(sc)) {
4087 device_printf(dev, "Disabling fastboot\n");
4088 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
4092 * Write the magic number to SRAM at offset 0xB50.
4093 * When firmware finishes its initialization it will
4094 * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
4096 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
4098 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
4100 /* XXX: Broadcom Linux driver. */
4101 if (sc->bge_flags & BGE_FLAG_PCIE) {
4102 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
4103 (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) {
4104 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */
4105 CSR_WRITE_4(sc, 0x7E2C, 0x20);
4107 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
4108 /* Prevent PCIE link training during global reset */
4109 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
4114 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4115 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4116 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
4117 val | BGE_VCPU_STATUS_DRV_RESET);
4118 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
4119 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
4120 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
4124 * Set GPHY Power Down Override to leave GPHY
4125 * powered up in D0 uninitialized.
4127 if (BGE_IS_5705_PLUS(sc) &&
4128 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0)
4129 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
4131 /* Issue global reset */
4132 write_op(sc, BGE_MISC_CFG, reset);
4134 if (sc->bge_flags & BGE_FLAG_PCIE)
4139 /* XXX: Broadcom Linux driver. */
4140 if (sc->bge_flags & BGE_FLAG_PCIE) {
4141 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
4142 DELAY(500000); /* wait for link training to complete */
4143 val = pci_read_config(dev, 0xC4, 4);
4144 pci_write_config(dev, 0xC4, val | (1 << 15), 4);
4146 devctl = pci_read_config(dev,
4147 sc->bge_expcap + PCIER_DEVICE_CTL, 2);
4148 /* Clear enable no snoop and disable relaxed ordering. */
4149 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE |
4150 PCIEM_CTL_NOSNOOP_ENABLE);
4151 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL,
4153 pci_set_max_read_req(dev, sc->bge_expmrq);
4154 /* Clear error status. */
4155 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA,
4156 PCIEM_STA_CORRECTABLE_ERROR |
4157 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
4158 PCIEM_STA_UNSUPPORTED_REQ, 2);
4161 /* Reset some of the PCI state that got zapped by reset. */
4162 pci_write_config(dev, BGE_PCI_MISC_CTL,
4163 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4164 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4165 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
4166 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
4167 (sc->bge_flags & BGE_FLAG_PCIX) != 0)
4168 val |= BGE_PCISTATE_RETRY_SAME_DMA;
4169 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4170 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
4171 BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
4172 BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
4173 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4);
4174 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
4175 pci_write_config(dev, BGE_PCI_CMD, command, 4);
4177 * Disable PCI-X relaxed ordering to ensure status block update
4178 * comes first then packet buffer DMA. Otherwise driver may
4179 * read stale status block.
4181 if (sc->bge_flags & BGE_FLAG_PCIX) {
4182 devctl = pci_read_config(dev,
4183 sc->bge_pcixcap + PCIXR_COMMAND, 2);
4184 devctl &= ~PCIXM_COMMAND_ERO;
4185 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
4186 devctl &= ~PCIXM_COMMAND_MAX_READ;
4187 devctl |= PCIXM_COMMAND_MAX_READ_2048;
4188 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4189 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
4190 PCIXM_COMMAND_MAX_READ);
4191 devctl |= PCIXM_COMMAND_MAX_READ_2048;
4193 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
4196 /* Re-enable MSI, if necessary, and enable the memory arbiter. */
4197 if (BGE_IS_5714_FAMILY(sc)) {
4198 /* This chip disables MSI on reset. */
4199 if (sc->bge_flags & BGE_FLAG_MSI) {
4200 val = pci_read_config(dev,
4201 sc->bge_msicap + PCIR_MSI_CTRL, 2);
4202 pci_write_config(dev,
4203 sc->bge_msicap + PCIR_MSI_CTRL,
4204 val | PCIM_MSICTRL_MSI_ENABLE, 2);
4205 val = CSR_READ_4(sc, BGE_MSI_MODE);
4206 CSR_WRITE_4(sc, BGE_MSI_MODE,
4207 val | BGE_MSIMODE_ENABLE);
4209 val = CSR_READ_4(sc, BGE_MARB_MODE);
4210 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
4212 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4214 /* Fix up byte swapping. */
4215 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
4217 val = CSR_READ_4(sc, BGE_MAC_MODE);
4218 val = (val & ~mac_mode_mask) | mac_mode;
4219 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
4222 bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
4224 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4225 for (i = 0; i < BGE_TIMEOUT; i++) {
4226 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4227 if (val & BGE_VCPU_STATUS_INIT_DONE)
4231 if (i == BGE_TIMEOUT) {
4232 device_printf(dev, "reset timed out\n");
4237 * Poll until we see the 1's complement of the magic number.
4238 * This indicates that the firmware initialization is complete.
4239 * We expect this to fail if no chip containing the Ethernet
4240 * address is fitted though.
4242 for (i = 0; i < BGE_TIMEOUT; i++) {
4244 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
4245 if (val == ~BGE_SRAM_FW_MB_MAGIC)
4249 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
4251 "firmware handshake timed out, found 0x%08x\n",
4253 /* BCM57765 A0 needs additional time before accessing. */
4254 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
4255 DELAY(10 * 1000); /* XXX */
4259 * The 5704 in TBI mode apparently needs some special
4260 * adjustment to insure the SERDES drive level is set
4263 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
4264 sc->bge_flags & BGE_FLAG_TBI) {
4265 val = CSR_READ_4(sc, BGE_SERDES_CFG);
4266 val = (val & ~0xFFF) | 0x880;
4267 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
4270 /* XXX: Broadcom Linux driver. */
4271 if (sc->bge_flags & BGE_FLAG_PCIE &&
4272 !BGE_IS_5717_PLUS(sc) &&
4273 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
4274 sc->bge_asicrev != BGE_ASICREV_BCM5785) {
4275 /* Enable Data FIFO protection. */
4276 val = CSR_READ_4(sc, 0x7C00);
4277 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
4280 if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
4281 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
4282 CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
4287 static __inline void
4288 bge_rxreuse_std(struct bge_softc *sc, int i)
4290 struct bge_rx_bd *r;
4292 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
4293 r->bge_flags = BGE_RXBDFLAG_END;
4294 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
4296 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4299 static __inline void
4300 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
4302 struct bge_extrx_bd *r;
4304 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
4305 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
4306 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
4307 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
4308 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
4309 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
4311 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4315 * Frame reception handling. This is called if there's a frame
4316 * on the receive return list.
4318 * Note: we have to be able to handle two possibilities here:
4319 * 1) the frame is from the jumbo receive ring
4320 * 2) the frame is from the standard receive ring
4324 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
4327 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
4330 rx_cons = sc->bge_rx_saved_considx;
4332 /* Nothing to do. */
4333 if (rx_cons == rx_prod)
4338 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4339 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
4340 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4341 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
4342 if (BGE_IS_JUMBO_CAPABLE(sc) &&
4343 if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
4344 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))
4345 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4346 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
4348 while (rx_cons != rx_prod) {
4349 struct bge_rx_bd *cur_rx;
4351 struct mbuf *m = NULL;
4352 uint16_t vlan_tag = 0;
4355 #ifdef DEVICE_POLLING
4356 if (if_getcapenable(ifp) & IFCAP_POLLING) {
4357 if (sc->rxcycles <= 0)
4363 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
4365 rxidx = cur_rx->bge_idx;
4366 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
4368 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING &&
4369 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
4371 vlan_tag = cur_rx->bge_vlan_tag;
4374 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
4376 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
4377 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4378 bge_rxreuse_jumbo(sc, rxidx);
4381 if (bge_newbuf_jumbo(sc, rxidx) != 0) {
4382 bge_rxreuse_jumbo(sc, rxidx);
4383 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
4386 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4389 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
4390 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4391 bge_rxreuse_std(sc, rxidx);
4394 if (bge_newbuf_std(sc, rxidx) != 0) {
4395 bge_rxreuse_std(sc, rxidx);
4396 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
4399 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4402 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
4403 #ifndef __NO_STRICT_ALIGNMENT
4405 * For architectures with strict alignment we must make sure
4406 * the payload is aligned.
4408 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
4409 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
4411 m->m_data += ETHER_ALIGN;
4414 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
4415 m->m_pkthdr.rcvif = ifp;
4417 if (if_getcapenable(ifp) & IFCAP_RXCSUM)
4418 bge_rxcsum(sc, cur_rx, m);
4421 * If we received a packet with a vlan tag,
4422 * attach that information to the packet.
4425 m->m_pkthdr.ether_vtag = vlan_tag;
4426 m->m_flags |= M_VLANTAG;
4437 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4441 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4442 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
4444 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4445 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
4448 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4449 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
4451 sc->bge_rx_saved_considx = rx_cons;
4452 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
4454 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
4455 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT);
4457 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
4458 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT);
4461 * This register wraps very quickly under heavy packet drops.
4462 * If you need correct statistics, you can enable this check.
4464 if (BGE_IS_5705_PLUS(sc))
4465 if_incierrors(ifp, CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS));
4471 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
4474 if (BGE_IS_5717_PLUS(sc)) {
4475 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
4476 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4477 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4478 if ((cur_rx->bge_error_flag &
4479 BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
4480 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4482 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
4483 m->m_pkthdr.csum_data =
4484 cur_rx->bge_tcp_udp_csum;
4485 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4490 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4491 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4492 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
4493 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4495 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
4496 m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
4497 m->m_pkthdr.csum_data =
4498 cur_rx->bge_tcp_udp_csum;
4499 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4506 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
4508 struct bge_tx_bd *cur_tx;
4511 BGE_LOCK_ASSERT(sc);
4513 /* Nothing to do. */
4514 if (sc->bge_tx_saved_considx == tx_cons)
4519 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4520 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
4522 * Go through our tx ring and free mbufs for those
4523 * frames that have been sent.
4525 while (sc->bge_tx_saved_considx != tx_cons) {
4528 idx = sc->bge_tx_saved_considx;
4529 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
4530 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
4531 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
4532 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
4533 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
4534 sc->bge_cdata.bge_tx_dmamap[idx],
4535 BUS_DMASYNC_POSTWRITE);
4536 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
4537 sc->bge_cdata.bge_tx_dmamap[idx]);
4538 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
4539 sc->bge_cdata.bge_tx_chain[idx] = NULL;
4542 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
4545 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
4546 if (sc->bge_txcnt == 0)
4550 #ifdef DEVICE_POLLING
4552 bge_poll(if_t ifp, enum poll_cmd cmd, int count)
4554 struct bge_softc *sc = if_getsoftc(ifp);
4555 uint16_t rx_prod, tx_cons;
4556 uint32_t statusword;
4560 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
4565 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4566 sc->bge_cdata.bge_status_map,
4567 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4568 /* Fetch updates from the status block. */
4569 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4570 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4572 statusword = sc->bge_ldata.bge_status_block->bge_status;
4573 /* Clear the status so the next pass only sees the changes. */
4574 sc->bge_ldata.bge_status_block->bge_status = 0;
4576 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4577 sc->bge_cdata.bge_status_map,
4578 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4580 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
4581 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
4584 if (cmd == POLL_AND_CHECK_STATUS)
4585 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4586 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4587 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
4590 sc->rxcycles = count;
4591 rx_npkts = bge_rxeof(sc, rx_prod, 1);
4592 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
4596 bge_txeof(sc, tx_cons);
4597 if (!if_sendq_empty(ifp))
4598 bge_start_locked(ifp);
4603 #endif /* DEVICE_POLLING */
4606 bge_msi_intr(void *arg)
4608 struct bge_softc *sc;
4610 sc = (struct bge_softc *)arg;
4612 * This interrupt is not shared and controller already
4613 * disabled further interrupt.
4615 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
4616 return (FILTER_HANDLED);
4620 bge_intr_task(void *arg, int pending)
4622 struct bge_softc *sc;
4624 uint32_t status, status_tag;
4625 uint16_t rx_prod, tx_cons;
4627 sc = (struct bge_softc *)arg;
4631 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
4636 /* Get updated status block. */
4637 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4638 sc->bge_cdata.bge_status_map,
4639 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4641 /* Save producer/consumer indices. */
4642 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4643 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4644 status = sc->bge_ldata.bge_status_block->bge_status;
4645 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
4646 /* Dirty the status flag. */
4647 sc->bge_ldata.bge_status_block->bge_status = 0;
4648 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4649 sc->bge_cdata.bge_status_map,
4650 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4651 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
4654 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
4657 /* Let controller work. */
4658 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
4660 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
4661 sc->bge_rx_saved_considx != rx_prod) {
4662 /* Check RX return ring producer/consumer. */
4664 bge_rxeof(sc, rx_prod, 0);
4667 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4668 /* Check TX ring producer/consumer. */
4669 bge_txeof(sc, tx_cons);
4670 if (!if_sendq_empty(ifp))
4671 bge_start_locked(ifp);
4679 struct bge_softc *sc;
4681 uint32_t statusword;
4682 uint16_t rx_prod, tx_cons;
4690 #ifdef DEVICE_POLLING
4691 if (if_getcapenable(ifp) & IFCAP_POLLING) {
4698 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
4699 * disable interrupts by writing nonzero like we used to, since with
4700 * our current organization this just gives complications and
4701 * pessimizations for re-enabling interrupts. We used to have races
4702 * instead of the necessary complications. Disabling interrupts
4703 * would just reduce the chance of a status update while we are
4704 * running (by switching to the interrupt-mode coalescence
4705 * parameters), but this chance is already very low so it is more
4706 * efficient to get another interrupt than prevent it.
4708 * We do the ack first to ensure another interrupt if there is a
4709 * status update after the ack. We don't check for the status
4710 * changing later because it is more efficient to get another
4711 * interrupt than prevent it, not quite as above (not checking is
4712 * a smaller optimization than not toggling the interrupt enable,
4713 * since checking doesn't involve PCI accesses and toggling require
4714 * the status check). So toggling would probably be a pessimization
4715 * even with MSI. It would only be needed for using a task queue.
4717 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4720 * Do the mandatory PCI flush as well as get the link status.
4722 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
4724 /* Make sure the descriptor ring indexes are coherent. */
4725 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4726 sc->bge_cdata.bge_status_map,
4727 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4728 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4729 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4730 sc->bge_ldata.bge_status_block->bge_status = 0;
4731 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4732 sc->bge_cdata.bge_status_map,
4733 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4735 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4736 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4737 statusword || sc->bge_link_evt)
4740 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4741 /* Check RX return ring producer/consumer. */
4742 bge_rxeof(sc, rx_prod, 1);
4745 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4746 /* Check TX ring producer/consumer. */
4747 bge_txeof(sc, tx_cons);
4750 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
4751 !if_sendq_empty(ifp))
4752 bge_start_locked(ifp);
4758 bge_asf_driver_up(struct bge_softc *sc)
4760 if (sc->bge_asf_mode & ASF_STACKUP) {
4761 /* Send ASF heartbeat aprox. every 2s */
4762 if (sc->bge_asf_count)
4763 sc->bge_asf_count --;
4765 sc->bge_asf_count = 2;
4766 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4767 BGE_FW_CMD_DRV_ALIVE);
4768 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4769 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
4770 BGE_FW_HB_TIMEOUT_SEC);
4771 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
4772 CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4773 BGE_RX_CPU_DRV_EVENT);
4781 struct bge_softc *sc = xsc;
4782 struct mii_data *mii = NULL;
4784 BGE_LOCK_ASSERT(sc);
4786 /* Synchronize with possible callout reset/stop. */
4787 if (callout_pending(&sc->bge_stat_ch) ||
4788 !callout_active(&sc->bge_stat_ch))
4791 if (BGE_IS_5705_PLUS(sc))
4792 bge_stats_update_regs(sc);
4794 bge_stats_update(sc);
4796 /* XXX Add APE heartbeat check here? */
4798 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4799 mii = device_get_softc(sc->bge_miibus);
4801 * Do not touch PHY if we have link up. This could break
4802 * IPMI/ASF mode or produce extra input errors
4803 * (extra errors was reported for bcm5701 & bcm5704).
4809 * Since in TBI mode auto-polling can't be used we should poll
4810 * link status manually. Here we register pending link event
4811 * and trigger interrupt.
4813 #ifdef DEVICE_POLLING
4814 /* In polling mode we poll link state in bge_poll(). */
4815 if (!(if_getcapenable(sc->bge_ifp) & IFCAP_POLLING))
4819 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4820 sc->bge_flags & BGE_FLAG_5788)
4821 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4823 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4827 bge_asf_driver_up(sc);
4830 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4834 bge_stats_update_regs(struct bge_softc *sc)
4837 struct bge_mac_stats *stats;
4841 stats = &sc->bge_mac_stats;
4843 stats->ifHCOutOctets +=
4844 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4845 stats->etherStatsCollisions +=
4846 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4847 stats->outXonSent +=
4848 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4849 stats->outXoffSent +=
4850 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4851 stats->dot3StatsInternalMacTransmitErrors +=
4852 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4853 stats->dot3StatsSingleCollisionFrames +=
4854 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4855 stats->dot3StatsMultipleCollisionFrames +=
4856 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4857 stats->dot3StatsDeferredTransmissions +=
4858 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4859 stats->dot3StatsExcessiveCollisions +=
4860 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4861 stats->dot3StatsLateCollisions +=
4862 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4863 stats->ifHCOutUcastPkts +=
4864 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4865 stats->ifHCOutMulticastPkts +=
4866 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4867 stats->ifHCOutBroadcastPkts +=
4868 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4870 stats->ifHCInOctets +=
4871 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4872 stats->etherStatsFragments +=
4873 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4874 stats->ifHCInUcastPkts +=
4875 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4876 stats->ifHCInMulticastPkts +=
4877 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4878 stats->ifHCInBroadcastPkts +=
4879 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4880 stats->dot3StatsFCSErrors +=
4881 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4882 stats->dot3StatsAlignmentErrors +=
4883 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4884 stats->xonPauseFramesReceived +=
4885 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4886 stats->xoffPauseFramesReceived +=
4887 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4888 stats->macControlFramesReceived +=
4889 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4890 stats->xoffStateEntered +=
4891 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4892 stats->dot3StatsFramesTooLong +=
4893 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4894 stats->etherStatsJabbers +=
4895 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4896 stats->etherStatsUndersizePkts +=
4897 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4899 stats->FramesDroppedDueToFilters +=
4900 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4901 stats->DmaWriteQueueFull +=
4902 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4903 stats->DmaWriteHighPriQueueFull +=
4904 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4905 stats->NoMoreRxBDs +=
4906 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4909 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS
4910 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0
4911 * includes number of unwanted multicast frames. This comes
4912 * from silicon bug and known workaround to get rough(not
4913 * exact) counter is to enable interrupt on MBUF low water
4914 * attention. This can be accomplished by setting
4915 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE,
4916 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and
4917 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL.
4918 * However that change would generate more interrupts and
4919 * there are still possibilities of losing multiple frames
4920 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling.
4921 * Given that the workaround still would not get correct
4922 * counter I don't think it's worth to implement it. So
4923 * ignore reading the counter on controllers that have the
4926 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
4927 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
4928 sc->bge_chipid != BGE_CHIPID_BCM5720_A0)
4929 stats->InputDiscards +=
4930 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4931 stats->InputErrors +=
4932 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4933 stats->RecvThresholdHit +=
4934 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4936 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
4938 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS
4939 * frames, it's safe to disable workaround for DMA engine's
4940 * miscalculation of TXMBUF space.
4942 if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts +
4943 stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) {
4944 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
4945 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
4946 val &= ~BGE_RDMA_TX_LENGTH_WA_5719;
4948 val &= ~BGE_RDMA_TX_LENGTH_WA_5720;
4949 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
4950 sc->bge_flags &= ~BGE_FLAG_RDMA_BUG;
4956 bge_stats_clear_regs(struct bge_softc *sc)
4959 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4960 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4961 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4962 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4963 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4964 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4965 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4966 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4967 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4968 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4969 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4970 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4971 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4973 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4974 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4975 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4976 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4977 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4978 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4979 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4980 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4981 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4982 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4983 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4984 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4985 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4986 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4988 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4989 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4990 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4991 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4992 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4993 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4994 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4998 bge_stats_update(struct bge_softc *sc)
5002 uint32_t cnt; /* current register value */
5006 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
5008 #define READ_STAT(sc, stats, stat) \
5009 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
5011 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
5012 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, cnt - sc->bge_tx_collisions);
5013 sc->bge_tx_collisions = cnt;
5015 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo);
5016 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_nobds);
5017 sc->bge_rx_nobds = cnt;
5018 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo);
5019 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_inerrs);
5020 sc->bge_rx_inerrs = cnt;
5021 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
5022 if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_discards);
5023 sc->bge_rx_discards = cnt;
5025 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
5026 if_inc_counter(ifp, IFCOUNTER_OERRORS, cnt - sc->bge_tx_discards);
5027 sc->bge_tx_discards = cnt;
5033 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
5034 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
5035 * but when such padded frames employ the bge IP/TCP checksum offload,
5036 * the hardware checksum assist gives incorrect results (possibly
5037 * from incorporating its own padding into the UDP/TCP checksum; who knows).
5038 * If we pad such runts with zeros, the onboard checksum comes out correct.
5041 bge_cksum_pad(struct mbuf *m)
5043 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
5046 /* If there's only the packet-header and we can pad there, use it. */
5047 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
5048 M_TRAILINGSPACE(m) >= padlen) {
5052 * Walk packet chain to find last mbuf. We will either
5053 * pad there, or append a new mbuf and pad it.
5055 for (last = m; last->m_next != NULL; last = last->m_next);
5056 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
5057 /* Allocate new empty mbuf, pad it. Compact later. */
5060 MGET(n, M_NOWAIT, MT_DATA);
5069 /* Now zero the pad area, to avoid the bge cksum-assist bug. */
5070 memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
5071 last->m_len += padlen;
5072 m->m_pkthdr.len += padlen;
5077 static struct mbuf *
5078 bge_check_short_dma(struct mbuf *m)
5084 * If device receive two back-to-back send BDs with less than
5085 * or equal to 8 total bytes then the device may hang. The two
5086 * back-to-back send BDs must in the same frame for this failure
5087 * to occur. Scan mbuf chains and see whether two back-to-back
5088 * send BDs are there. If this is the case, allocate new mbuf
5089 * and copy the frame to workaround the silicon bug.
5091 for (n = m, found = 0; n != NULL; n = n->m_next) {
5102 n = m_defrag(m, M_NOWAIT);
5110 static struct mbuf *
5111 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
5120 if (M_WRITABLE(m) == 0) {
5121 /* Get a writable copy. */
5122 n = m_dup(m, M_NOWAIT);
5128 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
5131 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5132 poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
5133 m = m_pullup(m, poff + sizeof(struct tcphdr));
5136 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5137 m = m_pullup(m, poff + (tcp->th_off << 2));
5141 * It seems controller doesn't modify IP length and TCP pseudo
5142 * checksum. These checksum computed by upper stack should be 0.
5144 *mss = m->m_pkthdr.tso_segsz;
5145 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5147 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
5148 /* Clear pseudo checksum computed by TCP stack. */
5149 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5152 * Broadcom controllers uses different descriptor format for
5153 * TSO depending on ASIC revision. Due to TSO-capable firmware
5154 * license issue and lower performance of firmware based TSO
5155 * we only support hardware based TSO.
5157 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */
5158 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
5159 if (sc->bge_flags & BGE_FLAG_TSO3) {
5161 * For BCM5717 and newer controllers, hardware based TSO
5162 * uses the 14 lower bits of the bge_mss field to store the
5163 * MSS and the upper 2 bits to store the lowest 2 bits of
5164 * the IP/TCP header length. The upper 6 bits of the header
5165 * length are stored in the bge_flags[14:10,4] field. Jumbo
5166 * frames are supported.
5168 *mss |= ((hlen & 0x3) << 14);
5169 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2);
5172 * For BCM5755 and newer controllers, hardware based TSO uses
5173 * the lower 11 bits to store the MSS and the upper 5 bits to
5174 * store the IP/TCP header length. Jumbo frames are not
5177 *mss |= (hlen << 11);
5183 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
5184 * pointers to descriptors.
5187 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
5189 bus_dma_segment_t segs[BGE_NSEG_NEW];
5191 struct bge_tx_bd *d;
5192 struct mbuf *m = *m_head;
5193 uint32_t idx = *txidx;
5194 uint16_t csum_flags, mss, vlan_tag;
5195 int nsegs, i, error;
5200 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
5201 m->m_next != NULL) {
5202 *m_head = bge_check_short_dma(m);
5203 if (*m_head == NULL)
5207 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5208 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
5209 if (*m_head == NULL)
5211 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
5212 BGE_TXBDFLAG_CPU_POST_DMA;
5213 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
5214 if (m->m_pkthdr.csum_flags & CSUM_IP)
5215 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
5216 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
5217 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
5218 if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
5219 (error = bge_cksum_pad(m)) != 0) {
5227 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
5228 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
5229 m->m_pkthdr.len > ETHER_MAX_LEN)
5230 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME;
5231 if (sc->bge_forced_collapse > 0 &&
5232 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
5234 * Forcedly collapse mbuf chains to overcome hardware
5235 * limitation which only support a single outstanding
5236 * DMA read operation.
5238 if (sc->bge_forced_collapse == 1)
5239 m = m_defrag(m, M_NOWAIT);
5241 m = m_collapse(m, M_NOWAIT,
5242 sc->bge_forced_collapse);
5249 map = sc->bge_cdata.bge_tx_dmamap[idx];
5250 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
5251 &nsegs, BUS_DMA_NOWAIT);
5252 if (error == EFBIG) {
5253 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW);
5260 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
5261 m, segs, &nsegs, BUS_DMA_NOWAIT);
5267 } else if (error != 0)
5270 /* Check if we have enough free send BDs. */
5271 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
5272 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5276 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
5278 if (m->m_flags & M_VLANTAG) {
5279 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
5280 vlan_tag = m->m_pkthdr.ether_vtag;
5283 if (sc->bge_asicrev == BGE_ASICREV_BCM5762 &&
5284 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5286 * 5725 family of devices corrupts TSO packets when TSO DMA
5287 * buffers cross into regions which are within MSS bytes of
5288 * a 4GB boundary. If we encounter the condition, drop the
5291 for (i = 0; ; i++) {
5292 d = &sc->bge_ldata.bge_tx_ring[idx];
5293 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5294 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5295 d->bge_len = segs[i].ds_len;
5296 if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss <
5297 d->bge_addr.bge_addr_lo)
5299 d->bge_flags = csum_flags;
5300 d->bge_vlan_tag = vlan_tag;
5304 BGE_INC(idx, BGE_TX_RING_CNT);
5306 if (i != nsegs - 1) {
5307 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map,
5308 BUS_DMASYNC_POSTWRITE);
5309 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5315 for (i = 0; ; i++) {
5316 d = &sc->bge_ldata.bge_tx_ring[idx];
5317 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5318 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5319 d->bge_len = segs[i].ds_len;
5320 d->bge_flags = csum_flags;
5321 d->bge_vlan_tag = vlan_tag;
5325 BGE_INC(idx, BGE_TX_RING_CNT);
5329 /* Mark the last segment as end of packet... */
5330 d->bge_flags |= BGE_TXBDFLAG_END;
5333 * Insure that the map for this transmission
5334 * is placed at the array index of the last descriptor
5337 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
5338 sc->bge_cdata.bge_tx_dmamap[idx] = map;
5339 sc->bge_cdata.bge_tx_chain[idx] = m;
5340 sc->bge_txcnt += nsegs;
5342 BGE_INC(idx, BGE_TX_RING_CNT);
5349 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5350 * to the mbuf data regions directly in the transmit descriptors.
5353 bge_start_locked(if_t ifp)
5355 struct bge_softc *sc;
5356 struct mbuf *m_head;
5360 sc = if_getsoftc(ifp);
5361 BGE_LOCK_ASSERT(sc);
5363 if (!sc->bge_link ||
5364 (if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
5368 prodidx = sc->bge_tx_prodidx;
5370 for (count = 0; !if_sendq_empty(ifp);) {
5371 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
5372 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5375 m_head = if_dequeue(ifp);
5380 * Pack the data into the transmit ring. If we
5381 * don't have room, set the OACTIVE flag and wait
5382 * for the NIC to drain the ring.
5384 if (bge_encap(sc, &m_head, &prodidx)) {
5387 if_sendq_prepend(ifp, m_head);
5388 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5394 * If there's a BPF listener, bounce a copy of this frame
5397 if_bpfmtap(ifp, m_head);
5401 bge_start_tx(sc, prodidx);
5405 bge_start_tx(struct bge_softc *sc, uint32_t prodidx)
5408 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
5409 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
5411 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5412 /* 5700 b2 errata */
5413 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
5414 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5416 sc->bge_tx_prodidx = prodidx;
5418 /* Set a timeout in case the chip goes out to lunch. */
5419 sc->bge_timer = BGE_TX_TIMEOUT;
5423 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5424 * to the mbuf data regions directly in the transmit descriptors.
5429 struct bge_softc *sc;
5431 sc = if_getsoftc(ifp);
5433 bge_start_locked(ifp);
5438 bge_init_locked(struct bge_softc *sc)
5444 BGE_LOCK_ASSERT(sc);
5448 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
5451 /* Cancel pending I/O and flush buffers. */
5455 bge_sig_pre_reset(sc, BGE_RESET_START);
5457 bge_sig_legacy(sc, BGE_RESET_START);
5458 bge_sig_post_reset(sc, BGE_RESET_START);
5463 * Init the various state machines, ring
5464 * control blocks and firmware.
5466 if (bge_blockinit(sc)) {
5467 device_printf(sc->bge_dev, "initialization failure\n");
5474 CSR_WRITE_4(sc, BGE_RX_MTU, if_getmtu(ifp) +
5475 ETHER_HDR_LEN + ETHER_CRC_LEN +
5476 (if_getcapenable(ifp) & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
5478 /* Load our MAC address. */
5479 m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
5480 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
5481 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
5483 /* Program promiscuous mode. */
5486 /* Program multicast filter. */
5489 /* Program VLAN tag stripping. */
5492 /* Override UDP checksum offloading. */
5493 if (sc->bge_forced_udpcsum == 0)
5494 sc->bge_csum_features &= ~CSUM_UDP;
5496 sc->bge_csum_features |= CSUM_UDP;
5497 if (if_getcapabilities(ifp) & IFCAP_TXCSUM &&
5498 if_getcapenable(ifp) & IFCAP_TXCSUM) {
5499 if_sethwassistbits(ifp, 0, (BGE_CSUM_FEATURES | CSUM_UDP));
5500 if_sethwassistbits(ifp, sc->bge_csum_features, 0);
5504 if (bge_init_rx_ring_std(sc) != 0) {
5505 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
5511 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
5512 * memory to insure that the chip has in fact read the first
5513 * entry of the ring.
5515 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
5517 for (i = 0; i < 10; i++) {
5519 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
5520 if (v == (MCLBYTES - ETHER_ALIGN))
5524 device_printf (sc->bge_dev,
5525 "5705 A0 chip failed to load RX ring\n");
5528 /* Init jumbo RX ring. */
5529 if (BGE_IS_JUMBO_CAPABLE(sc) &&
5530 if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
5531 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) {
5532 if (bge_init_rx_ring_jumbo(sc) != 0) {
5533 device_printf(sc->bge_dev,
5534 "no memory for jumbo Rx buffers.\n");
5540 /* Init our RX return ring index. */
5541 sc->bge_rx_saved_considx = 0;
5543 /* Init our RX/TX stat counters. */
5544 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
5547 bge_init_tx_ring(sc);
5549 /* Enable TX MAC state machine lockup fix. */
5550 mode = CSR_READ_4(sc, BGE_TX_MODE);
5551 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
5552 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
5553 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
5554 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
5555 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5556 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
5557 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5559 /* Turn on transmitter. */
5560 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
5563 /* Turn on receiver. */
5564 mode = CSR_READ_4(sc, BGE_RX_MODE);
5565 if (BGE_IS_5755_PLUS(sc))
5566 mode |= BGE_RXMODE_IPV6_ENABLE;
5567 if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
5568 mode |= BGE_RXMODE_IPV4_FRAG_FIX;
5569 CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
5573 * Set the number of good frames to receive after RX MBUF
5574 * Low Watermark has been reached. After the RX MAC receives
5575 * this number of frames, it will drop subsequent incoming
5576 * frames until the MBUF High Watermark is reached.
5578 if (BGE_IS_57765_PLUS(sc))
5579 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
5581 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
5583 /* Clear MAC statistics. */
5584 if (BGE_IS_5705_PLUS(sc))
5585 bge_stats_clear_regs(sc);
5587 /* Tell firmware we're alive. */
5588 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5590 #ifdef DEVICE_POLLING
5591 /* Disable interrupts if we are polling. */
5592 if (if_getcapenable(ifp) & IFCAP_POLLING) {
5593 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5594 BGE_PCIMISCCTL_MASK_PCI_INTR);
5595 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5599 /* Enable host interrupts. */
5601 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
5602 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5603 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5606 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
5607 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
5609 bge_ifmedia_upd_locked(ifp);
5611 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
5617 struct bge_softc *sc = xsc;
5620 bge_init_locked(sc);
5625 * Set media options.
5628 bge_ifmedia_upd(if_t ifp)
5630 struct bge_softc *sc = if_getsoftc(ifp);
5634 res = bge_ifmedia_upd_locked(ifp);
5641 bge_ifmedia_upd_locked(if_t ifp)
5643 struct bge_softc *sc = if_getsoftc(ifp);
5644 struct mii_data *mii;
5645 struct mii_softc *miisc;
5646 struct ifmedia *ifm;
5648 BGE_LOCK_ASSERT(sc);
5650 ifm = &sc->bge_ifmedia;
5652 /* If this is a 1000baseX NIC, enable the TBI port. */
5653 if (sc->bge_flags & BGE_FLAG_TBI) {
5654 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
5656 switch(IFM_SUBTYPE(ifm->ifm_media)) {
5659 * The BCM5704 ASIC appears to have a special
5660 * mechanism for programming the autoneg
5661 * advertisement registers in TBI mode.
5663 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
5665 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5666 if (sgdig & BGE_SGDIGSTS_DONE) {
5667 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5668 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5669 sgdig |= BGE_SGDIGCFG_AUTO |
5670 BGE_SGDIGCFG_PAUSE_CAP |
5671 BGE_SGDIGCFG_ASYM_PAUSE;
5672 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
5673 sgdig | BGE_SGDIGCFG_SEND);
5675 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
5680 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
5681 BGE_CLRBIT(sc, BGE_MAC_MODE,
5682 BGE_MACMODE_HALF_DUPLEX);
5684 BGE_SETBIT(sc, BGE_MAC_MODE,
5685 BGE_MACMODE_HALF_DUPLEX);
5696 mii = device_get_softc(sc->bge_miibus);
5697 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
5702 * Force an interrupt so that we will call bge_link_upd
5703 * if needed and clear any pending link state attention.
5704 * Without this we are not getting any further interrupts
5705 * for link state changes and thus will not UP the link and
5706 * not be able to send in bge_start_locked. The only
5707 * way to get things working was to receive a packet and
5709 * bge_tick should help for fiber cards and we might not
5710 * need to do this here if BGE_FLAG_TBI is set but as
5711 * we poll for fiber anyway it should not harm.
5713 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
5714 sc->bge_flags & BGE_FLAG_5788)
5715 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
5717 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
5723 * Report current media status.
5726 bge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
5728 struct bge_softc *sc = if_getsoftc(ifp);
5729 struct mii_data *mii;
5733 if ((if_getflags(ifp) & IFF_UP) == 0) {
5737 if (sc->bge_flags & BGE_FLAG_TBI) {
5738 ifmr->ifm_status = IFM_AVALID;
5739 ifmr->ifm_active = IFM_ETHER;
5740 if (CSR_READ_4(sc, BGE_MAC_STS) &
5741 BGE_MACSTAT_TBI_PCS_SYNCHED)
5742 ifmr->ifm_status |= IFM_ACTIVE;
5744 ifmr->ifm_active |= IFM_NONE;
5748 ifmr->ifm_active |= IFM_1000_SX;
5749 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5750 ifmr->ifm_active |= IFM_HDX;
5752 ifmr->ifm_active |= IFM_FDX;
5757 mii = device_get_softc(sc->bge_miibus);
5759 ifmr->ifm_active = mii->mii_media_active;
5760 ifmr->ifm_status = mii->mii_media_status;
5766 bge_ioctl(if_t ifp, u_long command, caddr_t data)
5768 struct bge_softc *sc = if_getsoftc(ifp);
5769 struct ifreq *ifr = (struct ifreq *) data;
5770 struct mii_data *mii;
5771 int flags, mask, error = 0;
5775 if (BGE_IS_JUMBO_CAPABLE(sc) ||
5776 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
5777 if (ifr->ifr_mtu < ETHERMIN ||
5778 ifr->ifr_mtu > BGE_JUMBO_MTU) {
5782 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) {
5787 if (if_getmtu(ifp) != ifr->ifr_mtu) {
5788 if_setmtu(ifp, ifr->ifr_mtu);
5789 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5790 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5791 bge_init_locked(sc);
5798 if (if_getflags(ifp) & IFF_UP) {
5800 * If only the state of the PROMISC flag changed,
5801 * then just use the 'set promisc mode' command
5802 * instead of reinitializing the entire NIC. Doing
5803 * a full re-init means reloading the firmware and
5804 * waiting for it to start up, which may take a
5805 * second or two. Similarly for ALLMULTI.
5807 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5808 flags = if_getflags(ifp) ^ sc->bge_if_flags;
5809 if (flags & IFF_PROMISC)
5811 if (flags & IFF_ALLMULTI)
5814 bge_init_locked(sc);
5816 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5820 sc->bge_if_flags = if_getflags(ifp);
5826 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5835 if (sc->bge_flags & BGE_FLAG_TBI) {
5836 error = ifmedia_ioctl(ifp, ifr,
5837 &sc->bge_ifmedia, command);
5839 mii = device_get_softc(sc->bge_miibus);
5840 error = ifmedia_ioctl(ifp, ifr,
5841 &mii->mii_media, command);
5845 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
5846 #ifdef DEVICE_POLLING
5847 if (mask & IFCAP_POLLING) {
5848 if (ifr->ifr_reqcap & IFCAP_POLLING) {
5849 error = ether_poll_register(bge_poll, ifp);
5853 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5854 BGE_PCIMISCCTL_MASK_PCI_INTR);
5855 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5856 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
5859 error = ether_poll_deregister(ifp);
5860 /* Enable interrupt even in error case */
5862 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
5863 BGE_PCIMISCCTL_MASK_PCI_INTR);
5864 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5865 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
5870 if ((mask & IFCAP_TXCSUM) != 0 &&
5871 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
5872 if_togglecapenable(ifp, IFCAP_TXCSUM);
5873 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
5874 if_sethwassistbits(ifp,
5875 sc->bge_csum_features, 0);
5877 if_sethwassistbits(ifp, 0,
5878 sc->bge_csum_features);
5881 if ((mask & IFCAP_RXCSUM) != 0 &&
5882 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0)
5883 if_togglecapenable(ifp, IFCAP_RXCSUM);
5885 if ((mask & IFCAP_TSO4) != 0 &&
5886 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
5887 if_togglecapenable(ifp, IFCAP_TSO4);
5888 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
5889 if_sethwassistbits(ifp, CSUM_TSO, 0);
5891 if_sethwassistbits(ifp, 0, CSUM_TSO);
5894 if (mask & IFCAP_VLAN_MTU) {
5895 if_togglecapenable(ifp, IFCAP_VLAN_MTU);
5896 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5900 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
5901 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
5902 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
5903 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
5904 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
5905 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
5906 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
5907 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO);
5912 #ifdef VLAN_CAPABILITIES
5917 error = ether_ioctl(ifp, command, data);
5925 bge_watchdog(struct bge_softc *sc)
5930 BGE_LOCK_ASSERT(sc);
5932 if (sc->bge_timer == 0 || --sc->bge_timer)
5935 /* If pause frames are active then don't reset the hardware. */
5936 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) {
5937 status = CSR_READ_4(sc, BGE_RX_STS);
5938 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) {
5940 * If link partner has us in XOFF state then wait for
5941 * the condition to clear.
5943 CSR_WRITE_4(sc, BGE_RX_STS, status);
5944 sc->bge_timer = BGE_TX_TIMEOUT;
5946 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 &&
5947 (status & BGE_RXSTAT_RCVD_XON) != 0) {
5949 * If link partner has us in XOFF state then wait for
5950 * the condition to clear.
5952 CSR_WRITE_4(sc, BGE_RX_STS, status);
5953 sc->bge_timer = BGE_TX_TIMEOUT;
5957 * Any other condition is unexpected and the controller
5964 if_printf(ifp, "watchdog timeout -- resetting\n");
5966 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5967 bge_init_locked(sc);
5969 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
5973 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
5977 BGE_CLRBIT(sc, reg, bit);
5979 for (i = 0; i < BGE_TIMEOUT; i++) {
5980 if ((CSR_READ_4(sc, reg) & bit) == 0)
5987 * Stop the adapter and free any mbufs allocated to the
5991 bge_stop(struct bge_softc *sc)
5995 BGE_LOCK_ASSERT(sc);
5999 callout_stop(&sc->bge_stat_ch);
6001 /* Disable host interrupts. */
6002 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
6003 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
6006 * Tell firmware we're shutting down.
6009 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
6012 * Disable all of the receiver blocks.
6014 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
6015 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
6016 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
6017 if (BGE_IS_5700_FAMILY(sc))
6018 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
6019 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
6020 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
6021 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
6024 * Disable all of the transmit blocks.
6026 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
6027 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
6028 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
6029 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
6030 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
6031 if (BGE_IS_5700_FAMILY(sc))
6032 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
6033 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
6036 * Shut down all of the memory managers and related
6039 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
6040 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
6041 if (BGE_IS_5700_FAMILY(sc))
6042 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
6044 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
6045 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
6046 if (!(BGE_IS_5705_PLUS(sc))) {
6047 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
6048 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
6050 /* Update MAC statistics. */
6051 if (BGE_IS_5705_PLUS(sc))
6052 bge_stats_update_regs(sc);
6055 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
6056 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
6059 * Keep the ASF firmware running if up.
6061 if (sc->bge_asf_mode & ASF_STACKUP)
6062 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6064 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6066 /* Free the RX lists. */
6067 bge_free_rx_ring_std(sc);
6069 /* Free jumbo RX list. */
6070 if (BGE_IS_JUMBO_CAPABLE(sc))
6071 bge_free_rx_ring_jumbo(sc);
6073 /* Free TX buffers. */
6074 bge_free_tx_ring(sc);
6076 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
6078 /* Clear MAC's link state (PHY may still have link UP). */
6079 if (bootverbose && sc->bge_link)
6080 if_printf(sc->bge_ifp, "link DOWN\n");
6083 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
6087 * Stop all chip I/O so that the kernel's probe routines don't
6088 * get confused by errant DMAs when rebooting.
6091 bge_shutdown(device_t dev)
6093 struct bge_softc *sc;
6095 sc = device_get_softc(dev);
6104 bge_suspend(device_t dev)
6106 struct bge_softc *sc;
6108 sc = device_get_softc(dev);
6117 bge_resume(device_t dev)
6119 struct bge_softc *sc;
6122 sc = device_get_softc(dev);
6125 if (if_getflags(ifp) & IFF_UP) {
6126 bge_init_locked(sc);
6127 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
6128 bge_start_locked(ifp);
6136 bge_link_upd(struct bge_softc *sc)
6138 struct mii_data *mii;
6139 uint32_t link, status;
6141 BGE_LOCK_ASSERT(sc);
6143 /* Clear 'pending link event' flag. */
6144 sc->bge_link_evt = 0;
6147 * Process link state changes.
6148 * Grrr. The link status word in the status block does
6149 * not work correctly on the BCM5700 rev AX and BX chips,
6150 * according to all available information. Hence, we have
6151 * to enable MII interrupts in order to properly obtain
6152 * async link changes. Unfortunately, this also means that
6153 * we have to read the MAC status register to detect link
6154 * changes, thereby adding an additional register access to
6155 * the interrupt handler.
6157 * XXX: perhaps link state detection procedure used for
6158 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
6161 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6162 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
6163 status = CSR_READ_4(sc, BGE_MAC_STS);
6164 if (status & BGE_MACSTAT_MI_INTERRUPT) {
6165 mii = device_get_softc(sc->bge_miibus);
6167 if (!sc->bge_link &&
6168 mii->mii_media_status & IFM_ACTIVE &&
6169 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6172 if_printf(sc->bge_ifp, "link UP\n");
6173 } else if (sc->bge_link &&
6174 (!(mii->mii_media_status & IFM_ACTIVE) ||
6175 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6178 if_printf(sc->bge_ifp, "link DOWN\n");
6181 /* Clear the interrupt. */
6182 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
6183 BGE_EVTENB_MI_INTERRUPT);
6184 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
6186 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
6187 BRGPHY_MII_IMR, BRGPHY_INTRS);
6192 if (sc->bge_flags & BGE_FLAG_TBI) {
6193 status = CSR_READ_4(sc, BGE_MAC_STS);
6194 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
6195 if (!sc->bge_link) {
6197 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
6198 BGE_CLRBIT(sc, BGE_MAC_MODE,
6199 BGE_MACMODE_TBI_SEND_CFGS);
6202 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
6204 if_printf(sc->bge_ifp, "link UP\n");
6205 if_link_state_change(sc->bge_ifp,
6208 } else if (sc->bge_link) {
6211 if_printf(sc->bge_ifp, "link DOWN\n");
6212 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
6214 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
6216 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
6217 * in status word always set. Workaround this bug by reading
6218 * PHY link status directly.
6220 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
6222 if (link != sc->bge_link ||
6223 sc->bge_asicrev == BGE_ASICREV_BCM5700) {
6224 mii = device_get_softc(sc->bge_miibus);
6226 if (!sc->bge_link &&
6227 mii->mii_media_status & IFM_ACTIVE &&
6228 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6231 if_printf(sc->bge_ifp, "link UP\n");
6232 } else if (sc->bge_link &&
6233 (!(mii->mii_media_status & IFM_ACTIVE) ||
6234 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6237 if_printf(sc->bge_ifp, "link DOWN\n");
6242 * For controllers that call mii_tick, we have to poll
6245 mii = device_get_softc(sc->bge_miibus);
6247 bge_miibus_statchg(sc->bge_dev);
6250 /* Disable MAC attention when link is up. */
6251 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
6252 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
6253 BGE_MACSTAT_LINK_CHANGED);
6257 bge_add_sysctls(struct bge_softc *sc)
6259 struct sysctl_ctx_list *ctx;
6260 struct sysctl_oid_list *children;
6263 ctx = device_get_sysctl_ctx(sc->bge_dev);
6264 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
6266 #ifdef BGE_REGISTER_DEBUG
6267 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
6268 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
6269 "Debug Information");
6271 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
6272 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
6273 "MAC Register Read");
6275 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read",
6276 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I",
6277 "APE Register Read");
6279 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
6280 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
6285 unit = device_get_unit(sc->bge_dev);
6287 * A common design characteristic for many Broadcom client controllers
6288 * is that they only support a single outstanding DMA read operation
6289 * on the PCIe bus. This means that it will take twice as long to fetch
6290 * a TX frame that is split into header and payload buffers as it does
6291 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
6292 * these controllers, coalescing buffers to reduce the number of memory
6293 * reads is effective way to get maximum performance(about 940Mbps).
6294 * Without collapsing TX buffers the maximum TCP bulk transfer
6295 * performance is about 850Mbps. However forcing coalescing mbufs
6296 * consumes a lot of CPU cycles, so leave it off by default.
6298 sc->bge_forced_collapse = 0;
6299 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
6300 CTLFLAG_RWTUN, &sc->bge_forced_collapse, 0,
6301 "Number of fragmented TX buffers of a frame allowed before "
6302 "forced collapsing");
6305 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi",
6306 CTLFLAG_RDTUN, &sc->bge_msi, 0, "Enable MSI");
6309 * It seems all Broadcom controllers have a bug that can generate UDP
6310 * datagrams with checksum value 0 when TX UDP checksum offloading is
6311 * enabled. Generating UDP checksum value 0 is RFC 768 violation.
6312 * Even though the probability of generating such UDP datagrams is
6313 * low, I don't want to see FreeBSD boxes to inject such datagrams
6314 * into network so disable UDP checksum offloading by default. Users
6315 * still override this behavior by setting a sysctl variable,
6316 * dev.bge.0.forced_udpcsum.
6318 sc->bge_forced_udpcsum = 0;
6319 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum",
6320 CTLFLAG_RWTUN, &sc->bge_forced_udpcsum, 0,
6321 "Enable UDP checksum offloading even if controller can "
6322 "generate UDP checksum value 0");
6324 if (BGE_IS_5705_PLUS(sc))
6325 bge_add_sysctl_stats_regs(sc, ctx, children);
6327 bge_add_sysctl_stats(sc, ctx, children);
6330 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
6331 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
6332 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
6336 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6337 struct sysctl_oid_list *parent)
6339 struct sysctl_oid *tree;
6340 struct sysctl_oid_list *children, *schildren;
6342 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6343 NULL, "BGE Statistics");
6344 schildren = children = SYSCTL_CHILDREN(tree);
6345 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
6346 children, COSFramesDroppedDueToFilters,
6347 "FramesDroppedDueToFilters");
6348 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
6349 children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
6350 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
6351 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
6352 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
6353 children, nicNoMoreRxBDs, "NoMoreRxBDs");
6354 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
6355 children, ifInDiscards, "InputDiscards");
6356 BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
6357 children, ifInErrors, "InputErrors");
6358 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
6359 children, nicRecvThresholdHit, "RecvThresholdHit");
6360 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
6361 children, nicDmaReadQueueFull, "DmaReadQueueFull");
6362 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
6363 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
6364 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
6365 children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
6366 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
6367 children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
6368 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
6369 children, nicRingStatusUpdate, "RingStatusUpdate");
6370 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
6371 children, nicInterrupts, "Interrupts");
6372 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
6373 children, nicAvoidedInterrupts, "AvoidedInterrupts");
6374 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
6375 children, nicSendThresholdHit, "SendThresholdHit");
6377 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
6378 NULL, "BGE RX Statistics");
6379 children = SYSCTL_CHILDREN(tree);
6380 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
6381 children, rxstats.ifHCInOctets, "ifHCInOctets");
6382 BGE_SYSCTL_STAT(sc, ctx, "Fragments",
6383 children, rxstats.etherStatsFragments, "Fragments");
6384 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
6385 children, rxstats.ifHCInUcastPkts, "UnicastPkts");
6386 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
6387 children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
6388 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
6389 children, rxstats.dot3StatsFCSErrors, "FCSErrors");
6390 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
6391 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
6392 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
6393 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
6394 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
6395 children, rxstats.xoffPauseFramesReceived,
6396 "xoffPauseFramesReceived");
6397 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
6398 children, rxstats.macControlFramesReceived,
6399 "ControlFramesReceived");
6400 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
6401 children, rxstats.xoffStateEntered, "xoffStateEntered");
6402 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
6403 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
6404 BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
6405 children, rxstats.etherStatsJabbers, "Jabbers");
6406 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
6407 children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
6408 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
6409 children, rxstats.inRangeLengthError, "inRangeLengthError");
6410 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
6411 children, rxstats.outRangeLengthError, "outRangeLengthError");
6413 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
6414 NULL, "BGE TX Statistics");
6415 children = SYSCTL_CHILDREN(tree);
6416 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
6417 children, txstats.ifHCOutOctets, "ifHCOutOctets");
6418 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
6419 children, txstats.etherStatsCollisions, "Collisions");
6420 BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
6421 children, txstats.outXonSent, "XonSent");
6422 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
6423 children, txstats.outXoffSent, "XoffSent");
6424 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
6425 children, txstats.flowControlDone, "flowControlDone");
6426 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
6427 children, txstats.dot3StatsInternalMacTransmitErrors,
6428 "InternalMacTransmitErrors");
6429 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
6430 children, txstats.dot3StatsSingleCollisionFrames,
6431 "SingleCollisionFrames");
6432 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
6433 children, txstats.dot3StatsMultipleCollisionFrames,
6434 "MultipleCollisionFrames");
6435 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
6436 children, txstats.dot3StatsDeferredTransmissions,
6437 "DeferredTransmissions");
6438 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
6439 children, txstats.dot3StatsExcessiveCollisions,
6440 "ExcessiveCollisions");
6441 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
6442 children, txstats.dot3StatsLateCollisions,
6444 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
6445 children, txstats.ifHCOutUcastPkts, "UnicastPkts");
6446 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
6447 children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
6448 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
6449 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
6450 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
6451 children, txstats.dot3StatsCarrierSenseErrors,
6452 "CarrierSenseErrors");
6453 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
6454 children, txstats.ifOutDiscards, "Discards");
6455 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
6456 children, txstats.ifOutErrors, "Errors");
6459 #undef BGE_SYSCTL_STAT
6461 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
6462 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
6465 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6466 struct sysctl_oid_list *parent)
6468 struct sysctl_oid *tree;
6469 struct sysctl_oid_list *child, *schild;
6470 struct bge_mac_stats *stats;
6472 stats = &sc->bge_mac_stats;
6473 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6474 NULL, "BGE Statistics");
6475 schild = child = SYSCTL_CHILDREN(tree);
6476 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters",
6477 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters");
6478 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull",
6479 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full");
6480 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull",
6481 &stats->DmaWriteHighPriQueueFull,
6482 "NIC DMA Write High Priority Queue Full");
6483 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs",
6484 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors");
6485 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards",
6486 &stats->InputDiscards, "Discarded Input Frames");
6487 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors",
6488 &stats->InputErrors, "Input Errors");
6489 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit",
6490 &stats->RecvThresholdHit, "NIC Recv Threshold Hit");
6492 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD,
6493 NULL, "BGE RX Statistics");
6494 child = SYSCTL_CHILDREN(tree);
6495 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets",
6496 &stats->ifHCInOctets, "Inbound Octets");
6497 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments",
6498 &stats->etherStatsFragments, "Fragments");
6499 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6500 &stats->ifHCInUcastPkts, "Inbound Unicast Packets");
6501 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6502 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets");
6503 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6504 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets");
6505 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors",
6506 &stats->dot3StatsFCSErrors, "FCS Errors");
6507 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors",
6508 &stats->dot3StatsAlignmentErrors, "Alignment Errors");
6509 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived",
6510 &stats->xonPauseFramesReceived, "XON Pause Frames Received");
6511 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived",
6512 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received");
6513 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived",
6514 &stats->macControlFramesReceived, "MAC Control Frames Received");
6515 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered",
6516 &stats->xoffStateEntered, "XOFF State Entered");
6517 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong",
6518 &stats->dot3StatsFramesTooLong, "Frames Too Long");
6519 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers",
6520 &stats->etherStatsJabbers, "Jabbers");
6521 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts",
6522 &stats->etherStatsUndersizePkts, "Undersized Packets");
6524 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD,
6525 NULL, "BGE TX Statistics");
6526 child = SYSCTL_CHILDREN(tree);
6527 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets",
6528 &stats->ifHCOutOctets, "Outbound Octets");
6529 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions",
6530 &stats->etherStatsCollisions, "TX Collisions");
6531 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent",
6532 &stats->outXonSent, "XON Sent");
6533 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent",
6534 &stats->outXoffSent, "XOFF Sent");
6535 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors",
6536 &stats->dot3StatsInternalMacTransmitErrors,
6537 "Internal MAC TX Errors");
6538 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames",
6539 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames");
6540 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames",
6541 &stats->dot3StatsMultipleCollisionFrames,
6542 "Multiple Collision Frames");
6543 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions",
6544 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions");
6545 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions",
6546 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions");
6547 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions",
6548 &stats->dot3StatsLateCollisions, "Late Collisions");
6549 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6550 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets");
6551 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6552 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets");
6553 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6554 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets");
6557 #undef BGE_SYSCTL_STAT_ADD64
6560 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
6562 struct bge_softc *sc;
6566 sc = (struct bge_softc *)arg1;
6568 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
6569 offsetof(bge_hostaddr, bge_addr_lo));
6570 return (sysctl_handle_int(oidp, &result, 0, req));
6573 #ifdef BGE_REGISTER_DEBUG
6575 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
6577 struct bge_softc *sc;
6579 int error, result, sbsz;
6583 error = sysctl_handle_int(oidp, &result, 0, req);
6584 if (error || (req->newptr == NULL))
6588 sc = (struct bge_softc *)arg1;
6590 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6591 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
6592 sbsz = BGE_STATUS_BLK_SZ;
6595 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
6596 printf("Status Block:\n");
6598 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6599 sc->bge_cdata.bge_status_map,
6600 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6601 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) {
6603 for (j = 0; j < 8; j++)
6604 printf(" %04x", sbdata[i++]);
6608 printf("Registers:\n");
6609 for (i = 0x800; i < 0xA00; ) {
6611 for (j = 0; j < 8; j++) {
6612 printf(" %08x", CSR_READ_4(sc, i));
6619 printf("Hardware Flags:\n");
6620 if (BGE_IS_5717_PLUS(sc))
6621 printf(" - 5717 Plus\n");
6622 if (BGE_IS_5755_PLUS(sc))
6623 printf(" - 5755 Plus\n");
6624 if (BGE_IS_575X_PLUS(sc))
6625 printf(" - 575X Plus\n");
6626 if (BGE_IS_5705_PLUS(sc))
6627 printf(" - 5705 Plus\n");
6628 if (BGE_IS_5714_FAMILY(sc))
6629 printf(" - 5714 Family\n");
6630 if (BGE_IS_5700_FAMILY(sc))
6631 printf(" - 5700 Family\n");
6632 if (sc->bge_flags & BGE_FLAG_JUMBO)
6633 printf(" - Supports Jumbo Frames\n");
6634 if (sc->bge_flags & BGE_FLAG_PCIX)
6635 printf(" - PCI-X Bus\n");
6636 if (sc->bge_flags & BGE_FLAG_PCIE)
6637 printf(" - PCI Express Bus\n");
6638 if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
6639 printf(" - No 3 LEDs\n");
6640 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
6641 printf(" - RX Alignment Bug\n");
6648 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6650 struct bge_softc *sc;
6656 error = sysctl_handle_int(oidp, &result, 0, req);
6657 if (error || (req->newptr == NULL))
6660 if (result < 0x8000) {
6661 sc = (struct bge_softc *)arg1;
6662 val = CSR_READ_4(sc, result);
6663 printf("reg 0x%06X = 0x%08X\n", result, val);
6670 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS)
6672 struct bge_softc *sc;
6678 error = sysctl_handle_int(oidp, &result, 0, req);
6679 if (error || (req->newptr == NULL))
6682 if (result < 0x8000) {
6683 sc = (struct bge_softc *)arg1;
6684 val = APE_READ_4(sc, result);
6685 printf("reg 0x%06X = 0x%08X\n", result, val);
6692 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
6694 struct bge_softc *sc;
6700 error = sysctl_handle_int(oidp, &result, 0, req);
6701 if (error || (req->newptr == NULL))
6704 if (result < 0x8000) {
6705 sc = (struct bge_softc *)arg1;
6706 val = bge_readmem_ind(sc, result);
6707 printf("mem 0x%06X = 0x%08X\n", result, val);
6715 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
6718 if (sc->bge_flags & BGE_FLAG_EADDR)
6722 OF_getetheraddr(sc->bge_dev, ether_addr);
6729 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
6733 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
6734 if ((mac_addr >> 16) == 0x484b) {
6735 ether_addr[0] = (uint8_t)(mac_addr >> 8);
6736 ether_addr[1] = (uint8_t)mac_addr;
6737 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
6738 ether_addr[2] = (uint8_t)(mac_addr >> 24);
6739 ether_addr[3] = (uint8_t)(mac_addr >> 16);
6740 ether_addr[4] = (uint8_t)(mac_addr >> 8);
6741 ether_addr[5] = (uint8_t)mac_addr;
6748 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
6750 int mac_offset = BGE_EE_MAC_OFFSET;
6752 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6753 mac_offset = BGE_EE_MAC_OFFSET_5906;
6755 return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
6760 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
6763 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6766 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
6771 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
6773 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
6774 /* NOTE: Order is critical */
6777 bge_get_eaddr_nvram,
6778 bge_get_eaddr_eeprom,
6781 const bge_eaddr_fcn_t *func;
6783 for (func = bge_eaddr_funcs; *func != NULL; ++func) {
6784 if ((*func)(sc, eaddr) == 0)
6787 return (*func == NULL ? ENXIO : 0);
6791 bge_get_counter(if_t ifp, ift_counter cnt)
6793 struct bge_softc *sc;
6794 struct bge_mac_stats *stats;
6796 sc = if_getsoftc(ifp);
6797 if (!BGE_IS_5705_PLUS(sc))
6798 return (if_get_counter_default(ifp, cnt));
6799 stats = &sc->bge_mac_stats;
6802 case IFCOUNTER_IERRORS:
6803 return (stats->NoMoreRxBDs + stats->InputDiscards +
6804 stats->InputErrors);
6805 case IFCOUNTER_COLLISIONS:
6806 return (stats->etherStatsCollisions);
6808 return (if_get_counter_default(ifp, cnt));
6814 bge_netdump_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6816 struct bge_softc *sc;
6818 sc = if_getsoftc(ifp);
6820 *nrxr = sc->bge_return_ring_cnt;
6821 *ncl = NETDUMP_MAX_IN_FLIGHT;
6822 if ((sc->bge_flags & BGE_FLAG_JUMBO_STD) != 0 &&
6823 (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
6824 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)))
6825 *clsize = MJUM9BYTES;
6832 bge_netdump_event(if_t ifp __unused, enum netdump_ev event __unused)
6837 bge_netdump_transmit(if_t ifp, struct mbuf *m)
6839 struct bge_softc *sc;
6843 sc = if_getsoftc(ifp);
6844 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6848 prodidx = sc->bge_tx_prodidx;
6849 error = bge_encap(sc, &m, &prodidx);
6851 bge_start_tx(sc, prodidx);
6856 bge_netdump_poll(if_t ifp, int count)
6858 struct bge_softc *sc;
6859 uint32_t rx_prod, tx_cons;
6861 sc = if_getsoftc(ifp);
6862 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6866 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6867 sc->bge_cdata.bge_status_map,
6868 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6870 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
6871 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
6873 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6874 sc->bge_cdata.bge_status_map,
6875 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
6877 (void)bge_rxeof(sc, rx_prod, 0);
6878 bge_txeof(sc, tx_cons);
6881 #endif /* NETDUMP */