2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
45 * frames, highly configurable RX filtering, and 16 RX and TX queues
46 * (which, along with RX filter rules, can be used for QOS applications).
47 * Other features, such as TCP segmentation, may be available as part
48 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
49 * firmware images can be stored in hardware and need not be compiled
52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
55 * The BCM5701 is a single-chip solution incorporating both the BCM5700
56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
57 * does not support external SSRAM.
59 * Broadcom also produces a variation of the BCM5700 under the "Altima"
60 * brand name, which is functionally similar but lacks PCI-X support.
62 * Without external SSRAM, you can only have at most 4 TX rings,
63 * and the use of the mini RX ring is disabled. This seems to imply
64 * that these features are simply not available on the BCM5701. As a
65 * result, this driver does not implement any support for the mini RX
69 #ifdef HAVE_KERNEL_OPTION_HEADERS
70 #include "opt_device_polling.h"
73 #include <sys/param.h>
74 #include <sys/endian.h>
75 #include <sys/systm.h>
76 #include <sys/sockio.h>
78 #include <sys/malloc.h>
79 #include <sys/kernel.h>
80 #include <sys/module.h>
81 #include <sys/socket.h>
82 #include <sys/sysctl.h>
83 #include <sys/taskqueue.h>
86 #include <net/if_arp.h>
87 #include <net/ethernet.h>
88 #include <net/if_dl.h>
89 #include <net/if_media.h>
93 #include <net/if_types.h>
94 #include <net/if_vlan_var.h>
96 #include <netinet/in_systm.h>
97 #include <netinet/in.h>
98 #include <netinet/ip.h>
99 #include <netinet/tcp.h>
101 #include <machine/bus.h>
102 #include <machine/resource.h>
104 #include <sys/rman.h>
106 #include <dev/mii/mii.h>
107 #include <dev/mii/miivar.h>
109 #include <dev/mii/brgphyreg.h>
112 #include <dev/ofw/ofw_bus.h>
113 #include <dev/ofw/openfirm.h>
114 #include <machine/ofw_machdep.h>
115 #include <machine/ver.h>
118 #include <dev/pci/pcireg.h>
119 #include <dev/pci/pcivar.h>
121 #include <dev/bge/if_bgereg.h>
123 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
124 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
126 MODULE_DEPEND(bge, pci, 1, 1, 1);
127 MODULE_DEPEND(bge, ether, 1, 1, 1);
128 MODULE_DEPEND(bge, miibus, 1, 1, 1);
130 /* "device miibus" required. See GENERIC if you get errors here. */
131 #include "miibus_if.h"
134 * Various supported device vendors/types and their names. Note: the
135 * spec seems to indicate that the hardware still has Alteon's vendor
136 * ID burned into it, though it will always be overriden by the vendor
137 * ID in the EEPROM. Just to be safe, we cover all possibilities.
139 static const struct bge_type {
143 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 },
144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 },
146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 },
147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 },
148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 },
150 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 },
152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 },
153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 },
154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 },
155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT },
156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X },
157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 },
158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT },
159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X },
160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C },
161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S },
162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT },
163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 },
164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F },
165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K },
166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M },
167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT },
168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C },
169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S },
170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 },
171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S },
172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 },
173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 },
174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 },
175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 },
176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 },
177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M },
178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 },
179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F },
180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M },
181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 },
182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M },
183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 },
184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F },
185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M },
186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 },
187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M },
188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 },
189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M },
190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 },
191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 },
192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E },
193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S },
194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE },
195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 },
196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 },
197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S },
198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 },
199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 },
200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 },
201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F },
202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G },
203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 },
204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 },
205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F },
206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M },
207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 },
208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 },
209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 },
210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 },
211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M },
212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 },
213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M },
214 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 },
215 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 },
216 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 },
217 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 },
219 { SK_VENDORID, SK_DEVICEID_ALTIMA },
221 { TC_VENDORID, TC_DEVICEID_3C996 },
223 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 },
224 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 },
225 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 },
230 static const struct bge_vendor {
234 { ALTEON_VENDORID, "Alteon" },
235 { ALTIMA_VENDORID, "Altima" },
236 { APPLE_VENDORID, "Apple" },
237 { BCOM_VENDORID, "Broadcom" },
238 { SK_VENDORID, "SysKonnect" },
239 { TC_VENDORID, "3Com" },
240 { FJTSU_VENDORID, "Fujitsu" },
245 static const struct bge_revision {
248 } bge_revisions[] = {
249 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" },
250 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" },
251 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" },
252 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" },
253 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" },
254 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" },
255 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" },
256 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" },
257 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" },
258 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" },
259 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" },
260 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" },
261 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" },
262 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" },
263 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" },
264 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" },
265 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" },
266 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" },
267 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" },
268 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" },
269 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" },
270 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" },
271 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" },
272 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" },
273 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" },
274 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" },
275 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" },
276 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" },
277 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" },
278 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" },
279 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" },
280 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" },
281 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" },
282 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" },
283 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
284 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
285 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
286 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
287 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
288 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
289 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
290 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
291 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
292 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
293 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
294 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
295 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" },
296 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" },
297 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" },
298 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" },
299 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" },
300 /* 5754 and 5787 share the same ASIC ID */
301 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
302 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
303 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
304 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" },
305 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" },
306 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" },
307 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" },
313 * Some defaults for major revisions, so that newer steppings
314 * that we don't know about have a shot at working.
316 static const struct bge_revision bge_majorrevs[] = {
317 { BGE_ASICREV_BCM5700, "unknown BCM5700" },
318 { BGE_ASICREV_BCM5701, "unknown BCM5701" },
319 { BGE_ASICREV_BCM5703, "unknown BCM5703" },
320 { BGE_ASICREV_BCM5704, "unknown BCM5704" },
321 { BGE_ASICREV_BCM5705, "unknown BCM5705" },
322 { BGE_ASICREV_BCM5750, "unknown BCM5750" },
323 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
324 { BGE_ASICREV_BCM5752, "unknown BCM5752" },
325 { BGE_ASICREV_BCM5780, "unknown BCM5780" },
326 { BGE_ASICREV_BCM5714, "unknown BCM5714" },
327 { BGE_ASICREV_BCM5755, "unknown BCM5755" },
328 { BGE_ASICREV_BCM5761, "unknown BCM5761" },
329 { BGE_ASICREV_BCM5784, "unknown BCM5784" },
330 { BGE_ASICREV_BCM5785, "unknown BCM5785" },
331 /* 5754 and 5787 share the same ASIC ID */
332 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
333 { BGE_ASICREV_BCM5906, "unknown BCM5906" },
334 { BGE_ASICREV_BCM57780, "unknown BCM57780" },
339 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
340 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
341 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
342 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
343 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
344 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
346 const struct bge_revision * bge_lookup_rev(uint32_t);
347 const struct bge_vendor * bge_lookup_vendor(uint16_t);
349 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
351 static int bge_probe(device_t);
352 static int bge_attach(device_t);
353 static int bge_detach(device_t);
354 static int bge_suspend(device_t);
355 static int bge_resume(device_t);
356 static void bge_release_resources(struct bge_softc *);
357 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
358 static int bge_dma_alloc(device_t);
359 static void bge_dma_free(struct bge_softc *);
361 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
362 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
363 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
364 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
365 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
367 static void bge_txeof(struct bge_softc *, uint16_t);
368 static int bge_rxeof(struct bge_softc *, uint16_t, int);
370 static void bge_asf_driver_up (struct bge_softc *);
371 static void bge_tick(void *);
372 static void bge_stats_update(struct bge_softc *);
373 static void bge_stats_update_regs(struct bge_softc *);
374 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
376 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
378 static void bge_intr(void *);
379 static int bge_msi_intr(void *);
380 static void bge_intr_task(void *, int);
381 static void bge_start_locked(struct ifnet *);
382 static void bge_start(struct ifnet *);
383 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
384 static void bge_init_locked(struct bge_softc *);
385 static void bge_init(void *);
386 static void bge_stop(struct bge_softc *);
387 static void bge_watchdog(struct bge_softc *);
388 static int bge_shutdown(device_t);
389 static int bge_ifmedia_upd_locked(struct ifnet *);
390 static int bge_ifmedia_upd(struct ifnet *);
391 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
393 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
394 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
396 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
397 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
399 static void bge_setpromisc(struct bge_softc *);
400 static void bge_setmulti(struct bge_softc *);
401 static void bge_setvlan(struct bge_softc *);
403 static int bge_newbuf_std(struct bge_softc *, int);
404 static int bge_newbuf_jumbo(struct bge_softc *, int);
405 static int bge_init_rx_ring_std(struct bge_softc *);
406 static void bge_free_rx_ring_std(struct bge_softc *);
407 static int bge_init_rx_ring_jumbo(struct bge_softc *);
408 static void bge_free_rx_ring_jumbo(struct bge_softc *);
409 static void bge_free_tx_ring(struct bge_softc *);
410 static int bge_init_tx_ring(struct bge_softc *);
412 static int bge_chipinit(struct bge_softc *);
413 static int bge_blockinit(struct bge_softc *);
415 static int bge_has_eaddr(struct bge_softc *);
416 static uint32_t bge_readmem_ind(struct bge_softc *, int);
417 static void bge_writemem_ind(struct bge_softc *, int, int);
418 static void bge_writembx(struct bge_softc *, int, int);
420 static uint32_t bge_readreg_ind(struct bge_softc *, int);
422 static void bge_writemem_direct(struct bge_softc *, int, int);
423 static void bge_writereg_ind(struct bge_softc *, int, int);
424 static void bge_set_max_readrq(struct bge_softc *);
426 static int bge_miibus_readreg(device_t, int, int);
427 static int bge_miibus_writereg(device_t, int, int, int);
428 static void bge_miibus_statchg(device_t);
429 #ifdef DEVICE_POLLING
430 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
433 #define BGE_RESET_START 1
434 #define BGE_RESET_STOP 2
435 static void bge_sig_post_reset(struct bge_softc *, int);
436 static void bge_sig_legacy(struct bge_softc *, int);
437 static void bge_sig_pre_reset(struct bge_softc *, int);
438 static int bge_reset(struct bge_softc *);
439 static void bge_link_upd(struct bge_softc *);
442 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may
443 * leak information to untrusted users. It is also known to cause alignment
444 * traps on certain architectures.
446 #ifdef BGE_REGISTER_DEBUG
447 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
448 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
449 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
451 static void bge_add_sysctls(struct bge_softc *);
452 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
454 static device_method_t bge_methods[] = {
455 /* Device interface */
456 DEVMETHOD(device_probe, bge_probe),
457 DEVMETHOD(device_attach, bge_attach),
458 DEVMETHOD(device_detach, bge_detach),
459 DEVMETHOD(device_shutdown, bge_shutdown),
460 DEVMETHOD(device_suspend, bge_suspend),
461 DEVMETHOD(device_resume, bge_resume),
464 DEVMETHOD(bus_print_child, bus_generic_print_child),
465 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
468 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
469 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
470 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
475 static driver_t bge_driver = {
478 sizeof(struct bge_softc)
481 static devclass_t bge_devclass;
483 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
484 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
486 static int bge_allow_asf = 1;
488 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
490 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
491 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
492 "Allow ASF mode if available");
494 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500"
495 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2"
496 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500"
497 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3"
498 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id"
501 bge_has_eaddr(struct bge_softc *sc)
504 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
511 * The on-board BGEs found in sun4u machines aren't fitted with
512 * an EEPROM which means that we have to obtain the MAC address
513 * via OFW and that some tests will always fail. We distinguish
514 * such BGEs by the subvendor ID, which also has to be obtained
515 * from OFW instead of the PCI configuration space as the latter
516 * indicates Broadcom as the subvendor of the netboot interface.
517 * For early Blade 1500 and 2500 we even have to check the OFW
518 * device path as the subvendor ID always defaults to Broadcom
521 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
522 &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
523 subvendor == SUN_VENDORID)
525 memset(buf, 0, sizeof(buf));
526 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
527 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
528 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
530 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
531 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
539 bge_readmem_ind(struct bge_softc *sc, int off)
546 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
547 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
548 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
553 bge_writemem_ind(struct bge_softc *sc, int off, int val)
559 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
560 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
561 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
568 bge_set_max_readrq(struct bge_softc *sc)
575 val = pci_read_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
576 if ((val & PCIM_EXP_CTL_MAX_READ_REQUEST) !=
577 BGE_PCIE_DEVCTL_MAX_READRQ_4096) {
579 device_printf(dev, "adjust device control 0x%04x ",
581 val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST;
582 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096;
583 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL,
586 printf("-> 0x%04x\n", val);
592 bge_readreg_ind(struct bge_softc *sc, int off)
598 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
599 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
604 bge_writereg_ind(struct bge_softc *sc, int off, int val)
610 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
611 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
615 bge_writemem_direct(struct bge_softc *sc, int off, int val)
617 CSR_WRITE_4(sc, off, val);
621 bge_writembx(struct bge_softc *sc, int off, int val)
623 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
624 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
626 CSR_WRITE_4(sc, off, val);
630 * Map a single buffer address.
634 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
636 struct bge_dmamap_arg *ctx;
643 if (nseg > ctx->bge_maxsegs) {
644 ctx->bge_maxsegs = 0;
648 ctx->bge_busaddr = segs->ds_addr;
652 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
654 uint32_t access, byte = 0;
658 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
659 for (i = 0; i < 8000; i++) {
660 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
668 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
669 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
671 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
672 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
673 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
675 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
681 if (i == BGE_TIMEOUT * 10) {
682 if_printf(sc->bge_ifp, "nvram read timed out\n");
687 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
689 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
691 /* Disable access. */
692 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
695 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
696 CSR_READ_4(sc, BGE_NVRAM_SWARB);
702 * Read a sequence of bytes from NVRAM.
705 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
710 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
713 for (i = 0; i < cnt; i++) {
714 err = bge_nvram_getbyte(sc, off + i, &byte);
720 return (err ? 1 : 0);
724 * Read a byte of data stored in the EEPROM at address 'addr.' The
725 * BCM570x supports both the traditional bitbang interface and an
726 * auto access interface for reading the EEPROM. We use the auto
730 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
736 * Enable use of auto EEPROM access so we can avoid
737 * having to use the bitbang method.
739 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
741 /* Reset the EEPROM, load the clock period. */
742 CSR_WRITE_4(sc, BGE_EE_ADDR,
743 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
746 /* Issue the read EEPROM command. */
747 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
749 /* Wait for completion */
750 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
752 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
756 if (i == BGE_TIMEOUT * 10) {
757 device_printf(sc->bge_dev, "EEPROM read timed out\n");
762 byte = CSR_READ_4(sc, BGE_EE_DATA);
764 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
770 * Read a sequence of bytes from the EEPROM.
773 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
778 for (i = 0; i < cnt; i++) {
779 error = bge_eeprom_getbyte(sc, off + i, &byte);
785 return (error ? 1 : 0);
789 bge_miibus_readreg(device_t dev, int phy, int reg)
791 struct bge_softc *sc;
792 uint32_t val, autopoll;
795 sc = device_get_softc(dev);
798 * Broadcom's own driver always assumes the internal
799 * PHY is at GMII address 1. On some chips, the PHY responds
800 * to accesses at all addresses, which could cause us to
801 * bogusly attach the PHY 32 times at probe type. Always
802 * restricting the lookup to address 1 is simpler than
803 * trying to figure out which chips revisions should be
809 /* Reading with autopolling on may trigger PCI errors */
810 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
811 if (autopoll & BGE_MIMODE_AUTOPOLL) {
812 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
816 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
817 BGE_MIPHY(phy) | BGE_MIREG(reg));
819 for (i = 0; i < BGE_TIMEOUT; i++) {
821 val = CSR_READ_4(sc, BGE_MI_COMM);
822 if (!(val & BGE_MICOMM_BUSY))
826 if (i == BGE_TIMEOUT) {
827 device_printf(sc->bge_dev,
828 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
835 val = CSR_READ_4(sc, BGE_MI_COMM);
838 if (autopoll & BGE_MIMODE_AUTOPOLL) {
839 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
843 if (val & BGE_MICOMM_READFAIL)
846 return (val & 0xFFFF);
850 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
852 struct bge_softc *sc;
856 sc = device_get_softc(dev);
858 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
859 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
862 /* Reading with autopolling on may trigger PCI errors */
863 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
864 if (autopoll & BGE_MIMODE_AUTOPOLL) {
865 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
869 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
870 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
872 for (i = 0; i < BGE_TIMEOUT; i++) {
874 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
876 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
881 if (i == BGE_TIMEOUT) {
882 device_printf(sc->bge_dev,
883 "PHY write timed out (phy %d, reg %d, val %d)\n",
888 if (autopoll & BGE_MIMODE_AUTOPOLL) {
889 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
897 bge_miibus_statchg(device_t dev)
899 struct bge_softc *sc;
900 struct mii_data *mii;
901 sc = device_get_softc(dev);
902 mii = device_get_softc(sc->bge_miibus);
904 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
905 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
906 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
907 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
909 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
911 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
912 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
914 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
918 * Intialize a standard receive ring descriptor.
921 bge_newbuf_std(struct bge_softc *sc, int i)
925 bus_dma_segment_t segs[1];
929 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
932 m->m_len = m->m_pkthdr.len = MCLBYTES;
933 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
934 m_adj(m, ETHER_ALIGN);
936 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
937 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
942 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
943 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
944 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
945 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
946 sc->bge_cdata.bge_rx_std_dmamap[i]);
948 map = sc->bge_cdata.bge_rx_std_dmamap[i];
949 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
950 sc->bge_cdata.bge_rx_std_sparemap = map;
951 sc->bge_cdata.bge_rx_std_chain[i] = m;
952 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
953 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
954 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
955 r->bge_flags = BGE_RXBDFLAG_END;
956 r->bge_len = segs[0].ds_len;
959 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
960 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
966 * Initialize a jumbo receive ring descriptor. This allocates
967 * a jumbo buffer from the pool managed internally by the driver.
970 bge_newbuf_jumbo(struct bge_softc *sc, int i)
972 bus_dma_segment_t segs[BGE_NSEG_JUMBO];
974 struct bge_extrx_bd *r;
978 MGETHDR(m, M_DONTWAIT, MT_DATA);
982 m_cljget(m, M_DONTWAIT, MJUM9BYTES);
983 if (!(m->m_flags & M_EXT)) {
987 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
988 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
989 m_adj(m, ETHER_ALIGN);
991 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
992 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
998 if (sc->bge_cdata.bge_rx_jumbo_chain[i] == NULL) {
999 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1000 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1001 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1002 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1004 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1005 sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1006 sc->bge_cdata.bge_rx_jumbo_sparemap;
1007 sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1008 sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1010 * Fill in the extended RX buffer descriptor.
1012 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1013 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1015 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1018 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1019 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1020 r->bge_len3 = segs[3].ds_len;
1022 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1023 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1024 r->bge_len2 = segs[2].ds_len;
1026 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1027 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1028 r->bge_len1 = segs[1].ds_len;
1030 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1031 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1032 r->bge_len0 = segs[0].ds_len;
1035 panic("%s: %d segments\n", __func__, nsegs);
1038 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1039 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1045 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1046 * that's 1MB or memory, which is a lot. For now, we fill only the first
1047 * 256 ring entries and hope that our CPU is fast enough to keep up with
1051 bge_init_rx_ring_std(struct bge_softc *sc)
1055 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1057 for (i = 0; i < BGE_SSLOTS; i++) {
1058 if ((error = bge_newbuf_std(sc, i)) != 0)
1060 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1063 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1064 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1066 sc->bge_std = i - 1;
1067 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1073 bge_free_rx_ring_std(struct bge_softc *sc)
1077 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1078 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1079 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1080 sc->bge_cdata.bge_rx_std_dmamap[i],
1081 BUS_DMASYNC_POSTREAD);
1082 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1083 sc->bge_cdata.bge_rx_std_dmamap[i]);
1084 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1085 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1087 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1088 sizeof(struct bge_rx_bd));
1093 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1095 struct bge_rcb *rcb;
1098 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1100 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1101 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1103 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1106 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1107 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1109 sc->bge_jumbo = i - 1;
1111 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1112 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1113 BGE_RCB_FLAG_USE_EXT_RX_BD);
1114 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1116 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1122 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1126 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1127 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1128 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1129 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1130 BUS_DMASYNC_POSTREAD);
1131 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1132 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1133 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1134 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1136 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1137 sizeof(struct bge_extrx_bd));
1142 bge_free_tx_ring(struct bge_softc *sc)
1146 if (sc->bge_ldata.bge_tx_ring == NULL)
1149 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1150 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1151 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1152 sc->bge_cdata.bge_tx_dmamap[i],
1153 BUS_DMASYNC_POSTWRITE);
1154 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1155 sc->bge_cdata.bge_tx_dmamap[i]);
1156 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1157 sc->bge_cdata.bge_tx_chain[i] = NULL;
1159 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1160 sizeof(struct bge_tx_bd));
1165 bge_init_tx_ring(struct bge_softc *sc)
1168 sc->bge_tx_saved_considx = 0;
1170 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1171 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1172 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1174 /* Initialize transmit producer index for host-memory send ring. */
1175 sc->bge_tx_prodidx = 0;
1176 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1178 /* 5700 b2 errata */
1179 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1180 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1182 /* NIC-memory send ring not used; initialize to zero. */
1183 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1184 /* 5700 b2 errata */
1185 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1186 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1192 bge_setpromisc(struct bge_softc *sc)
1196 BGE_LOCK_ASSERT(sc);
1200 /* Enable or disable promiscuous mode as needed. */
1201 if (ifp->if_flags & IFF_PROMISC)
1202 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1204 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1208 bge_setmulti(struct bge_softc *sc)
1211 struct ifmultiaddr *ifma;
1212 uint32_t hashes[4] = { 0, 0, 0, 0 };
1215 BGE_LOCK_ASSERT(sc);
1219 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1220 for (i = 0; i < 4; i++)
1221 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1225 /* First, zot all the existing filters. */
1226 for (i = 0; i < 4; i++)
1227 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1229 /* Now program new ones. */
1230 if_maddr_rlock(ifp);
1231 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1232 if (ifma->ifma_addr->sa_family != AF_LINK)
1234 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1235 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1236 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1238 if_maddr_runlock(ifp);
1240 for (i = 0; i < 4; i++)
1241 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1245 bge_setvlan(struct bge_softc *sc)
1249 BGE_LOCK_ASSERT(sc);
1253 /* Enable or disable VLAN tag stripping as needed. */
1254 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1255 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1257 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1261 bge_sig_pre_reset(sc, type)
1262 struct bge_softc *sc;
1266 * Some chips don't like this so only do this if ASF is enabled
1268 if (sc->bge_asf_mode)
1269 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1271 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1273 case BGE_RESET_START:
1274 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1276 case BGE_RESET_STOP:
1277 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1284 bge_sig_post_reset(sc, type)
1285 struct bge_softc *sc;
1288 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1290 case BGE_RESET_START:
1291 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001);
1294 case BGE_RESET_STOP:
1295 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002);
1302 bge_sig_legacy(sc, type)
1303 struct bge_softc *sc;
1306 if (sc->bge_asf_mode) {
1308 case BGE_RESET_START:
1309 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1311 case BGE_RESET_STOP:
1312 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1318 void bge_stop_fw(struct bge_softc *);
1321 struct bge_softc *sc;
1325 if (sc->bge_asf_mode) {
1326 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE);
1327 CSR_WRITE_4(sc, BGE_CPU_EVENT,
1328 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
1330 for (i = 0; i < 100; i++ ) {
1331 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14)))
1339 * Do endian, PCI and DMA initialization.
1342 bge_chipinit(struct bge_softc *sc)
1344 uint32_t dma_rw_ctl;
1347 /* Set endianness before we access any non-PCI registers. */
1348 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1350 /* Clear the MAC control register */
1351 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1354 * Clear the MAC statistics block in the NIC's
1357 for (i = BGE_STATS_BLOCK;
1358 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1359 BGE_MEMWIN_WRITE(sc, i, 0);
1361 for (i = BGE_STATUS_BLOCK;
1362 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1363 BGE_MEMWIN_WRITE(sc, i, 0);
1366 * Set up the PCI DMA control register.
1368 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1369 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1370 if (sc->bge_flags & BGE_FLAG_PCIE) {
1371 /* Read watermark not used, 128 bytes for write. */
1372 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1373 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1374 if (BGE_IS_5714_FAMILY(sc)) {
1375 /* 256 bytes for read and write. */
1376 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1377 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1378 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1379 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1380 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1381 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1382 /* 1536 bytes for read, 384 bytes for write. */
1383 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1384 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1386 /* 384 bytes for read and write. */
1387 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1388 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1391 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1392 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1395 /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1396 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1397 if (tmp == 6 || tmp == 7)
1399 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1401 /* Set PCI-X DMA write workaround. */
1402 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1405 /* Conventional PCI bus: 256 bytes for read and write. */
1406 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1407 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1409 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1410 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1413 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1414 sc->bge_asicrev == BGE_ASICREV_BCM5701)
1415 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1416 BGE_PCIDMARWCTL_ASRT_ALL_BE;
1417 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1418 sc->bge_asicrev == BGE_ASICREV_BCM5704)
1419 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1420 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1423 * Set up general mode register.
1425 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
1426 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1427 BGE_MODECTL_TX_NO_PHDR_CSUM);
1430 * BCM5701 B5 have a bug causing data corruption when using
1431 * 64-bit DMA reads, which can be terminated early and then
1432 * completed later as 32-bit accesses, in combination with
1435 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1436 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1437 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1440 * Tell the firmware the driver is running
1442 if (sc->bge_asf_mode & ASF_STACKUP)
1443 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
1446 * Disable memory write invalidate. Apparently it is not supported
1447 * properly by these devices. Also ensure that INTx isn't disabled,
1448 * as these chips need it even when using MSI.
1450 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1451 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
1453 /* Set the timer prescaler (always 66Mhz) */
1454 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1456 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1457 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1458 DELAY(40); /* XXX */
1460 /* Put PHY into ready state */
1461 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1462 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1470 bge_blockinit(struct bge_softc *sc)
1472 struct bge_rcb *rcb;
1479 * Initialize the memory window pointer register so that
1480 * we can access the first 32K of internal NIC RAM. This will
1481 * allow us to set up the TX send ring RCBs and the RX return
1482 * ring RCBs, plus other things which live in NIC memory.
1484 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1486 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1488 if (!(BGE_IS_5705_PLUS(sc))) {
1489 /* Configure mbuf memory pool */
1490 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1491 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1492 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1494 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1496 /* Configure DMA resource pool */
1497 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1498 BGE_DMA_DESCRIPTORS);
1499 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1502 /* Configure mbuf pool watermarks */
1503 if (!BGE_IS_5705_PLUS(sc)) {
1504 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1505 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1506 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1507 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1508 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1509 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1510 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1512 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1513 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1514 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1517 /* Configure DMA resource watermarks */
1518 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1519 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1521 /* Enable buffer manager */
1522 if (!(BGE_IS_5705_PLUS(sc))) {
1523 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1524 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN);
1526 /* Poll for buffer manager start indication */
1527 for (i = 0; i < BGE_TIMEOUT; i++) {
1529 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1533 if (i == BGE_TIMEOUT) {
1534 device_printf(sc->bge_dev,
1535 "buffer manager failed to start\n");
1540 /* Enable flow-through queues */
1541 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1542 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1544 /* Wait until queue initialization is complete */
1545 for (i = 0; i < BGE_TIMEOUT; i++) {
1547 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1551 if (i == BGE_TIMEOUT) {
1552 device_printf(sc->bge_dev, "flow-through queue init failed\n");
1556 /* Initialize the standard RX ring control block */
1557 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1558 rcb->bge_hostaddr.bge_addr_lo =
1559 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1560 rcb->bge_hostaddr.bge_addr_hi =
1561 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1562 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1563 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1564 if (BGE_IS_5705_PLUS(sc))
1565 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1567 rcb->bge_maxlen_flags =
1568 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1569 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1570 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1571 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1573 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1574 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1577 * Initialize the jumbo RX ring control block
1578 * We set the 'ring disabled' bit in the flags
1579 * field until we're actually ready to start
1580 * using this ring (i.e. once we set the MTU
1581 * high enough to require it).
1583 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1584 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1586 rcb->bge_hostaddr.bge_addr_lo =
1587 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1588 rcb->bge_hostaddr.bge_addr_hi =
1589 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1590 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1591 sc->bge_cdata.bge_rx_jumbo_ring_map,
1592 BUS_DMASYNC_PREREAD);
1593 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1594 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1595 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1596 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1597 rcb->bge_hostaddr.bge_addr_hi);
1598 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1599 rcb->bge_hostaddr.bge_addr_lo);
1601 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1602 rcb->bge_maxlen_flags);
1603 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1605 /* Set up dummy disabled mini ring RCB */
1606 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1607 rcb->bge_maxlen_flags =
1608 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1609 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1610 rcb->bge_maxlen_flags);
1614 * Set the BD ring replentish thresholds. The recommended
1615 * values are 1/8th the number of descriptors allocated to
1617 * XXX The 5754 requires a lower threshold, so it might be a
1618 * requirement of all 575x family chips. The Linux driver sets
1619 * the lower threshold for all 5705 family chips as well, but there
1620 * are reports that it might not need to be so strict.
1622 * XXX Linux does some extra fiddling here for the 5906 parts as
1625 if (BGE_IS_5705_PLUS(sc))
1628 val = BGE_STD_RX_RING_CNT / 8;
1629 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1630 if (BGE_IS_JUMBO_CAPABLE(sc))
1631 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1632 BGE_JUMBO_RX_RING_CNT/8);
1635 * Disable all unused send rings by setting the 'ring disabled'
1636 * bit in the flags field of all the TX send ring control blocks.
1637 * These are located in NIC memory.
1639 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1640 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1641 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1642 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1643 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1644 vrcb += sizeof(struct bge_rcb);
1647 /* Configure TX RCB 0 (we use only the first ring) */
1648 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1649 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1650 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1651 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1652 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1653 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1654 if (!(BGE_IS_5705_PLUS(sc)))
1655 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1656 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1658 /* Disable all unused RX return rings */
1659 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1660 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1661 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1662 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1663 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1664 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1665 BGE_RCB_FLAG_RING_DISABLED));
1666 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1667 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1668 (i * (sizeof(uint64_t))), 0);
1669 vrcb += sizeof(struct bge_rcb);
1672 /* Initialize RX ring indexes */
1673 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1674 if (BGE_IS_JUMBO_CAPABLE(sc))
1675 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1676 if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1677 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1680 * Set up RX return ring 0
1681 * Note that the NIC address for RX return rings is 0x00000000.
1682 * The return rings live entirely within the host, so the
1683 * nicaddr field in the RCB isn't used.
1685 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1686 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1687 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1688 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1689 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1690 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1691 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1693 /* Set random backoff seed for TX */
1694 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1695 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1696 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1697 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1698 BGE_TX_BACKOFF_SEED_MASK);
1700 /* Set inter-packet gap */
1701 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1704 * Specify which ring to use for packets that don't match
1707 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1710 * Configure number of RX lists. One interrupt distribution
1711 * list, sixteen active lists, one bad frames class.
1713 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1715 /* Inialize RX list placement stats mask. */
1716 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1717 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1719 /* Disable host coalescing until we get it set up */
1720 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1722 /* Poll to make sure it's shut down. */
1723 for (i = 0; i < BGE_TIMEOUT; i++) {
1725 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1729 if (i == BGE_TIMEOUT) {
1730 device_printf(sc->bge_dev,
1731 "host coalescing engine failed to idle\n");
1735 /* Set up host coalescing defaults */
1736 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1737 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1738 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1739 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1740 if (!(BGE_IS_5705_PLUS(sc))) {
1741 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1742 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1744 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1745 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1747 /* Set up address of statistics block */
1748 if (!(BGE_IS_5705_PLUS(sc))) {
1749 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1750 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1751 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1752 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1753 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1754 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1755 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1758 /* Set up address of status block */
1759 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1760 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1761 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1762 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1763 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1764 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1766 /* Set up status block size. */
1767 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1768 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
1769 val = BGE_STATBLKSZ_FULL;
1771 val = BGE_STATBLKSZ_32BYTE;
1773 /* Turn on host coalescing state machine */
1774 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1776 /* Turn on RX BD completion state machine and enable attentions */
1777 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1778 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
1780 /* Turn on RX list placement state machine */
1781 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1783 /* Turn on RX list selector state machine. */
1784 if (!(BGE_IS_5705_PLUS(sc)))
1785 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1787 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1788 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1789 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1790 BGE_MACMODE_FRMHDR_DMA_ENB;
1792 if (sc->bge_flags & BGE_FLAG_TBI)
1793 val |= BGE_PORTMODE_TBI;
1794 else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1795 val |= BGE_PORTMODE_GMII;
1797 val |= BGE_PORTMODE_MII;
1799 /* Turn on DMA, clear stats */
1800 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1802 /* Set misc. local control, enable interrupts on attentions */
1803 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1806 /* Assert GPIO pins for PHY reset */
1807 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
1808 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
1809 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
1810 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
1813 /* Turn on DMA completion state machine */
1814 if (!(BGE_IS_5705_PLUS(sc)))
1815 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1817 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
1819 /* Enable host coalescing bug fix. */
1820 if (BGE_IS_5755_PLUS(sc))
1821 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1823 /* Turn on write DMA state machine */
1824 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1827 /* Turn on read DMA state machine */
1828 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1829 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1830 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1831 sc->bge_asicrev == BGE_ASICREV_BCM57780)
1832 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1833 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1834 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1835 if (sc->bge_flags & BGE_FLAG_PCIE)
1836 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1837 if (sc->bge_flags & BGE_FLAG_TSO)
1838 val |= BGE_RDMAMODE_TSO4_ENABLE;
1839 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1842 /* Turn on RX data completion state machine */
1843 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1845 /* Turn on RX BD initiator state machine */
1846 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1848 /* Turn on RX data and RX BD initiator state machine */
1849 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1851 /* Turn on Mbuf cluster free state machine */
1852 if (!(BGE_IS_5705_PLUS(sc)))
1853 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1855 /* Turn on send BD completion state machine */
1856 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1858 /* Turn on send data completion state machine */
1859 val = BGE_SDCMODE_ENABLE;
1860 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1861 val |= BGE_SDCMODE_CDELAY;
1862 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1864 /* Turn on send data initiator state machine */
1865 if (sc->bge_flags & BGE_FLAG_TSO)
1866 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08);
1868 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1870 /* Turn on send BD initiator state machine */
1871 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1873 /* Turn on send BD selector state machine */
1874 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1876 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1877 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1878 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
1880 /* ack/clear link change events */
1881 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1882 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1883 BGE_MACSTAT_LINK_CHANGED);
1884 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1886 /* Enable PHY auto polling (for MII/GMII only) */
1887 if (sc->bge_flags & BGE_FLAG_TBI) {
1888 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1890 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16));
1891 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1892 sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
1893 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1894 BGE_EVTENB_MI_INTERRUPT);
1898 * Clear any pending link state attention.
1899 * Otherwise some link state change events may be lost until attention
1900 * is cleared by bge_intr() -> bge_link_upd() sequence.
1901 * It's not necessary on newer BCM chips - perhaps enabling link
1902 * state change attentions implies clearing pending attention.
1904 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1905 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1906 BGE_MACSTAT_LINK_CHANGED);
1908 /* Enable link state change attentions. */
1909 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1914 const struct bge_revision *
1915 bge_lookup_rev(uint32_t chipid)
1917 const struct bge_revision *br;
1919 for (br = bge_revisions; br->br_name != NULL; br++) {
1920 if (br->br_chipid == chipid)
1924 for (br = bge_majorrevs; br->br_name != NULL; br++) {
1925 if (br->br_chipid == BGE_ASICREV(chipid))
1932 const struct bge_vendor *
1933 bge_lookup_vendor(uint16_t vid)
1935 const struct bge_vendor *v;
1937 for (v = bge_vendors; v->v_name != NULL; v++)
1941 panic("%s: unknown vendor %d", __func__, vid);
1946 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1947 * against our list and return its name if we find a match.
1949 * Note that since the Broadcom controller contains VPD support, we
1950 * try to get the device name string from the controller itself instead
1951 * of the compiled-in string. It guarantees we'll always announce the
1952 * right product name. We fall back to the compiled-in string when
1953 * VPD is unavailable or corrupt.
1956 bge_probe(device_t dev)
1958 const struct bge_type *t = bge_devs;
1959 struct bge_softc *sc = device_get_softc(dev);
1963 vid = pci_get_vendor(dev);
1964 did = pci_get_device(dev);
1965 while(t->bge_vid != 0) {
1966 if ((vid == t->bge_vid) && (did == t->bge_did)) {
1967 char model[64], buf[96];
1968 const struct bge_revision *br;
1969 const struct bge_vendor *v;
1972 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1973 BGE_PCIMISCCTL_ASICREV_SHIFT;
1974 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG)
1975 id = pci_read_config(dev,
1976 BGE_PCI_PRODID_ASICREV, 4);
1977 br = bge_lookup_rev(id);
1978 v = bge_lookup_vendor(vid);
1980 #if __FreeBSD_version > 700024
1983 if (bge_has_eaddr(sc) &&
1984 pci_get_vpd_ident(dev, &pname) == 0)
1985 snprintf(model, 64, "%s", pname);
1988 snprintf(model, 64, "%s %s",
1990 br != NULL ? br->br_name :
1991 "NetXtreme Ethernet Controller");
1993 snprintf(buf, 96, "%s, %sASIC rev. %#08x", model,
1994 br != NULL ? "" : "unknown ", id);
1995 device_set_desc_copy(dev, buf);
2005 bge_dma_free(struct bge_softc *sc)
2009 /* Destroy DMA maps for RX buffers. */
2010 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2011 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2012 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2013 sc->bge_cdata.bge_rx_std_dmamap[i]);
2015 if (sc->bge_cdata.bge_rx_std_sparemap)
2016 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2017 sc->bge_cdata.bge_rx_std_sparemap);
2019 /* Destroy DMA maps for jumbo RX buffers. */
2020 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2021 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2022 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2023 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2025 if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2026 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2027 sc->bge_cdata.bge_rx_jumbo_sparemap);
2029 /* Destroy DMA maps for TX buffers. */
2030 for (i = 0; i < BGE_TX_RING_CNT; i++) {
2031 if (sc->bge_cdata.bge_tx_dmamap[i])
2032 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2033 sc->bge_cdata.bge_tx_dmamap[i]);
2036 if (sc->bge_cdata.bge_rx_mtag)
2037 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2038 if (sc->bge_cdata.bge_tx_mtag)
2039 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2042 /* Destroy standard RX ring. */
2043 if (sc->bge_cdata.bge_rx_std_ring_map)
2044 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2045 sc->bge_cdata.bge_rx_std_ring_map);
2046 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
2047 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2048 sc->bge_ldata.bge_rx_std_ring,
2049 sc->bge_cdata.bge_rx_std_ring_map);
2051 if (sc->bge_cdata.bge_rx_std_ring_tag)
2052 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2054 /* Destroy jumbo RX ring. */
2055 if (sc->bge_cdata.bge_rx_jumbo_ring_map)
2056 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2057 sc->bge_cdata.bge_rx_jumbo_ring_map);
2059 if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
2060 sc->bge_ldata.bge_rx_jumbo_ring)
2061 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2062 sc->bge_ldata.bge_rx_jumbo_ring,
2063 sc->bge_cdata.bge_rx_jumbo_ring_map);
2065 if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2066 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2068 /* Destroy RX return ring. */
2069 if (sc->bge_cdata.bge_rx_return_ring_map)
2070 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2071 sc->bge_cdata.bge_rx_return_ring_map);
2073 if (sc->bge_cdata.bge_rx_return_ring_map &&
2074 sc->bge_ldata.bge_rx_return_ring)
2075 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2076 sc->bge_ldata.bge_rx_return_ring,
2077 sc->bge_cdata.bge_rx_return_ring_map);
2079 if (sc->bge_cdata.bge_rx_return_ring_tag)
2080 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2082 /* Destroy TX ring. */
2083 if (sc->bge_cdata.bge_tx_ring_map)
2084 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2085 sc->bge_cdata.bge_tx_ring_map);
2087 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
2088 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2089 sc->bge_ldata.bge_tx_ring,
2090 sc->bge_cdata.bge_tx_ring_map);
2092 if (sc->bge_cdata.bge_tx_ring_tag)
2093 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2095 /* Destroy status block. */
2096 if (sc->bge_cdata.bge_status_map)
2097 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2098 sc->bge_cdata.bge_status_map);
2100 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
2101 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2102 sc->bge_ldata.bge_status_block,
2103 sc->bge_cdata.bge_status_map);
2105 if (sc->bge_cdata.bge_status_tag)
2106 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2108 /* Destroy statistics block. */
2109 if (sc->bge_cdata.bge_stats_map)
2110 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2111 sc->bge_cdata.bge_stats_map);
2113 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2114 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2115 sc->bge_ldata.bge_stats,
2116 sc->bge_cdata.bge_stats_map);
2118 if (sc->bge_cdata.bge_stats_tag)
2119 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2121 /* Destroy the parent tag. */
2122 if (sc->bge_cdata.bge_parent_tag)
2123 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2127 bge_dma_alloc(device_t dev)
2129 struct bge_dmamap_arg ctx;
2130 struct bge_softc *sc;
2132 bus_size_t sbsz, txsegsz, txmaxsegsz;
2135 sc = device_get_softc(dev);
2137 lowaddr = BUS_SPACE_MAXADDR;
2138 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2139 lowaddr = BGE_DMA_MAXADDR;
2140 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0)
2141 lowaddr = BUS_SPACE_MAXADDR_32BIT;
2143 * Allocate the parent bus DMA tag appropriate for PCI.
2145 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2146 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2147 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2148 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2151 device_printf(sc->bge_dev,
2152 "could not allocate parent dma tag\n");
2157 * Create tag for Tx mbufs.
2159 if (sc->bge_flags & BGE_FLAG_TSO) {
2160 txsegsz = BGE_TSOSEG_SZ;
2161 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
2164 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
2166 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1,
2167 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2168 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
2169 &sc->bge_cdata.bge_tx_mtag);
2172 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
2177 * Create tag for Rx mbufs.
2179 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
2180 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
2181 MCLBYTES, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
2184 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
2188 /* Create DMA maps for RX buffers. */
2189 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2190 &sc->bge_cdata.bge_rx_std_sparemap);
2192 device_printf(sc->bge_dev,
2193 "can't create spare DMA map for RX\n");
2196 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2197 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2198 &sc->bge_cdata.bge_rx_std_dmamap[i]);
2200 device_printf(sc->bge_dev,
2201 "can't create DMA map for RX\n");
2206 /* Create DMA maps for TX buffers. */
2207 for (i = 0; i < BGE_TX_RING_CNT; i++) {
2208 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
2209 &sc->bge_cdata.bge_tx_dmamap[i]);
2211 device_printf(sc->bge_dev,
2212 "can't create DMA map for TX\n");
2217 /* Create tag for standard RX ring. */
2218 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2219 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2220 NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0,
2221 NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag);
2224 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2228 /* Allocate DMA'able memory for standard RX ring. */
2229 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag,
2230 (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT,
2231 &sc->bge_cdata.bge_rx_std_ring_map);
2235 bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
2237 /* Load the address of the standard RX ring. */
2238 ctx.bge_maxsegs = 1;
2241 error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag,
2242 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring,
2243 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2248 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr;
2250 /* Create tags for jumbo mbufs. */
2251 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2252 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2253 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2254 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
2255 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
2257 device_printf(sc->bge_dev,
2258 "could not allocate jumbo dma tag\n");
2262 /* Create tag for jumbo RX ring. */
2263 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2264 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2265 NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0,
2266 NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag);
2269 device_printf(sc->bge_dev,
2270 "could not allocate jumbo ring dma tag\n");
2274 /* Allocate DMA'able memory for jumbo RX ring. */
2275 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2276 (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
2277 BUS_DMA_NOWAIT | BUS_DMA_ZERO,
2278 &sc->bge_cdata.bge_rx_jumbo_ring_map);
2282 /* Load the address of the jumbo RX ring. */
2283 ctx.bge_maxsegs = 1;
2286 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2287 sc->bge_cdata.bge_rx_jumbo_ring_map,
2288 sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ,
2289 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2294 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr;
2296 /* Create DMA maps for jumbo RX buffers. */
2297 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2298 0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
2300 device_printf(sc->bge_dev,
2301 "can't create spare DMA map for jumbo RX\n");
2304 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2305 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2306 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2308 device_printf(sc->bge_dev,
2309 "can't create DMA map for jumbo RX\n");
2316 /* Create tag for RX return ring. */
2317 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2318 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2319 NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0,
2320 NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag);
2323 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2327 /* Allocate DMA'able memory for RX return ring. */
2328 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag,
2329 (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT,
2330 &sc->bge_cdata.bge_rx_return_ring_map);
2334 bzero((char *)sc->bge_ldata.bge_rx_return_ring,
2335 BGE_RX_RTN_RING_SZ(sc));
2337 /* Load the address of the RX return ring. */
2338 ctx.bge_maxsegs = 1;
2341 error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag,
2342 sc->bge_cdata.bge_rx_return_ring_map,
2343 sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc),
2344 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2349 sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr;
2351 /* Create tag for TX ring. */
2352 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2353 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2354 NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL,
2355 &sc->bge_cdata.bge_tx_ring_tag);
2358 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2362 /* Allocate DMA'able memory for TX ring. */
2363 error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag,
2364 (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT,
2365 &sc->bge_cdata.bge_tx_ring_map);
2369 bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
2371 /* Load the address of the TX ring. */
2372 ctx.bge_maxsegs = 1;
2375 error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag,
2376 sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring,
2377 BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2382 sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr;
2385 * Create tag for status block.
2386 * Because we only use single Tx/Rx/Rx return ring, use
2387 * minimum status block size except BCM5700 AX/BX which
2388 * seems to want to see full status block size regardless
2389 * of configured number of ring.
2391 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2392 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
2393 sbsz = BGE_STATUS_BLK_SZ;
2396 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2397 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2398 NULL, sbsz, 1, sbsz, 0, NULL, NULL, &sc->bge_cdata.bge_status_tag);
2401 device_printf(sc->bge_dev,
2402 "could not allocate status dma tag\n");
2406 /* Allocate DMA'able memory for status block. */
2407 error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag,
2408 (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT,
2409 &sc->bge_cdata.bge_status_map);
2413 bzero((char *)sc->bge_ldata.bge_status_block, sbsz);
2415 /* Load the address of the status block. */
2417 ctx.bge_maxsegs = 1;
2419 error = bus_dmamap_load(sc->bge_cdata.bge_status_tag,
2420 sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block,
2421 sbsz, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2426 sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr;
2428 /* Create tag for statistics block. */
2429 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2430 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2431 NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL,
2432 &sc->bge_cdata.bge_stats_tag);
2435 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2439 /* Allocate DMA'able memory for statistics block. */
2440 error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag,
2441 (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT,
2442 &sc->bge_cdata.bge_stats_map);
2446 bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ);
2448 /* Load the address of the statstics block. */
2450 ctx.bge_maxsegs = 1;
2452 error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag,
2453 sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats,
2454 BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2459 sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr;
2465 * Return true if this device has more than one port.
2468 bge_has_multiple_ports(struct bge_softc *sc)
2470 device_t dev = sc->bge_dev;
2471 u_int b, d, f, fscan, s;
2473 d = pci_get_domain(dev);
2474 b = pci_get_bus(dev);
2475 s = pci_get_slot(dev);
2476 f = pci_get_function(dev);
2477 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
2478 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
2484 * Return true if MSI can be used with this device.
2487 bge_can_use_msi(struct bge_softc *sc)
2489 int can_use_msi = 0;
2491 switch (sc->bge_asicrev) {
2492 case BGE_ASICREV_BCM5714_A0:
2493 case BGE_ASICREV_BCM5714:
2495 * Apparently, MSI doesn't work when these chips are
2496 * configured in single-port mode.
2498 if (bge_has_multiple_ports(sc))
2501 case BGE_ASICREV_BCM5750:
2502 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
2503 sc->bge_chiprev != BGE_CHIPREV_5750_BX)
2507 if (BGE_IS_575X_PLUS(sc))
2510 return (can_use_msi);
2514 bge_attach(device_t dev)
2517 struct bge_softc *sc;
2518 uint32_t hwcfg = 0, misccfg;
2519 u_char eaddr[ETHER_ADDR_LEN];
2520 int error, msicount, reg, rid, trys;
2522 sc = device_get_softc(dev);
2525 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
2528 * Map control/status registers.
2530 pci_enable_busmaster(dev);
2533 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2536 if (sc->bge_res == NULL) {
2537 device_printf (sc->bge_dev, "couldn't map memory\n");
2542 /* Save various chip information. */
2544 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2545 BGE_PCIMISCCTL_ASICREV_SHIFT;
2546 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
2547 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV,
2549 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2550 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2553 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the
2554 * 5705 A0 and A1 chips.
2556 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
2557 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2558 sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2559 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)
2560 sc->bge_flags |= BGE_FLAG_WIRESPEED;
2562 if (bge_has_eaddr(sc))
2563 sc->bge_flags |= BGE_FLAG_EADDR;
2565 /* Save chipset family. */
2566 switch (sc->bge_asicrev) {
2567 case BGE_ASICREV_BCM5755:
2568 case BGE_ASICREV_BCM5761:
2569 case BGE_ASICREV_BCM5784:
2570 case BGE_ASICREV_BCM5785:
2571 case BGE_ASICREV_BCM5787:
2572 case BGE_ASICREV_BCM57780:
2573 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2576 case BGE_ASICREV_BCM5700:
2577 case BGE_ASICREV_BCM5701:
2578 case BGE_ASICREV_BCM5703:
2579 case BGE_ASICREV_BCM5704:
2580 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2582 case BGE_ASICREV_BCM5714_A0:
2583 case BGE_ASICREV_BCM5780:
2584 case BGE_ASICREV_BCM5714:
2585 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */;
2587 case BGE_ASICREV_BCM5750:
2588 case BGE_ASICREV_BCM5752:
2589 case BGE_ASICREV_BCM5906:
2590 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2592 case BGE_ASICREV_BCM5705:
2593 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2597 /* Set various bug flags. */
2598 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2599 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2600 sc->bge_flags |= BGE_FLAG_CRC_BUG;
2601 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2602 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2603 sc->bge_flags |= BGE_FLAG_ADC_BUG;
2604 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2605 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
2606 if (pci_get_subvendor(dev) == DELL_VENDORID)
2607 sc->bge_flags |= BGE_FLAG_NO_3LED;
2608 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
2609 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
2610 if (BGE_IS_5705_PLUS(sc) &&
2611 !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) {
2612 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2613 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2614 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2615 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2616 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
2617 pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
2618 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
2619 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
2620 sc->bge_flags |= BGE_FLAG_BER_BUG;
2624 * All controllers that are not 5755 or higher have 4GB
2626 * Whenever an address crosses a multiple of the 4GB boundary
2627 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
2628 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
2629 * state machine will lockup and cause the device to hang.
2631 if (BGE_IS_5755_PLUS(sc) == 0)
2632 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
2635 * We could possibly check for BCOM_DEVICEID_BCM5788 in bge_probe()
2636 * but I do not know the DEVICEID for the 5788M.
2638 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID;
2639 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2640 misccfg == BGE_MISCCFG_BOARD_ID_5788M)
2641 sc->bge_flags |= BGE_FLAG_5788;
2644 * Some controllers seem to require a special firmware to use
2645 * TSO. But the firmware is not available to FreeBSD and Linux
2646 * claims that the TSO performed by the firmware is slower than
2647 * hardware based TSO. Moreover the firmware based TSO has one
2648 * known bug which can't handle TSO if ethernet header + IP/TCP
2649 * header is greater than 80 bytes. The workaround for the TSO
2650 * bug exist but it seems it's too expensive than not using
2651 * TSO at all. Some hardwares also have the TSO bug so limit
2652 * the TSO to the controllers that are not affected TSO issues
2653 * (e.g. 5755 or higher).
2655 if (BGE_IS_5755_PLUS(sc)) {
2657 * BCM5754 and BCM5787 shares the same ASIC id so
2658 * explicit device id check is required.
2659 * Due to unknown reason TSO does not work on BCM5755M.
2661 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
2662 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
2663 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
2664 sc->bge_flags |= BGE_FLAG_TSO;
2668 * Check if this is a PCI-X or PCI Express device.
2670 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
2672 * Found a PCI Express capabilities register, this
2673 * must be a PCI Express device.
2675 sc->bge_flags |= BGE_FLAG_PCIE;
2676 sc->bge_expcap = reg;
2677 bge_set_max_readrq(sc);
2680 * Check if the device is in PCI-X Mode.
2681 * (This bit is not valid on PCI Express controllers.)
2683 if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0)
2684 sc->bge_pcixcap = reg;
2685 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
2686 BGE_PCISTATE_PCI_BUSMODE) == 0)
2687 sc->bge_flags |= BGE_FLAG_PCIX;
2691 * The 40bit DMA bug applies to the 5714/5715 controllers and is
2692 * not actually a MAC controller bug but an issue with the embedded
2693 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2695 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
2696 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
2698 * Allocate the interrupt, using MSI if possible. These devices
2699 * support 8 MSI messages, but only the first one is used in
2703 if (pci_find_extcap(sc->bge_dev, PCIY_MSI, ®) == 0) {
2704 sc->bge_msicap = reg;
2705 if (bge_can_use_msi(sc)) {
2706 msicount = pci_msi_count(dev);
2711 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
2713 sc->bge_flags |= BGE_FLAG_MSI;
2717 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2718 RF_SHAREABLE | RF_ACTIVE);
2720 if (sc->bge_irq == NULL) {
2721 device_printf(sc->bge_dev, "couldn't map interrupt\n");
2728 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2729 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2730 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" :
2731 ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI"));
2733 BGE_LOCK_INIT(sc, device_get_nameunit(dev));
2735 /* Try to reset the chip. */
2736 if (bge_reset(sc)) {
2737 device_printf(sc->bge_dev, "chip reset failed\n");
2742 sc->bge_asf_mode = 0;
2743 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG)
2744 == BGE_MAGIC_NUMBER)) {
2745 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG)
2747 sc->bge_asf_mode |= ASF_ENABLE;
2748 sc->bge_asf_mode |= ASF_STACKUP;
2749 if (BGE_IS_575X_PLUS(sc))
2750 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
2754 /* Try to reset the chip again the nice way. */
2756 bge_sig_pre_reset(sc, BGE_RESET_STOP);
2757 if (bge_reset(sc)) {
2758 device_printf(sc->bge_dev, "chip reset failed\n");
2763 bge_sig_legacy(sc, BGE_RESET_STOP);
2764 bge_sig_post_reset(sc, BGE_RESET_STOP);
2766 if (bge_chipinit(sc)) {
2767 device_printf(sc->bge_dev, "chip initialization failed\n");
2772 error = bge_get_eaddr(sc, eaddr);
2774 device_printf(sc->bge_dev,
2775 "failed to read station address\n");
2780 /* 5705 limits RX return ring to 512 entries. */
2781 if (BGE_IS_5705_PLUS(sc))
2782 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2784 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2786 if (bge_dma_alloc(dev)) {
2787 device_printf(sc->bge_dev,
2788 "failed to allocate DMA resources\n");
2793 /* Set default tuneable values. */
2794 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2795 sc->bge_rx_coal_ticks = 150;
2796 sc->bge_tx_coal_ticks = 150;
2797 sc->bge_rx_max_coal_bds = 10;
2798 sc->bge_tx_max_coal_bds = 10;
2800 /* Set up ifnet structure */
2801 ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
2803 device_printf(sc->bge_dev, "failed to if_alloc()\n");
2808 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2809 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2810 ifp->if_ioctl = bge_ioctl;
2811 ifp->if_start = bge_start;
2812 ifp->if_init = bge_init;
2813 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
2814 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2815 IFQ_SET_READY(&ifp->if_snd);
2816 ifp->if_hwassist = BGE_CSUM_FEATURES;
2817 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
2819 if ((sc->bge_flags & BGE_FLAG_TSO) != 0) {
2820 ifp->if_hwassist |= CSUM_TSO;
2821 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO;
2823 #ifdef IFCAP_VLAN_HWCSUM
2824 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
2826 ifp->if_capenable = ifp->if_capabilities;
2827 #ifdef DEVICE_POLLING
2828 ifp->if_capabilities |= IFCAP_POLLING;
2832 * 5700 B0 chips do not support checksumming correctly due
2835 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
2836 ifp->if_capabilities &= ~IFCAP_HWCSUM;
2837 ifp->if_capenable &= ~IFCAP_HWCSUM;
2838 ifp->if_hwassist = 0;
2842 * Figure out what sort of media we have by checking the
2843 * hardware config word in the first 32k of NIC internal memory,
2844 * or fall back to examining the EEPROM if necessary.
2845 * Note: on some BCM5700 cards, this value appears to be unset.
2846 * If that's the case, we have to rely on identifying the NIC
2847 * by its PCI subsystem ID, as we do below for the SysKonnect
2850 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2851 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2852 else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
2853 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
2854 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2856 device_printf(sc->bge_dev, "failed to read EEPROM\n");
2860 hwcfg = ntohl(hwcfg);
2863 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2864 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
2865 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2866 if (BGE_IS_5714_FAMILY(sc))
2867 sc->bge_flags |= BGE_FLAG_MII_SERDES;
2869 sc->bge_flags |= BGE_FLAG_TBI;
2872 if (sc->bge_flags & BGE_FLAG_TBI) {
2873 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
2875 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
2876 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2878 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
2879 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
2880 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2883 * Do transceiver setup and tell the firmware the
2884 * driver is down so we can try to get access the
2885 * probe if ASF is running. Retry a couple of times
2886 * if we get a conflict with the ASF firmware accessing
2890 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2892 bge_asf_driver_up(sc);
2894 if (mii_phy_probe(dev, &sc->bge_miibus,
2895 bge_ifmedia_upd, bge_ifmedia_sts)) {
2897 device_printf(sc->bge_dev, "Try again\n");
2898 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR,
2903 device_printf(sc->bge_dev, "MII without any PHY!\n");
2909 * Now tell the firmware we are going up after probing the PHY
2911 if (sc->bge_asf_mode & ASF_STACKUP)
2912 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2916 * When using the BCM5701 in PCI-X mode, data corruption has
2917 * been observed in the first few bytes of some received packets.
2918 * Aligning the packet buffer in memory eliminates the corruption.
2919 * Unfortunately, this misaligns the packet payloads. On platforms
2920 * which do not support unaligned accesses, we will realign the
2921 * payloads by copying the received packets.
2923 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2924 sc->bge_flags & BGE_FLAG_PCIX)
2925 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2928 * Call MI attach routine.
2930 ether_ifattach(ifp, eaddr);
2931 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
2933 /* Tell upper layer we support long frames. */
2934 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2939 #if __FreeBSD_version > 700030
2940 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
2941 /* Take advantage of single-shot MSI. */
2942 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
2943 ~BGE_MSIMODE_ONE_SHOT_DISABLE);
2944 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
2945 taskqueue_thread_enqueue, &sc->bge_tq);
2946 if (sc->bge_tq == NULL) {
2947 device_printf(dev, "could not create taskqueue.\n");
2948 ether_ifdetach(ifp);
2952 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq",
2953 device_get_nameunit(sc->bge_dev));
2954 error = bus_setup_intr(dev, sc->bge_irq,
2955 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
2958 ether_ifdetach(ifp);
2960 error = bus_setup_intr(dev, sc->bge_irq,
2961 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
2964 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2965 bge_intr, sc, &sc->bge_intrhand);
2970 device_printf(sc->bge_dev, "couldn't set up irq\n");
2973 bge_add_sysctls(sc);
2978 bge_release_resources(sc);
2984 bge_detach(device_t dev)
2986 struct bge_softc *sc;
2989 sc = device_get_softc(dev);
2992 #ifdef DEVICE_POLLING
2993 if (ifp->if_capenable & IFCAP_POLLING)
2994 ether_poll_deregister(ifp);
3002 callout_drain(&sc->bge_stat_ch);
3005 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3006 ether_ifdetach(ifp);
3008 if (sc->bge_flags & BGE_FLAG_TBI) {
3009 ifmedia_removeall(&sc->bge_ifmedia);
3011 bus_generic_detach(dev);
3012 device_delete_child(dev, sc->bge_miibus);
3015 bge_release_resources(sc);
3021 bge_release_resources(struct bge_softc *sc)
3027 if (sc->bge_tq != NULL)
3028 taskqueue_free(sc->bge_tq);
3030 if (sc->bge_intrhand != NULL)
3031 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3033 if (sc->bge_irq != NULL)
3034 bus_release_resource(dev, SYS_RES_IRQ,
3035 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
3037 if (sc->bge_flags & BGE_FLAG_MSI)
3038 pci_release_msi(dev);
3040 if (sc->bge_res != NULL)
3041 bus_release_resource(dev, SYS_RES_MEMORY,
3042 BGE_PCI_BAR0, sc->bge_res);
3044 if (sc->bge_ifp != NULL)
3045 if_free(sc->bge_ifp);
3049 if (mtx_initialized(&sc->bge_mtx)) /* XXX */
3050 BGE_LOCK_DESTROY(sc);
3054 bge_reset(struct bge_softc *sc)
3057 uint32_t cachesize, command, pcistate, reset, val;
3058 void (*write_op)(struct bge_softc *, int, int);
3064 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
3065 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3066 if (sc->bge_flags & BGE_FLAG_PCIE)
3067 write_op = bge_writemem_direct;
3069 write_op = bge_writemem_ind;
3071 write_op = bge_writereg_ind;
3073 /* Save some important PCI state. */
3074 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
3075 command = pci_read_config(dev, BGE_PCI_CMD, 4);
3076 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3078 pci_write_config(dev, BGE_PCI_MISC_CTL,
3079 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3080 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3082 /* Disable fastboot on controllers that support it. */
3083 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
3084 BGE_IS_5755_PLUS(sc)) {
3086 device_printf(sc->bge_dev, "Disabling fastboot\n");
3087 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
3091 * Write the magic number to SRAM at offset 0xB50.
3092 * When firmware finishes its initialization it will
3093 * write ~BGE_MAGIC_NUMBER to the same location.
3095 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
3097 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
3099 /* XXX: Broadcom Linux driver. */
3100 if (sc->bge_flags & BGE_FLAG_PCIE) {
3101 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */
3102 CSR_WRITE_4(sc, 0x7E2C, 0x20);
3103 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3104 /* Prevent PCIE link training during global reset */
3105 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
3111 * Set GPHY Power Down Override to leave GPHY
3112 * powered up in D0 uninitialized.
3114 if (BGE_IS_5705_PLUS(sc))
3115 reset |= 0x04000000;
3117 /* Issue global reset */
3118 write_op(sc, BGE_MISC_CFG, reset);
3120 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3121 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3122 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
3123 val | BGE_VCPU_STATUS_DRV_RESET);
3124 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
3125 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
3126 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
3131 /* XXX: Broadcom Linux driver. */
3132 if (sc->bge_flags & BGE_FLAG_PCIE) {
3133 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
3134 DELAY(500000); /* wait for link training to complete */
3135 val = pci_read_config(dev, 0xC4, 4);
3136 pci_write_config(dev, 0xC4, val | (1 << 15), 4);
3138 devctl = pci_read_config(dev,
3139 sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
3140 /* Clear enable no snoop and disable relaxed ordering. */
3141 devctl &= ~(PCIM_EXP_CTL_RELAXED_ORD_ENABLE |
3142 PCIM_EXP_CTL_NOSNOOP_ENABLE);
3143 /* Set PCIE max payload size to 128. */
3144 devctl &= ~PCIM_EXP_CTL_MAX_PAYLOAD;
3145 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL,
3147 /* Clear error status. */
3148 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA,
3149 PCIM_EXP_STA_CORRECTABLE_ERROR |
3150 PCIM_EXP_STA_NON_FATAL_ERROR | PCIM_EXP_STA_FATAL_ERROR |
3151 PCIM_EXP_STA_UNSUPPORTED_REQ, 2);
3154 /* Reset some of the PCI state that got zapped by reset. */
3155 pci_write_config(dev, BGE_PCI_MISC_CTL,
3156 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3157 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3158 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
3159 pci_write_config(dev, BGE_PCI_CMD, command, 4);
3160 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
3162 /* Re-enable MSI, if neccesary, and enable the memory arbiter. */
3163 if (BGE_IS_5714_FAMILY(sc)) {
3164 /* This chip disables MSI on reset. */
3165 if (sc->bge_flags & BGE_FLAG_MSI) {
3166 val = pci_read_config(dev,
3167 sc->bge_msicap + PCIR_MSI_CTRL, 2);
3168 pci_write_config(dev,
3169 sc->bge_msicap + PCIR_MSI_CTRL,
3170 val | PCIM_MSICTRL_MSI_ENABLE, 2);
3171 val = CSR_READ_4(sc, BGE_MSI_MODE);
3172 CSR_WRITE_4(sc, BGE_MSI_MODE,
3173 val | BGE_MSIMODE_ENABLE);
3175 val = CSR_READ_4(sc, BGE_MARB_MODE);
3176 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
3178 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3180 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3181 for (i = 0; i < BGE_TIMEOUT; i++) {
3182 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3183 if (val & BGE_VCPU_STATUS_INIT_DONE)
3187 if (i == BGE_TIMEOUT) {
3188 device_printf(sc->bge_dev, "reset timed out\n");
3193 * Poll until we see the 1's complement of the magic number.
3194 * This indicates that the firmware initialization is complete.
3195 * We expect this to fail if no chip containing the Ethernet
3196 * address is fitted though.
3198 for (i = 0; i < BGE_TIMEOUT; i++) {
3200 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
3201 if (val == ~BGE_MAGIC_NUMBER)
3205 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
3206 device_printf(sc->bge_dev, "firmware handshake timed out, "
3207 "found 0x%08x\n", val);
3211 * XXX Wait for the value of the PCISTATE register to
3212 * return to its original pre-reset state. This is a
3213 * fairly good indicator of reset completion. If we don't
3214 * wait for the reset to fully complete, trying to read
3215 * from the device's non-PCI registers may yield garbage
3218 for (i = 0; i < BGE_TIMEOUT; i++) {
3219 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
3224 if (sc->bge_flags & BGE_FLAG_PCIE) {
3225 reset = bge_readmem_ind(sc, 0x7C00);
3226 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25));
3229 /* Fix up byte swapping. */
3230 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
3231 BGE_MODECTL_BYTESWAP_DATA);
3233 /* Tell the ASF firmware we are up */
3234 if (sc->bge_asf_mode & ASF_STACKUP)
3235 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3237 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
3240 * The 5704 in TBI mode apparently needs some special
3241 * adjustment to insure the SERDES drive level is set
3244 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
3245 sc->bge_flags & BGE_FLAG_TBI) {
3246 val = CSR_READ_4(sc, BGE_SERDES_CFG);
3247 val = (val & ~0xFFF) | 0x880;
3248 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
3251 /* XXX: Broadcom Linux driver. */
3252 if (sc->bge_flags & BGE_FLAG_PCIE &&
3253 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3254 val = CSR_READ_4(sc, 0x7C00);
3255 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
3263 * Frame reception handling. This is called if there's a frame
3264 * on the receive return list.
3266 * Note: we have to be able to handle two possibilities here:
3267 * 1) the frame is from the jumbo receive ring
3268 * 2) the frame is from the standard receive ring
3272 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
3275 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
3278 rx_cons = sc->bge_rx_saved_considx;
3280 /* Nothing to do. */
3281 if (rx_cons == rx_prod)
3286 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3287 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
3288 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3289 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
3290 if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
3291 (MCLBYTES - ETHER_ALIGN))
3292 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3293 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
3295 while (rx_cons != rx_prod) {
3296 struct bge_rx_bd *cur_rx;
3298 struct mbuf *m = NULL;
3299 uint16_t vlan_tag = 0;
3302 #ifdef DEVICE_POLLING
3303 if (ifp->if_capenable & IFCAP_POLLING) {
3304 if (sc->rxcycles <= 0)
3310 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
3312 rxidx = cur_rx->bge_idx;
3313 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
3315 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
3316 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
3318 vlan_tag = cur_rx->bge_vlan_tag;
3321 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
3323 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
3324 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3325 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3328 if (bge_newbuf_jumbo(sc, rxidx) != 0) {
3329 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3333 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3336 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3337 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3340 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
3341 if (bge_newbuf_std(sc, rxidx) != 0) {
3342 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3346 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3350 #ifndef __NO_STRICT_ALIGNMENT
3352 * For architectures with strict alignment we must make sure
3353 * the payload is aligned.
3355 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
3356 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
3358 m->m_data += ETHER_ALIGN;
3361 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3362 m->m_pkthdr.rcvif = ifp;
3364 if (ifp->if_capenable & IFCAP_RXCSUM) {
3365 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3366 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3367 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
3368 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3370 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
3371 m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
3372 m->m_pkthdr.csum_data =
3373 cur_rx->bge_tcp_udp_csum;
3374 m->m_pkthdr.csum_flags |=
3375 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
3380 * If we received a packet with a vlan tag,
3381 * attach that information to the packet.
3384 #if __FreeBSD_version > 700022
3385 m->m_pkthdr.ether_vtag = vlan_tag;
3386 m->m_flags |= M_VLANTAG;
3388 VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag);
3396 (*ifp->if_input)(ifp, m);
3399 (*ifp->if_input)(ifp, m);
3402 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
3406 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3407 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
3409 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3410 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
3413 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3414 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
3416 sc->bge_rx_saved_considx = rx_cons;
3417 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3419 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
3421 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
3424 * This register wraps very quickly under heavy packet drops.
3425 * If you need correct statistics, you can enable this check.
3427 if (BGE_IS_5705_PLUS(sc))
3428 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3434 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
3436 struct bge_tx_bd *cur_tx = NULL;
3439 BGE_LOCK_ASSERT(sc);
3441 /* Nothing to do. */
3442 if (sc->bge_tx_saved_considx == tx_cons)
3447 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
3448 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
3450 * Go through our tx ring and free mbufs for those
3451 * frames that have been sent.
3453 while (sc->bge_tx_saved_considx != tx_cons) {
3456 idx = sc->bge_tx_saved_considx;
3457 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
3458 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
3460 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
3461 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
3462 sc->bge_cdata.bge_tx_dmamap[idx],
3463 BUS_DMASYNC_POSTWRITE);
3464 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
3465 sc->bge_cdata.bge_tx_dmamap[idx]);
3466 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
3467 sc->bge_cdata.bge_tx_chain[idx] = NULL;
3470 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3474 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3475 if (sc->bge_txcnt == 0)
3479 #ifdef DEVICE_POLLING
3481 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3483 struct bge_softc *sc = ifp->if_softc;
3484 uint16_t rx_prod, tx_cons;
3485 uint32_t statusword;
3489 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3494 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3495 sc->bge_cdata.bge_status_map,
3496 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3497 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3498 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3500 statusword = atomic_readandclear_32(
3501 &sc->bge_ldata.bge_status_block->bge_status);
3503 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3504 sc->bge_cdata.bge_status_map,
3505 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3507 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
3508 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
3511 if (cmd == POLL_AND_CHECK_STATUS)
3512 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3513 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3514 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
3517 sc->rxcycles = count;
3518 rx_npkts = bge_rxeof(sc, rx_prod, 1);
3519 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3523 bge_txeof(sc, tx_cons);
3524 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3525 bge_start_locked(ifp);
3530 #endif /* DEVICE_POLLING */
3533 bge_msi_intr(void *arg)
3535 struct bge_softc *sc;
3537 sc = (struct bge_softc *)arg;
3539 * This interrupt is not shared and controller already
3540 * disabled further interrupt.
3542 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
3543 return (FILTER_HANDLED);
3547 bge_intr_task(void *arg, int pending)
3549 struct bge_softc *sc;
3552 uint16_t rx_prod, tx_cons;
3554 sc = (struct bge_softc *)arg;
3557 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3560 /* Get updated status block. */
3561 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3562 sc->bge_cdata.bge_status_map,
3563 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3565 /* Save producer/consumer indexess. */
3566 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3567 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3568 status = sc->bge_ldata.bge_status_block->bge_status;
3569 sc->bge_ldata.bge_status_block->bge_status = 0;
3570 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3571 sc->bge_cdata.bge_status_map,
3572 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3573 /* Let controller work. */
3574 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3576 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) {
3581 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3582 /* Check RX return ring producer/consumer. */
3583 bge_rxeof(sc, rx_prod, 0);
3585 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3587 /* Check TX ring producer/consumer. */
3588 bge_txeof(sc, tx_cons);
3589 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3590 bge_start_locked(ifp);
3598 struct bge_softc *sc;
3600 uint32_t statusword;
3601 uint16_t rx_prod, tx_cons;
3609 #ifdef DEVICE_POLLING
3610 if (ifp->if_capenable & IFCAP_POLLING) {
3617 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
3618 * disable interrupts by writing nonzero like we used to, since with
3619 * our current organization this just gives complications and
3620 * pessimizations for re-enabling interrupts. We used to have races
3621 * instead of the necessary complications. Disabling interrupts
3622 * would just reduce the chance of a status update while we are
3623 * running (by switching to the interrupt-mode coalescence
3624 * parameters), but this chance is already very low so it is more
3625 * efficient to get another interrupt than prevent it.
3627 * We do the ack first to ensure another interrupt if there is a
3628 * status update after the ack. We don't check for the status
3629 * changing later because it is more efficient to get another
3630 * interrupt than prevent it, not quite as above (not checking is
3631 * a smaller optimization than not toggling the interrupt enable,
3632 * since checking doesn't involve PCI accesses and toggling require
3633 * the status check). So toggling would probably be a pessimization
3634 * even with MSI. It would only be needed for using a task queue.
3636 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3639 * Do the mandatory PCI flush as well as get the link status.
3641 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
3643 /* Make sure the descriptor ring indexes are coherent. */
3644 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3645 sc->bge_cdata.bge_status_map,
3646 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3647 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3648 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3649 sc->bge_ldata.bge_status_block->bge_status = 0;
3650 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3651 sc->bge_cdata.bge_status_map,
3652 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3654 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3655 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3656 statusword || sc->bge_link_evt)
3659 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3660 /* Check RX return ring producer/consumer. */
3661 bge_rxeof(sc, rx_prod, 1);
3664 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3665 /* Check TX ring producer/consumer. */
3666 bge_txeof(sc, tx_cons);
3669 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3670 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3671 bge_start_locked(ifp);
3677 bge_asf_driver_up(struct bge_softc *sc)
3679 if (sc->bge_asf_mode & ASF_STACKUP) {
3680 /* Send ASF heartbeat aprox. every 2s */
3681 if (sc->bge_asf_count)
3682 sc->bge_asf_count --;
3684 sc->bge_asf_count = 2;
3685 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW,
3687 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4);
3688 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3);
3689 CSR_WRITE_4(sc, BGE_CPU_EVENT,
3690 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
3698 struct bge_softc *sc = xsc;
3699 struct mii_data *mii = NULL;
3701 BGE_LOCK_ASSERT(sc);
3703 /* Synchronize with possible callout reset/stop. */
3704 if (callout_pending(&sc->bge_stat_ch) ||
3705 !callout_active(&sc->bge_stat_ch))
3708 if (BGE_IS_5705_PLUS(sc))
3709 bge_stats_update_regs(sc);
3711 bge_stats_update(sc);
3713 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
3714 mii = device_get_softc(sc->bge_miibus);
3716 * Do not touch PHY if we have link up. This could break
3717 * IPMI/ASF mode or produce extra input errors
3718 * (extra errors was reported for bcm5701 & bcm5704).
3724 * Since in TBI mode auto-polling can't be used we should poll
3725 * link status manually. Here we register pending link event
3726 * and trigger interrupt.
3728 #ifdef DEVICE_POLLING
3729 /* In polling mode we poll link state in bge_poll(). */
3730 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
3734 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3735 sc->bge_flags & BGE_FLAG_5788)
3736 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3738 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3742 bge_asf_driver_up(sc);
3745 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
3749 bge_stats_update_regs(struct bge_softc *sc)
3755 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS +
3756 offsetof(struct bge_mac_stats_regs, etherStatsCollisions));
3758 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
3759 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3760 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
3764 bge_stats_update(struct bge_softc *sc)
3768 uint32_t cnt; /* current register value */
3772 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3774 #define READ_STAT(sc, stats, stat) \
3775 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3777 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
3778 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
3779 sc->bge_tx_collisions = cnt;
3781 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
3782 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
3783 sc->bge_rx_discards = cnt;
3785 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
3786 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
3787 sc->bge_tx_discards = cnt;
3793 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
3794 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
3795 * but when such padded frames employ the bge IP/TCP checksum offload,
3796 * the hardware checksum assist gives incorrect results (possibly
3797 * from incorporating its own padding into the UDP/TCP checksum; who knows).
3798 * If we pad such runts with zeros, the onboard checksum comes out correct.
3801 bge_cksum_pad(struct mbuf *m)
3803 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
3806 /* If there's only the packet-header and we can pad there, use it. */
3807 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
3808 M_TRAILINGSPACE(m) >= padlen) {
3812 * Walk packet chain to find last mbuf. We will either
3813 * pad there, or append a new mbuf and pad it.
3815 for (last = m; last->m_next != NULL; last = last->m_next);
3816 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
3817 /* Allocate new empty mbuf, pad it. Compact later. */
3820 MGET(n, M_DONTWAIT, MT_DATA);
3829 /* Now zero the pad area, to avoid the bge cksum-assist bug. */
3830 memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
3831 last->m_len += padlen;
3832 m->m_pkthdr.len += padlen;
3837 static struct mbuf *
3838 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss)
3846 if (M_WRITABLE(m) == 0) {
3847 /* Get a writable copy. */
3848 n = m_dup(m, M_DONTWAIT);
3854 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
3857 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
3858 poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
3859 m = m_pullup(m, poff + sizeof(struct tcphdr));
3862 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
3863 m = m_pullup(m, poff + (tcp->th_off << 2));
3867 * It seems controller doesn't modify IP length and TCP pseudo
3868 * checksum. These checksum computed by upper stack should be 0.
3870 *mss = m->m_pkthdr.tso_segsz;
3872 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
3873 /* Clear pseudo checksum computed by TCP stack. */
3876 * Broadcom controllers uses different descriptor format for
3877 * TSO depending on ASIC revision. Due to TSO-capable firmware
3878 * license issue and lower performance of firmware based TSO
3879 * we only support hardware based TSO which is applicable for
3880 * BCM5755 or newer controllers. Hardware based TSO uses 11
3881 * bits to store MSS and upper 5 bits are used to store IP/TCP
3882 * header length(including IP/TCP options). The header length
3883 * is expressed as 32 bits unit.
3885 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
3886 *mss |= (hlen << 11);
3891 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
3892 * pointers to descriptors.
3895 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
3897 bus_dma_segment_t segs[BGE_NSEG_NEW];
3899 struct bge_tx_bd *d;
3900 struct mbuf *m = *m_head;
3901 uint32_t idx = *txidx;
3902 uint16_t csum_flags, mss, vlan_tag;
3903 int nsegs, i, error;
3908 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
3909 *m_head = m = bge_setup_tso(sc, m, &mss);
3910 if (*m_head == NULL)
3912 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
3913 BGE_TXBDFLAG_CPU_POST_DMA;
3914 } else if ((m->m_pkthdr.csum_flags & BGE_CSUM_FEATURES) != 0) {
3915 if (m->m_pkthdr.csum_flags & CSUM_IP)
3916 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3917 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
3918 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3919 if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
3920 (error = bge_cksum_pad(m)) != 0) {
3926 if (m->m_flags & M_LASTFRAG)
3927 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3928 else if (m->m_flags & M_FRAG)
3929 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3932 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
3933 sc->bge_forced_collapse > 0 &&
3934 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
3936 * Forcedly collapse mbuf chains to overcome hardware
3937 * limitation which only support a single outstanding
3938 * DMA read operation.
3940 if (sc->bge_forced_collapse == 1)
3941 m = m_defrag(m, M_DONTWAIT);
3943 m = m_collapse(m, M_DONTWAIT, sc->bge_forced_collapse);
3949 map = sc->bge_cdata.bge_tx_dmamap[idx];
3950 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
3951 &nsegs, BUS_DMA_NOWAIT);
3952 if (error == EFBIG) {
3953 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW);
3960 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
3961 m, segs, &nsegs, BUS_DMA_NOWAIT);
3967 } else if (error != 0)
3970 /* Check if we have enough free send BDs. */
3971 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
3972 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
3976 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3978 #if __FreeBSD_version > 700022
3979 if (m->m_flags & M_VLANTAG) {
3980 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
3981 vlan_tag = m->m_pkthdr.ether_vtag;
3987 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) {
3988 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
3989 vlan_tag = VLAN_TAG_VALUE(mtag);
3993 for (i = 0; ; i++) {
3994 d = &sc->bge_ldata.bge_tx_ring[idx];
3995 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3996 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3997 d->bge_len = segs[i].ds_len;
3998 d->bge_flags = csum_flags;
3999 d->bge_vlan_tag = vlan_tag;
4003 BGE_INC(idx, BGE_TX_RING_CNT);
4006 /* Mark the last segment as end of packet... */
4007 d->bge_flags |= BGE_TXBDFLAG_END;
4010 * Insure that the map for this transmission
4011 * is placed at the array index of the last descriptor
4014 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
4015 sc->bge_cdata.bge_tx_dmamap[idx] = map;
4016 sc->bge_cdata.bge_tx_chain[idx] = m;
4017 sc->bge_txcnt += nsegs;
4019 BGE_INC(idx, BGE_TX_RING_CNT);
4026 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4027 * to the mbuf data regions directly in the transmit descriptors.
4030 bge_start_locked(struct ifnet *ifp)
4032 struct bge_softc *sc;
4033 struct mbuf *m_head;
4038 BGE_LOCK_ASSERT(sc);
4040 if (!sc->bge_link ||
4041 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4045 prodidx = sc->bge_tx_prodidx;
4047 for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
4048 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
4049 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4052 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
4058 * The code inside the if() block is never reached since we
4059 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
4060 * requests to checksum TCP/UDP in a fragmented packet.
4063 * safety overkill. If this is a fragmented packet chain
4064 * with delayed TCP/UDP checksums, then only encapsulate
4065 * it if we have enough descriptors to handle the entire
4067 * (paranoia -- may not actually be needed)
4069 if (m_head->m_flags & M_FIRSTFRAG &&
4070 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
4071 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
4072 m_head->m_pkthdr.csum_data + 16) {
4073 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4074 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4080 * Pack the data into the transmit ring. If we
4081 * don't have room, set the OACTIVE flag and wait
4082 * for the NIC to drain the ring.
4084 if (bge_encap(sc, &m_head, &prodidx)) {
4087 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4088 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4094 * If there's a BPF listener, bounce a copy of this frame
4097 #ifdef ETHER_BPF_MTAP
4098 ETHER_BPF_MTAP(ifp, m_head);
4100 BPF_MTAP(ifp, m_head);
4105 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4106 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
4108 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4109 /* 5700 b2 errata */
4110 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
4111 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4113 sc->bge_tx_prodidx = prodidx;
4116 * Set a timeout in case the chip goes out to lunch.
4123 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4124 * to the mbuf data regions directly in the transmit descriptors.
4127 bge_start(struct ifnet *ifp)
4129 struct bge_softc *sc;
4133 bge_start_locked(ifp);
4138 bge_init_locked(struct bge_softc *sc)
4143 BGE_LOCK_ASSERT(sc);
4147 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4150 /* Cancel pending I/O and flush buffers. */
4154 bge_sig_pre_reset(sc, BGE_RESET_START);
4156 bge_sig_legacy(sc, BGE_RESET_START);
4157 bge_sig_post_reset(sc, BGE_RESET_START);
4162 * Init the various state machines, ring
4163 * control blocks and firmware.
4165 if (bge_blockinit(sc)) {
4166 device_printf(sc->bge_dev, "initialization failure\n");
4173 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
4174 ETHER_HDR_LEN + ETHER_CRC_LEN +
4175 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
4177 /* Load our MAC address. */
4178 m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
4179 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
4180 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
4182 /* Program promiscuous mode. */
4185 /* Program multicast filter. */
4188 /* Program VLAN tag stripping. */
4192 if (bge_init_rx_ring_std(sc) != 0) {
4193 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
4199 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
4200 * memory to insure that the chip has in fact read the first
4201 * entry of the ring.
4203 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
4205 for (i = 0; i < 10; i++) {
4207 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
4208 if (v == (MCLBYTES - ETHER_ALIGN))
4212 device_printf (sc->bge_dev,
4213 "5705 A0 chip failed to load RX ring\n");
4216 /* Init jumbo RX ring. */
4217 if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
4218 (MCLBYTES - ETHER_ALIGN)) {
4219 if (bge_init_rx_ring_jumbo(sc) != 0) {
4220 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
4226 /* Init our RX return ring index. */
4227 sc->bge_rx_saved_considx = 0;
4229 /* Init our RX/TX stat counters. */
4230 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
4233 bge_init_tx_ring(sc);
4235 /* Turn on transmitter. */
4236 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
4238 /* Turn on receiver. */
4239 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4241 /* Tell firmware we're alive. */
4242 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4244 #ifdef DEVICE_POLLING
4245 /* Disable interrupts if we are polling. */
4246 if (ifp->if_capenable & IFCAP_POLLING) {
4247 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4248 BGE_PCIMISCCTL_MASK_PCI_INTR);
4249 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4253 /* Enable host interrupts. */
4255 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
4256 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4257 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4260 bge_ifmedia_upd_locked(ifp);
4262 ifp->if_drv_flags |= IFF_DRV_RUNNING;
4263 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4265 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4271 struct bge_softc *sc = xsc;
4274 bge_init_locked(sc);
4279 * Set media options.
4282 bge_ifmedia_upd(struct ifnet *ifp)
4284 struct bge_softc *sc = ifp->if_softc;
4288 res = bge_ifmedia_upd_locked(ifp);
4295 bge_ifmedia_upd_locked(struct ifnet *ifp)
4297 struct bge_softc *sc = ifp->if_softc;
4298 struct mii_data *mii;
4299 struct mii_softc *miisc;
4300 struct ifmedia *ifm;
4302 BGE_LOCK_ASSERT(sc);
4304 ifm = &sc->bge_ifmedia;
4306 /* If this is a 1000baseX NIC, enable the TBI port. */
4307 if (sc->bge_flags & BGE_FLAG_TBI) {
4308 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
4310 switch(IFM_SUBTYPE(ifm->ifm_media)) {
4313 * The BCM5704 ASIC appears to have a special
4314 * mechanism for programming the autoneg
4315 * advertisement registers in TBI mode.
4317 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4319 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
4320 if (sgdig & BGE_SGDIGSTS_DONE) {
4321 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
4322 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
4323 sgdig |= BGE_SGDIGCFG_AUTO |
4324 BGE_SGDIGCFG_PAUSE_CAP |
4325 BGE_SGDIGCFG_ASYM_PAUSE;
4326 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
4327 sgdig | BGE_SGDIGCFG_SEND);
4329 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
4334 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
4335 BGE_CLRBIT(sc, BGE_MAC_MODE,
4336 BGE_MACMODE_HALF_DUPLEX);
4338 BGE_SETBIT(sc, BGE_MAC_MODE,
4339 BGE_MACMODE_HALF_DUPLEX);
4349 mii = device_get_softc(sc->bge_miibus);
4350 if (mii->mii_instance)
4351 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4352 mii_phy_reset(miisc);
4356 * Force an interrupt so that we will call bge_link_upd
4357 * if needed and clear any pending link state attention.
4358 * Without this we are not getting any further interrupts
4359 * for link state changes and thus will not UP the link and
4360 * not be able to send in bge_start_locked. The only
4361 * way to get things working was to receive a packet and
4363 * bge_tick should help for fiber cards and we might not
4364 * need to do this here if BGE_FLAG_TBI is set but as
4365 * we poll for fiber anyway it should not harm.
4367 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4368 sc->bge_flags & BGE_FLAG_5788)
4369 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4371 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4377 * Report current media status.
4380 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4382 struct bge_softc *sc = ifp->if_softc;
4383 struct mii_data *mii;
4387 if (sc->bge_flags & BGE_FLAG_TBI) {
4388 ifmr->ifm_status = IFM_AVALID;
4389 ifmr->ifm_active = IFM_ETHER;
4390 if (CSR_READ_4(sc, BGE_MAC_STS) &
4391 BGE_MACSTAT_TBI_PCS_SYNCHED)
4392 ifmr->ifm_status |= IFM_ACTIVE;
4394 ifmr->ifm_active |= IFM_NONE;
4398 ifmr->ifm_active |= IFM_1000_SX;
4399 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
4400 ifmr->ifm_active |= IFM_HDX;
4402 ifmr->ifm_active |= IFM_FDX;
4407 mii = device_get_softc(sc->bge_miibus);
4409 ifmr->ifm_active = mii->mii_media_active;
4410 ifmr->ifm_status = mii->mii_media_status;
4416 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
4418 struct bge_softc *sc = ifp->if_softc;
4419 struct ifreq *ifr = (struct ifreq *) data;
4420 struct mii_data *mii;
4421 int flags, mask, error = 0;
4425 if (ifr->ifr_mtu < ETHERMIN ||
4426 ((BGE_IS_JUMBO_CAPABLE(sc)) &&
4427 ifr->ifr_mtu > BGE_JUMBO_MTU) ||
4428 ((!BGE_IS_JUMBO_CAPABLE(sc)) &&
4429 ifr->ifr_mtu > ETHERMTU))
4431 else if (ifp->if_mtu != ifr->ifr_mtu) {
4432 ifp->if_mtu = ifr->ifr_mtu;
4433 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4439 if (ifp->if_flags & IFF_UP) {
4441 * If only the state of the PROMISC flag changed,
4442 * then just use the 'set promisc mode' command
4443 * instead of reinitializing the entire NIC. Doing
4444 * a full re-init means reloading the firmware and
4445 * waiting for it to start up, which may take a
4446 * second or two. Similarly for ALLMULTI.
4448 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4449 flags = ifp->if_flags ^ sc->bge_if_flags;
4450 if (flags & IFF_PROMISC)
4452 if (flags & IFF_ALLMULTI)
4455 bge_init_locked(sc);
4457 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4461 sc->bge_if_flags = ifp->if_flags;
4467 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4476 if (sc->bge_flags & BGE_FLAG_TBI) {
4477 error = ifmedia_ioctl(ifp, ifr,
4478 &sc->bge_ifmedia, command);
4480 mii = device_get_softc(sc->bge_miibus);
4481 error = ifmedia_ioctl(ifp, ifr,
4482 &mii->mii_media, command);
4486 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
4487 #ifdef DEVICE_POLLING
4488 if (mask & IFCAP_POLLING) {
4489 if (ifr->ifr_reqcap & IFCAP_POLLING) {
4490 error = ether_poll_register(bge_poll, ifp);
4494 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4495 BGE_PCIMISCCTL_MASK_PCI_INTR);
4496 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4497 ifp->if_capenable |= IFCAP_POLLING;
4500 error = ether_poll_deregister(ifp);
4501 /* Enable interrupt even in error case */
4503 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
4504 BGE_PCIMISCCTL_MASK_PCI_INTR);
4505 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4506 ifp->if_capenable &= ~IFCAP_POLLING;
4511 if (mask & IFCAP_HWCSUM) {
4512 ifp->if_capenable ^= IFCAP_HWCSUM;
4513 if (IFCAP_HWCSUM & ifp->if_capenable &&
4514 IFCAP_HWCSUM & ifp->if_capabilities)
4515 ifp->if_hwassist |= BGE_CSUM_FEATURES;
4517 ifp->if_hwassist &= ~BGE_CSUM_FEATURES;
4520 if ((mask & IFCAP_TSO4) != 0 &&
4521 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
4522 ifp->if_capenable ^= IFCAP_TSO4;
4523 if ((ifp->if_capenable & IFCAP_TSO4) != 0)
4524 ifp->if_hwassist |= CSUM_TSO;
4526 ifp->if_hwassist &= ~CSUM_TSO;
4529 if (mask & IFCAP_VLAN_MTU) {
4530 ifp->if_capenable ^= IFCAP_VLAN_MTU;
4531 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4535 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
4536 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
4537 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
4538 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
4539 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
4540 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
4541 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
4542 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
4547 #ifdef VLAN_CAPABILITIES
4548 VLAN_CAPABILITIES(ifp);
4552 error = ether_ioctl(ifp, command, data);
4560 bge_watchdog(struct bge_softc *sc)
4564 BGE_LOCK_ASSERT(sc);
4566 if (sc->bge_timer == 0 || --sc->bge_timer)
4571 if_printf(ifp, "watchdog timeout -- resetting\n");
4573 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4574 bge_init_locked(sc);
4580 * Stop the adapter and free any mbufs allocated to the
4584 bge_stop(struct bge_softc *sc)
4588 BGE_LOCK_ASSERT(sc);
4592 callout_stop(&sc->bge_stat_ch);
4594 /* Disable host interrupts. */
4595 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4596 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4599 * Tell firmware we're shutting down.
4602 bge_sig_pre_reset(sc, BGE_RESET_STOP);
4605 * Disable all of the receiver blocks.
4607 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4608 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
4609 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
4610 if (!(BGE_IS_5705_PLUS(sc)))
4611 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
4612 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
4613 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
4614 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
4617 * Disable all of the transmit blocks.
4619 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
4620 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
4621 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
4622 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
4623 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
4624 if (!(BGE_IS_5705_PLUS(sc)))
4625 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
4626 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
4629 * Shut down all of the memory managers and related
4632 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
4633 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
4634 if (!(BGE_IS_5705_PLUS(sc)))
4635 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
4636 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
4637 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
4638 if (!(BGE_IS_5705_PLUS(sc))) {
4639 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
4640 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4644 bge_sig_legacy(sc, BGE_RESET_STOP);
4645 bge_sig_post_reset(sc, BGE_RESET_STOP);
4648 * Keep the ASF firmware running if up.
4650 if (sc->bge_asf_mode & ASF_STACKUP)
4651 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4653 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4655 /* Free the RX lists. */
4656 bge_free_rx_ring_std(sc);
4658 /* Free jumbo RX list. */
4659 if (BGE_IS_JUMBO_CAPABLE(sc))
4660 bge_free_rx_ring_jumbo(sc);
4662 /* Free TX buffers. */
4663 bge_free_tx_ring(sc);
4665 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
4667 /* Clear MAC's link state (PHY may still have link UP). */
4668 if (bootverbose && sc->bge_link)
4669 if_printf(sc->bge_ifp, "link DOWN\n");
4672 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4676 * Stop all chip I/O so that the kernel's probe routines don't
4677 * get confused by errant DMAs when rebooting.
4680 bge_shutdown(device_t dev)
4682 struct bge_softc *sc;
4684 sc = device_get_softc(dev);
4694 bge_suspend(device_t dev)
4696 struct bge_softc *sc;
4698 sc = device_get_softc(dev);
4707 bge_resume(device_t dev)
4709 struct bge_softc *sc;
4712 sc = device_get_softc(dev);
4715 if (ifp->if_flags & IFF_UP) {
4716 bge_init_locked(sc);
4717 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4718 bge_start_locked(ifp);
4726 bge_link_upd(struct bge_softc *sc)
4728 struct mii_data *mii;
4729 uint32_t link, status;
4731 BGE_LOCK_ASSERT(sc);
4733 /* Clear 'pending link event' flag. */
4734 sc->bge_link_evt = 0;
4737 * Process link state changes.
4738 * Grrr. The link status word in the status block does
4739 * not work correctly on the BCM5700 rev AX and BX chips,
4740 * according to all available information. Hence, we have
4741 * to enable MII interrupts in order to properly obtain
4742 * async link changes. Unfortunately, this also means that
4743 * we have to read the MAC status register to detect link
4744 * changes, thereby adding an additional register access to
4745 * the interrupt handler.
4747 * XXX: perhaps link state detection procedure used for
4748 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
4751 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4752 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
4753 status = CSR_READ_4(sc, BGE_MAC_STS);
4754 if (status & BGE_MACSTAT_MI_INTERRUPT) {
4755 mii = device_get_softc(sc->bge_miibus);
4757 if (!sc->bge_link &&
4758 mii->mii_media_status & IFM_ACTIVE &&
4759 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4762 if_printf(sc->bge_ifp, "link UP\n");
4763 } else if (sc->bge_link &&
4764 (!(mii->mii_media_status & IFM_ACTIVE) ||
4765 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4768 if_printf(sc->bge_ifp, "link DOWN\n");
4771 /* Clear the interrupt. */
4772 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
4773 BGE_EVTENB_MI_INTERRUPT);
4774 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4775 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
4781 if (sc->bge_flags & BGE_FLAG_TBI) {
4782 status = CSR_READ_4(sc, BGE_MAC_STS);
4783 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4784 if (!sc->bge_link) {
4786 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
4787 BGE_CLRBIT(sc, BGE_MAC_MODE,
4788 BGE_MACMODE_TBI_SEND_CFGS);
4789 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4791 if_printf(sc->bge_ifp, "link UP\n");
4792 if_link_state_change(sc->bge_ifp,
4795 } else if (sc->bge_link) {
4798 if_printf(sc->bge_ifp, "link DOWN\n");
4799 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
4801 } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
4803 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
4804 * in status word always set. Workaround this bug by reading
4805 * PHY link status directly.
4807 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
4809 if (link != sc->bge_link ||
4810 sc->bge_asicrev == BGE_ASICREV_BCM5700) {
4811 mii = device_get_softc(sc->bge_miibus);
4813 if (!sc->bge_link &&
4814 mii->mii_media_status & IFM_ACTIVE &&
4815 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4818 if_printf(sc->bge_ifp, "link UP\n");
4819 } else if (sc->bge_link &&
4820 (!(mii->mii_media_status & IFM_ACTIVE) ||
4821 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4824 if_printf(sc->bge_ifp, "link DOWN\n");
4829 * Discard link events for MII/GMII controllers
4830 * if MI auto-polling is disabled.
4834 /* Clear the attention. */
4835 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4836 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4837 BGE_MACSTAT_LINK_CHANGED);
4840 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
4841 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
4842 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
4846 bge_add_sysctls(struct bge_softc *sc)
4848 struct sysctl_ctx_list *ctx;
4849 struct sysctl_oid_list *children, *schildren;
4850 struct sysctl_oid *tree;
4852 ctx = device_get_sysctl_ctx(sc->bge_dev);
4853 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
4855 #ifdef BGE_REGISTER_DEBUG
4856 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
4857 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
4858 "Debug Information");
4860 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
4861 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
4864 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
4865 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
4871 * A common design characteristic for many Broadcom client controllers
4872 * is that they only support a single outstanding DMA read operation
4873 * on the PCIe bus. This means that it will take twice as long to fetch
4874 * a TX frame that is split into header and payload buffers as it does
4875 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
4876 * these controllers, coalescing buffers to reduce the number of memory
4877 * reads is effective way to get maximum performance(about 940Mbps).
4878 * Without collapsing TX buffers the maximum TCP bulk transfer
4879 * performance is about 850Mbps. However forcing coalescing mbufs
4880 * consumes a lot of CPU cycles, so leave it off by default.
4882 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
4883 CTLFLAG_RW, &sc->bge_forced_collapse, 0,
4884 "Number of fragmented TX buffers of a frame allowed before "
4885 "forced collapsing");
4886 resource_int_value(device_get_name(sc->bge_dev),
4887 device_get_unit(sc->bge_dev), "forced_collapse",
4888 &sc->bge_forced_collapse);
4890 if (BGE_IS_5705_PLUS(sc))
4893 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
4894 NULL, "BGE Statistics");
4895 schildren = children = SYSCTL_CHILDREN(tree);
4896 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
4897 children, COSFramesDroppedDueToFilters,
4898 "FramesDroppedDueToFilters");
4899 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
4900 children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
4901 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
4902 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
4903 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
4904 children, nicNoMoreRxBDs, "NoMoreRxBDs");
4905 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
4906 children, ifInDiscards, "InputDiscards");
4907 BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
4908 children, ifInErrors, "InputErrors");
4909 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
4910 children, nicRecvThresholdHit, "RecvThresholdHit");
4911 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
4912 children, nicDmaReadQueueFull, "DmaReadQueueFull");
4913 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
4914 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
4915 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
4916 children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
4917 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
4918 children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
4919 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
4920 children, nicRingStatusUpdate, "RingStatusUpdate");
4921 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
4922 children, nicInterrupts, "Interrupts");
4923 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
4924 children, nicAvoidedInterrupts, "AvoidedInterrupts");
4925 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
4926 children, nicSendThresholdHit, "SendThresholdHit");
4928 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
4929 NULL, "BGE RX Statistics");
4930 children = SYSCTL_CHILDREN(tree);
4931 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
4932 children, rxstats.ifHCInOctets, "Octets");
4933 BGE_SYSCTL_STAT(sc, ctx, "Fragments",
4934 children, rxstats.etherStatsFragments, "Fragments");
4935 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
4936 children, rxstats.ifHCInUcastPkts, "UcastPkts");
4937 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
4938 children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
4939 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
4940 children, rxstats.dot3StatsFCSErrors, "FCSErrors");
4941 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
4942 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
4943 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
4944 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
4945 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
4946 children, rxstats.xoffPauseFramesReceived,
4947 "xoffPauseFramesReceived");
4948 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
4949 children, rxstats.macControlFramesReceived,
4950 "ControlFramesReceived");
4951 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
4952 children, rxstats.xoffStateEntered, "xoffStateEntered");
4953 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
4954 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
4955 BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
4956 children, rxstats.etherStatsJabbers, "Jabbers");
4957 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
4958 children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
4959 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
4960 children, rxstats.inRangeLengthError, "inRangeLengthError");
4961 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
4962 children, rxstats.outRangeLengthError, "outRangeLengthError");
4964 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
4965 NULL, "BGE TX Statistics");
4966 children = SYSCTL_CHILDREN(tree);
4967 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
4968 children, txstats.ifHCOutOctets, "Octets");
4969 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
4970 children, txstats.etherStatsCollisions, "Collisions");
4971 BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
4972 children, txstats.outXonSent, "XonSent");
4973 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
4974 children, txstats.outXoffSent, "XoffSent");
4975 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
4976 children, txstats.flowControlDone, "flowControlDone");
4977 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
4978 children, txstats.dot3StatsInternalMacTransmitErrors,
4979 "InternalMacTransmitErrors");
4980 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
4981 children, txstats.dot3StatsSingleCollisionFrames,
4982 "SingleCollisionFrames");
4983 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
4984 children, txstats.dot3StatsMultipleCollisionFrames,
4985 "MultipleCollisionFrames");
4986 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
4987 children, txstats.dot3StatsDeferredTransmissions,
4988 "DeferredTransmissions");
4989 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
4990 children, txstats.dot3StatsExcessiveCollisions,
4991 "ExcessiveCollisions");
4992 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
4993 children, txstats.dot3StatsLateCollisions,
4995 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
4996 children, txstats.ifHCOutUcastPkts, "UcastPkts");
4997 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
4998 children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
4999 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
5000 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
5001 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
5002 children, txstats.dot3StatsCarrierSenseErrors,
5003 "CarrierSenseErrors");
5004 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
5005 children, txstats.ifOutDiscards, "Discards");
5006 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
5007 children, txstats.ifOutErrors, "Errors");
5011 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
5013 struct bge_softc *sc;
5017 sc = (struct bge_softc *)arg1;
5019 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
5020 offsetof(bge_hostaddr, bge_addr_lo));
5021 return (sysctl_handle_int(oidp, &result, 0, req));
5024 #ifdef BGE_REGISTER_DEBUG
5026 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
5028 struct bge_softc *sc;
5035 error = sysctl_handle_int(oidp, &result, 0, req);
5036 if (error || (req->newptr == NULL))
5040 sc = (struct bge_softc *)arg1;
5042 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
5043 printf("Status Block:\n");
5044 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) {
5046 for (j = 0; j < 8; j++) {
5047 printf(" %04x", sbdata[i]);
5053 printf("Registers:\n");
5054 for (i = 0x800; i < 0xA00; ) {
5056 for (j = 0; j < 8; j++) {
5057 printf(" %08x", CSR_READ_4(sc, i));
5063 printf("Hardware Flags:\n");
5064 if (BGE_IS_5755_PLUS(sc))
5065 printf(" - 5755 Plus\n");
5066 if (BGE_IS_575X_PLUS(sc))
5067 printf(" - 575X Plus\n");
5068 if (BGE_IS_5705_PLUS(sc))
5069 printf(" - 5705 Plus\n");
5070 if (BGE_IS_5714_FAMILY(sc))
5071 printf(" - 5714 Family\n");
5072 if (BGE_IS_5700_FAMILY(sc))
5073 printf(" - 5700 Family\n");
5074 if (sc->bge_flags & BGE_FLAG_JUMBO)
5075 printf(" - Supports Jumbo Frames\n");
5076 if (sc->bge_flags & BGE_FLAG_PCIX)
5077 printf(" - PCI-X Bus\n");
5078 if (sc->bge_flags & BGE_FLAG_PCIE)
5079 printf(" - PCI Express Bus\n");
5080 if (sc->bge_flags & BGE_FLAG_NO_3LED)
5081 printf(" - No 3 LEDs\n");
5082 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
5083 printf(" - RX Alignment Bug\n");
5090 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5092 struct bge_softc *sc;
5098 error = sysctl_handle_int(oidp, &result, 0, req);
5099 if (error || (req->newptr == NULL))
5102 if (result < 0x8000) {
5103 sc = (struct bge_softc *)arg1;
5104 val = CSR_READ_4(sc, result);
5105 printf("reg 0x%06X = 0x%08X\n", result, val);
5112 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
5114 struct bge_softc *sc;
5120 error = sysctl_handle_int(oidp, &result, 0, req);
5121 if (error || (req->newptr == NULL))
5124 if (result < 0x8000) {
5125 sc = (struct bge_softc *)arg1;
5126 val = bge_readmem_ind(sc, result);
5127 printf("mem 0x%06X = 0x%08X\n", result, val);
5135 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
5138 if (sc->bge_flags & BGE_FLAG_EADDR)
5142 OF_getetheraddr(sc->bge_dev, ether_addr);
5149 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
5153 mac_addr = bge_readmem_ind(sc, 0x0c14);
5154 if ((mac_addr >> 16) == 0x484b) {
5155 ether_addr[0] = (uint8_t)(mac_addr >> 8);
5156 ether_addr[1] = (uint8_t)mac_addr;
5157 mac_addr = bge_readmem_ind(sc, 0x0c18);
5158 ether_addr[2] = (uint8_t)(mac_addr >> 24);
5159 ether_addr[3] = (uint8_t)(mac_addr >> 16);
5160 ether_addr[4] = (uint8_t)(mac_addr >> 8);
5161 ether_addr[5] = (uint8_t)mac_addr;
5168 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
5170 int mac_offset = BGE_EE_MAC_OFFSET;
5172 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
5173 mac_offset = BGE_EE_MAC_OFFSET_5906;
5175 return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
5180 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
5183 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
5186 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
5191 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
5193 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
5194 /* NOTE: Order is critical */
5197 bge_get_eaddr_nvram,
5198 bge_get_eaddr_eeprom,
5201 const bge_eaddr_fcn_t *func;
5203 for (func = bge_eaddr_funcs; *func != NULL; ++func) {
5204 if ((*func)(sc, eaddr) == 0)
5207 return (*func == NULL ? ENXIO : 0);