2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet
42 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
45 * frames, highly configurable RX filtering, and 16 RX and TX queues
46 * (which, along with RX filter rules, can be used for QOS applications).
47 * Other features, such as TCP segmentation, may be available as part
48 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
49 * firmware images can be stored in hardware and need not be compiled
52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
55 * The BCM5701 is a single-chip solution incorporating both the BCM5700
56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
57 * does not support external SSRAM.
59 * Broadcom also produces a variation of the BCM5700 under the "Altima"
60 * brand name, which is functionally similar but lacks PCI-X support.
62 * Without external SSRAM, you can only have at most 4 TX rings,
63 * and the use of the mini RX ring is disabled. This seems to imply
64 * that these features are simply not available on the BCM5701. As a
65 * result, this driver does not implement any support for the mini RX
69 #ifdef HAVE_KERNEL_OPTION_HEADERS
70 #include "opt_device_polling.h"
73 #include <sys/param.h>
74 #include <sys/endian.h>
75 #include <sys/systm.h>
76 #include <sys/sockio.h>
78 #include <sys/malloc.h>
79 #include <sys/kernel.h>
80 #include <sys/module.h>
81 #include <sys/socket.h>
82 #include <sys/sysctl.h>
83 #include <sys/taskqueue.h>
86 #include <net/if_arp.h>
87 #include <net/ethernet.h>
88 #include <net/if_dl.h>
89 #include <net/if_media.h>
93 #include <net/if_types.h>
94 #include <net/if_vlan_var.h>
96 #include <netinet/in_systm.h>
97 #include <netinet/in.h>
98 #include <netinet/ip.h>
99 #include <netinet/tcp.h>
101 #include <machine/bus.h>
102 #include <machine/resource.h>
104 #include <sys/rman.h>
106 #include <dev/mii/mii.h>
107 #include <dev/mii/miivar.h>
109 #include <dev/mii/brgphyreg.h>
112 #include <dev/ofw/ofw_bus.h>
113 #include <dev/ofw/openfirm.h>
114 #include <machine/ofw_machdep.h>
115 #include <machine/ver.h>
118 #include <dev/pci/pcireg.h>
119 #include <dev/pci/pcivar.h>
121 #include <dev/bge/if_bgereg.h>
123 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP)
124 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
126 MODULE_DEPEND(bge, pci, 1, 1, 1);
127 MODULE_DEPEND(bge, ether, 1, 1, 1);
128 MODULE_DEPEND(bge, miibus, 1, 1, 1);
130 /* "device miibus" required. See GENERIC if you get errors here. */
131 #include "miibus_if.h"
134 * Various supported device vendors/types and their names. Note: the
135 * spec seems to indicate that the hardware still has Alteon's vendor
136 * ID burned into it, though it will always be overriden by the vendor
137 * ID in the EEPROM. Just to be safe, we cover all possibilities.
139 static const struct bge_type {
143 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 },
144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 },
146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 },
147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 },
148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 },
150 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 },
152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 },
153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 },
154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 },
155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT },
156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X },
157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 },
158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT },
159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X },
160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C },
161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S },
162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT },
163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 },
164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F },
165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K },
166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M },
167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT },
168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C },
169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S },
170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 },
171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S },
172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 },
173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 },
174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 },
175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 },
176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 },
177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 },
178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 },
179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 },
180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M },
181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 },
182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F },
183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M },
184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 },
185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M },
186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 },
187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F },
188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M },
189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 },
190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M },
191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 },
192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M },
193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 },
194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 },
195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E },
196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S },
197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE },
198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 },
199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 },
200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S },
201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 },
202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 },
203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 },
204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F },
205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G },
206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 },
207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 },
208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F },
209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M },
210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 },
211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 },
212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 },
213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 },
214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M },
215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 },
216 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M },
217 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 },
218 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 },
219 { BCOM_VENDORID, BCOM_DEVICEID_BCM57762 },
220 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 },
221 { BCOM_VENDORID, BCOM_DEVICEID_BCM57766 },
222 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 },
223 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 },
224 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 },
225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 },
226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 },
227 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 },
228 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 },
230 { SK_VENDORID, SK_DEVICEID_ALTIMA },
232 { TC_VENDORID, TC_DEVICEID_3C996 },
234 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 },
235 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 },
236 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 },
241 static const struct bge_vendor {
245 { ALTEON_VENDORID, "Alteon" },
246 { ALTIMA_VENDORID, "Altima" },
247 { APPLE_VENDORID, "Apple" },
248 { BCOM_VENDORID, "Broadcom" },
249 { SK_VENDORID, "SysKonnect" },
250 { TC_VENDORID, "3Com" },
251 { FJTSU_VENDORID, "Fujitsu" },
256 static const struct bge_revision {
259 } bge_revisions[] = {
260 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" },
261 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" },
262 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" },
263 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" },
264 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" },
265 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" },
266 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" },
267 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" },
268 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" },
269 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" },
270 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" },
271 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" },
272 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" },
273 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" },
274 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" },
275 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" },
276 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" },
277 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" },
278 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" },
279 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" },
280 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" },
281 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" },
282 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" },
283 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" },
284 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" },
285 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" },
286 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" },
287 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" },
288 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" },
289 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" },
290 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" },
291 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" },
292 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" },
293 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" },
294 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
295 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
296 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
297 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
298 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
299 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
300 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
301 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
302 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
303 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" },
304 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" },
305 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" },
306 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" },
307 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
308 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
309 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
310 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" },
311 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" },
312 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" },
313 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" },
314 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" },
315 /* 5754 and 5787 share the same ASIC ID */
316 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
317 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
318 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
319 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" },
320 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" },
321 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" },
322 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" },
323 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" },
324 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" },
330 * Some defaults for major revisions, so that newer steppings
331 * that we don't know about have a shot at working.
333 static const struct bge_revision bge_majorrevs[] = {
334 { BGE_ASICREV_BCM5700, "unknown BCM5700" },
335 { BGE_ASICREV_BCM5701, "unknown BCM5701" },
336 { BGE_ASICREV_BCM5703, "unknown BCM5703" },
337 { BGE_ASICREV_BCM5704, "unknown BCM5704" },
338 { BGE_ASICREV_BCM5705, "unknown BCM5705" },
339 { BGE_ASICREV_BCM5750, "unknown BCM5750" },
340 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
341 { BGE_ASICREV_BCM5752, "unknown BCM5752" },
342 { BGE_ASICREV_BCM5780, "unknown BCM5780" },
343 { BGE_ASICREV_BCM5714, "unknown BCM5714" },
344 { BGE_ASICREV_BCM5755, "unknown BCM5755" },
345 { BGE_ASICREV_BCM5761, "unknown BCM5761" },
346 { BGE_ASICREV_BCM5784, "unknown BCM5784" },
347 { BGE_ASICREV_BCM5785, "unknown BCM5785" },
348 /* 5754 and 5787 share the same ASIC ID */
349 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
350 { BGE_ASICREV_BCM5906, "unknown BCM5906" },
351 { BGE_ASICREV_BCM57765, "unknown BCM57765" },
352 { BGE_ASICREV_BCM57766, "unknown BCM57766" },
353 { BGE_ASICREV_BCM57780, "unknown BCM57780" },
354 { BGE_ASICREV_BCM5717, "unknown BCM5717" },
355 { BGE_ASICREV_BCM5719, "unknown BCM5719" },
356 { BGE_ASICREV_BCM5720, "unknown BCM5720" },
361 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
362 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
363 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
364 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
365 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
366 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
367 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS)
368 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_57765_PLUS)
370 static uint32_t bge_chipid(device_t);
371 static const struct bge_vendor * bge_lookup_vendor(uint16_t);
372 static const struct bge_revision * bge_lookup_rev(uint32_t);
374 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
376 static int bge_probe(device_t);
377 static int bge_attach(device_t);
378 static int bge_detach(device_t);
379 static int bge_suspend(device_t);
380 static int bge_resume(device_t);
381 static void bge_release_resources(struct bge_softc *);
382 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
383 static int bge_dma_alloc(struct bge_softc *);
384 static void bge_dma_free(struct bge_softc *);
385 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t,
386 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
388 static void bge_devinfo(struct bge_softc *);
389 static int bge_mbox_reorder(struct bge_softc *);
391 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
392 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
393 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
394 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
395 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
397 static void bge_txeof(struct bge_softc *, uint16_t);
398 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
399 static int bge_rxeof(struct bge_softc *, uint16_t, int);
401 static void bge_asf_driver_up (struct bge_softc *);
402 static void bge_tick(void *);
403 static void bge_stats_clear_regs(struct bge_softc *);
404 static void bge_stats_update(struct bge_softc *);
405 static void bge_stats_update_regs(struct bge_softc *);
406 static struct mbuf *bge_check_short_dma(struct mbuf *);
407 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
408 uint16_t *, uint16_t *);
409 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
411 static void bge_intr(void *);
412 static int bge_msi_intr(void *);
413 static void bge_intr_task(void *, int);
414 static void bge_start_locked(struct ifnet *);
415 static void bge_start(struct ifnet *);
416 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
417 static void bge_init_locked(struct bge_softc *);
418 static void bge_init(void *);
419 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
420 static void bge_stop(struct bge_softc *);
421 static void bge_watchdog(struct bge_softc *);
422 static int bge_shutdown(device_t);
423 static int bge_ifmedia_upd_locked(struct ifnet *);
424 static int bge_ifmedia_upd(struct ifnet *);
425 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
427 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
428 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
430 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
431 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
433 static void bge_setpromisc(struct bge_softc *);
434 static void bge_setmulti(struct bge_softc *);
435 static void bge_setvlan(struct bge_softc *);
437 static __inline void bge_rxreuse_std(struct bge_softc *, int);
438 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
439 static int bge_newbuf_std(struct bge_softc *, int);
440 static int bge_newbuf_jumbo(struct bge_softc *, int);
441 static int bge_init_rx_ring_std(struct bge_softc *);
442 static void bge_free_rx_ring_std(struct bge_softc *);
443 static int bge_init_rx_ring_jumbo(struct bge_softc *);
444 static void bge_free_rx_ring_jumbo(struct bge_softc *);
445 static void bge_free_tx_ring(struct bge_softc *);
446 static int bge_init_tx_ring(struct bge_softc *);
448 static int bge_chipinit(struct bge_softc *);
449 static int bge_blockinit(struct bge_softc *);
450 static uint32_t bge_dma_swap_options(struct bge_softc *);
452 static int bge_has_eaddr(struct bge_softc *);
453 static uint32_t bge_readmem_ind(struct bge_softc *, int);
454 static void bge_writemem_ind(struct bge_softc *, int, int);
455 static void bge_writembx(struct bge_softc *, int, int);
457 static uint32_t bge_readreg_ind(struct bge_softc *, int);
459 static void bge_writemem_direct(struct bge_softc *, int, int);
460 static void bge_writereg_ind(struct bge_softc *, int, int);
462 static int bge_miibus_readreg(device_t, int, int);
463 static int bge_miibus_writereg(device_t, int, int, int);
464 static void bge_miibus_statchg(device_t);
465 #ifdef DEVICE_POLLING
466 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
469 #define BGE_RESET_SHUTDOWN 0
470 #define BGE_RESET_START 1
471 #define BGE_RESET_SUSPEND 2
472 static void bge_sig_post_reset(struct bge_softc *, int);
473 static void bge_sig_legacy(struct bge_softc *, int);
474 static void bge_sig_pre_reset(struct bge_softc *, int);
475 static void bge_stop_fw(struct bge_softc *);
476 static int bge_reset(struct bge_softc *);
477 static void bge_link_upd(struct bge_softc *);
479 static void bge_ape_lock_init(struct bge_softc *);
480 static void bge_ape_read_fw_ver(struct bge_softc *);
481 static int bge_ape_lock(struct bge_softc *, int);
482 static void bge_ape_unlock(struct bge_softc *, int);
483 static void bge_ape_send_event(struct bge_softc *, uint32_t);
484 static void bge_ape_driver_state_change(struct bge_softc *, int);
487 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may
488 * leak information to untrusted users. It is also known to cause alignment
489 * traps on certain architectures.
491 #ifdef BGE_REGISTER_DEBUG
492 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
493 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
494 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS);
495 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
497 static void bge_add_sysctls(struct bge_softc *);
498 static void bge_add_sysctl_stats_regs(struct bge_softc *,
499 struct sysctl_ctx_list *, struct sysctl_oid_list *);
500 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *,
501 struct sysctl_oid_list *);
502 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
504 static device_method_t bge_methods[] = {
505 /* Device interface */
506 DEVMETHOD(device_probe, bge_probe),
507 DEVMETHOD(device_attach, bge_attach),
508 DEVMETHOD(device_detach, bge_detach),
509 DEVMETHOD(device_shutdown, bge_shutdown),
510 DEVMETHOD(device_suspend, bge_suspend),
511 DEVMETHOD(device_resume, bge_resume),
514 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
515 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
516 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
521 static driver_t bge_driver = {
524 sizeof(struct bge_softc)
527 static devclass_t bge_devclass;
529 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
530 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
532 static int bge_allow_asf = 1;
534 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
536 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
537 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
538 "Allow ASF mode if available");
540 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500"
541 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2"
542 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500"
543 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3"
544 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id"
547 bge_has_eaddr(struct bge_softc *sc)
550 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
557 * The on-board BGEs found in sun4u machines aren't fitted with
558 * an EEPROM which means that we have to obtain the MAC address
559 * via OFW and that some tests will always fail. We distinguish
560 * such BGEs by the subvendor ID, which also has to be obtained
561 * from OFW instead of the PCI configuration space as the latter
562 * indicates Broadcom as the subvendor of the netboot interface.
563 * For early Blade 1500 and 2500 we even have to check the OFW
564 * device path as the subvendor ID always defaults to Broadcom
567 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
568 &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
569 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID))
571 memset(buf, 0, sizeof(buf));
572 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
573 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
574 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
576 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
577 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
585 bge_readmem_ind(struct bge_softc *sc, int off)
590 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
591 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
596 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
597 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
598 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
603 bge_writemem_ind(struct bge_softc *sc, int off, int val)
607 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
608 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
613 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
614 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
615 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
620 bge_readreg_ind(struct bge_softc *sc, int off)
626 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
627 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
632 bge_writereg_ind(struct bge_softc *sc, int off, int val)
638 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
639 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
643 bge_writemem_direct(struct bge_softc *sc, int off, int val)
645 CSR_WRITE_4(sc, off, val);
649 bge_writembx(struct bge_softc *sc, int off, int val)
651 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
652 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
654 CSR_WRITE_4(sc, off, val);
655 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0)
660 * Clear all stale locks and select the lock for this driver instance.
663 bge_ape_lock_init(struct bge_softc *sc)
665 uint32_t bit, regbase;
668 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
669 regbase = BGE_APE_LOCK_GRANT;
671 regbase = BGE_APE_PER_LOCK_GRANT;
673 /* Clear any stale locks. */
674 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
676 case BGE_APE_LOCK_PHY0:
677 case BGE_APE_LOCK_PHY1:
678 case BGE_APE_LOCK_PHY2:
679 case BGE_APE_LOCK_PHY3:
680 bit = BGE_APE_LOCK_GRANT_DRIVER0;
683 if (sc->bge_func_addr == 0)
684 bit = BGE_APE_LOCK_GRANT_DRIVER0;
686 bit = (1 << sc->bge_func_addr);
688 APE_WRITE_4(sc, regbase + 4 * i, bit);
691 /* Select the PHY lock based on the device's function number. */
692 switch (sc->bge_func_addr) {
694 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
697 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
700 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
703 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
706 device_printf(sc->bge_dev,
707 "PHY lock not supported on this function\n");
712 * Check for APE firmware, set flags, and print version info.
715 bge_ape_read_fw_ver(struct bge_softc *sc)
718 uint32_t apedata, features;
720 /* Check for a valid APE signature in shared memory. */
721 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
722 if (apedata != BGE_APE_SEG_SIG_MAGIC) {
723 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE;
727 /* Check if APE firmware is running. */
728 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
729 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) {
730 device_printf(sc->bge_dev, "APE signature found "
731 "but FW status not ready! 0x%08x\n", apedata);
735 sc->bge_mfw_flags |= BGE_MFW_ON_APE;
737 /* Fetch the APE firwmare type and version. */
738 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
739 features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
740 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) {
741 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
743 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) {
744 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
749 /* Print the APE firmware version. */
750 device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n",
752 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT,
753 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT,
754 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT,
755 (apedata & BGE_APE_FW_VERSION_BLDMSK));
759 bge_ape_lock(struct bge_softc *sc, int locknum)
761 uint32_t bit, gnt, req, status;
764 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
767 /* Lock request/grant registers have different bases. */
768 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) {
769 req = BGE_APE_LOCK_REQ;
770 gnt = BGE_APE_LOCK_GRANT;
772 req = BGE_APE_PER_LOCK_REQ;
773 gnt = BGE_APE_PER_LOCK_GRANT;
779 case BGE_APE_LOCK_GPIO:
780 /* Lock required when using GPIO. */
781 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
783 if (sc->bge_func_addr == 0)
784 bit = BGE_APE_LOCK_REQ_DRIVER0;
786 bit = (1 << sc->bge_func_addr);
788 case BGE_APE_LOCK_GRC:
789 /* Lock required to reset the device. */
790 if (sc->bge_func_addr == 0)
791 bit = BGE_APE_LOCK_REQ_DRIVER0;
793 bit = (1 << sc->bge_func_addr);
795 case BGE_APE_LOCK_MEM:
796 /* Lock required when accessing certain APE memory. */
797 if (sc->bge_func_addr == 0)
798 bit = BGE_APE_LOCK_REQ_DRIVER0;
800 bit = (1 << sc->bge_func_addr);
802 case BGE_APE_LOCK_PHY0:
803 case BGE_APE_LOCK_PHY1:
804 case BGE_APE_LOCK_PHY2:
805 case BGE_APE_LOCK_PHY3:
806 /* Lock required when accessing PHYs. */
807 bit = BGE_APE_LOCK_REQ_DRIVER0;
813 /* Request a lock. */
814 APE_WRITE_4(sc, req + off, bit);
816 /* Wait up to 1 second to acquire lock. */
817 for (i = 0; i < 20000; i++) {
818 status = APE_READ_4(sc, gnt + off);
824 /* Handle any errors. */
826 device_printf(sc->bge_dev, "APE lock %d request failed! "
827 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
828 locknum, req + off, bit & 0xFFFF, gnt + off,
830 /* Revoke the lock request. */
831 APE_WRITE_4(sc, gnt + off, bit);
839 bge_ape_unlock(struct bge_softc *sc, int locknum)
844 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
847 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
848 gnt = BGE_APE_LOCK_GRANT;
850 gnt = BGE_APE_PER_LOCK_GRANT;
855 case BGE_APE_LOCK_GPIO:
856 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
858 if (sc->bge_func_addr == 0)
859 bit = BGE_APE_LOCK_GRANT_DRIVER0;
861 bit = (1 << sc->bge_func_addr);
863 case BGE_APE_LOCK_GRC:
864 if (sc->bge_func_addr == 0)
865 bit = BGE_APE_LOCK_GRANT_DRIVER0;
867 bit = (1 << sc->bge_func_addr);
869 case BGE_APE_LOCK_MEM:
870 if (sc->bge_func_addr == 0)
871 bit = BGE_APE_LOCK_GRANT_DRIVER0;
873 bit = (1 << sc->bge_func_addr);
875 case BGE_APE_LOCK_PHY0:
876 case BGE_APE_LOCK_PHY1:
877 case BGE_APE_LOCK_PHY2:
878 case BGE_APE_LOCK_PHY3:
879 bit = BGE_APE_LOCK_GRANT_DRIVER0;
885 APE_WRITE_4(sc, gnt + off, bit);
889 * Send an event to the APE firmware.
892 bge_ape_send_event(struct bge_softc *sc, uint32_t event)
897 /* NCSI does not support APE events. */
898 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
901 /* Wait up to 1ms for APE to service previous event. */
902 for (i = 10; i > 0; i--) {
903 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
905 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
906 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) {
907 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
908 BGE_APE_EVENT_STATUS_EVENT_PENDING);
909 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
910 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
913 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
917 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n",
922 bge_ape_driver_state_change(struct bge_softc *sc, int kind)
924 uint32_t apedata, event;
926 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
930 case BGE_RESET_START:
931 /* If this is the first load, clear the load counter. */
932 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
933 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC)
934 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
936 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
937 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
939 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
940 BGE_APE_HOST_SEG_SIG_MAGIC);
941 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
942 BGE_APE_HOST_SEG_LEN_MAGIC);
944 /* Add some version info if bge(4) supports it. */
945 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
946 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0));
947 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
948 BGE_APE_HOST_BEHAV_NO_PHYLOCK);
949 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
950 BGE_APE_HOST_HEARTBEAT_INT_DISABLE);
951 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
952 BGE_APE_HOST_DRVR_STATE_START);
953 event = BGE_APE_EVENT_STATUS_STATE_START;
955 case BGE_RESET_SHUTDOWN:
956 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
957 BGE_APE_HOST_DRVR_STATE_UNLOAD);
958 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
960 case BGE_RESET_SUSPEND:
961 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
967 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
968 BGE_APE_EVENT_STATUS_STATE_CHNGE);
972 * Map a single buffer address.
976 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
978 struct bge_dmamap_arg *ctx;
983 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
986 ctx->bge_busaddr = segs->ds_addr;
990 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
992 uint32_t access, byte = 0;
996 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
997 for (i = 0; i < 8000; i++) {
998 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
1005 /* Enable access. */
1006 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
1007 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
1009 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
1010 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
1011 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
1013 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
1019 if (i == BGE_TIMEOUT * 10) {
1020 if_printf(sc->bge_ifp, "nvram read timed out\n");
1025 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
1027 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
1029 /* Disable access. */
1030 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
1033 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
1034 CSR_READ_4(sc, BGE_NVRAM_SWARB);
1040 * Read a sequence of bytes from NVRAM.
1043 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1048 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1051 for (i = 0; i < cnt; i++) {
1052 err = bge_nvram_getbyte(sc, off + i, &byte);
1058 return (err ? 1 : 0);
1062 * Read a byte of data stored in the EEPROM at address 'addr.' The
1063 * BCM570x supports both the traditional bitbang interface and an
1064 * auto access interface for reading the EEPROM. We use the auto
1068 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1074 * Enable use of auto EEPROM access so we can avoid
1075 * having to use the bitbang method.
1077 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
1079 /* Reset the EEPROM, load the clock period. */
1080 CSR_WRITE_4(sc, BGE_EE_ADDR,
1081 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
1084 /* Issue the read EEPROM command. */
1085 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
1087 /* Wait for completion */
1088 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
1090 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1094 if (i == BGE_TIMEOUT * 10) {
1095 device_printf(sc->bge_dev, "EEPROM read timed out\n");
1100 byte = CSR_READ_4(sc, BGE_EE_DATA);
1102 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
1108 * Read a sequence of bytes from the EEPROM.
1111 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1116 for (i = 0; i < cnt; i++) {
1117 error = bge_eeprom_getbyte(sc, off + i, &byte);
1123 return (error ? 1 : 0);
1127 bge_miibus_readreg(device_t dev, int phy, int reg)
1129 struct bge_softc *sc;
1133 sc = device_get_softc(dev);
1135 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1138 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1139 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1140 CSR_WRITE_4(sc, BGE_MI_MODE,
1141 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1145 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
1146 BGE_MIPHY(phy) | BGE_MIREG(reg));
1148 /* Poll for the PHY register access to complete. */
1149 for (i = 0; i < BGE_TIMEOUT; i++) {
1151 val = CSR_READ_4(sc, BGE_MI_COMM);
1152 if ((val & BGE_MICOMM_BUSY) == 0) {
1154 val = CSR_READ_4(sc, BGE_MI_COMM);
1159 if (i == BGE_TIMEOUT) {
1160 device_printf(sc->bge_dev,
1161 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
1166 /* Restore the autopoll bit if necessary. */
1167 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1168 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1172 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1174 if (val & BGE_MICOMM_READFAIL)
1177 return (val & 0xFFFF);
1181 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
1183 struct bge_softc *sc;
1186 sc = device_get_softc(dev);
1188 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1189 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
1192 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1195 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1196 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1197 CSR_WRITE_4(sc, BGE_MI_MODE,
1198 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1202 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
1203 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
1205 for (i = 0; i < BGE_TIMEOUT; i++) {
1207 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
1209 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
1214 /* Restore the autopoll bit if necessary. */
1215 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1216 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1220 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1222 if (i == BGE_TIMEOUT)
1223 device_printf(sc->bge_dev,
1224 "PHY write timed out (phy %d, reg %d, val 0x%04x)\n",
1231 bge_miibus_statchg(device_t dev)
1233 struct bge_softc *sc;
1234 struct mii_data *mii;
1235 uint32_t mac_mode, rx_mode, tx_mode;
1237 sc = device_get_softc(dev);
1238 if ((sc->bge_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1240 mii = device_get_softc(sc->bge_miibus);
1242 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1243 (IFM_ACTIVE | IFM_AVALID)) {
1244 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1252 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1263 if (sc->bge_link == 0)
1267 * APE firmware touches these registers to keep the MAC
1268 * connected to the outside world. Try to keep the
1272 /* Set the port mode (MII/GMII) to match the link speed. */
1273 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
1274 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
1275 tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
1276 rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
1278 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1279 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
1280 mac_mode |= BGE_PORTMODE_GMII;
1282 mac_mode |= BGE_PORTMODE_MII;
1284 /* Set MAC flow control behavior to match link flow control settings. */
1285 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE;
1286 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE;
1287 if (IFM_OPTIONS(mii->mii_media_active & IFM_FDX) != 0) {
1288 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1289 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE;
1290 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1291 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE;
1293 mac_mode |= BGE_MACMODE_HALF_DUPLEX;
1295 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
1297 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
1298 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
1302 * Intialize a standard receive ring descriptor.
1305 bge_newbuf_std(struct bge_softc *sc, int i)
1308 struct bge_rx_bd *r;
1309 bus_dma_segment_t segs[1];
1313 if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
1314 (sc->bge_ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN +
1315 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) {
1316 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1319 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1321 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1324 m->m_len = m->m_pkthdr.len = MCLBYTES;
1326 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1327 m_adj(m, ETHER_ALIGN);
1329 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
1330 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
1335 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1336 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1337 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
1338 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1339 sc->bge_cdata.bge_rx_std_dmamap[i]);
1341 map = sc->bge_cdata.bge_rx_std_dmamap[i];
1342 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
1343 sc->bge_cdata.bge_rx_std_sparemap = map;
1344 sc->bge_cdata.bge_rx_std_chain[i] = m;
1345 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
1346 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
1347 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1348 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1349 r->bge_flags = BGE_RXBDFLAG_END;
1350 r->bge_len = segs[0].ds_len;
1353 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1354 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
1360 * Initialize a jumbo receive ring descriptor. This allocates
1361 * a jumbo buffer from the pool managed internally by the driver.
1364 bge_newbuf_jumbo(struct bge_softc *sc, int i)
1366 bus_dma_segment_t segs[BGE_NSEG_JUMBO];
1368 struct bge_extrx_bd *r;
1372 MGETHDR(m, M_NOWAIT, MT_DATA);
1376 m_cljget(m, M_NOWAIT, MJUM9BYTES);
1377 if (!(m->m_flags & M_EXT)) {
1381 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1382 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1383 m_adj(m, ETHER_ALIGN);
1385 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1386 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1392 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1393 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1394 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1395 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1396 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1398 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1399 sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1400 sc->bge_cdata.bge_rx_jumbo_sparemap;
1401 sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1402 sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1403 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1404 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1405 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1406 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1409 * Fill in the extended RX buffer descriptor.
1411 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1412 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1414 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1417 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1418 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1419 r->bge_len3 = segs[3].ds_len;
1420 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1422 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1423 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1424 r->bge_len2 = segs[2].ds_len;
1425 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1427 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1428 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1429 r->bge_len1 = segs[1].ds_len;
1430 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1432 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1433 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1434 r->bge_len0 = segs[0].ds_len;
1435 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1438 panic("%s: %d segments\n", __func__, nsegs);
1441 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1442 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1448 bge_init_rx_ring_std(struct bge_softc *sc)
1452 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1454 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1455 if ((error = bge_newbuf_std(sc, i)) != 0)
1457 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1460 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1461 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1464 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1470 bge_free_rx_ring_std(struct bge_softc *sc)
1474 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1475 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1476 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1477 sc->bge_cdata.bge_rx_std_dmamap[i],
1478 BUS_DMASYNC_POSTREAD);
1479 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1480 sc->bge_cdata.bge_rx_std_dmamap[i]);
1481 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1482 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1484 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1485 sizeof(struct bge_rx_bd));
1490 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1492 struct bge_rcb *rcb;
1495 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1497 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1498 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1500 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1503 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1504 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1508 /* Enable the jumbo receive producer ring. */
1509 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1510 rcb->bge_maxlen_flags =
1511 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD);
1512 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1514 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1520 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1524 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1525 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1526 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1527 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1528 BUS_DMASYNC_POSTREAD);
1529 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1530 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1531 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1532 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1534 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1535 sizeof(struct bge_extrx_bd));
1540 bge_free_tx_ring(struct bge_softc *sc)
1544 if (sc->bge_ldata.bge_tx_ring == NULL)
1547 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1548 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1549 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1550 sc->bge_cdata.bge_tx_dmamap[i],
1551 BUS_DMASYNC_POSTWRITE);
1552 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1553 sc->bge_cdata.bge_tx_dmamap[i]);
1554 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1555 sc->bge_cdata.bge_tx_chain[i] = NULL;
1557 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1558 sizeof(struct bge_tx_bd));
1563 bge_init_tx_ring(struct bge_softc *sc)
1566 sc->bge_tx_saved_considx = 0;
1568 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1569 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1570 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1572 /* Initialize transmit producer index for host-memory send ring. */
1573 sc->bge_tx_prodidx = 0;
1574 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1576 /* 5700 b2 errata */
1577 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1578 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1580 /* NIC-memory send ring not used; initialize to zero. */
1581 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1582 /* 5700 b2 errata */
1583 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1584 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1590 bge_setpromisc(struct bge_softc *sc)
1594 BGE_LOCK_ASSERT(sc);
1598 /* Enable or disable promiscuous mode as needed. */
1599 if (ifp->if_flags & IFF_PROMISC)
1600 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1602 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1606 bge_setmulti(struct bge_softc *sc)
1609 struct ifmultiaddr *ifma;
1610 uint32_t hashes[4] = { 0, 0, 0, 0 };
1613 BGE_LOCK_ASSERT(sc);
1617 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1618 for (i = 0; i < 4; i++)
1619 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1623 /* First, zot all the existing filters. */
1624 for (i = 0; i < 4; i++)
1625 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1627 /* Now program new ones. */
1628 if_maddr_rlock(ifp);
1629 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1630 if (ifma->ifma_addr->sa_family != AF_LINK)
1632 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1633 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1634 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1636 if_maddr_runlock(ifp);
1638 for (i = 0; i < 4; i++)
1639 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1643 bge_setvlan(struct bge_softc *sc)
1647 BGE_LOCK_ASSERT(sc);
1651 /* Enable or disable VLAN tag stripping as needed. */
1652 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1653 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1655 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1659 bge_sig_pre_reset(struct bge_softc *sc, int type)
1663 * Some chips don't like this so only do this if ASF is enabled
1665 if (sc->bge_asf_mode)
1666 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
1668 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1670 case BGE_RESET_START:
1671 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1672 BGE_FW_DRV_STATE_START);
1674 case BGE_RESET_SHUTDOWN:
1675 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1676 BGE_FW_DRV_STATE_UNLOAD);
1678 case BGE_RESET_SUSPEND:
1679 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1680 BGE_FW_DRV_STATE_SUSPEND);
1685 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
1686 bge_ape_driver_state_change(sc, type);
1690 bge_sig_post_reset(struct bge_softc *sc, int type)
1693 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1695 case BGE_RESET_START:
1696 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1697 BGE_FW_DRV_STATE_START_DONE);
1700 case BGE_RESET_SHUTDOWN:
1701 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1702 BGE_FW_DRV_STATE_UNLOAD_DONE);
1706 if (type == BGE_RESET_SHUTDOWN)
1707 bge_ape_driver_state_change(sc, type);
1711 bge_sig_legacy(struct bge_softc *sc, int type)
1714 if (sc->bge_asf_mode) {
1716 case BGE_RESET_START:
1717 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1718 BGE_FW_DRV_STATE_START);
1720 case BGE_RESET_SHUTDOWN:
1721 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1722 BGE_FW_DRV_STATE_UNLOAD);
1729 bge_stop_fw(struct bge_softc *sc)
1733 if (sc->bge_asf_mode) {
1734 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
1735 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
1736 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
1738 for (i = 0; i < 100; i++ ) {
1739 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1740 BGE_RX_CPU_DRV_EVENT))
1748 bge_dma_swap_options(struct bge_softc *sc)
1750 uint32_t dma_options;
1752 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
1753 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
1754 #if BYTE_ORDER == BIG_ENDIAN
1755 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
1757 return (dma_options);
1761 * Do endian, PCI and DMA initialization.
1764 bge_chipinit(struct bge_softc *sc)
1766 uint32_t dma_rw_ctl, misc_ctl, mode_ctl;
1770 /* Set endianness before we access any non-PCI registers. */
1771 misc_ctl = BGE_INIT;
1772 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1773 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1774 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1777 * Clear the MAC statistics block in the NIC's
1780 for (i = BGE_STATS_BLOCK;
1781 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1782 BGE_MEMWIN_WRITE(sc, i, 0);
1784 for (i = BGE_STATUS_BLOCK;
1785 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1786 BGE_MEMWIN_WRITE(sc, i, 0);
1788 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1790 * Fix data corruption caused by non-qword write with WB.
1791 * Fix master abort in PCI mode.
1792 * Fix PCI latency timer.
1794 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1795 val |= (1 << 10) | (1 << 12) | (1 << 13);
1796 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1800 * Set up the PCI DMA control register.
1802 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1803 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1804 if (sc->bge_flags & BGE_FLAG_PCIE) {
1805 if (sc->bge_mps >= 256)
1806 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1808 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1809 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1810 if (BGE_IS_5714_FAMILY(sc)) {
1811 /* 256 bytes for read and write. */
1812 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1813 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1814 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1815 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1816 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1817 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1819 * In the BCM5703, the DMA read watermark should
1820 * be set to less than or equal to the maximum
1821 * memory read byte count of the PCI-X command
1824 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1825 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1826 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1827 /* 1536 bytes for read, 384 bytes for write. */
1828 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1829 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1831 /* 384 bytes for read and write. */
1832 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1833 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1836 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1837 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1840 /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1841 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1842 if (tmp == 6 || tmp == 7)
1844 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1846 /* Set PCI-X DMA write workaround. */
1847 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1850 /* Conventional PCI bus: 256 bytes for read and write. */
1851 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1852 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1854 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1855 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1858 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1859 sc->bge_asicrev == BGE_ASICREV_BCM5701)
1860 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1861 BGE_PCIDMARWCTL_ASRT_ALL_BE;
1862 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1863 sc->bge_asicrev == BGE_ASICREV_BCM5704)
1864 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1865 if (BGE_IS_5717_PLUS(sc)) {
1866 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1867 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
1868 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1870 * Enable HW workaround for controllers that misinterpret
1871 * a status tag update and leave interrupts permanently
1874 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
1875 sc->bge_asicrev != BGE_ASICREV_BCM57765)
1876 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1878 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1881 * Set up general mode register.
1883 mode_ctl = bge_dma_swap_options(sc);
1884 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
1885 /* Retain Host-2-BMC settings written by APE firmware. */
1886 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
1887 (BGE_MODECTL_BYTESWAP_B2HRX_DATA |
1888 BGE_MODECTL_WORDSWAP_B2HRX_DATA |
1889 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE);
1891 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1892 BGE_MODECTL_TX_NO_PHDR_CSUM;
1895 * BCM5701 B5 have a bug causing data corruption when using
1896 * 64-bit DMA reads, which can be terminated early and then
1897 * completed later as 32-bit accesses, in combination with
1900 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1901 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1902 mode_ctl |= BGE_MODECTL_FORCE_PCI32;
1905 * Tell the firmware the driver is running
1907 if (sc->bge_asf_mode & ASF_STACKUP)
1908 mode_ctl |= BGE_MODECTL_STACKUP;
1910 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1913 * Disable memory write invalidate. Apparently it is not supported
1914 * properly by these devices. Also ensure that INTx isn't disabled,
1915 * as these chips need it even when using MSI.
1917 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1918 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
1920 /* Set the timer prescaler (always 66 MHz). */
1921 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1923 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1924 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1925 DELAY(40); /* XXX */
1927 /* Put PHY into ready state */
1928 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1929 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1937 bge_blockinit(struct bge_softc *sc)
1939 struct bge_rcb *rcb;
1942 uint32_t dmactl, val;
1946 * Initialize the memory window pointer register so that
1947 * we can access the first 32K of internal NIC RAM. This will
1948 * allow us to set up the TX send ring RCBs and the RX return
1949 * ring RCBs, plus other things which live in NIC memory.
1951 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1953 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1955 if (!(BGE_IS_5705_PLUS(sc))) {
1956 /* Configure mbuf memory pool */
1957 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1958 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1959 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1961 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1963 /* Configure DMA resource pool */
1964 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1965 BGE_DMA_DESCRIPTORS);
1966 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1969 /* Configure mbuf pool watermarks */
1970 if (BGE_IS_5717_PLUS(sc)) {
1971 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1972 if (sc->bge_ifp->if_mtu > ETHERMTU) {
1973 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1974 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1976 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1977 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1979 } else if (!BGE_IS_5705_PLUS(sc)) {
1980 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1981 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1982 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1983 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1984 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1985 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1986 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1988 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1989 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1990 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1993 /* Configure DMA resource watermarks */
1994 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1995 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1997 /* Enable buffer manager */
1998 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
2000 * Change the arbitration algorithm of TXMBUF read request to
2001 * round-robin instead of priority based for BCM5719. When
2002 * TXFIFO is almost empty, RDMA will hold its request until
2003 * TXFIFO is not almost empty.
2005 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2006 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
2007 CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
2009 /* Poll for buffer manager start indication */
2010 for (i = 0; i < BGE_TIMEOUT; i++) {
2012 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
2016 if (i == BGE_TIMEOUT) {
2017 device_printf(sc->bge_dev, "buffer manager failed to start\n");
2021 /* Enable flow-through queues */
2022 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2023 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2025 /* Wait until queue initialization is complete */
2026 for (i = 0; i < BGE_TIMEOUT; i++) {
2028 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
2032 if (i == BGE_TIMEOUT) {
2033 device_printf(sc->bge_dev, "flow-through queue init failed\n");
2038 * Summary of rings supported by the controller:
2040 * Standard Receive Producer Ring
2041 * - This ring is used to feed receive buffers for "standard"
2042 * sized frames (typically 1536 bytes) to the controller.
2044 * Jumbo Receive Producer Ring
2045 * - This ring is used to feed receive buffers for jumbo sized
2046 * frames (i.e. anything bigger than the "standard" frames)
2047 * to the controller.
2049 * Mini Receive Producer Ring
2050 * - This ring is used to feed receive buffers for "mini"
2051 * sized frames to the controller.
2052 * - This feature required external memory for the controller
2053 * but was never used in a production system. Should always
2056 * Receive Return Ring
2057 * - After the controller has placed an incoming frame into a
2058 * receive buffer that buffer is moved into a receive return
2059 * ring. The driver is then responsible to passing the
2060 * buffer up to the stack. Many versions of the controller
2061 * support multiple RR rings.
2064 * - This ring is used for outgoing frames. Many versions of
2065 * the controller support multiple send rings.
2068 /* Initialize the standard receive producer ring control block. */
2069 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
2070 rcb->bge_hostaddr.bge_addr_lo =
2071 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
2072 rcb->bge_hostaddr.bge_addr_hi =
2073 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
2074 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2075 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
2076 if (BGE_IS_5717_PLUS(sc)) {
2078 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
2079 * Bits 15-2 : Maximum RX frame size
2080 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled
2083 rcb->bge_maxlen_flags =
2084 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
2085 } else if (BGE_IS_5705_PLUS(sc)) {
2087 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
2088 * Bits 15-2 : Reserved (should be 0)
2089 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
2092 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
2095 * Ring size is always XXX entries
2096 * Bits 31-16: Maximum RX frame size
2097 * Bits 15-2 : Reserved (should be 0)
2098 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
2101 rcb->bge_maxlen_flags =
2102 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
2104 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2105 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2106 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2107 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
2109 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
2110 /* Write the standard receive producer ring control block. */
2111 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
2112 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
2113 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
2114 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
2116 /* Reset the standard receive producer ring producer index. */
2117 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
2120 * Initialize the jumbo RX producer ring control
2121 * block. We set the 'ring disabled' bit in the
2122 * flags field until we're actually ready to start
2123 * using this ring (i.e. once we set the MTU
2124 * high enough to require it).
2126 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2127 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
2128 /* Get the jumbo receive producer ring RCB parameters. */
2129 rcb->bge_hostaddr.bge_addr_lo =
2130 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2131 rcb->bge_hostaddr.bge_addr_hi =
2132 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2133 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2134 sc->bge_cdata.bge_rx_jumbo_ring_map,
2135 BUS_DMASYNC_PREREAD);
2136 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
2137 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
2138 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2139 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2140 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2141 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
2143 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
2144 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
2145 rcb->bge_hostaddr.bge_addr_hi);
2146 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
2147 rcb->bge_hostaddr.bge_addr_lo);
2148 /* Program the jumbo receive producer ring RCB parameters. */
2149 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
2150 rcb->bge_maxlen_flags);
2151 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
2152 /* Reset the jumbo receive producer ring producer index. */
2153 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
2156 /* Disable the mini receive producer ring RCB. */
2157 if (BGE_IS_5700_FAMILY(sc)) {
2158 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
2159 rcb->bge_maxlen_flags =
2160 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
2161 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
2162 rcb->bge_maxlen_flags);
2163 /* Reset the mini receive producer ring producer index. */
2164 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
2167 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
2168 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2169 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
2170 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
2171 sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
2172 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
2173 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
2176 * The BD ring replenish thresholds control how often the
2177 * hardware fetches new BD's from the producer rings in host
2178 * memory. Setting the value too low on a busy system can
2179 * starve the hardware and recue the throughpout.
2181 * Set the BD ring replentish thresholds. The recommended
2182 * values are 1/8th the number of descriptors allocated to
2184 * XXX The 5754 requires a lower threshold, so it might be a
2185 * requirement of all 575x family chips. The Linux driver sets
2186 * the lower threshold for all 5705 family chips as well, but there
2187 * are reports that it might not need to be so strict.
2189 * XXX Linux does some extra fiddling here for the 5906 parts as
2192 if (BGE_IS_5705_PLUS(sc))
2195 val = BGE_STD_RX_RING_CNT / 8;
2196 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
2197 if (BGE_IS_JUMBO_CAPABLE(sc))
2198 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
2199 BGE_JUMBO_RX_RING_CNT/8);
2200 if (BGE_IS_5717_PLUS(sc)) {
2201 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
2202 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
2206 * Disable all send rings by setting the 'ring disabled' bit
2207 * in the flags field of all the TX send ring control blocks,
2208 * located in NIC memory.
2210 if (!BGE_IS_5705_PLUS(sc))
2211 /* 5700 to 5704 had 16 send rings. */
2212 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
2215 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2216 for (i = 0; i < limit; i++) {
2217 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2218 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
2219 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2220 vrcb += sizeof(struct bge_rcb);
2223 /* Configure send ring RCB 0 (we use only the first ring) */
2224 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2225 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
2226 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2227 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2228 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2229 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2230 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2231 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
2233 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
2234 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
2235 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2236 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
2239 * Disable all receive return rings by setting the
2240 * 'ring diabled' bit in the flags field of all the receive
2241 * return ring control blocks, located in NIC memory.
2243 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2244 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2245 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2246 /* Should be 17, use 16 until we get an SRAM map. */
2248 } else if (!BGE_IS_5705_PLUS(sc))
2249 limit = BGE_RX_RINGS_MAX;
2250 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2251 BGE_IS_57765_PLUS(sc))
2255 /* Disable all receive return rings. */
2256 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2257 for (i = 0; i < limit; i++) {
2258 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
2259 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
2260 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2261 BGE_RCB_FLAG_RING_DISABLED);
2262 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2263 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
2264 (i * (sizeof(uint64_t))), 0);
2265 vrcb += sizeof(struct bge_rcb);
2269 * Set up receive return ring 0. Note that the NIC address
2270 * for RX return rings is 0x0. The return rings live entirely
2271 * within the host, so the nicaddr field in the RCB isn't used.
2273 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2274 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
2275 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2276 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2277 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2278 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2279 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
2281 /* Set random backoff seed for TX */
2282 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
2283 (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
2284 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
2285 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) &
2286 BGE_TX_BACKOFF_SEED_MASK);
2288 /* Set inter-packet gap */
2290 if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
2291 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
2292 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
2293 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
2296 * Specify which ring to use for packets that don't match
2299 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
2302 * Configure number of RX lists. One interrupt distribution
2303 * list, sixteen active lists, one bad frames class.
2305 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
2307 /* Inialize RX list placement stats mask. */
2308 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
2309 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
2311 /* Disable host coalescing until we get it set up */
2312 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
2314 /* Poll to make sure it's shut down. */
2315 for (i = 0; i < BGE_TIMEOUT; i++) {
2317 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
2321 if (i == BGE_TIMEOUT) {
2322 device_printf(sc->bge_dev,
2323 "host coalescing engine failed to idle\n");
2327 /* Set up host coalescing defaults */
2328 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
2329 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
2330 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
2331 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
2332 if (!(BGE_IS_5705_PLUS(sc))) {
2333 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
2334 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
2336 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
2337 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
2339 /* Set up address of statistics block */
2340 if (!(BGE_IS_5705_PLUS(sc))) {
2341 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
2342 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
2343 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
2344 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
2345 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
2346 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
2347 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
2350 /* Set up address of status block */
2351 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
2352 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
2353 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
2354 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
2356 /* Set up status block size. */
2357 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2358 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
2359 val = BGE_STATBLKSZ_FULL;
2360 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2362 val = BGE_STATBLKSZ_32BYTE;
2363 bzero(sc->bge_ldata.bge_status_block, 32);
2365 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2366 sc->bge_cdata.bge_status_map,
2367 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2369 /* Turn on host coalescing state machine */
2370 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2372 /* Turn on RX BD completion state machine and enable attentions */
2373 CSR_WRITE_4(sc, BGE_RBDC_MODE,
2374 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
2376 /* Turn on RX list placement state machine */
2377 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2379 /* Turn on RX list selector state machine. */
2380 if (!(BGE_IS_5705_PLUS(sc)))
2381 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2383 /* Turn on DMA, clear stats. */
2384 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
2385 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
2386 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
2387 BGE_MACMODE_FRMHDR_DMA_ENB;
2389 if (sc->bge_flags & BGE_FLAG_TBI)
2390 val |= BGE_PORTMODE_TBI;
2391 else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
2392 val |= BGE_PORTMODE_GMII;
2394 val |= BGE_PORTMODE_MII;
2396 /* Allow APE to send/receive frames. */
2397 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
2398 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
2400 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
2403 /* Set misc. local control, enable interrupts on attentions */
2404 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2407 /* Assert GPIO pins for PHY reset */
2408 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
2409 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
2410 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
2411 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
2414 /* Turn on DMA completion state machine */
2415 if (!(BGE_IS_5705_PLUS(sc)))
2416 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2418 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
2420 /* Enable host coalescing bug fix. */
2421 if (BGE_IS_5755_PLUS(sc))
2422 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
2424 /* Request larger DMA burst size to get better performance. */
2425 if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
2426 val |= BGE_WDMAMODE_BURST_ALL_DATA;
2428 /* Turn on write DMA state machine */
2429 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
2432 /* Turn on read DMA state machine */
2433 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
2435 if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
2436 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
2438 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2439 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2440 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2441 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
2442 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
2443 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
2444 if (sc->bge_flags & BGE_FLAG_PCIE)
2445 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2446 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2447 val |= BGE_RDMAMODE_TSO4_ENABLE;
2448 if (sc->bge_flags & BGE_FLAG_TSO3 ||
2449 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2450 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2451 val |= BGE_RDMAMODE_TSO6_ENABLE;
2454 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2455 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
2456 BGE_RDMAMODE_H2BNC_VLAN_DET;
2458 * Allow multiple outstanding read requests from
2459 * non-LSO read DMA engine.
2461 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
2464 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2465 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2466 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2467 sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2468 BGE_IS_5717_PLUS(sc)) {
2469 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
2471 * Adjust tx margin to prevent TX data corruption and
2472 * fix internal FIFO overflow.
2474 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
2475 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
2476 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2477 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2478 BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2479 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2480 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2481 BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2484 * Enable fix for read DMA FIFO overruns.
2485 * The fix is to limit the number of RX BDs
2486 * the hardware would fetch at a fime.
2488 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl |
2489 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2492 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2493 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2494 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2495 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2496 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2497 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2499 * Allow 4KB burst length reads for non-LSO frames.
2500 * Enable 512B burst length reads for buffer descriptors.
2502 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2503 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2504 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
2505 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2508 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2511 /* Turn on RX data completion state machine */
2512 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2514 /* Turn on RX BD initiator state machine */
2515 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2517 /* Turn on RX data and RX BD initiator state machine */
2518 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2520 /* Turn on Mbuf cluster free state machine */
2521 if (!(BGE_IS_5705_PLUS(sc)))
2522 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2524 /* Turn on send BD completion state machine */
2525 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2527 /* Turn on send data completion state machine */
2528 val = BGE_SDCMODE_ENABLE;
2529 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2530 val |= BGE_SDCMODE_CDELAY;
2531 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2533 /* Turn on send data initiator state machine */
2534 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2535 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2536 BGE_SDIMODE_HW_LSO_PRE_DMA);
2538 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2540 /* Turn on send BD initiator state machine */
2541 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2543 /* Turn on send BD selector state machine */
2544 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2546 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
2547 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
2548 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
2550 /* ack/clear link change events */
2551 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2552 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2553 BGE_MACSTAT_LINK_CHANGED);
2554 CSR_WRITE_4(sc, BGE_MI_STS, 0);
2557 * Enable attention when the link has changed state for
2558 * devices that use auto polling.
2560 if (sc->bge_flags & BGE_FLAG_TBI) {
2561 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
2563 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2564 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
2567 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2568 sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
2569 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2570 BGE_EVTENB_MI_INTERRUPT);
2574 * Clear any pending link state attention.
2575 * Otherwise some link state change events may be lost until attention
2576 * is cleared by bge_intr() -> bge_link_upd() sequence.
2577 * It's not necessary on newer BCM chips - perhaps enabling link
2578 * state change attentions implies clearing pending attention.
2580 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2581 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2582 BGE_MACSTAT_LINK_CHANGED);
2584 /* Enable link state change attentions. */
2585 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2590 static const struct bge_revision *
2591 bge_lookup_rev(uint32_t chipid)
2593 const struct bge_revision *br;
2595 for (br = bge_revisions; br->br_name != NULL; br++) {
2596 if (br->br_chipid == chipid)
2600 for (br = bge_majorrevs; br->br_name != NULL; br++) {
2601 if (br->br_chipid == BGE_ASICREV(chipid))
2608 static const struct bge_vendor *
2609 bge_lookup_vendor(uint16_t vid)
2611 const struct bge_vendor *v;
2613 for (v = bge_vendors; v->v_name != NULL; v++)
2621 bge_chipid(device_t dev)
2625 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2626 BGE_PCIMISCCTL_ASICREV_SHIFT;
2627 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
2629 * Find the ASCI revision. Different chips use different
2632 switch (pci_get_device(dev)) {
2633 case BCOM_DEVICEID_BCM5717:
2634 case BCOM_DEVICEID_BCM5718:
2635 case BCOM_DEVICEID_BCM5719:
2636 case BCOM_DEVICEID_BCM5720:
2637 id = pci_read_config(dev,
2638 BGE_PCI_GEN2_PRODID_ASICREV, 4);
2640 case BCOM_DEVICEID_BCM57761:
2641 case BCOM_DEVICEID_BCM57762:
2642 case BCOM_DEVICEID_BCM57765:
2643 case BCOM_DEVICEID_BCM57766:
2644 case BCOM_DEVICEID_BCM57781:
2645 case BCOM_DEVICEID_BCM57785:
2646 case BCOM_DEVICEID_BCM57791:
2647 case BCOM_DEVICEID_BCM57795:
2648 id = pci_read_config(dev,
2649 BGE_PCI_GEN15_PRODID_ASICREV, 4);
2652 id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
2659 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
2660 * against our list and return its name if we find a match.
2662 * Note that since the Broadcom controller contains VPD support, we
2663 * try to get the device name string from the controller itself instead
2664 * of the compiled-in string. It guarantees we'll always announce the
2665 * right product name. We fall back to the compiled-in string when
2666 * VPD is unavailable or corrupt.
2669 bge_probe(device_t dev)
2673 const struct bge_revision *br;
2675 struct bge_softc *sc;
2676 const struct bge_type *t = bge_devs;
2677 const struct bge_vendor *v;
2681 sc = device_get_softc(dev);
2683 vid = pci_get_vendor(dev);
2684 did = pci_get_device(dev);
2685 while(t->bge_vid != 0) {
2686 if ((vid == t->bge_vid) && (did == t->bge_did)) {
2687 id = bge_chipid(dev);
2688 br = bge_lookup_rev(id);
2689 if (bge_has_eaddr(sc) &&
2690 pci_get_vpd_ident(dev, &pname) == 0)
2691 snprintf(model, sizeof(model), "%s", pname);
2693 v = bge_lookup_vendor(vid);
2694 snprintf(model, sizeof(model), "%s %s",
2695 v != NULL ? v->v_name : "Unknown",
2696 br != NULL ? br->br_name :
2697 "NetXtreme/NetLink Ethernet Controller");
2699 snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x",
2700 model, br != NULL ? "" : "unknown ", id);
2701 device_set_desc_copy(dev, buf);
2702 return (BUS_PROBE_DEFAULT);
2711 bge_dma_free(struct bge_softc *sc)
2715 /* Destroy DMA maps for RX buffers. */
2716 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2717 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2718 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2719 sc->bge_cdata.bge_rx_std_dmamap[i]);
2721 if (sc->bge_cdata.bge_rx_std_sparemap)
2722 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2723 sc->bge_cdata.bge_rx_std_sparemap);
2725 /* Destroy DMA maps for jumbo RX buffers. */
2726 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2727 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2728 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2729 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2731 if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2732 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2733 sc->bge_cdata.bge_rx_jumbo_sparemap);
2735 /* Destroy DMA maps for TX buffers. */
2736 for (i = 0; i < BGE_TX_RING_CNT; i++) {
2737 if (sc->bge_cdata.bge_tx_dmamap[i])
2738 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2739 sc->bge_cdata.bge_tx_dmamap[i]);
2742 if (sc->bge_cdata.bge_rx_mtag)
2743 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2744 if (sc->bge_cdata.bge_mtag_jumbo)
2745 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
2746 if (sc->bge_cdata.bge_tx_mtag)
2747 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2749 /* Destroy standard RX ring. */
2750 if (sc->bge_cdata.bge_rx_std_ring_map)
2751 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2752 sc->bge_cdata.bge_rx_std_ring_map);
2753 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
2754 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2755 sc->bge_ldata.bge_rx_std_ring,
2756 sc->bge_cdata.bge_rx_std_ring_map);
2758 if (sc->bge_cdata.bge_rx_std_ring_tag)
2759 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2761 /* Destroy jumbo RX ring. */
2762 if (sc->bge_cdata.bge_rx_jumbo_ring_map)
2763 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2764 sc->bge_cdata.bge_rx_jumbo_ring_map);
2766 if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
2767 sc->bge_ldata.bge_rx_jumbo_ring)
2768 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2769 sc->bge_ldata.bge_rx_jumbo_ring,
2770 sc->bge_cdata.bge_rx_jumbo_ring_map);
2772 if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2773 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2775 /* Destroy RX return ring. */
2776 if (sc->bge_cdata.bge_rx_return_ring_map)
2777 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2778 sc->bge_cdata.bge_rx_return_ring_map);
2780 if (sc->bge_cdata.bge_rx_return_ring_map &&
2781 sc->bge_ldata.bge_rx_return_ring)
2782 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2783 sc->bge_ldata.bge_rx_return_ring,
2784 sc->bge_cdata.bge_rx_return_ring_map);
2786 if (sc->bge_cdata.bge_rx_return_ring_tag)
2787 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2789 /* Destroy TX ring. */
2790 if (sc->bge_cdata.bge_tx_ring_map)
2791 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2792 sc->bge_cdata.bge_tx_ring_map);
2794 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
2795 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2796 sc->bge_ldata.bge_tx_ring,
2797 sc->bge_cdata.bge_tx_ring_map);
2799 if (sc->bge_cdata.bge_tx_ring_tag)
2800 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2802 /* Destroy status block. */
2803 if (sc->bge_cdata.bge_status_map)
2804 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2805 sc->bge_cdata.bge_status_map);
2807 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
2808 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2809 sc->bge_ldata.bge_status_block,
2810 sc->bge_cdata.bge_status_map);
2812 if (sc->bge_cdata.bge_status_tag)
2813 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2815 /* Destroy statistics block. */
2816 if (sc->bge_cdata.bge_stats_map)
2817 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2818 sc->bge_cdata.bge_stats_map);
2820 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2821 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2822 sc->bge_ldata.bge_stats,
2823 sc->bge_cdata.bge_stats_map);
2825 if (sc->bge_cdata.bge_stats_tag)
2826 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2828 if (sc->bge_cdata.bge_buffer_tag)
2829 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
2831 /* Destroy the parent tag. */
2832 if (sc->bge_cdata.bge_parent_tag)
2833 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2837 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
2838 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
2839 bus_addr_t *paddr, const char *msg)
2841 struct bge_dmamap_arg ctx;
2844 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2845 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2846 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
2848 device_printf(sc->bge_dev,
2849 "could not create %s dma tag\n", msg);
2852 /* Allocate DMA'able memory for ring. */
2853 error = bus_dmamem_alloc(*tag, (void **)ring,
2854 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
2856 device_printf(sc->bge_dev,
2857 "could not allocate DMA'able memory for %s\n", msg);
2860 /* Load the address of the ring. */
2861 ctx.bge_busaddr = 0;
2862 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr,
2863 &ctx, BUS_DMA_NOWAIT);
2865 device_printf(sc->bge_dev,
2866 "could not load DMA'able memory for %s\n", msg);
2869 *paddr = ctx.bge_busaddr;
2874 bge_dma_alloc(struct bge_softc *sc)
2877 bus_size_t rxmaxsegsz, sbsz, txsegsz, txmaxsegsz;
2880 lowaddr = BUS_SPACE_MAXADDR;
2881 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2882 lowaddr = BGE_DMA_MAXADDR;
2884 * Allocate the parent bus DMA tag appropriate for PCI.
2886 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2887 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2888 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2889 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2891 device_printf(sc->bge_dev,
2892 "could not allocate parent dma tag\n");
2896 /* Create tag for standard RX ring. */
2897 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
2898 &sc->bge_cdata.bge_rx_std_ring_tag,
2899 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
2900 &sc->bge_cdata.bge_rx_std_ring_map,
2901 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
2905 /* Create tag for RX return ring. */
2906 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
2907 &sc->bge_cdata.bge_rx_return_ring_tag,
2908 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
2909 &sc->bge_cdata.bge_rx_return_ring_map,
2910 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
2914 /* Create tag for TX ring. */
2915 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
2916 &sc->bge_cdata.bge_tx_ring_tag,
2917 (uint8_t **)&sc->bge_ldata.bge_tx_ring,
2918 &sc->bge_cdata.bge_tx_ring_map,
2919 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
2924 * Create tag for status block.
2925 * Because we only use single Tx/Rx/Rx return ring, use
2926 * minimum status block size except BCM5700 AX/BX which
2927 * seems to want to see full status block size regardless
2928 * of configured number of ring.
2930 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2931 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
2932 sbsz = BGE_STATUS_BLK_SZ;
2935 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
2936 &sc->bge_cdata.bge_status_tag,
2937 (uint8_t **)&sc->bge_ldata.bge_status_block,
2938 &sc->bge_cdata.bge_status_map,
2939 &sc->bge_ldata.bge_status_block_paddr, "status block");
2943 /* Create tag for statistics block. */
2944 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
2945 &sc->bge_cdata.bge_stats_tag,
2946 (uint8_t **)&sc->bge_ldata.bge_stats,
2947 &sc->bge_cdata.bge_stats_map,
2948 &sc->bge_ldata.bge_stats_paddr, "statistics block");
2952 /* Create tag for jumbo RX ring. */
2953 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2954 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
2955 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
2956 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
2957 &sc->bge_cdata.bge_rx_jumbo_ring_map,
2958 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
2963 /* Create parent tag for buffers. */
2964 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
2967 * watchdog timeout issue was observed on BCM5704 which
2968 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge).
2969 * Both limiting DMA address space to 32bits and flushing
2970 * mailbox write seem to address the issue.
2972 if (sc->bge_pcixcap != 0)
2973 lowaddr = BUS_SPACE_MAXADDR_32BIT;
2975 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 1, 0, lowaddr,
2976 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0,
2977 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
2978 &sc->bge_cdata.bge_buffer_tag);
2980 device_printf(sc->bge_dev,
2981 "could not allocate buffer dma tag\n");
2984 /* Create tag for Tx mbufs. */
2985 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2986 txsegsz = BGE_TSOSEG_SZ;
2987 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
2990 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
2992 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
2993 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2994 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
2995 &sc->bge_cdata.bge_tx_mtag);
2998 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
3002 /* Create tag for Rx mbufs. */
3003 if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
3004 rxmaxsegsz = MJUM9BYTES;
3006 rxmaxsegsz = MCLBYTES;
3007 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
3008 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1,
3009 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
3012 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
3016 /* Create DMA maps for RX buffers. */
3017 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3018 &sc->bge_cdata.bge_rx_std_sparemap);
3020 device_printf(sc->bge_dev,
3021 "can't create spare DMA map for RX\n");
3024 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3025 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3026 &sc->bge_cdata.bge_rx_std_dmamap[i]);
3028 device_printf(sc->bge_dev,
3029 "can't create DMA map for RX\n");
3034 /* Create DMA maps for TX buffers. */
3035 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3036 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
3037 &sc->bge_cdata.bge_tx_dmamap[i]);
3039 device_printf(sc->bge_dev,
3040 "can't create DMA map for TX\n");
3045 /* Create tags for jumbo RX buffers. */
3046 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3047 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
3048 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
3049 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
3050 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
3052 device_printf(sc->bge_dev,
3053 "could not allocate jumbo dma tag\n");
3056 /* Create DMA maps for jumbo RX buffers. */
3057 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3058 0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
3060 device_printf(sc->bge_dev,
3061 "can't create spare DMA map for jumbo RX\n");
3064 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
3065 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3066 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
3068 device_printf(sc->bge_dev,
3069 "can't create DMA map for jumbo RX\n");
3079 * Return true if this device has more than one port.
3082 bge_has_multiple_ports(struct bge_softc *sc)
3084 device_t dev = sc->bge_dev;
3085 u_int b, d, f, fscan, s;
3087 d = pci_get_domain(dev);
3088 b = pci_get_bus(dev);
3089 s = pci_get_slot(dev);
3090 f = pci_get_function(dev);
3091 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
3092 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
3098 * Return true if MSI can be used with this device.
3101 bge_can_use_msi(struct bge_softc *sc)
3103 int can_use_msi = 0;
3105 if (sc->bge_msi == 0)
3108 /* Disable MSI for polling(4). */
3109 #ifdef DEVICE_POLLING
3112 switch (sc->bge_asicrev) {
3113 case BGE_ASICREV_BCM5714_A0:
3114 case BGE_ASICREV_BCM5714:
3116 * Apparently, MSI doesn't work when these chips are
3117 * configured in single-port mode.
3119 if (bge_has_multiple_ports(sc))
3122 case BGE_ASICREV_BCM5750:
3123 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
3124 sc->bge_chiprev != BGE_CHIPREV_5750_BX)
3128 if (BGE_IS_575X_PLUS(sc))
3131 return (can_use_msi);
3135 bge_mbox_reorder(struct bge_softc *sc)
3137 /* Lists of PCI bridges that are known to reorder mailbox writes. */
3138 static const struct mbox_reorder {
3139 const uint16_t vendor;
3140 const uint16_t device;
3142 } mbox_reorder_lists[] = {
3143 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" },
3145 devclass_t pci, pcib;
3149 pci = devclass_find("pci");
3150 pcib = devclass_find("pcib");
3152 bus = device_get_parent(dev);
3154 dev = device_get_parent(bus);
3155 bus = device_get_parent(dev);
3156 if (device_get_devclass(dev) != pcib)
3158 for (i = 0; i < nitems(mbox_reorder_lists); i++) {
3159 if (pci_get_vendor(dev) ==
3160 mbox_reorder_lists[i].vendor &&
3161 pci_get_device(dev) ==
3162 mbox_reorder_lists[i].device) {
3163 device_printf(sc->bge_dev,
3164 "enabling MBOX workaround for %s\n",
3165 mbox_reorder_lists[i].desc);
3169 if (device_get_devclass(bus) != pci)
3176 bge_devinfo(struct bge_softc *sc)
3180 device_printf(sc->bge_dev,
3181 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ",
3182 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev);
3183 if (sc->bge_flags & BGE_FLAG_PCIE)
3185 else if (sc->bge_flags & BGE_FLAG_PCIX) {
3187 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3188 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE)
3191 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
3210 printf("%u MHz\n", clk);
3212 if (sc->bge_pcixcap != 0)
3213 printf("PCI on PCI-X ");
3216 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3217 if (cfg & BGE_PCISTATE_PCI_BUSSPEED)
3221 if (cfg & BGE_PCISTATE_32BIT_BUS)
3222 printf("%u MHz; 32bit\n", clk);
3224 printf("%u MHz; 64bit\n", clk);
3229 bge_attach(device_t dev)
3232 struct bge_softc *sc;
3233 uint32_t hwcfg = 0, misccfg, pcistate;
3234 u_char eaddr[ETHER_ADDR_LEN];
3235 int capmask, error, msicount, reg, rid, trys;
3237 sc = device_get_softc(dev);
3240 BGE_LOCK_INIT(sc, device_get_nameunit(dev));
3241 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
3242 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
3245 * Map control/status registers.
3247 pci_enable_busmaster(dev);
3250 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3253 if (sc->bge_res == NULL) {
3254 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n");
3259 /* Save various chip information. */
3260 sc->bge_func_addr = pci_get_function(dev);
3261 sc->bge_chipid = bge_chipid(dev);
3262 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
3263 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
3265 /* Set default PHY address. */
3266 sc->bge_phy_addr = 1;
3268 * PHY address mapping for various devices.
3270 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
3271 * ---------+-------+-------+-------+-------+
3272 * BCM57XX | 1 | X | X | X |
3273 * BCM5704 | 1 | X | 1 | X |
3274 * BCM5717 | 1 | 8 | 2 | 9 |
3275 * BCM5719 | 1 | 8 | 2 | 9 |
3276 * BCM5720 | 1 | 8 | 2 | 9 |
3278 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr |
3279 * ---------+-------+-------+-------+-------+
3280 * BCM57XX | X | X | X | X |
3281 * BCM5704 | X | X | X | X |
3282 * BCM5717 | X | X | X | X |
3283 * BCM5719 | 3 | 10 | 4 | 11 |
3284 * BCM5720 | X | X | X | X |
3286 * Other addresses may respond but they are not
3287 * IEEE compliant PHYs and should be ignored.
3289 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
3290 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3291 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3292 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) {
3293 if (CSR_READ_4(sc, BGE_SGDIG_STS) &
3294 BGE_SGDIGSTS_IS_SERDES)
3295 sc->bge_phy_addr = sc->bge_func_addr + 8;
3297 sc->bge_phy_addr = sc->bge_func_addr + 1;
3299 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
3300 BGE_CPMU_PHY_STRAP_IS_SERDES)
3301 sc->bge_phy_addr = sc->bge_func_addr + 8;
3303 sc->bge_phy_addr = sc->bge_func_addr + 1;
3307 if (bge_has_eaddr(sc))
3308 sc->bge_flags |= BGE_FLAG_EADDR;
3310 /* Save chipset family. */
3311 switch (sc->bge_asicrev) {
3312 case BGE_ASICREV_BCM57765:
3313 case BGE_ASICREV_BCM57766:
3314 sc->bge_flags |= BGE_FLAG_57765_PLUS;
3316 case BGE_ASICREV_BCM5717:
3317 case BGE_ASICREV_BCM5719:
3318 case BGE_ASICREV_BCM5720:
3319 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
3320 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
3321 BGE_FLAG_JUMBO_FRAME;
3322 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3323 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3324 /* Jumbo frame on BCM5719 A0 does not work. */
3325 sc->bge_flags &= ~BGE_FLAG_JUMBO;
3328 case BGE_ASICREV_BCM5755:
3329 case BGE_ASICREV_BCM5761:
3330 case BGE_ASICREV_BCM5784:
3331 case BGE_ASICREV_BCM5785:
3332 case BGE_ASICREV_BCM5787:
3333 case BGE_ASICREV_BCM57780:
3334 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
3337 case BGE_ASICREV_BCM5700:
3338 case BGE_ASICREV_BCM5701:
3339 case BGE_ASICREV_BCM5703:
3340 case BGE_ASICREV_BCM5704:
3341 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
3343 case BGE_ASICREV_BCM5714_A0:
3344 case BGE_ASICREV_BCM5780:
3345 case BGE_ASICREV_BCM5714:
3346 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
3348 case BGE_ASICREV_BCM5750:
3349 case BGE_ASICREV_BCM5752:
3350 case BGE_ASICREV_BCM5906:
3351 sc->bge_flags |= BGE_FLAG_575X_PLUS;
3353 case BGE_ASICREV_BCM5705:
3354 sc->bge_flags |= BGE_FLAG_5705_PLUS;
3358 /* Identify chips with APE processor. */
3359 switch (sc->bge_asicrev) {
3360 case BGE_ASICREV_BCM5717:
3361 case BGE_ASICREV_BCM5719:
3362 case BGE_ASICREV_BCM5720:
3363 case BGE_ASICREV_BCM5761:
3364 sc->bge_flags |= BGE_FLAG_APE;
3368 /* Chips with APE need BAR2 access for APE registers/memory. */
3369 if ((sc->bge_flags & BGE_FLAG_APE) != 0) {
3371 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3373 if (sc->bge_res2 == NULL) {
3374 device_printf (sc->bge_dev,
3375 "couldn't map BAR2 memory\n");
3380 /* Enable APE register/memory access by host driver. */
3381 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3382 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
3383 BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
3384 BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
3385 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4);
3387 bge_ape_lock_init(sc);
3388 bge_ape_read_fw_ver(sc);
3391 /* Add SYSCTLs, requires the chipset family to be set. */
3392 bge_add_sysctls(sc);
3394 /* Identify the chips that use an CPMU. */
3395 if (BGE_IS_5717_PLUS(sc) ||
3396 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3397 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3398 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
3399 sc->bge_asicrev == BGE_ASICREV_BCM57780)
3400 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
3401 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
3402 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
3404 sc->bge_mi_mode = BGE_MIMODE_BASE;
3405 /* Enable auto polling for BCM570[0-5]. */
3406 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
3407 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
3410 * All Broadcom controllers have 4GB boundary DMA bug.
3411 * Whenever an address crosses a multiple of the 4GB boundary
3412 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3413 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3414 * state machine will lockup and cause the device to hang.
3416 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
3418 /* BCM5755 or higher and BCM5906 have short DMA bug. */
3419 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3420 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
3423 * BCM5719 cannot handle DMA requests for DMA segments that
3424 * have larger than 4KB in size. However the maximum DMA
3425 * segment size created in DMA tag is 4KB for TSO, so we
3426 * wouldn't encounter the issue here.
3428 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
3429 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG;
3431 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3432 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
3433 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
3434 misccfg == BGE_MISCCFG_BOARD_ID_5788M)
3435 sc->bge_flags |= BGE_FLAG_5788;
3438 capmask = BMSR_DEFCAPMASK;
3439 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
3440 (misccfg == 0x4000 || misccfg == 0x8000)) ||
3441 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3442 pci_get_vendor(dev) == BCOM_VENDORID &&
3443 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 ||
3444 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 ||
3445 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) ||
3446 (pci_get_vendor(dev) == BCOM_VENDORID &&
3447 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F ||
3448 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F ||
3449 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) ||
3450 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 ||
3451 pci_get_device(dev) == BCOM_DEVICEID_BCM57791 ||
3452 pci_get_device(dev) == BCOM_DEVICEID_BCM57795 ||
3453 sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3454 /* These chips are 10/100 only. */
3455 capmask &= ~BMSR_EXTSTAT;
3456 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3460 * Some controllers seem to require a special firmware to use
3461 * TSO. But the firmware is not available to FreeBSD and Linux
3462 * claims that the TSO performed by the firmware is slower than
3463 * hardware based TSO. Moreover the firmware based TSO has one
3464 * known bug which can't handle TSO if Ethernet header + IP/TCP
3465 * header is greater than 80 bytes. A workaround for the TSO
3466 * bug exist but it seems it's too expensive than not using
3467 * TSO at all. Some hardwares also have the TSO bug so limit
3468 * the TSO to the controllers that are not affected TSO issues
3469 * (e.g. 5755 or higher).
3471 if (BGE_IS_5717_PLUS(sc)) {
3472 /* BCM5717 requires different TSO configuration. */
3473 sc->bge_flags |= BGE_FLAG_TSO3;
3474 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3475 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3476 /* TSO on BCM5719 A0 does not work. */
3477 sc->bge_flags &= ~BGE_FLAG_TSO3;
3479 } else if (BGE_IS_5755_PLUS(sc)) {
3481 * BCM5754 and BCM5787 shares the same ASIC id so
3482 * explicit device id check is required.
3483 * Due to unknown reason TSO does not work on BCM5755M.
3485 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
3486 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
3487 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
3488 sc->bge_flags |= BGE_FLAG_TSO;
3492 * Check if this is a PCI-X or PCI Express device.
3494 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
3496 * Found a PCI Express capabilities register, this
3497 * must be a PCI Express device.
3499 sc->bge_flags |= BGE_FLAG_PCIE;
3500 sc->bge_expcap = reg;
3501 /* Extract supported maximum payload size. */
3502 sc->bge_mps = pci_read_config(dev, sc->bge_expcap +
3503 PCIER_DEVICE_CAP, 2);
3504 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD);
3505 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3506 sc->bge_asicrev == BGE_ASICREV_BCM5720)
3507 sc->bge_expmrq = 2048;
3509 sc->bge_expmrq = 4096;
3510 pci_set_max_read_req(dev, sc->bge_expmrq);
3513 * Check if the device is in PCI-X Mode.
3514 * (This bit is not valid on PCI Express controllers.)
3516 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0)
3517 sc->bge_pcixcap = reg;
3518 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
3519 BGE_PCISTATE_PCI_BUSMODE) == 0)
3520 sc->bge_flags |= BGE_FLAG_PCIX;
3524 * The 40bit DMA bug applies to the 5714/5715 controllers and is
3525 * not actually a MAC controller bug but an issue with the embedded
3526 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
3528 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
3529 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
3531 * Some PCI-X bridges are known to trigger write reordering to
3532 * the mailbox registers. Typical phenomena is watchdog timeouts
3533 * caused by out-of-order TX completions. Enable workaround for
3534 * PCI-X devices that live behind these bridges.
3535 * Note, PCI-X controllers can run in PCI mode so we can't use
3536 * BGE_FLAG_PCIX flag to detect PCI-X controllers.
3538 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0)
3539 sc->bge_flags |= BGE_FLAG_MBOX_REORDER;
3541 * Allocate the interrupt, using MSI if possible. These devices
3542 * support 8 MSI messages, but only the first one is used in
3546 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) {
3547 sc->bge_msicap = reg;
3548 if (bge_can_use_msi(sc)) {
3549 msicount = pci_msi_count(dev);
3554 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
3556 sc->bge_flags |= BGE_FLAG_MSI;
3561 * All controllers except BCM5700 supports tagged status but
3562 * we use tagged status only for MSI case on BCM5717. Otherwise
3563 * MSI on BCM5717 does not work.
3565 #ifndef DEVICE_POLLING
3566 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
3567 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
3570 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3571 RF_SHAREABLE | RF_ACTIVE);
3573 if (sc->bge_irq == NULL) {
3574 device_printf(sc->bge_dev, "couldn't map interrupt\n");
3581 sc->bge_asf_mode = 0;
3582 /* No ASF if APE present. */
3583 if ((sc->bge_flags & BGE_FLAG_APE) == 0) {
3584 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3585 BGE_SRAM_DATA_SIG_MAGIC)) {
3586 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
3588 sc->bge_asf_mode |= ASF_ENABLE;
3589 sc->bge_asf_mode |= ASF_STACKUP;
3590 if (BGE_IS_575X_PLUS(sc))
3591 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3597 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
3598 if (bge_reset(sc)) {
3599 device_printf(sc->bge_dev, "chip reset failed\n");
3604 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
3605 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
3607 if (bge_chipinit(sc)) {
3608 device_printf(sc->bge_dev, "chip initialization failed\n");
3613 error = bge_get_eaddr(sc, eaddr);
3615 device_printf(sc->bge_dev,
3616 "failed to read station address\n");
3621 /* 5705 limits RX return ring to 512 entries. */
3622 if (BGE_IS_5717_PLUS(sc))
3623 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3624 else if (BGE_IS_5705_PLUS(sc))
3625 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3627 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3629 if (bge_dma_alloc(sc)) {
3630 device_printf(sc->bge_dev,
3631 "failed to allocate DMA resources\n");
3636 /* Set default tuneable values. */
3637 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3638 sc->bge_rx_coal_ticks = 150;
3639 sc->bge_tx_coal_ticks = 150;
3640 sc->bge_rx_max_coal_bds = 10;
3641 sc->bge_tx_max_coal_bds = 10;
3643 /* Initialize checksum features to use. */
3644 sc->bge_csum_features = BGE_CSUM_FEATURES;
3645 if (sc->bge_forced_udpcsum != 0)
3646 sc->bge_csum_features |= CSUM_UDP;
3648 /* Set up ifnet structure */
3649 ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
3651 device_printf(sc->bge_dev, "failed to if_alloc()\n");
3656 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3657 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3658 ifp->if_ioctl = bge_ioctl;
3659 ifp->if_start = bge_start;
3660 ifp->if_init = bge_init;
3661 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
3662 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
3663 IFQ_SET_READY(&ifp->if_snd);
3664 ifp->if_hwassist = sc->bge_csum_features;
3665 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3667 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3668 ifp->if_hwassist |= CSUM_TSO;
3669 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO;
3671 #ifdef IFCAP_VLAN_HWCSUM
3672 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
3674 ifp->if_capenable = ifp->if_capabilities;
3675 #ifdef DEVICE_POLLING
3676 ifp->if_capabilities |= IFCAP_POLLING;
3680 * 5700 B0 chips do not support checksumming correctly due
3683 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
3684 ifp->if_capabilities &= ~IFCAP_HWCSUM;
3685 ifp->if_capenable &= ~IFCAP_HWCSUM;
3686 ifp->if_hwassist = 0;
3690 * Figure out what sort of media we have by checking the
3691 * hardware config word in the first 32k of NIC internal memory,
3692 * or fall back to examining the EEPROM if necessary.
3693 * Note: on some BCM5700 cards, this value appears to be unset.
3694 * If that's the case, we have to rely on identifying the NIC
3695 * by its PCI subsystem ID, as we do below for the SysKonnect
3698 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
3699 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3700 else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
3701 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3702 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
3704 device_printf(sc->bge_dev, "failed to read EEPROM\n");
3708 hwcfg = ntohl(hwcfg);
3711 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
3712 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
3713 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
3714 if (BGE_IS_5705_PLUS(sc)) {
3715 sc->bge_flags |= BGE_FLAG_MII_SERDES;
3716 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3718 sc->bge_flags |= BGE_FLAG_TBI;
3721 /* Set various PHY bug flags. */
3722 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
3723 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
3724 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
3725 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
3726 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
3727 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
3728 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
3729 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
3730 if (pci_get_subvendor(dev) == DELL_VENDORID)
3731 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
3732 if ((BGE_IS_5705_PLUS(sc)) &&
3733 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
3734 sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
3735 sc->bge_asicrev != BGE_ASICREV_BCM57780 &&
3736 !BGE_IS_5717_PLUS(sc)) {
3737 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
3738 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3739 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3740 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
3741 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
3742 pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
3743 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
3744 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
3745 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
3747 sc->bge_phy_flags |= BGE_PHY_BER_BUG;
3751 * Don't enable Ethernet@WireSpeed for the 5700 or the
3752 * 5705 A0 and A1 chips.
3754 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3755 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3756 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
3757 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)))
3758 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3760 if (sc->bge_flags & BGE_FLAG_TBI) {
3761 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3763 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
3764 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
3766 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3767 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3768 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3771 * Do transceiver setup and tell the firmware the
3772 * driver is down so we can try to get access the
3773 * probe if ASF is running. Retry a couple of times
3774 * if we get a conflict with the ASF firmware accessing
3778 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3780 bge_asf_driver_up(sc);
3782 error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd,
3783 bge_ifmedia_sts, capmask, sc->bge_phy_addr, MII_OFFSET_ANY,
3787 device_printf(sc->bge_dev, "Try again\n");
3788 bge_miibus_writereg(sc->bge_dev,
3789 sc->bge_phy_addr, MII_BMCR, BMCR_RESET);
3792 device_printf(sc->bge_dev, "attaching PHYs failed\n");
3797 * Now tell the firmware we are going up after probing the PHY
3799 if (sc->bge_asf_mode & ASF_STACKUP)
3800 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3804 * When using the BCM5701 in PCI-X mode, data corruption has
3805 * been observed in the first few bytes of some received packets.
3806 * Aligning the packet buffer in memory eliminates the corruption.
3807 * Unfortunately, this misaligns the packet payloads. On platforms
3808 * which do not support unaligned accesses, we will realign the
3809 * payloads by copying the received packets.
3811 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
3812 sc->bge_flags & BGE_FLAG_PCIX)
3813 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
3816 * Call MI attach routine.
3818 ether_ifattach(ifp, eaddr);
3820 /* Tell upper layer we support long frames. */
3821 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
3826 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
3827 /* Take advantage of single-shot MSI. */
3828 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
3829 ~BGE_MSIMODE_ONE_SHOT_DISABLE);
3830 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
3831 taskqueue_thread_enqueue, &sc->bge_tq);
3832 if (sc->bge_tq == NULL) {
3833 device_printf(dev, "could not create taskqueue.\n");
3834 ether_ifdetach(ifp);
3838 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET,
3839 "%s taskq", device_get_nameunit(sc->bge_dev));
3841 device_printf(dev, "could not start threads.\n");
3842 ether_ifdetach(ifp);
3845 error = bus_setup_intr(dev, sc->bge_irq,
3846 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
3849 error = bus_setup_intr(dev, sc->bge_irq,
3850 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
3854 ether_ifdetach(ifp);
3855 device_printf(sc->bge_dev, "couldn't set up irq\n");
3865 bge_detach(device_t dev)
3867 struct bge_softc *sc;
3870 sc = device_get_softc(dev);
3873 #ifdef DEVICE_POLLING
3874 if (ifp->if_capenable & IFCAP_POLLING)
3875 ether_poll_deregister(ifp);
3878 if (device_is_attached(dev)) {
3879 ether_ifdetach(ifp);
3883 callout_drain(&sc->bge_stat_ch);
3887 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3889 if (sc->bge_flags & BGE_FLAG_TBI)
3890 ifmedia_removeall(&sc->bge_ifmedia);
3891 else if (sc->bge_miibus != NULL) {
3892 bus_generic_detach(dev);
3893 device_delete_child(dev, sc->bge_miibus);
3896 bge_release_resources(sc);
3902 bge_release_resources(struct bge_softc *sc)
3908 if (sc->bge_tq != NULL)
3909 taskqueue_free(sc->bge_tq);
3911 if (sc->bge_intrhand != NULL)
3912 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3914 if (sc->bge_irq != NULL)
3915 bus_release_resource(dev, SYS_RES_IRQ,
3916 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
3918 if (sc->bge_flags & BGE_FLAG_MSI)
3919 pci_release_msi(dev);
3921 if (sc->bge_res != NULL)
3922 bus_release_resource(dev, SYS_RES_MEMORY,
3923 PCIR_BAR(0), sc->bge_res);
3925 if (sc->bge_res2 != NULL)
3926 bus_release_resource(dev, SYS_RES_MEMORY,
3927 PCIR_BAR(2), sc->bge_res2);
3929 if (sc->bge_ifp != NULL)
3930 if_free(sc->bge_ifp);
3934 if (mtx_initialized(&sc->bge_mtx)) /* XXX */
3935 BGE_LOCK_DESTROY(sc);
3939 bge_reset(struct bge_softc *sc)
3942 uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val;
3943 void (*write_op)(struct bge_softc *, int, int);
3949 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
3950 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
3951 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
3952 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
3954 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
3955 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3956 if (sc->bge_flags & BGE_FLAG_PCIE)
3957 write_op = bge_writemem_direct;
3959 write_op = bge_writemem_ind;
3961 write_op = bge_writereg_ind;
3963 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
3964 sc->bge_asicrev != BGE_ASICREV_BCM5701) {
3965 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
3966 for (i = 0; i < 8000; i++) {
3967 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
3968 BGE_NVRAMSWARB_GNT1)
3974 device_printf(dev, "NVRAM lock timedout!\n");
3977 /* Take APE lock when performing reset. */
3978 bge_ape_lock(sc, BGE_APE_LOCK_GRC);
3980 /* Save some important PCI state. */
3981 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
3982 command = pci_read_config(dev, BGE_PCI_CMD, 4);
3984 pci_write_config(dev, BGE_PCI_MISC_CTL,
3985 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3986 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3988 /* Disable fastboot on controllers that support it. */
3989 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
3990 BGE_IS_5755_PLUS(sc)) {
3992 device_printf(dev, "Disabling fastboot\n");
3993 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
3997 * Write the magic number to SRAM at offset 0xB50.
3998 * When firmware finishes its initialization it will
3999 * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
4001 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
4003 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
4005 /* XXX: Broadcom Linux driver. */
4006 if (sc->bge_flags & BGE_FLAG_PCIE) {
4007 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
4008 (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) {
4009 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */
4010 CSR_WRITE_4(sc, 0x7E2C, 0x20);
4012 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
4013 /* Prevent PCIE link training during global reset */
4014 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
4019 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4020 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4021 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
4022 val | BGE_VCPU_STATUS_DRV_RESET);
4023 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
4024 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
4025 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
4029 * Set GPHY Power Down Override to leave GPHY
4030 * powered up in D0 uninitialized.
4032 if (BGE_IS_5705_PLUS(sc) &&
4033 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0)
4034 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
4036 /* Issue global reset */
4037 write_op(sc, BGE_MISC_CFG, reset);
4039 if (sc->bge_flags & BGE_FLAG_PCIE)
4044 /* XXX: Broadcom Linux driver. */
4045 if (sc->bge_flags & BGE_FLAG_PCIE) {
4046 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
4047 DELAY(500000); /* wait for link training to complete */
4048 val = pci_read_config(dev, 0xC4, 4);
4049 pci_write_config(dev, 0xC4, val | (1 << 15), 4);
4051 devctl = pci_read_config(dev,
4052 sc->bge_expcap + PCIER_DEVICE_CTL, 2);
4053 /* Clear enable no snoop and disable relaxed ordering. */
4054 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE |
4055 PCIEM_CTL_NOSNOOP_ENABLE);
4056 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL,
4058 pci_set_max_read_req(dev, sc->bge_expmrq);
4059 /* Clear error status. */
4060 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA,
4061 PCIEM_STA_CORRECTABLE_ERROR |
4062 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
4063 PCIEM_STA_UNSUPPORTED_REQ, 2);
4066 /* Reset some of the PCI state that got zapped by reset. */
4067 pci_write_config(dev, BGE_PCI_MISC_CTL,
4068 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4069 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4070 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
4071 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
4072 (sc->bge_flags & BGE_FLAG_PCIX) != 0)
4073 val |= BGE_PCISTATE_RETRY_SAME_DMA;
4074 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4075 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
4076 BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
4077 BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
4078 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4);
4079 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
4080 pci_write_config(dev, BGE_PCI_CMD, command, 4);
4082 * Disable PCI-X relaxed ordering to ensure status block update
4083 * comes first then packet buffer DMA. Otherwise driver may
4084 * read stale status block.
4086 if (sc->bge_flags & BGE_FLAG_PCIX) {
4087 devctl = pci_read_config(dev,
4088 sc->bge_pcixcap + PCIXR_COMMAND, 2);
4089 devctl &= ~PCIXM_COMMAND_ERO;
4090 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
4091 devctl &= ~PCIXM_COMMAND_MAX_READ;
4092 devctl |= PCIXM_COMMAND_MAX_READ_2048;
4093 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4094 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
4095 PCIXM_COMMAND_MAX_READ);
4096 devctl |= PCIXM_COMMAND_MAX_READ_2048;
4098 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
4101 /* Re-enable MSI, if necessary, and enable the memory arbiter. */
4102 if (BGE_IS_5714_FAMILY(sc)) {
4103 /* This chip disables MSI on reset. */
4104 if (sc->bge_flags & BGE_FLAG_MSI) {
4105 val = pci_read_config(dev,
4106 sc->bge_msicap + PCIR_MSI_CTRL, 2);
4107 pci_write_config(dev,
4108 sc->bge_msicap + PCIR_MSI_CTRL,
4109 val | PCIM_MSICTRL_MSI_ENABLE, 2);
4110 val = CSR_READ_4(sc, BGE_MSI_MODE);
4111 CSR_WRITE_4(sc, BGE_MSI_MODE,
4112 val | BGE_MSIMODE_ENABLE);
4114 val = CSR_READ_4(sc, BGE_MARB_MODE);
4115 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
4117 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4119 /* Fix up byte swapping. */
4120 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
4122 val = CSR_READ_4(sc, BGE_MAC_MODE);
4123 val = (val & ~mac_mode_mask) | mac_mode;
4124 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
4127 bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
4129 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4130 for (i = 0; i < BGE_TIMEOUT; i++) {
4131 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4132 if (val & BGE_VCPU_STATUS_INIT_DONE)
4136 if (i == BGE_TIMEOUT) {
4137 device_printf(dev, "reset timed out\n");
4142 * Poll until we see the 1's complement of the magic number.
4143 * This indicates that the firmware initialization is complete.
4144 * We expect this to fail if no chip containing the Ethernet
4145 * address is fitted though.
4147 for (i = 0; i < BGE_TIMEOUT; i++) {
4149 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
4150 if (val == ~BGE_SRAM_FW_MB_MAGIC)
4154 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
4156 "firmware handshake timed out, found 0x%08x\n",
4158 /* BCM57765 A0 needs additional time before accessing. */
4159 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
4160 DELAY(10 * 1000); /* XXX */
4164 * The 5704 in TBI mode apparently needs some special
4165 * adjustment to insure the SERDES drive level is set
4168 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
4169 sc->bge_flags & BGE_FLAG_TBI) {
4170 val = CSR_READ_4(sc, BGE_SERDES_CFG);
4171 val = (val & ~0xFFF) | 0x880;
4172 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
4175 /* XXX: Broadcom Linux driver. */
4176 if (sc->bge_flags & BGE_FLAG_PCIE &&
4177 !BGE_IS_5717_PLUS(sc) &&
4178 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
4179 sc->bge_asicrev != BGE_ASICREV_BCM5785) {
4180 /* Enable Data FIFO protection. */
4181 val = CSR_READ_4(sc, 0x7C00);
4182 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
4185 if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
4186 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
4187 CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
4192 static __inline void
4193 bge_rxreuse_std(struct bge_softc *sc, int i)
4195 struct bge_rx_bd *r;
4197 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
4198 r->bge_flags = BGE_RXBDFLAG_END;
4199 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
4201 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4204 static __inline void
4205 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
4207 struct bge_extrx_bd *r;
4209 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
4210 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
4211 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
4212 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
4213 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
4214 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
4216 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4220 * Frame reception handling. This is called if there's a frame
4221 * on the receive return list.
4223 * Note: we have to be able to handle two possibilities here:
4224 * 1) the frame is from the jumbo receive ring
4225 * 2) the frame is from the standard receive ring
4229 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
4232 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
4235 rx_cons = sc->bge_rx_saved_considx;
4237 /* Nothing to do. */
4238 if (rx_cons == rx_prod)
4243 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4244 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
4245 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4246 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
4247 if (BGE_IS_JUMBO_CAPABLE(sc) &&
4248 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
4249 (MCLBYTES - ETHER_ALIGN))
4250 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4251 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
4253 while (rx_cons != rx_prod) {
4254 struct bge_rx_bd *cur_rx;
4256 struct mbuf *m = NULL;
4257 uint16_t vlan_tag = 0;
4260 #ifdef DEVICE_POLLING
4261 if (ifp->if_capenable & IFCAP_POLLING) {
4262 if (sc->rxcycles <= 0)
4268 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
4270 rxidx = cur_rx->bge_idx;
4271 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
4273 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
4274 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
4276 vlan_tag = cur_rx->bge_vlan_tag;
4279 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
4281 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
4282 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4283 bge_rxreuse_jumbo(sc, rxidx);
4286 if (bge_newbuf_jumbo(sc, rxidx) != 0) {
4287 bge_rxreuse_jumbo(sc, rxidx);
4291 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4294 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
4295 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4296 bge_rxreuse_std(sc, rxidx);
4299 if (bge_newbuf_std(sc, rxidx) != 0) {
4300 bge_rxreuse_std(sc, rxidx);
4304 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4308 #ifndef __NO_STRICT_ALIGNMENT
4310 * For architectures with strict alignment we must make sure
4311 * the payload is aligned.
4313 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
4314 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
4316 m->m_data += ETHER_ALIGN;
4319 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
4320 m->m_pkthdr.rcvif = ifp;
4322 if (ifp->if_capenable & IFCAP_RXCSUM)
4323 bge_rxcsum(sc, cur_rx, m);
4326 * If we received a packet with a vlan tag,
4327 * attach that information to the packet.
4330 m->m_pkthdr.ether_vtag = vlan_tag;
4331 m->m_flags |= M_VLANTAG;
4336 (*ifp->if_input)(ifp, m);
4339 (*ifp->if_input)(ifp, m);
4342 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
4346 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4347 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
4349 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4350 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
4353 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4354 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
4356 sc->bge_rx_saved_considx = rx_cons;
4357 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
4359 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
4360 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT);
4362 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
4363 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT);
4366 * This register wraps very quickly under heavy packet drops.
4367 * If you need correct statistics, you can enable this check.
4369 if (BGE_IS_5705_PLUS(sc))
4370 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4376 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
4379 if (BGE_IS_5717_PLUS(sc)) {
4380 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
4381 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4382 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4383 if ((cur_rx->bge_error_flag &
4384 BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
4385 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4387 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
4388 m->m_pkthdr.csum_data =
4389 cur_rx->bge_tcp_udp_csum;
4390 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4395 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4396 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4397 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
4398 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4400 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
4401 m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
4402 m->m_pkthdr.csum_data =
4403 cur_rx->bge_tcp_udp_csum;
4404 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4411 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
4413 struct bge_tx_bd *cur_tx;
4416 BGE_LOCK_ASSERT(sc);
4418 /* Nothing to do. */
4419 if (sc->bge_tx_saved_considx == tx_cons)
4424 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4425 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
4427 * Go through our tx ring and free mbufs for those
4428 * frames that have been sent.
4430 while (sc->bge_tx_saved_considx != tx_cons) {
4433 idx = sc->bge_tx_saved_considx;
4434 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
4435 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
4437 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
4438 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
4439 sc->bge_cdata.bge_tx_dmamap[idx],
4440 BUS_DMASYNC_POSTWRITE);
4441 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
4442 sc->bge_cdata.bge_tx_dmamap[idx]);
4443 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
4444 sc->bge_cdata.bge_tx_chain[idx] = NULL;
4447 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
4450 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4451 if (sc->bge_txcnt == 0)
4455 #ifdef DEVICE_POLLING
4457 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
4459 struct bge_softc *sc = ifp->if_softc;
4460 uint16_t rx_prod, tx_cons;
4461 uint32_t statusword;
4465 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4470 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4471 sc->bge_cdata.bge_status_map,
4472 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4473 /* Fetch updates from the status block. */
4474 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4475 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4477 statusword = sc->bge_ldata.bge_status_block->bge_status;
4478 /* Clear the status so the next pass only sees the changes. */
4479 sc->bge_ldata.bge_status_block->bge_status = 0;
4481 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4482 sc->bge_cdata.bge_status_map,
4483 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4485 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
4486 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
4489 if (cmd == POLL_AND_CHECK_STATUS)
4490 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4491 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4492 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
4495 sc->rxcycles = count;
4496 rx_npkts = bge_rxeof(sc, rx_prod, 1);
4497 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4501 bge_txeof(sc, tx_cons);
4502 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4503 bge_start_locked(ifp);
4508 #endif /* DEVICE_POLLING */
4511 bge_msi_intr(void *arg)
4513 struct bge_softc *sc;
4515 sc = (struct bge_softc *)arg;
4517 * This interrupt is not shared and controller already
4518 * disabled further interrupt.
4520 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
4521 return (FILTER_HANDLED);
4525 bge_intr_task(void *arg, int pending)
4527 struct bge_softc *sc;
4529 uint32_t status, status_tag;
4530 uint16_t rx_prod, tx_cons;
4532 sc = (struct bge_softc *)arg;
4536 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
4541 /* Get updated status block. */
4542 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4543 sc->bge_cdata.bge_status_map,
4544 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4546 /* Save producer/consumer indices. */
4547 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4548 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4549 status = sc->bge_ldata.bge_status_block->bge_status;
4550 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
4551 /* Dirty the status flag. */
4552 sc->bge_ldata.bge_status_block->bge_status = 0;
4553 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4554 sc->bge_cdata.bge_status_map,
4555 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4556 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
4559 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
4562 /* Let controller work. */
4563 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
4565 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
4566 sc->bge_rx_saved_considx != rx_prod) {
4567 /* Check RX return ring producer/consumer. */
4569 bge_rxeof(sc, rx_prod, 0);
4572 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4573 /* Check TX ring producer/consumer. */
4574 bge_txeof(sc, tx_cons);
4575 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4576 bge_start_locked(ifp);
4584 struct bge_softc *sc;
4586 uint32_t statusword;
4587 uint16_t rx_prod, tx_cons;
4595 #ifdef DEVICE_POLLING
4596 if (ifp->if_capenable & IFCAP_POLLING) {
4603 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
4604 * disable interrupts by writing nonzero like we used to, since with
4605 * our current organization this just gives complications and
4606 * pessimizations for re-enabling interrupts. We used to have races
4607 * instead of the necessary complications. Disabling interrupts
4608 * would just reduce the chance of a status update while we are
4609 * running (by switching to the interrupt-mode coalescence
4610 * parameters), but this chance is already very low so it is more
4611 * efficient to get another interrupt than prevent it.
4613 * We do the ack first to ensure another interrupt if there is a
4614 * status update after the ack. We don't check for the status
4615 * changing later because it is more efficient to get another
4616 * interrupt than prevent it, not quite as above (not checking is
4617 * a smaller optimization than not toggling the interrupt enable,
4618 * since checking doesn't involve PCI accesses and toggling require
4619 * the status check). So toggling would probably be a pessimization
4620 * even with MSI. It would only be needed for using a task queue.
4622 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4625 * Do the mandatory PCI flush as well as get the link status.
4627 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
4629 /* Make sure the descriptor ring indexes are coherent. */
4630 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4631 sc->bge_cdata.bge_status_map,
4632 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4633 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4634 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4635 sc->bge_ldata.bge_status_block->bge_status = 0;
4636 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4637 sc->bge_cdata.bge_status_map,
4638 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4640 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4641 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4642 statusword || sc->bge_link_evt)
4645 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4646 /* Check RX return ring producer/consumer. */
4647 bge_rxeof(sc, rx_prod, 1);
4650 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4651 /* Check TX ring producer/consumer. */
4652 bge_txeof(sc, tx_cons);
4655 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
4656 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4657 bge_start_locked(ifp);
4663 bge_asf_driver_up(struct bge_softc *sc)
4665 if (sc->bge_asf_mode & ASF_STACKUP) {
4666 /* Send ASF heartbeat aprox. every 2s */
4667 if (sc->bge_asf_count)
4668 sc->bge_asf_count --;
4670 sc->bge_asf_count = 2;
4671 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4672 BGE_FW_CMD_DRV_ALIVE);
4673 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4674 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
4675 BGE_FW_HB_TIMEOUT_SEC);
4676 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
4677 CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4678 BGE_RX_CPU_DRV_EVENT);
4686 struct bge_softc *sc = xsc;
4687 struct mii_data *mii = NULL;
4689 BGE_LOCK_ASSERT(sc);
4691 /* Synchronize with possible callout reset/stop. */
4692 if (callout_pending(&sc->bge_stat_ch) ||
4693 !callout_active(&sc->bge_stat_ch))
4696 if (BGE_IS_5705_PLUS(sc))
4697 bge_stats_update_regs(sc);
4699 bge_stats_update(sc);
4701 /* XXX Add APE heartbeat check here? */
4703 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4704 mii = device_get_softc(sc->bge_miibus);
4706 * Do not touch PHY if we have link up. This could break
4707 * IPMI/ASF mode or produce extra input errors
4708 * (extra errors was reported for bcm5701 & bcm5704).
4714 * Since in TBI mode auto-polling can't be used we should poll
4715 * link status manually. Here we register pending link event
4716 * and trigger interrupt.
4718 #ifdef DEVICE_POLLING
4719 /* In polling mode we poll link state in bge_poll(). */
4720 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
4724 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4725 sc->bge_flags & BGE_FLAG_5788)
4726 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4728 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4732 bge_asf_driver_up(sc);
4735 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4739 bge_stats_update_regs(struct bge_softc *sc)
4742 struct bge_mac_stats *stats;
4745 stats = &sc->bge_mac_stats;
4747 stats->ifHCOutOctets +=
4748 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4749 stats->etherStatsCollisions +=
4750 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4751 stats->outXonSent +=
4752 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4753 stats->outXoffSent +=
4754 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4755 stats->dot3StatsInternalMacTransmitErrors +=
4756 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4757 stats->dot3StatsSingleCollisionFrames +=
4758 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4759 stats->dot3StatsMultipleCollisionFrames +=
4760 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4761 stats->dot3StatsDeferredTransmissions +=
4762 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4763 stats->dot3StatsExcessiveCollisions +=
4764 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4765 stats->dot3StatsLateCollisions +=
4766 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4767 stats->ifHCOutUcastPkts +=
4768 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4769 stats->ifHCOutMulticastPkts +=
4770 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4771 stats->ifHCOutBroadcastPkts +=
4772 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4774 stats->ifHCInOctets +=
4775 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4776 stats->etherStatsFragments +=
4777 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4778 stats->ifHCInUcastPkts +=
4779 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4780 stats->ifHCInMulticastPkts +=
4781 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4782 stats->ifHCInBroadcastPkts +=
4783 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4784 stats->dot3StatsFCSErrors +=
4785 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4786 stats->dot3StatsAlignmentErrors +=
4787 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4788 stats->xonPauseFramesReceived +=
4789 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4790 stats->xoffPauseFramesReceived +=
4791 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4792 stats->macControlFramesReceived +=
4793 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4794 stats->xoffStateEntered +=
4795 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4796 stats->dot3StatsFramesTooLong +=
4797 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4798 stats->etherStatsJabbers +=
4799 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4800 stats->etherStatsUndersizePkts +=
4801 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4803 stats->FramesDroppedDueToFilters +=
4804 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4805 stats->DmaWriteQueueFull +=
4806 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4807 stats->DmaWriteHighPriQueueFull +=
4808 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4809 stats->NoMoreRxBDs +=
4810 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4813 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS
4814 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0
4815 * includes number of unwanted multicast frames. This comes
4816 * from silicon bug and known workaround to get rough(not
4817 * exact) counter is to enable interrupt on MBUF low water
4818 * attention. This can be accomplished by setting
4819 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE,
4820 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and
4821 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL.
4822 * However that change would generate more interrupts and
4823 * there are still possibilities of losing multiple frames
4824 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling.
4825 * Given that the workaround still would not get correct
4826 * counter I don't think it's worth to implement it. So
4827 * ignore reading the counter on controllers that have the
4830 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
4831 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
4832 sc->bge_chipid != BGE_CHIPID_BCM5720_A0)
4833 stats->InputDiscards +=
4834 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4835 stats->InputErrors +=
4836 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4837 stats->RecvThresholdHit +=
4838 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4840 ifp->if_collisions = (u_long)stats->etherStatsCollisions;
4841 ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards +
4842 stats->InputErrors);
4846 bge_stats_clear_regs(struct bge_softc *sc)
4849 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4850 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4851 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4852 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4853 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4854 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4855 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4856 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4857 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4858 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4859 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4860 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4861 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4863 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4864 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4865 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4866 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4867 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4868 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4869 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4870 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4871 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4872 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4873 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4874 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4875 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4876 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4878 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4879 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4880 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4881 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4882 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4883 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4884 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4888 bge_stats_update(struct bge_softc *sc)
4892 uint32_t cnt; /* current register value */
4896 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
4898 #define READ_STAT(sc, stats, stat) \
4899 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
4901 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
4902 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
4903 sc->bge_tx_collisions = cnt;
4905 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo);
4906 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_nobds);
4907 sc->bge_rx_nobds = cnt;
4908 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo);
4909 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_inerrs);
4910 sc->bge_rx_inerrs = cnt;
4911 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
4912 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
4913 sc->bge_rx_discards = cnt;
4915 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
4916 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
4917 sc->bge_tx_discards = cnt;
4923 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
4924 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
4925 * but when such padded frames employ the bge IP/TCP checksum offload,
4926 * the hardware checksum assist gives incorrect results (possibly
4927 * from incorporating its own padding into the UDP/TCP checksum; who knows).
4928 * If we pad such runts with zeros, the onboard checksum comes out correct.
4931 bge_cksum_pad(struct mbuf *m)
4933 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
4936 /* If there's only the packet-header and we can pad there, use it. */
4937 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
4938 M_TRAILINGSPACE(m) >= padlen) {
4942 * Walk packet chain to find last mbuf. We will either
4943 * pad there, or append a new mbuf and pad it.
4945 for (last = m; last->m_next != NULL; last = last->m_next);
4946 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
4947 /* Allocate new empty mbuf, pad it. Compact later. */
4950 MGET(n, M_NOWAIT, MT_DATA);
4959 /* Now zero the pad area, to avoid the bge cksum-assist bug. */
4960 memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
4961 last->m_len += padlen;
4962 m->m_pkthdr.len += padlen;
4967 static struct mbuf *
4968 bge_check_short_dma(struct mbuf *m)
4974 * If device receive two back-to-back send BDs with less than
4975 * or equal to 8 total bytes then the device may hang. The two
4976 * back-to-back send BDs must in the same frame for this failure
4977 * to occur. Scan mbuf chains and see whether two back-to-back
4978 * send BDs are there. If this is the case, allocate new mbuf
4979 * and copy the frame to workaround the silicon bug.
4981 for (n = m, found = 0; n != NULL; n = n->m_next) {
4992 n = m_defrag(m, M_NOWAIT);
5000 static struct mbuf *
5001 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
5010 if (M_WRITABLE(m) == 0) {
5011 /* Get a writable copy. */
5012 n = m_dup(m, M_NOWAIT);
5018 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
5021 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5022 poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
5023 m = m_pullup(m, poff + sizeof(struct tcphdr));
5026 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5027 m = m_pullup(m, poff + (tcp->th_off << 2));
5031 * It seems controller doesn't modify IP length and TCP pseudo
5032 * checksum. These checksum computed by upper stack should be 0.
5034 *mss = m->m_pkthdr.tso_segsz;
5035 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5037 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
5038 /* Clear pseudo checksum computed by TCP stack. */
5039 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5042 * Broadcom controllers uses different descriptor format for
5043 * TSO depending on ASIC revision. Due to TSO-capable firmware
5044 * license issue and lower performance of firmware based TSO
5045 * we only support hardware based TSO.
5047 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */
5048 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
5049 if (sc->bge_flags & BGE_FLAG_TSO3) {
5051 * For BCM5717 and newer controllers, hardware based TSO
5052 * uses the 14 lower bits of the bge_mss field to store the
5053 * MSS and the upper 2 bits to store the lowest 2 bits of
5054 * the IP/TCP header length. The upper 6 bits of the header
5055 * length are stored in the bge_flags[14:10,4] field. Jumbo
5056 * frames are supported.
5058 *mss |= ((hlen & 0x3) << 14);
5059 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2);
5062 * For BCM5755 and newer controllers, hardware based TSO uses
5063 * the lower 11 bits to store the MSS and the upper 5 bits to
5064 * store the IP/TCP header length. Jumbo frames are not
5067 *mss |= (hlen << 11);
5073 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
5074 * pointers to descriptors.
5077 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
5079 bus_dma_segment_t segs[BGE_NSEG_NEW];
5081 struct bge_tx_bd *d;
5082 struct mbuf *m = *m_head;
5083 uint32_t idx = *txidx;
5084 uint16_t csum_flags, mss, vlan_tag;
5085 int nsegs, i, error;
5090 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
5091 m->m_next != NULL) {
5092 *m_head = bge_check_short_dma(m);
5093 if (*m_head == NULL)
5097 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5098 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
5099 if (*m_head == NULL)
5101 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
5102 BGE_TXBDFLAG_CPU_POST_DMA;
5103 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
5104 if (m->m_pkthdr.csum_flags & CSUM_IP)
5105 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
5106 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
5107 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
5108 if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
5109 (error = bge_cksum_pad(m)) != 0) {
5117 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
5118 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
5119 m->m_pkthdr.len > ETHER_MAX_LEN)
5120 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME;
5121 if (sc->bge_forced_collapse > 0 &&
5122 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
5124 * Forcedly collapse mbuf chains to overcome hardware
5125 * limitation which only support a single outstanding
5126 * DMA read operation.
5128 if (sc->bge_forced_collapse == 1)
5129 m = m_defrag(m, M_NOWAIT);
5131 m = m_collapse(m, M_NOWAIT,
5132 sc->bge_forced_collapse);
5139 map = sc->bge_cdata.bge_tx_dmamap[idx];
5140 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
5141 &nsegs, BUS_DMA_NOWAIT);
5142 if (error == EFBIG) {
5143 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW);
5150 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
5151 m, segs, &nsegs, BUS_DMA_NOWAIT);
5157 } else if (error != 0)
5160 /* Check if we have enough free send BDs. */
5161 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
5162 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5166 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
5168 if (m->m_flags & M_VLANTAG) {
5169 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
5170 vlan_tag = m->m_pkthdr.ether_vtag;
5172 for (i = 0; ; i++) {
5173 d = &sc->bge_ldata.bge_tx_ring[idx];
5174 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5175 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5176 d->bge_len = segs[i].ds_len;
5177 d->bge_flags = csum_flags;
5178 d->bge_vlan_tag = vlan_tag;
5182 BGE_INC(idx, BGE_TX_RING_CNT);
5185 /* Mark the last segment as end of packet... */
5186 d->bge_flags |= BGE_TXBDFLAG_END;
5189 * Insure that the map for this transmission
5190 * is placed at the array index of the last descriptor
5193 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
5194 sc->bge_cdata.bge_tx_dmamap[idx] = map;
5195 sc->bge_cdata.bge_tx_chain[idx] = m;
5196 sc->bge_txcnt += nsegs;
5198 BGE_INC(idx, BGE_TX_RING_CNT);
5205 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5206 * to the mbuf data regions directly in the transmit descriptors.
5209 bge_start_locked(struct ifnet *ifp)
5211 struct bge_softc *sc;
5212 struct mbuf *m_head;
5217 BGE_LOCK_ASSERT(sc);
5219 if (!sc->bge_link ||
5220 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
5224 prodidx = sc->bge_tx_prodidx;
5226 for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
5227 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
5228 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
5231 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
5236 * Pack the data into the transmit ring. If we
5237 * don't have room, set the OACTIVE flag and wait
5238 * for the NIC to drain the ring.
5240 if (bge_encap(sc, &m_head, &prodidx)) {
5243 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
5244 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
5250 * If there's a BPF listener, bounce a copy of this frame
5253 #ifdef ETHER_BPF_MTAP
5254 ETHER_BPF_MTAP(ifp, m_head);
5256 BPF_MTAP(ifp, m_head);
5261 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
5262 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
5264 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5265 /* 5700 b2 errata */
5266 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
5267 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5269 sc->bge_tx_prodidx = prodidx;
5272 * Set a timeout in case the chip goes out to lunch.
5279 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5280 * to the mbuf data regions directly in the transmit descriptors.
5283 bge_start(struct ifnet *ifp)
5285 struct bge_softc *sc;
5289 bge_start_locked(ifp);
5294 bge_init_locked(struct bge_softc *sc)
5300 BGE_LOCK_ASSERT(sc);
5304 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
5307 /* Cancel pending I/O and flush buffers. */
5311 bge_sig_pre_reset(sc, BGE_RESET_START);
5313 bge_sig_legacy(sc, BGE_RESET_START);
5314 bge_sig_post_reset(sc, BGE_RESET_START);
5319 * Init the various state machines, ring
5320 * control blocks and firmware.
5322 if (bge_blockinit(sc)) {
5323 device_printf(sc->bge_dev, "initialization failure\n");
5330 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
5331 ETHER_HDR_LEN + ETHER_CRC_LEN +
5332 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
5334 /* Load our MAC address. */
5335 m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
5336 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
5337 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
5339 /* Program promiscuous mode. */
5342 /* Program multicast filter. */
5345 /* Program VLAN tag stripping. */
5348 /* Override UDP checksum offloading. */
5349 if (sc->bge_forced_udpcsum == 0)
5350 sc->bge_csum_features &= ~CSUM_UDP;
5352 sc->bge_csum_features |= CSUM_UDP;
5353 if (ifp->if_capabilities & IFCAP_TXCSUM &&
5354 ifp->if_capenable & IFCAP_TXCSUM) {
5355 ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP);
5356 ifp->if_hwassist |= sc->bge_csum_features;
5360 if (bge_init_rx_ring_std(sc) != 0) {
5361 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
5367 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
5368 * memory to insure that the chip has in fact read the first
5369 * entry of the ring.
5371 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
5373 for (i = 0; i < 10; i++) {
5375 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
5376 if (v == (MCLBYTES - ETHER_ALIGN))
5380 device_printf (sc->bge_dev,
5381 "5705 A0 chip failed to load RX ring\n");
5384 /* Init jumbo RX ring. */
5385 if (BGE_IS_JUMBO_CAPABLE(sc) &&
5386 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
5387 (MCLBYTES - ETHER_ALIGN)) {
5388 if (bge_init_rx_ring_jumbo(sc) != 0) {
5389 device_printf(sc->bge_dev,
5390 "no memory for jumbo Rx buffers.\n");
5396 /* Init our RX return ring index. */
5397 sc->bge_rx_saved_considx = 0;
5399 /* Init our RX/TX stat counters. */
5400 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
5403 bge_init_tx_ring(sc);
5405 /* Enable TX MAC state machine lockup fix. */
5406 mode = CSR_READ_4(sc, BGE_TX_MODE);
5407 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
5408 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
5409 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
5410 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5411 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
5412 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5414 /* Turn on transmitter. */
5415 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
5418 /* Turn on receiver. */
5419 mode = CSR_READ_4(sc, BGE_RX_MODE);
5420 if (BGE_IS_5755_PLUS(sc))
5421 mode |= BGE_RXMODE_IPV6_ENABLE;
5422 CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
5426 * Set the number of good frames to receive after RX MBUF
5427 * Low Watermark has been reached. After the RX MAC receives
5428 * this number of frames, it will drop subsequent incoming
5429 * frames until the MBUF High Watermark is reached.
5431 if (BGE_IS_57765_PLUS(sc))
5432 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
5434 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
5436 /* Clear MAC statistics. */
5437 if (BGE_IS_5705_PLUS(sc))
5438 bge_stats_clear_regs(sc);
5440 /* Tell firmware we're alive. */
5441 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5443 #ifdef DEVICE_POLLING
5444 /* Disable interrupts if we are polling. */
5445 if (ifp->if_capenable & IFCAP_POLLING) {
5446 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5447 BGE_PCIMISCCTL_MASK_PCI_INTR);
5448 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5452 /* Enable host interrupts. */
5454 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
5455 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5456 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5459 ifp->if_drv_flags |= IFF_DRV_RUNNING;
5460 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5462 bge_ifmedia_upd_locked(ifp);
5464 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
5470 struct bge_softc *sc = xsc;
5473 bge_init_locked(sc);
5478 * Set media options.
5481 bge_ifmedia_upd(struct ifnet *ifp)
5483 struct bge_softc *sc = ifp->if_softc;
5487 res = bge_ifmedia_upd_locked(ifp);
5494 bge_ifmedia_upd_locked(struct ifnet *ifp)
5496 struct bge_softc *sc = ifp->if_softc;
5497 struct mii_data *mii;
5498 struct mii_softc *miisc;
5499 struct ifmedia *ifm;
5501 BGE_LOCK_ASSERT(sc);
5503 ifm = &sc->bge_ifmedia;
5505 /* If this is a 1000baseX NIC, enable the TBI port. */
5506 if (sc->bge_flags & BGE_FLAG_TBI) {
5507 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
5509 switch(IFM_SUBTYPE(ifm->ifm_media)) {
5512 * The BCM5704 ASIC appears to have a special
5513 * mechanism for programming the autoneg
5514 * advertisement registers in TBI mode.
5516 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
5518 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5519 if (sgdig & BGE_SGDIGSTS_DONE) {
5520 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5521 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5522 sgdig |= BGE_SGDIGCFG_AUTO |
5523 BGE_SGDIGCFG_PAUSE_CAP |
5524 BGE_SGDIGCFG_ASYM_PAUSE;
5525 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
5526 sgdig | BGE_SGDIGCFG_SEND);
5528 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
5533 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
5534 BGE_CLRBIT(sc, BGE_MAC_MODE,
5535 BGE_MACMODE_HALF_DUPLEX);
5537 BGE_SETBIT(sc, BGE_MAC_MODE,
5538 BGE_MACMODE_HALF_DUPLEX);
5549 mii = device_get_softc(sc->bge_miibus);
5550 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
5555 * Force an interrupt so that we will call bge_link_upd
5556 * if needed and clear any pending link state attention.
5557 * Without this we are not getting any further interrupts
5558 * for link state changes and thus will not UP the link and
5559 * not be able to send in bge_start_locked. The only
5560 * way to get things working was to receive a packet and
5562 * bge_tick should help for fiber cards and we might not
5563 * need to do this here if BGE_FLAG_TBI is set but as
5564 * we poll for fiber anyway it should not harm.
5566 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
5567 sc->bge_flags & BGE_FLAG_5788)
5568 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
5570 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
5576 * Report current media status.
5579 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
5581 struct bge_softc *sc = ifp->if_softc;
5582 struct mii_data *mii;
5586 if ((ifp->if_flags & IFF_UP) == 0) {
5590 if (sc->bge_flags & BGE_FLAG_TBI) {
5591 ifmr->ifm_status = IFM_AVALID;
5592 ifmr->ifm_active = IFM_ETHER;
5593 if (CSR_READ_4(sc, BGE_MAC_STS) &
5594 BGE_MACSTAT_TBI_PCS_SYNCHED)
5595 ifmr->ifm_status |= IFM_ACTIVE;
5597 ifmr->ifm_active |= IFM_NONE;
5601 ifmr->ifm_active |= IFM_1000_SX;
5602 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5603 ifmr->ifm_active |= IFM_HDX;
5605 ifmr->ifm_active |= IFM_FDX;
5610 mii = device_get_softc(sc->bge_miibus);
5612 ifmr->ifm_active = mii->mii_media_active;
5613 ifmr->ifm_status = mii->mii_media_status;
5619 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
5621 struct bge_softc *sc = ifp->if_softc;
5622 struct ifreq *ifr = (struct ifreq *) data;
5623 struct mii_data *mii;
5624 int flags, mask, error = 0;
5628 if (BGE_IS_JUMBO_CAPABLE(sc) ||
5629 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
5630 if (ifr->ifr_mtu < ETHERMIN ||
5631 ifr->ifr_mtu > BGE_JUMBO_MTU) {
5635 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) {
5640 if (ifp->if_mtu != ifr->ifr_mtu) {
5641 ifp->if_mtu = ifr->ifr_mtu;
5642 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5643 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5644 bge_init_locked(sc);
5651 if (ifp->if_flags & IFF_UP) {
5653 * If only the state of the PROMISC flag changed,
5654 * then just use the 'set promisc mode' command
5655 * instead of reinitializing the entire NIC. Doing
5656 * a full re-init means reloading the firmware and
5657 * waiting for it to start up, which may take a
5658 * second or two. Similarly for ALLMULTI.
5660 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5661 flags = ifp->if_flags ^ sc->bge_if_flags;
5662 if (flags & IFF_PROMISC)
5664 if (flags & IFF_ALLMULTI)
5667 bge_init_locked(sc);
5669 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5673 sc->bge_if_flags = ifp->if_flags;
5679 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5688 if (sc->bge_flags & BGE_FLAG_TBI) {
5689 error = ifmedia_ioctl(ifp, ifr,
5690 &sc->bge_ifmedia, command);
5692 mii = device_get_softc(sc->bge_miibus);
5693 error = ifmedia_ioctl(ifp, ifr,
5694 &mii->mii_media, command);
5698 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5699 #ifdef DEVICE_POLLING
5700 if (mask & IFCAP_POLLING) {
5701 if (ifr->ifr_reqcap & IFCAP_POLLING) {
5702 error = ether_poll_register(bge_poll, ifp);
5706 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5707 BGE_PCIMISCCTL_MASK_PCI_INTR);
5708 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5709 ifp->if_capenable |= IFCAP_POLLING;
5712 error = ether_poll_deregister(ifp);
5713 /* Enable interrupt even in error case */
5715 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
5716 BGE_PCIMISCCTL_MASK_PCI_INTR);
5717 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5718 ifp->if_capenable &= ~IFCAP_POLLING;
5723 if ((mask & IFCAP_TXCSUM) != 0 &&
5724 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
5725 ifp->if_capenable ^= IFCAP_TXCSUM;
5726 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
5727 ifp->if_hwassist |= sc->bge_csum_features;
5729 ifp->if_hwassist &= ~sc->bge_csum_features;
5732 if ((mask & IFCAP_RXCSUM) != 0 &&
5733 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
5734 ifp->if_capenable ^= IFCAP_RXCSUM;
5736 if ((mask & IFCAP_TSO4) != 0 &&
5737 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
5738 ifp->if_capenable ^= IFCAP_TSO4;
5739 if ((ifp->if_capenable & IFCAP_TSO4) != 0)
5740 ifp->if_hwassist |= CSUM_TSO;
5742 ifp->if_hwassist &= ~CSUM_TSO;
5745 if (mask & IFCAP_VLAN_MTU) {
5746 ifp->if_capenable ^= IFCAP_VLAN_MTU;
5747 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5751 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
5752 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
5753 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
5754 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
5755 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
5756 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
5757 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
5758 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
5763 #ifdef VLAN_CAPABILITIES
5764 VLAN_CAPABILITIES(ifp);
5768 error = ether_ioctl(ifp, command, data);
5776 bge_watchdog(struct bge_softc *sc)
5780 BGE_LOCK_ASSERT(sc);
5782 if (sc->bge_timer == 0 || --sc->bge_timer)
5787 if_printf(ifp, "watchdog timeout -- resetting\n");
5789 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5790 bge_init_locked(sc);
5796 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
5800 BGE_CLRBIT(sc, reg, bit);
5802 for (i = 0; i < BGE_TIMEOUT; i++) {
5803 if ((CSR_READ_4(sc, reg) & bit) == 0)
5810 * Stop the adapter and free any mbufs allocated to the
5814 bge_stop(struct bge_softc *sc)
5818 BGE_LOCK_ASSERT(sc);
5822 callout_stop(&sc->bge_stat_ch);
5824 /* Disable host interrupts. */
5825 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5826 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5829 * Tell firmware we're shutting down.
5832 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
5835 * Disable all of the receiver blocks.
5837 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
5838 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
5839 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
5840 if (BGE_IS_5700_FAMILY(sc))
5841 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
5842 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
5843 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
5844 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
5847 * Disable all of the transmit blocks.
5849 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
5850 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
5851 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
5852 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
5853 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
5854 if (BGE_IS_5700_FAMILY(sc))
5855 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
5856 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
5859 * Shut down all of the memory managers and related
5862 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
5863 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
5864 if (BGE_IS_5700_FAMILY(sc))
5865 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
5867 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
5868 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
5869 if (!(BGE_IS_5705_PLUS(sc))) {
5870 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
5871 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
5873 /* Update MAC statistics. */
5874 if (BGE_IS_5705_PLUS(sc))
5875 bge_stats_update_regs(sc);
5878 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
5879 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
5882 * Keep the ASF firmware running if up.
5884 if (sc->bge_asf_mode & ASF_STACKUP)
5885 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5887 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5889 /* Free the RX lists. */
5890 bge_free_rx_ring_std(sc);
5892 /* Free jumbo RX list. */
5893 if (BGE_IS_JUMBO_CAPABLE(sc))
5894 bge_free_rx_ring_jumbo(sc);
5896 /* Free TX buffers. */
5897 bge_free_tx_ring(sc);
5899 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
5901 /* Clear MAC's link state (PHY may still have link UP). */
5902 if (bootverbose && sc->bge_link)
5903 if_printf(sc->bge_ifp, "link DOWN\n");
5906 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
5910 * Stop all chip I/O so that the kernel's probe routines don't
5911 * get confused by errant DMAs when rebooting.
5914 bge_shutdown(device_t dev)
5916 struct bge_softc *sc;
5918 sc = device_get_softc(dev);
5927 bge_suspend(device_t dev)
5929 struct bge_softc *sc;
5931 sc = device_get_softc(dev);
5940 bge_resume(device_t dev)
5942 struct bge_softc *sc;
5945 sc = device_get_softc(dev);
5948 if (ifp->if_flags & IFF_UP) {
5949 bge_init_locked(sc);
5950 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
5951 bge_start_locked(ifp);
5959 bge_link_upd(struct bge_softc *sc)
5961 struct mii_data *mii;
5962 uint32_t link, status;
5964 BGE_LOCK_ASSERT(sc);
5966 /* Clear 'pending link event' flag. */
5967 sc->bge_link_evt = 0;
5970 * Process link state changes.
5971 * Grrr. The link status word in the status block does
5972 * not work correctly on the BCM5700 rev AX and BX chips,
5973 * according to all available information. Hence, we have
5974 * to enable MII interrupts in order to properly obtain
5975 * async link changes. Unfortunately, this also means that
5976 * we have to read the MAC status register to detect link
5977 * changes, thereby adding an additional register access to
5978 * the interrupt handler.
5980 * XXX: perhaps link state detection procedure used for
5981 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
5984 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
5985 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
5986 status = CSR_READ_4(sc, BGE_MAC_STS);
5987 if (status & BGE_MACSTAT_MI_INTERRUPT) {
5988 mii = device_get_softc(sc->bge_miibus);
5990 if (!sc->bge_link &&
5991 mii->mii_media_status & IFM_ACTIVE &&
5992 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5995 if_printf(sc->bge_ifp, "link UP\n");
5996 } else if (sc->bge_link &&
5997 (!(mii->mii_media_status & IFM_ACTIVE) ||
5998 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6001 if_printf(sc->bge_ifp, "link DOWN\n");
6004 /* Clear the interrupt. */
6005 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
6006 BGE_EVTENB_MI_INTERRUPT);
6007 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
6009 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
6010 BRGPHY_MII_IMR, BRGPHY_INTRS);
6015 if (sc->bge_flags & BGE_FLAG_TBI) {
6016 status = CSR_READ_4(sc, BGE_MAC_STS);
6017 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
6018 if (!sc->bge_link) {
6020 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
6021 BGE_CLRBIT(sc, BGE_MAC_MODE,
6022 BGE_MACMODE_TBI_SEND_CFGS);
6025 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
6027 if_printf(sc->bge_ifp, "link UP\n");
6028 if_link_state_change(sc->bge_ifp,
6031 } else if (sc->bge_link) {
6034 if_printf(sc->bge_ifp, "link DOWN\n");
6035 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
6037 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
6039 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
6040 * in status word always set. Workaround this bug by reading
6041 * PHY link status directly.
6043 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
6045 if (link != sc->bge_link ||
6046 sc->bge_asicrev == BGE_ASICREV_BCM5700) {
6047 mii = device_get_softc(sc->bge_miibus);
6049 if (!sc->bge_link &&
6050 mii->mii_media_status & IFM_ACTIVE &&
6051 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6054 if_printf(sc->bge_ifp, "link UP\n");
6055 } else if (sc->bge_link &&
6056 (!(mii->mii_media_status & IFM_ACTIVE) ||
6057 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6060 if_printf(sc->bge_ifp, "link DOWN\n");
6065 * For controllers that call mii_tick, we have to poll
6068 mii = device_get_softc(sc->bge_miibus);
6070 bge_miibus_statchg(sc->bge_dev);
6073 /* Disable MAC attention when link is up. */
6074 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
6075 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
6076 BGE_MACSTAT_LINK_CHANGED);
6080 bge_add_sysctls(struct bge_softc *sc)
6082 struct sysctl_ctx_list *ctx;
6083 struct sysctl_oid_list *children;
6087 ctx = device_get_sysctl_ctx(sc->bge_dev);
6088 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
6090 #ifdef BGE_REGISTER_DEBUG
6091 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
6092 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
6093 "Debug Information");
6095 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
6096 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
6097 "MAC Register Read");
6099 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read",
6100 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I",
6101 "APE Register Read");
6103 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
6104 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
6109 unit = device_get_unit(sc->bge_dev);
6111 * A common design characteristic for many Broadcom client controllers
6112 * is that they only support a single outstanding DMA read operation
6113 * on the PCIe bus. This means that it will take twice as long to fetch
6114 * a TX frame that is split into header and payload buffers as it does
6115 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
6116 * these controllers, coalescing buffers to reduce the number of memory
6117 * reads is effective way to get maximum performance(about 940Mbps).
6118 * Without collapsing TX buffers the maximum TCP bulk transfer
6119 * performance is about 850Mbps. However forcing coalescing mbufs
6120 * consumes a lot of CPU cycles, so leave it off by default.
6122 sc->bge_forced_collapse = 0;
6123 snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit);
6124 TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse);
6125 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
6126 CTLFLAG_RW, &sc->bge_forced_collapse, 0,
6127 "Number of fragmented TX buffers of a frame allowed before "
6128 "forced collapsing");
6131 snprintf(tn, sizeof(tn), "dev.bge.%d.msi", unit);
6132 TUNABLE_INT_FETCH(tn, &sc->bge_msi);
6133 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi",
6134 CTLFLAG_RD, &sc->bge_msi, 0, "Enable MSI");
6137 * It seems all Broadcom controllers have a bug that can generate UDP
6138 * datagrams with checksum value 0 when TX UDP checksum offloading is
6139 * enabled. Generating UDP checksum value 0 is RFC 768 violation.
6140 * Even though the probability of generating such UDP datagrams is
6141 * low, I don't want to see FreeBSD boxes to inject such datagrams
6142 * into network so disable UDP checksum offloading by default. Users
6143 * still override this behavior by setting a sysctl variable,
6144 * dev.bge.0.forced_udpcsum.
6146 sc->bge_forced_udpcsum = 0;
6147 snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit);
6148 TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum);
6149 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum",
6150 CTLFLAG_RW, &sc->bge_forced_udpcsum, 0,
6151 "Enable UDP checksum offloading even if controller can "
6152 "generate UDP checksum value 0");
6154 if (BGE_IS_5705_PLUS(sc))
6155 bge_add_sysctl_stats_regs(sc, ctx, children);
6157 bge_add_sysctl_stats(sc, ctx, children);
6160 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
6161 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
6162 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
6166 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6167 struct sysctl_oid_list *parent)
6169 struct sysctl_oid *tree;
6170 struct sysctl_oid_list *children, *schildren;
6172 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6173 NULL, "BGE Statistics");
6174 schildren = children = SYSCTL_CHILDREN(tree);
6175 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
6176 children, COSFramesDroppedDueToFilters,
6177 "FramesDroppedDueToFilters");
6178 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
6179 children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
6180 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
6181 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
6182 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
6183 children, nicNoMoreRxBDs, "NoMoreRxBDs");
6184 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
6185 children, ifInDiscards, "InputDiscards");
6186 BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
6187 children, ifInErrors, "InputErrors");
6188 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
6189 children, nicRecvThresholdHit, "RecvThresholdHit");
6190 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
6191 children, nicDmaReadQueueFull, "DmaReadQueueFull");
6192 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
6193 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
6194 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
6195 children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
6196 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
6197 children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
6198 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
6199 children, nicRingStatusUpdate, "RingStatusUpdate");
6200 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
6201 children, nicInterrupts, "Interrupts");
6202 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
6203 children, nicAvoidedInterrupts, "AvoidedInterrupts");
6204 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
6205 children, nicSendThresholdHit, "SendThresholdHit");
6207 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
6208 NULL, "BGE RX Statistics");
6209 children = SYSCTL_CHILDREN(tree);
6210 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
6211 children, rxstats.ifHCInOctets, "ifHCInOctets");
6212 BGE_SYSCTL_STAT(sc, ctx, "Fragments",
6213 children, rxstats.etherStatsFragments, "Fragments");
6214 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
6215 children, rxstats.ifHCInUcastPkts, "UnicastPkts");
6216 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
6217 children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
6218 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
6219 children, rxstats.dot3StatsFCSErrors, "FCSErrors");
6220 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
6221 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
6222 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
6223 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
6224 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
6225 children, rxstats.xoffPauseFramesReceived,
6226 "xoffPauseFramesReceived");
6227 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
6228 children, rxstats.macControlFramesReceived,
6229 "ControlFramesReceived");
6230 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
6231 children, rxstats.xoffStateEntered, "xoffStateEntered");
6232 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
6233 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
6234 BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
6235 children, rxstats.etherStatsJabbers, "Jabbers");
6236 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
6237 children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
6238 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
6239 children, rxstats.inRangeLengthError, "inRangeLengthError");
6240 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
6241 children, rxstats.outRangeLengthError, "outRangeLengthError");
6243 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
6244 NULL, "BGE TX Statistics");
6245 children = SYSCTL_CHILDREN(tree);
6246 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
6247 children, txstats.ifHCOutOctets, "ifHCOutOctets");
6248 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
6249 children, txstats.etherStatsCollisions, "Collisions");
6250 BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
6251 children, txstats.outXonSent, "XonSent");
6252 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
6253 children, txstats.outXoffSent, "XoffSent");
6254 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
6255 children, txstats.flowControlDone, "flowControlDone");
6256 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
6257 children, txstats.dot3StatsInternalMacTransmitErrors,
6258 "InternalMacTransmitErrors");
6259 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
6260 children, txstats.dot3StatsSingleCollisionFrames,
6261 "SingleCollisionFrames");
6262 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
6263 children, txstats.dot3StatsMultipleCollisionFrames,
6264 "MultipleCollisionFrames");
6265 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
6266 children, txstats.dot3StatsDeferredTransmissions,
6267 "DeferredTransmissions");
6268 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
6269 children, txstats.dot3StatsExcessiveCollisions,
6270 "ExcessiveCollisions");
6271 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
6272 children, txstats.dot3StatsLateCollisions,
6274 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
6275 children, txstats.ifHCOutUcastPkts, "UnicastPkts");
6276 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
6277 children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
6278 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
6279 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
6280 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
6281 children, txstats.dot3StatsCarrierSenseErrors,
6282 "CarrierSenseErrors");
6283 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
6284 children, txstats.ifOutDiscards, "Discards");
6285 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
6286 children, txstats.ifOutErrors, "Errors");
6289 #undef BGE_SYSCTL_STAT
6291 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
6292 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
6295 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6296 struct sysctl_oid_list *parent)
6298 struct sysctl_oid *tree;
6299 struct sysctl_oid_list *child, *schild;
6300 struct bge_mac_stats *stats;
6302 stats = &sc->bge_mac_stats;
6303 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6304 NULL, "BGE Statistics");
6305 schild = child = SYSCTL_CHILDREN(tree);
6306 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters",
6307 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters");
6308 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull",
6309 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full");
6310 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull",
6311 &stats->DmaWriteHighPriQueueFull,
6312 "NIC DMA Write High Priority Queue Full");
6313 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs",
6314 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors");
6315 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards",
6316 &stats->InputDiscards, "Discarded Input Frames");
6317 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors",
6318 &stats->InputErrors, "Input Errors");
6319 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit",
6320 &stats->RecvThresholdHit, "NIC Recv Threshold Hit");
6322 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD,
6323 NULL, "BGE RX Statistics");
6324 child = SYSCTL_CHILDREN(tree);
6325 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets",
6326 &stats->ifHCInOctets, "Inbound Octets");
6327 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments",
6328 &stats->etherStatsFragments, "Fragments");
6329 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6330 &stats->ifHCInUcastPkts, "Inbound Unicast Packets");
6331 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6332 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets");
6333 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6334 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets");
6335 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors",
6336 &stats->dot3StatsFCSErrors, "FCS Errors");
6337 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors",
6338 &stats->dot3StatsAlignmentErrors, "Alignment Errors");
6339 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived",
6340 &stats->xonPauseFramesReceived, "XON Pause Frames Received");
6341 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived",
6342 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received");
6343 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived",
6344 &stats->macControlFramesReceived, "MAC Control Frames Received");
6345 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered",
6346 &stats->xoffStateEntered, "XOFF State Entered");
6347 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong",
6348 &stats->dot3StatsFramesTooLong, "Frames Too Long");
6349 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers",
6350 &stats->etherStatsJabbers, "Jabbers");
6351 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts",
6352 &stats->etherStatsUndersizePkts, "Undersized Packets");
6354 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD,
6355 NULL, "BGE TX Statistics");
6356 child = SYSCTL_CHILDREN(tree);
6357 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets",
6358 &stats->ifHCOutOctets, "Outbound Octets");
6359 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions",
6360 &stats->etherStatsCollisions, "TX Collisions");
6361 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent",
6362 &stats->outXonSent, "XON Sent");
6363 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent",
6364 &stats->outXoffSent, "XOFF Sent");
6365 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors",
6366 &stats->dot3StatsInternalMacTransmitErrors,
6367 "Internal MAC TX Errors");
6368 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames",
6369 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames");
6370 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames",
6371 &stats->dot3StatsMultipleCollisionFrames,
6372 "Multiple Collision Frames");
6373 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions",
6374 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions");
6375 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions",
6376 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions");
6377 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions",
6378 &stats->dot3StatsLateCollisions, "Late Collisions");
6379 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6380 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets");
6381 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6382 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets");
6383 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6384 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets");
6387 #undef BGE_SYSCTL_STAT_ADD64
6390 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
6392 struct bge_softc *sc;
6396 sc = (struct bge_softc *)arg1;
6398 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
6399 offsetof(bge_hostaddr, bge_addr_lo));
6400 return (sysctl_handle_int(oidp, &result, 0, req));
6403 #ifdef BGE_REGISTER_DEBUG
6405 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
6407 struct bge_softc *sc;
6409 int error, result, sbsz;
6413 error = sysctl_handle_int(oidp, &result, 0, req);
6414 if (error || (req->newptr == NULL))
6418 sc = (struct bge_softc *)arg1;
6420 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6421 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
6422 sbsz = BGE_STATUS_BLK_SZ;
6425 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
6426 printf("Status Block:\n");
6428 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6429 sc->bge_cdata.bge_status_map,
6430 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6431 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) {
6433 for (j = 0; j < 8; j++)
6434 printf(" %04x", sbdata[i++]);
6438 printf("Registers:\n");
6439 for (i = 0x800; i < 0xA00; ) {
6441 for (j = 0; j < 8; j++) {
6442 printf(" %08x", CSR_READ_4(sc, i));
6449 printf("Hardware Flags:\n");
6450 if (BGE_IS_5717_PLUS(sc))
6451 printf(" - 5717 Plus\n");
6452 if (BGE_IS_5755_PLUS(sc))
6453 printf(" - 5755 Plus\n");
6454 if (BGE_IS_575X_PLUS(sc))
6455 printf(" - 575X Plus\n");
6456 if (BGE_IS_5705_PLUS(sc))
6457 printf(" - 5705 Plus\n");
6458 if (BGE_IS_5714_FAMILY(sc))
6459 printf(" - 5714 Family\n");
6460 if (BGE_IS_5700_FAMILY(sc))
6461 printf(" - 5700 Family\n");
6462 if (sc->bge_flags & BGE_FLAG_JUMBO)
6463 printf(" - Supports Jumbo Frames\n");
6464 if (sc->bge_flags & BGE_FLAG_PCIX)
6465 printf(" - PCI-X Bus\n");
6466 if (sc->bge_flags & BGE_FLAG_PCIE)
6467 printf(" - PCI Express Bus\n");
6468 if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
6469 printf(" - No 3 LEDs\n");
6470 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
6471 printf(" - RX Alignment Bug\n");
6478 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6480 struct bge_softc *sc;
6486 error = sysctl_handle_int(oidp, &result, 0, req);
6487 if (error || (req->newptr == NULL))
6490 if (result < 0x8000) {
6491 sc = (struct bge_softc *)arg1;
6492 val = CSR_READ_4(sc, result);
6493 printf("reg 0x%06X = 0x%08X\n", result, val);
6500 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS)
6502 struct bge_softc *sc;
6508 error = sysctl_handle_int(oidp, &result, 0, req);
6509 if (error || (req->newptr == NULL))
6512 if (result < 0x8000) {
6513 sc = (struct bge_softc *)arg1;
6514 val = APE_READ_4(sc, result);
6515 printf("reg 0x%06X = 0x%08X\n", result, val);
6522 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
6524 struct bge_softc *sc;
6530 error = sysctl_handle_int(oidp, &result, 0, req);
6531 if (error || (req->newptr == NULL))
6534 if (result < 0x8000) {
6535 sc = (struct bge_softc *)arg1;
6536 val = bge_readmem_ind(sc, result);
6537 printf("mem 0x%06X = 0x%08X\n", result, val);
6545 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
6548 if (sc->bge_flags & BGE_FLAG_EADDR)
6552 OF_getetheraddr(sc->bge_dev, ether_addr);
6559 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
6563 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
6564 if ((mac_addr >> 16) == 0x484b) {
6565 ether_addr[0] = (uint8_t)(mac_addr >> 8);
6566 ether_addr[1] = (uint8_t)mac_addr;
6567 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
6568 ether_addr[2] = (uint8_t)(mac_addr >> 24);
6569 ether_addr[3] = (uint8_t)(mac_addr >> 16);
6570 ether_addr[4] = (uint8_t)(mac_addr >> 8);
6571 ether_addr[5] = (uint8_t)mac_addr;
6578 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
6580 int mac_offset = BGE_EE_MAC_OFFSET;
6582 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6583 mac_offset = BGE_EE_MAC_OFFSET_5906;
6585 return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
6590 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
6593 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6596 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
6601 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
6603 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
6604 /* NOTE: Order is critical */
6607 bge_get_eaddr_nvram,
6608 bge_get_eaddr_eeprom,
6611 const bge_eaddr_fcn_t *func;
6613 for (func = bge_eaddr_funcs; *func != NULL; ++func) {
6614 if ((*func)(sc, eaddr) == 0)
6617 return (*func == NULL ? ENXIO : 0);