sys/dev/bge/if_bge.c

   1 /*-
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/cdefs.h>
  35 __FBSDID("$FreeBSD$");
  36
  37 /*
  38  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  39  *
  40  * The Broadcom BCM5700 is based on technology originally developed by
  41  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  42  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  43  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  44  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  45  * frames, highly configurable RX filtering, and 16 RX and TX queues
  46  * (which, along with RX filter rules, can be used for QOS applications).
  47  * Other features, such as TCP segmentation, may be available as part
  48  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  49  * firmware images can be stored in hardware and need not be compiled
  50  * into the driver.
  51  *
  52  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  53  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  54  *
  55  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  56  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  57  * does not support external SSRAM.
  58  *
  59  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  60  * brand name, which is functionally similar but lacks PCI-X support.
  61  *
  62  * Without external SSRAM, you can only have at most 4 TX rings,
  63  * and the use of the mini RX ring is disabled. This seems to imply
  64  * that these features are simply not available on the BCM5701. As a
  65  * result, this driver does not implement any support for the mini RX
  66  * ring.
  67  */
  68
  69 #ifdef HAVE_KERNEL_OPTION_HEADERS
  70 #include "opt_device_polling.h"
  71 #endif
  72
  73 #include <sys/param.h>
  74 #include <sys/endian.h>
  75 #include <sys/systm.h>
  76 #include <sys/sockio.h>
  77 #include <sys/mbuf.h>
  78 #include <sys/malloc.h>
  79 #include <sys/kernel.h>
  80 #include <sys/module.h>
  81 #include <sys/socket.h>
  82 #include <sys/sysctl.h>
  83 #include <sys/taskqueue.h>
  84
  85 #include <net/if.h>
  86 #include <net/if_arp.h>
  87 #include <net/ethernet.h>
  88 #include <net/if_dl.h>
  89 #include <net/if_media.h>
  90
  91 #include <net/bpf.h>
  92
  93 #include <net/if_types.h>
  94 #include <net/if_vlan_var.h>
  95
  96 #include <netinet/in_systm.h>
  97 #include <netinet/in.h>
  98 #include <netinet/ip.h>
  99 #include <netinet/tcp.h>
 100
 101 #include <machine/bus.h>
 102 #include <machine/resource.h>
 103 #include <sys/bus.h>
 104 #include <sys/rman.h>
 105
 106 #include <dev/mii/mii.h>
 107 #include <dev/mii/miivar.h>
 108 #include "miidevs.h"
 109 #include <dev/mii/brgphyreg.h>
 110
 111 #ifdef __sparc64__
 112 #include <dev/ofw/ofw_bus.h>
 113 #include <dev/ofw/openfirm.h>
 114 #include <machine/ofw_machdep.h>
 115 #include <machine/ver.h>
 116 #endif
 117
 118 #include <dev/pci/pcireg.h>
 119 #include <dev/pci/pcivar.h>
 120
 121 #include <dev/bge/if_bgereg.h>
 122
 123 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 124 #define ETHER_MIN_NOPAD         (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
 125
 126 MODULE_DEPEND(bge, pci, 1, 1, 1);
 127 MODULE_DEPEND(bge, ether, 1, 1, 1);
 128 MODULE_DEPEND(bge, miibus, 1, 1, 1);
 129
 130 /* "device miibus" required.  See GENERIC if you get errors here. */
 131 #include "miibus_if.h"
 132
 133 /*
 134  * Various supported device vendors/types and their names. Note: the
 135  * spec seems to indicate that the hardware still has Alteon's vendor
 136  * ID burned into it, though it will always be overriden by the vendor
 137  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 138  */
 139 static const struct bge_type {
 140         uint16_t        bge_vid;
 141         uint16_t        bge_did;
 142 } bge_devs[] = {
 143         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5700 },
 144         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5701 },
 145
 146         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1000 },
 147         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1002 },
 148         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC9100 },
 149
 150         { APPLE_VENDORID,       APPLE_DEVICE_BCM5701 },
 151
 152         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5700 },
 153         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5701 },
 154         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702 },
 155         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702_ALT },
 156         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702X },
 157         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703 },
 158         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703_ALT },
 159         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703X },
 160         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704C },
 161         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S },
 162         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S_ALT },
 163         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705 },
 164         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705F },
 165         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705K },
 166         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M },
 167         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M_ALT },
 168         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714C },
 169         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714S },
 170         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715 },
 171         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715S },
 172         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5720 },
 173         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5721 },
 174         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5722 },
 175         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5723 },
 176         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750 },
 177         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750M },
 178         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751 },
 179         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751F },
 180         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751M },
 181         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752 },
 182         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752M },
 183         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753 },
 184         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753F },
 185         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753M },
 186         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754 },
 187         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754M },
 188         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755 },
 189         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755M },
 190         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761 },
 191         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761E },
 192         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761S },
 193         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761SE },
 194         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5764 },
 195         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780 },
 196         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780S },
 197         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5781 },
 198         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5782 },
 199         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5784 },
 200         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785F },
 201         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785G },
 202         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5786 },
 203         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787 },
 204         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787F },
 205         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787M },
 206         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5788 },
 207         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5789 },
 208         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901 },
 209         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901A2 },
 210         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5903M },
 211         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906 },
 212         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906M },
 213         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57760 },
 214         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57780 },
 215         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57788 },
 216         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57790 },
 217
 218         { SK_VENDORID,          SK_DEVICEID_ALTIMA },
 219
 220         { TC_VENDORID,          TC_DEVICEID_3C996 },
 221
 222         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE4 },
 223         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE5 },
 224         { FJTSU_VENDORID,       FJTSU_DEVICEID_PP250450 },
 225
 226         { 0, 0 }
 227 };
 228
 229 static const struct bge_vendor {
 230         uint16_t        v_id;
 231         const char      *v_name;
 232 } bge_vendors[] = {
 233         { ALTEON_VENDORID,      "Alteon" },
 234         { ALTIMA_VENDORID,      "Altima" },
 235         { APPLE_VENDORID,       "Apple" },
 236         { BCOM_VENDORID,        "Broadcom" },
 237         { SK_VENDORID,          "SysKonnect" },
 238         { TC_VENDORID,          "3Com" },
 239         { FJTSU_VENDORID,       "Fujitsu" },
 240
 241         { 0, NULL }
 242 };
 243
 244 static const struct bge_revision {
 245         uint32_t        br_chipid;
 246         const char      *br_name;
 247 } bge_revisions[] = {
 248         { BGE_CHIPID_BCM5700_A0,        "BCM5700 A0" },
 249         { BGE_CHIPID_BCM5700_A1,        "BCM5700 A1" },
 250         { BGE_CHIPID_BCM5700_B0,        "BCM5700 B0" },
 251         { BGE_CHIPID_BCM5700_B1,        "BCM5700 B1" },
 252         { BGE_CHIPID_BCM5700_B2,        "BCM5700 B2" },
 253         { BGE_CHIPID_BCM5700_B3,        "BCM5700 B3" },
 254         { BGE_CHIPID_BCM5700_ALTIMA,    "BCM5700 Altima" },
 255         { BGE_CHIPID_BCM5700_C0,        "BCM5700 C0" },
 256         { BGE_CHIPID_BCM5701_A0,        "BCM5701 A0" },
 257         { BGE_CHIPID_BCM5701_B0,        "BCM5701 B0" },
 258         { BGE_CHIPID_BCM5701_B2,        "BCM5701 B2" },
 259         { BGE_CHIPID_BCM5701_B5,        "BCM5701 B5" },
 260         { BGE_CHIPID_BCM5703_A0,        "BCM5703 A0" },
 261         { BGE_CHIPID_BCM5703_A1,        "BCM5703 A1" },
 262         { BGE_CHIPID_BCM5703_A2,        "BCM5703 A2" },
 263         { BGE_CHIPID_BCM5703_A3,        "BCM5703 A3" },
 264         { BGE_CHIPID_BCM5703_B0,        "BCM5703 B0" },
 265         { BGE_CHIPID_BCM5704_A0,        "BCM5704 A0" },
 266         { BGE_CHIPID_BCM5704_A1,        "BCM5704 A1" },
 267         { BGE_CHIPID_BCM5704_A2,        "BCM5704 A2" },
 268         { BGE_CHIPID_BCM5704_A3,        "BCM5704 A3" },
 269         { BGE_CHIPID_BCM5704_B0,        "BCM5704 B0" },
 270         { BGE_CHIPID_BCM5705_A0,        "BCM5705 A0" },
 271         { BGE_CHIPID_BCM5705_A1,        "BCM5705 A1" },
 272         { BGE_CHIPID_BCM5705_A2,        "BCM5705 A2" },
 273         { BGE_CHIPID_BCM5705_A3,        "BCM5705 A3" },
 274         { BGE_CHIPID_BCM5750_A0,        "BCM5750 A0" },
 275         { BGE_CHIPID_BCM5750_A1,        "BCM5750 A1" },
 276         { BGE_CHIPID_BCM5750_A3,        "BCM5750 A3" },
 277         { BGE_CHIPID_BCM5750_B0,        "BCM5750 B0" },
 278         { BGE_CHIPID_BCM5750_B1,        "BCM5750 B1" },
 279         { BGE_CHIPID_BCM5750_C0,        "BCM5750 C0" },
 280         { BGE_CHIPID_BCM5750_C1,        "BCM5750 C1" },
 281         { BGE_CHIPID_BCM5750_C2,        "BCM5750 C2" },
 282         { BGE_CHIPID_BCM5714_A0,        "BCM5714 A0" },
 283         { BGE_CHIPID_BCM5752_A0,        "BCM5752 A0" },
 284         { BGE_CHIPID_BCM5752_A1,        "BCM5752 A1" },
 285         { BGE_CHIPID_BCM5752_A2,        "BCM5752 A2" },
 286         { BGE_CHIPID_BCM5714_B0,        "BCM5714 B0" },
 287         { BGE_CHIPID_BCM5714_B3,        "BCM5714 B3" },
 288         { BGE_CHIPID_BCM5715_A0,        "BCM5715 A0" },
 289         { BGE_CHIPID_BCM5715_A1,        "BCM5715 A1" },
 290         { BGE_CHIPID_BCM5715_A3,        "BCM5715 A3" },
 291         { BGE_CHIPID_BCM5755_A0,        "BCM5755 A0" },
 292         { BGE_CHIPID_BCM5755_A1,        "BCM5755 A1" },
 293         { BGE_CHIPID_BCM5755_A2,        "BCM5755 A2" },
 294         { BGE_CHIPID_BCM5722_A0,        "BCM5722 A0" },
 295         { BGE_CHIPID_BCM5761_A0,        "BCM5761 A0" },
 296         { BGE_CHIPID_BCM5761_A1,        "BCM5761 A1" },
 297         { BGE_CHIPID_BCM5784_A0,        "BCM5784 A0" },
 298         { BGE_CHIPID_BCM5784_A1,        "BCM5784 A1" },
 299         /* 5754 and 5787 share the same ASIC ID */
 300         { BGE_CHIPID_BCM5787_A0,        "BCM5754/5787 A0" },
 301         { BGE_CHIPID_BCM5787_A1,        "BCM5754/5787 A1" },
 302         { BGE_CHIPID_BCM5787_A2,        "BCM5754/5787 A2" },
 303         { BGE_CHIPID_BCM5906_A1,        "BCM5906 A1" },
 304         { BGE_CHIPID_BCM5906_A2,        "BCM5906 A2" },
 305         { BGE_CHIPID_BCM57780_A0,       "BCM57780 A0" },
 306         { BGE_CHIPID_BCM57780_A1,       "BCM57780 A1" },
 307
 308         { 0, NULL }
 309 };
 310
 311 /*
 312  * Some defaults for major revisions, so that newer steppings
 313  * that we don't know about have a shot at working.
 314  */
 315 static const struct bge_revision bge_majorrevs[] = {
 316         { BGE_ASICREV_BCM5700,          "unknown BCM5700" },
 317         { BGE_ASICREV_BCM5701,          "unknown BCM5701" },
 318         { BGE_ASICREV_BCM5703,          "unknown BCM5703" },
 319         { BGE_ASICREV_BCM5704,          "unknown BCM5704" },
 320         { BGE_ASICREV_BCM5705,          "unknown BCM5705" },
 321         { BGE_ASICREV_BCM5750,          "unknown BCM5750" },
 322         { BGE_ASICREV_BCM5714_A0,       "unknown BCM5714" },
 323         { BGE_ASICREV_BCM5752,          "unknown BCM5752" },
 324         { BGE_ASICREV_BCM5780,          "unknown BCM5780" },
 325         { BGE_ASICREV_BCM5714,          "unknown BCM5714" },
 326         { BGE_ASICREV_BCM5755,          "unknown BCM5755" },
 327         { BGE_ASICREV_BCM5761,          "unknown BCM5761" },
 328         { BGE_ASICREV_BCM5784,          "unknown BCM5784" },
 329         { BGE_ASICREV_BCM5785,          "unknown BCM5785" },
 330         /* 5754 and 5787 share the same ASIC ID */
 331         { BGE_ASICREV_BCM5787,          "unknown BCM5754/5787" },
 332         { BGE_ASICREV_BCM5906,          "unknown BCM5906" },
 333         { BGE_ASICREV_BCM57780,         "unknown BCM57780" },
 334
 335         { 0, NULL }
 336 };
 337
 338 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 339 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 340 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 341 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 342 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 343 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 344
 345 const struct bge_revision * bge_lookup_rev(uint32_t);
 346 const struct bge_vendor * bge_lookup_vendor(uint16_t);
 347
 348 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 349
 350 static int bge_probe(device_t);
 351 static int bge_attach(device_t);
 352 static int bge_detach(device_t);
 353 static int bge_suspend(device_t);
 354 static int bge_resume(device_t);
 355 static void bge_release_resources(struct bge_softc *);
 356 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 357 static int bge_dma_alloc(device_t);
 358 static void bge_dma_free(struct bge_softc *);
 359
 360 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
 361 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 362 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 363 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 364 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
 365
 366 static void bge_txeof(struct bge_softc *, uint16_t);
 367 static int bge_rxeof(struct bge_softc *, uint16_t, int);
 368
 369 static void bge_asf_driver_up (struct bge_softc *);
 370 static void bge_tick(void *);
 371 static void bge_stats_update(struct bge_softc *);
 372 static void bge_stats_update_regs(struct bge_softc *);
 373 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
 374     uint16_t *);
 375 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 376
 377 static void bge_intr(void *);
 378 static int bge_msi_intr(void *);
 379 static void bge_intr_task(void *, int);
 380 static void bge_start_locked(struct ifnet *);
 381 static void bge_start(struct ifnet *);
 382 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
 383 static void bge_init_locked(struct bge_softc *);
 384 static void bge_init(void *);
 385 static void bge_stop(struct bge_softc *);
 386 static void bge_watchdog(struct bge_softc *);
 387 static int bge_shutdown(device_t);
 388 static int bge_ifmedia_upd_locked(struct ifnet *);
 389 static int bge_ifmedia_upd(struct ifnet *);
 390 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 391
 392 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 393 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 394
 395 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
 396 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
 397
 398 static void bge_setpromisc(struct bge_softc *);
 399 static void bge_setmulti(struct bge_softc *);
 400 static void bge_setvlan(struct bge_softc *);
 401
 402 static int bge_newbuf_std(struct bge_softc *, int);
 403 static int bge_newbuf_jumbo(struct bge_softc *, int);
 404 static int bge_init_rx_ring_std(struct bge_softc *);
 405 static void bge_free_rx_ring_std(struct bge_softc *);
 406 static int bge_init_rx_ring_jumbo(struct bge_softc *);
 407 static void bge_free_rx_ring_jumbo(struct bge_softc *);
 408 static void bge_free_tx_ring(struct bge_softc *);
 409 static int bge_init_tx_ring(struct bge_softc *);
 410
 411 static int bge_chipinit(struct bge_softc *);
 412 static int bge_blockinit(struct bge_softc *);
 413
 414 static int bge_has_eaddr(struct bge_softc *);
 415 static uint32_t bge_readmem_ind(struct bge_softc *, int);
 416 static void bge_writemem_ind(struct bge_softc *, int, int);
 417 static void bge_writembx(struct bge_softc *, int, int);
 418 #ifdef notdef
 419 static uint32_t bge_readreg_ind(struct bge_softc *, int);
 420 #endif
 421 static void bge_writemem_direct(struct bge_softc *, int, int);
 422 static void bge_writereg_ind(struct bge_softc *, int, int);
 423 static void bge_set_max_readrq(struct bge_softc *);
 424
 425 static int bge_miibus_readreg(device_t, int, int);
 426 static int bge_miibus_writereg(device_t, int, int, int);
 427 static void bge_miibus_statchg(device_t);
 428 #ifdef DEVICE_POLLING
 429 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 430 #endif
 431
 432 #define BGE_RESET_START 1
 433 #define BGE_RESET_STOP  2
 434 static void bge_sig_post_reset(struct bge_softc *, int);
 435 static void bge_sig_legacy(struct bge_softc *, int);
 436 static void bge_sig_pre_reset(struct bge_softc *, int);
 437 static int bge_reset(struct bge_softc *);
 438 static void bge_link_upd(struct bge_softc *);
 439
 440 /*
 441  * The BGE_REGISTER_DEBUG option is only for low-level debugging.  It may
 442  * leak information to untrusted users.  It is also known to cause alignment
 443  * traps on certain architectures.
 444  */
 445 #ifdef BGE_REGISTER_DEBUG
 446 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 447 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
 448 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
 449 #endif
 450 static void bge_add_sysctls(struct bge_softc *);
 451 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
 452
 453 static device_method_t bge_methods[] = {
 454         /* Device interface */
 455         DEVMETHOD(device_probe,         bge_probe),
 456         DEVMETHOD(device_attach,        bge_attach),
 457         DEVMETHOD(device_detach,        bge_detach),
 458         DEVMETHOD(device_shutdown,      bge_shutdown),
 459         DEVMETHOD(device_suspend,       bge_suspend),
 460         DEVMETHOD(device_resume,        bge_resume),
 461
 462         /* bus interface */
 463         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 464         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 465
 466         /* MII interface */
 467         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 468         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 469         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 470
 471         { 0, 0 }
 472 };
 473
 474 static driver_t bge_driver = {
 475         "bge",
 476         bge_methods,
 477         sizeof(struct bge_softc)
 478 };
 479
 480 static devclass_t bge_devclass;
 481
 482 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
 483 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 484
 485 static int bge_allow_asf = 1;
 486 /*
 487  * A common design characteristic for many Broadcom client controllers
 488  * is that they only support a single outstanding DMA read operation
 489  * on the PCIe bus. This means that it will take twice as long to fetch
 490  * a TX frame that is split into header and payload buffers as it does
 491  * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
 492  * these controllers, coalescing buffers to reduce the number of memory
 493  * reads is effective way to get maximum performance(about 940Mbps).
 494  * Without collapsing TX buffers the maximum TCP bulk transfer
 495  * performance is about 850Mbps. However forcing coalescing mbufs
 496  * consumes a lot of CPU cycles, so leave it off by default.
 497  */
 498 static int bge_forced_collapse = 0;
 499
 500 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
 501 TUNABLE_INT("hw.bge.forced_collapse", &bge_forced_collapse);
 502
 503 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
 504 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
 505         "Allow ASF mode if available");
 506 SYSCTL_INT(_hw_bge, OID_AUTO, forced_collapse, CTLFLAG_RD, &bge_forced_collapse,
 507         0, "Number of fragmented TX buffers of a frame allowed before "
 508         "forced collapsing");
 509
 510 #define SPARC64_BLADE_1500_MODEL        "SUNW,Sun-Blade-1500"
 511 #define SPARC64_BLADE_1500_PATH_BGE     "/pci@1f,700000/network@2"
 512 #define SPARC64_BLADE_2500_MODEL        "SUNW,Sun-Blade-2500"
 513 #define SPARC64_BLADE_2500_PATH_BGE     "/pci@1c,600000/network@3"
 514 #define SPARC64_OFW_SUBVENDOR           "subsystem-vendor-id"
 515
 516 static int
 517 bge_has_eaddr(struct bge_softc *sc)
 518 {
 519 #ifdef __sparc64__
 520         char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
 521         device_t dev;
 522         uint32_t subvendor;
 523
 524         dev = sc->bge_dev;
 525
 526         /*
 527          * The on-board BGEs found in sun4u machines aren't fitted with
 528          * an EEPROM which means that we have to obtain the MAC address
 529          * via OFW and that some tests will always fail.  We distinguish
 530          * such BGEs by the subvendor ID, which also has to be obtained
 531          * from OFW instead of the PCI configuration space as the latter
 532          * indicates Broadcom as the subvendor of the netboot interface.
 533          * For early Blade 1500 and 2500 we even have to check the OFW
 534          * device path as the subvendor ID always defaults to Broadcom
 535          * there.
 536          */
 537         if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
 538             &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
 539             subvendor == SUN_VENDORID)
 540                 return (0);
 541         memset(buf, 0, sizeof(buf));
 542         if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
 543                 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
 544                     strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
 545                         return (0);
 546                 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
 547                     strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
 548                         return (0);
 549         }
 550 #endif
 551         return (1);
 552 }
 553
 554 static uint32_t
 555 bge_readmem_ind(struct bge_softc *sc, int off)
 556 {
 557         device_t dev;
 558         uint32_t val;
 559
 560         dev = sc->bge_dev;
 561
 562         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 563         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 564         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 565         return (val);
 566 }
 567
 568 static void
 569 bge_writemem_ind(struct bge_softc *sc, int off, int val)
 570 {
 571         device_t dev;
 572
 573         dev = sc->bge_dev;
 574
 575         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 576         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 577         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 578 }
 579
 580 /*
 581  * PCI Express only
 582  */
 583 static void
 584 bge_set_max_readrq(struct bge_softc *sc)
 585 {
 586         device_t dev;
 587         uint16_t val;
 588
 589         dev = sc->bge_dev;
 590
 591         val = pci_read_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
 592         if ((val & PCIM_EXP_CTL_MAX_READ_REQUEST) !=
 593             BGE_PCIE_DEVCTL_MAX_READRQ_4096) {
 594                 if (bootverbose)
 595                         device_printf(dev, "adjust device control 0x%04x ",
 596                             val);
 597                 val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST;
 598                 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096;
 599                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL,
 600                     val, 2);
 601                 if (bootverbose)
 602                         printf("-> 0x%04x\n", val);
 603         }
 604 }
 605
 606 #ifdef notdef
 607 static uint32_t
 608 bge_readreg_ind(struct bge_softc *sc, int off)
 609 {
 610         device_t dev;
 611
 612         dev = sc->bge_dev;
 613
 614         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 615         return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 616 }
 617 #endif
 618
 619 static void
 620 bge_writereg_ind(struct bge_softc *sc, int off, int val)
 621 {
 622         device_t dev;
 623
 624         dev = sc->bge_dev;
 625
 626         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 627         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 628 }
 629
 630 static void
 631 bge_writemem_direct(struct bge_softc *sc, int off, int val)
 632 {
 633         CSR_WRITE_4(sc, off, val);
 634 }
 635
 636 static void
 637 bge_writembx(struct bge_softc *sc, int off, int val)
 638 {
 639         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 640                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 641
 642         CSR_WRITE_4(sc, off, val);
 643 }
 644
 645 /*
 646  * Map a single buffer address.
 647  */
 648
 649 static void
 650 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 651 {
 652         struct bge_dmamap_arg *ctx;
 653
 654         if (error)
 655                 return;
 656
 657         ctx = arg;
 658
 659         if (nseg > ctx->bge_maxsegs) {
 660                 ctx->bge_maxsegs = 0;
 661                 return;
 662         }
 663
 664         ctx->bge_busaddr = segs->ds_addr;
 665 }
 666
 667 static uint8_t
 668 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 669 {
 670         uint32_t access, byte = 0;
 671         int i;
 672
 673         /* Lock. */
 674         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 675         for (i = 0; i < 8000; i++) {
 676                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 677                         break;
 678                 DELAY(20);
 679         }
 680         if (i == 8000)
 681                 return (1);
 682
 683         /* Enable access. */
 684         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 685         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 686
 687         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 688         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 689         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 690                 DELAY(10);
 691                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 692                         DELAY(10);
 693                         break;
 694                 }
 695         }
 696
 697         if (i == BGE_TIMEOUT * 10) {
 698                 if_printf(sc->bge_ifp, "nvram read timed out\n");
 699                 return (1);
 700         }
 701
 702         /* Get result. */
 703         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 704
 705         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 706
 707         /* Disable access. */
 708         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 709
 710         /* Unlock. */
 711         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 712         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 713
 714         return (0);
 715 }
 716
 717 /*
 718  * Read a sequence of bytes from NVRAM.
 719  */
 720 static int
 721 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 722 {
 723         int err = 0, i;
 724         uint8_t byte = 0;
 725
 726         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 727                 return (1);
 728
 729         for (i = 0; i < cnt; i++) {
 730                 err = bge_nvram_getbyte(sc, off + i, &byte);
 731                 if (err)
 732                         break;
 733                 *(dest + i) = byte;
 734         }
 735
 736         return (err ? 1 : 0);
 737 }
 738
 739 /*
 740  * Read a byte of data stored in the EEPROM at address 'addr.' The
 741  * BCM570x supports both the traditional bitbang interface and an
 742  * auto access interface for reading the EEPROM. We use the auto
 743  * access method.
 744  */
 745 static uint8_t
 746 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 747 {
 748         int i;
 749         uint32_t byte = 0;
 750
 751         /*
 752          * Enable use of auto EEPROM access so we can avoid
 753          * having to use the bitbang method.
 754          */
 755         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 756
 757         /* Reset the EEPROM, load the clock period. */
 758         CSR_WRITE_4(sc, BGE_EE_ADDR,
 759             BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 760         DELAY(20);
 761
 762         /* Issue the read EEPROM command. */
 763         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 764
 765         /* Wait for completion */
 766         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 767                 DELAY(10);
 768                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 769                         break;
 770         }
 771
 772         if (i == BGE_TIMEOUT * 10) {
 773                 device_printf(sc->bge_dev, "EEPROM read timed out\n");
 774                 return (1);
 775         }
 776
 777         /* Get result. */
 778         byte = CSR_READ_4(sc, BGE_EE_DATA);
 779
 780         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 781
 782         return (0);
 783 }
 784
 785 /*
 786  * Read a sequence of bytes from the EEPROM.
 787  */
 788 static int
 789 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 790 {
 791         int i, error = 0;
 792         uint8_t byte = 0;
 793
 794         for (i = 0; i < cnt; i++) {
 795                 error = bge_eeprom_getbyte(sc, off + i, &byte);
 796                 if (error)
 797                         break;
 798                 *(dest + i) = byte;
 799         }
 800
 801         return (error ? 1 : 0);
 802 }
 803
 804 static int
 805 bge_miibus_readreg(device_t dev, int phy, int reg)
 806 {
 807         struct bge_softc *sc;
 808         uint32_t val, autopoll;
 809         int i;
 810
 811         sc = device_get_softc(dev);
 812
 813         /*
 814          * Broadcom's own driver always assumes the internal
 815          * PHY is at GMII address 1. On some chips, the PHY responds
 816          * to accesses at all addresses, which could cause us to
 817          * bogusly attach the PHY 32 times at probe type. Always
 818          * restricting the lookup to address 1 is simpler than
 819          * trying to figure out which chips revisions should be
 820          * special-cased.
 821          */
 822         if (phy != 1)
 823                 return (0);
 824
 825         /* Reading with autopolling on may trigger PCI errors */
 826         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 827         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 828                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 829                 DELAY(40);
 830         }
 831
 832         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 833             BGE_MIPHY(phy) | BGE_MIREG(reg));
 834
 835         for (i = 0; i < BGE_TIMEOUT; i++) {
 836                 DELAY(10);
 837                 val = CSR_READ_4(sc, BGE_MI_COMM);
 838                 if (!(val & BGE_MICOMM_BUSY))
 839                         break;
 840         }
 841
 842         if (i == BGE_TIMEOUT) {
 843                 device_printf(sc->bge_dev,
 844                     "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
 845                     phy, reg, val);
 846                 val = 0;
 847                 goto done;
 848         }
 849
 850         DELAY(5);
 851         val = CSR_READ_4(sc, BGE_MI_COMM);
 852
 853 done:
 854         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 855                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 856                 DELAY(40);
 857         }
 858
 859         if (val & BGE_MICOMM_READFAIL)
 860                 return (0);
 861
 862         return (val & 0xFFFF);
 863 }
 864
 865 static int
 866 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 867 {
 868         struct bge_softc *sc;
 869         uint32_t autopoll;
 870         int i;
 871
 872         sc = device_get_softc(dev);
 873
 874         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 875             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 876                 return(0);
 877
 878         /* Reading with autopolling on may trigger PCI errors */
 879         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 880         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 881                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 882                 DELAY(40);
 883         }
 884
 885         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 886             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 887
 888         for (i = 0; i < BGE_TIMEOUT; i++) {
 889                 DELAY(10);
 890                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 891                         DELAY(5);
 892                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 893                         break;
 894                 }
 895         }
 896
 897         if (i == BGE_TIMEOUT) {
 898                 device_printf(sc->bge_dev,
 899                     "PHY write timed out (phy %d, reg %d, val %d)\n",
 900                     phy, reg, val);
 901                 return (0);
 902         }
 903
 904         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 905                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 906                 DELAY(40);
 907         }
 908
 909         return (0);
 910 }
 911
 912 static void
 913 bge_miibus_statchg(device_t dev)
 914 {
 915         struct bge_softc *sc;
 916         struct mii_data *mii;
 917         sc = device_get_softc(dev);
 918         mii = device_get_softc(sc->bge_miibus);
 919
 920         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 921         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
 922                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 923         else
 924                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 925
 926         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
 927                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 928         else
 929                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 930 }
 931
 932 /*
 933  * Intialize a standard receive ring descriptor.
 934  */
 935 static int
 936 bge_newbuf_std(struct bge_softc *sc, int i)
 937 {
 938         struct mbuf *m;
 939         struct bge_rx_bd *r;
 940         bus_dma_segment_t segs[1];
 941         bus_dmamap_t map;
 942         int error, nsegs;
 943
 944         m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
 945         if (m == NULL)
 946                 return (ENOBUFS);
 947         m->m_len = m->m_pkthdr.len = MCLBYTES;
 948         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 949                 m_adj(m, ETHER_ALIGN);
 950
 951         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
 952             sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
 953         if (error != 0) {
 954                 m_freem(m);
 955                 return (error);
 956         }
 957         if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 958                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 959                     sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
 960                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 961                     sc->bge_cdata.bge_rx_std_dmamap[i]);
 962         }
 963         map = sc->bge_cdata.bge_rx_std_dmamap[i];
 964         sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
 965         sc->bge_cdata.bge_rx_std_sparemap = map;
 966         sc->bge_cdata.bge_rx_std_chain[i] = m;
 967         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
 968         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
 969         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
 970         r->bge_flags = BGE_RXBDFLAG_END;
 971         r->bge_len = segs[0].ds_len;
 972         r->bge_idx = i;
 973
 974         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 975             sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
 976
 977         return (0);
 978 }
 979
 980 /*
 981  * Initialize a jumbo receive ring descriptor. This allocates
 982  * a jumbo buffer from the pool managed internally by the driver.
 983  */
 984 static int
 985 bge_newbuf_jumbo(struct bge_softc *sc, int i)
 986 {
 987         bus_dma_segment_t segs[BGE_NSEG_JUMBO];
 988         bus_dmamap_t map;
 989         struct bge_extrx_bd *r;
 990         struct mbuf *m;
 991         int error, nsegs;
 992
 993         MGETHDR(m, M_DONTWAIT, MT_DATA);
 994         if (m == NULL)
 995                 return (ENOBUFS);
 996
 997         m_cljget(m, M_DONTWAIT, MJUM9BYTES);
 998         if (!(m->m_flags & M_EXT)) {
 999                 m_freem(m);
1000                 return (ENOBUFS);
1001         }
1002         m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1003         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1004                 m_adj(m, ETHER_ALIGN);
1005
1006         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1007             sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1008         if (error != 0) {
1009                 m_freem(m);
1010                 return (error);
1011         }
1012
1013         if (sc->bge_cdata.bge_rx_jumbo_chain[i] == NULL) {
1014                 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1015                     sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1016                 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1017                     sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1018         }
1019         map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1020         sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1021             sc->bge_cdata.bge_rx_jumbo_sparemap;
1022         sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1023         sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1024         /*
1025          * Fill in the extended RX buffer descriptor.
1026          */
1027         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1028         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1029         r->bge_idx = i;
1030         r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1031         switch (nsegs) {
1032         case 4:
1033                 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1034                 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1035                 r->bge_len3 = segs[3].ds_len;
1036         case 3:
1037                 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1038                 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1039                 r->bge_len2 = segs[2].ds_len;
1040         case 2:
1041                 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1042                 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1043                 r->bge_len1 = segs[1].ds_len;
1044         case 1:
1045                 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1046                 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1047                 r->bge_len0 = segs[0].ds_len;
1048                 break;
1049         default:
1050                 panic("%s: %d segments\n", __func__, nsegs);
1051         }
1052
1053         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1054             sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1055
1056         return (0);
1057 }
1058
1059 /*
1060  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1061  * that's 1MB or memory, which is a lot. For now, we fill only the first
1062  * 256 ring entries and hope that our CPU is fast enough to keep up with
1063  * the NIC.
1064  */
1065 static int
1066 bge_init_rx_ring_std(struct bge_softc *sc)
1067 {
1068         int error, i;
1069
1070         bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1071         sc->bge_std = 0;
1072         for (i = 0; i < BGE_SSLOTS; i++) {
1073                 if ((error = bge_newbuf_std(sc, i)) != 0)
1074                         return (error);
1075                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1076         };
1077
1078         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1079             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1080
1081         sc->bge_std = i - 1;
1082         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1083
1084         return (0);
1085 }
1086
1087 static void
1088 bge_free_rx_ring_std(struct bge_softc *sc)
1089 {
1090         int i;
1091
1092         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1093                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1094                         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1095                             sc->bge_cdata.bge_rx_std_dmamap[i],
1096                             BUS_DMASYNC_POSTREAD);
1097                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1098                             sc->bge_cdata.bge_rx_std_dmamap[i]);
1099                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1100                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1101                 }
1102                 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1103                     sizeof(struct bge_rx_bd));
1104         }
1105 }
1106
1107 static int
1108 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1109 {
1110         struct bge_rcb *rcb;
1111         int error, i;
1112
1113         bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1114         sc->bge_jumbo = 0;
1115         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1116                 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1117                         return (error);
1118                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1119         };
1120
1121         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1122             sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1123
1124         sc->bge_jumbo = i - 1;
1125
1126         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1127         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1128                                     BGE_RCB_FLAG_USE_EXT_RX_BD);
1129         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1130
1131         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1132
1133         return (0);
1134 }
1135
1136 static void
1137 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1138 {
1139         int i;
1140
1141         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1142                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1143                         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1144                             sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1145                             BUS_DMASYNC_POSTREAD);
1146                         bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1147                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1148                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1149                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1150                 }
1151                 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1152                     sizeof(struct bge_extrx_bd));
1153         }
1154 }
1155
1156 static void
1157 bge_free_tx_ring(struct bge_softc *sc)
1158 {
1159         int i;
1160
1161         if (sc->bge_ldata.bge_tx_ring == NULL)
1162                 return;
1163
1164         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1165                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1166                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1167                             sc->bge_cdata.bge_tx_dmamap[i],
1168                             BUS_DMASYNC_POSTWRITE);
1169                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1170                             sc->bge_cdata.bge_tx_dmamap[i]);
1171                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1172                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1173                 }
1174                 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1175                     sizeof(struct bge_tx_bd));
1176         }
1177 }
1178
1179 static int
1180 bge_init_tx_ring(struct bge_softc *sc)
1181 {
1182         sc->bge_txcnt = 0;
1183         sc->bge_tx_saved_considx = 0;
1184
1185         bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1186         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1187             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1188
1189         /* Initialize transmit producer index for host-memory send ring. */
1190         sc->bge_tx_prodidx = 0;
1191         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1192
1193         /* 5700 b2 errata */
1194         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1195                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1196
1197         /* NIC-memory send ring not used; initialize to zero. */
1198         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1199         /* 5700 b2 errata */
1200         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1201                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1202
1203         return (0);
1204 }
1205
1206 static void
1207 bge_setpromisc(struct bge_softc *sc)
1208 {
1209         struct ifnet *ifp;
1210
1211         BGE_LOCK_ASSERT(sc);
1212
1213         ifp = sc->bge_ifp;
1214
1215         /* Enable or disable promiscuous mode as needed. */
1216         if (ifp->if_flags & IFF_PROMISC)
1217                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1218         else
1219                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1220 }
1221
1222 static void
1223 bge_setmulti(struct bge_softc *sc)
1224 {
1225         struct ifnet *ifp;
1226         struct ifmultiaddr *ifma;
1227         uint32_t hashes[4] = { 0, 0, 0, 0 };
1228         int h, i;
1229
1230         BGE_LOCK_ASSERT(sc);
1231
1232         ifp = sc->bge_ifp;
1233
1234         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1235                 for (i = 0; i < 4; i++)
1236                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1237                 return;
1238         }
1239
1240         /* First, zot all the existing filters. */
1241         for (i = 0; i < 4; i++)
1242                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1243
1244         /* Now program new ones. */
1245         if_maddr_rlock(ifp);
1246         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1247                 if (ifma->ifma_addr->sa_family != AF_LINK)
1248                         continue;
1249                 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1250                     ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1251                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1252         }
1253         if_maddr_runlock(ifp);
1254
1255         for (i = 0; i < 4; i++)
1256                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1257 }
1258
1259 static void
1260 bge_setvlan(struct bge_softc *sc)
1261 {
1262         struct ifnet *ifp;
1263
1264         BGE_LOCK_ASSERT(sc);
1265
1266         ifp = sc->bge_ifp;
1267
1268         /* Enable or disable VLAN tag stripping as needed. */
1269         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1270                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1271         else
1272                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1273 }
1274
1275 static void
1276 bge_sig_pre_reset(sc, type)
1277         struct bge_softc *sc;
1278         int type;
1279 {
1280         /*
1281          * Some chips don't like this so only do this if ASF is enabled
1282          */
1283         if (sc->bge_asf_mode)
1284                 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1285
1286         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1287                 switch (type) {
1288                 case BGE_RESET_START:
1289                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1290                         break;
1291                 case BGE_RESET_STOP:
1292                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1293                         break;
1294                 }
1295         }
1296 }
1297
1298 static void
1299 bge_sig_post_reset(sc, type)
1300         struct bge_softc *sc;
1301         int type;
1302 {
1303         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1304                 switch (type) {
1305                 case BGE_RESET_START:
1306                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001);
1307                         /* START DONE */
1308                         break;
1309                 case BGE_RESET_STOP:
1310                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002);
1311                         break;
1312                 }
1313         }
1314 }
1315
1316 static void
1317 bge_sig_legacy(sc, type)
1318         struct bge_softc *sc;
1319         int type;
1320 {
1321         if (sc->bge_asf_mode) {
1322                 switch (type) {
1323                 case BGE_RESET_START:
1324                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1325                         break;
1326                 case BGE_RESET_STOP:
1327                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1328                         break;
1329                 }
1330         }
1331 }
1332
1333 void bge_stop_fw(struct bge_softc *);
1334 void
1335 bge_stop_fw(sc)
1336         struct bge_softc *sc;
1337 {
1338         int i;
1339
1340         if (sc->bge_asf_mode) {
1341                 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE);
1342                 CSR_WRITE_4(sc, BGE_CPU_EVENT,
1343                     CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
1344
1345                 for (i = 0; i < 100; i++ ) {
1346                         if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14)))
1347                                 break;
1348                         DELAY(10);
1349                 }
1350         }
1351 }
1352
1353 /*
1354  * Do endian, PCI and DMA initialization.
1355  */
1356 static int
1357 bge_chipinit(struct bge_softc *sc)
1358 {
1359         uint32_t dma_rw_ctl;
1360         int i;
1361
1362         /* Set endianness before we access any non-PCI registers. */
1363         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1364
1365         /* Clear the MAC control register */
1366         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1367
1368         /*
1369          * Clear the MAC statistics block in the NIC's
1370          * internal memory.
1371          */
1372         for (i = BGE_STATS_BLOCK;
1373             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1374                 BGE_MEMWIN_WRITE(sc, i, 0);
1375
1376         for (i = BGE_STATUS_BLOCK;
1377             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1378                 BGE_MEMWIN_WRITE(sc, i, 0);
1379
1380         /*
1381          * Set up the PCI DMA control register.
1382          */
1383         dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1384             BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1385         if (sc->bge_flags & BGE_FLAG_PCIE) {
1386                 /* Read watermark not used, 128 bytes for write. */
1387                 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1388         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1389                 if (BGE_IS_5714_FAMILY(sc)) {
1390                         /* 256 bytes for read and write. */
1391                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1392                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1393                         dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1394                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1395                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1396                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1397                         /* 1536 bytes for read, 384 bytes for write. */
1398                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1399                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1400                 } else {
1401                         /* 384 bytes for read and write. */
1402                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1403                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1404                             0x0F;
1405                 }
1406                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1407                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1408                         uint32_t tmp;
1409
1410                         /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1411                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1412                         if (tmp == 6 || tmp == 7)
1413                                 dma_rw_ctl |=
1414                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1415
1416                         /* Set PCI-X DMA write workaround. */
1417                         dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1418                 }
1419         } else {
1420                 /* Conventional PCI bus: 256 bytes for read and write. */
1421                 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1422                     BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1423
1424                 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1425                     sc->bge_asicrev != BGE_ASICREV_BCM5750)
1426                         dma_rw_ctl |= 0x0F;
1427         }
1428         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1429             sc->bge_asicrev == BGE_ASICREV_BCM5701)
1430                 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1431                     BGE_PCIDMARWCTL_ASRT_ALL_BE;
1432         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1433             sc->bge_asicrev == BGE_ASICREV_BCM5704)
1434                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1435         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1436
1437         /*
1438          * Set up general mode register.
1439          */
1440         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
1441             BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1442             BGE_MODECTL_TX_NO_PHDR_CSUM);
1443
1444         /*
1445          * BCM5701 B5 have a bug causing data corruption when using
1446          * 64-bit DMA reads, which can be terminated early and then
1447          * completed later as 32-bit accesses, in combination with
1448          * certain bridges.
1449          */
1450         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1451             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1452                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1453
1454         /*
1455          * Tell the firmware the driver is running
1456          */
1457         if (sc->bge_asf_mode & ASF_STACKUP)
1458                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
1459
1460         /*
1461          * Disable memory write invalidate.  Apparently it is not supported
1462          * properly by these devices.  Also ensure that INTx isn't disabled,
1463          * as these chips need it even when using MSI.
1464          */
1465         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1466             PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
1467
1468         /* Set the timer prescaler (always 66Mhz) */
1469         CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1470
1471         /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1472         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1473                 DELAY(40);      /* XXX */
1474
1475                 /* Put PHY into ready state */
1476                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1477                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1478                 DELAY(40);
1479         }
1480
1481         return (0);
1482 }
1483
1484 static int
1485 bge_blockinit(struct bge_softc *sc)
1486 {
1487         struct bge_rcb *rcb;
1488         bus_size_t vrcb;
1489         bge_hostaddr taddr;
1490         uint32_t val;
1491         int i;
1492
1493         /*
1494          * Initialize the memory window pointer register so that
1495          * we can access the first 32K of internal NIC RAM. This will
1496          * allow us to set up the TX send ring RCBs and the RX return
1497          * ring RCBs, plus other things which live in NIC memory.
1498          */
1499         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1500
1501         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1502
1503         if (!(BGE_IS_5705_PLUS(sc))) {
1504                 /* Configure mbuf memory pool */
1505                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1506                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1507                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1508                 else
1509                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1510
1511                 /* Configure DMA resource pool */
1512                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1513                     BGE_DMA_DESCRIPTORS);
1514                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1515         }
1516
1517         /* Configure mbuf pool watermarks */
1518         if (!BGE_IS_5705_PLUS(sc)) {
1519                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1520                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1521                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1522         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1523                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1524                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1525                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1526         } else {
1527                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1528                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1529                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1530         }
1531
1532         /* Configure DMA resource watermarks */
1533         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1534         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1535
1536         /* Enable buffer manager */
1537         if (!(BGE_IS_5705_PLUS(sc))) {
1538                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1539                     BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN);
1540
1541                 /* Poll for buffer manager start indication */
1542                 for (i = 0; i < BGE_TIMEOUT; i++) {
1543                         DELAY(10);
1544                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1545                                 break;
1546                 }
1547
1548                 if (i == BGE_TIMEOUT) {
1549                         device_printf(sc->bge_dev,
1550                             "buffer manager failed to start\n");
1551                         return (ENXIO);
1552                 }
1553         }
1554
1555         /* Enable flow-through queues */
1556         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1557         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1558
1559         /* Wait until queue initialization is complete */
1560         for (i = 0; i < BGE_TIMEOUT; i++) {
1561                 DELAY(10);
1562                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1563                         break;
1564         }
1565
1566         if (i == BGE_TIMEOUT) {
1567                 device_printf(sc->bge_dev, "flow-through queue init failed\n");
1568                 return (ENXIO);
1569         }
1570
1571         /* Initialize the standard RX ring control block */
1572         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1573         rcb->bge_hostaddr.bge_addr_lo =
1574             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1575         rcb->bge_hostaddr.bge_addr_hi =
1576             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1577         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1578             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1579         if (BGE_IS_5705_PLUS(sc))
1580                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1581         else
1582                 rcb->bge_maxlen_flags =
1583                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1584         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1585         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1586         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1587
1588         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1589         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1590
1591         /*
1592          * Initialize the jumbo RX ring control block
1593          * We set the 'ring disabled' bit in the flags
1594          * field until we're actually ready to start
1595          * using this ring (i.e. once we set the MTU
1596          * high enough to require it).
1597          */
1598         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1599                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1600
1601                 rcb->bge_hostaddr.bge_addr_lo =
1602                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1603                 rcb->bge_hostaddr.bge_addr_hi =
1604                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1605                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1606                     sc->bge_cdata.bge_rx_jumbo_ring_map,
1607                     BUS_DMASYNC_PREREAD);
1608                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1609                     BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1610                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1611                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1612                     rcb->bge_hostaddr.bge_addr_hi);
1613                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1614                     rcb->bge_hostaddr.bge_addr_lo);
1615
1616                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1617                     rcb->bge_maxlen_flags);
1618                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1619
1620                 /* Set up dummy disabled mini ring RCB */
1621                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1622                 rcb->bge_maxlen_flags =
1623                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1624                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1625                     rcb->bge_maxlen_flags);
1626         }
1627
1628         /*
1629          * Set the BD ring replentish thresholds. The recommended
1630          * values are 1/8th the number of descriptors allocated to
1631          * each ring.
1632          * XXX The 5754 requires a lower threshold, so it might be a
1633          * requirement of all 575x family chips.  The Linux driver sets
1634          * the lower threshold for all 5705 family chips as well, but there
1635          * are reports that it might not need to be so strict.
1636          *
1637          * XXX Linux does some extra fiddling here for the 5906 parts as
1638          * well.
1639          */
1640         if (BGE_IS_5705_PLUS(sc))
1641                 val = 8;
1642         else
1643                 val = BGE_STD_RX_RING_CNT / 8;
1644         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1645         CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1646
1647         /*
1648          * Disable all unused send rings by setting the 'ring disabled'
1649          * bit in the flags field of all the TX send ring control blocks.
1650          * These are located in NIC memory.
1651          */
1652         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1653         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1654                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1655                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1656                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1657                 vrcb += sizeof(struct bge_rcb);
1658         }
1659
1660         /* Configure TX RCB 0 (we use only the first ring) */
1661         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1662         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1663         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1664         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1665         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1666             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1667         if (!(BGE_IS_5705_PLUS(sc)))
1668                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1669                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1670
1671         /* Disable all unused RX return rings */
1672         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1673         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1674                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1675                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1676                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1677                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1678                     BGE_RCB_FLAG_RING_DISABLED));
1679                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1680                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1681                     (i * (sizeof(uint64_t))), 0);
1682                 vrcb += sizeof(struct bge_rcb);
1683         }
1684
1685         /* Initialize RX ring indexes */
1686         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1687         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1688         bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1689
1690         /*
1691          * Set up RX return ring 0
1692          * Note that the NIC address for RX return rings is 0x00000000.
1693          * The return rings live entirely within the host, so the
1694          * nicaddr field in the RCB isn't used.
1695          */
1696         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1697         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1698         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1699         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1700         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1701         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1702             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1703
1704         /* Set random backoff seed for TX */
1705         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1706             IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1707             IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1708             IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1709             BGE_TX_BACKOFF_SEED_MASK);
1710
1711         /* Set inter-packet gap */
1712         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1713
1714         /*
1715          * Specify which ring to use for packets that don't match
1716          * any RX rules.
1717          */
1718         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1719
1720         /*
1721          * Configure number of RX lists. One interrupt distribution
1722          * list, sixteen active lists, one bad frames class.
1723          */
1724         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1725
1726         /* Inialize RX list placement stats mask. */
1727         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1728         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1729
1730         /* Disable host coalescing until we get it set up */
1731         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1732
1733         /* Poll to make sure it's shut down. */
1734         for (i = 0; i < BGE_TIMEOUT; i++) {
1735                 DELAY(10);
1736                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1737                         break;
1738         }
1739
1740         if (i == BGE_TIMEOUT) {
1741                 device_printf(sc->bge_dev,
1742                     "host coalescing engine failed to idle\n");
1743                 return (ENXIO);
1744         }
1745
1746         /* Set up host coalescing defaults */
1747         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1748         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1749         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1750         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1751         if (!(BGE_IS_5705_PLUS(sc))) {
1752                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1753                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1754         }
1755         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1756         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1757
1758         /* Set up address of statistics block */
1759         if (!(BGE_IS_5705_PLUS(sc))) {
1760                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1761                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1762                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1763                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1764                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1765                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1766                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1767         }
1768
1769         /* Set up address of status block */
1770         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1771             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1772         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1773             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1774         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1775         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1776
1777         /* Set up status block size. */
1778         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1779             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
1780                 val = BGE_STATBLKSZ_FULL;
1781         else
1782                 val = BGE_STATBLKSZ_32BYTE;
1783
1784         /* Turn on host coalescing state machine */
1785         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1786
1787         /* Turn on RX BD completion state machine and enable attentions */
1788         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1789             BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
1790
1791         /* Turn on RX list placement state machine */
1792         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1793
1794         /* Turn on RX list selector state machine. */
1795         if (!(BGE_IS_5705_PLUS(sc)))
1796                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1797
1798         /* Turn on DMA, clear stats */
1799         CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB |
1800             BGE_MACMODE_RXDMA_ENB | BGE_MACMODE_RX_STATS_CLEAR |
1801             BGE_MACMODE_TX_STATS_CLEAR | BGE_MACMODE_RX_STATS_ENB |
1802             BGE_MACMODE_TX_STATS_ENB | BGE_MACMODE_FRMHDR_DMA_ENB |
1803             ((sc->bge_flags & BGE_FLAG_TBI) ?
1804             BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1805
1806         /* Set misc. local control, enable interrupts on attentions */
1807         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1808
1809 #ifdef notdef
1810         /* Assert GPIO pins for PHY reset */
1811         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
1812             BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
1813         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
1814             BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
1815 #endif
1816
1817         /* Turn on DMA completion state machine */
1818         if (!(BGE_IS_5705_PLUS(sc)))
1819                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1820
1821         val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
1822
1823         /* Enable host coalescing bug fix. */
1824         if (BGE_IS_5755_PLUS(sc))
1825                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1826
1827         /* Turn on write DMA state machine */
1828         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1829         DELAY(40);
1830
1831         /* Turn on read DMA state machine */
1832         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1833         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1834             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1835             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1836                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1837                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1838                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1839         if (sc->bge_flags & BGE_FLAG_PCIE)
1840                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1841         if (sc->bge_flags & BGE_FLAG_TSO)
1842                 val |= BGE_RDMAMODE_TSO4_ENABLE;
1843         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1844         DELAY(40);
1845
1846         /* Turn on RX data completion state machine */
1847         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1848
1849         /* Turn on RX BD initiator state machine */
1850         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1851
1852         /* Turn on RX data and RX BD initiator state machine */
1853         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1854
1855         /* Turn on Mbuf cluster free state machine */
1856         if (!(BGE_IS_5705_PLUS(sc)))
1857                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1858
1859         /* Turn on send BD completion state machine */
1860         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1861
1862         /* Turn on send data completion state machine */
1863         val = BGE_SDCMODE_ENABLE;
1864         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1865                 val |= BGE_SDCMODE_CDELAY;
1866         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1867
1868         /* Turn on send data initiator state machine */
1869         if (sc->bge_flags & BGE_FLAG_TSO)
1870                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08);
1871         else
1872                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1873
1874         /* Turn on send BD initiator state machine */
1875         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1876
1877         /* Turn on send BD selector state machine */
1878         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1879
1880         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1881         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1882             BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
1883
1884         /* ack/clear link change events */
1885         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1886             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1887             BGE_MACSTAT_LINK_CHANGED);
1888         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1889
1890         /* Enable PHY auto polling (for MII/GMII only) */
1891         if (sc->bge_flags & BGE_FLAG_TBI) {
1892                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1893         } else {
1894                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16));
1895                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1896                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
1897                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1898                             BGE_EVTENB_MI_INTERRUPT);
1899         }
1900
1901         /*
1902          * Clear any pending link state attention.
1903          * Otherwise some link state change events may be lost until attention
1904          * is cleared by bge_intr() -> bge_link_upd() sequence.
1905          * It's not necessary on newer BCM chips - perhaps enabling link
1906          * state change attentions implies clearing pending attention.
1907          */
1908         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1909             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1910             BGE_MACSTAT_LINK_CHANGED);
1911
1912         /* Enable link state change attentions. */
1913         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1914
1915         return (0);
1916 }
1917
1918 const struct bge_revision *
1919 bge_lookup_rev(uint32_t chipid)
1920 {
1921         const struct bge_revision *br;
1922
1923         for (br = bge_revisions; br->br_name != NULL; br++) {
1924                 if (br->br_chipid == chipid)
1925                         return (br);
1926         }
1927
1928         for (br = bge_majorrevs; br->br_name != NULL; br++) {
1929                 if (br->br_chipid == BGE_ASICREV(chipid))
1930                         return (br);
1931         }
1932
1933         return (NULL);
1934 }
1935
1936 const struct bge_vendor *
1937 bge_lookup_vendor(uint16_t vid)
1938 {
1939         const struct bge_vendor *v;
1940
1941         for (v = bge_vendors; v->v_name != NULL; v++)
1942                 if (v->v_id == vid)
1943                         return (v);
1944
1945         panic("%s: unknown vendor %d", __func__, vid);
1946         return (NULL);
1947 }
1948
1949 /*
1950  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1951  * against our list and return its name if we find a match.
1952  *
1953  * Note that since the Broadcom controller contains VPD support, we
1954  * try to get the device name string from the controller itself instead
1955  * of the compiled-in string. It guarantees we'll always announce the
1956  * right product name. We fall back to the compiled-in string when
1957  * VPD is unavailable or corrupt.
1958  */
1959 static int
1960 bge_probe(device_t dev)
1961 {
1962         const struct bge_type *t = bge_devs;
1963         struct bge_softc *sc = device_get_softc(dev);
1964         uint16_t vid, did;
1965
1966         sc->bge_dev = dev;
1967         vid = pci_get_vendor(dev);
1968         did = pci_get_device(dev);
1969         while(t->bge_vid != 0) {
1970                 if ((vid == t->bge_vid) && (did == t->bge_did)) {
1971                         char model[64], buf[96];
1972                         const struct bge_revision *br;
1973                         const struct bge_vendor *v;
1974                         uint32_t id;
1975
1976                         id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1977                             BGE_PCIMISCCTL_ASICREV_SHIFT;
1978                         if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG)
1979                                 id = pci_read_config(dev,
1980                                     BGE_PCI_PRODID_ASICREV, 4);
1981                         br = bge_lookup_rev(id);
1982                         v = bge_lookup_vendor(vid);
1983                         {
1984 #if __FreeBSD_version > 700024
1985                                 const char *pname;
1986
1987                                 if (bge_has_eaddr(sc) &&
1988                                     pci_get_vpd_ident(dev, &pname) == 0)
1989                                         snprintf(model, 64, "%s", pname);
1990                                 else
1991 #endif
1992                                         snprintf(model, 64, "%s %s",
1993                                             v->v_name,
1994                                             br != NULL ? br->br_name :
1995                                             "NetXtreme Ethernet Controller");
1996                         }
1997                         snprintf(buf, 96, "%s, %sASIC rev. %#08x", model,
1998                             br != NULL ? "" : "unknown ", id);
1999                         device_set_desc_copy(dev, buf);
2000                         if (pci_get_subvendor(dev) == DELL_VENDORID)
2001                                 sc->bge_flags |= BGE_FLAG_NO_3LED;
2002                         if (did == BCOM_DEVICEID_BCM5755M)
2003                                 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
2004                         return (0);
2005                 }
2006                 t++;
2007         }
2008
2009         return (ENXIO);
2010 }
2011
2012 static void
2013 bge_dma_free(struct bge_softc *sc)
2014 {
2015         int i;
2016
2017         /* Destroy DMA maps for RX buffers. */
2018         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2019                 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2020                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2021                             sc->bge_cdata.bge_rx_std_dmamap[i]);
2022         }
2023         if (sc->bge_cdata.bge_rx_std_sparemap)
2024                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2025                     sc->bge_cdata.bge_rx_std_sparemap);
2026
2027         /* Destroy DMA maps for jumbo RX buffers. */
2028         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2029                 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2030                         bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2031                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2032         }
2033         if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2034                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2035                     sc->bge_cdata.bge_rx_jumbo_sparemap);
2036
2037         /* Destroy DMA maps for TX buffers. */
2038         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2039                 if (sc->bge_cdata.bge_tx_dmamap[i])
2040                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2041                             sc->bge_cdata.bge_tx_dmamap[i]);
2042         }
2043
2044         if (sc->bge_cdata.bge_rx_mtag)
2045                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2046         if (sc->bge_cdata.bge_tx_mtag)
2047                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2048
2049
2050         /* Destroy standard RX ring. */
2051         if (sc->bge_cdata.bge_rx_std_ring_map)
2052                 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2053                     sc->bge_cdata.bge_rx_std_ring_map);
2054         if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
2055                 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2056                     sc->bge_ldata.bge_rx_std_ring,
2057                     sc->bge_cdata.bge_rx_std_ring_map);
2058
2059         if (sc->bge_cdata.bge_rx_std_ring_tag)
2060                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2061
2062         /* Destroy jumbo RX ring. */
2063         if (sc->bge_cdata.bge_rx_jumbo_ring_map)
2064                 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2065                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2066
2067         if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
2068             sc->bge_ldata.bge_rx_jumbo_ring)
2069                 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2070                     sc->bge_ldata.bge_rx_jumbo_ring,
2071                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2072
2073         if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2074                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2075
2076         /* Destroy RX return ring. */
2077         if (sc->bge_cdata.bge_rx_return_ring_map)
2078                 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2079                     sc->bge_cdata.bge_rx_return_ring_map);
2080
2081         if (sc->bge_cdata.bge_rx_return_ring_map &&
2082             sc->bge_ldata.bge_rx_return_ring)
2083                 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2084                     sc->bge_ldata.bge_rx_return_ring,
2085                     sc->bge_cdata.bge_rx_return_ring_map);
2086
2087         if (sc->bge_cdata.bge_rx_return_ring_tag)
2088                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2089
2090         /* Destroy TX ring. */
2091         if (sc->bge_cdata.bge_tx_ring_map)
2092                 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2093                     sc->bge_cdata.bge_tx_ring_map);
2094
2095         if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
2096                 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2097                     sc->bge_ldata.bge_tx_ring,
2098                     sc->bge_cdata.bge_tx_ring_map);
2099
2100         if (sc->bge_cdata.bge_tx_ring_tag)
2101                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2102
2103         /* Destroy status block. */
2104         if (sc->bge_cdata.bge_status_map)
2105                 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2106                     sc->bge_cdata.bge_status_map);
2107
2108         if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
2109                 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2110                     sc->bge_ldata.bge_status_block,
2111                     sc->bge_cdata.bge_status_map);
2112
2113         if (sc->bge_cdata.bge_status_tag)
2114                 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2115
2116         /* Destroy statistics block. */
2117         if (sc->bge_cdata.bge_stats_map)
2118                 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2119                     sc->bge_cdata.bge_stats_map);
2120
2121         if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2122                 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2123                     sc->bge_ldata.bge_stats,
2124                     sc->bge_cdata.bge_stats_map);
2125
2126         if (sc->bge_cdata.bge_stats_tag)
2127                 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2128
2129         /* Destroy the parent tag. */
2130         if (sc->bge_cdata.bge_parent_tag)
2131                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2132 }
2133
2134 static int
2135 bge_dma_alloc(device_t dev)
2136 {
2137         struct bge_dmamap_arg ctx;
2138         struct bge_softc *sc;
2139         bus_addr_t lowaddr;
2140         bus_size_t sbsz, txsegsz, txmaxsegsz;
2141         int i, error;
2142
2143         sc = device_get_softc(dev);
2144
2145         lowaddr = BUS_SPACE_MAXADDR;
2146         if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2147                 lowaddr = BGE_DMA_MAXADDR;
2148         if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0)
2149                 lowaddr = BUS_SPACE_MAXADDR_32BIT;
2150         /*
2151          * Allocate the parent bus DMA tag appropriate for PCI.
2152          */
2153         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2154             1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2155             NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2156             0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2157
2158         if (error != 0) {
2159                 device_printf(sc->bge_dev,
2160                     "could not allocate parent dma tag\n");
2161                 return (ENOMEM);
2162         }
2163
2164         /*
2165          * Create tag for Tx mbufs.
2166          */
2167         if (sc->bge_flags & BGE_FLAG_TSO) {
2168                 txsegsz = BGE_TSOSEG_SZ;
2169                 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
2170         } else {
2171                 txsegsz = MCLBYTES;
2172                 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
2173         }
2174         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1,
2175             0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2176             txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
2177             &sc->bge_cdata.bge_tx_mtag);
2178
2179         if (error) {
2180                 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
2181                 return (ENOMEM);
2182         }
2183
2184         /*
2185          * Create tag for Rx mbufs.
2186          */
2187         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
2188             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
2189             MCLBYTES, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
2190
2191         if (error) {
2192                 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
2193                 return (ENOMEM);
2194         }
2195
2196         /* Create DMA maps for RX buffers. */
2197         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2198             &sc->bge_cdata.bge_rx_std_sparemap);
2199         if (error) {
2200                 device_printf(sc->bge_dev,
2201                     "can't create spare DMA map for RX\n");
2202                 return (ENOMEM);
2203         }
2204         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2205                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2206                             &sc->bge_cdata.bge_rx_std_dmamap[i]);
2207                 if (error) {
2208                         device_printf(sc->bge_dev,
2209                             "can't create DMA map for RX\n");
2210                         return (ENOMEM);
2211                 }
2212         }
2213
2214         /* Create DMA maps for TX buffers. */
2215         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2216                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
2217                             &sc->bge_cdata.bge_tx_dmamap[i]);
2218                 if (error) {
2219                         device_printf(sc->bge_dev,
2220                             "can't create DMA map for TX\n");
2221                         return (ENOMEM);
2222                 }
2223         }
2224
2225         /* Create tag for standard RX ring. */
2226         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2227             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2228             NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0,
2229             NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag);
2230
2231         if (error) {
2232                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2233                 return (ENOMEM);
2234         }
2235
2236         /* Allocate DMA'able memory for standard RX ring. */
2237         error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag,
2238             (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT,
2239             &sc->bge_cdata.bge_rx_std_ring_map);
2240         if (error)
2241                 return (ENOMEM);
2242
2243         bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
2244
2245         /* Load the address of the standard RX ring. */
2246         ctx.bge_maxsegs = 1;
2247         ctx.sc = sc;
2248
2249         error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag,
2250             sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring,
2251             BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2252
2253         if (error)
2254                 return (ENOMEM);
2255
2256         sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr;
2257
2258         /* Create tags for jumbo mbufs. */
2259         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2260                 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2261                     1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2262                     NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
2263                     0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
2264                 if (error) {
2265                         device_printf(sc->bge_dev,
2266                             "could not allocate jumbo dma tag\n");
2267                         return (ENOMEM);
2268                 }
2269
2270                 /* Create tag for jumbo RX ring. */
2271                 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2272                     PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2273                     NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0,
2274                     NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag);
2275
2276                 if (error) {
2277                         device_printf(sc->bge_dev,
2278                             "could not allocate jumbo ring dma tag\n");
2279                         return (ENOMEM);
2280                 }
2281
2282                 /* Allocate DMA'able memory for jumbo RX ring. */
2283                 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2284                     (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
2285                     BUS_DMA_NOWAIT | BUS_DMA_ZERO,
2286                     &sc->bge_cdata.bge_rx_jumbo_ring_map);
2287                 if (error)
2288                         return (ENOMEM);
2289
2290                 /* Load the address of the jumbo RX ring. */
2291                 ctx.bge_maxsegs = 1;
2292                 ctx.sc = sc;
2293
2294                 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2295                     sc->bge_cdata.bge_rx_jumbo_ring_map,
2296                     sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ,
2297                     bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2298
2299                 if (error)
2300                         return (ENOMEM);
2301
2302                 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr;
2303
2304                 /* Create DMA maps for jumbo RX buffers. */
2305                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2306                     0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
2307                 if (error) {
2308                         device_printf(sc->bge_dev,
2309                             "can't create spare DMA map for jumbo RX\n");
2310                         return (ENOMEM);
2311                 }
2312                 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2313                         error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2314                                     0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2315                         if (error) {
2316                                 device_printf(sc->bge_dev,
2317                                     "can't create DMA map for jumbo RX\n");
2318                                 return (ENOMEM);
2319                         }
2320                 }
2321
2322         }
2323
2324         /* Create tag for RX return ring. */
2325         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2326             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2327             NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0,
2328             NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag);
2329
2330         if (error) {
2331                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2332                 return (ENOMEM);
2333         }
2334
2335         /* Allocate DMA'able memory for RX return ring. */
2336         error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag,
2337             (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT,
2338             &sc->bge_cdata.bge_rx_return_ring_map);
2339         if (error)
2340                 return (ENOMEM);
2341
2342         bzero((char *)sc->bge_ldata.bge_rx_return_ring,
2343             BGE_RX_RTN_RING_SZ(sc));
2344
2345         /* Load the address of the RX return ring. */
2346         ctx.bge_maxsegs = 1;
2347         ctx.sc = sc;
2348
2349         error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag,
2350             sc->bge_cdata.bge_rx_return_ring_map,
2351             sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc),
2352             bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2353
2354         if (error)
2355                 return (ENOMEM);
2356
2357         sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr;
2358
2359         /* Create tag for TX ring. */
2360         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2361             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2362             NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL,
2363             &sc->bge_cdata.bge_tx_ring_tag);
2364
2365         if (error) {
2366                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2367                 return (ENOMEM);
2368         }
2369
2370         /* Allocate DMA'able memory for TX ring. */
2371         error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag,
2372             (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT,
2373             &sc->bge_cdata.bge_tx_ring_map);
2374         if (error)
2375                 return (ENOMEM);
2376
2377         bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
2378
2379         /* Load the address of the TX ring. */
2380         ctx.bge_maxsegs = 1;
2381         ctx.sc = sc;
2382
2383         error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag,
2384             sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring,
2385             BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2386
2387         if (error)
2388                 return (ENOMEM);
2389
2390         sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr;
2391
2392         /*
2393          * Create tag for status block.
2394          * Because we only use single Tx/Rx/Rx return ring, use
2395          * minimum status block size except BCM5700 AX/BX which
2396          * seems to want to see full status block size regardless
2397          * of configured number of ring.
2398          */
2399         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2400             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
2401                 sbsz = BGE_STATUS_BLK_SZ;
2402         else
2403                 sbsz = 32;
2404         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2405             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2406             NULL, sbsz, 1, sbsz, 0, NULL, NULL, &sc->bge_cdata.bge_status_tag);
2407
2408         if (error) {
2409                 device_printf(sc->bge_dev,
2410                     "could not allocate status dma tag\n");
2411                 return (ENOMEM);
2412         }
2413
2414         /* Allocate DMA'able memory for status block. */
2415         error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag,
2416             (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT,
2417             &sc->bge_cdata.bge_status_map);
2418         if (error)
2419                 return (ENOMEM);
2420
2421         bzero((char *)sc->bge_ldata.bge_status_block, sbsz);
2422
2423         /* Load the address of the status block. */
2424         ctx.sc = sc;
2425         ctx.bge_maxsegs = 1;
2426
2427         error = bus_dmamap_load(sc->bge_cdata.bge_status_tag,
2428             sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block,
2429             sbsz, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2430
2431         if (error)
2432                 return (ENOMEM);
2433
2434         sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr;
2435
2436         /* Create tag for statistics block. */
2437         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2438             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2439             NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL,
2440             &sc->bge_cdata.bge_stats_tag);
2441
2442         if (error) {
2443                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2444                 return (ENOMEM);
2445         }
2446
2447         /* Allocate DMA'able memory for statistics block. */
2448         error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag,
2449             (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT,
2450             &sc->bge_cdata.bge_stats_map);
2451         if (error)
2452                 return (ENOMEM);
2453
2454         bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ);
2455
2456         /* Load the address of the statstics block. */
2457         ctx.sc = sc;
2458         ctx.bge_maxsegs = 1;
2459
2460         error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag,
2461             sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats,
2462             BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2463
2464         if (error)
2465                 return (ENOMEM);
2466
2467         sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr;
2468
2469         return (0);
2470 }
2471
2472 /*
2473  * Return true if this device has more than one port.
2474  */
2475 static int
2476 bge_has_multiple_ports(struct bge_softc *sc)
2477 {
2478         device_t dev = sc->bge_dev;
2479         u_int b, d, f, fscan, s;
2480
2481         d = pci_get_domain(dev);
2482         b = pci_get_bus(dev);
2483         s = pci_get_slot(dev);
2484         f = pci_get_function(dev);
2485         for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
2486                 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
2487                         return (1);
2488         return (0);
2489 }
2490
2491 /*
2492  * Return true if MSI can be used with this device.
2493  */
2494 static int
2495 bge_can_use_msi(struct bge_softc *sc)
2496 {
2497         int can_use_msi = 0;
2498
2499         switch (sc->bge_asicrev) {
2500         case BGE_ASICREV_BCM5714_A0:
2501         case BGE_ASICREV_BCM5714:
2502                 /*
2503                  * Apparently, MSI doesn't work when these chips are
2504                  * configured in single-port mode.
2505                  */
2506                 if (bge_has_multiple_ports(sc))
2507                         can_use_msi = 1;
2508                 break;
2509         case BGE_ASICREV_BCM5750:
2510                 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
2511                     sc->bge_chiprev != BGE_CHIPREV_5750_BX)
2512                         can_use_msi = 1;
2513                 break;
2514         default:
2515                 if (BGE_IS_575X_PLUS(sc))
2516                         can_use_msi = 1;
2517         }
2518         return (can_use_msi);
2519 }
2520
2521 static int
2522 bge_attach(device_t dev)
2523 {
2524         struct ifnet *ifp;
2525         struct bge_softc *sc;
2526         uint32_t hwcfg = 0, misccfg;
2527         u_char eaddr[ETHER_ADDR_LEN];
2528         int error, msicount, reg, rid, trys;
2529
2530         sc = device_get_softc(dev);
2531         sc->bge_dev = dev;
2532
2533         TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
2534
2535         /*
2536          * Map control/status registers.
2537          */
2538         pci_enable_busmaster(dev);
2539
2540         rid = BGE_PCI_BAR0;
2541         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2542             RF_ACTIVE);
2543
2544         if (sc->bge_res == NULL) {
2545                 device_printf (sc->bge_dev, "couldn't map memory\n");
2546                 error = ENXIO;
2547                 goto fail;
2548         }
2549
2550         /* Save various chip information. */
2551         sc->bge_chipid =
2552             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2553             BGE_PCIMISCCTL_ASICREV_SHIFT;
2554         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
2555                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV,
2556                     4);
2557         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2558         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2559
2560         /*
2561          * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the
2562          * 5705 A0 and A1 chips.
2563          */
2564         if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
2565             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2566             sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2567             sc->bge_chipid != BGE_CHIPID_BCM5705_A1)
2568                 sc->bge_flags |= BGE_FLAG_WIRESPEED;
2569
2570         if (bge_has_eaddr(sc))
2571                 sc->bge_flags |= BGE_FLAG_EADDR;
2572
2573         /* Save chipset family. */
2574         switch (sc->bge_asicrev) {
2575         case BGE_ASICREV_BCM5755:
2576         case BGE_ASICREV_BCM5761:
2577         case BGE_ASICREV_BCM5784:
2578         case BGE_ASICREV_BCM5785:
2579         case BGE_ASICREV_BCM5787:
2580         case BGE_ASICREV_BCM57780:
2581                 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2582                     BGE_FLAG_5705_PLUS;
2583                 break;
2584         case BGE_ASICREV_BCM5700:
2585         case BGE_ASICREV_BCM5701:
2586         case BGE_ASICREV_BCM5703:
2587         case BGE_ASICREV_BCM5704:
2588                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2589                 break;
2590         case BGE_ASICREV_BCM5714_A0:
2591         case BGE_ASICREV_BCM5780:
2592         case BGE_ASICREV_BCM5714:
2593                 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */;
2594                 /* FALLTHROUGH */
2595         case BGE_ASICREV_BCM5750:
2596         case BGE_ASICREV_BCM5752:
2597         case BGE_ASICREV_BCM5906:
2598                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2599                 /* FALLTHROUGH */
2600         case BGE_ASICREV_BCM5705:
2601                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2602                 break;
2603         }
2604
2605         /* Set various bug flags. */
2606         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2607             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2608                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
2609         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2610             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2611                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
2612         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2613                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
2614         if (BGE_IS_5705_PLUS(sc) &&
2615             !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) {
2616                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2617                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2618                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2619                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2620                         if (sc->bge_chipid != BGE_CHIPID_BCM5722_A0)
2621                                 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
2622                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
2623                         sc->bge_flags |= BGE_FLAG_BER_BUG;
2624         }
2625
2626         /*
2627          * All controllers that are not 5755 or higher have 4GB
2628          * boundary DMA bug.
2629          * Whenever an address crosses a multiple of the 4GB boundary
2630          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
2631          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
2632          * state machine will lockup and cause the device to hang.
2633          */
2634         if (BGE_IS_5755_PLUS(sc) == 0)
2635                 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
2636
2637         /*
2638          * We could possibly check for BCOM_DEVICEID_BCM5788 in bge_probe()
2639          * but I do not know the DEVICEID for the 5788M.
2640          */
2641         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID;
2642         if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2643             misccfg == BGE_MISCCFG_BOARD_ID_5788M)
2644                 sc->bge_flags |= BGE_FLAG_5788;
2645
2646         /*
2647          * Some controllers seem to require a special firmware to use
2648          * TSO. But the firmware is not available to FreeBSD and Linux
2649          * claims that the TSO performed by the firmware is slower than
2650          * hardware based TSO. Moreover the firmware based TSO has one
2651          * known bug which can't handle TSO if ethernet header + IP/TCP
2652          * header is greater than 80 bytes. The workaround for the TSO
2653          * bug exist but it seems it's too expensive than not using
2654          * TSO at all. Some hardwares also have the TSO bug so limit
2655          * the TSO to the controllers that are not affected TSO issues
2656          * (e.g. 5755 or higher).
2657          */
2658         if (BGE_IS_5755_PLUS(sc))
2659                 sc->bge_flags |= BGE_FLAG_TSO;
2660
2661         /*
2662          * Check if this is a PCI-X or PCI Express device.
2663          */
2664         if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {
2665                 /*
2666                  * Found a PCI Express capabilities register, this
2667                  * must be a PCI Express device.
2668                  */
2669                 sc->bge_flags |= BGE_FLAG_PCIE;
2670                 sc->bge_expcap = reg;
2671                 bge_set_max_readrq(sc);
2672         } else {
2673                 /*
2674                  * Check if the device is in PCI-X Mode.
2675                  * (This bit is not valid on PCI Express controllers.)
2676                  */
2677                 if (pci_find_extcap(dev, PCIY_PCIX, &reg) == 0)
2678                         sc->bge_pcixcap = reg;
2679                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
2680                     BGE_PCISTATE_PCI_BUSMODE) == 0)
2681                         sc->bge_flags |= BGE_FLAG_PCIX;
2682         }
2683
2684         /*
2685          * The 40bit DMA bug applies to the 5714/5715 controllers and is
2686          * not actually a MAC controller bug but an issue with the embedded
2687          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2688          */
2689         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
2690                 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
2691         /*
2692          * Allocate the interrupt, using MSI if possible.  These devices
2693          * support 8 MSI messages, but only the first one is used in
2694          * normal operation.
2695          */
2696         rid = 0;
2697         if (pci_find_extcap(sc->bge_dev, PCIY_MSI, &reg) == 0) {
2698                 sc->bge_msicap = reg;
2699                 if (bge_can_use_msi(sc)) {
2700                         msicount = pci_msi_count(dev);
2701                         if (msicount > 1)
2702                                 msicount = 1;
2703                 } else
2704                         msicount = 0;
2705                 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
2706                         rid = 1;
2707                         sc->bge_flags |= BGE_FLAG_MSI;
2708                 }
2709         }
2710
2711         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2712             RF_SHAREABLE | RF_ACTIVE);
2713
2714         if (sc->bge_irq == NULL) {
2715                 device_printf(sc->bge_dev, "couldn't map interrupt\n");
2716                 error = ENXIO;
2717                 goto fail;
2718         }
2719
2720         if (bootverbose)
2721                 device_printf(dev,
2722                     "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2723                     sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2724                     (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" :
2725                     ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI"));
2726
2727         BGE_LOCK_INIT(sc, device_get_nameunit(dev));
2728
2729         /* Try to reset the chip. */
2730         if (bge_reset(sc)) {
2731                 device_printf(sc->bge_dev, "chip reset failed\n");
2732                 error = ENXIO;
2733                 goto fail;
2734         }
2735
2736         sc->bge_asf_mode = 0;
2737         if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG)
2738             == BGE_MAGIC_NUMBER)) {
2739                 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG)
2740                     & BGE_HWCFG_ASF) {
2741                         sc->bge_asf_mode |= ASF_ENABLE;
2742                         sc->bge_asf_mode |= ASF_STACKUP;
2743                         if (sc->bge_asicrev == BGE_ASICREV_BCM5750) {
2744                                 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
2745                         }
2746                 }
2747         }
2748
2749         /* Try to reset the chip again the nice way. */
2750         bge_stop_fw(sc);
2751         bge_sig_pre_reset(sc, BGE_RESET_STOP);
2752         if (bge_reset(sc)) {
2753                 device_printf(sc->bge_dev, "chip reset failed\n");
2754                 error = ENXIO;
2755                 goto fail;
2756         }
2757
2758         bge_sig_legacy(sc, BGE_RESET_STOP);
2759         bge_sig_post_reset(sc, BGE_RESET_STOP);
2760
2761         if (bge_chipinit(sc)) {
2762                 device_printf(sc->bge_dev, "chip initialization failed\n");
2763                 error = ENXIO;
2764                 goto fail;
2765         }
2766
2767         error = bge_get_eaddr(sc, eaddr);
2768         if (error) {
2769                 device_printf(sc->bge_dev,
2770                     "failed to read station address\n");
2771                 error = ENXIO;
2772                 goto fail;
2773         }
2774
2775         /* 5705 limits RX return ring to 512 entries. */
2776         if (BGE_IS_5705_PLUS(sc))
2777                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2778         else
2779                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2780
2781         if (bge_dma_alloc(dev)) {
2782                 device_printf(sc->bge_dev,
2783                     "failed to allocate DMA resources\n");
2784                 error = ENXIO;
2785                 goto fail;
2786         }
2787
2788         /* Set default tuneable values. */
2789         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2790         sc->bge_rx_coal_ticks = 150;
2791         sc->bge_tx_coal_ticks = 150;
2792         sc->bge_rx_max_coal_bds = 10;
2793         sc->bge_tx_max_coal_bds = 10;
2794
2795         /* Set up ifnet structure */
2796         ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
2797         if (ifp == NULL) {
2798                 device_printf(sc->bge_dev, "failed to if_alloc()\n");
2799                 error = ENXIO;
2800                 goto fail;
2801         }
2802         ifp->if_softc = sc;
2803         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2804         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2805         ifp->if_ioctl = bge_ioctl;
2806         ifp->if_start = bge_start;
2807         ifp->if_init = bge_init;
2808         ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
2809         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2810         IFQ_SET_READY(&ifp->if_snd);
2811         ifp->if_hwassist = BGE_CSUM_FEATURES;
2812         ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
2813             IFCAP_VLAN_MTU;
2814         if ((sc->bge_flags & BGE_FLAG_TSO) != 0) {
2815                 ifp->if_hwassist |= CSUM_TSO;
2816                 ifp->if_capabilities |= IFCAP_TSO4;
2817         }
2818 #ifdef IFCAP_VLAN_HWCSUM
2819         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
2820 #endif
2821         ifp->if_capenable = ifp->if_capabilities;
2822 #ifdef DEVICE_POLLING
2823         ifp->if_capabilities |= IFCAP_POLLING;
2824 #endif
2825
2826         /*
2827          * 5700 B0 chips do not support checksumming correctly due
2828          * to hardware bugs.
2829          */
2830         if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
2831                 ifp->if_capabilities &= ~IFCAP_HWCSUM;
2832                 ifp->if_capenable &= ~IFCAP_HWCSUM;
2833                 ifp->if_hwassist = 0;
2834         }
2835
2836         /*
2837          * Figure out what sort of media we have by checking the
2838          * hardware config word in the first 32k of NIC internal memory,
2839          * or fall back to examining the EEPROM if necessary.
2840          * Note: on some BCM5700 cards, this value appears to be unset.
2841          * If that's the case, we have to rely on identifying the NIC
2842          * by its PCI subsystem ID, as we do below for the SysKonnect
2843          * SK-9D41.
2844          */
2845         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2846                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2847         else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
2848             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
2849                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2850                     sizeof(hwcfg))) {
2851                         device_printf(sc->bge_dev, "failed to read EEPROM\n");
2852                         error = ENXIO;
2853                         goto fail;
2854                 }
2855                 hwcfg = ntohl(hwcfg);
2856         }
2857
2858         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2859                 sc->bge_flags |= BGE_FLAG_TBI;
2860
2861         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2862         if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41)
2863                 sc->bge_flags |= BGE_FLAG_TBI;
2864
2865         if (sc->bge_flags & BGE_FLAG_TBI) {
2866                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
2867                     bge_ifmedia_sts);
2868                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
2869                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2870                     0, NULL);
2871                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
2872                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
2873                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2874         } else {
2875                 /*
2876                  * Do transceiver setup and tell the firmware the
2877                  * driver is down so we can try to get access the
2878                  * probe if ASF is running.  Retry a couple of times
2879                  * if we get a conflict with the ASF firmware accessing
2880                  * the PHY.
2881                  */
2882                 trys = 0;
2883                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2884 again:
2885                 bge_asf_driver_up(sc);
2886
2887                 if (mii_phy_probe(dev, &sc->bge_miibus,
2888                     bge_ifmedia_upd, bge_ifmedia_sts)) {
2889                         if (trys++ < 4) {
2890                                 device_printf(sc->bge_dev, "Try again\n");
2891                                 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR,
2892                                     BMCR_RESET);
2893                                 goto again;
2894                         }
2895
2896                         device_printf(sc->bge_dev, "MII without any PHY!\n");
2897                         error = ENXIO;
2898                         goto fail;
2899                 }
2900
2901                 /*
2902                  * Now tell the firmware we are going up after probing the PHY
2903                  */
2904                 if (sc->bge_asf_mode & ASF_STACKUP)
2905                         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2906         }
2907
2908         /*
2909          * When using the BCM5701 in PCI-X mode, data corruption has
2910          * been observed in the first few bytes of some received packets.
2911          * Aligning the packet buffer in memory eliminates the corruption.
2912          * Unfortunately, this misaligns the packet payloads.  On platforms
2913          * which do not support unaligned accesses, we will realign the
2914          * payloads by copying the received packets.
2915          */
2916         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2917             sc->bge_flags & BGE_FLAG_PCIX)
2918                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2919
2920         /*
2921          * Call MI attach routine.
2922          */
2923         ether_ifattach(ifp, eaddr);
2924         callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
2925
2926         /* Tell upper layer we support long frames. */
2927         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2928
2929         /*
2930          * Hookup IRQ last.
2931          */
2932 #if __FreeBSD_version > 700030
2933         if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
2934                 /* Take advantage of single-shot MSI. */
2935                 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
2936                     ~BGE_MSIMODE_ONE_SHOT_DISABLE);
2937                 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
2938                     taskqueue_thread_enqueue, &sc->bge_tq);
2939                 if (sc->bge_tq == NULL) {
2940                         device_printf(dev, "could not create taskqueue.\n");
2941                         ether_ifdetach(ifp);
2942                         error = ENXIO;
2943                         goto fail;
2944                 }
2945                 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq",
2946                     device_get_nameunit(sc->bge_dev));
2947                 error = bus_setup_intr(dev, sc->bge_irq,
2948                     INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
2949                     &sc->bge_intrhand);
2950                 if (error)
2951                         ether_ifdetach(ifp);
2952         } else
2953                 error = bus_setup_intr(dev, sc->bge_irq,
2954                     INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
2955                     &sc->bge_intrhand);
2956 #else
2957         error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2958            bge_intr, sc, &sc->bge_intrhand);
2959 #endif
2960
2961         if (error) {
2962                 bge_detach(dev);
2963                 device_printf(sc->bge_dev, "couldn't set up irq\n");
2964         }
2965
2966         bge_add_sysctls(sc);
2967
2968         return (0);
2969
2970 fail:
2971         bge_release_resources(sc);
2972
2973         return (error);
2974 }
2975
2976 static int
2977 bge_detach(device_t dev)
2978 {
2979         struct bge_softc *sc;
2980         struct ifnet *ifp;
2981
2982         sc = device_get_softc(dev);
2983         ifp = sc->bge_ifp;
2984
2985 #ifdef DEVICE_POLLING
2986         if (ifp->if_capenable & IFCAP_POLLING)
2987                 ether_poll_deregister(ifp);
2988 #endif
2989
2990         BGE_LOCK(sc);
2991         bge_stop(sc);
2992         bge_reset(sc);
2993         BGE_UNLOCK(sc);
2994
2995         callout_drain(&sc->bge_stat_ch);
2996
2997         if (sc->bge_tq)
2998                 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
2999         ether_ifdetach(ifp);
3000
3001         if (sc->bge_flags & BGE_FLAG_TBI) {
3002                 ifmedia_removeall(&sc->bge_ifmedia);
3003         } else {
3004                 bus_generic_detach(dev);
3005                 device_delete_child(dev, sc->bge_miibus);
3006         }
3007
3008         bge_release_resources(sc);
3009
3010         return (0);
3011 }
3012
3013 static void
3014 bge_release_resources(struct bge_softc *sc)
3015 {
3016         device_t dev;
3017
3018         dev = sc->bge_dev;
3019
3020         if (sc->bge_tq != NULL)
3021                 taskqueue_free(sc->bge_tq);
3022
3023         if (sc->bge_intrhand != NULL)
3024                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3025
3026         if (sc->bge_irq != NULL)
3027                 bus_release_resource(dev, SYS_RES_IRQ,
3028                     sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
3029
3030         if (sc->bge_flags & BGE_FLAG_MSI)
3031                 pci_release_msi(dev);
3032
3033         if (sc->bge_res != NULL)
3034                 bus_release_resource(dev, SYS_RES_MEMORY,
3035                     BGE_PCI_BAR0, sc->bge_res);
3036
3037         if (sc->bge_ifp != NULL)
3038                 if_free(sc->bge_ifp);
3039
3040         bge_dma_free(sc);
3041
3042         if (mtx_initialized(&sc->bge_mtx))      /* XXX */
3043                 BGE_LOCK_DESTROY(sc);
3044 }
3045
3046 static int
3047 bge_reset(struct bge_softc *sc)
3048 {
3049         device_t dev;
3050         uint32_t cachesize, command, pcistate, reset, val;
3051         void (*write_op)(struct bge_softc *, int, int);
3052         uint16_t devctl;
3053         int i;
3054
3055         dev = sc->bge_dev;
3056
3057         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
3058             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3059                 if (sc->bge_flags & BGE_FLAG_PCIE)
3060                         write_op = bge_writemem_direct;
3061                 else
3062                         write_op = bge_writemem_ind;
3063         } else
3064                 write_op = bge_writereg_ind;
3065
3066         /* Save some important PCI state. */
3067         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
3068         command = pci_read_config(dev, BGE_PCI_CMD, 4);
3069         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3070
3071         pci_write_config(dev, BGE_PCI_MISC_CTL,
3072             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3073             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3074
3075         /* Disable fastboot on controllers that support it. */
3076         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
3077             BGE_IS_5755_PLUS(sc)) {
3078                 if (bootverbose)
3079                         device_printf(sc->bge_dev, "Disabling fastboot\n");
3080                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
3081         }
3082
3083         /*
3084          * Write the magic number to SRAM at offset 0xB50.
3085          * When firmware finishes its initialization it will
3086          * write ~BGE_MAGIC_NUMBER to the same location.
3087          */
3088         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
3089
3090         reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
3091
3092         /* XXX: Broadcom Linux driver. */
3093         if (sc->bge_flags & BGE_FLAG_PCIE) {
3094                 if (CSR_READ_4(sc, 0x7E2C) == 0x60)     /* PCIE 1.0 */
3095                         CSR_WRITE_4(sc, 0x7E2C, 0x20);
3096                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3097                         /* Prevent PCIE link training during global reset */
3098                         CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
3099                         reset |= 1 << 29;
3100                 }
3101         }
3102
3103         /*
3104          * Set GPHY Power Down Override to leave GPHY
3105          * powered up in D0 uninitialized.
3106          */
3107         if (BGE_IS_5705_PLUS(sc))
3108                 reset |= 0x04000000;
3109
3110         /* Issue global reset */
3111         write_op(sc, BGE_MISC_CFG, reset);
3112
3113         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3114                 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3115                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
3116                     val | BGE_VCPU_STATUS_DRV_RESET);
3117                 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
3118                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
3119                     val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
3120         }
3121
3122         DELAY(1000);
3123
3124         /* XXX: Broadcom Linux driver. */
3125         if (sc->bge_flags & BGE_FLAG_PCIE) {
3126                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
3127                         DELAY(500000); /* wait for link training to complete */
3128                         val = pci_read_config(dev, 0xC4, 4);
3129                         pci_write_config(dev, 0xC4, val | (1 << 15), 4);
3130                 }
3131                 devctl = pci_read_config(dev,
3132                     sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
3133                 /* Clear enable no snoop and disable relaxed ordering. */
3134                 devctl &= ~(0x0010 | 0x0800);
3135                 /* Set PCIE max payload size to 128. */
3136                 devctl &= ~PCIM_EXP_CTL_MAX_PAYLOAD;
3137                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL,
3138                     devctl, 2);
3139                 /* Clear error status. */
3140                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA,
3141                     0, 2);
3142         }
3143
3144         /* Reset some of the PCI state that got zapped by reset. */
3145         pci_write_config(dev, BGE_PCI_MISC_CTL,
3146             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3147             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3148         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
3149         pci_write_config(dev, BGE_PCI_CMD, command, 4);
3150         write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
3151
3152         /* Re-enable MSI, if neccesary, and enable the memory arbiter. */
3153         if (BGE_IS_5714_FAMILY(sc)) {
3154                 /* This chip disables MSI on reset. */
3155                 if (sc->bge_flags & BGE_FLAG_MSI) {
3156                         val = pci_read_config(dev,
3157                             sc->bge_msicap + PCIR_MSI_CTRL, 2);
3158                         pci_write_config(dev,
3159                             sc->bge_msicap + PCIR_MSI_CTRL,
3160                             val | PCIM_MSICTRL_MSI_ENABLE, 2);
3161                         val = CSR_READ_4(sc, BGE_MSI_MODE);
3162                         CSR_WRITE_4(sc, BGE_MSI_MODE,
3163                             val | BGE_MSIMODE_ENABLE);
3164                 }
3165                 val = CSR_READ_4(sc, BGE_MARB_MODE);
3166                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
3167         } else
3168                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3169
3170         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3171                 for (i = 0; i < BGE_TIMEOUT; i++) {
3172                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3173                         if (val & BGE_VCPU_STATUS_INIT_DONE)
3174                                 break;
3175                         DELAY(100);
3176                 }
3177                 if (i == BGE_TIMEOUT) {
3178                         device_printf(sc->bge_dev, "reset timed out\n");
3179                         return (1);
3180                 }
3181         } else {
3182                 /*
3183                  * Poll until we see the 1's complement of the magic number.
3184                  * This indicates that the firmware initialization is complete.
3185                  * We expect this to fail if no chip containing the Ethernet
3186                  * address is fitted though.
3187                  */
3188                 for (i = 0; i < BGE_TIMEOUT; i++) {
3189                         DELAY(10);
3190                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
3191                         if (val == ~BGE_MAGIC_NUMBER)
3192                                 break;
3193                 }
3194
3195                 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
3196                         device_printf(sc->bge_dev, "firmware handshake timed out, "
3197                             "found 0x%08x\n", val);
3198         }
3199
3200         /*
3201          * XXX Wait for the value of the PCISTATE register to
3202          * return to its original pre-reset state. This is a
3203          * fairly good indicator of reset completion. If we don't
3204          * wait for the reset to fully complete, trying to read
3205          * from the device's non-PCI registers may yield garbage
3206          * results.
3207          */
3208         for (i = 0; i < BGE_TIMEOUT; i++) {
3209                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
3210                         break;
3211                 DELAY(10);
3212         }
3213
3214         if (sc->bge_flags & BGE_FLAG_PCIE) {
3215                 reset = bge_readmem_ind(sc, 0x7C00);
3216                 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25));
3217         }
3218
3219         /* Fix up byte swapping. */
3220         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
3221             BGE_MODECTL_BYTESWAP_DATA);
3222
3223         /* Tell the ASF firmware we are up */
3224         if (sc->bge_asf_mode & ASF_STACKUP)
3225                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3226
3227         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
3228
3229         /*
3230          * The 5704 in TBI mode apparently needs some special
3231          * adjustment to insure the SERDES drive level is set
3232          * to 1.2V.
3233          */
3234         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
3235             sc->bge_flags & BGE_FLAG_TBI) {
3236                 val = CSR_READ_4(sc, BGE_SERDES_CFG);
3237                 val = (val & ~0xFFF) | 0x880;
3238                 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
3239         }
3240
3241         /* XXX: Broadcom Linux driver. */
3242         if (sc->bge_flags & BGE_FLAG_PCIE &&
3243             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3244                 val = CSR_READ_4(sc, 0x7C00);
3245                 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
3246         }
3247         DELAY(10000);
3248
3249         return(0);
3250 }
3251
3252 /*
3253  * Frame reception handling. This is called if there's a frame
3254  * on the receive return list.
3255  *
3256  * Note: we have to be able to handle two possibilities here:
3257  * 1) the frame is from the jumbo receive ring
3258  * 2) the frame is from the standard receive ring
3259  */
3260
3261 static int
3262 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
3263 {
3264         struct ifnet *ifp;
3265         int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
3266         uint16_t rx_cons;
3267
3268         rx_cons = sc->bge_rx_saved_considx;
3269
3270         /* Nothing to do. */
3271         if (rx_cons == rx_prod)
3272                 return (rx_npkts);
3273
3274         ifp = sc->bge_ifp;
3275
3276         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3277             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
3278         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3279             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
3280         if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
3281             (MCLBYTES - ETHER_ALIGN))
3282                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3283                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
3284
3285         while (rx_cons != rx_prod) {
3286                 struct bge_rx_bd        *cur_rx;
3287                 uint32_t                rxidx;
3288                 struct mbuf             *m = NULL;
3289                 uint16_t                vlan_tag = 0;
3290                 int                     have_tag = 0;
3291
3292 #ifdef DEVICE_POLLING
3293                 if (ifp->if_capenable & IFCAP_POLLING) {
3294                         if (sc->rxcycles <= 0)
3295                                 break;
3296                         sc->rxcycles--;
3297                 }
3298 #endif
3299
3300                 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
3301
3302                 rxidx = cur_rx->bge_idx;
3303                 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
3304
3305                 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
3306                     cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
3307                         have_tag = 1;
3308                         vlan_tag = cur_rx->bge_vlan_tag;
3309                 }
3310
3311                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
3312                         jumbocnt++;
3313                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
3314                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3315                                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3316                                 continue;
3317                         }
3318                         if (bge_newbuf_jumbo(sc, rxidx) != 0) {
3319                                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3320                                 ifp->if_iqdrops++;
3321                                 continue;
3322                         }
3323                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3324                 } else {
3325                         stdcnt++;
3326                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3327                                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3328                                 continue;
3329                         }
3330                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
3331                         if (bge_newbuf_std(sc, rxidx) != 0) {
3332                                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3333                                 ifp->if_iqdrops++;
3334                                 continue;
3335                         }
3336                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3337                 }
3338
3339                 ifp->if_ipackets++;
3340 #ifndef __NO_STRICT_ALIGNMENT
3341                 /*
3342                  * For architectures with strict alignment we must make sure
3343                  * the payload is aligned.
3344                  */
3345                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
3346                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
3347                             cur_rx->bge_len);
3348                         m->m_data += ETHER_ALIGN;
3349                 }
3350 #endif
3351                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3352                 m->m_pkthdr.rcvif = ifp;
3353
3354                 if (ifp->if_capenable & IFCAP_RXCSUM) {
3355                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3356                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3357                                 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
3358                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3359                         }
3360                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
3361                             m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
3362                                 m->m_pkthdr.csum_data =
3363                                     cur_rx->bge_tcp_udp_csum;
3364                                 m->m_pkthdr.csum_flags |=
3365                                     CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
3366                         }
3367                 }
3368
3369                 /*
3370                  * If we received a packet with a vlan tag,
3371                  * attach that information to the packet.
3372                  */
3373                 if (have_tag) {
3374 #if __FreeBSD_version > 700022
3375                         m->m_pkthdr.ether_vtag = vlan_tag;
3376                         m->m_flags |= M_VLANTAG;
3377 #else
3378                         VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag);
3379                         if (m == NULL)
3380                                 continue;
3381 #endif
3382                 }
3383
3384                 if (holdlck != 0) {
3385                         BGE_UNLOCK(sc);
3386                         (*ifp->if_input)(ifp, m);
3387                         BGE_LOCK(sc);
3388                 } else
3389                         (*ifp->if_input)(ifp, m);
3390                 rx_npkts++;
3391
3392                 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
3393                         return (rx_npkts);
3394         }
3395
3396         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3397             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
3398         if (stdcnt > 0)
3399                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3400                     sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
3401
3402         if (jumbocnt > 0)
3403                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3404                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
3405
3406         sc->bge_rx_saved_considx = rx_cons;
3407         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3408         if (stdcnt)
3409                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
3410         if (jumbocnt)
3411                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
3412 #ifdef notyet
3413         /*
3414          * This register wraps very quickly under heavy packet drops.
3415          * If you need correct statistics, you can enable this check.
3416          */
3417         if (BGE_IS_5705_PLUS(sc))
3418                 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3419 #endif
3420         return (rx_npkts);
3421 }
3422
3423 static void
3424 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
3425 {
3426         struct bge_tx_bd *cur_tx = NULL;
3427         struct ifnet *ifp;
3428
3429         BGE_LOCK_ASSERT(sc);
3430
3431         /* Nothing to do. */
3432         if (sc->bge_tx_saved_considx == tx_cons)
3433                 return;
3434
3435         ifp = sc->bge_ifp;
3436
3437         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
3438             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
3439         /*
3440          * Go through our tx ring and free mbufs for those
3441          * frames that have been sent.
3442          */
3443         while (sc->bge_tx_saved_considx != tx_cons) {
3444                 uint32_t                idx = 0;
3445
3446                 idx = sc->bge_tx_saved_considx;
3447                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
3448                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
3449                         ifp->if_opackets++;
3450                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
3451                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
3452                             sc->bge_cdata.bge_tx_dmamap[idx],
3453                             BUS_DMASYNC_POSTWRITE);
3454                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
3455                             sc->bge_cdata.bge_tx_dmamap[idx]);
3456                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
3457                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
3458                 }
3459                 sc->bge_txcnt--;
3460                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3461         }
3462
3463         if (cur_tx != NULL)
3464                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3465         if (sc->bge_txcnt == 0)
3466                 sc->bge_timer = 0;
3467 }
3468
3469 #ifdef DEVICE_POLLING
3470 static int
3471 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3472 {
3473         struct bge_softc *sc = ifp->if_softc;
3474         uint16_t rx_prod, tx_cons;
3475         uint32_t statusword;
3476         int rx_npkts = 0;
3477
3478         BGE_LOCK(sc);
3479         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3480                 BGE_UNLOCK(sc);
3481                 return (rx_npkts);
3482         }
3483
3484         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3485             sc->bge_cdata.bge_status_map,
3486             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3487         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3488         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3489
3490         statusword = atomic_readandclear_32(
3491             &sc->bge_ldata.bge_status_block->bge_status);
3492
3493         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3494             sc->bge_cdata.bge_status_map,
3495             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3496
3497         /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
3498         if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
3499                 sc->bge_link_evt++;
3500
3501         if (cmd == POLL_AND_CHECK_STATUS)
3502                 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3503                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3504                     sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
3505                         bge_link_upd(sc);
3506
3507         sc->rxcycles = count;
3508         rx_npkts = bge_rxeof(sc, rx_prod, 1);
3509         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3510                 BGE_UNLOCK(sc);
3511                 return (rx_npkts);
3512         }
3513         bge_txeof(sc, tx_cons);
3514         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3515                 bge_start_locked(ifp);
3516
3517         BGE_UNLOCK(sc);
3518         return (rx_npkts);
3519 }
3520 #endif /* DEVICE_POLLING */
3521
3522 static int
3523 bge_msi_intr(void *arg)
3524 {
3525         struct bge_softc *sc;
3526
3527         sc = (struct bge_softc *)arg;
3528         /*
3529          * This interrupt is not shared and controller already
3530          * disabled further interrupt.
3531          */
3532         taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
3533         return (FILTER_HANDLED);
3534 }
3535
3536 static void
3537 bge_intr_task(void *arg, int pending)
3538 {
3539         struct bge_softc *sc;
3540         struct ifnet *ifp;
3541         uint32_t status;
3542         uint16_t rx_prod, tx_cons;
3543
3544         sc = (struct bge_softc *)arg;
3545         ifp = sc->bge_ifp;
3546
3547         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3548                 return;
3549
3550         /* Get updated status block. */
3551         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3552             sc->bge_cdata.bge_status_map,
3553             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3554
3555         /* Save producer/consumer indexess. */
3556         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3557         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3558         status = sc->bge_ldata.bge_status_block->bge_status;
3559         sc->bge_ldata.bge_status_block->bge_status = 0;
3560         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3561             sc->bge_cdata.bge_status_map,
3562             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3563         /* Let controller work. */
3564         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3565
3566         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) {
3567                 BGE_LOCK(sc);
3568                 bge_link_upd(sc);
3569                 BGE_UNLOCK(sc);
3570         }
3571         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3572                 /* Check RX return ring producer/consumer. */
3573                 bge_rxeof(sc, rx_prod, 0);
3574         }
3575         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3576                 BGE_LOCK(sc);
3577                 /* Check TX ring producer/consumer. */
3578                 bge_txeof(sc, tx_cons);
3579                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3580                         bge_start_locked(ifp);
3581                 BGE_UNLOCK(sc);
3582         }
3583 }
3584
3585 static void
3586 bge_intr(void *xsc)
3587 {
3588         struct bge_softc *sc;
3589         struct ifnet *ifp;
3590         uint32_t statusword;
3591         uint16_t rx_prod, tx_cons;
3592
3593         sc = xsc;
3594
3595         BGE_LOCK(sc);
3596
3597         ifp = sc->bge_ifp;
3598
3599 #ifdef DEVICE_POLLING
3600         if (ifp->if_capenable & IFCAP_POLLING) {
3601                 BGE_UNLOCK(sc);
3602                 return;
3603         }
3604 #endif
3605
3606         /*
3607          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
3608          * disable interrupts by writing nonzero like we used to, since with
3609          * our current organization this just gives complications and
3610          * pessimizations for re-enabling interrupts.  We used to have races
3611          * instead of the necessary complications.  Disabling interrupts
3612          * would just reduce the chance of a status update while we are
3613          * running (by switching to the interrupt-mode coalescence
3614          * parameters), but this chance is already very low so it is more
3615          * efficient to get another interrupt than prevent it.
3616          *
3617          * We do the ack first to ensure another interrupt if there is a
3618          * status update after the ack.  We don't check for the status
3619          * changing later because it is more efficient to get another
3620          * interrupt than prevent it, not quite as above (not checking is
3621          * a smaller optimization than not toggling the interrupt enable,
3622          * since checking doesn't involve PCI accesses and toggling require
3623          * the status check).  So toggling would probably be a pessimization
3624          * even with MSI.  It would only be needed for using a task queue.
3625          */
3626         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3627
3628         /*
3629          * Do the mandatory PCI flush as well as get the link status.
3630          */
3631         statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
3632
3633         /* Make sure the descriptor ring indexes are coherent. */
3634         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3635             sc->bge_cdata.bge_status_map,
3636             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3637         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3638         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3639         sc->bge_ldata.bge_status_block->bge_status = 0;
3640         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3641             sc->bge_cdata.bge_status_map,
3642             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3643
3644         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3645             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3646             statusword || sc->bge_link_evt)
3647                 bge_link_upd(sc);
3648
3649         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3650                 /* Check RX return ring producer/consumer. */
3651                 bge_rxeof(sc, rx_prod, 1);
3652         }
3653
3654         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3655                 /* Check TX ring producer/consumer. */
3656                 bge_txeof(sc, tx_cons);
3657         }
3658
3659         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3660             !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3661                 bge_start_locked(ifp);
3662
3663         BGE_UNLOCK(sc);
3664 }
3665
3666 static void
3667 bge_asf_driver_up(struct bge_softc *sc)
3668 {
3669         if (sc->bge_asf_mode & ASF_STACKUP) {
3670                 /* Send ASF heartbeat aprox. every 2s */
3671                 if (sc->bge_asf_count)
3672                         sc->bge_asf_count --;
3673                 else {
3674                         sc->bge_asf_count = 5;
3675                         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW,
3676                             BGE_FW_DRV_ALIVE);
3677                         bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4);
3678                         bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3);
3679                         CSR_WRITE_4(sc, BGE_CPU_EVENT,
3680                             CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
3681                 }
3682         }
3683 }
3684
3685 static void
3686 bge_tick(void *xsc)
3687 {
3688         struct bge_softc *sc = xsc;
3689         struct mii_data *mii = NULL;
3690
3691         BGE_LOCK_ASSERT(sc);
3692
3693         /* Synchronize with possible callout reset/stop. */
3694         if (callout_pending(&sc->bge_stat_ch) ||
3695             !callout_active(&sc->bge_stat_ch))
3696                 return;
3697
3698         if (BGE_IS_5705_PLUS(sc))
3699                 bge_stats_update_regs(sc);
3700         else
3701                 bge_stats_update(sc);
3702
3703         if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
3704                 mii = device_get_softc(sc->bge_miibus);
3705                 /*
3706                  * Do not touch PHY if we have link up. This could break
3707                  * IPMI/ASF mode or produce extra input errors
3708                  * (extra errors was reported for bcm5701 & bcm5704).
3709                  */
3710                 if (!sc->bge_link)
3711                         mii_tick(mii);
3712         } else {
3713                 /*
3714                  * Since in TBI mode auto-polling can't be used we should poll
3715                  * link status manually. Here we register pending link event
3716                  * and trigger interrupt.
3717                  */
3718 #ifdef DEVICE_POLLING
3719                 /* In polling mode we poll link state in bge_poll(). */
3720                 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
3721 #endif
3722                 {
3723                 sc->bge_link_evt++;
3724                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3725                     sc->bge_flags & BGE_FLAG_5788)
3726                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3727                 else
3728                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3729                 }
3730         }
3731
3732         bge_asf_driver_up(sc);
3733         bge_watchdog(sc);
3734
3735         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
3736 }
3737
3738 static void
3739 bge_stats_update_regs(struct bge_softc *sc)
3740 {
3741         struct ifnet *ifp;
3742
3743         ifp = sc->bge_ifp;
3744
3745         ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS +
3746             offsetof(struct bge_mac_stats_regs, etherStatsCollisions));
3747
3748         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
3749         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3750         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
3751 }
3752
3753 static void
3754 bge_stats_update(struct bge_softc *sc)
3755 {
3756         struct ifnet *ifp;
3757         bus_size_t stats;
3758         uint32_t cnt;   /* current register value */
3759
3760         ifp = sc->bge_ifp;
3761
3762         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3763
3764 #define READ_STAT(sc, stats, stat) \
3765         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3766
3767         cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
3768         ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
3769         sc->bge_tx_collisions = cnt;
3770
3771         cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
3772         ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
3773         sc->bge_rx_discards = cnt;
3774
3775         cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
3776         ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
3777         sc->bge_tx_discards = cnt;
3778
3779 #undef  READ_STAT
3780 }
3781
3782 /*
3783  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
3784  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
3785  * but when such padded frames employ the bge IP/TCP checksum offload,
3786  * the hardware checksum assist gives incorrect results (possibly
3787  * from incorporating its own padding into the UDP/TCP checksum; who knows).
3788  * If we pad such runts with zeros, the onboard checksum comes out correct.
3789  */
3790 static __inline int
3791 bge_cksum_pad(struct mbuf *m)
3792 {
3793         int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
3794         struct mbuf *last;
3795
3796         /* If there's only the packet-header and we can pad there, use it. */
3797         if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
3798             M_TRAILINGSPACE(m) >= padlen) {
3799                 last = m;
3800         } else {
3801                 /*
3802                  * Walk packet chain to find last mbuf. We will either
3803                  * pad there, or append a new mbuf and pad it.
3804                  */
3805                 for (last = m; last->m_next != NULL; last = last->m_next);
3806                 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
3807                         /* Allocate new empty mbuf, pad it. Compact later. */
3808                         struct mbuf *n;
3809
3810                         MGET(n, M_DONTWAIT, MT_DATA);
3811                         if (n == NULL)
3812                                 return (ENOBUFS);
3813                         n->m_len = 0;
3814                         last->m_next = n;
3815                         last = n;
3816                 }
3817         }
3818
3819         /* Now zero the pad area, to avoid the bge cksum-assist bug. */
3820         memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
3821         last->m_len += padlen;
3822         m->m_pkthdr.len += padlen;
3823
3824         return (0);
3825 }
3826
3827 static struct mbuf *
3828 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss)
3829 {
3830         struct ether_header *eh;
3831         struct ip *ip;
3832         struct tcphdr *tcp;
3833         struct mbuf *n;
3834         uint16_t hlen;
3835         uint32_t ip_off, poff;
3836
3837         if (M_WRITABLE(m) == 0) {
3838                 /* Get a writable copy. */
3839                 n = m_dup(m, M_DONTWAIT);
3840                 m_freem(m);
3841                 if (n == NULL)
3842                         return (NULL);
3843                 m = n;
3844         }
3845         ip_off = sizeof(struct ether_header);
3846         m = m_pullup(m, ip_off);
3847         if (m == NULL)
3848                 return (NULL);
3849         eh = mtod(m, struct ether_header *);
3850         /* Check the existence of VLAN tag. */
3851         if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
3852                 ip_off = sizeof(struct ether_vlan_header);
3853                 m = m_pullup(m, ip_off);
3854                 if (m == NULL)
3855                         return (NULL);
3856         }
3857         m = m_pullup(m, ip_off + sizeof(struct ip));
3858         if (m == NULL)
3859                 return (NULL);
3860         ip = (struct ip *)(mtod(m, char *) + ip_off);
3861         poff = ip_off + (ip->ip_hl << 2);
3862         m = m_pullup(m, poff + sizeof(struct tcphdr));
3863         if (m == NULL)
3864                 return (NULL);
3865         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
3866         m = m_pullup(m, poff + sizeof(struct tcphdr) + tcp->th_off);
3867         if (m == NULL)
3868                 return (NULL);
3869         /*
3870          * It seems controller doesn't modify IP length and TCP pseudo
3871          * checksum. These checksum computed by upper stack should be 0.
3872          */
3873         *mss = m->m_pkthdr.tso_segsz;
3874         ip->ip_sum = 0;
3875         ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
3876         /* Clear pseudo checksum computed by TCP stack. */
3877         tcp->th_sum = 0;
3878         /*
3879          * Broadcom controllers uses different descriptor format for
3880          * TSO depending on ASIC revision. Due to TSO-capable firmware
3881          * license issue and lower performance of firmware based TSO
3882          * we only support hardware based TSO which is applicable for
3883          * BCM5755 or newer controllers. Hardware based TSO uses 11
3884          * bits to store MSS and upper 5 bits are used to store IP/TCP
3885          * header length(including IP/TCP options). The header length
3886          * is expressed as 32 bits unit.
3887          */
3888         hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
3889         *mss |= (hlen << 11);
3890         return (m);
3891 }
3892
3893 /*
3894  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
3895  * pointers to descriptors.
3896  */
3897 static int
3898 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
3899 {
3900         bus_dma_segment_t       segs[BGE_NSEG_NEW];
3901         bus_dmamap_t            map;
3902         struct bge_tx_bd        *d;
3903         struct mbuf             *m = *m_head;
3904         uint32_t                idx = *txidx;
3905         uint16_t                csum_flags, mss, vlan_tag;
3906         int                     nsegs, i, error;
3907
3908         csum_flags = 0;
3909         mss = 0;
3910         vlan_tag = 0;
3911         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
3912                 *m_head = m = bge_setup_tso(sc, m, &mss);
3913                 if (*m_head == NULL)
3914                         return (ENOBUFS);
3915                 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
3916                     BGE_TXBDFLAG_CPU_POST_DMA;
3917         } else if ((m->m_pkthdr.csum_flags & BGE_CSUM_FEATURES) != 0) {
3918                 if (m->m_pkthdr.csum_flags & CSUM_IP)
3919                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3920                 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
3921                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3922                         if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
3923                             (error = bge_cksum_pad(m)) != 0) {
3924                                 m_freem(m);
3925                                 *m_head = NULL;
3926                                 return (error);
3927                         }
3928                 }
3929                 if (m->m_flags & M_LASTFRAG)
3930                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3931                 else if (m->m_flags & M_FRAG)
3932                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3933         }
3934
3935         if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
3936             bge_forced_collapse > 0 && (sc->bge_flags & BGE_FLAG_PCIE) != 0 &&
3937             m->m_next != NULL) {
3938                 /*
3939                  * Forcedly collapse mbuf chains to overcome hardware
3940                  * limitation which only support a single outstanding
3941                  * DMA read operation.
3942                  */
3943                 if (bge_forced_collapse == 1)
3944                         m = m_defrag(m, M_DONTWAIT);
3945                 else
3946                         m = m_collapse(m, M_DONTWAIT, bge_forced_collapse);
3947                 if (m == NULL) {
3948                         m_freem(*m_head);
3949                         *m_head = NULL;
3950                         return (ENOBUFS);
3951                 }
3952                 *m_head = m;
3953         }
3954
3955         map = sc->bge_cdata.bge_tx_dmamap[idx];
3956         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
3957             &nsegs, BUS_DMA_NOWAIT);
3958         if (error == EFBIG) {
3959                 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW);
3960                 if (m == NULL) {
3961                         m_freem(*m_head);
3962                         *m_head = NULL;
3963                         return (ENOBUFS);
3964                 }
3965                 *m_head = m;
3966                 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
3967                     m, segs, &nsegs, BUS_DMA_NOWAIT);
3968                 if (error) {
3969                         m_freem(m);
3970                         *m_head = NULL;
3971                         return (error);
3972                 }
3973         } else if (error != 0)
3974                 return (error);
3975
3976         /* Check if we have enough free send BDs. */
3977         if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
3978                 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
3979                 return (ENOBUFS);
3980         }
3981
3982         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3983
3984 #if __FreeBSD_version > 700022
3985         if (m->m_flags & M_VLANTAG) {
3986                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
3987                 vlan_tag = m->m_pkthdr.ether_vtag;
3988         }
3989 #else
3990         {
3991                 struct m_tag            *mtag;
3992
3993                 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) {
3994                         csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
3995                         vlan_tag = VLAN_TAG_VALUE(mtag);
3996                 }
3997         }
3998 #endif
3999         for (i = 0; ; i++) {
4000                 d = &sc->bge_ldata.bge_tx_ring[idx];
4001                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
4002                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
4003                 d->bge_len = segs[i].ds_len;
4004                 d->bge_flags = csum_flags;
4005                 d->bge_vlan_tag = vlan_tag;
4006                 d->bge_mss = mss;
4007                 if (i == nsegs - 1)
4008                         break;
4009                 BGE_INC(idx, BGE_TX_RING_CNT);
4010         }
4011
4012         /* Mark the last segment as end of packet... */
4013         d->bge_flags |= BGE_TXBDFLAG_END;
4014
4015         /*
4016          * Insure that the map for this transmission
4017          * is placed at the array index of the last descriptor
4018          * in this chain.
4019          */
4020         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
4021         sc->bge_cdata.bge_tx_dmamap[idx] = map;
4022         sc->bge_cdata.bge_tx_chain[idx] = m;
4023         sc->bge_txcnt += nsegs;
4024
4025         BGE_INC(idx, BGE_TX_RING_CNT);
4026         *txidx = idx;
4027
4028         return (0);
4029 }
4030
4031 /*
4032  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4033  * to the mbuf data regions directly in the transmit descriptors.
4034  */
4035 static void
4036 bge_start_locked(struct ifnet *ifp)
4037 {
4038         struct bge_softc *sc;
4039         struct mbuf *m_head;
4040         uint32_t prodidx;
4041         int count;
4042
4043         sc = ifp->if_softc;
4044         BGE_LOCK_ASSERT(sc);
4045
4046         if (!sc->bge_link ||
4047             (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4048             IFF_DRV_RUNNING)
4049                 return;
4050
4051         prodidx = sc->bge_tx_prodidx;
4052
4053         for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
4054                 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
4055                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4056                         break;
4057                 }
4058                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
4059                 if (m_head == NULL)
4060                         break;
4061
4062                 /*
4063                  * XXX
4064                  * The code inside the if() block is never reached since we
4065                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
4066                  * requests to checksum TCP/UDP in a fragmented packet.
4067                  *
4068                  * XXX
4069                  * safety overkill.  If this is a fragmented packet chain
4070                  * with delayed TCP/UDP checksums, then only encapsulate
4071                  * it if we have enough descriptors to handle the entire
4072                  * chain at once.
4073                  * (paranoia -- may not actually be needed)
4074                  */
4075                 if (m_head->m_flags & M_FIRSTFRAG &&
4076                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
4077                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
4078                             m_head->m_pkthdr.csum_data + 16) {
4079                                 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4080                                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4081                                 break;
4082                         }
4083                 }
4084
4085                 /*
4086                  * Pack the data into the transmit ring. If we
4087                  * don't have room, set the OACTIVE flag and wait
4088                  * for the NIC to drain the ring.
4089                  */
4090                 if (bge_encap(sc, &m_head, &prodidx)) {
4091                         if (m_head == NULL)
4092                                 break;
4093                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4094                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4095                         break;
4096                 }
4097                 ++count;
4098
4099                 /*
4100                  * If there's a BPF listener, bounce a copy of this frame
4101                  * to him.
4102                  */
4103 #ifdef ETHER_BPF_MTAP
4104                 ETHER_BPF_MTAP(ifp, m_head);
4105 #else
4106                 BPF_MTAP(ifp, m_head);
4107 #endif
4108         }
4109
4110         if (count > 0) {
4111                 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4112                     sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
4113                 /* Transmit. */
4114                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4115                 /* 5700 b2 errata */
4116                 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
4117                         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4118
4119                 sc->bge_tx_prodidx = prodidx;
4120
4121                 /*
4122                  * Set a timeout in case the chip goes out to lunch.
4123                  */
4124                 sc->bge_timer = 5;
4125         }
4126 }
4127
4128 /*
4129  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4130  * to the mbuf data regions directly in the transmit descriptors.
4131  */
4132 static void
4133 bge_start(struct ifnet *ifp)
4134 {
4135         struct bge_softc *sc;
4136
4137         sc = ifp->if_softc;
4138         BGE_LOCK(sc);
4139         bge_start_locked(ifp);
4140         BGE_UNLOCK(sc);
4141 }
4142
4143 static void
4144 bge_init_locked(struct bge_softc *sc)
4145 {
4146         struct ifnet *ifp;
4147         uint16_t *m;
4148
4149         BGE_LOCK_ASSERT(sc);
4150
4151         ifp = sc->bge_ifp;
4152
4153         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4154                 return;
4155
4156         /* Cancel pending I/O and flush buffers. */
4157         bge_stop(sc);
4158
4159         bge_stop_fw(sc);
4160         bge_sig_pre_reset(sc, BGE_RESET_START);
4161         bge_reset(sc);
4162         bge_sig_legacy(sc, BGE_RESET_START);
4163         bge_sig_post_reset(sc, BGE_RESET_START);
4164
4165         bge_chipinit(sc);
4166
4167         /*
4168          * Init the various state machines, ring
4169          * control blocks and firmware.
4170          */
4171         if (bge_blockinit(sc)) {
4172                 device_printf(sc->bge_dev, "initialization failure\n");
4173                 return;
4174         }
4175
4176         ifp = sc->bge_ifp;
4177
4178         /* Specify MTU. */
4179         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
4180             ETHER_HDR_LEN + ETHER_CRC_LEN +
4181             (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
4182
4183         /* Load our MAC address. */
4184         m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
4185         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
4186         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
4187
4188         /* Program promiscuous mode. */
4189         bge_setpromisc(sc);
4190
4191         /* Program multicast filter. */
4192         bge_setmulti(sc);
4193
4194         /* Program VLAN tag stripping. */
4195         bge_setvlan(sc);
4196
4197         /* Init RX ring. */
4198         if (bge_init_rx_ring_std(sc) != 0) {
4199                 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
4200                 bge_stop(sc);
4201                 return;
4202         }
4203
4204         /*
4205          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
4206          * memory to insure that the chip has in fact read the first
4207          * entry of the ring.
4208          */
4209         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
4210                 uint32_t                v, i;
4211                 for (i = 0; i < 10; i++) {
4212                         DELAY(20);
4213                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
4214                         if (v == (MCLBYTES - ETHER_ALIGN))
4215                                 break;
4216                 }
4217                 if (i == 10)
4218                         device_printf (sc->bge_dev,
4219                             "5705 A0 chip failed to load RX ring\n");
4220         }
4221
4222         /* Init jumbo RX ring. */
4223         if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
4224             (MCLBYTES - ETHER_ALIGN)) {
4225                 if (bge_init_rx_ring_jumbo(sc) != 0) {
4226                         device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
4227                         bge_stop(sc);
4228                         return;
4229                 }
4230         }
4231
4232         /* Init our RX return ring index. */
4233         sc->bge_rx_saved_considx = 0;
4234
4235         /* Init our RX/TX stat counters. */
4236         sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
4237
4238         /* Init TX ring. */
4239         bge_init_tx_ring(sc);
4240
4241         /* Turn on transmitter. */
4242         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
4243
4244         /* Turn on receiver. */
4245         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4246
4247         /* Tell firmware we're alive. */
4248         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4249
4250 #ifdef DEVICE_POLLING
4251         /* Disable interrupts if we are polling. */
4252         if (ifp->if_capenable & IFCAP_POLLING) {
4253                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4254                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4255                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4256         } else
4257 #endif
4258
4259         /* Enable host interrupts. */
4260         {
4261         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
4262         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4263         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4264         }
4265
4266         bge_ifmedia_upd_locked(ifp);
4267
4268         ifp->if_drv_flags |= IFF_DRV_RUNNING;
4269         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4270
4271         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4272 }
4273
4274 static void
4275 bge_init(void *xsc)
4276 {
4277         struct bge_softc *sc = xsc;
4278
4279         BGE_LOCK(sc);
4280         bge_init_locked(sc);
4281         BGE_UNLOCK(sc);
4282 }
4283
4284 /*
4285  * Set media options.
4286  */
4287 static int
4288 bge_ifmedia_upd(struct ifnet *ifp)
4289 {
4290         struct bge_softc *sc = ifp->if_softc;
4291         int res;
4292
4293         BGE_LOCK(sc);
4294         res = bge_ifmedia_upd_locked(ifp);
4295         BGE_UNLOCK(sc);
4296
4297         return (res);
4298 }
4299
4300 static int
4301 bge_ifmedia_upd_locked(struct ifnet *ifp)
4302 {
4303         struct bge_softc *sc = ifp->if_softc;
4304         struct mii_data *mii;
4305         struct mii_softc *miisc;
4306         struct ifmedia *ifm;
4307
4308         BGE_LOCK_ASSERT(sc);
4309
4310         ifm = &sc->bge_ifmedia;
4311
4312         /* If this is a 1000baseX NIC, enable the TBI port. */
4313         if (sc->bge_flags & BGE_FLAG_TBI) {
4314                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
4315                         return (EINVAL);
4316                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
4317                 case IFM_AUTO:
4318                         /*
4319                          * The BCM5704 ASIC appears to have a special
4320                          * mechanism for programming the autoneg
4321                          * advertisement registers in TBI mode.
4322                          */
4323                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4324                                 uint32_t sgdig;
4325                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
4326                                 if (sgdig & BGE_SGDIGSTS_DONE) {
4327                                         CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
4328                                         sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
4329                                         sgdig |= BGE_SGDIGCFG_AUTO |
4330                                             BGE_SGDIGCFG_PAUSE_CAP |
4331                                             BGE_SGDIGCFG_ASYM_PAUSE;
4332                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG,
4333                                             sgdig | BGE_SGDIGCFG_SEND);
4334                                         DELAY(5);
4335                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
4336                                 }
4337                         }
4338                         break;
4339                 case IFM_1000_SX:
4340                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
4341                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
4342                                     BGE_MACMODE_HALF_DUPLEX);
4343                         } else {
4344                                 BGE_SETBIT(sc, BGE_MAC_MODE,
4345                                     BGE_MACMODE_HALF_DUPLEX);
4346                         }
4347                         break;
4348                 default:
4349                         return (EINVAL);
4350                 }
4351                 return (0);
4352         }
4353
4354         sc->bge_link_evt++;
4355         mii = device_get_softc(sc->bge_miibus);
4356         if (mii->mii_instance)
4357                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4358                         mii_phy_reset(miisc);
4359         mii_mediachg(mii);
4360
4361         /*
4362          * Force an interrupt so that we will call bge_link_upd
4363          * if needed and clear any pending link state attention.
4364          * Without this we are not getting any further interrupts
4365          * for link state changes and thus will not UP the link and
4366          * not be able to send in bge_start_locked. The only
4367          * way to get things working was to receive a packet and
4368          * get an RX intr.
4369          * bge_tick should help for fiber cards and we might not
4370          * need to do this here if BGE_FLAG_TBI is set but as
4371          * we poll for fiber anyway it should not harm.
4372          */
4373         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4374             sc->bge_flags & BGE_FLAG_5788)
4375                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4376         else
4377                 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4378
4379         return (0);
4380 }
4381
4382 /*
4383  * Report current media status.
4384  */
4385 static void
4386 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4387 {
4388         struct bge_softc *sc = ifp->if_softc;
4389         struct mii_data *mii;
4390
4391         BGE_LOCK(sc);
4392
4393         if (sc->bge_flags & BGE_FLAG_TBI) {
4394                 ifmr->ifm_status = IFM_AVALID;
4395                 ifmr->ifm_active = IFM_ETHER;
4396                 if (CSR_READ_4(sc, BGE_MAC_STS) &
4397                     BGE_MACSTAT_TBI_PCS_SYNCHED)
4398                         ifmr->ifm_status |= IFM_ACTIVE;
4399                 else {
4400                         ifmr->ifm_active |= IFM_NONE;
4401                         BGE_UNLOCK(sc);
4402                         return;
4403                 }
4404                 ifmr->ifm_active |= IFM_1000_SX;
4405                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
4406                         ifmr->ifm_active |= IFM_HDX;
4407                 else
4408                         ifmr->ifm_active |= IFM_FDX;
4409                 BGE_UNLOCK(sc);
4410                 return;
4411         }
4412
4413         mii = device_get_softc(sc->bge_miibus);
4414         mii_pollstat(mii);
4415         ifmr->ifm_active = mii->mii_media_active;
4416         ifmr->ifm_status = mii->mii_media_status;
4417
4418         BGE_UNLOCK(sc);
4419 }
4420
4421 static int
4422 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
4423 {
4424         struct bge_softc *sc = ifp->if_softc;
4425         struct ifreq *ifr = (struct ifreq *) data;
4426         struct mii_data *mii;
4427         int flags, mask, error = 0;
4428
4429         switch (command) {
4430         case SIOCSIFMTU:
4431                 if (ifr->ifr_mtu < ETHERMIN ||
4432                     ((BGE_IS_JUMBO_CAPABLE(sc)) &&
4433                     ifr->ifr_mtu > BGE_JUMBO_MTU) ||
4434                     ((!BGE_IS_JUMBO_CAPABLE(sc)) &&
4435                     ifr->ifr_mtu > ETHERMTU))
4436                         error = EINVAL;
4437                 else if (ifp->if_mtu != ifr->ifr_mtu) {
4438                         ifp->if_mtu = ifr->ifr_mtu;
4439                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4440                         bge_init(sc);
4441                 }
4442                 break;
4443         case SIOCSIFFLAGS:
4444                 BGE_LOCK(sc);
4445                 if (ifp->if_flags & IFF_UP) {
4446                         /*
4447                          * If only the state of the PROMISC flag changed,
4448                          * then just use the 'set promisc mode' command
4449                          * instead of reinitializing the entire NIC. Doing
4450                          * a full re-init means reloading the firmware and
4451                          * waiting for it to start up, which may take a
4452                          * second or two.  Similarly for ALLMULTI.
4453                          */
4454                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4455                                 flags = ifp->if_flags ^ sc->bge_if_flags;
4456                                 if (flags & IFF_PROMISC)
4457                                         bge_setpromisc(sc);
4458                                 if (flags & IFF_ALLMULTI)
4459                                         bge_setmulti(sc);
4460                         } else
4461                                 bge_init_locked(sc);
4462                 } else {
4463                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4464                                 bge_stop(sc);
4465                         }
4466                 }
4467                 sc->bge_if_flags = ifp->if_flags;
4468                 BGE_UNLOCK(sc);
4469                 error = 0;
4470                 break;
4471         case SIOCADDMULTI:
4472         case SIOCDELMULTI:
4473                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4474                         BGE_LOCK(sc);
4475                         bge_setmulti(sc);
4476                         BGE_UNLOCK(sc);
4477                         error = 0;
4478                 }
4479                 break;
4480         case SIOCSIFMEDIA:
4481         case SIOCGIFMEDIA:
4482                 if (sc->bge_flags & BGE_FLAG_TBI) {
4483                         error = ifmedia_ioctl(ifp, ifr,
4484                             &sc->bge_ifmedia, command);
4485                 } else {
4486                         mii = device_get_softc(sc->bge_miibus);
4487                         error = ifmedia_ioctl(ifp, ifr,
4488                             &mii->mii_media, command);
4489                 }
4490                 break;
4491         case SIOCSIFCAP:
4492                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
4493 #ifdef DEVICE_POLLING
4494                 if (mask & IFCAP_POLLING) {
4495                         if (ifr->ifr_reqcap & IFCAP_POLLING) {
4496                                 error = ether_poll_register(bge_poll, ifp);
4497                                 if (error)
4498                                         return (error);
4499                                 BGE_LOCK(sc);
4500                                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4501                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4502                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4503                                 ifp->if_capenable |= IFCAP_POLLING;
4504                                 BGE_UNLOCK(sc);
4505                         } else {
4506                                 error = ether_poll_deregister(ifp);
4507                                 /* Enable interrupt even in error case */
4508                                 BGE_LOCK(sc);
4509                                 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
4510                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4511                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4512                                 ifp->if_capenable &= ~IFCAP_POLLING;
4513                                 BGE_UNLOCK(sc);
4514                         }
4515                 }
4516 #endif
4517                 if (mask & IFCAP_HWCSUM) {
4518                         ifp->if_capenable ^= IFCAP_HWCSUM;
4519                         if (IFCAP_HWCSUM & ifp->if_capenable &&
4520                             IFCAP_HWCSUM & ifp->if_capabilities)
4521                                 ifp->if_hwassist |= BGE_CSUM_FEATURES;
4522                         else
4523                                 ifp->if_hwassist &= ~BGE_CSUM_FEATURES;
4524 #ifdef VLAN_CAPABILITIES
4525                         VLAN_CAPABILITIES(ifp);
4526 #endif
4527                 }
4528
4529                 if ((mask & IFCAP_TSO4) != 0 &&
4530                     (ifp->if_capabilities & IFCAP_TSO4) != 0) {
4531                         ifp->if_capenable ^= IFCAP_TSO4;
4532                         if ((ifp->if_capenable & IFCAP_TSO4) != 0)
4533                                 ifp->if_hwassist |= CSUM_TSO;
4534                         else
4535                                 ifp->if_hwassist &= ~CSUM_TSO;
4536                 }
4537
4538                 if (mask & IFCAP_VLAN_MTU) {
4539                         ifp->if_capenable ^= IFCAP_VLAN_MTU;
4540                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4541                         bge_init(sc);
4542                 }
4543
4544                 if (mask & IFCAP_VLAN_HWTAGGING) {
4545                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
4546                         BGE_LOCK(sc);
4547                         bge_setvlan(sc);
4548                         BGE_UNLOCK(sc);
4549 #ifdef VLAN_CAPABILITIES
4550                         VLAN_CAPABILITIES(ifp);
4551 #endif
4552                 }
4553
4554                 break;
4555         default:
4556                 error = ether_ioctl(ifp, command, data);
4557                 break;
4558         }
4559
4560         return (error);
4561 }
4562
4563 static void
4564 bge_watchdog(struct bge_softc *sc)
4565 {
4566         struct ifnet *ifp;
4567
4568         BGE_LOCK_ASSERT(sc);
4569
4570         if (sc->bge_timer == 0 || --sc->bge_timer)
4571                 return;
4572
4573         ifp = sc->bge_ifp;
4574
4575         if_printf(ifp, "watchdog timeout -- resetting\n");
4576
4577         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4578         bge_init_locked(sc);
4579
4580         ifp->if_oerrors++;
4581 }
4582
4583 /*
4584  * Stop the adapter and free any mbufs allocated to the
4585  * RX and TX lists.
4586  */
4587 static void
4588 bge_stop(struct bge_softc *sc)
4589 {
4590         struct ifnet *ifp;
4591         struct ifmedia_entry *ifm;
4592         struct mii_data *mii = NULL;
4593         int mtmp, itmp;
4594
4595         BGE_LOCK_ASSERT(sc);
4596
4597         ifp = sc->bge_ifp;
4598
4599         if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
4600                 mii = device_get_softc(sc->bge_miibus);
4601
4602         callout_stop(&sc->bge_stat_ch);
4603
4604         /* Disable host interrupts. */
4605         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4606         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4607
4608         /*
4609          * Tell firmware we're shutting down.
4610          */
4611         bge_stop_fw(sc);
4612         bge_sig_pre_reset(sc, BGE_RESET_STOP);
4613
4614         /*
4615          * Disable all of the receiver blocks.
4616          */
4617         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4618         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
4619         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
4620         if (!(BGE_IS_5705_PLUS(sc)))
4621                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
4622         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
4623         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
4624         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
4625
4626         /*
4627          * Disable all of the transmit blocks.
4628          */
4629         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
4630         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
4631         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
4632         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
4633         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
4634         if (!(BGE_IS_5705_PLUS(sc)))
4635                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
4636         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
4637
4638         /*
4639          * Shut down all of the memory managers and related
4640          * state machines.
4641          */
4642         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
4643         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
4644         if (!(BGE_IS_5705_PLUS(sc)))
4645                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
4646         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
4647         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
4648         if (!(BGE_IS_5705_PLUS(sc))) {
4649                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
4650                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4651         }
4652
4653         bge_reset(sc);
4654         bge_sig_legacy(sc, BGE_RESET_STOP);
4655         bge_sig_post_reset(sc, BGE_RESET_STOP);
4656
4657         /*
4658          * Keep the ASF firmware running if up.
4659          */
4660         if (sc->bge_asf_mode & ASF_STACKUP)
4661                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4662         else
4663                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4664
4665         /* Free the RX lists. */
4666         bge_free_rx_ring_std(sc);
4667
4668         /* Free jumbo RX list. */
4669         if (BGE_IS_JUMBO_CAPABLE(sc))
4670                 bge_free_rx_ring_jumbo(sc);
4671
4672         /* Free TX buffers. */
4673         bge_free_tx_ring(sc);
4674
4675         /*
4676          * Isolate/power down the PHY, but leave the media selection
4677          * unchanged so that things will be put back to normal when
4678          * we bring the interface back up.
4679          */
4680         if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4681                 itmp = ifp->if_flags;
4682                 ifp->if_flags |= IFF_UP;
4683                 /*
4684                  * If we are called from bge_detach(), mii is already NULL.
4685                  */
4686                 if (mii != NULL) {
4687                         ifm = mii->mii_media.ifm_cur;
4688                         mtmp = ifm->ifm_media;
4689                         ifm->ifm_media = IFM_ETHER | IFM_NONE;
4690                         mii_mediachg(mii);
4691                         ifm->ifm_media = mtmp;
4692                 }
4693                 ifp->if_flags = itmp;
4694         }
4695
4696         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
4697
4698         /* Clear MAC's link state (PHY may still have link UP). */
4699         if (bootverbose && sc->bge_link)
4700                 if_printf(sc->bge_ifp, "link DOWN\n");
4701         sc->bge_link = 0;
4702
4703         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4704 }
4705
4706 /*
4707  * Stop all chip I/O so that the kernel's probe routines don't
4708  * get confused by errant DMAs when rebooting.
4709  */
4710 static int
4711 bge_shutdown(device_t dev)
4712 {
4713         struct bge_softc *sc;
4714
4715         sc = device_get_softc(dev);
4716         BGE_LOCK(sc);
4717         bge_stop(sc);
4718         bge_reset(sc);
4719         BGE_UNLOCK(sc);
4720
4721         return (0);
4722 }
4723
4724 static int
4725 bge_suspend(device_t dev)
4726 {
4727         struct bge_softc *sc;
4728
4729         sc = device_get_softc(dev);
4730         BGE_LOCK(sc);
4731         bge_stop(sc);
4732         BGE_UNLOCK(sc);
4733
4734         return (0);
4735 }
4736
4737 static int
4738 bge_resume(device_t dev)
4739 {
4740         struct bge_softc *sc;
4741         struct ifnet *ifp;
4742
4743         sc = device_get_softc(dev);
4744         BGE_LOCK(sc);
4745         ifp = sc->bge_ifp;
4746         if (ifp->if_flags & IFF_UP) {
4747                 bge_init_locked(sc);
4748                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4749                         bge_start_locked(ifp);
4750         }
4751         BGE_UNLOCK(sc);
4752
4753         return (0);
4754 }
4755
4756 static void
4757 bge_link_upd(struct bge_softc *sc)
4758 {
4759         struct mii_data *mii;
4760         uint32_t link, status;
4761
4762         BGE_LOCK_ASSERT(sc);
4763
4764         /* Clear 'pending link event' flag. */
4765         sc->bge_link_evt = 0;
4766
4767         /*
4768          * Process link state changes.
4769          * Grrr. The link status word in the status block does
4770          * not work correctly on the BCM5700 rev AX and BX chips,
4771          * according to all available information. Hence, we have
4772          * to enable MII interrupts in order to properly obtain
4773          * async link changes. Unfortunately, this also means that
4774          * we have to read the MAC status register to detect link
4775          * changes, thereby adding an additional register access to
4776          * the interrupt handler.
4777          *
4778          * XXX: perhaps link state detection procedure used for
4779          * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
4780          */
4781
4782         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4783             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
4784                 status = CSR_READ_4(sc, BGE_MAC_STS);
4785                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
4786                         mii = device_get_softc(sc->bge_miibus);
4787                         mii_pollstat(mii);
4788                         if (!sc->bge_link &&
4789                             mii->mii_media_status & IFM_ACTIVE &&
4790                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4791                                 sc->bge_link++;
4792                                 if (bootverbose)
4793                                         if_printf(sc->bge_ifp, "link UP\n");
4794                         } else if (sc->bge_link &&
4795                             (!(mii->mii_media_status & IFM_ACTIVE) ||
4796                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4797                                 sc->bge_link = 0;
4798                                 if (bootverbose)
4799                                         if_printf(sc->bge_ifp, "link DOWN\n");
4800                         }
4801
4802                         /* Clear the interrupt. */
4803                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
4804                             BGE_EVTENB_MI_INTERRUPT);
4805                         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4806                         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
4807                             BRGPHY_INTRS);
4808                 }
4809                 return;
4810         }
4811
4812         if (sc->bge_flags & BGE_FLAG_TBI) {
4813                 status = CSR_READ_4(sc, BGE_MAC_STS);
4814                 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4815                         if (!sc->bge_link) {
4816                                 sc->bge_link++;
4817                                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
4818                                         BGE_CLRBIT(sc, BGE_MAC_MODE,
4819                                             BGE_MACMODE_TBI_SEND_CFGS);
4820                                 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4821                                 if (bootverbose)
4822                                         if_printf(sc->bge_ifp, "link UP\n");
4823                                 if_link_state_change(sc->bge_ifp,
4824                                     LINK_STATE_UP);
4825                         }
4826                 } else if (sc->bge_link) {
4827                         sc->bge_link = 0;
4828                         if (bootverbose)
4829                                 if_printf(sc->bge_ifp, "link DOWN\n");
4830                         if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
4831                 }
4832         } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
4833                 /*
4834                  * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
4835                  * in status word always set. Workaround this bug by reading
4836                  * PHY link status directly.
4837                  */
4838                 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
4839
4840                 if (link != sc->bge_link ||
4841                     sc->bge_asicrev == BGE_ASICREV_BCM5700) {
4842                         mii = device_get_softc(sc->bge_miibus);
4843                         mii_pollstat(mii);
4844                         if (!sc->bge_link &&
4845                             mii->mii_media_status & IFM_ACTIVE &&
4846                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4847                                 sc->bge_link++;
4848                                 if (bootverbose)
4849                                         if_printf(sc->bge_ifp, "link UP\n");
4850                         } else if (sc->bge_link &&
4851                             (!(mii->mii_media_status & IFM_ACTIVE) ||
4852                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4853                                 sc->bge_link = 0;
4854                                 if (bootverbose)
4855                                         if_printf(sc->bge_ifp, "link DOWN\n");
4856                         }
4857                 }
4858         } else {
4859                 /*
4860                  * Discard link events for MII/GMII controllers
4861                  * if MI auto-polling is disabled.
4862                  */
4863         }
4864
4865         /* Clear the attention. */
4866         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4867             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4868             BGE_MACSTAT_LINK_CHANGED);
4869 }
4870
4871 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
4872         SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
4873             sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
4874             desc)
4875
4876 static void
4877 bge_add_sysctls(struct bge_softc *sc)
4878 {
4879         struct sysctl_ctx_list *ctx;
4880         struct sysctl_oid_list *children, *schildren;
4881         struct sysctl_oid *tree;
4882
4883         ctx = device_get_sysctl_ctx(sc->bge_dev);
4884         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
4885
4886 #ifdef BGE_REGISTER_DEBUG
4887         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
4888             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
4889             "Debug Information");
4890
4891         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
4892             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
4893             "Register Read");
4894
4895         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
4896             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
4897             "Memory Read");
4898
4899 #endif
4900
4901         if (BGE_IS_5705_PLUS(sc))
4902                 return;
4903
4904         tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
4905             NULL, "BGE Statistics");
4906         schildren = children = SYSCTL_CHILDREN(tree);
4907         BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
4908             children, COSFramesDroppedDueToFilters,
4909             "FramesDroppedDueToFilters");
4910         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
4911             children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
4912         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
4913             children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
4914         BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
4915             children, nicNoMoreRxBDs, "NoMoreRxBDs");
4916         BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
4917             children, ifInDiscards, "InputDiscards");
4918         BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
4919             children, ifInErrors, "InputErrors");
4920         BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
4921             children, nicRecvThresholdHit, "RecvThresholdHit");
4922         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
4923             children, nicDmaReadQueueFull, "DmaReadQueueFull");
4924         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
4925             children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
4926         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
4927             children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
4928         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
4929             children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
4930         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
4931             children, nicRingStatusUpdate, "RingStatusUpdate");
4932         BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
4933             children, nicInterrupts, "Interrupts");
4934         BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
4935             children, nicAvoidedInterrupts, "AvoidedInterrupts");
4936         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
4937             children, nicSendThresholdHit, "SendThresholdHit");
4938
4939         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
4940             NULL, "BGE RX Statistics");
4941         children = SYSCTL_CHILDREN(tree);
4942         BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
4943             children, rxstats.ifHCInOctets, "Octets");
4944         BGE_SYSCTL_STAT(sc, ctx, "Fragments",
4945             children, rxstats.etherStatsFragments, "Fragments");
4946         BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
4947             children, rxstats.ifHCInUcastPkts, "UcastPkts");
4948         BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
4949             children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
4950         BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
4951             children, rxstats.dot3StatsFCSErrors, "FCSErrors");
4952         BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
4953             children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
4954         BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
4955             children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
4956         BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
4957             children, rxstats.xoffPauseFramesReceived,
4958             "xoffPauseFramesReceived");
4959         BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
4960             children, rxstats.macControlFramesReceived,
4961             "ControlFramesReceived");
4962         BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
4963             children, rxstats.xoffStateEntered, "xoffStateEntered");
4964         BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
4965             children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
4966         BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
4967             children, rxstats.etherStatsJabbers, "Jabbers");
4968         BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
4969             children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
4970         BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
4971             children, rxstats.inRangeLengthError, "inRangeLengthError");
4972         BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
4973             children, rxstats.outRangeLengthError, "outRangeLengthError");
4974
4975         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
4976             NULL, "BGE TX Statistics");
4977         children = SYSCTL_CHILDREN(tree);
4978         BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
4979             children, txstats.ifHCOutOctets, "Octets");
4980         BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
4981             children, txstats.etherStatsCollisions, "Collisions");
4982         BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
4983             children, txstats.outXonSent, "XonSent");
4984         BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
4985             children, txstats.outXoffSent, "XoffSent");
4986         BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
4987             children, txstats.flowControlDone, "flowControlDone");
4988         BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
4989             children, txstats.dot3StatsInternalMacTransmitErrors,
4990             "InternalMacTransmitErrors");
4991         BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
4992             children, txstats.dot3StatsSingleCollisionFrames,
4993             "SingleCollisionFrames");
4994         BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
4995             children, txstats.dot3StatsMultipleCollisionFrames,
4996             "MultipleCollisionFrames");
4997         BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
4998             children, txstats.dot3StatsDeferredTransmissions,
4999             "DeferredTransmissions");
5000         BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
5001             children, txstats.dot3StatsExcessiveCollisions,
5002             "ExcessiveCollisions");
5003         BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
5004             children, txstats.dot3StatsLateCollisions,
5005             "LateCollisions");
5006         BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
5007             children, txstats.ifHCOutUcastPkts, "UcastPkts");
5008         BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
5009             children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
5010         BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
5011             children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
5012         BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
5013             children, txstats.dot3StatsCarrierSenseErrors,
5014             "CarrierSenseErrors");
5015         BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
5016             children, txstats.ifOutDiscards, "Discards");
5017         BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
5018             children, txstats.ifOutErrors, "Errors");
5019 }
5020
5021 static int
5022 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
5023 {
5024         struct bge_softc *sc;
5025         uint32_t result;
5026         int offset;
5027
5028         sc = (struct bge_softc *)arg1;
5029         offset = arg2;
5030         result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
5031             offsetof(bge_hostaddr, bge_addr_lo));
5032         return (sysctl_handle_int(oidp, &result, 0, req));
5033 }
5034
5035 #ifdef BGE_REGISTER_DEBUG
5036 static int
5037 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
5038 {
5039         struct bge_softc *sc;
5040         uint16_t *sbdata;
5041         int error;
5042         int result;
5043         int i, j;
5044
5045         result = -1;
5046         error = sysctl_handle_int(oidp, &result, 0, req);
5047         if (error || (req->newptr == NULL))
5048                 return (error);
5049
5050         if (result == 1) {
5051                 sc = (struct bge_softc *)arg1;
5052
5053                 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
5054                 printf("Status Block:\n");
5055                 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) {
5056                         printf("%06x:", i);
5057                         for (j = 0; j < 8; j++) {
5058                                 printf(" %04x", sbdata[i]);
5059                                 i += 4;
5060                         }
5061                         printf("\n");
5062                 }
5063
5064                 printf("Registers:\n");
5065                 for (i = 0x800; i < 0xA00; ) {
5066                         printf("%06x:", i);
5067                         for (j = 0; j < 8; j++) {
5068                                 printf(" %08x", CSR_READ_4(sc, i));
5069                                 i += 4;
5070                         }
5071                         printf("\n");
5072                 }
5073
5074                 printf("Hardware Flags:\n");
5075                 if (BGE_IS_5755_PLUS(sc))
5076                         printf(" - 5755 Plus\n");
5077                 if (BGE_IS_575X_PLUS(sc))
5078                         printf(" - 575X Plus\n");
5079                 if (BGE_IS_5705_PLUS(sc))
5080                         printf(" - 5705 Plus\n");
5081                 if (BGE_IS_5714_FAMILY(sc))
5082                         printf(" - 5714 Family\n");
5083                 if (BGE_IS_5700_FAMILY(sc))
5084                         printf(" - 5700 Family\n");
5085                 if (sc->bge_flags & BGE_FLAG_JUMBO)
5086                         printf(" - Supports Jumbo Frames\n");
5087                 if (sc->bge_flags & BGE_FLAG_PCIX)
5088                         printf(" - PCI-X Bus\n");
5089                 if (sc->bge_flags & BGE_FLAG_PCIE)
5090                         printf(" - PCI Express Bus\n");
5091                 if (sc->bge_flags & BGE_FLAG_NO_3LED)
5092                         printf(" - No 3 LEDs\n");
5093                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
5094                         printf(" - RX Alignment Bug\n");
5095         }
5096
5097         return (error);
5098 }
5099
5100 static int
5101 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5102 {
5103         struct bge_softc *sc;
5104         int error;
5105         uint16_t result;
5106         uint32_t val;
5107
5108         result = -1;
5109         error = sysctl_handle_int(oidp, &result, 0, req);
5110         if (error || (req->newptr == NULL))
5111                 return (error);
5112
5113         if (result < 0x8000) {
5114                 sc = (struct bge_softc *)arg1;
5115                 val = CSR_READ_4(sc, result);
5116                 printf("reg 0x%06X = 0x%08X\n", result, val);
5117         }
5118
5119         return (error);
5120 }
5121
5122 static int
5123 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
5124 {
5125         struct bge_softc *sc;
5126         int error;
5127         uint16_t result;
5128         uint32_t val;
5129
5130         result = -1;
5131         error = sysctl_handle_int(oidp, &result, 0, req);
5132         if (error || (req->newptr == NULL))
5133                 return (error);
5134
5135         if (result < 0x8000) {
5136                 sc = (struct bge_softc *)arg1;
5137                 val = bge_readmem_ind(sc, result);
5138                 printf("mem 0x%06X = 0x%08X\n", result, val);
5139         }
5140
5141         return (error);
5142 }
5143 #endif
5144
5145 static int
5146 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
5147 {
5148
5149         if (sc->bge_flags & BGE_FLAG_EADDR)
5150                 return (1);
5151
5152 #ifdef __sparc64__
5153         OF_getetheraddr(sc->bge_dev, ether_addr);
5154         return (0);
5155 #endif
5156         return (1);
5157 }
5158
5159 static int
5160 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
5161 {
5162         uint32_t mac_addr;
5163
5164         mac_addr = bge_readmem_ind(sc, 0x0c14);
5165         if ((mac_addr >> 16) == 0x484b) {
5166                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
5167                 ether_addr[1] = (uint8_t)mac_addr;
5168                 mac_addr = bge_readmem_ind(sc, 0x0c18);
5169                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
5170                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
5171                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
5172                 ether_addr[5] = (uint8_t)mac_addr;
5173                 return (0);
5174         }
5175         return (1);
5176 }
5177
5178 static int
5179 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
5180 {
5181         int mac_offset = BGE_EE_MAC_OFFSET;
5182
5183         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
5184                 mac_offset = BGE_EE_MAC_OFFSET_5906;
5185
5186         return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
5187             ETHER_ADDR_LEN));
5188 }
5189
5190 static int
5191 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
5192 {
5193
5194         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
5195                 return (1);
5196
5197         return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
5198            ETHER_ADDR_LEN));
5199 }
5200
5201 static int
5202 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
5203 {
5204         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
5205                 /* NOTE: Order is critical */
5206                 bge_get_eaddr_fw,
5207                 bge_get_eaddr_mem,
5208                 bge_get_eaddr_nvram,
5209                 bge_get_eaddr_eeprom,
5210                 NULL
5211         };
5212         const bge_eaddr_fcn_t *func;
5213
5214         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
5215                 if ((*func)(sc, eaddr) == 0)
5216                         break;
5217         }
5218         return (*func == NULL ? ENXIO : 0);
5219 }