sys/dev/bge/if_bge.c

   1 /*-
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/cdefs.h>
  35 __FBSDID("$FreeBSD$");
  36
  37 /*
  38  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  39  *
  40  * The Broadcom BCM5700 is based on technology originally developed by
  41  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  42  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  43  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  44  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  45  * frames, highly configurable RX filtering, and 16 RX and TX queues
  46  * (which, along with RX filter rules, can be used for QOS applications).
  47  * Other features, such as TCP segmentation, may be available as part
  48  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  49  * firmware images can be stored in hardware and need not be compiled
  50  * into the driver.
  51  *
  52  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  53  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  54  *
  55  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  56  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  57  * does not support external SSRAM.
  58  *
  59  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  60  * brand name, which is functionally similar but lacks PCI-X support.
  61  *
  62  * Without external SSRAM, you can only have at most 4 TX rings,
  63  * and the use of the mini RX ring is disabled. This seems to imply
  64  * that these features are simply not available on the BCM5701. As a
  65  * result, this driver does not implement any support for the mini RX
  66  * ring.
  67  */
  68
  69 #ifdef HAVE_KERNEL_OPTION_HEADERS
  70 #include "opt_device_polling.h"
  71 #endif
  72
  73 #include <sys/param.h>
  74 #include <sys/endian.h>
  75 #include <sys/systm.h>
  76 #include <sys/sockio.h>
  77 #include <sys/mbuf.h>
  78 #include <sys/malloc.h>
  79 #include <sys/kernel.h>
  80 #include <sys/module.h>
  81 #include <sys/socket.h>
  82 #include <sys/sysctl.h>
  83 #include <sys/taskqueue.h>
  84
  85 #include <net/if.h>
  86 #include <net/if_arp.h>
  87 #include <net/ethernet.h>
  88 #include <net/if_dl.h>
  89 #include <net/if_media.h>
  90
  91 #include <net/bpf.h>
  92
  93 #include <net/if_types.h>
  94 #include <net/if_vlan_var.h>
  95
  96 #include <netinet/in_systm.h>
  97 #include <netinet/in.h>
  98 #include <netinet/ip.h>
  99 #include <netinet/tcp.h>
 100
 101 #include <machine/bus.h>
 102 #include <machine/resource.h>
 103 #include <sys/bus.h>
 104 #include <sys/rman.h>
 105
 106 #include <dev/mii/mii.h>
 107 #include <dev/mii/miivar.h>
 108 #include "miidevs.h"
 109 #include <dev/mii/brgphyreg.h>
 110
 111 #ifdef __sparc64__
 112 #include <dev/ofw/ofw_bus.h>
 113 #include <dev/ofw/openfirm.h>
 114 #include <machine/ofw_machdep.h>
 115 #include <machine/ver.h>
 116 #endif
 117
 118 #include <dev/pci/pcireg.h>
 119 #include <dev/pci/pcivar.h>
 120
 121 #include <dev/bge/if_bgereg.h>
 122
 123 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 124 #define ETHER_MIN_NOPAD         (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
 125
 126 MODULE_DEPEND(bge, pci, 1, 1, 1);
 127 MODULE_DEPEND(bge, ether, 1, 1, 1);
 128 MODULE_DEPEND(bge, miibus, 1, 1, 1);
 129
 130 /* "device miibus" required.  See GENERIC if you get errors here. */
 131 #include "miibus_if.h"
 132
 133 /*
 134  * Various supported device vendors/types and their names. Note: the
 135  * spec seems to indicate that the hardware still has Alteon's vendor
 136  * ID burned into it, though it will always be overriden by the vendor
 137  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 138  */
 139 static const struct bge_type {
 140         uint16_t        bge_vid;
 141         uint16_t        bge_did;
 142 } bge_devs[] = {
 143         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5700 },
 144         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5701 },
 145
 146         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1000 },
 147         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1002 },
 148         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC9100 },
 149
 150         { APPLE_VENDORID,       APPLE_DEVICE_BCM5701 },
 151
 152         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5700 },
 153         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5701 },
 154         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702 },
 155         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702_ALT },
 156         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702X },
 157         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703 },
 158         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703_ALT },
 159         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703X },
 160         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704C },
 161         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S },
 162         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S_ALT },
 163         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705 },
 164         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705F },
 165         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705K },
 166         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M },
 167         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M_ALT },
 168         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714C },
 169         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714S },
 170         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715 },
 171         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715S },
 172         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5720 },
 173         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5721 },
 174         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5722 },
 175         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5723 },
 176         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750 },
 177         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750M },
 178         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751 },
 179         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751F },
 180         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751M },
 181         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752 },
 182         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752M },
 183         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753 },
 184         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753F },
 185         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753M },
 186         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754 },
 187         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754M },
 188         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755 },
 189         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755M },
 190         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5756 },
 191         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761 },
 192         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761E },
 193         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761S },
 194         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761SE },
 195         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5764 },
 196         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780 },
 197         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780S },
 198         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5781 },
 199         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5782 },
 200         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5784 },
 201         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785F },
 202         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785G },
 203         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5786 },
 204         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787 },
 205         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787F },
 206         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787M },
 207         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5788 },
 208         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5789 },
 209         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901 },
 210         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901A2 },
 211         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5903M },
 212         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906 },
 213         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906M },
 214         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57760 },
 215         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57780 },
 216         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57788 },
 217         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57790 },
 218
 219         { SK_VENDORID,          SK_DEVICEID_ALTIMA },
 220
 221         { TC_VENDORID,          TC_DEVICEID_3C996 },
 222
 223         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE4 },
 224         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE5 },
 225         { FJTSU_VENDORID,       FJTSU_DEVICEID_PP250450 },
 226
 227         { 0, 0 }
 228 };
 229
 230 static const struct bge_vendor {
 231         uint16_t        v_id;
 232         const char      *v_name;
 233 } bge_vendors[] = {
 234         { ALTEON_VENDORID,      "Alteon" },
 235         { ALTIMA_VENDORID,      "Altima" },
 236         { APPLE_VENDORID,       "Apple" },
 237         { BCOM_VENDORID,        "Broadcom" },
 238         { SK_VENDORID,          "SysKonnect" },
 239         { TC_VENDORID,          "3Com" },
 240         { FJTSU_VENDORID,       "Fujitsu" },
 241
 242         { 0, NULL }
 243 };
 244
 245 static const struct bge_revision {
 246         uint32_t        br_chipid;
 247         const char      *br_name;
 248 } bge_revisions[] = {
 249         { BGE_CHIPID_BCM5700_A0,        "BCM5700 A0" },
 250         { BGE_CHIPID_BCM5700_A1,        "BCM5700 A1" },
 251         { BGE_CHIPID_BCM5700_B0,        "BCM5700 B0" },
 252         { BGE_CHIPID_BCM5700_B1,        "BCM5700 B1" },
 253         { BGE_CHIPID_BCM5700_B2,        "BCM5700 B2" },
 254         { BGE_CHIPID_BCM5700_B3,        "BCM5700 B3" },
 255         { BGE_CHIPID_BCM5700_ALTIMA,    "BCM5700 Altima" },
 256         { BGE_CHIPID_BCM5700_C0,        "BCM5700 C0" },
 257         { BGE_CHIPID_BCM5701_A0,        "BCM5701 A0" },
 258         { BGE_CHIPID_BCM5701_B0,        "BCM5701 B0" },
 259         { BGE_CHIPID_BCM5701_B2,        "BCM5701 B2" },
 260         { BGE_CHIPID_BCM5701_B5,        "BCM5701 B5" },
 261         { BGE_CHIPID_BCM5703_A0,        "BCM5703 A0" },
 262         { BGE_CHIPID_BCM5703_A1,        "BCM5703 A1" },
 263         { BGE_CHIPID_BCM5703_A2,        "BCM5703 A2" },
 264         { BGE_CHIPID_BCM5703_A3,        "BCM5703 A3" },
 265         { BGE_CHIPID_BCM5703_B0,        "BCM5703 B0" },
 266         { BGE_CHIPID_BCM5704_A0,        "BCM5704 A0" },
 267         { BGE_CHIPID_BCM5704_A1,        "BCM5704 A1" },
 268         { BGE_CHIPID_BCM5704_A2,        "BCM5704 A2" },
 269         { BGE_CHIPID_BCM5704_A3,        "BCM5704 A3" },
 270         { BGE_CHIPID_BCM5704_B0,        "BCM5704 B0" },
 271         { BGE_CHIPID_BCM5705_A0,        "BCM5705 A0" },
 272         { BGE_CHIPID_BCM5705_A1,        "BCM5705 A1" },
 273         { BGE_CHIPID_BCM5705_A2,        "BCM5705 A2" },
 274         { BGE_CHIPID_BCM5705_A3,        "BCM5705 A3" },
 275         { BGE_CHIPID_BCM5750_A0,        "BCM5750 A0" },
 276         { BGE_CHIPID_BCM5750_A1,        "BCM5750 A1" },
 277         { BGE_CHIPID_BCM5750_A3,        "BCM5750 A3" },
 278         { BGE_CHIPID_BCM5750_B0,        "BCM5750 B0" },
 279         { BGE_CHIPID_BCM5750_B1,        "BCM5750 B1" },
 280         { BGE_CHIPID_BCM5750_C0,        "BCM5750 C0" },
 281         { BGE_CHIPID_BCM5750_C1,        "BCM5750 C1" },
 282         { BGE_CHIPID_BCM5750_C2,        "BCM5750 C2" },
 283         { BGE_CHIPID_BCM5714_A0,        "BCM5714 A0" },
 284         { BGE_CHIPID_BCM5752_A0,        "BCM5752 A0" },
 285         { BGE_CHIPID_BCM5752_A1,        "BCM5752 A1" },
 286         { BGE_CHIPID_BCM5752_A2,        "BCM5752 A2" },
 287         { BGE_CHIPID_BCM5714_B0,        "BCM5714 B0" },
 288         { BGE_CHIPID_BCM5714_B3,        "BCM5714 B3" },
 289         { BGE_CHIPID_BCM5715_A0,        "BCM5715 A0" },
 290         { BGE_CHIPID_BCM5715_A1,        "BCM5715 A1" },
 291         { BGE_CHIPID_BCM5715_A3,        "BCM5715 A3" },
 292         { BGE_CHIPID_BCM5755_A0,        "BCM5755 A0" },
 293         { BGE_CHIPID_BCM5755_A1,        "BCM5755 A1" },
 294         { BGE_CHIPID_BCM5755_A2,        "BCM5755 A2" },
 295         { BGE_CHIPID_BCM5722_A0,        "BCM5722 A0" },
 296         { BGE_CHIPID_BCM5761_A0,        "BCM5761 A0" },
 297         { BGE_CHIPID_BCM5761_A1,        "BCM5761 A1" },
 298         { BGE_CHIPID_BCM5784_A0,        "BCM5784 A0" },
 299         { BGE_CHIPID_BCM5784_A1,        "BCM5784 A1" },
 300         /* 5754 and 5787 share the same ASIC ID */
 301         { BGE_CHIPID_BCM5787_A0,        "BCM5754/5787 A0" },
 302         { BGE_CHIPID_BCM5787_A1,        "BCM5754/5787 A1" },
 303         { BGE_CHIPID_BCM5787_A2,        "BCM5754/5787 A2" },
 304         { BGE_CHIPID_BCM5906_A1,        "BCM5906 A1" },
 305         { BGE_CHIPID_BCM5906_A2,        "BCM5906 A2" },
 306         { BGE_CHIPID_BCM57780_A0,       "BCM57780 A0" },
 307         { BGE_CHIPID_BCM57780_A1,       "BCM57780 A1" },
 308
 309         { 0, NULL }
 310 };
 311
 312 /*
 313  * Some defaults for major revisions, so that newer steppings
 314  * that we don't know about have a shot at working.
 315  */
 316 static const struct bge_revision bge_majorrevs[] = {
 317         { BGE_ASICREV_BCM5700,          "unknown BCM5700" },
 318         { BGE_ASICREV_BCM5701,          "unknown BCM5701" },
 319         { BGE_ASICREV_BCM5703,          "unknown BCM5703" },
 320         { BGE_ASICREV_BCM5704,          "unknown BCM5704" },
 321         { BGE_ASICREV_BCM5705,          "unknown BCM5705" },
 322         { BGE_ASICREV_BCM5750,          "unknown BCM5750" },
 323         { BGE_ASICREV_BCM5714_A0,       "unknown BCM5714" },
 324         { BGE_ASICREV_BCM5752,          "unknown BCM5752" },
 325         { BGE_ASICREV_BCM5780,          "unknown BCM5780" },
 326         { BGE_ASICREV_BCM5714,          "unknown BCM5714" },
 327         { BGE_ASICREV_BCM5755,          "unknown BCM5755" },
 328         { BGE_ASICREV_BCM5761,          "unknown BCM5761" },
 329         { BGE_ASICREV_BCM5784,          "unknown BCM5784" },
 330         { BGE_ASICREV_BCM5785,          "unknown BCM5785" },
 331         /* 5754 and 5787 share the same ASIC ID */
 332         { BGE_ASICREV_BCM5787,          "unknown BCM5754/5787" },
 333         { BGE_ASICREV_BCM5906,          "unknown BCM5906" },
 334         { BGE_ASICREV_BCM57780,         "unknown BCM57780" },
 335
 336         { 0, NULL }
 337 };
 338
 339 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 340 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 341 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 342 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 343 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 344 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 345
 346 const struct bge_revision * bge_lookup_rev(uint32_t);
 347 const struct bge_vendor * bge_lookup_vendor(uint16_t);
 348
 349 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 350
 351 static int bge_probe(device_t);
 352 static int bge_attach(device_t);
 353 static int bge_detach(device_t);
 354 static int bge_suspend(device_t);
 355 static int bge_resume(device_t);
 356 static void bge_release_resources(struct bge_softc *);
 357 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 358 static int bge_dma_alloc(device_t);
 359 static void bge_dma_free(struct bge_softc *);
 360
 361 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
 362 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 363 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 364 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 365 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
 366
 367 static void bge_txeof(struct bge_softc *, uint16_t);
 368 static int bge_rxeof(struct bge_softc *, uint16_t, int);
 369
 370 static void bge_asf_driver_up (struct bge_softc *);
 371 static void bge_tick(void *);
 372 static void bge_stats_update(struct bge_softc *);
 373 static void bge_stats_update_regs(struct bge_softc *);
 374 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
 375     uint16_t *);
 376 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 377
 378 static void bge_intr(void *);
 379 static int bge_msi_intr(void *);
 380 static void bge_intr_task(void *, int);
 381 static void bge_start_locked(struct ifnet *);
 382 static void bge_start(struct ifnet *);
 383 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
 384 static void bge_init_locked(struct bge_softc *);
 385 static void bge_init(void *);
 386 static void bge_stop(struct bge_softc *);
 387 static void bge_watchdog(struct bge_softc *);
 388 static int bge_shutdown(device_t);
 389 static int bge_ifmedia_upd_locked(struct ifnet *);
 390 static int bge_ifmedia_upd(struct ifnet *);
 391 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 392
 393 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 394 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 395
 396 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
 397 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
 398
 399 static void bge_setpromisc(struct bge_softc *);
 400 static void bge_setmulti(struct bge_softc *);
 401 static void bge_setvlan(struct bge_softc *);
 402
 403 static int bge_newbuf_std(struct bge_softc *, int);
 404 static int bge_newbuf_jumbo(struct bge_softc *, int);
 405 static int bge_init_rx_ring_std(struct bge_softc *);
 406 static void bge_free_rx_ring_std(struct bge_softc *);
 407 static int bge_init_rx_ring_jumbo(struct bge_softc *);
 408 static void bge_free_rx_ring_jumbo(struct bge_softc *);
 409 static void bge_free_tx_ring(struct bge_softc *);
 410 static int bge_init_tx_ring(struct bge_softc *);
 411
 412 static int bge_chipinit(struct bge_softc *);
 413 static int bge_blockinit(struct bge_softc *);
 414
 415 static int bge_has_eaddr(struct bge_softc *);
 416 static uint32_t bge_readmem_ind(struct bge_softc *, int);
 417 static void bge_writemem_ind(struct bge_softc *, int, int);
 418 static void bge_writembx(struct bge_softc *, int, int);
 419 #ifdef notdef
 420 static uint32_t bge_readreg_ind(struct bge_softc *, int);
 421 #endif
 422 static void bge_writemem_direct(struct bge_softc *, int, int);
 423 static void bge_writereg_ind(struct bge_softc *, int, int);
 424 static void bge_set_max_readrq(struct bge_softc *);
 425
 426 static int bge_miibus_readreg(device_t, int, int);
 427 static int bge_miibus_writereg(device_t, int, int, int);
 428 static void bge_miibus_statchg(device_t);
 429 #ifdef DEVICE_POLLING
 430 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 431 #endif
 432
 433 #define BGE_RESET_START 1
 434 #define BGE_RESET_STOP  2
 435 static void bge_sig_post_reset(struct bge_softc *, int);
 436 static void bge_sig_legacy(struct bge_softc *, int);
 437 static void bge_sig_pre_reset(struct bge_softc *, int);
 438 static int bge_reset(struct bge_softc *);
 439 static void bge_link_upd(struct bge_softc *);
 440
 441 /*
 442  * The BGE_REGISTER_DEBUG option is only for low-level debugging.  It may
 443  * leak information to untrusted users.  It is also known to cause alignment
 444  * traps on certain architectures.
 445  */
 446 #ifdef BGE_REGISTER_DEBUG
 447 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 448 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
 449 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
 450 #endif
 451 static void bge_add_sysctls(struct bge_softc *);
 452 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
 453
 454 static device_method_t bge_methods[] = {
 455         /* Device interface */
 456         DEVMETHOD(device_probe,         bge_probe),
 457         DEVMETHOD(device_attach,        bge_attach),
 458         DEVMETHOD(device_detach,        bge_detach),
 459         DEVMETHOD(device_shutdown,      bge_shutdown),
 460         DEVMETHOD(device_suspend,       bge_suspend),
 461         DEVMETHOD(device_resume,        bge_resume),
 462
 463         /* bus interface */
 464         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 465         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 466
 467         /* MII interface */
 468         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 469         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 470         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 471
 472         { 0, 0 }
 473 };
 474
 475 static driver_t bge_driver = {
 476         "bge",
 477         bge_methods,
 478         sizeof(struct bge_softc)
 479 };
 480
 481 static devclass_t bge_devclass;
 482
 483 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
 484 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 485
 486 static int bge_allow_asf = 1;
 487
 488 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
 489
 490 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
 491 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
 492         "Allow ASF mode if available");
 493
 494 #define SPARC64_BLADE_1500_MODEL        "SUNW,Sun-Blade-1500"
 495 #define SPARC64_BLADE_1500_PATH_BGE     "/pci@1f,700000/network@2"
 496 #define SPARC64_BLADE_2500_MODEL        "SUNW,Sun-Blade-2500"
 497 #define SPARC64_BLADE_2500_PATH_BGE     "/pci@1c,600000/network@3"
 498 #define SPARC64_OFW_SUBVENDOR           "subsystem-vendor-id"
 499
 500 static int
 501 bge_has_eaddr(struct bge_softc *sc)
 502 {
 503 #ifdef __sparc64__
 504         char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
 505         device_t dev;
 506         uint32_t subvendor;
 507
 508         dev = sc->bge_dev;
 509
 510         /*
 511          * The on-board BGEs found in sun4u machines aren't fitted with
 512          * an EEPROM which means that we have to obtain the MAC address
 513          * via OFW and that some tests will always fail.  We distinguish
 514          * such BGEs by the subvendor ID, which also has to be obtained
 515          * from OFW instead of the PCI configuration space as the latter
 516          * indicates Broadcom as the subvendor of the netboot interface.
 517          * For early Blade 1500 and 2500 we even have to check the OFW
 518          * device path as the subvendor ID always defaults to Broadcom
 519          * there.
 520          */
 521         if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
 522             &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
 523             subvendor == SUN_VENDORID)
 524                 return (0);
 525         memset(buf, 0, sizeof(buf));
 526         if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
 527                 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
 528                     strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
 529                         return (0);
 530                 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
 531                     strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
 532                         return (0);
 533         }
 534 #endif
 535         return (1);
 536 }
 537
 538 static uint32_t
 539 bge_readmem_ind(struct bge_softc *sc, int off)
 540 {
 541         device_t dev;
 542         uint32_t val;
 543
 544         dev = sc->bge_dev;
 545
 546         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 547         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 548         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 549         return (val);
 550 }
 551
 552 static void
 553 bge_writemem_ind(struct bge_softc *sc, int off, int val)
 554 {
 555         device_t dev;
 556
 557         dev = sc->bge_dev;
 558
 559         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 560         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 561         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 562 }
 563
 564 /*
 565  * PCI Express only
 566  */
 567 static void
 568 bge_set_max_readrq(struct bge_softc *sc)
 569 {
 570         device_t dev;
 571         uint16_t val;
 572
 573         dev = sc->bge_dev;
 574
 575         val = pci_read_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
 576         if ((val & PCIM_EXP_CTL_MAX_READ_REQUEST) !=
 577             BGE_PCIE_DEVCTL_MAX_READRQ_4096) {
 578                 if (bootverbose)
 579                         device_printf(dev, "adjust device control 0x%04x ",
 580                             val);
 581                 val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST;
 582                 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096;
 583                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL,
 584                     val, 2);
 585                 if (bootverbose)
 586                         printf("-> 0x%04x\n", val);
 587         }
 588 }
 589
 590 #ifdef notdef
 591 static uint32_t
 592 bge_readreg_ind(struct bge_softc *sc, int off)
 593 {
 594         device_t dev;
 595
 596         dev = sc->bge_dev;
 597
 598         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 599         return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 600 }
 601 #endif
 602
 603 static void
 604 bge_writereg_ind(struct bge_softc *sc, int off, int val)
 605 {
 606         device_t dev;
 607
 608         dev = sc->bge_dev;
 609
 610         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 611         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 612 }
 613
 614 static void
 615 bge_writemem_direct(struct bge_softc *sc, int off, int val)
 616 {
 617         CSR_WRITE_4(sc, off, val);
 618 }
 619
 620 static void
 621 bge_writembx(struct bge_softc *sc, int off, int val)
 622 {
 623         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 624                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 625
 626         CSR_WRITE_4(sc, off, val);
 627 }
 628
 629 /*
 630  * Map a single buffer address.
 631  */
 632
 633 static void
 634 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 635 {
 636         struct bge_dmamap_arg *ctx;
 637
 638         if (error)
 639                 return;
 640
 641         ctx = arg;
 642
 643         if (nseg > ctx->bge_maxsegs) {
 644                 ctx->bge_maxsegs = 0;
 645                 return;
 646         }
 647
 648         ctx->bge_busaddr = segs->ds_addr;
 649 }
 650
 651 static uint8_t
 652 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 653 {
 654         uint32_t access, byte = 0;
 655         int i;
 656
 657         /* Lock. */
 658         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 659         for (i = 0; i < 8000; i++) {
 660                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 661                         break;
 662                 DELAY(20);
 663         }
 664         if (i == 8000)
 665                 return (1);
 666
 667         /* Enable access. */
 668         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 669         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 670
 671         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 672         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 673         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 674                 DELAY(10);
 675                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 676                         DELAY(10);
 677                         break;
 678                 }
 679         }
 680
 681         if (i == BGE_TIMEOUT * 10) {
 682                 if_printf(sc->bge_ifp, "nvram read timed out\n");
 683                 return (1);
 684         }
 685
 686         /* Get result. */
 687         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 688
 689         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 690
 691         /* Disable access. */
 692         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 693
 694         /* Unlock. */
 695         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 696         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 697
 698         return (0);
 699 }
 700
 701 /*
 702  * Read a sequence of bytes from NVRAM.
 703  */
 704 static int
 705 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 706 {
 707         int err = 0, i;
 708         uint8_t byte = 0;
 709
 710         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 711                 return (1);
 712
 713         for (i = 0; i < cnt; i++) {
 714                 err = bge_nvram_getbyte(sc, off + i, &byte);
 715                 if (err)
 716                         break;
 717                 *(dest + i) = byte;
 718         }
 719
 720         return (err ? 1 : 0);
 721 }
 722
 723 /*
 724  * Read a byte of data stored in the EEPROM at address 'addr.' The
 725  * BCM570x supports both the traditional bitbang interface and an
 726  * auto access interface for reading the EEPROM. We use the auto
 727  * access method.
 728  */
 729 static uint8_t
 730 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 731 {
 732         int i;
 733         uint32_t byte = 0;
 734
 735         /*
 736          * Enable use of auto EEPROM access so we can avoid
 737          * having to use the bitbang method.
 738          */
 739         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 740
 741         /* Reset the EEPROM, load the clock period. */
 742         CSR_WRITE_4(sc, BGE_EE_ADDR,
 743             BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 744         DELAY(20);
 745
 746         /* Issue the read EEPROM command. */
 747         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 748
 749         /* Wait for completion */
 750         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 751                 DELAY(10);
 752                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 753                         break;
 754         }
 755
 756         if (i == BGE_TIMEOUT * 10) {
 757                 device_printf(sc->bge_dev, "EEPROM read timed out\n");
 758                 return (1);
 759         }
 760
 761         /* Get result. */
 762         byte = CSR_READ_4(sc, BGE_EE_DATA);
 763
 764         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 765
 766         return (0);
 767 }
 768
 769 /*
 770  * Read a sequence of bytes from the EEPROM.
 771  */
 772 static int
 773 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 774 {
 775         int i, error = 0;
 776         uint8_t byte = 0;
 777
 778         for (i = 0; i < cnt; i++) {
 779                 error = bge_eeprom_getbyte(sc, off + i, &byte);
 780                 if (error)
 781                         break;
 782                 *(dest + i) = byte;
 783         }
 784
 785         return (error ? 1 : 0);
 786 }
 787
 788 static int
 789 bge_miibus_readreg(device_t dev, int phy, int reg)
 790 {
 791         struct bge_softc *sc;
 792         uint32_t val, autopoll;
 793         int i;
 794
 795         sc = device_get_softc(dev);
 796
 797         /*
 798          * Broadcom's own driver always assumes the internal
 799          * PHY is at GMII address 1. On some chips, the PHY responds
 800          * to accesses at all addresses, which could cause us to
 801          * bogusly attach the PHY 32 times at probe type. Always
 802          * restricting the lookup to address 1 is simpler than
 803          * trying to figure out which chips revisions should be
 804          * special-cased.
 805          */
 806         if (phy != 1)
 807                 return (0);
 808
 809         /* Reading with autopolling on may trigger PCI errors */
 810         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 811         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 812                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 813                 DELAY(40);
 814         }
 815
 816         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 817             BGE_MIPHY(phy) | BGE_MIREG(reg));
 818
 819         for (i = 0; i < BGE_TIMEOUT; i++) {
 820                 DELAY(10);
 821                 val = CSR_READ_4(sc, BGE_MI_COMM);
 822                 if (!(val & BGE_MICOMM_BUSY))
 823                         break;
 824         }
 825
 826         if (i == BGE_TIMEOUT) {
 827                 device_printf(sc->bge_dev,
 828                     "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
 829                     phy, reg, val);
 830                 val = 0;
 831                 goto done;
 832         }
 833
 834         DELAY(5);
 835         val = CSR_READ_4(sc, BGE_MI_COMM);
 836
 837 done:
 838         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 839                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 840                 DELAY(40);
 841         }
 842
 843         if (val & BGE_MICOMM_READFAIL)
 844                 return (0);
 845
 846         return (val & 0xFFFF);
 847 }
 848
 849 static int
 850 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 851 {
 852         struct bge_softc *sc;
 853         uint32_t autopoll;
 854         int i;
 855
 856         sc = device_get_softc(dev);
 857
 858         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 859             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 860                 return(0);
 861
 862         /* Reading with autopolling on may trigger PCI errors */
 863         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 864         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 865                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 866                 DELAY(40);
 867         }
 868
 869         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 870             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 871
 872         for (i = 0; i < BGE_TIMEOUT; i++) {
 873                 DELAY(10);
 874                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 875                         DELAY(5);
 876                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 877                         break;
 878                 }
 879         }
 880
 881         if (i == BGE_TIMEOUT) {
 882                 device_printf(sc->bge_dev,
 883                     "PHY write timed out (phy %d, reg %d, val %d)\n",
 884                     phy, reg, val);
 885                 return (0);
 886         }
 887
 888         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 889                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 890                 DELAY(40);
 891         }
 892
 893         return (0);
 894 }
 895
 896 static void
 897 bge_miibus_statchg(device_t dev)
 898 {
 899         struct bge_softc *sc;
 900         struct mii_data *mii;
 901         sc = device_get_softc(dev);
 902         mii = device_get_softc(sc->bge_miibus);
 903
 904         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 905         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 906             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
 907                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 908         else
 909                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 910
 911         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
 912                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 913         else
 914                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 915 }
 916
 917 /*
 918  * Intialize a standard receive ring descriptor.
 919  */
 920 static int
 921 bge_newbuf_std(struct bge_softc *sc, int i)
 922 {
 923         struct mbuf *m;
 924         struct bge_rx_bd *r;
 925         bus_dma_segment_t segs[1];
 926         bus_dmamap_t map;
 927         int error, nsegs;
 928
 929         m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
 930         if (m == NULL)
 931                 return (ENOBUFS);
 932         m->m_len = m->m_pkthdr.len = MCLBYTES;
 933         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 934                 m_adj(m, ETHER_ALIGN);
 935
 936         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
 937             sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
 938         if (error != 0) {
 939                 m_freem(m);
 940                 return (error);
 941         }
 942         if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 943                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 944                     sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
 945                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 946                     sc->bge_cdata.bge_rx_std_dmamap[i]);
 947         }
 948         map = sc->bge_cdata.bge_rx_std_dmamap[i];
 949         sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
 950         sc->bge_cdata.bge_rx_std_sparemap = map;
 951         sc->bge_cdata.bge_rx_std_chain[i] = m;
 952         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
 953         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
 954         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
 955         r->bge_flags = BGE_RXBDFLAG_END;
 956         r->bge_len = segs[0].ds_len;
 957         r->bge_idx = i;
 958
 959         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 960             sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
 961
 962         return (0);
 963 }
 964
 965 /*
 966  * Initialize a jumbo receive ring descriptor. This allocates
 967  * a jumbo buffer from the pool managed internally by the driver.
 968  */
 969 static int
 970 bge_newbuf_jumbo(struct bge_softc *sc, int i)
 971 {
 972         bus_dma_segment_t segs[BGE_NSEG_JUMBO];
 973         bus_dmamap_t map;
 974         struct bge_extrx_bd *r;
 975         struct mbuf *m;
 976         int error, nsegs;
 977
 978         MGETHDR(m, M_DONTWAIT, MT_DATA);
 979         if (m == NULL)
 980                 return (ENOBUFS);
 981
 982         m_cljget(m, M_DONTWAIT, MJUM9BYTES);
 983         if (!(m->m_flags & M_EXT)) {
 984                 m_freem(m);
 985                 return (ENOBUFS);
 986         }
 987         m->m_len = m->m_pkthdr.len = MJUM9BYTES;
 988         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 989                 m_adj(m, ETHER_ALIGN);
 990
 991         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
 992             sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
 993         if (error != 0) {
 994                 m_freem(m);
 995                 return (error);
 996         }
 997
 998         if (sc->bge_cdata.bge_rx_jumbo_chain[i] == NULL) {
 999                 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1000                     sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1001                 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1002                     sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1003         }
1004         map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1005         sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1006             sc->bge_cdata.bge_rx_jumbo_sparemap;
1007         sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1008         sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1009         /*
1010          * Fill in the extended RX buffer descriptor.
1011          */
1012         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1013         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1014         r->bge_idx = i;
1015         r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1016         switch (nsegs) {
1017         case 4:
1018                 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1019                 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1020                 r->bge_len3 = segs[3].ds_len;
1021         case 3:
1022                 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1023                 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1024                 r->bge_len2 = segs[2].ds_len;
1025         case 2:
1026                 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1027                 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1028                 r->bge_len1 = segs[1].ds_len;
1029         case 1:
1030                 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1031                 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1032                 r->bge_len0 = segs[0].ds_len;
1033                 break;
1034         default:
1035                 panic("%s: %d segments\n", __func__, nsegs);
1036         }
1037
1038         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1039             sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1040
1041         return (0);
1042 }
1043
1044 /*
1045  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1046  * that's 1MB or memory, which is a lot. For now, we fill only the first
1047  * 256 ring entries and hope that our CPU is fast enough to keep up with
1048  * the NIC.
1049  */
1050 static int
1051 bge_init_rx_ring_std(struct bge_softc *sc)
1052 {
1053         int error, i;
1054
1055         bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1056         sc->bge_std = 0;
1057         for (i = 0; i < BGE_SSLOTS; i++) {
1058                 if ((error = bge_newbuf_std(sc, i)) != 0)
1059                         return (error);
1060                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1061         };
1062
1063         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1064             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1065
1066         sc->bge_std = i - 1;
1067         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1068
1069         return (0);
1070 }
1071
1072 static void
1073 bge_free_rx_ring_std(struct bge_softc *sc)
1074 {
1075         int i;
1076
1077         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1078                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1079                         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1080                             sc->bge_cdata.bge_rx_std_dmamap[i],
1081                             BUS_DMASYNC_POSTREAD);
1082                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1083                             sc->bge_cdata.bge_rx_std_dmamap[i]);
1084                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1085                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1086                 }
1087                 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1088                     sizeof(struct bge_rx_bd));
1089         }
1090 }
1091
1092 static int
1093 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1094 {
1095         struct bge_rcb *rcb;
1096         int error, i;
1097
1098         bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1099         sc->bge_jumbo = 0;
1100         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1101                 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1102                         return (error);
1103                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1104         };
1105
1106         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1107             sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1108
1109         sc->bge_jumbo = i - 1;
1110
1111         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1112         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1113                                     BGE_RCB_FLAG_USE_EXT_RX_BD);
1114         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1115
1116         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1117
1118         return (0);
1119 }
1120
1121 static void
1122 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1123 {
1124         int i;
1125
1126         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1127                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1128                         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1129                             sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1130                             BUS_DMASYNC_POSTREAD);
1131                         bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1132                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1133                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1134                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1135                 }
1136                 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1137                     sizeof(struct bge_extrx_bd));
1138         }
1139 }
1140
1141 static void
1142 bge_free_tx_ring(struct bge_softc *sc)
1143 {
1144         int i;
1145
1146         if (sc->bge_ldata.bge_tx_ring == NULL)
1147                 return;
1148
1149         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1150                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1151                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1152                             sc->bge_cdata.bge_tx_dmamap[i],
1153                             BUS_DMASYNC_POSTWRITE);
1154                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1155                             sc->bge_cdata.bge_tx_dmamap[i]);
1156                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1157                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1158                 }
1159                 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1160                     sizeof(struct bge_tx_bd));
1161         }
1162 }
1163
1164 static int
1165 bge_init_tx_ring(struct bge_softc *sc)
1166 {
1167         sc->bge_txcnt = 0;
1168         sc->bge_tx_saved_considx = 0;
1169
1170         bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1171         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1172             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1173
1174         /* Initialize transmit producer index for host-memory send ring. */
1175         sc->bge_tx_prodidx = 0;
1176         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1177
1178         /* 5700 b2 errata */
1179         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1180                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1181
1182         /* NIC-memory send ring not used; initialize to zero. */
1183         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1184         /* 5700 b2 errata */
1185         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1186                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1187
1188         return (0);
1189 }
1190
1191 static void
1192 bge_setpromisc(struct bge_softc *sc)
1193 {
1194         struct ifnet *ifp;
1195
1196         BGE_LOCK_ASSERT(sc);
1197
1198         ifp = sc->bge_ifp;
1199
1200         /* Enable or disable promiscuous mode as needed. */
1201         if (ifp->if_flags & IFF_PROMISC)
1202                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1203         else
1204                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1205 }
1206
1207 static void
1208 bge_setmulti(struct bge_softc *sc)
1209 {
1210         struct ifnet *ifp;
1211         struct ifmultiaddr *ifma;
1212         uint32_t hashes[4] = { 0, 0, 0, 0 };
1213         int h, i;
1214
1215         BGE_LOCK_ASSERT(sc);
1216
1217         ifp = sc->bge_ifp;
1218
1219         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1220                 for (i = 0; i < 4; i++)
1221                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1222                 return;
1223         }
1224
1225         /* First, zot all the existing filters. */
1226         for (i = 0; i < 4; i++)
1227                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1228
1229         /* Now program new ones. */
1230         if_maddr_rlock(ifp);
1231         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1232                 if (ifma->ifma_addr->sa_family != AF_LINK)
1233                         continue;
1234                 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1235                     ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1236                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1237         }
1238         if_maddr_runlock(ifp);
1239
1240         for (i = 0; i < 4; i++)
1241                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1242 }
1243
1244 static void
1245 bge_setvlan(struct bge_softc *sc)
1246 {
1247         struct ifnet *ifp;
1248
1249         BGE_LOCK_ASSERT(sc);
1250
1251         ifp = sc->bge_ifp;
1252
1253         /* Enable or disable VLAN tag stripping as needed. */
1254         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1255                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1256         else
1257                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1258 }
1259
1260 static void
1261 bge_sig_pre_reset(sc, type)
1262         struct bge_softc *sc;
1263         int type;
1264 {
1265         /*
1266          * Some chips don't like this so only do this if ASF is enabled
1267          */
1268         if (sc->bge_asf_mode)
1269                 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1270
1271         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1272                 switch (type) {
1273                 case BGE_RESET_START:
1274                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1275                         break;
1276                 case BGE_RESET_STOP:
1277                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1278                         break;
1279                 }
1280         }
1281 }
1282
1283 static void
1284 bge_sig_post_reset(sc, type)
1285         struct bge_softc *sc;
1286         int type;
1287 {
1288         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1289                 switch (type) {
1290                 case BGE_RESET_START:
1291                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001);
1292                         /* START DONE */
1293                         break;
1294                 case BGE_RESET_STOP:
1295                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002);
1296                         break;
1297                 }
1298         }
1299 }
1300
1301 static void
1302 bge_sig_legacy(sc, type)
1303         struct bge_softc *sc;
1304         int type;
1305 {
1306         if (sc->bge_asf_mode) {
1307                 switch (type) {
1308                 case BGE_RESET_START:
1309                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1310                         break;
1311                 case BGE_RESET_STOP:
1312                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1313                         break;
1314                 }
1315         }
1316 }
1317
1318 void bge_stop_fw(struct bge_softc *);
1319 void
1320 bge_stop_fw(sc)
1321         struct bge_softc *sc;
1322 {
1323         int i;
1324
1325         if (sc->bge_asf_mode) {
1326                 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE);
1327                 CSR_WRITE_4(sc, BGE_CPU_EVENT,
1328                     CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
1329
1330                 for (i = 0; i < 100; i++ ) {
1331                         if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14)))
1332                                 break;
1333                         DELAY(10);
1334                 }
1335         }
1336 }
1337
1338 /*
1339  * Do endian, PCI and DMA initialization.
1340  */
1341 static int
1342 bge_chipinit(struct bge_softc *sc)
1343 {
1344         uint32_t dma_rw_ctl;
1345         uint16_t val;
1346         int i;
1347
1348         /* Set endianness before we access any non-PCI registers. */
1349         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1350
1351         /* Clear the MAC control register */
1352         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1353
1354         /*
1355          * Clear the MAC statistics block in the NIC's
1356          * internal memory.
1357          */
1358         for (i = BGE_STATS_BLOCK;
1359             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1360                 BGE_MEMWIN_WRITE(sc, i, 0);
1361
1362         for (i = BGE_STATUS_BLOCK;
1363             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1364                 BGE_MEMWIN_WRITE(sc, i, 0);
1365
1366         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1367                 /*
1368                  *  Fix data corruption caused by non-qword write with WB.
1369                  *  Fix master abort in PCI mode.
1370                  *  Fix PCI latency timer.
1371                  */
1372                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1373                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1374                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1375         }
1376
1377         /*
1378          * Set up the PCI DMA control register.
1379          */
1380         dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1381             BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1382         if (sc->bge_flags & BGE_FLAG_PCIE) {
1383                 /* Read watermark not used, 128 bytes for write. */
1384                 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1385         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1386                 if (BGE_IS_5714_FAMILY(sc)) {
1387                         /* 256 bytes for read and write. */
1388                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1389                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1390                         dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1391                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1392                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1393                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1394                         /*
1395                          * In the BCM5703, the DMA read watermark should
1396                          * be set to less than or equal to the maximum
1397                          * memory read byte count of the PCI-X command
1398                          * register.
1399                          */
1400                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1401                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1402                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1403                         /* 1536 bytes for read, 384 bytes for write. */
1404                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1405                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1406                 } else {
1407                         /* 384 bytes for read and write. */
1408                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1409                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1410                             0x0F;
1411                 }
1412                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1413                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1414                         uint32_t tmp;
1415
1416                         /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1417                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1418                         if (tmp == 6 || tmp == 7)
1419                                 dma_rw_ctl |=
1420                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1421
1422                         /* Set PCI-X DMA write workaround. */
1423                         dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1424                 }
1425         } else {
1426                 /* Conventional PCI bus: 256 bytes for read and write. */
1427                 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1428                     BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1429
1430                 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1431                     sc->bge_asicrev != BGE_ASICREV_BCM5750)
1432                         dma_rw_ctl |= 0x0F;
1433         }
1434         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1435             sc->bge_asicrev == BGE_ASICREV_BCM5701)
1436                 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1437                     BGE_PCIDMARWCTL_ASRT_ALL_BE;
1438         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1439             sc->bge_asicrev == BGE_ASICREV_BCM5704)
1440                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1441         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1442
1443         /*
1444          * Set up general mode register.
1445          */
1446         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
1447             BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1448             BGE_MODECTL_TX_NO_PHDR_CSUM);
1449
1450         /*
1451          * BCM5701 B5 have a bug causing data corruption when using
1452          * 64-bit DMA reads, which can be terminated early and then
1453          * completed later as 32-bit accesses, in combination with
1454          * certain bridges.
1455          */
1456         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1457             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1458                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1459
1460         /*
1461          * Tell the firmware the driver is running
1462          */
1463         if (sc->bge_asf_mode & ASF_STACKUP)
1464                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
1465
1466         /*
1467          * Disable memory write invalidate.  Apparently it is not supported
1468          * properly by these devices.  Also ensure that INTx isn't disabled,
1469          * as these chips need it even when using MSI.
1470          */
1471         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1472             PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
1473
1474         /* Set the timer prescaler (always 66Mhz) */
1475         CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1476
1477         /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1478         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1479                 DELAY(40);      /* XXX */
1480
1481                 /* Put PHY into ready state */
1482                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1483                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1484                 DELAY(40);
1485         }
1486
1487         return (0);
1488 }
1489
1490 static int
1491 bge_blockinit(struct bge_softc *sc)
1492 {
1493         struct bge_rcb *rcb;
1494         bus_size_t vrcb;
1495         bge_hostaddr taddr;
1496         uint32_t val;
1497         int i;
1498
1499         /*
1500          * Initialize the memory window pointer register so that
1501          * we can access the first 32K of internal NIC RAM. This will
1502          * allow us to set up the TX send ring RCBs and the RX return
1503          * ring RCBs, plus other things which live in NIC memory.
1504          */
1505         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1506
1507         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1508
1509         if (!(BGE_IS_5705_PLUS(sc))) {
1510                 /* Configure mbuf memory pool */
1511                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1512                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1513                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1514                 else
1515                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1516
1517                 /* Configure DMA resource pool */
1518                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1519                     BGE_DMA_DESCRIPTORS);
1520                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1521         }
1522
1523         /* Configure mbuf pool watermarks */
1524         if (!BGE_IS_5705_PLUS(sc)) {
1525                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1526                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1527                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1528         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1529                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1530                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1531                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1532         } else {
1533                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1534                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1535                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1536         }
1537
1538         /* Configure DMA resource watermarks */
1539         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1540         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1541
1542         /* Enable buffer manager */
1543         if (!(BGE_IS_5705_PLUS(sc))) {
1544                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1545                     BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN);
1546
1547                 /* Poll for buffer manager start indication */
1548                 for (i = 0; i < BGE_TIMEOUT; i++) {
1549                         DELAY(10);
1550                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1551                                 break;
1552                 }
1553
1554                 if (i == BGE_TIMEOUT) {
1555                         device_printf(sc->bge_dev,
1556                             "buffer manager failed to start\n");
1557                         return (ENXIO);
1558                 }
1559         }
1560
1561         /* Enable flow-through queues */
1562         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1563         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1564
1565         /* Wait until queue initialization is complete */
1566         for (i = 0; i < BGE_TIMEOUT; i++) {
1567                 DELAY(10);
1568                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1569                         break;
1570         }
1571
1572         if (i == BGE_TIMEOUT) {
1573                 device_printf(sc->bge_dev, "flow-through queue init failed\n");
1574                 return (ENXIO);
1575         }
1576
1577         /* Initialize the standard RX ring control block */
1578         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1579         rcb->bge_hostaddr.bge_addr_lo =
1580             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1581         rcb->bge_hostaddr.bge_addr_hi =
1582             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1583         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1584             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1585         if (BGE_IS_5705_PLUS(sc))
1586                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1587         else
1588                 rcb->bge_maxlen_flags =
1589                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1590         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1591         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1592         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1593
1594         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1595         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1596
1597         /*
1598          * Initialize the jumbo RX ring control block
1599          * We set the 'ring disabled' bit in the flags
1600          * field until we're actually ready to start
1601          * using this ring (i.e. once we set the MTU
1602          * high enough to require it).
1603          */
1604         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1605                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1606
1607                 rcb->bge_hostaddr.bge_addr_lo =
1608                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1609                 rcb->bge_hostaddr.bge_addr_hi =
1610                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1611                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1612                     sc->bge_cdata.bge_rx_jumbo_ring_map,
1613                     BUS_DMASYNC_PREREAD);
1614                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1615                     BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1616                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1617                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1618                     rcb->bge_hostaddr.bge_addr_hi);
1619                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1620                     rcb->bge_hostaddr.bge_addr_lo);
1621
1622                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1623                     rcb->bge_maxlen_flags);
1624                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1625
1626                 /* Set up dummy disabled mini ring RCB */
1627                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1628                 rcb->bge_maxlen_flags =
1629                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1630                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1631                     rcb->bge_maxlen_flags);
1632         }
1633
1634         /*
1635          * Set the BD ring replentish thresholds. The recommended
1636          * values are 1/8th the number of descriptors allocated to
1637          * each ring.
1638          * XXX The 5754 requires a lower threshold, so it might be a
1639          * requirement of all 575x family chips.  The Linux driver sets
1640          * the lower threshold for all 5705 family chips as well, but there
1641          * are reports that it might not need to be so strict.
1642          *
1643          * XXX Linux does some extra fiddling here for the 5906 parts as
1644          * well.
1645          */
1646         if (BGE_IS_5705_PLUS(sc))
1647                 val = 8;
1648         else
1649                 val = BGE_STD_RX_RING_CNT / 8;
1650         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1651         if (BGE_IS_JUMBO_CAPABLE(sc))
1652                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1653                     BGE_JUMBO_RX_RING_CNT/8);
1654
1655         /*
1656          * Disable all unused send rings by setting the 'ring disabled'
1657          * bit in the flags field of all the TX send ring control blocks.
1658          * These are located in NIC memory.
1659          */
1660         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1661         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1662                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1663                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1664                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1665                 vrcb += sizeof(struct bge_rcb);
1666         }
1667
1668         /* Configure TX RCB 0 (we use only the first ring) */
1669         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1670         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1671         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1672         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1673         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1674             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1675         if (!(BGE_IS_5705_PLUS(sc)))
1676                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1677                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1678
1679         /* Disable all unused RX return rings */
1680         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1681         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1682                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1683                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1684                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1685                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1686                     BGE_RCB_FLAG_RING_DISABLED));
1687                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1688                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1689                     (i * (sizeof(uint64_t))), 0);
1690                 vrcb += sizeof(struct bge_rcb);
1691         }
1692
1693         /* Initialize RX ring indexes */
1694         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1695         if (BGE_IS_JUMBO_CAPABLE(sc))
1696                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1697         if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1698                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1699
1700         /*
1701          * Set up RX return ring 0
1702          * Note that the NIC address for RX return rings is 0x00000000.
1703          * The return rings live entirely within the host, so the
1704          * nicaddr field in the RCB isn't used.
1705          */
1706         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1707         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1708         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1709         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1710         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1711         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1712             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1713
1714         /* Set random backoff seed for TX */
1715         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1716             IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1717             IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1718             IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1719             BGE_TX_BACKOFF_SEED_MASK);
1720
1721         /* Set inter-packet gap */
1722         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1723
1724         /*
1725          * Specify which ring to use for packets that don't match
1726          * any RX rules.
1727          */
1728         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1729
1730         /*
1731          * Configure number of RX lists. One interrupt distribution
1732          * list, sixteen active lists, one bad frames class.
1733          */
1734         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1735
1736         /* Inialize RX list placement stats mask. */
1737         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1738         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1739
1740         /* Disable host coalescing until we get it set up */
1741         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1742
1743         /* Poll to make sure it's shut down. */
1744         for (i = 0; i < BGE_TIMEOUT; i++) {
1745                 DELAY(10);
1746                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1747                         break;
1748         }
1749
1750         if (i == BGE_TIMEOUT) {
1751                 device_printf(sc->bge_dev,
1752                     "host coalescing engine failed to idle\n");
1753                 return (ENXIO);
1754         }
1755
1756         /* Set up host coalescing defaults */
1757         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1758         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1759         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1760         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1761         if (!(BGE_IS_5705_PLUS(sc))) {
1762                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1763                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1764         }
1765         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1766         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1767
1768         /* Set up address of statistics block */
1769         if (!(BGE_IS_5705_PLUS(sc))) {
1770                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1771                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1772                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1773                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1774                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1775                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1776                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1777         }
1778
1779         /* Set up address of status block */
1780         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1781             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1782         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1783             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1784         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1785         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1786
1787         /* Set up status block size. */
1788         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1789             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
1790                 val = BGE_STATBLKSZ_FULL;
1791         else
1792                 val = BGE_STATBLKSZ_32BYTE;
1793
1794         /* Turn on host coalescing state machine */
1795         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1796
1797         /* Turn on RX BD completion state machine and enable attentions */
1798         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1799             BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
1800
1801         /* Turn on RX list placement state machine */
1802         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1803
1804         /* Turn on RX list selector state machine. */
1805         if (!(BGE_IS_5705_PLUS(sc)))
1806                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1807
1808         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1809             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1810             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1811             BGE_MACMODE_FRMHDR_DMA_ENB;
1812
1813         if (sc->bge_flags & BGE_FLAG_TBI)
1814                 val |= BGE_PORTMODE_TBI;
1815         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1816                 val |= BGE_PORTMODE_GMII;
1817         else
1818                 val |= BGE_PORTMODE_MII;
1819
1820         /* Turn on DMA, clear stats */
1821         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1822
1823         /* Set misc. local control, enable interrupts on attentions */
1824         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1825
1826 #ifdef notdef
1827         /* Assert GPIO pins for PHY reset */
1828         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
1829             BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
1830         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
1831             BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
1832 #endif
1833
1834         /* Turn on DMA completion state machine */
1835         if (!(BGE_IS_5705_PLUS(sc)))
1836                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1837
1838         val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
1839
1840         /* Enable host coalescing bug fix. */
1841         if (BGE_IS_5755_PLUS(sc))
1842                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1843
1844         /* Turn on write DMA state machine */
1845         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1846         DELAY(40);
1847
1848         /* Turn on read DMA state machine */
1849         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1850         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1851             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1852             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1853                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1854                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1855                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1856         if (sc->bge_flags & BGE_FLAG_PCIE)
1857                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1858         if (sc->bge_flags & BGE_FLAG_TSO)
1859                 val |= BGE_RDMAMODE_TSO4_ENABLE;
1860         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1861         DELAY(40);
1862
1863         /* Turn on RX data completion state machine */
1864         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1865
1866         /* Turn on RX BD initiator state machine */
1867         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1868
1869         /* Turn on RX data and RX BD initiator state machine */
1870         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1871
1872         /* Turn on Mbuf cluster free state machine */
1873         if (!(BGE_IS_5705_PLUS(sc)))
1874                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1875
1876         /* Turn on send BD completion state machine */
1877         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1878
1879         /* Turn on send data completion state machine */
1880         val = BGE_SDCMODE_ENABLE;
1881         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1882                 val |= BGE_SDCMODE_CDELAY;
1883         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1884
1885         /* Turn on send data initiator state machine */
1886         if (sc->bge_flags & BGE_FLAG_TSO)
1887                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08);
1888         else
1889                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1890
1891         /* Turn on send BD initiator state machine */
1892         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1893
1894         /* Turn on send BD selector state machine */
1895         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1896
1897         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1898         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1899             BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
1900
1901         /* ack/clear link change events */
1902         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1903             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1904             BGE_MACSTAT_LINK_CHANGED);
1905         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1906
1907         /* Enable PHY auto polling (for MII/GMII only) */
1908         if (sc->bge_flags & BGE_FLAG_TBI) {
1909                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1910         } else {
1911                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16));
1912                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1913                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
1914                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1915                             BGE_EVTENB_MI_INTERRUPT);
1916         }
1917
1918         /*
1919          * Clear any pending link state attention.
1920          * Otherwise some link state change events may be lost until attention
1921          * is cleared by bge_intr() -> bge_link_upd() sequence.
1922          * It's not necessary on newer BCM chips - perhaps enabling link
1923          * state change attentions implies clearing pending attention.
1924          */
1925         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1926             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1927             BGE_MACSTAT_LINK_CHANGED);
1928
1929         /* Enable link state change attentions. */
1930         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1931
1932         return (0);
1933 }
1934
1935 const struct bge_revision *
1936 bge_lookup_rev(uint32_t chipid)
1937 {
1938         const struct bge_revision *br;
1939
1940         for (br = bge_revisions; br->br_name != NULL; br++) {
1941                 if (br->br_chipid == chipid)
1942                         return (br);
1943         }
1944
1945         for (br = bge_majorrevs; br->br_name != NULL; br++) {
1946                 if (br->br_chipid == BGE_ASICREV(chipid))
1947                         return (br);
1948         }
1949
1950         return (NULL);
1951 }
1952
1953 const struct bge_vendor *
1954 bge_lookup_vendor(uint16_t vid)
1955 {
1956         const struct bge_vendor *v;
1957
1958         for (v = bge_vendors; v->v_name != NULL; v++)
1959                 if (v->v_id == vid)
1960                         return (v);
1961
1962         panic("%s: unknown vendor %d", __func__, vid);
1963         return (NULL);
1964 }
1965
1966 /*
1967  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1968  * against our list and return its name if we find a match.
1969  *
1970  * Note that since the Broadcom controller contains VPD support, we
1971  * try to get the device name string from the controller itself instead
1972  * of the compiled-in string. It guarantees we'll always announce the
1973  * right product name. We fall back to the compiled-in string when
1974  * VPD is unavailable or corrupt.
1975  */
1976 static int
1977 bge_probe(device_t dev)
1978 {
1979         const struct bge_type *t = bge_devs;
1980         struct bge_softc *sc = device_get_softc(dev);
1981         uint16_t vid, did;
1982
1983         sc->bge_dev = dev;
1984         vid = pci_get_vendor(dev);
1985         did = pci_get_device(dev);
1986         while(t->bge_vid != 0) {
1987                 if ((vid == t->bge_vid) && (did == t->bge_did)) {
1988                         char model[64], buf[96];
1989                         const struct bge_revision *br;
1990                         const struct bge_vendor *v;
1991                         uint32_t id;
1992
1993                         id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1994                             BGE_PCIMISCCTL_ASICREV_SHIFT;
1995                         if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG)
1996                                 id = pci_read_config(dev,
1997                                     BGE_PCI_PRODID_ASICREV, 4);
1998                         br = bge_lookup_rev(id);
1999                         v = bge_lookup_vendor(vid);
2000                         {
2001 #if __FreeBSD_version > 700024
2002                                 const char *pname;
2003
2004                                 if (bge_has_eaddr(sc) &&
2005                                     pci_get_vpd_ident(dev, &pname) == 0)
2006                                         snprintf(model, 64, "%s", pname);
2007                                 else
2008 #endif
2009                                         snprintf(model, 64, "%s %s",
2010                                             v->v_name,
2011                                             br != NULL ? br->br_name :
2012                                             "NetXtreme Ethernet Controller");
2013                         }
2014                         snprintf(buf, 96, "%s, %sASIC rev. %#08x", model,
2015                             br != NULL ? "" : "unknown ", id);
2016                         device_set_desc_copy(dev, buf);
2017                         return (0);
2018                 }
2019                 t++;
2020         }
2021
2022         return (ENXIO);
2023 }
2024
2025 static void
2026 bge_dma_free(struct bge_softc *sc)
2027 {
2028         int i;
2029
2030         /* Destroy DMA maps for RX buffers. */
2031         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2032                 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2033                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2034                             sc->bge_cdata.bge_rx_std_dmamap[i]);
2035         }
2036         if (sc->bge_cdata.bge_rx_std_sparemap)
2037                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2038                     sc->bge_cdata.bge_rx_std_sparemap);
2039
2040         /* Destroy DMA maps for jumbo RX buffers. */
2041         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2042                 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2043                         bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2044                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2045         }
2046         if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2047                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2048                     sc->bge_cdata.bge_rx_jumbo_sparemap);
2049
2050         /* Destroy DMA maps for TX buffers. */
2051         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2052                 if (sc->bge_cdata.bge_tx_dmamap[i])
2053                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2054                             sc->bge_cdata.bge_tx_dmamap[i]);
2055         }
2056
2057         if (sc->bge_cdata.bge_rx_mtag)
2058                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2059         if (sc->bge_cdata.bge_tx_mtag)
2060                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2061
2062
2063         /* Destroy standard RX ring. */
2064         if (sc->bge_cdata.bge_rx_std_ring_map)
2065                 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2066                     sc->bge_cdata.bge_rx_std_ring_map);
2067         if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
2068                 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2069                     sc->bge_ldata.bge_rx_std_ring,
2070                     sc->bge_cdata.bge_rx_std_ring_map);
2071
2072         if (sc->bge_cdata.bge_rx_std_ring_tag)
2073                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2074
2075         /* Destroy jumbo RX ring. */
2076         if (sc->bge_cdata.bge_rx_jumbo_ring_map)
2077                 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2078                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2079
2080         if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
2081             sc->bge_ldata.bge_rx_jumbo_ring)
2082                 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2083                     sc->bge_ldata.bge_rx_jumbo_ring,
2084                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2085
2086         if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2087                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2088
2089         /* Destroy RX return ring. */
2090         if (sc->bge_cdata.bge_rx_return_ring_map)
2091                 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2092                     sc->bge_cdata.bge_rx_return_ring_map);
2093
2094         if (sc->bge_cdata.bge_rx_return_ring_map &&
2095             sc->bge_ldata.bge_rx_return_ring)
2096                 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2097                     sc->bge_ldata.bge_rx_return_ring,
2098                     sc->bge_cdata.bge_rx_return_ring_map);
2099
2100         if (sc->bge_cdata.bge_rx_return_ring_tag)
2101                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2102
2103         /* Destroy TX ring. */
2104         if (sc->bge_cdata.bge_tx_ring_map)
2105                 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2106                     sc->bge_cdata.bge_tx_ring_map);
2107
2108         if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
2109                 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2110                     sc->bge_ldata.bge_tx_ring,
2111                     sc->bge_cdata.bge_tx_ring_map);
2112
2113         if (sc->bge_cdata.bge_tx_ring_tag)
2114                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2115
2116         /* Destroy status block. */
2117         if (sc->bge_cdata.bge_status_map)
2118                 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2119                     sc->bge_cdata.bge_status_map);
2120
2121         if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
2122                 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2123                     sc->bge_ldata.bge_status_block,
2124                     sc->bge_cdata.bge_status_map);
2125
2126         if (sc->bge_cdata.bge_status_tag)
2127                 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2128
2129         /* Destroy statistics block. */
2130         if (sc->bge_cdata.bge_stats_map)
2131                 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2132                     sc->bge_cdata.bge_stats_map);
2133
2134         if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2135                 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2136                     sc->bge_ldata.bge_stats,
2137                     sc->bge_cdata.bge_stats_map);
2138
2139         if (sc->bge_cdata.bge_stats_tag)
2140                 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2141
2142         /* Destroy the parent tag. */
2143         if (sc->bge_cdata.bge_parent_tag)
2144                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2145 }
2146
2147 static int
2148 bge_dma_alloc(device_t dev)
2149 {
2150         struct bge_dmamap_arg ctx;
2151         struct bge_softc *sc;
2152         bus_addr_t lowaddr;
2153         bus_size_t sbsz, txsegsz, txmaxsegsz;
2154         int i, error;
2155
2156         sc = device_get_softc(dev);
2157
2158         lowaddr = BUS_SPACE_MAXADDR;
2159         if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2160                 lowaddr = BGE_DMA_MAXADDR;
2161         if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0)
2162                 lowaddr = BUS_SPACE_MAXADDR_32BIT;
2163         /*
2164          * Allocate the parent bus DMA tag appropriate for PCI.
2165          */
2166         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2167             1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2168             NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2169             0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2170
2171         if (error != 0) {
2172                 device_printf(sc->bge_dev,
2173                     "could not allocate parent dma tag\n");
2174                 return (ENOMEM);
2175         }
2176
2177         /*
2178          * Create tag for Tx mbufs.
2179          */
2180         if (sc->bge_flags & BGE_FLAG_TSO) {
2181                 txsegsz = BGE_TSOSEG_SZ;
2182                 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
2183         } else {
2184                 txsegsz = MCLBYTES;
2185                 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
2186         }
2187         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1,
2188             0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2189             txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
2190             &sc->bge_cdata.bge_tx_mtag);
2191
2192         if (error) {
2193                 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
2194                 return (ENOMEM);
2195         }
2196
2197         /*
2198          * Create tag for Rx mbufs.
2199          */
2200         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
2201             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
2202             MCLBYTES, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
2203
2204         if (error) {
2205                 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
2206                 return (ENOMEM);
2207         }
2208
2209         /* Create DMA maps for RX buffers. */
2210         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2211             &sc->bge_cdata.bge_rx_std_sparemap);
2212         if (error) {
2213                 device_printf(sc->bge_dev,
2214                     "can't create spare DMA map for RX\n");
2215                 return (ENOMEM);
2216         }
2217         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2218                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2219                             &sc->bge_cdata.bge_rx_std_dmamap[i]);
2220                 if (error) {
2221                         device_printf(sc->bge_dev,
2222                             "can't create DMA map for RX\n");
2223                         return (ENOMEM);
2224                 }
2225         }
2226
2227         /* Create DMA maps for TX buffers. */
2228         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2229                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
2230                             &sc->bge_cdata.bge_tx_dmamap[i]);
2231                 if (error) {
2232                         device_printf(sc->bge_dev,
2233                             "can't create DMA map for TX\n");
2234                         return (ENOMEM);
2235                 }
2236         }
2237
2238         /* Create tag for standard RX ring. */
2239         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2240             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2241             NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0,
2242             NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag);
2243
2244         if (error) {
2245                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2246                 return (ENOMEM);
2247         }
2248
2249         /* Allocate DMA'able memory for standard RX ring. */
2250         error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag,
2251             (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT,
2252             &sc->bge_cdata.bge_rx_std_ring_map);
2253         if (error)
2254                 return (ENOMEM);
2255
2256         bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
2257
2258         /* Load the address of the standard RX ring. */
2259         ctx.bge_maxsegs = 1;
2260         ctx.sc = sc;
2261
2262         error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag,
2263             sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring,
2264             BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2265
2266         if (error)
2267                 return (ENOMEM);
2268
2269         sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr;
2270
2271         /* Create tags for jumbo mbufs. */
2272         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2273                 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2274                     1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2275                     NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
2276                     0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
2277                 if (error) {
2278                         device_printf(sc->bge_dev,
2279                             "could not allocate jumbo dma tag\n");
2280                         return (ENOMEM);
2281                 }
2282
2283                 /* Create tag for jumbo RX ring. */
2284                 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2285                     PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2286                     NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0,
2287                     NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag);
2288
2289                 if (error) {
2290                         device_printf(sc->bge_dev,
2291                             "could not allocate jumbo ring dma tag\n");
2292                         return (ENOMEM);
2293                 }
2294
2295                 /* Allocate DMA'able memory for jumbo RX ring. */
2296                 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2297                     (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
2298                     BUS_DMA_NOWAIT | BUS_DMA_ZERO,
2299                     &sc->bge_cdata.bge_rx_jumbo_ring_map);
2300                 if (error)
2301                         return (ENOMEM);
2302
2303                 /* Load the address of the jumbo RX ring. */
2304                 ctx.bge_maxsegs = 1;
2305                 ctx.sc = sc;
2306
2307                 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2308                     sc->bge_cdata.bge_rx_jumbo_ring_map,
2309                     sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ,
2310                     bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2311
2312                 if (error)
2313                         return (ENOMEM);
2314
2315                 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr;
2316
2317                 /* Create DMA maps for jumbo RX buffers. */
2318                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2319                     0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
2320                 if (error) {
2321                         device_printf(sc->bge_dev,
2322                             "can't create spare DMA map for jumbo RX\n");
2323                         return (ENOMEM);
2324                 }
2325                 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2326                         error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2327                                     0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2328                         if (error) {
2329                                 device_printf(sc->bge_dev,
2330                                     "can't create DMA map for jumbo RX\n");
2331                                 return (ENOMEM);
2332                         }
2333                 }
2334
2335         }
2336
2337         /* Create tag for RX return ring. */
2338         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2339             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2340             NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0,
2341             NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag);
2342
2343         if (error) {
2344                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2345                 return (ENOMEM);
2346         }
2347
2348         /* Allocate DMA'able memory for RX return ring. */
2349         error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag,
2350             (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT,
2351             &sc->bge_cdata.bge_rx_return_ring_map);
2352         if (error)
2353                 return (ENOMEM);
2354
2355         bzero((char *)sc->bge_ldata.bge_rx_return_ring,
2356             BGE_RX_RTN_RING_SZ(sc));
2357
2358         /* Load the address of the RX return ring. */
2359         ctx.bge_maxsegs = 1;
2360         ctx.sc = sc;
2361
2362         error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag,
2363             sc->bge_cdata.bge_rx_return_ring_map,
2364             sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc),
2365             bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2366
2367         if (error)
2368                 return (ENOMEM);
2369
2370         sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr;
2371
2372         /* Create tag for TX ring. */
2373         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2374             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2375             NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL,
2376             &sc->bge_cdata.bge_tx_ring_tag);
2377
2378         if (error) {
2379                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2380                 return (ENOMEM);
2381         }
2382
2383         /* Allocate DMA'able memory for TX ring. */
2384         error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag,
2385             (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT,
2386             &sc->bge_cdata.bge_tx_ring_map);
2387         if (error)
2388                 return (ENOMEM);
2389
2390         bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
2391
2392         /* Load the address of the TX ring. */
2393         ctx.bge_maxsegs = 1;
2394         ctx.sc = sc;
2395
2396         error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag,
2397             sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring,
2398             BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2399
2400         if (error)
2401                 return (ENOMEM);
2402
2403         sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr;
2404
2405         /*
2406          * Create tag for status block.
2407          * Because we only use single Tx/Rx/Rx return ring, use
2408          * minimum status block size except BCM5700 AX/BX which
2409          * seems to want to see full status block size regardless
2410          * of configured number of ring.
2411          */
2412         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2413             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
2414                 sbsz = BGE_STATUS_BLK_SZ;
2415         else
2416                 sbsz = 32;
2417         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2418             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2419             NULL, sbsz, 1, sbsz, 0, NULL, NULL, &sc->bge_cdata.bge_status_tag);
2420
2421         if (error) {
2422                 device_printf(sc->bge_dev,
2423                     "could not allocate status dma tag\n");
2424                 return (ENOMEM);
2425         }
2426
2427         /* Allocate DMA'able memory for status block. */
2428         error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag,
2429             (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT,
2430             &sc->bge_cdata.bge_status_map);
2431         if (error)
2432                 return (ENOMEM);
2433
2434         bzero((char *)sc->bge_ldata.bge_status_block, sbsz);
2435
2436         /* Load the address of the status block. */
2437         ctx.sc = sc;
2438         ctx.bge_maxsegs = 1;
2439
2440         error = bus_dmamap_load(sc->bge_cdata.bge_status_tag,
2441             sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block,
2442             sbsz, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2443
2444         if (error)
2445                 return (ENOMEM);
2446
2447         sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr;
2448
2449         /* Create tag for statistics block. */
2450         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2451             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2452             NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL,
2453             &sc->bge_cdata.bge_stats_tag);
2454
2455         if (error) {
2456                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2457                 return (ENOMEM);
2458         }
2459
2460         /* Allocate DMA'able memory for statistics block. */
2461         error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag,
2462             (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT,
2463             &sc->bge_cdata.bge_stats_map);
2464         if (error)
2465                 return (ENOMEM);
2466
2467         bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ);
2468
2469         /* Load the address of the statstics block. */
2470         ctx.sc = sc;
2471         ctx.bge_maxsegs = 1;
2472
2473         error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag,
2474             sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats,
2475             BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2476
2477         if (error)
2478                 return (ENOMEM);
2479
2480         sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr;
2481
2482         return (0);
2483 }
2484
2485 /*
2486  * Return true if this device has more than one port.
2487  */
2488 static int
2489 bge_has_multiple_ports(struct bge_softc *sc)
2490 {
2491         device_t dev = sc->bge_dev;
2492         u_int b, d, f, fscan, s;
2493
2494         d = pci_get_domain(dev);
2495         b = pci_get_bus(dev);
2496         s = pci_get_slot(dev);
2497         f = pci_get_function(dev);
2498         for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
2499                 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
2500                         return (1);
2501         return (0);
2502 }
2503
2504 /*
2505  * Return true if MSI can be used with this device.
2506  */
2507 static int
2508 bge_can_use_msi(struct bge_softc *sc)
2509 {
2510         int can_use_msi = 0;
2511
2512         switch (sc->bge_asicrev) {
2513         case BGE_ASICREV_BCM5714_A0:
2514         case BGE_ASICREV_BCM5714:
2515                 /*
2516                  * Apparently, MSI doesn't work when these chips are
2517                  * configured in single-port mode.
2518                  */
2519                 if (bge_has_multiple_ports(sc))
2520                         can_use_msi = 1;
2521                 break;
2522         case BGE_ASICREV_BCM5750:
2523                 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
2524                     sc->bge_chiprev != BGE_CHIPREV_5750_BX)
2525                         can_use_msi = 1;
2526                 break;
2527         default:
2528                 if (BGE_IS_575X_PLUS(sc))
2529                         can_use_msi = 1;
2530         }
2531         return (can_use_msi);
2532 }
2533
2534 static int
2535 bge_attach(device_t dev)
2536 {
2537         struct ifnet *ifp;
2538         struct bge_softc *sc;
2539         uint32_t hwcfg = 0, misccfg;
2540         u_char eaddr[ETHER_ADDR_LEN];
2541         int error, msicount, reg, rid, trys;
2542
2543         sc = device_get_softc(dev);
2544         sc->bge_dev = dev;
2545
2546         TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
2547
2548         /*
2549          * Map control/status registers.
2550          */
2551         pci_enable_busmaster(dev);
2552
2553         rid = BGE_PCI_BAR0;
2554         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2555             RF_ACTIVE);
2556
2557         if (sc->bge_res == NULL) {
2558                 device_printf (sc->bge_dev, "couldn't map memory\n");
2559                 error = ENXIO;
2560                 goto fail;
2561         }
2562
2563         /* Save various chip information. */
2564         sc->bge_chipid =
2565             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2566             BGE_PCIMISCCTL_ASICREV_SHIFT;
2567         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
2568                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV,
2569                     4);
2570         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2571         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2572
2573         /*
2574          * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the
2575          * 5705 A0 and A1 chips.
2576          */
2577         if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
2578             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2579             sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2580             sc->bge_chipid != BGE_CHIPID_BCM5705_A1)
2581                 sc->bge_flags |= BGE_FLAG_WIRESPEED;
2582
2583         if (bge_has_eaddr(sc))
2584                 sc->bge_flags |= BGE_FLAG_EADDR;
2585
2586         /* Save chipset family. */
2587         switch (sc->bge_asicrev) {
2588         case BGE_ASICREV_BCM5755:
2589         case BGE_ASICREV_BCM5761:
2590         case BGE_ASICREV_BCM5784:
2591         case BGE_ASICREV_BCM5785:
2592         case BGE_ASICREV_BCM5787:
2593         case BGE_ASICREV_BCM57780:
2594                 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2595                     BGE_FLAG_5705_PLUS;
2596                 break;
2597         case BGE_ASICREV_BCM5700:
2598         case BGE_ASICREV_BCM5701:
2599         case BGE_ASICREV_BCM5703:
2600         case BGE_ASICREV_BCM5704:
2601                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2602                 break;
2603         case BGE_ASICREV_BCM5714_A0:
2604         case BGE_ASICREV_BCM5780:
2605         case BGE_ASICREV_BCM5714:
2606                 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */;
2607                 /* FALLTHROUGH */
2608         case BGE_ASICREV_BCM5750:
2609         case BGE_ASICREV_BCM5752:
2610         case BGE_ASICREV_BCM5906:
2611                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2612                 /* FALLTHROUGH */
2613         case BGE_ASICREV_BCM5705:
2614                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2615                 break;
2616         }
2617
2618         /* Set various bug flags. */
2619         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2620             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2621                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
2622         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2623             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2624                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
2625         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2626                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
2627         if (pci_get_subvendor(dev) == DELL_VENDORID)
2628                 sc->bge_flags |= BGE_FLAG_NO_3LED;
2629         if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
2630                 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
2631         if (BGE_IS_5705_PLUS(sc) &&
2632             !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) {
2633                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2634                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2635                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2636                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2637                         if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
2638                             pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
2639                                 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
2640                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
2641                         sc->bge_flags |= BGE_FLAG_BER_BUG;
2642         }
2643
2644         /*
2645          * All controllers that are not 5755 or higher have 4GB
2646          * boundary DMA bug.
2647          * Whenever an address crosses a multiple of the 4GB boundary
2648          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
2649          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
2650          * state machine will lockup and cause the device to hang.
2651          */
2652         if (BGE_IS_5755_PLUS(sc) == 0)
2653                 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
2654
2655         /*
2656          * We could possibly check for BCOM_DEVICEID_BCM5788 in bge_probe()
2657          * but I do not know the DEVICEID for the 5788M.
2658          */
2659         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID;
2660         if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2661             misccfg == BGE_MISCCFG_BOARD_ID_5788M)
2662                 sc->bge_flags |= BGE_FLAG_5788;
2663
2664         /*
2665          * Some controllers seem to require a special firmware to use
2666          * TSO. But the firmware is not available to FreeBSD and Linux
2667          * claims that the TSO performed by the firmware is slower than
2668          * hardware based TSO. Moreover the firmware based TSO has one
2669          * known bug which can't handle TSO if ethernet header + IP/TCP
2670          * header is greater than 80 bytes. The workaround for the TSO
2671          * bug exist but it seems it's too expensive than not using
2672          * TSO at all. Some hardwares also have the TSO bug so limit
2673          * the TSO to the controllers that are not affected TSO issues
2674          * (e.g. 5755 or higher).
2675          */
2676         if (BGE_IS_5755_PLUS(sc)) {
2677                 /*
2678                  * BCM5754 and BCM5787 shares the same ASIC id so
2679                  * explicit device id check is required.
2680                  * Due to unknown reason TSO does not work on BCM5755M.
2681                  */
2682                 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
2683                     pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
2684                     pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
2685                         sc->bge_flags |= BGE_FLAG_TSO;
2686         }
2687
2688         /*
2689          * Check if this is a PCI-X or PCI Express device.
2690          */
2691         if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {
2692                 /*
2693                  * Found a PCI Express capabilities register, this
2694                  * must be a PCI Express device.
2695                  */
2696                 sc->bge_flags |= BGE_FLAG_PCIE;
2697                 sc->bge_expcap = reg;
2698                 bge_set_max_readrq(sc);
2699         } else {
2700                 /*
2701                  * Check if the device is in PCI-X Mode.
2702                  * (This bit is not valid on PCI Express controllers.)
2703                  */
2704                 if (pci_find_extcap(dev, PCIY_PCIX, &reg) == 0)
2705                         sc->bge_pcixcap = reg;
2706                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
2707                     BGE_PCISTATE_PCI_BUSMODE) == 0)
2708                         sc->bge_flags |= BGE_FLAG_PCIX;
2709         }
2710
2711         /*
2712          * The 40bit DMA bug applies to the 5714/5715 controllers and is
2713          * not actually a MAC controller bug but an issue with the embedded
2714          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2715          */
2716         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
2717                 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
2718         /*
2719          * Allocate the interrupt, using MSI if possible.  These devices
2720          * support 8 MSI messages, but only the first one is used in
2721          * normal operation.
2722          */
2723         rid = 0;
2724         if (pci_find_extcap(sc->bge_dev, PCIY_MSI, &reg) == 0) {
2725                 sc->bge_msicap = reg;
2726                 if (bge_can_use_msi(sc)) {
2727                         msicount = pci_msi_count(dev);
2728                         if (msicount > 1)
2729                                 msicount = 1;
2730                 } else
2731                         msicount = 0;
2732                 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
2733                         rid = 1;
2734                         sc->bge_flags |= BGE_FLAG_MSI;
2735                 }
2736         }
2737
2738         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2739             RF_SHAREABLE | RF_ACTIVE);
2740
2741         if (sc->bge_irq == NULL) {
2742                 device_printf(sc->bge_dev, "couldn't map interrupt\n");
2743                 error = ENXIO;
2744                 goto fail;
2745         }
2746
2747         if (bootverbose)
2748                 device_printf(dev,
2749                     "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2750                     sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2751                     (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" :
2752                     ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI"));
2753
2754         BGE_LOCK_INIT(sc, device_get_nameunit(dev));
2755
2756         /* Try to reset the chip. */
2757         if (bge_reset(sc)) {
2758                 device_printf(sc->bge_dev, "chip reset failed\n");
2759                 error = ENXIO;
2760                 goto fail;
2761         }
2762
2763         sc->bge_asf_mode = 0;
2764         if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG)
2765             == BGE_MAGIC_NUMBER)) {
2766                 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG)
2767                     & BGE_HWCFG_ASF) {
2768                         sc->bge_asf_mode |= ASF_ENABLE;
2769                         sc->bge_asf_mode |= ASF_STACKUP;
2770                         if (BGE_IS_575X_PLUS(sc))
2771                                 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
2772                 }
2773         }
2774
2775         /* Try to reset the chip again the nice way. */
2776         bge_stop_fw(sc);
2777         bge_sig_pre_reset(sc, BGE_RESET_STOP);
2778         if (bge_reset(sc)) {
2779                 device_printf(sc->bge_dev, "chip reset failed\n");
2780                 error = ENXIO;
2781                 goto fail;
2782         }
2783
2784         bge_sig_legacy(sc, BGE_RESET_STOP);
2785         bge_sig_post_reset(sc, BGE_RESET_STOP);
2786
2787         if (bge_chipinit(sc)) {
2788                 device_printf(sc->bge_dev, "chip initialization failed\n");
2789                 error = ENXIO;
2790                 goto fail;
2791         }
2792
2793         error = bge_get_eaddr(sc, eaddr);
2794         if (error) {
2795                 device_printf(sc->bge_dev,
2796                     "failed to read station address\n");
2797                 error = ENXIO;
2798                 goto fail;
2799         }
2800
2801         /* 5705 limits RX return ring to 512 entries. */
2802         if (BGE_IS_5705_PLUS(sc))
2803                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2804         else
2805                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2806
2807         if (bge_dma_alloc(dev)) {
2808                 device_printf(sc->bge_dev,
2809                     "failed to allocate DMA resources\n");
2810                 error = ENXIO;
2811                 goto fail;
2812         }
2813
2814         /* Set default tuneable values. */
2815         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2816         sc->bge_rx_coal_ticks = 150;
2817         sc->bge_tx_coal_ticks = 150;
2818         sc->bge_rx_max_coal_bds = 10;
2819         sc->bge_tx_max_coal_bds = 10;
2820
2821         /* Set up ifnet structure */
2822         ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
2823         if (ifp == NULL) {
2824                 device_printf(sc->bge_dev, "failed to if_alloc()\n");
2825                 error = ENXIO;
2826                 goto fail;
2827         }
2828         ifp->if_softc = sc;
2829         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2830         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2831         ifp->if_ioctl = bge_ioctl;
2832         ifp->if_start = bge_start;
2833         ifp->if_init = bge_init;
2834         ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
2835         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2836         IFQ_SET_READY(&ifp->if_snd);
2837         ifp->if_hwassist = BGE_CSUM_FEATURES;
2838         ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
2839             IFCAP_VLAN_MTU;
2840         if ((sc->bge_flags & BGE_FLAG_TSO) != 0) {
2841                 ifp->if_hwassist |= CSUM_TSO;
2842                 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO;
2843         }
2844 #ifdef IFCAP_VLAN_HWCSUM
2845         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
2846 #endif
2847         ifp->if_capenable = ifp->if_capabilities;
2848 #ifdef DEVICE_POLLING
2849         ifp->if_capabilities |= IFCAP_POLLING;
2850 #endif
2851
2852         /*
2853          * 5700 B0 chips do not support checksumming correctly due
2854          * to hardware bugs.
2855          */
2856         if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
2857                 ifp->if_capabilities &= ~IFCAP_HWCSUM;
2858                 ifp->if_capenable &= ~IFCAP_HWCSUM;
2859                 ifp->if_hwassist = 0;
2860         }
2861
2862         /*
2863          * Figure out what sort of media we have by checking the
2864          * hardware config word in the first 32k of NIC internal memory,
2865          * or fall back to examining the EEPROM if necessary.
2866          * Note: on some BCM5700 cards, this value appears to be unset.
2867          * If that's the case, we have to rely on identifying the NIC
2868          * by its PCI subsystem ID, as we do below for the SysKonnect
2869          * SK-9D41.
2870          */
2871         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2872                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2873         else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
2874             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
2875                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2876                     sizeof(hwcfg))) {
2877                         device_printf(sc->bge_dev, "failed to read EEPROM\n");
2878                         error = ENXIO;
2879                         goto fail;
2880                 }
2881                 hwcfg = ntohl(hwcfg);
2882         }
2883
2884         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2885         if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
2886             SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2887                 if (BGE_IS_5714_FAMILY(sc))
2888                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
2889                 else
2890                         sc->bge_flags |= BGE_FLAG_TBI;
2891         }
2892
2893         if (sc->bge_flags & BGE_FLAG_TBI) {
2894                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
2895                     bge_ifmedia_sts);
2896                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
2897                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2898                     0, NULL);
2899                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
2900                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
2901                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2902         } else {
2903                 /*
2904                  * Do transceiver setup and tell the firmware the
2905                  * driver is down so we can try to get access the
2906                  * probe if ASF is running.  Retry a couple of times
2907                  * if we get a conflict with the ASF firmware accessing
2908                  * the PHY.
2909                  */
2910                 trys = 0;
2911                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2912 again:
2913                 bge_asf_driver_up(sc);
2914
2915                 if (mii_phy_probe(dev, &sc->bge_miibus,
2916                     bge_ifmedia_upd, bge_ifmedia_sts)) {
2917                         if (trys++ < 4) {
2918                                 device_printf(sc->bge_dev, "Try again\n");
2919                                 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR,
2920                                     BMCR_RESET);
2921                                 goto again;
2922                         }
2923
2924                         device_printf(sc->bge_dev, "MII without any PHY!\n");
2925                         error = ENXIO;
2926                         goto fail;
2927                 }
2928
2929                 /*
2930                  * Now tell the firmware we are going up after probing the PHY
2931                  */
2932                 if (sc->bge_asf_mode & ASF_STACKUP)
2933                         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2934         }
2935
2936         /*
2937          * When using the BCM5701 in PCI-X mode, data corruption has
2938          * been observed in the first few bytes of some received packets.
2939          * Aligning the packet buffer in memory eliminates the corruption.
2940          * Unfortunately, this misaligns the packet payloads.  On platforms
2941          * which do not support unaligned accesses, we will realign the
2942          * payloads by copying the received packets.
2943          */
2944         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2945             sc->bge_flags & BGE_FLAG_PCIX)
2946                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2947
2948         /*
2949          * Call MI attach routine.
2950          */
2951         ether_ifattach(ifp, eaddr);
2952         callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
2953
2954         /* Tell upper layer we support long frames. */
2955         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2956
2957         /*
2958          * Hookup IRQ last.
2959          */
2960 #if __FreeBSD_version > 700030
2961         if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
2962                 /* Take advantage of single-shot MSI. */
2963                 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
2964                     ~BGE_MSIMODE_ONE_SHOT_DISABLE);
2965                 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
2966                     taskqueue_thread_enqueue, &sc->bge_tq);
2967                 if (sc->bge_tq == NULL) {
2968                         device_printf(dev, "could not create taskqueue.\n");
2969                         ether_ifdetach(ifp);
2970                         error = ENXIO;
2971                         goto fail;
2972                 }
2973                 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq",
2974                     device_get_nameunit(sc->bge_dev));
2975                 error = bus_setup_intr(dev, sc->bge_irq,
2976                     INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
2977                     &sc->bge_intrhand);
2978                 if (error)
2979                         ether_ifdetach(ifp);
2980         } else
2981                 error = bus_setup_intr(dev, sc->bge_irq,
2982                     INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
2983                     &sc->bge_intrhand);
2984 #else
2985         error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2986            bge_intr, sc, &sc->bge_intrhand);
2987 #endif
2988
2989         if (error) {
2990                 bge_detach(dev);
2991                 device_printf(sc->bge_dev, "couldn't set up irq\n");
2992         }
2993
2994         bge_add_sysctls(sc);
2995
2996         return (0);
2997
2998 fail:
2999         bge_release_resources(sc);
3000
3001         return (error);
3002 }
3003
3004 static int
3005 bge_detach(device_t dev)
3006 {
3007         struct bge_softc *sc;
3008         struct ifnet *ifp;
3009
3010         sc = device_get_softc(dev);
3011         ifp = sc->bge_ifp;
3012
3013 #ifdef DEVICE_POLLING
3014         if (ifp->if_capenable & IFCAP_POLLING)
3015                 ether_poll_deregister(ifp);
3016 #endif
3017
3018         BGE_LOCK(sc);
3019         bge_stop(sc);
3020         bge_reset(sc);
3021         BGE_UNLOCK(sc);
3022
3023         callout_drain(&sc->bge_stat_ch);
3024
3025         if (sc->bge_tq)
3026                 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3027         ether_ifdetach(ifp);
3028
3029         if (sc->bge_flags & BGE_FLAG_TBI) {
3030                 ifmedia_removeall(&sc->bge_ifmedia);
3031         } else {
3032                 bus_generic_detach(dev);
3033                 device_delete_child(dev, sc->bge_miibus);
3034         }
3035
3036         bge_release_resources(sc);
3037
3038         return (0);
3039 }
3040
3041 static void
3042 bge_release_resources(struct bge_softc *sc)
3043 {
3044         device_t dev;
3045
3046         dev = sc->bge_dev;
3047
3048         if (sc->bge_tq != NULL)
3049                 taskqueue_free(sc->bge_tq);
3050
3051         if (sc->bge_intrhand != NULL)
3052                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3053
3054         if (sc->bge_irq != NULL)
3055                 bus_release_resource(dev, SYS_RES_IRQ,
3056                     sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
3057
3058         if (sc->bge_flags & BGE_FLAG_MSI)
3059                 pci_release_msi(dev);
3060
3061         if (sc->bge_res != NULL)
3062                 bus_release_resource(dev, SYS_RES_MEMORY,
3063                     BGE_PCI_BAR0, sc->bge_res);
3064
3065         if (sc->bge_ifp != NULL)
3066                 if_free(sc->bge_ifp);
3067
3068         bge_dma_free(sc);
3069
3070         if (mtx_initialized(&sc->bge_mtx))      /* XXX */
3071                 BGE_LOCK_DESTROY(sc);
3072 }
3073
3074 static int
3075 bge_reset(struct bge_softc *sc)
3076 {
3077         device_t dev;
3078         uint32_t cachesize, command, pcistate, reset, val;
3079         void (*write_op)(struct bge_softc *, int, int);
3080         uint16_t devctl;
3081         int i;
3082
3083         dev = sc->bge_dev;
3084
3085         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
3086             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3087                 if (sc->bge_flags & BGE_FLAG_PCIE)
3088                         write_op = bge_writemem_direct;
3089                 else
3090                         write_op = bge_writemem_ind;
3091         } else
3092                 write_op = bge_writereg_ind;
3093
3094         /* Save some important PCI state. */
3095         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
3096         command = pci_read_config(dev, BGE_PCI_CMD, 4);
3097         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3098
3099         pci_write_config(dev, BGE_PCI_MISC_CTL,
3100             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3101             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3102
3103         /* Disable fastboot on controllers that support it. */
3104         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
3105             BGE_IS_5755_PLUS(sc)) {
3106                 if (bootverbose)
3107                         device_printf(sc->bge_dev, "Disabling fastboot\n");
3108                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
3109         }
3110
3111         /*
3112          * Write the magic number to SRAM at offset 0xB50.
3113          * When firmware finishes its initialization it will
3114          * write ~BGE_MAGIC_NUMBER to the same location.
3115          */
3116         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
3117
3118         reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
3119
3120         /* XXX: Broadcom Linux driver. */
3121         if (sc->bge_flags & BGE_FLAG_PCIE) {
3122                 if (CSR_READ_4(sc, 0x7E2C) == 0x60)     /* PCIE 1.0 */
3123                         CSR_WRITE_4(sc, 0x7E2C, 0x20);
3124                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3125                         /* Prevent PCIE link training during global reset */
3126                         CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
3127                         reset |= 1 << 29;
3128                 }
3129         }
3130
3131         /*
3132          * Set GPHY Power Down Override to leave GPHY
3133          * powered up in D0 uninitialized.
3134          */
3135         if (BGE_IS_5705_PLUS(sc))
3136                 reset |= 0x04000000;
3137
3138         /* Issue global reset */
3139         write_op(sc, BGE_MISC_CFG, reset);
3140
3141         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3142                 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3143                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
3144                     val | BGE_VCPU_STATUS_DRV_RESET);
3145                 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
3146                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
3147                     val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
3148         }
3149
3150         DELAY(1000);
3151
3152         /* XXX: Broadcom Linux driver. */
3153         if (sc->bge_flags & BGE_FLAG_PCIE) {
3154                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
3155                         DELAY(500000); /* wait for link training to complete */
3156                         val = pci_read_config(dev, 0xC4, 4);
3157                         pci_write_config(dev, 0xC4, val | (1 << 15), 4);
3158                 }
3159                 devctl = pci_read_config(dev,
3160                     sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
3161                 /* Clear enable no snoop and disable relaxed ordering. */
3162                 devctl &= ~(PCIM_EXP_CTL_RELAXED_ORD_ENABLE |
3163                     PCIM_EXP_CTL_NOSNOOP_ENABLE);
3164                 /* Set PCIE max payload size to 128. */
3165                 devctl &= ~PCIM_EXP_CTL_MAX_PAYLOAD;
3166                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL,
3167                     devctl, 2);
3168                 /* Clear error status. */
3169                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA,
3170                     PCIM_EXP_STA_CORRECTABLE_ERROR |
3171                     PCIM_EXP_STA_NON_FATAL_ERROR | PCIM_EXP_STA_FATAL_ERROR |
3172                     PCIM_EXP_STA_UNSUPPORTED_REQ, 2);
3173         }
3174
3175         /* Reset some of the PCI state that got zapped by reset. */
3176         pci_write_config(dev, BGE_PCI_MISC_CTL,
3177             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3178             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3179         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
3180         pci_write_config(dev, BGE_PCI_CMD, command, 4);
3181         write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
3182         /*
3183          * Disable PCI-X relaxed ordering to ensure status block update
3184          * comes first then packet buffer DMA. Otherwise driver may
3185          * read stale status block.
3186          */
3187         if (sc->bge_flags & BGE_FLAG_PCIX) {
3188                 devctl = pci_read_config(dev,
3189                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
3190                 devctl &= ~PCIXM_COMMAND_ERO;
3191                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
3192                         devctl &= ~PCIXM_COMMAND_MAX_READ;
3193                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
3194                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3195                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
3196                             PCIXM_COMMAND_MAX_READ);
3197                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
3198                 }
3199                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
3200                     devctl, 2);
3201         }
3202         /* Re-enable MSI, if neccesary, and enable the memory arbiter. */
3203         if (BGE_IS_5714_FAMILY(sc)) {
3204                 /* This chip disables MSI on reset. */
3205                 if (sc->bge_flags & BGE_FLAG_MSI) {
3206                         val = pci_read_config(dev,
3207                             sc->bge_msicap + PCIR_MSI_CTRL, 2);
3208                         pci_write_config(dev,
3209                             sc->bge_msicap + PCIR_MSI_CTRL,
3210                             val | PCIM_MSICTRL_MSI_ENABLE, 2);
3211                         val = CSR_READ_4(sc, BGE_MSI_MODE);
3212                         CSR_WRITE_4(sc, BGE_MSI_MODE,
3213                             val | BGE_MSIMODE_ENABLE);
3214                 }
3215                 val = CSR_READ_4(sc, BGE_MARB_MODE);
3216                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
3217         } else
3218                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3219
3220         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3221                 for (i = 0; i < BGE_TIMEOUT; i++) {
3222                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3223                         if (val & BGE_VCPU_STATUS_INIT_DONE)
3224                                 break;
3225                         DELAY(100);
3226                 }
3227                 if (i == BGE_TIMEOUT) {
3228                         device_printf(sc->bge_dev, "reset timed out\n");
3229                         return (1);
3230                 }
3231         } else {
3232                 /*
3233                  * Poll until we see the 1's complement of the magic number.
3234                  * This indicates that the firmware initialization is complete.
3235                  * We expect this to fail if no chip containing the Ethernet
3236                  * address is fitted though.
3237                  */
3238                 for (i = 0; i < BGE_TIMEOUT; i++) {
3239                         DELAY(10);
3240                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
3241                         if (val == ~BGE_MAGIC_NUMBER)
3242                                 break;
3243                 }
3244
3245                 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
3246                         device_printf(sc->bge_dev, "firmware handshake timed out, "
3247                             "found 0x%08x\n", val);
3248         }
3249
3250         /*
3251          * XXX Wait for the value of the PCISTATE register to
3252          * return to its original pre-reset state. This is a
3253          * fairly good indicator of reset completion. If we don't
3254          * wait for the reset to fully complete, trying to read
3255          * from the device's non-PCI registers may yield garbage
3256          * results.
3257          */
3258         for (i = 0; i < BGE_TIMEOUT; i++) {
3259                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
3260                         break;
3261                 DELAY(10);
3262         }
3263
3264         if (sc->bge_flags & BGE_FLAG_PCIE) {
3265                 reset = bge_readmem_ind(sc, 0x7C00);
3266                 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25));
3267         }
3268
3269         /* Fix up byte swapping. */
3270         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
3271             BGE_MODECTL_BYTESWAP_DATA);
3272
3273         /* Tell the ASF firmware we are up */
3274         if (sc->bge_asf_mode & ASF_STACKUP)
3275                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3276
3277         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
3278
3279         /*
3280          * The 5704 in TBI mode apparently needs some special
3281          * adjustment to insure the SERDES drive level is set
3282          * to 1.2V.
3283          */
3284         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
3285             sc->bge_flags & BGE_FLAG_TBI) {
3286                 val = CSR_READ_4(sc, BGE_SERDES_CFG);
3287                 val = (val & ~0xFFF) | 0x880;
3288                 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
3289         }
3290
3291         /* XXX: Broadcom Linux driver. */
3292         if (sc->bge_flags & BGE_FLAG_PCIE &&
3293             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3294                 val = CSR_READ_4(sc, 0x7C00);
3295                 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
3296         }
3297         DELAY(10000);
3298
3299         return(0);
3300 }
3301
3302 /*
3303  * Frame reception handling. This is called if there's a frame
3304  * on the receive return list.
3305  *
3306  * Note: we have to be able to handle two possibilities here:
3307  * 1) the frame is from the jumbo receive ring
3308  * 2) the frame is from the standard receive ring
3309  */
3310
3311 static int
3312 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
3313 {
3314         struct ifnet *ifp;
3315         int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
3316         uint16_t rx_cons;
3317
3318         rx_cons = sc->bge_rx_saved_considx;
3319
3320         /* Nothing to do. */
3321         if (rx_cons == rx_prod)
3322                 return (rx_npkts);
3323
3324         ifp = sc->bge_ifp;
3325
3326         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3327             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
3328         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3329             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
3330         if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
3331             (MCLBYTES - ETHER_ALIGN))
3332                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3333                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
3334
3335         while (rx_cons != rx_prod) {
3336                 struct bge_rx_bd        *cur_rx;
3337                 uint32_t                rxidx;
3338                 struct mbuf             *m = NULL;
3339                 uint16_t                vlan_tag = 0;
3340                 int                     have_tag = 0;
3341
3342 #ifdef DEVICE_POLLING
3343                 if (ifp->if_capenable & IFCAP_POLLING) {
3344                         if (sc->rxcycles <= 0)
3345                                 break;
3346                         sc->rxcycles--;
3347                 }
3348 #endif
3349
3350                 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
3351
3352                 rxidx = cur_rx->bge_idx;
3353                 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
3354
3355                 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
3356                     cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
3357                         have_tag = 1;
3358                         vlan_tag = cur_rx->bge_vlan_tag;
3359                 }
3360
3361                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
3362                         jumbocnt++;
3363                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
3364                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3365                                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3366                                 continue;
3367                         }
3368                         if (bge_newbuf_jumbo(sc, rxidx) != 0) {
3369                                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3370                                 ifp->if_iqdrops++;
3371                                 continue;
3372                         }
3373                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3374                 } else {
3375                         stdcnt++;
3376                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3377                                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3378                                 continue;
3379                         }
3380                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
3381                         if (bge_newbuf_std(sc, rxidx) != 0) {
3382                                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3383                                 ifp->if_iqdrops++;
3384                                 continue;
3385                         }
3386                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3387                 }
3388
3389                 ifp->if_ipackets++;
3390 #ifndef __NO_STRICT_ALIGNMENT
3391                 /*
3392                  * For architectures with strict alignment we must make sure
3393                  * the payload is aligned.
3394                  */
3395                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
3396                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
3397                             cur_rx->bge_len);
3398                         m->m_data += ETHER_ALIGN;
3399                 }
3400 #endif
3401                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3402                 m->m_pkthdr.rcvif = ifp;
3403
3404                 if (ifp->if_capenable & IFCAP_RXCSUM) {
3405                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3406                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3407                                 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
3408                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3409                         }
3410                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
3411                             m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
3412                                 m->m_pkthdr.csum_data =
3413                                     cur_rx->bge_tcp_udp_csum;
3414                                 m->m_pkthdr.csum_flags |=
3415                                     CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
3416                         }
3417                 }
3418
3419                 /*
3420                  * If we received a packet with a vlan tag,
3421                  * attach that information to the packet.
3422                  */
3423                 if (have_tag) {
3424 #if __FreeBSD_version > 700022
3425                         m->m_pkthdr.ether_vtag = vlan_tag;
3426                         m->m_flags |= M_VLANTAG;
3427 #else
3428                         VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag);
3429                         if (m == NULL)
3430                                 continue;
3431 #endif
3432                 }
3433
3434                 if (holdlck != 0) {
3435                         BGE_UNLOCK(sc);
3436                         (*ifp->if_input)(ifp, m);
3437                         BGE_LOCK(sc);
3438                 } else
3439                         (*ifp->if_input)(ifp, m);
3440                 rx_npkts++;
3441
3442                 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
3443                         return (rx_npkts);
3444         }
3445
3446         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3447             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
3448         if (stdcnt > 0)
3449                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3450                     sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
3451
3452         if (jumbocnt > 0)
3453                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3454                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
3455
3456         sc->bge_rx_saved_considx = rx_cons;
3457         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3458         if (stdcnt)
3459                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
3460         if (jumbocnt)
3461                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
3462 #ifdef notyet
3463         /*
3464          * This register wraps very quickly under heavy packet drops.
3465          * If you need correct statistics, you can enable this check.
3466          */
3467         if (BGE_IS_5705_PLUS(sc))
3468                 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3469 #endif
3470         return (rx_npkts);
3471 }
3472
3473 static void
3474 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
3475 {
3476         struct bge_tx_bd *cur_tx = NULL;
3477         struct ifnet *ifp;
3478
3479         BGE_LOCK_ASSERT(sc);
3480
3481         /* Nothing to do. */
3482         if (sc->bge_tx_saved_considx == tx_cons)
3483                 return;
3484
3485         ifp = sc->bge_ifp;
3486
3487         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
3488             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
3489         /*
3490          * Go through our tx ring and free mbufs for those
3491          * frames that have been sent.
3492          */
3493         while (sc->bge_tx_saved_considx != tx_cons) {
3494                 uint32_t                idx = 0;
3495
3496                 idx = sc->bge_tx_saved_considx;
3497                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
3498                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
3499                         ifp->if_opackets++;
3500                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
3501                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
3502                             sc->bge_cdata.bge_tx_dmamap[idx],
3503                             BUS_DMASYNC_POSTWRITE);
3504                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
3505                             sc->bge_cdata.bge_tx_dmamap[idx]);
3506                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
3507                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
3508                 }
3509                 sc->bge_txcnt--;
3510                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3511         }
3512
3513         if (cur_tx != NULL)
3514                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3515         if (sc->bge_txcnt == 0)
3516                 sc->bge_timer = 0;
3517 }
3518
3519 #ifdef DEVICE_POLLING
3520 static int
3521 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3522 {
3523         struct bge_softc *sc = ifp->if_softc;
3524         uint16_t rx_prod, tx_cons;
3525         uint32_t statusword;
3526         int rx_npkts = 0;
3527
3528         BGE_LOCK(sc);
3529         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3530                 BGE_UNLOCK(sc);
3531                 return (rx_npkts);
3532         }
3533
3534         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3535             sc->bge_cdata.bge_status_map,
3536             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3537         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3538         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3539
3540         statusword = atomic_readandclear_32(
3541             &sc->bge_ldata.bge_status_block->bge_status);
3542
3543         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3544             sc->bge_cdata.bge_status_map,
3545             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3546
3547         /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
3548         if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
3549                 sc->bge_link_evt++;
3550
3551         if (cmd == POLL_AND_CHECK_STATUS)
3552                 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3553                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3554                     sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
3555                         bge_link_upd(sc);
3556
3557         sc->rxcycles = count;
3558         rx_npkts = bge_rxeof(sc, rx_prod, 1);
3559         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3560                 BGE_UNLOCK(sc);
3561                 return (rx_npkts);
3562         }
3563         bge_txeof(sc, tx_cons);
3564         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3565                 bge_start_locked(ifp);
3566
3567         BGE_UNLOCK(sc);
3568         return (rx_npkts);
3569 }
3570 #endif /* DEVICE_POLLING */
3571
3572 static int
3573 bge_msi_intr(void *arg)
3574 {
3575         struct bge_softc *sc;
3576
3577         sc = (struct bge_softc *)arg;
3578         /*
3579          * This interrupt is not shared and controller already
3580          * disabled further interrupt.
3581          */
3582         taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
3583         return (FILTER_HANDLED);
3584 }
3585
3586 static void
3587 bge_intr_task(void *arg, int pending)
3588 {
3589         struct bge_softc *sc;
3590         struct ifnet *ifp;
3591         uint32_t status;
3592         uint16_t rx_prod, tx_cons;
3593
3594         sc = (struct bge_softc *)arg;
3595         ifp = sc->bge_ifp;
3596
3597         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3598                 return;
3599
3600         /* Get updated status block. */
3601         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3602             sc->bge_cdata.bge_status_map,
3603             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3604
3605         /* Save producer/consumer indexess. */
3606         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3607         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3608         status = sc->bge_ldata.bge_status_block->bge_status;
3609         sc->bge_ldata.bge_status_block->bge_status = 0;
3610         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3611             sc->bge_cdata.bge_status_map,
3612             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3613         /* Let controller work. */
3614         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3615
3616         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) {
3617                 BGE_LOCK(sc);
3618                 bge_link_upd(sc);
3619                 BGE_UNLOCK(sc);
3620         }
3621         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3622                 /* Check RX return ring producer/consumer. */
3623                 bge_rxeof(sc, rx_prod, 0);
3624         }
3625         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3626                 BGE_LOCK(sc);
3627                 /* Check TX ring producer/consumer. */
3628                 bge_txeof(sc, tx_cons);
3629                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3630                         bge_start_locked(ifp);
3631                 BGE_UNLOCK(sc);
3632         }
3633 }
3634
3635 static void
3636 bge_intr(void *xsc)
3637 {
3638         struct bge_softc *sc;
3639         struct ifnet *ifp;
3640         uint32_t statusword;
3641         uint16_t rx_prod, tx_cons;
3642
3643         sc = xsc;
3644
3645         BGE_LOCK(sc);
3646
3647         ifp = sc->bge_ifp;
3648
3649 #ifdef DEVICE_POLLING
3650         if (ifp->if_capenable & IFCAP_POLLING) {
3651                 BGE_UNLOCK(sc);
3652                 return;
3653         }
3654 #endif
3655
3656         /*
3657          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
3658          * disable interrupts by writing nonzero like we used to, since with
3659          * our current organization this just gives complications and
3660          * pessimizations for re-enabling interrupts.  We used to have races
3661          * instead of the necessary complications.  Disabling interrupts
3662          * would just reduce the chance of a status update while we are
3663          * running (by switching to the interrupt-mode coalescence
3664          * parameters), but this chance is already very low so it is more
3665          * efficient to get another interrupt than prevent it.
3666          *
3667          * We do the ack first to ensure another interrupt if there is a
3668          * status update after the ack.  We don't check for the status
3669          * changing later because it is more efficient to get another
3670          * interrupt than prevent it, not quite as above (not checking is
3671          * a smaller optimization than not toggling the interrupt enable,
3672          * since checking doesn't involve PCI accesses and toggling require
3673          * the status check).  So toggling would probably be a pessimization
3674          * even with MSI.  It would only be needed for using a task queue.
3675          */
3676         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3677
3678         /*
3679          * Do the mandatory PCI flush as well as get the link status.
3680          */
3681         statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
3682
3683         /* Make sure the descriptor ring indexes are coherent. */
3684         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3685             sc->bge_cdata.bge_status_map,
3686             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3687         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3688         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3689         sc->bge_ldata.bge_status_block->bge_status = 0;
3690         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3691             sc->bge_cdata.bge_status_map,
3692             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3693
3694         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3695             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3696             statusword || sc->bge_link_evt)
3697                 bge_link_upd(sc);
3698
3699         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3700                 /* Check RX return ring producer/consumer. */
3701                 bge_rxeof(sc, rx_prod, 1);
3702         }
3703
3704         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3705                 /* Check TX ring producer/consumer. */
3706                 bge_txeof(sc, tx_cons);
3707         }
3708
3709         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3710             !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3711                 bge_start_locked(ifp);
3712
3713         BGE_UNLOCK(sc);
3714 }
3715
3716 static void
3717 bge_asf_driver_up(struct bge_softc *sc)
3718 {
3719         if (sc->bge_asf_mode & ASF_STACKUP) {
3720                 /* Send ASF heartbeat aprox. every 2s */
3721                 if (sc->bge_asf_count)
3722                         sc->bge_asf_count --;
3723                 else {
3724                         sc->bge_asf_count = 2;
3725                         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW,
3726                             BGE_FW_DRV_ALIVE);
3727                         bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4);
3728                         bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3);
3729                         CSR_WRITE_4(sc, BGE_CPU_EVENT,
3730                             CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
3731                 }
3732         }
3733 }
3734
3735 static void
3736 bge_tick(void *xsc)
3737 {
3738         struct bge_softc *sc = xsc;
3739         struct mii_data *mii = NULL;
3740
3741         BGE_LOCK_ASSERT(sc);
3742
3743         /* Synchronize with possible callout reset/stop. */
3744         if (callout_pending(&sc->bge_stat_ch) ||
3745             !callout_active(&sc->bge_stat_ch))
3746                 return;
3747
3748         if (BGE_IS_5705_PLUS(sc))
3749                 bge_stats_update_regs(sc);
3750         else
3751                 bge_stats_update(sc);
3752
3753         if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
3754                 mii = device_get_softc(sc->bge_miibus);
3755                 /*
3756                  * Do not touch PHY if we have link up. This could break
3757                  * IPMI/ASF mode or produce extra input errors
3758                  * (extra errors was reported for bcm5701 & bcm5704).
3759                  */
3760                 if (!sc->bge_link)
3761                         mii_tick(mii);
3762         } else {
3763                 /*
3764                  * Since in TBI mode auto-polling can't be used we should poll
3765                  * link status manually. Here we register pending link event
3766                  * and trigger interrupt.
3767                  */
3768 #ifdef DEVICE_POLLING
3769                 /* In polling mode we poll link state in bge_poll(). */
3770                 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
3771 #endif
3772                 {
3773                 sc->bge_link_evt++;
3774                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3775                     sc->bge_flags & BGE_FLAG_5788)
3776                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3777                 else
3778                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3779                 }
3780         }
3781
3782         bge_asf_driver_up(sc);
3783         bge_watchdog(sc);
3784
3785         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
3786 }
3787
3788 static void
3789 bge_stats_update_regs(struct bge_softc *sc)
3790 {
3791         struct ifnet *ifp;
3792
3793         ifp = sc->bge_ifp;
3794
3795         ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS +
3796             offsetof(struct bge_mac_stats_regs, etherStatsCollisions));
3797
3798         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
3799         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3800         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
3801 }
3802
3803 static void
3804 bge_stats_update(struct bge_softc *sc)
3805 {
3806         struct ifnet *ifp;
3807         bus_size_t stats;
3808         uint32_t cnt;   /* current register value */
3809
3810         ifp = sc->bge_ifp;
3811
3812         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3813
3814 #define READ_STAT(sc, stats, stat) \
3815         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3816
3817         cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
3818         ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
3819         sc->bge_tx_collisions = cnt;
3820
3821         cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
3822         ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
3823         sc->bge_rx_discards = cnt;
3824
3825         cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
3826         ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
3827         sc->bge_tx_discards = cnt;
3828
3829 #undef  READ_STAT
3830 }
3831
3832 /*
3833  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
3834  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
3835  * but when such padded frames employ the bge IP/TCP checksum offload,
3836  * the hardware checksum assist gives incorrect results (possibly
3837  * from incorporating its own padding into the UDP/TCP checksum; who knows).
3838  * If we pad such runts with zeros, the onboard checksum comes out correct.
3839  */
3840 static __inline int
3841 bge_cksum_pad(struct mbuf *m)
3842 {
3843         int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
3844         struct mbuf *last;
3845
3846         /* If there's only the packet-header and we can pad there, use it. */
3847         if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
3848             M_TRAILINGSPACE(m) >= padlen) {
3849                 last = m;
3850         } else {
3851                 /*
3852                  * Walk packet chain to find last mbuf. We will either
3853                  * pad there, or append a new mbuf and pad it.
3854                  */
3855                 for (last = m; last->m_next != NULL; last = last->m_next);
3856                 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
3857                         /* Allocate new empty mbuf, pad it. Compact later. */
3858                         struct mbuf *n;
3859
3860                         MGET(n, M_DONTWAIT, MT_DATA);
3861                         if (n == NULL)
3862                                 return (ENOBUFS);
3863                         n->m_len = 0;
3864                         last->m_next = n;
3865                         last = n;
3866                 }
3867         }
3868
3869         /* Now zero the pad area, to avoid the bge cksum-assist bug. */
3870         memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
3871         last->m_len += padlen;
3872         m->m_pkthdr.len += padlen;
3873
3874         return (0);
3875 }
3876
3877 static struct mbuf *
3878 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss)
3879 {
3880         struct ip *ip;
3881         struct tcphdr *tcp;
3882         struct mbuf *n;
3883         uint16_t hlen;
3884         uint32_t poff;
3885
3886         if (M_WRITABLE(m) == 0) {
3887                 /* Get a writable copy. */
3888                 n = m_dup(m, M_DONTWAIT);
3889                 m_freem(m);
3890                 if (n == NULL)
3891                         return (NULL);
3892                 m = n;
3893         }
3894         m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
3895         if (m == NULL)
3896                 return (NULL);
3897         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
3898         poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
3899         m = m_pullup(m, poff + sizeof(struct tcphdr));
3900         if (m == NULL)
3901                 return (NULL);
3902         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
3903         m = m_pullup(m, poff + (tcp->th_off << 2));
3904         if (m == NULL)
3905                 return (NULL);
3906         /*
3907          * It seems controller doesn't modify IP length and TCP pseudo
3908          * checksum. These checksum computed by upper stack should be 0.
3909          */
3910         *mss = m->m_pkthdr.tso_segsz;
3911         ip->ip_sum = 0;
3912         ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
3913         /* Clear pseudo checksum computed by TCP stack. */
3914         tcp->th_sum = 0;
3915         /*
3916          * Broadcom controllers uses different descriptor format for
3917          * TSO depending on ASIC revision. Due to TSO-capable firmware
3918          * license issue and lower performance of firmware based TSO
3919          * we only support hardware based TSO which is applicable for
3920          * BCM5755 or newer controllers. Hardware based TSO uses 11
3921          * bits to store MSS and upper 5 bits are used to store IP/TCP
3922          * header length(including IP/TCP options). The header length
3923          * is expressed as 32 bits unit.
3924          */
3925         hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
3926         *mss |= (hlen << 11);
3927         return (m);
3928 }
3929
3930 /*
3931  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
3932  * pointers to descriptors.
3933  */
3934 static int
3935 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
3936 {
3937         bus_dma_segment_t       segs[BGE_NSEG_NEW];
3938         bus_dmamap_t            map;
3939         struct bge_tx_bd        *d;
3940         struct mbuf             *m = *m_head;
3941         uint32_t                idx = *txidx;
3942         uint16_t                csum_flags, mss, vlan_tag;
3943         int                     nsegs, i, error;
3944
3945         csum_flags = 0;
3946         mss = 0;
3947         vlan_tag = 0;
3948         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
3949                 *m_head = m = bge_setup_tso(sc, m, &mss);
3950                 if (*m_head == NULL)
3951                         return (ENOBUFS);
3952                 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
3953                     BGE_TXBDFLAG_CPU_POST_DMA;
3954         } else if ((m->m_pkthdr.csum_flags & BGE_CSUM_FEATURES) != 0) {
3955                 if (m->m_pkthdr.csum_flags & CSUM_IP)
3956                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3957                 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
3958                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3959                         if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
3960                             (error = bge_cksum_pad(m)) != 0) {
3961                                 m_freem(m);
3962                                 *m_head = NULL;
3963                                 return (error);
3964                         }
3965                 }
3966                 if (m->m_flags & M_LASTFRAG)
3967                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3968                 else if (m->m_flags & M_FRAG)
3969                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3970         }
3971
3972         if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
3973             sc->bge_forced_collapse > 0 &&
3974             (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
3975                 /*
3976                  * Forcedly collapse mbuf chains to overcome hardware
3977                  * limitation which only support a single outstanding
3978                  * DMA read operation.
3979                  */
3980                 if (sc->bge_forced_collapse == 1)
3981                         m = m_defrag(m, M_DONTWAIT);
3982                 else
3983                         m = m_collapse(m, M_DONTWAIT, sc->bge_forced_collapse);
3984                 if (m == NULL)
3985                         m = *m_head;
3986                 *m_head = m;
3987         }
3988
3989         map = sc->bge_cdata.bge_tx_dmamap[idx];
3990         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
3991             &nsegs, BUS_DMA_NOWAIT);
3992         if (error == EFBIG) {
3993                 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW);
3994                 if (m == NULL) {
3995                         m_freem(*m_head);
3996                         *m_head = NULL;
3997                         return (ENOBUFS);
3998                 }
3999                 *m_head = m;
4000                 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
4001                     m, segs, &nsegs, BUS_DMA_NOWAIT);
4002                 if (error) {
4003                         m_freem(m);
4004                         *m_head = NULL;
4005                         return (error);
4006                 }
4007         } else if (error != 0)
4008                 return (error);
4009
4010         /* Check if we have enough free send BDs. */
4011         if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
4012                 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
4013                 return (ENOBUFS);
4014         }
4015
4016         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
4017
4018 #if __FreeBSD_version > 700022
4019         if (m->m_flags & M_VLANTAG) {
4020                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
4021                 vlan_tag = m->m_pkthdr.ether_vtag;
4022         }
4023 #else
4024         {
4025                 struct m_tag            *mtag;
4026
4027                 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) {
4028                         csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
4029                         vlan_tag = VLAN_TAG_VALUE(mtag);
4030                 }
4031         }
4032 #endif
4033         for (i = 0; ; i++) {
4034                 d = &sc->bge_ldata.bge_tx_ring[idx];
4035                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
4036                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
4037                 d->bge_len = segs[i].ds_len;
4038                 d->bge_flags = csum_flags;
4039                 d->bge_vlan_tag = vlan_tag;
4040                 d->bge_mss = mss;
4041                 if (i == nsegs - 1)
4042                         break;
4043                 BGE_INC(idx, BGE_TX_RING_CNT);
4044         }
4045
4046         /* Mark the last segment as end of packet... */
4047         d->bge_flags |= BGE_TXBDFLAG_END;
4048
4049         /*
4050          * Insure that the map for this transmission
4051          * is placed at the array index of the last descriptor
4052          * in this chain.
4053          */
4054         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
4055         sc->bge_cdata.bge_tx_dmamap[idx] = map;
4056         sc->bge_cdata.bge_tx_chain[idx] = m;
4057         sc->bge_txcnt += nsegs;
4058
4059         BGE_INC(idx, BGE_TX_RING_CNT);
4060         *txidx = idx;
4061
4062         return (0);
4063 }
4064
4065 /*
4066  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4067  * to the mbuf data regions directly in the transmit descriptors.
4068  */
4069 static void
4070 bge_start_locked(struct ifnet *ifp)
4071 {
4072         struct bge_softc *sc;
4073         struct mbuf *m_head;
4074         uint32_t prodidx;
4075         int count;
4076
4077         sc = ifp->if_softc;
4078         BGE_LOCK_ASSERT(sc);
4079
4080         if (!sc->bge_link ||
4081             (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4082             IFF_DRV_RUNNING)
4083                 return;
4084
4085         prodidx = sc->bge_tx_prodidx;
4086
4087         for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
4088                 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
4089                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4090                         break;
4091                 }
4092                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
4093                 if (m_head == NULL)
4094                         break;
4095
4096                 /*
4097                  * XXX
4098                  * The code inside the if() block is never reached since we
4099                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
4100                  * requests to checksum TCP/UDP in a fragmented packet.
4101                  *
4102                  * XXX
4103                  * safety overkill.  If this is a fragmented packet chain
4104                  * with delayed TCP/UDP checksums, then only encapsulate
4105                  * it if we have enough descriptors to handle the entire
4106                  * chain at once.
4107                  * (paranoia -- may not actually be needed)
4108                  */
4109                 if (m_head->m_flags & M_FIRSTFRAG &&
4110                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
4111                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
4112                             m_head->m_pkthdr.csum_data + 16) {
4113                                 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4114                                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4115                                 break;
4116                         }
4117                 }
4118
4119                 /*
4120                  * Pack the data into the transmit ring. If we
4121                  * don't have room, set the OACTIVE flag and wait
4122                  * for the NIC to drain the ring.
4123                  */
4124                 if (bge_encap(sc, &m_head, &prodidx)) {
4125                         if (m_head == NULL)
4126                                 break;
4127                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4128                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4129                         break;
4130                 }
4131                 ++count;
4132
4133                 /*
4134                  * If there's a BPF listener, bounce a copy of this frame
4135                  * to him.
4136                  */
4137 #ifdef ETHER_BPF_MTAP
4138                 ETHER_BPF_MTAP(ifp, m_head);
4139 #else
4140                 BPF_MTAP(ifp, m_head);
4141 #endif
4142         }
4143
4144         if (count > 0) {
4145                 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4146                     sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
4147                 /* Transmit. */
4148                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4149                 /* 5700 b2 errata */
4150                 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
4151                         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4152
4153                 sc->bge_tx_prodidx = prodidx;
4154
4155                 /*
4156                  * Set a timeout in case the chip goes out to lunch.
4157                  */
4158                 sc->bge_timer = 5;
4159         }
4160 }
4161
4162 /*
4163  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4164  * to the mbuf data regions directly in the transmit descriptors.
4165  */
4166 static void
4167 bge_start(struct ifnet *ifp)
4168 {
4169         struct bge_softc *sc;
4170
4171         sc = ifp->if_softc;
4172         BGE_LOCK(sc);
4173         bge_start_locked(ifp);
4174         BGE_UNLOCK(sc);
4175 }
4176
4177 static void
4178 bge_init_locked(struct bge_softc *sc)
4179 {
4180         struct ifnet *ifp;
4181         uint16_t *m;
4182
4183         BGE_LOCK_ASSERT(sc);
4184
4185         ifp = sc->bge_ifp;
4186
4187         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4188                 return;
4189
4190         /* Cancel pending I/O and flush buffers. */
4191         bge_stop(sc);
4192
4193         bge_stop_fw(sc);
4194         bge_sig_pre_reset(sc, BGE_RESET_START);
4195         bge_reset(sc);
4196         bge_sig_legacy(sc, BGE_RESET_START);
4197         bge_sig_post_reset(sc, BGE_RESET_START);
4198
4199         bge_chipinit(sc);
4200
4201         /*
4202          * Init the various state machines, ring
4203          * control blocks and firmware.
4204          */
4205         if (bge_blockinit(sc)) {
4206                 device_printf(sc->bge_dev, "initialization failure\n");
4207                 return;
4208         }
4209
4210         ifp = sc->bge_ifp;
4211
4212         /* Specify MTU. */
4213         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
4214             ETHER_HDR_LEN + ETHER_CRC_LEN +
4215             (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
4216
4217         /* Load our MAC address. */
4218         m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
4219         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
4220         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
4221
4222         /* Program promiscuous mode. */
4223         bge_setpromisc(sc);
4224
4225         /* Program multicast filter. */
4226         bge_setmulti(sc);
4227
4228         /* Program VLAN tag stripping. */
4229         bge_setvlan(sc);
4230
4231         /* Init RX ring. */
4232         if (bge_init_rx_ring_std(sc) != 0) {
4233                 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
4234                 bge_stop(sc);
4235                 return;
4236         }
4237
4238         /*
4239          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
4240          * memory to insure that the chip has in fact read the first
4241          * entry of the ring.
4242          */
4243         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
4244                 uint32_t                v, i;
4245                 for (i = 0; i < 10; i++) {
4246                         DELAY(20);
4247                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
4248                         if (v == (MCLBYTES - ETHER_ALIGN))
4249                                 break;
4250                 }
4251                 if (i == 10)
4252                         device_printf (sc->bge_dev,
4253                             "5705 A0 chip failed to load RX ring\n");
4254         }
4255
4256         /* Init jumbo RX ring. */
4257         if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
4258             (MCLBYTES - ETHER_ALIGN)) {
4259                 if (bge_init_rx_ring_jumbo(sc) != 0) {
4260                         device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
4261                         bge_stop(sc);
4262                         return;
4263                 }
4264         }
4265
4266         /* Init our RX return ring index. */
4267         sc->bge_rx_saved_considx = 0;
4268
4269         /* Init our RX/TX stat counters. */
4270         sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
4271
4272         /* Init TX ring. */
4273         bge_init_tx_ring(sc);
4274
4275         /* Turn on transmitter. */
4276         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
4277
4278         /* Turn on receiver. */
4279         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4280
4281         /* Tell firmware we're alive. */
4282         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4283
4284 #ifdef DEVICE_POLLING
4285         /* Disable interrupts if we are polling. */
4286         if (ifp->if_capenable & IFCAP_POLLING) {
4287                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4288                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4289                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4290         } else
4291 #endif
4292
4293         /* Enable host interrupts. */
4294         {
4295         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
4296         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4297         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4298         }
4299
4300         bge_ifmedia_upd_locked(ifp);
4301
4302         ifp->if_drv_flags |= IFF_DRV_RUNNING;
4303         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4304
4305         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4306 }
4307
4308 static void
4309 bge_init(void *xsc)
4310 {
4311         struct bge_softc *sc = xsc;
4312
4313         BGE_LOCK(sc);
4314         bge_init_locked(sc);
4315         BGE_UNLOCK(sc);
4316 }
4317
4318 /*
4319  * Set media options.
4320  */
4321 static int
4322 bge_ifmedia_upd(struct ifnet *ifp)
4323 {
4324         struct bge_softc *sc = ifp->if_softc;
4325         int res;
4326
4327         BGE_LOCK(sc);
4328         res = bge_ifmedia_upd_locked(ifp);
4329         BGE_UNLOCK(sc);
4330
4331         return (res);
4332 }
4333
4334 static int
4335 bge_ifmedia_upd_locked(struct ifnet *ifp)
4336 {
4337         struct bge_softc *sc = ifp->if_softc;
4338         struct mii_data *mii;
4339         struct mii_softc *miisc;
4340         struct ifmedia *ifm;
4341
4342         BGE_LOCK_ASSERT(sc);
4343
4344         ifm = &sc->bge_ifmedia;
4345
4346         /* If this is a 1000baseX NIC, enable the TBI port. */
4347         if (sc->bge_flags & BGE_FLAG_TBI) {
4348                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
4349                         return (EINVAL);
4350                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
4351                 case IFM_AUTO:
4352                         /*
4353                          * The BCM5704 ASIC appears to have a special
4354                          * mechanism for programming the autoneg
4355                          * advertisement registers in TBI mode.
4356                          */
4357                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4358                                 uint32_t sgdig;
4359                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
4360                                 if (sgdig & BGE_SGDIGSTS_DONE) {
4361                                         CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
4362                                         sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
4363                                         sgdig |= BGE_SGDIGCFG_AUTO |
4364                                             BGE_SGDIGCFG_PAUSE_CAP |
4365                                             BGE_SGDIGCFG_ASYM_PAUSE;
4366                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG,
4367                                             sgdig | BGE_SGDIGCFG_SEND);
4368                                         DELAY(5);
4369                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
4370                                 }
4371                         }
4372                         break;
4373                 case IFM_1000_SX:
4374                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
4375                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
4376                                     BGE_MACMODE_HALF_DUPLEX);
4377                         } else {
4378                                 BGE_SETBIT(sc, BGE_MAC_MODE,
4379                                     BGE_MACMODE_HALF_DUPLEX);
4380                         }
4381                         break;
4382                 default:
4383                         return (EINVAL);
4384                 }
4385                 return (0);
4386         }
4387
4388         sc->bge_link_evt++;
4389         mii = device_get_softc(sc->bge_miibus);
4390         if (mii->mii_instance)
4391                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4392                         mii_phy_reset(miisc);
4393         mii_mediachg(mii);
4394
4395         /*
4396          * Force an interrupt so that we will call bge_link_upd
4397          * if needed and clear any pending link state attention.
4398          * Without this we are not getting any further interrupts
4399          * for link state changes and thus will not UP the link and
4400          * not be able to send in bge_start_locked. The only
4401          * way to get things working was to receive a packet and
4402          * get an RX intr.
4403          * bge_tick should help for fiber cards and we might not
4404          * need to do this here if BGE_FLAG_TBI is set but as
4405          * we poll for fiber anyway it should not harm.
4406          */
4407         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4408             sc->bge_flags & BGE_FLAG_5788)
4409                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4410         else
4411                 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4412
4413         return (0);
4414 }
4415
4416 /*
4417  * Report current media status.
4418  */
4419 static void
4420 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4421 {
4422         struct bge_softc *sc = ifp->if_softc;
4423         struct mii_data *mii;
4424
4425         BGE_LOCK(sc);
4426
4427         if (sc->bge_flags & BGE_FLAG_TBI) {
4428                 ifmr->ifm_status = IFM_AVALID;
4429                 ifmr->ifm_active = IFM_ETHER;
4430                 if (CSR_READ_4(sc, BGE_MAC_STS) &
4431                     BGE_MACSTAT_TBI_PCS_SYNCHED)
4432                         ifmr->ifm_status |= IFM_ACTIVE;
4433                 else {
4434                         ifmr->ifm_active |= IFM_NONE;
4435                         BGE_UNLOCK(sc);
4436                         return;
4437                 }
4438                 ifmr->ifm_active |= IFM_1000_SX;
4439                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
4440                         ifmr->ifm_active |= IFM_HDX;
4441                 else
4442                         ifmr->ifm_active |= IFM_FDX;
4443                 BGE_UNLOCK(sc);
4444                 return;
4445         }
4446
4447         mii = device_get_softc(sc->bge_miibus);
4448         mii_pollstat(mii);
4449         ifmr->ifm_active = mii->mii_media_active;
4450         ifmr->ifm_status = mii->mii_media_status;
4451
4452         BGE_UNLOCK(sc);
4453 }
4454
4455 static int
4456 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
4457 {
4458         struct bge_softc *sc = ifp->if_softc;
4459         struct ifreq *ifr = (struct ifreq *) data;
4460         struct mii_data *mii;
4461         int flags, mask, error = 0;
4462
4463         switch (command) {
4464         case SIOCSIFMTU:
4465                 if (ifr->ifr_mtu < ETHERMIN ||
4466                     ((BGE_IS_JUMBO_CAPABLE(sc)) &&
4467                     ifr->ifr_mtu > BGE_JUMBO_MTU) ||
4468                     ((!BGE_IS_JUMBO_CAPABLE(sc)) &&
4469                     ifr->ifr_mtu > ETHERMTU))
4470                         error = EINVAL;
4471                 else if (ifp->if_mtu != ifr->ifr_mtu) {
4472                         ifp->if_mtu = ifr->ifr_mtu;
4473                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4474                         bge_init(sc);
4475                 }
4476                 break;
4477         case SIOCSIFFLAGS:
4478                 BGE_LOCK(sc);
4479                 if (ifp->if_flags & IFF_UP) {
4480                         /*
4481                          * If only the state of the PROMISC flag changed,
4482                          * then just use the 'set promisc mode' command
4483                          * instead of reinitializing the entire NIC. Doing
4484                          * a full re-init means reloading the firmware and
4485                          * waiting for it to start up, which may take a
4486                          * second or two.  Similarly for ALLMULTI.
4487                          */
4488                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4489                                 flags = ifp->if_flags ^ sc->bge_if_flags;
4490                                 if (flags & IFF_PROMISC)
4491                                         bge_setpromisc(sc);
4492                                 if (flags & IFF_ALLMULTI)
4493                                         bge_setmulti(sc);
4494                         } else
4495                                 bge_init_locked(sc);
4496                 } else {
4497                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4498                                 bge_stop(sc);
4499                         }
4500                 }
4501                 sc->bge_if_flags = ifp->if_flags;
4502                 BGE_UNLOCK(sc);
4503                 error = 0;
4504                 break;
4505         case SIOCADDMULTI:
4506         case SIOCDELMULTI:
4507                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4508                         BGE_LOCK(sc);
4509                         bge_setmulti(sc);
4510                         BGE_UNLOCK(sc);
4511                         error = 0;
4512                 }
4513                 break;
4514         case SIOCSIFMEDIA:
4515         case SIOCGIFMEDIA:
4516                 if (sc->bge_flags & BGE_FLAG_TBI) {
4517                         error = ifmedia_ioctl(ifp, ifr,
4518                             &sc->bge_ifmedia, command);
4519                 } else {
4520                         mii = device_get_softc(sc->bge_miibus);
4521                         error = ifmedia_ioctl(ifp, ifr,
4522                             &mii->mii_media, command);
4523                 }
4524                 break;
4525         case SIOCSIFCAP:
4526                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
4527 #ifdef DEVICE_POLLING
4528                 if (mask & IFCAP_POLLING) {
4529                         if (ifr->ifr_reqcap & IFCAP_POLLING) {
4530                                 error = ether_poll_register(bge_poll, ifp);
4531                                 if (error)
4532                                         return (error);
4533                                 BGE_LOCK(sc);
4534                                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4535                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4536                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4537                                 ifp->if_capenable |= IFCAP_POLLING;
4538                                 BGE_UNLOCK(sc);
4539                         } else {
4540                                 error = ether_poll_deregister(ifp);
4541                                 /* Enable interrupt even in error case */
4542                                 BGE_LOCK(sc);
4543                                 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
4544                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4545                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4546                                 ifp->if_capenable &= ~IFCAP_POLLING;
4547                                 BGE_UNLOCK(sc);
4548                         }
4549                 }
4550 #endif
4551                 if (mask & IFCAP_HWCSUM) {
4552                         ifp->if_capenable ^= IFCAP_HWCSUM;
4553                         if (IFCAP_HWCSUM & ifp->if_capenable &&
4554                             IFCAP_HWCSUM & ifp->if_capabilities)
4555                                 ifp->if_hwassist |= BGE_CSUM_FEATURES;
4556                         else
4557                                 ifp->if_hwassist &= ~BGE_CSUM_FEATURES;
4558                 }
4559
4560                 if ((mask & IFCAP_TSO4) != 0 &&
4561                     (ifp->if_capabilities & IFCAP_TSO4) != 0) {
4562                         ifp->if_capenable ^= IFCAP_TSO4;
4563                         if ((ifp->if_capenable & IFCAP_TSO4) != 0)
4564                                 ifp->if_hwassist |= CSUM_TSO;
4565                         else
4566                                 ifp->if_hwassist &= ~CSUM_TSO;
4567                 }
4568
4569                 if (mask & IFCAP_VLAN_MTU) {
4570                         ifp->if_capenable ^= IFCAP_VLAN_MTU;
4571                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4572                         bge_init(sc);
4573                 }
4574
4575                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
4576                     (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
4577                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
4578                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
4579                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
4580                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
4581                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
4582                                 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
4583                         BGE_LOCK(sc);
4584                         bge_setvlan(sc);
4585                         BGE_UNLOCK(sc);
4586                 }
4587 #ifdef VLAN_CAPABILITIES
4588                 VLAN_CAPABILITIES(ifp);
4589 #endif
4590                 break;
4591         default:
4592                 error = ether_ioctl(ifp, command, data);
4593                 break;
4594         }
4595
4596         return (error);
4597 }
4598
4599 static void
4600 bge_watchdog(struct bge_softc *sc)
4601 {
4602         struct ifnet *ifp;
4603
4604         BGE_LOCK_ASSERT(sc);
4605
4606         if (sc->bge_timer == 0 || --sc->bge_timer)
4607                 return;
4608
4609         ifp = sc->bge_ifp;
4610
4611         if_printf(ifp, "watchdog timeout -- resetting\n");
4612
4613         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4614         bge_init_locked(sc);
4615
4616         ifp->if_oerrors++;
4617 }
4618
4619 /*
4620  * Stop the adapter and free any mbufs allocated to the
4621  * RX and TX lists.
4622  */
4623 static void
4624 bge_stop(struct bge_softc *sc)
4625 {
4626         struct ifnet *ifp;
4627
4628         BGE_LOCK_ASSERT(sc);
4629
4630         ifp = sc->bge_ifp;
4631
4632         callout_stop(&sc->bge_stat_ch);
4633
4634         /* Disable host interrupts. */
4635         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4636         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4637
4638         /*
4639          * Tell firmware we're shutting down.
4640          */
4641         bge_stop_fw(sc);
4642         bge_sig_pre_reset(sc, BGE_RESET_STOP);
4643
4644         /*
4645          * Disable all of the receiver blocks.
4646          */
4647         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4648         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
4649         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
4650         if (!(BGE_IS_5705_PLUS(sc)))
4651                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
4652         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
4653         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
4654         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
4655
4656         /*
4657          * Disable all of the transmit blocks.
4658          */
4659         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
4660         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
4661         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
4662         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
4663         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
4664         if (!(BGE_IS_5705_PLUS(sc)))
4665                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
4666         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
4667
4668         /*
4669          * Shut down all of the memory managers and related
4670          * state machines.
4671          */
4672         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
4673         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
4674         if (!(BGE_IS_5705_PLUS(sc)))
4675                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
4676         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
4677         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
4678         if (!(BGE_IS_5705_PLUS(sc))) {
4679                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
4680                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4681         }
4682
4683         bge_reset(sc);
4684         bge_sig_legacy(sc, BGE_RESET_STOP);
4685         bge_sig_post_reset(sc, BGE_RESET_STOP);
4686
4687         /*
4688          * Keep the ASF firmware running if up.
4689          */
4690         if (sc->bge_asf_mode & ASF_STACKUP)
4691                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4692         else
4693                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4694
4695         /* Free the RX lists. */
4696         bge_free_rx_ring_std(sc);
4697
4698         /* Free jumbo RX list. */
4699         if (BGE_IS_JUMBO_CAPABLE(sc))
4700                 bge_free_rx_ring_jumbo(sc);
4701
4702         /* Free TX buffers. */
4703         bge_free_tx_ring(sc);
4704
4705         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
4706
4707         /* Clear MAC's link state (PHY may still have link UP). */
4708         if (bootverbose && sc->bge_link)
4709                 if_printf(sc->bge_ifp, "link DOWN\n");
4710         sc->bge_link = 0;
4711
4712         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4713 }
4714
4715 /*
4716  * Stop all chip I/O so that the kernel's probe routines don't
4717  * get confused by errant DMAs when rebooting.
4718  */
4719 static int
4720 bge_shutdown(device_t dev)
4721 {
4722         struct bge_softc *sc;
4723
4724         sc = device_get_softc(dev);
4725         BGE_LOCK(sc);
4726         bge_stop(sc);
4727         bge_reset(sc);
4728         BGE_UNLOCK(sc);
4729
4730         return (0);
4731 }
4732
4733 static int
4734 bge_suspend(device_t dev)
4735 {
4736         struct bge_softc *sc;
4737
4738         sc = device_get_softc(dev);
4739         BGE_LOCK(sc);
4740         bge_stop(sc);
4741         BGE_UNLOCK(sc);
4742
4743         return (0);
4744 }
4745
4746 static int
4747 bge_resume(device_t dev)
4748 {
4749         struct bge_softc *sc;
4750         struct ifnet *ifp;
4751
4752         sc = device_get_softc(dev);
4753         BGE_LOCK(sc);
4754         ifp = sc->bge_ifp;
4755         if (ifp->if_flags & IFF_UP) {
4756                 bge_init_locked(sc);
4757                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4758                         bge_start_locked(ifp);
4759         }
4760         BGE_UNLOCK(sc);
4761
4762         return (0);
4763 }
4764
4765 static void
4766 bge_link_upd(struct bge_softc *sc)
4767 {
4768         struct mii_data *mii;
4769         uint32_t link, status;
4770
4771         BGE_LOCK_ASSERT(sc);
4772
4773         /* Clear 'pending link event' flag. */
4774         sc->bge_link_evt = 0;
4775
4776         /*
4777          * Process link state changes.
4778          * Grrr. The link status word in the status block does
4779          * not work correctly on the BCM5700 rev AX and BX chips,
4780          * according to all available information. Hence, we have
4781          * to enable MII interrupts in order to properly obtain
4782          * async link changes. Unfortunately, this also means that
4783          * we have to read the MAC status register to detect link
4784          * changes, thereby adding an additional register access to
4785          * the interrupt handler.
4786          *
4787          * XXX: perhaps link state detection procedure used for
4788          * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
4789          */
4790
4791         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4792             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
4793                 status = CSR_READ_4(sc, BGE_MAC_STS);
4794                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
4795                         mii = device_get_softc(sc->bge_miibus);
4796                         mii_pollstat(mii);
4797                         if (!sc->bge_link &&
4798                             mii->mii_media_status & IFM_ACTIVE &&
4799                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4800                                 sc->bge_link++;
4801                                 if (bootverbose)
4802                                         if_printf(sc->bge_ifp, "link UP\n");
4803                         } else if (sc->bge_link &&
4804                             (!(mii->mii_media_status & IFM_ACTIVE) ||
4805                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4806                                 sc->bge_link = 0;
4807                                 if (bootverbose)
4808                                         if_printf(sc->bge_ifp, "link DOWN\n");
4809                         }
4810
4811                         /* Clear the interrupt. */
4812                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
4813                             BGE_EVTENB_MI_INTERRUPT);
4814                         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4815                         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
4816                             BRGPHY_INTRS);
4817                 }
4818                 return;
4819         }
4820
4821         if (sc->bge_flags & BGE_FLAG_TBI) {
4822                 status = CSR_READ_4(sc, BGE_MAC_STS);
4823                 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4824                         if (!sc->bge_link) {
4825                                 sc->bge_link++;
4826                                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
4827                                         BGE_CLRBIT(sc, BGE_MAC_MODE,
4828                                             BGE_MACMODE_TBI_SEND_CFGS);
4829                                 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4830                                 if (bootverbose)
4831                                         if_printf(sc->bge_ifp, "link UP\n");
4832                                 if_link_state_change(sc->bge_ifp,
4833                                     LINK_STATE_UP);
4834                         }
4835                 } else if (sc->bge_link) {
4836                         sc->bge_link = 0;
4837                         if (bootverbose)
4838                                 if_printf(sc->bge_ifp, "link DOWN\n");
4839                         if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
4840                 }
4841         } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
4842                 /*
4843                  * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
4844                  * in status word always set. Workaround this bug by reading
4845                  * PHY link status directly.
4846                  */
4847                 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
4848
4849                 if (link != sc->bge_link ||
4850                     sc->bge_asicrev == BGE_ASICREV_BCM5700) {
4851                         mii = device_get_softc(sc->bge_miibus);
4852                         mii_pollstat(mii);
4853                         if (!sc->bge_link &&
4854                             mii->mii_media_status & IFM_ACTIVE &&
4855                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4856                                 sc->bge_link++;
4857                                 if (bootverbose)
4858                                         if_printf(sc->bge_ifp, "link UP\n");
4859                         } else if (sc->bge_link &&
4860                             (!(mii->mii_media_status & IFM_ACTIVE) ||
4861                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4862                                 sc->bge_link = 0;
4863                                 if (bootverbose)
4864                                         if_printf(sc->bge_ifp, "link DOWN\n");
4865                         }
4866                 }
4867         } else {
4868                 /*
4869                  * Discard link events for MII/GMII controllers
4870                  * if MI auto-polling is disabled.
4871                  */
4872         }
4873
4874         /* Clear the attention. */
4875         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4876             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4877             BGE_MACSTAT_LINK_CHANGED);
4878 }
4879
4880 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
4881         SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
4882             sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
4883             desc)
4884
4885 static void
4886 bge_add_sysctls(struct bge_softc *sc)
4887 {
4888         struct sysctl_ctx_list *ctx;
4889         struct sysctl_oid_list *children, *schildren;
4890         struct sysctl_oid *tree;
4891
4892         ctx = device_get_sysctl_ctx(sc->bge_dev);
4893         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
4894
4895 #ifdef BGE_REGISTER_DEBUG
4896         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
4897             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
4898             "Debug Information");
4899
4900         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
4901             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
4902             "Register Read");
4903
4904         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
4905             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
4906             "Memory Read");
4907
4908 #endif
4909
4910         /*
4911          * A common design characteristic for many Broadcom client controllers
4912          * is that they only support a single outstanding DMA read operation
4913          * on the PCIe bus. This means that it will take twice as long to fetch
4914          * a TX frame that is split into header and payload buffers as it does
4915          * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
4916          * these controllers, coalescing buffers to reduce the number of memory
4917          * reads is effective way to get maximum performance(about 940Mbps).
4918          * Without collapsing TX buffers the maximum TCP bulk transfer
4919          * performance is about 850Mbps. However forcing coalescing mbufs
4920          * consumes a lot of CPU cycles, so leave it off by default.
4921          */
4922         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
4923             CTLFLAG_RW, &sc->bge_forced_collapse, 0,
4924             "Number of fragmented TX buffers of a frame allowed before "
4925             "forced collapsing");
4926         resource_int_value(device_get_name(sc->bge_dev),
4927             device_get_unit(sc->bge_dev), "forced_collapse",
4928             &sc->bge_forced_collapse);
4929
4930         if (BGE_IS_5705_PLUS(sc))
4931                 return;
4932
4933         tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
4934             NULL, "BGE Statistics");
4935         schildren = children = SYSCTL_CHILDREN(tree);
4936         BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
4937             children, COSFramesDroppedDueToFilters,
4938             "FramesDroppedDueToFilters");
4939         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
4940             children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
4941         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
4942             children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
4943         BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
4944             children, nicNoMoreRxBDs, "NoMoreRxBDs");
4945         BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
4946             children, ifInDiscards, "InputDiscards");
4947         BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
4948             children, ifInErrors, "InputErrors");
4949         BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
4950             children, nicRecvThresholdHit, "RecvThresholdHit");
4951         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
4952             children, nicDmaReadQueueFull, "DmaReadQueueFull");
4953         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
4954             children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
4955         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
4956             children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
4957         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
4958             children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
4959         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
4960             children, nicRingStatusUpdate, "RingStatusUpdate");
4961         BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
4962             children, nicInterrupts, "Interrupts");
4963         BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
4964             children, nicAvoidedInterrupts, "AvoidedInterrupts");
4965         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
4966             children, nicSendThresholdHit, "SendThresholdHit");
4967
4968         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
4969             NULL, "BGE RX Statistics");
4970         children = SYSCTL_CHILDREN(tree);
4971         BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
4972             children, rxstats.ifHCInOctets, "Octets");
4973         BGE_SYSCTL_STAT(sc, ctx, "Fragments",
4974             children, rxstats.etherStatsFragments, "Fragments");
4975         BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
4976             children, rxstats.ifHCInUcastPkts, "UcastPkts");
4977         BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
4978             children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
4979         BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
4980             children, rxstats.dot3StatsFCSErrors, "FCSErrors");
4981         BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
4982             children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
4983         BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
4984             children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
4985         BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
4986             children, rxstats.xoffPauseFramesReceived,
4987             "xoffPauseFramesReceived");
4988         BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
4989             children, rxstats.macControlFramesReceived,
4990             "ControlFramesReceived");
4991         BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
4992             children, rxstats.xoffStateEntered, "xoffStateEntered");
4993         BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
4994             children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
4995         BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
4996             children, rxstats.etherStatsJabbers, "Jabbers");
4997         BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
4998             children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
4999         BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
5000             children, rxstats.inRangeLengthError, "inRangeLengthError");
5001         BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
5002             children, rxstats.outRangeLengthError, "outRangeLengthError");
5003
5004         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
5005             NULL, "BGE TX Statistics");
5006         children = SYSCTL_CHILDREN(tree);
5007         BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
5008             children, txstats.ifHCOutOctets, "Octets");
5009         BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
5010             children, txstats.etherStatsCollisions, "Collisions");
5011         BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
5012             children, txstats.outXonSent, "XonSent");
5013         BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
5014             children, txstats.outXoffSent, "XoffSent");
5015         BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
5016             children, txstats.flowControlDone, "flowControlDone");
5017         BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
5018             children, txstats.dot3StatsInternalMacTransmitErrors,
5019             "InternalMacTransmitErrors");
5020         BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
5021             children, txstats.dot3StatsSingleCollisionFrames,
5022             "SingleCollisionFrames");
5023         BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
5024             children, txstats.dot3StatsMultipleCollisionFrames,
5025             "MultipleCollisionFrames");
5026         BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
5027             children, txstats.dot3StatsDeferredTransmissions,
5028             "DeferredTransmissions");
5029         BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
5030             children, txstats.dot3StatsExcessiveCollisions,
5031             "ExcessiveCollisions");
5032         BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
5033             children, txstats.dot3StatsLateCollisions,
5034             "LateCollisions");
5035         BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
5036             children, txstats.ifHCOutUcastPkts, "UcastPkts");
5037         BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
5038             children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
5039         BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
5040             children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
5041         BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
5042             children, txstats.dot3StatsCarrierSenseErrors,
5043             "CarrierSenseErrors");
5044         BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
5045             children, txstats.ifOutDiscards, "Discards");
5046         BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
5047             children, txstats.ifOutErrors, "Errors");
5048 }
5049
5050 static int
5051 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
5052 {
5053         struct bge_softc *sc;
5054         uint32_t result;
5055         int offset;
5056
5057         sc = (struct bge_softc *)arg1;
5058         offset = arg2;
5059         result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
5060             offsetof(bge_hostaddr, bge_addr_lo));
5061         return (sysctl_handle_int(oidp, &result, 0, req));
5062 }
5063
5064 #ifdef BGE_REGISTER_DEBUG
5065 static int
5066 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
5067 {
5068         struct bge_softc *sc;
5069         uint16_t *sbdata;
5070         int error;
5071         int result;
5072         int i, j;
5073
5074         result = -1;
5075         error = sysctl_handle_int(oidp, &result, 0, req);
5076         if (error || (req->newptr == NULL))
5077                 return (error);
5078
5079         if (result == 1) {
5080                 sc = (struct bge_softc *)arg1;
5081
5082                 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
5083                 printf("Status Block:\n");
5084                 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) {
5085                         printf("%06x:", i);
5086                         for (j = 0; j < 8; j++) {
5087                                 printf(" %04x", sbdata[i]);
5088                                 i += 4;
5089                         }
5090                         printf("\n");
5091                 }
5092
5093                 printf("Registers:\n");
5094                 for (i = 0x800; i < 0xA00; ) {
5095                         printf("%06x:", i);
5096                         for (j = 0; j < 8; j++) {
5097                                 printf(" %08x", CSR_READ_4(sc, i));
5098                                 i += 4;
5099                         }
5100                         printf("\n");
5101                 }
5102
5103                 printf("Hardware Flags:\n");
5104                 if (BGE_IS_5755_PLUS(sc))
5105                         printf(" - 5755 Plus\n");
5106                 if (BGE_IS_575X_PLUS(sc))
5107                         printf(" - 575X Plus\n");
5108                 if (BGE_IS_5705_PLUS(sc))
5109                         printf(" - 5705 Plus\n");
5110                 if (BGE_IS_5714_FAMILY(sc))
5111                         printf(" - 5714 Family\n");
5112                 if (BGE_IS_5700_FAMILY(sc))
5113                         printf(" - 5700 Family\n");
5114                 if (sc->bge_flags & BGE_FLAG_JUMBO)
5115                         printf(" - Supports Jumbo Frames\n");
5116                 if (sc->bge_flags & BGE_FLAG_PCIX)
5117                         printf(" - PCI-X Bus\n");
5118                 if (sc->bge_flags & BGE_FLAG_PCIE)
5119                         printf(" - PCI Express Bus\n");
5120                 if (sc->bge_flags & BGE_FLAG_NO_3LED)
5121                         printf(" - No 3 LEDs\n");
5122                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
5123                         printf(" - RX Alignment Bug\n");
5124         }
5125
5126         return (error);
5127 }
5128
5129 static int
5130 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5131 {
5132         struct bge_softc *sc;
5133         int error;
5134         uint16_t result;
5135         uint32_t val;
5136
5137         result = -1;
5138         error = sysctl_handle_int(oidp, &result, 0, req);
5139         if (error || (req->newptr == NULL))
5140                 return (error);
5141
5142         if (result < 0x8000) {
5143                 sc = (struct bge_softc *)arg1;
5144                 val = CSR_READ_4(sc, result);
5145                 printf("reg 0x%06X = 0x%08X\n", result, val);
5146         }
5147
5148         return (error);
5149 }
5150
5151 static int
5152 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
5153 {
5154         struct bge_softc *sc;
5155         int error;
5156         uint16_t result;
5157         uint32_t val;
5158
5159         result = -1;
5160         error = sysctl_handle_int(oidp, &result, 0, req);
5161         if (error || (req->newptr == NULL))
5162                 return (error);
5163
5164         if (result < 0x8000) {
5165                 sc = (struct bge_softc *)arg1;
5166                 val = bge_readmem_ind(sc, result);
5167                 printf("mem 0x%06X = 0x%08X\n", result, val);
5168         }
5169
5170         return (error);
5171 }
5172 #endif
5173
5174 static int
5175 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
5176 {
5177
5178         if (sc->bge_flags & BGE_FLAG_EADDR)
5179                 return (1);
5180
5181 #ifdef __sparc64__
5182         OF_getetheraddr(sc->bge_dev, ether_addr);
5183         return (0);
5184 #endif
5185         return (1);
5186 }
5187
5188 static int
5189 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
5190 {
5191         uint32_t mac_addr;
5192
5193         mac_addr = bge_readmem_ind(sc, 0x0c14);
5194         if ((mac_addr >> 16) == 0x484b) {
5195                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
5196                 ether_addr[1] = (uint8_t)mac_addr;
5197                 mac_addr = bge_readmem_ind(sc, 0x0c18);
5198                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
5199                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
5200                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
5201                 ether_addr[5] = (uint8_t)mac_addr;
5202                 return (0);
5203         }
5204         return (1);
5205 }
5206
5207 static int
5208 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
5209 {
5210         int mac_offset = BGE_EE_MAC_OFFSET;
5211
5212         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
5213                 mac_offset = BGE_EE_MAC_OFFSET_5906;
5214
5215         return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
5216             ETHER_ADDR_LEN));
5217 }
5218
5219 static int
5220 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
5221 {
5222
5223         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
5224                 return (1);
5225
5226         return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
5227            ETHER_ADDR_LEN));
5228 }
5229
5230 static int
5231 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
5232 {
5233         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
5234                 /* NOTE: Order is critical */
5235                 bge_get_eaddr_fw,
5236                 bge_get_eaddr_mem,
5237                 bge_get_eaddr_nvram,
5238                 bge_get_eaddr_eeprom,
5239                 NULL
5240         };
5241         const bge_eaddr_fcn_t *func;
5242
5243         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
5244                 if ((*func)(sc, eaddr) == 0)
5245                         break;
5246         }
5247         return (*func == NULL ? ENXIO : 0);
5248 }