sys/dev/bge/if_bge.c

   1 /*-
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/cdefs.h>
  35 __FBSDID("$FreeBSD$");
  36
  37 /*
  38  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  39  *
  40  * The Broadcom BCM5700 is based on technology originally developed by
  41  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  42  * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
  43  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  44  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  45  * frames, highly configurable RX filtering, and 16 RX and TX queues
  46  * (which, along with RX filter rules, can be used for QOS applications).
  47  * Other features, such as TCP segmentation, may be available as part
  48  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  49  * firmware images can be stored in hardware and need not be compiled
  50  * into the driver.
  51  *
  52  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  53  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  54  *
  55  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  56  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  57  * does not support external SSRAM.
  58  *
  59  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  60  * brand name, which is functionally similar but lacks PCI-X support.
  61  *
  62  * Without external SSRAM, you can only have at most 4 TX rings,
  63  * and the use of the mini RX ring is disabled. This seems to imply
  64  * that these features are simply not available on the BCM5701. As a
  65  * result, this driver does not implement any support for the mini RX
  66  * ring.
  67  */
  68
  69 #ifdef HAVE_KERNEL_OPTION_HEADERS
  70 #include "opt_device_polling.h"
  71 #endif
  72
  73 #include <sys/param.h>
  74 #include <sys/endian.h>
  75 #include <sys/systm.h>
  76 #include <sys/sockio.h>
  77 #include <sys/mbuf.h>
  78 #include <sys/malloc.h>
  79 #include <sys/kernel.h>
  80 #include <sys/module.h>
  81 #include <sys/socket.h>
  82 #include <sys/sysctl.h>
  83 #include <sys/taskqueue.h>
  84
  85 #include <net/if.h>
  86 #include <net/if_arp.h>
  87 #include <net/ethernet.h>
  88 #include <net/if_dl.h>
  89 #include <net/if_media.h>
  90
  91 #include <net/bpf.h>
  92
  93 #include <net/if_types.h>
  94 #include <net/if_vlan_var.h>
  95
  96 #include <netinet/in_systm.h>
  97 #include <netinet/in.h>
  98 #include <netinet/ip.h>
  99 #include <netinet/tcp.h>
 100
 101 #include <machine/bus.h>
 102 #include <machine/resource.h>
 103 #include <sys/bus.h>
 104 #include <sys/rman.h>
 105
 106 #include <dev/mii/mii.h>
 107 #include <dev/mii/miivar.h>
 108 #include "miidevs.h"
 109 #include <dev/mii/brgphyreg.h>
 110
 111 #ifdef __sparc64__
 112 #include <dev/ofw/ofw_bus.h>
 113 #include <dev/ofw/openfirm.h>
 114 #include <machine/ofw_machdep.h>
 115 #include <machine/ver.h>
 116 #endif
 117
 118 #include <dev/pci/pcireg.h>
 119 #include <dev/pci/pcivar.h>
 120
 121 #include <dev/bge/if_bgereg.h>
 122
 123 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP)
 124 #define ETHER_MIN_NOPAD         (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
 125
 126 MODULE_DEPEND(bge, pci, 1, 1, 1);
 127 MODULE_DEPEND(bge, ether, 1, 1, 1);
 128 MODULE_DEPEND(bge, miibus, 1, 1, 1);
 129
 130 /* "device miibus" required.  See GENERIC if you get errors here. */
 131 #include "miibus_if.h"
 132
 133 /*
 134  * Various supported device vendors/types and their names. Note: the
 135  * spec seems to indicate that the hardware still has Alteon's vendor
 136  * ID burned into it, though it will always be overriden by the vendor
 137  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 138  */
 139 static const struct bge_type {
 140         uint16_t        bge_vid;
 141         uint16_t        bge_did;
 142 } const bge_devs[] = {
 143         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5700 },
 144         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5701 },
 145
 146         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1000 },
 147         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1002 },
 148         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC9100 },
 149
 150         { APPLE_VENDORID,       APPLE_DEVICE_BCM5701 },
 151
 152         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5700 },
 153         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5701 },
 154         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702 },
 155         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702_ALT },
 156         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702X },
 157         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703 },
 158         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703_ALT },
 159         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703X },
 160         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704C },
 161         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S },
 162         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S_ALT },
 163         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705 },
 164         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705F },
 165         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705K },
 166         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M },
 167         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M_ALT },
 168         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714C },
 169         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714S },
 170         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715 },
 171         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715S },
 172         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5717 },
 173         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5718 },
 174         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5719 },
 175         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5720 },
 176         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5721 },
 177         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5722 },
 178         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5723 },
 179         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750 },
 180         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750M },
 181         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751 },
 182         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751F },
 183         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751M },
 184         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752 },
 185         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752M },
 186         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753 },
 187         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753F },
 188         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753M },
 189         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754 },
 190         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754M },
 191         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755 },
 192         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755M },
 193         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5756 },
 194         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761 },
 195         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761E },
 196         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761S },
 197         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761SE },
 198         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5764 },
 199         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780 },
 200         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780S },
 201         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5781 },
 202         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5782 },
 203         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5784 },
 204         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785F },
 205         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785G },
 206         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5786 },
 207         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787 },
 208         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787F },
 209         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787M },
 210         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5788 },
 211         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5789 },
 212         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901 },
 213         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901A2 },
 214         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5903M },
 215         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906 },
 216         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906M },
 217         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57760 },
 218         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57761 },
 219         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57765 },
 220         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57780 },
 221         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57781 },
 222         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57785 },
 223         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57788 },
 224         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57790 },
 225         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57791 },
 226         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57795 },
 227
 228         { SK_VENDORID,          SK_DEVICEID_ALTIMA },
 229
 230         { TC_VENDORID,          TC_DEVICEID_3C996 },
 231
 232         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE4 },
 233         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE5 },
 234         { FJTSU_VENDORID,       FJTSU_DEVICEID_PP250450 },
 235
 236         { 0, 0 }
 237 };
 238
 239 static const struct bge_vendor {
 240         uint16_t        v_id;
 241         const char      *v_name;
 242 } const bge_vendors[] = {
 243         { ALTEON_VENDORID,      "Alteon" },
 244         { ALTIMA_VENDORID,      "Altima" },
 245         { APPLE_VENDORID,       "Apple" },
 246         { BCOM_VENDORID,        "Broadcom" },
 247         { SK_VENDORID,          "SysKonnect" },
 248         { TC_VENDORID,          "3Com" },
 249         { FJTSU_VENDORID,       "Fujitsu" },
 250
 251         { 0, NULL }
 252 };
 253
 254 static const struct bge_revision {
 255         uint32_t        br_chipid;
 256         const char      *br_name;
 257 } const bge_revisions[] = {
 258         { BGE_CHIPID_BCM5700_A0,        "BCM5700 A0" },
 259         { BGE_CHIPID_BCM5700_A1,        "BCM5700 A1" },
 260         { BGE_CHIPID_BCM5700_B0,        "BCM5700 B0" },
 261         { BGE_CHIPID_BCM5700_B1,        "BCM5700 B1" },
 262         { BGE_CHIPID_BCM5700_B2,        "BCM5700 B2" },
 263         { BGE_CHIPID_BCM5700_B3,        "BCM5700 B3" },
 264         { BGE_CHIPID_BCM5700_ALTIMA,    "BCM5700 Altima" },
 265         { BGE_CHIPID_BCM5700_C0,        "BCM5700 C0" },
 266         { BGE_CHIPID_BCM5701_A0,        "BCM5701 A0" },
 267         { BGE_CHIPID_BCM5701_B0,        "BCM5701 B0" },
 268         { BGE_CHIPID_BCM5701_B2,        "BCM5701 B2" },
 269         { BGE_CHIPID_BCM5701_B5,        "BCM5701 B5" },
 270         { BGE_CHIPID_BCM5703_A0,        "BCM5703 A0" },
 271         { BGE_CHIPID_BCM5703_A1,        "BCM5703 A1" },
 272         { BGE_CHIPID_BCM5703_A2,        "BCM5703 A2" },
 273         { BGE_CHIPID_BCM5703_A3,        "BCM5703 A3" },
 274         { BGE_CHIPID_BCM5703_B0,        "BCM5703 B0" },
 275         { BGE_CHIPID_BCM5704_A0,        "BCM5704 A0" },
 276         { BGE_CHIPID_BCM5704_A1,        "BCM5704 A1" },
 277         { BGE_CHIPID_BCM5704_A2,        "BCM5704 A2" },
 278         { BGE_CHIPID_BCM5704_A3,        "BCM5704 A3" },
 279         { BGE_CHIPID_BCM5704_B0,        "BCM5704 B0" },
 280         { BGE_CHIPID_BCM5705_A0,        "BCM5705 A0" },
 281         { BGE_CHIPID_BCM5705_A1,        "BCM5705 A1" },
 282         { BGE_CHIPID_BCM5705_A2,        "BCM5705 A2" },
 283         { BGE_CHIPID_BCM5705_A3,        "BCM5705 A3" },
 284         { BGE_CHIPID_BCM5750_A0,        "BCM5750 A0" },
 285         { BGE_CHIPID_BCM5750_A1,        "BCM5750 A1" },
 286         { BGE_CHIPID_BCM5750_A3,        "BCM5750 A3" },
 287         { BGE_CHIPID_BCM5750_B0,        "BCM5750 B0" },
 288         { BGE_CHIPID_BCM5750_B1,        "BCM5750 B1" },
 289         { BGE_CHIPID_BCM5750_C0,        "BCM5750 C0" },
 290         { BGE_CHIPID_BCM5750_C1,        "BCM5750 C1" },
 291         { BGE_CHIPID_BCM5750_C2,        "BCM5750 C2" },
 292         { BGE_CHIPID_BCM5714_A0,        "BCM5714 A0" },
 293         { BGE_CHIPID_BCM5752_A0,        "BCM5752 A0" },
 294         { BGE_CHIPID_BCM5752_A1,        "BCM5752 A1" },
 295         { BGE_CHIPID_BCM5752_A2,        "BCM5752 A2" },
 296         { BGE_CHIPID_BCM5714_B0,        "BCM5714 B0" },
 297         { BGE_CHIPID_BCM5714_B3,        "BCM5714 B3" },
 298         { BGE_CHIPID_BCM5715_A0,        "BCM5715 A0" },
 299         { BGE_CHIPID_BCM5715_A1,        "BCM5715 A1" },
 300         { BGE_CHIPID_BCM5715_A3,        "BCM5715 A3" },
 301         { BGE_CHIPID_BCM5717_A0,        "BCM5717 A0" },
 302         { BGE_CHIPID_BCM5717_B0,        "BCM5717 B0" },
 303         { BGE_CHIPID_BCM5719_A0,        "BCM5719 A0" },
 304         { BGE_CHIPID_BCM5720_A0,        "BCM5720 A0" },
 305         { BGE_CHIPID_BCM5755_A0,        "BCM5755 A0" },
 306         { BGE_CHIPID_BCM5755_A1,        "BCM5755 A1" },
 307         { BGE_CHIPID_BCM5755_A2,        "BCM5755 A2" },
 308         { BGE_CHIPID_BCM5722_A0,        "BCM5722 A0" },
 309         { BGE_CHIPID_BCM5761_A0,        "BCM5761 A0" },
 310         { BGE_CHIPID_BCM5761_A1,        "BCM5761 A1" },
 311         { BGE_CHIPID_BCM5784_A0,        "BCM5784 A0" },
 312         { BGE_CHIPID_BCM5784_A1,        "BCM5784 A1" },
 313         /* 5754 and 5787 share the same ASIC ID */
 314         { BGE_CHIPID_BCM5787_A0,        "BCM5754/5787 A0" },
 315         { BGE_CHIPID_BCM5787_A1,        "BCM5754/5787 A1" },
 316         { BGE_CHIPID_BCM5787_A2,        "BCM5754/5787 A2" },
 317         { BGE_CHIPID_BCM5906_A1,        "BCM5906 A1" },
 318         { BGE_CHIPID_BCM5906_A2,        "BCM5906 A2" },
 319         { BGE_CHIPID_BCM57765_A0,       "BCM57765 A0" },
 320         { BGE_CHIPID_BCM57765_B0,       "BCM57765 B0" },
 321         { BGE_CHIPID_BCM57780_A0,       "BCM57780 A0" },
 322         { BGE_CHIPID_BCM57780_A1,       "BCM57780 A1" },
 323
 324         { 0, NULL }
 325 };
 326
 327 /*
 328  * Some defaults for major revisions, so that newer steppings
 329  * that we don't know about have a shot at working.
 330  */
 331 static const struct bge_revision const bge_majorrevs[] = {
 332         { BGE_ASICREV_BCM5700,          "unknown BCM5700" },
 333         { BGE_ASICREV_BCM5701,          "unknown BCM5701" },
 334         { BGE_ASICREV_BCM5703,          "unknown BCM5703" },
 335         { BGE_ASICREV_BCM5704,          "unknown BCM5704" },
 336         { BGE_ASICREV_BCM5705,          "unknown BCM5705" },
 337         { BGE_ASICREV_BCM5750,          "unknown BCM5750" },
 338         { BGE_ASICREV_BCM5714_A0,       "unknown BCM5714" },
 339         { BGE_ASICREV_BCM5752,          "unknown BCM5752" },
 340         { BGE_ASICREV_BCM5780,          "unknown BCM5780" },
 341         { BGE_ASICREV_BCM5714,          "unknown BCM5714" },
 342         { BGE_ASICREV_BCM5755,          "unknown BCM5755" },
 343         { BGE_ASICREV_BCM5761,          "unknown BCM5761" },
 344         { BGE_ASICREV_BCM5784,          "unknown BCM5784" },
 345         { BGE_ASICREV_BCM5785,          "unknown BCM5785" },
 346         /* 5754 and 5787 share the same ASIC ID */
 347         { BGE_ASICREV_BCM5787,          "unknown BCM5754/5787" },
 348         { BGE_ASICREV_BCM5906,          "unknown BCM5906" },
 349         { BGE_ASICREV_BCM57765,         "unknown BCM57765" },
 350         { BGE_ASICREV_BCM57780,         "unknown BCM57780" },
 351         { BGE_ASICREV_BCM5717,          "unknown BCM5717" },
 352         { BGE_ASICREV_BCM5719,          "unknown BCM5719" },
 353         { BGE_ASICREV_BCM5720,          "unknown BCM5720" },
 354
 355         { 0, NULL }
 356 };
 357
 358 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 359 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 360 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 361 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 362 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 363 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 364 #define BGE_IS_5717_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5717_PLUS)
 365
 366 const struct bge_revision * bge_lookup_rev(uint32_t);
 367 const struct bge_vendor * bge_lookup_vendor(uint16_t);
 368
 369 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 370
 371 static int bge_probe(device_t);
 372 static int bge_attach(device_t);
 373 static int bge_detach(device_t);
 374 static int bge_suspend(device_t);
 375 static int bge_resume(device_t);
 376 static void bge_release_resources(struct bge_softc *);
 377 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 378 static int bge_dma_alloc(struct bge_softc *);
 379 static void bge_dma_free(struct bge_softc *);
 380 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t,
 381     bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
 382
 383 static void bge_devinfo(struct bge_softc *);
 384 static int bge_mbox_reorder(struct bge_softc *);
 385
 386 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
 387 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 388 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 389 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 390 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
 391
 392 static void bge_txeof(struct bge_softc *, uint16_t);
 393 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
 394 static int bge_rxeof(struct bge_softc *, uint16_t, int);
 395
 396 static void bge_asf_driver_up (struct bge_softc *);
 397 static void bge_tick(void *);
 398 static void bge_stats_clear_regs(struct bge_softc *);
 399 static void bge_stats_update(struct bge_softc *);
 400 static void bge_stats_update_regs(struct bge_softc *);
 401 static struct mbuf *bge_check_short_dma(struct mbuf *);
 402 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
 403     uint16_t *, uint16_t *);
 404 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 405
 406 static void bge_intr(void *);
 407 static int bge_msi_intr(void *);
 408 static void bge_intr_task(void *, int);
 409 static void bge_start_locked(struct ifnet *);
 410 static void bge_start(struct ifnet *);
 411 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
 412 static void bge_init_locked(struct bge_softc *);
 413 static void bge_init(void *);
 414 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
 415 static void bge_stop(struct bge_softc *);
 416 static void bge_watchdog(struct bge_softc *);
 417 static int bge_shutdown(device_t);
 418 static int bge_ifmedia_upd_locked(struct ifnet *);
 419 static int bge_ifmedia_upd(struct ifnet *);
 420 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 421
 422 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 423 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 424
 425 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
 426 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
 427
 428 static void bge_setpromisc(struct bge_softc *);
 429 static void bge_setmulti(struct bge_softc *);
 430 static void bge_setvlan(struct bge_softc *);
 431
 432 static __inline void bge_rxreuse_std(struct bge_softc *, int);
 433 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
 434 static int bge_newbuf_std(struct bge_softc *, int);
 435 static int bge_newbuf_jumbo(struct bge_softc *, int);
 436 static int bge_init_rx_ring_std(struct bge_softc *);
 437 static void bge_free_rx_ring_std(struct bge_softc *);
 438 static int bge_init_rx_ring_jumbo(struct bge_softc *);
 439 static void bge_free_rx_ring_jumbo(struct bge_softc *);
 440 static void bge_free_tx_ring(struct bge_softc *);
 441 static int bge_init_tx_ring(struct bge_softc *);
 442
 443 static int bge_chipinit(struct bge_softc *);
 444 static int bge_blockinit(struct bge_softc *);
 445 static uint32_t bge_dma_swap_options(struct bge_softc *);
 446
 447 static int bge_has_eaddr(struct bge_softc *);
 448 static uint32_t bge_readmem_ind(struct bge_softc *, int);
 449 static void bge_writemem_ind(struct bge_softc *, int, int);
 450 static void bge_writembx(struct bge_softc *, int, int);
 451 #ifdef notdef
 452 static uint32_t bge_readreg_ind(struct bge_softc *, int);
 453 #endif
 454 static void bge_writemem_direct(struct bge_softc *, int, int);
 455 static void bge_writereg_ind(struct bge_softc *, int, int);
 456
 457 static int bge_miibus_readreg(device_t, int, int);
 458 static int bge_miibus_writereg(device_t, int, int, int);
 459 static void bge_miibus_statchg(device_t);
 460 #ifdef DEVICE_POLLING
 461 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 462 #endif
 463
 464 #define BGE_RESET_START 1
 465 #define BGE_RESET_STOP  2
 466 static void bge_sig_post_reset(struct bge_softc *, int);
 467 static void bge_sig_legacy(struct bge_softc *, int);
 468 static void bge_sig_pre_reset(struct bge_softc *, int);
 469 static void bge_stop_fw(struct bge_softc *);
 470 static int bge_reset(struct bge_softc *);
 471 static void bge_link_upd(struct bge_softc *);
 472
 473 /*
 474  * The BGE_REGISTER_DEBUG option is only for low-level debugging.  It may
 475  * leak information to untrusted users.  It is also known to cause alignment
 476  * traps on certain architectures.
 477  */
 478 #ifdef BGE_REGISTER_DEBUG
 479 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 480 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
 481 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
 482 #endif
 483 static void bge_add_sysctls(struct bge_softc *);
 484 static void bge_add_sysctl_stats_regs(struct bge_softc *,
 485     struct sysctl_ctx_list *, struct sysctl_oid_list *);
 486 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *,
 487     struct sysctl_oid_list *);
 488 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
 489
 490 static device_method_t bge_methods[] = {
 491         /* Device interface */
 492         DEVMETHOD(device_probe,         bge_probe),
 493         DEVMETHOD(device_attach,        bge_attach),
 494         DEVMETHOD(device_detach,        bge_detach),
 495         DEVMETHOD(device_shutdown,      bge_shutdown),
 496         DEVMETHOD(device_suspend,       bge_suspend),
 497         DEVMETHOD(device_resume,        bge_resume),
 498
 499         /* MII interface */
 500         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 501         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 502         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 503
 504         DEVMETHOD_END
 505 };
 506
 507 static driver_t bge_driver = {
 508         "bge",
 509         bge_methods,
 510         sizeof(struct bge_softc)
 511 };
 512
 513 static devclass_t bge_devclass;
 514
 515 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
 516 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 517
 518 static int bge_allow_asf = 1;
 519
 520 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
 521
 522 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
 523 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
 524         "Allow ASF mode if available");
 525
 526 #define SPARC64_BLADE_1500_MODEL        "SUNW,Sun-Blade-1500"
 527 #define SPARC64_BLADE_1500_PATH_BGE     "/pci@1f,700000/network@2"
 528 #define SPARC64_BLADE_2500_MODEL        "SUNW,Sun-Blade-2500"
 529 #define SPARC64_BLADE_2500_PATH_BGE     "/pci@1c,600000/network@3"
 530 #define SPARC64_OFW_SUBVENDOR           "subsystem-vendor-id"
 531
 532 static int
 533 bge_has_eaddr(struct bge_softc *sc)
 534 {
 535 #ifdef __sparc64__
 536         char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
 537         device_t dev;
 538         uint32_t subvendor;
 539
 540         dev = sc->bge_dev;
 541
 542         /*
 543          * The on-board BGEs found in sun4u machines aren't fitted with
 544          * an EEPROM which means that we have to obtain the MAC address
 545          * via OFW and that some tests will always fail.  We distinguish
 546          * such BGEs by the subvendor ID, which also has to be obtained
 547          * from OFW instead of the PCI configuration space as the latter
 548          * indicates Broadcom as the subvendor of the netboot interface.
 549          * For early Blade 1500 and 2500 we even have to check the OFW
 550          * device path as the subvendor ID always defaults to Broadcom
 551          * there.
 552          */
 553         if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
 554             &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
 555             (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID))
 556                 return (0);
 557         memset(buf, 0, sizeof(buf));
 558         if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
 559                 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
 560                     strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
 561                         return (0);
 562                 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
 563                     strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
 564                         return (0);
 565         }
 566 #endif
 567         return (1);
 568 }
 569
 570 static uint32_t
 571 bge_readmem_ind(struct bge_softc *sc, int off)
 572 {
 573         device_t dev;
 574         uint32_t val;
 575
 576         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 577             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 578                 return (0);
 579
 580         dev = sc->bge_dev;
 581
 582         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 583         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 584         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 585         return (val);
 586 }
 587
 588 static void
 589 bge_writemem_ind(struct bge_softc *sc, int off, int val)
 590 {
 591         device_t dev;
 592
 593         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 594             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 595                 return;
 596
 597         dev = sc->bge_dev;
 598
 599         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 600         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 601         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 602 }
 603
 604 #ifdef notdef
 605 static uint32_t
 606 bge_readreg_ind(struct bge_softc *sc, int off)
 607 {
 608         device_t dev;
 609
 610         dev = sc->bge_dev;
 611
 612         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 613         return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 614 }
 615 #endif
 616
 617 static void
 618 bge_writereg_ind(struct bge_softc *sc, int off, int val)
 619 {
 620         device_t dev;
 621
 622         dev = sc->bge_dev;
 623
 624         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 625         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 626 }
 627
 628 static void
 629 bge_writemem_direct(struct bge_softc *sc, int off, int val)
 630 {
 631         CSR_WRITE_4(sc, off, val);
 632 }
 633
 634 static void
 635 bge_writembx(struct bge_softc *sc, int off, int val)
 636 {
 637         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 638                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 639
 640         CSR_WRITE_4(sc, off, val);
 641         if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0)
 642                 CSR_READ_4(sc, off);
 643 }
 644
 645 /*
 646  * Map a single buffer address.
 647  */
 648
 649 static void
 650 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 651 {
 652         struct bge_dmamap_arg *ctx;
 653
 654         if (error)
 655                 return;
 656
 657         KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
 658
 659         ctx = arg;
 660         ctx->bge_busaddr = segs->ds_addr;
 661 }
 662
 663 static uint8_t
 664 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 665 {
 666         uint32_t access, byte = 0;
 667         int i;
 668
 669         /* Lock. */
 670         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 671         for (i = 0; i < 8000; i++) {
 672                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 673                         break;
 674                 DELAY(20);
 675         }
 676         if (i == 8000)
 677                 return (1);
 678
 679         /* Enable access. */
 680         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 681         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 682
 683         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 684         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 685         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 686                 DELAY(10);
 687                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 688                         DELAY(10);
 689                         break;
 690                 }
 691         }
 692
 693         if (i == BGE_TIMEOUT * 10) {
 694                 if_printf(sc->bge_ifp, "nvram read timed out\n");
 695                 return (1);
 696         }
 697
 698         /* Get result. */
 699         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 700
 701         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 702
 703         /* Disable access. */
 704         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 705
 706         /* Unlock. */
 707         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 708         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 709
 710         return (0);
 711 }
 712
 713 /*
 714  * Read a sequence of bytes from NVRAM.
 715  */
 716 static int
 717 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 718 {
 719         int err = 0, i;
 720         uint8_t byte = 0;
 721
 722         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 723                 return (1);
 724
 725         for (i = 0; i < cnt; i++) {
 726                 err = bge_nvram_getbyte(sc, off + i, &byte);
 727                 if (err)
 728                         break;
 729                 *(dest + i) = byte;
 730         }
 731
 732         return (err ? 1 : 0);
 733 }
 734
 735 /*
 736  * Read a byte of data stored in the EEPROM at address 'addr.' The
 737  * BCM570x supports both the traditional bitbang interface and an
 738  * auto access interface for reading the EEPROM. We use the auto
 739  * access method.
 740  */
 741 static uint8_t
 742 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 743 {
 744         int i;
 745         uint32_t byte = 0;
 746
 747         /*
 748          * Enable use of auto EEPROM access so we can avoid
 749          * having to use the bitbang method.
 750          */
 751         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 752
 753         /* Reset the EEPROM, load the clock period. */
 754         CSR_WRITE_4(sc, BGE_EE_ADDR,
 755             BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 756         DELAY(20);
 757
 758         /* Issue the read EEPROM command. */
 759         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 760
 761         /* Wait for completion */
 762         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 763                 DELAY(10);
 764                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 765                         break;
 766         }
 767
 768         if (i == BGE_TIMEOUT * 10) {
 769                 device_printf(sc->bge_dev, "EEPROM read timed out\n");
 770                 return (1);
 771         }
 772
 773         /* Get result. */
 774         byte = CSR_READ_4(sc, BGE_EE_DATA);
 775
 776         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 777
 778         return (0);
 779 }
 780
 781 /*
 782  * Read a sequence of bytes from the EEPROM.
 783  */
 784 static int
 785 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 786 {
 787         int i, error = 0;
 788         uint8_t byte = 0;
 789
 790         for (i = 0; i < cnt; i++) {
 791                 error = bge_eeprom_getbyte(sc, off + i, &byte);
 792                 if (error)
 793                         break;
 794                 *(dest + i) = byte;
 795         }
 796
 797         return (error ? 1 : 0);
 798 }
 799
 800 static int
 801 bge_miibus_readreg(device_t dev, int phy, int reg)
 802 {
 803         struct bge_softc *sc;
 804         uint32_t val;
 805         int i;
 806
 807         sc = device_get_softc(dev);
 808
 809         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 810         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
 811                 CSR_WRITE_4(sc, BGE_MI_MODE,
 812                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 813                 DELAY(80);
 814         }
 815
 816         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 817             BGE_MIPHY(phy) | BGE_MIREG(reg));
 818
 819         /* Poll for the PHY register access to complete. */
 820         for (i = 0; i < BGE_TIMEOUT; i++) {
 821                 DELAY(10);
 822                 val = CSR_READ_4(sc, BGE_MI_COMM);
 823                 if ((val & BGE_MICOMM_BUSY) == 0) {
 824                         DELAY(5);
 825                         val = CSR_READ_4(sc, BGE_MI_COMM);
 826                         break;
 827                 }
 828         }
 829
 830         if (i == BGE_TIMEOUT) {
 831                 device_printf(sc->bge_dev,
 832                     "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
 833                     phy, reg, val);
 834                 val = 0;
 835         }
 836
 837         /* Restore the autopoll bit if necessary. */
 838         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
 839                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
 840                 DELAY(80);
 841         }
 842
 843         if (val & BGE_MICOMM_READFAIL)
 844                 return (0);
 845
 846         return (val & 0xFFFF);
 847 }
 848
 849 static int
 850 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 851 {
 852         struct bge_softc *sc;
 853         int i;
 854
 855         sc = device_get_softc(dev);
 856
 857         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 858             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 859                 return (0);
 860
 861         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 862         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
 863                 CSR_WRITE_4(sc, BGE_MI_MODE,
 864                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 865                 DELAY(80);
 866         }
 867
 868         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 869             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 870
 871         for (i = 0; i < BGE_TIMEOUT; i++) {
 872                 DELAY(10);
 873                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 874                         DELAY(5);
 875                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 876                         break;
 877                 }
 878         }
 879
 880         /* Restore the autopoll bit if necessary. */
 881         if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
 882                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
 883                 DELAY(80);
 884         }
 885
 886         if (i == BGE_TIMEOUT)
 887                 device_printf(sc->bge_dev,
 888                     "PHY write timed out (phy %d, reg %d, val %d)\n",
 889                     phy, reg, val);
 890
 891         return (0);
 892 }
 893
 894 static void
 895 bge_miibus_statchg(device_t dev)
 896 {
 897         struct bge_softc *sc;
 898         struct mii_data *mii;
 899         sc = device_get_softc(dev);
 900         mii = device_get_softc(sc->bge_miibus);
 901
 902         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 903             (IFM_ACTIVE | IFM_AVALID)) {
 904                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 905                 case IFM_10_T:
 906                 case IFM_100_TX:
 907                         sc->bge_link = 1;
 908                         break;
 909                 case IFM_1000_T:
 910                 case IFM_1000_SX:
 911                 case IFM_2500_SX:
 912                         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 913                                 sc->bge_link = 1;
 914                         else
 915                                 sc->bge_link = 0;
 916                         break;
 917                 default:
 918                         sc->bge_link = 0;
 919                         break;
 920                 }
 921         } else
 922                 sc->bge_link = 0;
 923         if (sc->bge_link == 0)
 924                 return;
 925         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 926         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 927             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
 928                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 929         else
 930                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 931
 932         if (IFM_OPTIONS(mii->mii_media_active & IFM_FDX) != 0) {
 933                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 934                 if ((IFM_OPTIONS(mii->mii_media_active) &
 935                     IFM_ETH_TXPAUSE) != 0)
 936                         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
 937                 else
 938                         BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
 939                 if ((IFM_OPTIONS(mii->mii_media_active) &
 940                     IFM_ETH_RXPAUSE) != 0)
 941                         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
 942                 else
 943                         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
 944         } else {
 945                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 946                 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
 947                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
 948         }
 949 }
 950
 951 /*
 952  * Intialize a standard receive ring descriptor.
 953  */
 954 static int
 955 bge_newbuf_std(struct bge_softc *sc, int i)
 956 {
 957         struct mbuf *m;
 958         struct bge_rx_bd *r;
 959         bus_dma_segment_t segs[1];
 960         bus_dmamap_t map;
 961         int error, nsegs;
 962
 963         if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
 964             (sc->bge_ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN +
 965             ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) {
 966                 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
 967                 if (m == NULL)
 968                         return (ENOBUFS);
 969                 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
 970         } else {
 971                 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
 972                 if (m == NULL)
 973                         return (ENOBUFS);
 974                 m->m_len = m->m_pkthdr.len = MCLBYTES;
 975         }
 976         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 977                 m_adj(m, ETHER_ALIGN);
 978
 979         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
 980             sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
 981         if (error != 0) {
 982                 m_freem(m);
 983                 return (error);
 984         }
 985         if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 986                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 987                     sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
 988                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 989                     sc->bge_cdata.bge_rx_std_dmamap[i]);
 990         }
 991         map = sc->bge_cdata.bge_rx_std_dmamap[i];
 992         sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
 993         sc->bge_cdata.bge_rx_std_sparemap = map;
 994         sc->bge_cdata.bge_rx_std_chain[i] = m;
 995         sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
 996         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
 997         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
 998         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
 999         r->bge_flags = BGE_RXBDFLAG_END;
1000         r->bge_len = segs[0].ds_len;
1001         r->bge_idx = i;
1002
1003         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1004             sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
1005
1006         return (0);
1007 }
1008
1009 /*
1010  * Initialize a jumbo receive ring descriptor. This allocates
1011  * a jumbo buffer from the pool managed internally by the driver.
1012  */
1013 static int
1014 bge_newbuf_jumbo(struct bge_softc *sc, int i)
1015 {
1016         bus_dma_segment_t segs[BGE_NSEG_JUMBO];
1017         bus_dmamap_t map;
1018         struct bge_extrx_bd *r;
1019         struct mbuf *m;
1020         int error, nsegs;
1021
1022         MGETHDR(m, M_DONTWAIT, MT_DATA);
1023         if (m == NULL)
1024                 return (ENOBUFS);
1025
1026         m_cljget(m, M_DONTWAIT, MJUM9BYTES);
1027         if (!(m->m_flags & M_EXT)) {
1028                 m_freem(m);
1029                 return (ENOBUFS);
1030         }
1031         m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1032         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1033                 m_adj(m, ETHER_ALIGN);
1034
1035         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1036             sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1037         if (error != 0) {
1038                 m_freem(m);
1039                 return (error);
1040         }
1041
1042         if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1043                 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1044                     sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1045                 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1046                     sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1047         }
1048         map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1049         sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1050             sc->bge_cdata.bge_rx_jumbo_sparemap;
1051         sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1052         sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1053         sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1054         sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1055         sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1056         sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1057
1058         /*
1059          * Fill in the extended RX buffer descriptor.
1060          */
1061         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1062         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1063         r->bge_idx = i;
1064         r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1065         switch (nsegs) {
1066         case 4:
1067                 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1068                 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1069                 r->bge_len3 = segs[3].ds_len;
1070                 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1071         case 3:
1072                 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1073                 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1074                 r->bge_len2 = segs[2].ds_len;
1075                 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1076         case 2:
1077                 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1078                 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1079                 r->bge_len1 = segs[1].ds_len;
1080                 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1081         case 1:
1082                 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1083                 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1084                 r->bge_len0 = segs[0].ds_len;
1085                 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1086                 break;
1087         default:
1088                 panic("%s: %d segments\n", __func__, nsegs);
1089         }
1090
1091         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1092             sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1093
1094         return (0);
1095 }
1096
1097 static int
1098 bge_init_rx_ring_std(struct bge_softc *sc)
1099 {
1100         int error, i;
1101
1102         bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1103         sc->bge_std = 0;
1104         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1105                 if ((error = bge_newbuf_std(sc, i)) != 0)
1106                         return (error);
1107                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1108         }
1109
1110         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1111             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1112
1113         sc->bge_std = 0;
1114         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1115
1116         return (0);
1117 }
1118
1119 static void
1120 bge_free_rx_ring_std(struct bge_softc *sc)
1121 {
1122         int i;
1123
1124         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1125                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1126                         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1127                             sc->bge_cdata.bge_rx_std_dmamap[i],
1128                             BUS_DMASYNC_POSTREAD);
1129                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1130                             sc->bge_cdata.bge_rx_std_dmamap[i]);
1131                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1132                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1133                 }
1134                 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1135                     sizeof(struct bge_rx_bd));
1136         }
1137 }
1138
1139 static int
1140 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1141 {
1142         struct bge_rcb *rcb;
1143         int error, i;
1144
1145         bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1146         sc->bge_jumbo = 0;
1147         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1148                 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1149                         return (error);
1150                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1151         }
1152
1153         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1154             sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1155
1156         sc->bge_jumbo = 0;
1157
1158         /* Enable the jumbo receive producer ring. */
1159         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1160         rcb->bge_maxlen_flags =
1161             BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD);
1162         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1163
1164         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1165
1166         return (0);
1167 }
1168
1169 static void
1170 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1171 {
1172         int i;
1173
1174         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1175                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1176                         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1177                             sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1178                             BUS_DMASYNC_POSTREAD);
1179                         bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1180                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1181                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1182                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1183                 }
1184                 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1185                     sizeof(struct bge_extrx_bd));
1186         }
1187 }
1188
1189 static void
1190 bge_free_tx_ring(struct bge_softc *sc)
1191 {
1192         int i;
1193
1194         if (sc->bge_ldata.bge_tx_ring == NULL)
1195                 return;
1196
1197         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1198                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1199                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1200                             sc->bge_cdata.bge_tx_dmamap[i],
1201                             BUS_DMASYNC_POSTWRITE);
1202                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1203                             sc->bge_cdata.bge_tx_dmamap[i]);
1204                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1205                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1206                 }
1207                 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1208                     sizeof(struct bge_tx_bd));
1209         }
1210 }
1211
1212 static int
1213 bge_init_tx_ring(struct bge_softc *sc)
1214 {
1215         sc->bge_txcnt = 0;
1216         sc->bge_tx_saved_considx = 0;
1217
1218         bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1219         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1220             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1221
1222         /* Initialize transmit producer index for host-memory send ring. */
1223         sc->bge_tx_prodidx = 0;
1224         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1225
1226         /* 5700 b2 errata */
1227         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1228                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1229
1230         /* NIC-memory send ring not used; initialize to zero. */
1231         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1232         /* 5700 b2 errata */
1233         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1234                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1235
1236         return (0);
1237 }
1238
1239 static void
1240 bge_setpromisc(struct bge_softc *sc)
1241 {
1242         struct ifnet *ifp;
1243
1244         BGE_LOCK_ASSERT(sc);
1245
1246         ifp = sc->bge_ifp;
1247
1248         /* Enable or disable promiscuous mode as needed. */
1249         if (ifp->if_flags & IFF_PROMISC)
1250                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1251         else
1252                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1253 }
1254
1255 static void
1256 bge_setmulti(struct bge_softc *sc)
1257 {
1258         struct ifnet *ifp;
1259         struct ifmultiaddr *ifma;
1260         uint32_t hashes[4] = { 0, 0, 0, 0 };
1261         int h, i;
1262
1263         BGE_LOCK_ASSERT(sc);
1264
1265         ifp = sc->bge_ifp;
1266
1267         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1268                 for (i = 0; i < 4; i++)
1269                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1270                 return;
1271         }
1272
1273         /* First, zot all the existing filters. */
1274         for (i = 0; i < 4; i++)
1275                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1276
1277         /* Now program new ones. */
1278         if_maddr_rlock(ifp);
1279         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1280                 if (ifma->ifma_addr->sa_family != AF_LINK)
1281                         continue;
1282                 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1283                     ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1284                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1285         }
1286         if_maddr_runlock(ifp);
1287
1288         for (i = 0; i < 4; i++)
1289                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1290 }
1291
1292 static void
1293 bge_setvlan(struct bge_softc *sc)
1294 {
1295         struct ifnet *ifp;
1296
1297         BGE_LOCK_ASSERT(sc);
1298
1299         ifp = sc->bge_ifp;
1300
1301         /* Enable or disable VLAN tag stripping as needed. */
1302         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1303                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1304         else
1305                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1306 }
1307
1308 static void
1309 bge_sig_pre_reset(struct bge_softc *sc, int type)
1310 {
1311
1312         /*
1313          * Some chips don't like this so only do this if ASF is enabled
1314          */
1315         if (sc->bge_asf_mode)
1316                 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
1317
1318         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1319                 switch (type) {
1320                 case BGE_RESET_START:
1321                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1322                             BGE_FW_DRV_STATE_START);
1323                         break;
1324                 case BGE_RESET_STOP:
1325                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1326                             BGE_FW_DRV_STATE_UNLOAD);
1327                         break;
1328                 }
1329         }
1330 }
1331
1332 static void
1333 bge_sig_post_reset(struct bge_softc *sc, int type)
1334 {
1335
1336         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1337                 switch (type) {
1338                 case BGE_RESET_START:
1339                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1340                             BGE_FW_DRV_STATE_START_DONE);
1341                         /* START DONE */
1342                         break;
1343                 case BGE_RESET_STOP:
1344                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1345                             BGE_FW_DRV_STATE_UNLOAD_DONE);
1346                         break;
1347                 }
1348         }
1349 }
1350
1351 static void
1352 bge_sig_legacy(struct bge_softc *sc, int type)
1353 {
1354
1355         if (sc->bge_asf_mode) {
1356                 switch (type) {
1357                 case BGE_RESET_START:
1358                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1359                             BGE_FW_DRV_STATE_START);
1360                         break;
1361                 case BGE_RESET_STOP:
1362                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1363                             BGE_FW_DRV_STATE_UNLOAD);
1364                         break;
1365                 }
1366         }
1367 }
1368
1369 static void
1370 bge_stop_fw(struct bge_softc *sc)
1371 {
1372         int i;
1373
1374         if (sc->bge_asf_mode) {
1375                 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
1376                 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
1377                     CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
1378
1379                 for (i = 0; i < 100; i++ ) {
1380                         if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1381                             BGE_RX_CPU_DRV_EVENT))
1382                                 break;
1383                         DELAY(10);
1384                 }
1385         }
1386 }
1387
1388 static uint32_t
1389 bge_dma_swap_options(struct bge_softc *sc)
1390 {
1391         uint32_t dma_options;
1392
1393         dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
1394             BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
1395 #if BYTE_ORDER == BIG_ENDIAN
1396         dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
1397 #endif
1398         if ((sc)->bge_asicrev == BGE_ASICREV_BCM5720)
1399                 dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA |
1400                     BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE |
1401                     BGE_MODECTL_HTX2B_ENABLE;
1402
1403         return (dma_options);
1404 }
1405
1406 /*
1407  * Do endian, PCI and DMA initialization.
1408  */
1409 static int
1410 bge_chipinit(struct bge_softc *sc)
1411 {
1412         uint32_t dma_rw_ctl, misc_ctl, mode_ctl;
1413         uint16_t val;
1414         int i;
1415
1416         /* Set endianness before we access any non-PCI registers. */
1417         misc_ctl = BGE_INIT;
1418         if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1419                 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1420         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1421
1422         /* Clear the MAC control register */
1423         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1424
1425         /*
1426          * Clear the MAC statistics block in the NIC's
1427          * internal memory.
1428          */
1429         for (i = BGE_STATS_BLOCK;
1430             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1431                 BGE_MEMWIN_WRITE(sc, i, 0);
1432
1433         for (i = BGE_STATUS_BLOCK;
1434             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1435                 BGE_MEMWIN_WRITE(sc, i, 0);
1436
1437         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1438                 /*
1439                  *  Fix data corruption caused by non-qword write with WB.
1440                  *  Fix master abort in PCI mode.
1441                  *  Fix PCI latency timer.
1442                  */
1443                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1444                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1445                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1446         }
1447
1448         /*
1449          * Set up the PCI DMA control register.
1450          */
1451         dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1452             BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1453         if (sc->bge_flags & BGE_FLAG_PCIE) {
1454                 /* Read watermark not used, 128 bytes for write. */
1455                 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1456         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1457                 if (BGE_IS_5714_FAMILY(sc)) {
1458                         /* 256 bytes for read and write. */
1459                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1460                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1461                         dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1462                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1463                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1464                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1465                         /*
1466                          * In the BCM5703, the DMA read watermark should
1467                          * be set to less than or equal to the maximum
1468                          * memory read byte count of the PCI-X command
1469                          * register.
1470                          */
1471                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1472                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1473                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1474                         /* 1536 bytes for read, 384 bytes for write. */
1475                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1476                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1477                 } else {
1478                         /* 384 bytes for read and write. */
1479                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1480                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1481                             0x0F;
1482                 }
1483                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1484                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1485                         uint32_t tmp;
1486
1487                         /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1488                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1489                         if (tmp == 6 || tmp == 7)
1490                                 dma_rw_ctl |=
1491                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1492
1493                         /* Set PCI-X DMA write workaround. */
1494                         dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1495                 }
1496         } else {
1497                 /* Conventional PCI bus: 256 bytes for read and write. */
1498                 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1499                     BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1500
1501                 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1502                     sc->bge_asicrev != BGE_ASICREV_BCM5750)
1503                         dma_rw_ctl |= 0x0F;
1504         }
1505         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1506             sc->bge_asicrev == BGE_ASICREV_BCM5701)
1507                 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1508                     BGE_PCIDMARWCTL_ASRT_ALL_BE;
1509         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1510             sc->bge_asicrev == BGE_ASICREV_BCM5704)
1511                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1512         if (BGE_IS_5717_PLUS(sc)) {
1513                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1514                 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
1515                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1516                 /*
1517                  * Enable HW workaround for controllers that misinterpret
1518                  * a status tag update and leave interrupts permanently
1519                  * disabled.
1520                  */
1521                 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
1522                     sc->bge_asicrev != BGE_ASICREV_BCM57765)
1523                         dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1524         }
1525         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1526
1527         /*
1528          * Set up general mode register.
1529          */
1530         mode_ctl = bge_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1531             BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM;
1532
1533         /*
1534          * BCM5701 B5 have a bug causing data corruption when using
1535          * 64-bit DMA reads, which can be terminated early and then
1536          * completed later as 32-bit accesses, in combination with
1537          * certain bridges.
1538          */
1539         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1540             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1541                 mode_ctl |= BGE_MODECTL_FORCE_PCI32;
1542
1543         /*
1544          * Tell the firmware the driver is running
1545          */
1546         if (sc->bge_asf_mode & ASF_STACKUP)
1547                 mode_ctl |= BGE_MODECTL_STACKUP;
1548
1549         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1550
1551         /*
1552          * Disable memory write invalidate.  Apparently it is not supported
1553          * properly by these devices.  Also ensure that INTx isn't disabled,
1554          * as these chips need it even when using MSI.
1555          */
1556         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1557             PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
1558
1559         /* Set the timer prescaler (always 66Mhz) */
1560         CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1561
1562         /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1563         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1564                 DELAY(40);      /* XXX */
1565
1566                 /* Put PHY into ready state */
1567                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1568                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1569                 DELAY(40);
1570         }
1571
1572         return (0);
1573 }
1574
1575 static int
1576 bge_blockinit(struct bge_softc *sc)
1577 {
1578         struct bge_rcb *rcb;
1579         bus_size_t vrcb;
1580         bge_hostaddr taddr;
1581         uint32_t dmactl, val;
1582         int i, limit;
1583
1584         /*
1585          * Initialize the memory window pointer register so that
1586          * we can access the first 32K of internal NIC RAM. This will
1587          * allow us to set up the TX send ring RCBs and the RX return
1588          * ring RCBs, plus other things which live in NIC memory.
1589          */
1590         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1591
1592         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1593
1594         if (!(BGE_IS_5705_PLUS(sc))) {
1595                 /* Configure mbuf memory pool */
1596                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1597                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1598                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1599                 else
1600                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1601
1602                 /* Configure DMA resource pool */
1603                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1604                     BGE_DMA_DESCRIPTORS);
1605                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1606         }
1607
1608         /* Configure mbuf pool watermarks */
1609         if (BGE_IS_5717_PLUS(sc)) {
1610                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1611                 if (sc->bge_ifp->if_mtu > ETHERMTU) {
1612                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1613                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1614                 } else {
1615                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1616                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1617                 }
1618         } else if (!BGE_IS_5705_PLUS(sc)) {
1619                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1620                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1621                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1622         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1623                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1624                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1625                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1626         } else {
1627                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1628                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1629                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1630         }
1631
1632         /* Configure DMA resource watermarks */
1633         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1634         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1635
1636         /* Enable buffer manager */
1637         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1638         /*
1639          * Change the arbitration algorithm of TXMBUF read request to
1640          * round-robin instead of priority based for BCM5719.  When
1641          * TXFIFO is almost empty, RDMA will hold its request until
1642          * TXFIFO is not almost empty.
1643          */
1644         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
1645                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1646         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1647
1648         /* Poll for buffer manager start indication */
1649         for (i = 0; i < BGE_TIMEOUT; i++) {
1650                 DELAY(10);
1651                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1652                         break;
1653         }
1654
1655         if (i == BGE_TIMEOUT) {
1656                 device_printf(sc->bge_dev, "buffer manager failed to start\n");
1657                 return (ENXIO);
1658         }
1659
1660         /* Enable flow-through queues */
1661         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1662         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1663
1664         /* Wait until queue initialization is complete */
1665         for (i = 0; i < BGE_TIMEOUT; i++) {
1666                 DELAY(10);
1667                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1668                         break;
1669         }
1670
1671         if (i == BGE_TIMEOUT) {
1672                 device_printf(sc->bge_dev, "flow-through queue init failed\n");
1673                 return (ENXIO);
1674         }
1675
1676         /*
1677          * Summary of rings supported by the controller:
1678          *
1679          * Standard Receive Producer Ring
1680          * - This ring is used to feed receive buffers for "standard"
1681          *   sized frames (typically 1536 bytes) to the controller.
1682          *
1683          * Jumbo Receive Producer Ring
1684          * - This ring is used to feed receive buffers for jumbo sized
1685          *   frames (i.e. anything bigger than the "standard" frames)
1686          *   to the controller.
1687          *
1688          * Mini Receive Producer Ring
1689          * - This ring is used to feed receive buffers for "mini"
1690          *   sized frames to the controller.
1691          * - This feature required external memory for the controller
1692          *   but was never used in a production system.  Should always
1693          *   be disabled.
1694          *
1695          * Receive Return Ring
1696          * - After the controller has placed an incoming frame into a
1697          *   receive buffer that buffer is moved into a receive return
1698          *   ring.  The driver is then responsible to passing the
1699          *   buffer up to the stack.  Many versions of the controller
1700          *   support multiple RR rings.
1701          *
1702          * Send Ring
1703          * - This ring is used for outgoing frames.  Many versions of
1704          *   the controller support multiple send rings.
1705          */
1706
1707         /* Initialize the standard receive producer ring control block. */
1708         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1709         rcb->bge_hostaddr.bge_addr_lo =
1710             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1711         rcb->bge_hostaddr.bge_addr_hi =
1712             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1713         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1714             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1715         if (BGE_IS_5717_PLUS(sc)) {
1716                 /*
1717                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1718                  * Bits 15-2 : Maximum RX frame size
1719                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
1720                  * Bit 0     : Reserved
1721                  */
1722                 rcb->bge_maxlen_flags =
1723                     BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
1724         } else if (BGE_IS_5705_PLUS(sc)) {
1725                 /*
1726                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1727                  * Bits 15-2 : Reserved (should be 0)
1728                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1729                  * Bit 0     : Reserved
1730                  */
1731                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1732         } else {
1733                 /*
1734                  * Ring size is always XXX entries
1735                  * Bits 31-16: Maximum RX frame size
1736                  * Bits 15-2 : Reserved (should be 0)
1737                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1738                  * Bit 0     : Reserved
1739                  */
1740                 rcb->bge_maxlen_flags =
1741                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1742         }
1743         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1744             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
1745             sc->bge_asicrev == BGE_ASICREV_BCM5720)
1746                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1747         else
1748                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1749         /* Write the standard receive producer ring control block. */
1750         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1751         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1752         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1753         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1754
1755         /* Reset the standard receive producer ring producer index. */
1756         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1757
1758         /*
1759          * Initialize the jumbo RX producer ring control
1760          * block.  We set the 'ring disabled' bit in the
1761          * flags field until we're actually ready to start
1762          * using this ring (i.e. once we set the MTU
1763          * high enough to require it).
1764          */
1765         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1766                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1767                 /* Get the jumbo receive producer ring RCB parameters. */
1768                 rcb->bge_hostaddr.bge_addr_lo =
1769                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1770                 rcb->bge_hostaddr.bge_addr_hi =
1771                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1772                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1773                     sc->bge_cdata.bge_rx_jumbo_ring_map,
1774                     BUS_DMASYNC_PREREAD);
1775                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1776                     BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1777                 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1778                     sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
1779                     sc->bge_asicrev == BGE_ASICREV_BCM5720)
1780                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1781                 else
1782                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1783                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1784                     rcb->bge_hostaddr.bge_addr_hi);
1785                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1786                     rcb->bge_hostaddr.bge_addr_lo);
1787                 /* Program the jumbo receive producer ring RCB parameters. */
1788                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1789                     rcb->bge_maxlen_flags);
1790                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1791                 /* Reset the jumbo receive producer ring producer index. */
1792                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1793         }
1794
1795         /* Disable the mini receive producer ring RCB. */
1796         if (BGE_IS_5700_FAMILY(sc)) {
1797                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1798                 rcb->bge_maxlen_flags =
1799                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1800                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1801                     rcb->bge_maxlen_flags);
1802                 /* Reset the mini receive producer ring producer index. */
1803                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1804         }
1805
1806         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1807         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1808                 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
1809                     sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
1810                     sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
1811                         CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1812                             (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1813         }
1814         /*
1815          * The BD ring replenish thresholds control how often the
1816          * hardware fetches new BD's from the producer rings in host
1817          * memory.  Setting the value too low on a busy system can
1818          * starve the hardware and recue the throughpout.
1819          *
1820          * Set the BD ring replentish thresholds. The recommended
1821          * values are 1/8th the number of descriptors allocated to
1822          * each ring.
1823          * XXX The 5754 requires a lower threshold, so it might be a
1824          * requirement of all 575x family chips.  The Linux driver sets
1825          * the lower threshold for all 5705 family chips as well, but there
1826          * are reports that it might not need to be so strict.
1827          *
1828          * XXX Linux does some extra fiddling here for the 5906 parts as
1829          * well.
1830          */
1831         if (BGE_IS_5705_PLUS(sc))
1832                 val = 8;
1833         else
1834                 val = BGE_STD_RX_RING_CNT / 8;
1835         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1836         if (BGE_IS_JUMBO_CAPABLE(sc))
1837                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1838                     BGE_JUMBO_RX_RING_CNT/8);
1839         if (BGE_IS_5717_PLUS(sc)) {
1840                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1841                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1842         }
1843
1844         /*
1845          * Disable all send rings by setting the 'ring disabled' bit
1846          * in the flags field of all the TX send ring control blocks,
1847          * located in NIC memory.
1848          */
1849         if (!BGE_IS_5705_PLUS(sc))
1850                 /* 5700 to 5704 had 16 send rings. */
1851                 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
1852         else
1853                 limit = 1;
1854         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1855         for (i = 0; i < limit; i++) {
1856                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1857                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1858                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1859                 vrcb += sizeof(struct bge_rcb);
1860         }
1861
1862         /* Configure send ring RCB 0 (we use only the first ring) */
1863         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1864         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1865         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1866         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1867         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1868             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
1869             sc->bge_asicrev == BGE_ASICREV_BCM5720)
1870                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1871         else
1872                 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1873                     BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1874         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1875             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1876
1877         /*
1878          * Disable all receive return rings by setting the
1879          * 'ring diabled' bit in the flags field of all the receive
1880          * return ring control blocks, located in NIC memory.
1881          */
1882         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
1883             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
1884             sc->bge_asicrev == BGE_ASICREV_BCM5720) {
1885                 /* Should be 17, use 16 until we get an SRAM map. */
1886                 limit = 16;
1887         } else if (!BGE_IS_5705_PLUS(sc))
1888                 limit = BGE_RX_RINGS_MAX;
1889         else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1890             sc->bge_asicrev == BGE_ASICREV_BCM57765)
1891                 limit = 4;
1892         else
1893                 limit = 1;
1894         /* Disable all receive return rings. */
1895         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1896         for (i = 0; i < limit; i++) {
1897                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1898                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1899                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1900                     BGE_RCB_FLAG_RING_DISABLED);
1901                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1902                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1903                     (i * (sizeof(uint64_t))), 0);
1904                 vrcb += sizeof(struct bge_rcb);
1905         }
1906
1907         /*
1908          * Set up receive return ring 0.  Note that the NIC address
1909          * for RX return rings is 0x0.  The return rings live entirely
1910          * within the host, so the nicaddr field in the RCB isn't used.
1911          */
1912         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1913         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1914         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1915         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1916         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1917         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1918             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1919
1920         /* Set random backoff seed for TX */
1921         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1922             IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1923             IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1924             IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1925             BGE_TX_BACKOFF_SEED_MASK);
1926
1927         /* Set inter-packet gap */
1928         val = 0x2620;
1929         if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
1930                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1931                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
1932         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1933
1934         /*
1935          * Specify which ring to use for packets that don't match
1936          * any RX rules.
1937          */
1938         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1939
1940         /*
1941          * Configure number of RX lists. One interrupt distribution
1942          * list, sixteen active lists, one bad frames class.
1943          */
1944         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1945
1946         /* Inialize RX list placement stats mask. */
1947         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1948         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1949
1950         /* Disable host coalescing until we get it set up */
1951         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1952
1953         /* Poll to make sure it's shut down. */
1954         for (i = 0; i < BGE_TIMEOUT; i++) {
1955                 DELAY(10);
1956                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1957                         break;
1958         }
1959
1960         if (i == BGE_TIMEOUT) {
1961                 device_printf(sc->bge_dev,
1962                     "host coalescing engine failed to idle\n");
1963                 return (ENXIO);
1964         }
1965
1966         /* Set up host coalescing defaults */
1967         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1968         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1969         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1970         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1971         if (!(BGE_IS_5705_PLUS(sc))) {
1972                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1973                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1974         }
1975         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1976         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1977
1978         /* Set up address of statistics block */
1979         if (!(BGE_IS_5705_PLUS(sc))) {
1980                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1981                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1982                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1983                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1984                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1985                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1986                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1987         }
1988
1989         /* Set up address of status block */
1990         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1991             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1992         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1993             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1994
1995         /* Set up status block size. */
1996         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1997             sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
1998                 val = BGE_STATBLKSZ_FULL;
1999                 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2000         } else {
2001                 val = BGE_STATBLKSZ_32BYTE;
2002                 bzero(sc->bge_ldata.bge_status_block, 32);
2003         }
2004         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2005             sc->bge_cdata.bge_status_map,
2006             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2007
2008         /* Turn on host coalescing state machine */
2009         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2010
2011         /* Turn on RX BD completion state machine and enable attentions */
2012         CSR_WRITE_4(sc, BGE_RBDC_MODE,
2013             BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
2014
2015         /* Turn on RX list placement state machine */
2016         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2017
2018         /* Turn on RX list selector state machine. */
2019         if (!(BGE_IS_5705_PLUS(sc)))
2020                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2021
2022         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
2023             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
2024             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
2025             BGE_MACMODE_FRMHDR_DMA_ENB;
2026
2027         if (sc->bge_flags & BGE_FLAG_TBI)
2028                 val |= BGE_PORTMODE_TBI;
2029         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
2030                 val |= BGE_PORTMODE_GMII;
2031         else
2032                 val |= BGE_PORTMODE_MII;
2033
2034         /* Turn on DMA, clear stats */
2035         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
2036
2037         /* Set misc. local control, enable interrupts on attentions */
2038         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2039
2040 #ifdef notdef
2041         /* Assert GPIO pins for PHY reset */
2042         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
2043             BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
2044         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
2045             BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
2046 #endif
2047
2048         /* Turn on DMA completion state machine */
2049         if (!(BGE_IS_5705_PLUS(sc)))
2050                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2051
2052         val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
2053
2054         /* Enable host coalescing bug fix. */
2055         if (BGE_IS_5755_PLUS(sc))
2056                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
2057
2058         /* Request larger DMA burst size to get better performance. */
2059         if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
2060                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
2061
2062         /* Turn on write DMA state machine */
2063         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
2064         DELAY(40);
2065
2066         /* Turn on read DMA state machine */
2067         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
2068
2069         if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
2070                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
2071
2072         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2073             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2074             sc->bge_asicrev == BGE_ASICREV_BCM57780)
2075                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
2076                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
2077                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
2078         if (sc->bge_flags & BGE_FLAG_PCIE)
2079                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2080         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2081                 val |= BGE_RDMAMODE_TSO4_ENABLE;
2082                 if (sc->bge_flags & BGE_FLAG_TSO3 ||
2083                     sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2084                     sc->bge_asicrev == BGE_ASICREV_BCM57780)
2085                         val |= BGE_RDMAMODE_TSO6_ENABLE;
2086         }
2087
2088         if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2089                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
2090                         BGE_RDMAMODE_H2BNC_VLAN_DET;
2091                 /*
2092                  * Allow multiple outstanding read requests from
2093                  * non-LSO read DMA engine.
2094                  */
2095                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
2096         }
2097
2098         if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2099             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2100             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2101             sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2102             BGE_IS_5717_PLUS(sc)) {
2103                 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
2104                 /*
2105                  * Adjust tx margin to prevent TX data corruption and
2106                  * fix internal FIFO overflow.
2107                  */
2108                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2109                     sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2110                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2111                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2112                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2113                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2114                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2115                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2116                 }
2117                 /*
2118                  * Enable fix for read DMA FIFO overruns.
2119                  * The fix is to limit the number of RX BDs
2120                  * the hardware would fetch at a fime.
2121                  */
2122                 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl |
2123                     BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2124         }
2125
2126         if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2127                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2128                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2129                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2130                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2131         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2132                 /*
2133                  * Allow 4KB burst length reads for non-LSO frames.
2134                  * Enable 512B burst length reads for buffer descriptors.
2135                  */
2136                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2137                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2138                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
2139                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2140         }
2141
2142         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2143         DELAY(40);
2144
2145         /* Turn on RX data completion state machine */
2146         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2147
2148         /* Turn on RX BD initiator state machine */
2149         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2150
2151         /* Turn on RX data and RX BD initiator state machine */
2152         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2153
2154         /* Turn on Mbuf cluster free state machine */
2155         if (!(BGE_IS_5705_PLUS(sc)))
2156                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2157
2158         /* Turn on send BD completion state machine */
2159         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2160
2161         /* Turn on send data completion state machine */
2162         val = BGE_SDCMODE_ENABLE;
2163         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2164                 val |= BGE_SDCMODE_CDELAY;
2165         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2166
2167         /* Turn on send data initiator state machine */
2168         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2169                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2170                     BGE_SDIMODE_HW_LSO_PRE_DMA);
2171         else
2172                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2173
2174         /* Turn on send BD initiator state machine */
2175         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2176
2177         /* Turn on send BD selector state machine */
2178         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2179
2180         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
2181         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
2182             BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
2183
2184         /* ack/clear link change events */
2185         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2186             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2187             BGE_MACSTAT_LINK_CHANGED);
2188         CSR_WRITE_4(sc, BGE_MI_STS, 0);
2189
2190         /*
2191          * Enable attention when the link has changed state for
2192          * devices that use auto polling.
2193          */
2194         if (sc->bge_flags & BGE_FLAG_TBI) {
2195                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
2196         } else {
2197                 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2198                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
2199                         DELAY(80);
2200                 }
2201                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2202                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
2203                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2204                             BGE_EVTENB_MI_INTERRUPT);
2205         }
2206
2207         /*
2208          * Clear any pending link state attention.
2209          * Otherwise some link state change events may be lost until attention
2210          * is cleared by bge_intr() -> bge_link_upd() sequence.
2211          * It's not necessary on newer BCM chips - perhaps enabling link
2212          * state change attentions implies clearing pending attention.
2213          */
2214         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2215             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2216             BGE_MACSTAT_LINK_CHANGED);
2217
2218         /* Enable link state change attentions. */
2219         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2220
2221         return (0);
2222 }
2223
2224 const struct bge_revision *
2225 bge_lookup_rev(uint32_t chipid)
2226 {
2227         const struct bge_revision *br;
2228
2229         for (br = bge_revisions; br->br_name != NULL; br++) {
2230                 if (br->br_chipid == chipid)
2231                         return (br);
2232         }
2233
2234         for (br = bge_majorrevs; br->br_name != NULL; br++) {
2235                 if (br->br_chipid == BGE_ASICREV(chipid))
2236                         return (br);
2237         }
2238
2239         return (NULL);
2240 }
2241
2242 const struct bge_vendor *
2243 bge_lookup_vendor(uint16_t vid)
2244 {
2245         const struct bge_vendor *v;
2246
2247         for (v = bge_vendors; v->v_name != NULL; v++)
2248                 if (v->v_id == vid)
2249                         return (v);
2250
2251         panic("%s: unknown vendor %d", __func__, vid);
2252         return (NULL);
2253 }
2254
2255 /*
2256  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
2257  * against our list and return its name if we find a match.
2258  *
2259  * Note that since the Broadcom controller contains VPD support, we
2260  * try to get the device name string from the controller itself instead
2261  * of the compiled-in string. It guarantees we'll always announce the
2262  * right product name. We fall back to the compiled-in string when
2263  * VPD is unavailable or corrupt.
2264  */
2265 static int
2266 bge_probe(device_t dev)
2267 {
2268         char buf[96];
2269         char model[64];
2270         const struct bge_revision *br;
2271         const char *pname;
2272         struct bge_softc *sc = device_get_softc(dev);
2273         const struct bge_type *t = bge_devs;
2274         const struct bge_vendor *v;
2275         uint32_t id;
2276         uint16_t did, vid;
2277
2278         sc->bge_dev = dev;
2279         vid = pci_get_vendor(dev);
2280         did = pci_get_device(dev);
2281         while(t->bge_vid != 0) {
2282                 if ((vid == t->bge_vid) && (did == t->bge_did)) {
2283                         id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2284                             BGE_PCIMISCCTL_ASICREV_SHIFT;
2285                         if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
2286                                 /*
2287                                  * Find the ASCI revision.  Different chips
2288                                  * use different registers.
2289                                  */
2290                                 switch (pci_get_device(dev)) {
2291                                 case BCOM_DEVICEID_BCM5717:
2292                                 case BCOM_DEVICEID_BCM5718:
2293                                 case BCOM_DEVICEID_BCM5719:
2294                                 case BCOM_DEVICEID_BCM5720:
2295                                         id = pci_read_config(dev,
2296                                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
2297                                         break;
2298                                 case BCOM_DEVICEID_BCM57761:
2299                                 case BCOM_DEVICEID_BCM57765:
2300                                 case BCOM_DEVICEID_BCM57781:
2301                                 case BCOM_DEVICEID_BCM57785:
2302                                 case BCOM_DEVICEID_BCM57791:
2303                                 case BCOM_DEVICEID_BCM57795:
2304                                         id = pci_read_config(dev,
2305                                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
2306                                         break;
2307                                 default:
2308                                         id = pci_read_config(dev,
2309                                             BGE_PCI_PRODID_ASICREV, 4);
2310                                 }
2311                         }
2312                         br = bge_lookup_rev(id);
2313                         v = bge_lookup_vendor(vid);
2314                         if (bge_has_eaddr(sc) &&
2315                             pci_get_vpd_ident(dev, &pname) == 0)
2316                                 snprintf(model, 64, "%s", pname);
2317                         else
2318                                 snprintf(model, 64, "%s %s", v->v_name,
2319                                     br != NULL ? br->br_name :
2320                                     "NetXtreme Ethernet Controller");
2321                         snprintf(buf, 96, "%s, %sASIC rev. %#08x", model,
2322                             br != NULL ? "" : "unknown ", id);
2323                         device_set_desc_copy(dev, buf);
2324                         return (0);
2325                 }
2326                 t++;
2327         }
2328
2329         return (ENXIO);
2330 }
2331
2332 static void
2333 bge_dma_free(struct bge_softc *sc)
2334 {
2335         int i;
2336
2337         /* Destroy DMA maps for RX buffers. */
2338         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2339                 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2340                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2341                             sc->bge_cdata.bge_rx_std_dmamap[i]);
2342         }
2343         if (sc->bge_cdata.bge_rx_std_sparemap)
2344                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2345                     sc->bge_cdata.bge_rx_std_sparemap);
2346
2347         /* Destroy DMA maps for jumbo RX buffers. */
2348         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2349                 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2350                         bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2351                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2352         }
2353         if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2354                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2355                     sc->bge_cdata.bge_rx_jumbo_sparemap);
2356
2357         /* Destroy DMA maps for TX buffers. */
2358         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2359                 if (sc->bge_cdata.bge_tx_dmamap[i])
2360                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2361                             sc->bge_cdata.bge_tx_dmamap[i]);
2362         }
2363
2364         if (sc->bge_cdata.bge_rx_mtag)
2365                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2366         if (sc->bge_cdata.bge_mtag_jumbo)
2367                 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
2368         if (sc->bge_cdata.bge_tx_mtag)
2369                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2370
2371
2372         /* Destroy standard RX ring. */
2373         if (sc->bge_cdata.bge_rx_std_ring_map)
2374                 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2375                     sc->bge_cdata.bge_rx_std_ring_map);
2376         if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
2377                 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2378                     sc->bge_ldata.bge_rx_std_ring,
2379                     sc->bge_cdata.bge_rx_std_ring_map);
2380
2381         if (sc->bge_cdata.bge_rx_std_ring_tag)
2382                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2383
2384         /* Destroy jumbo RX ring. */
2385         if (sc->bge_cdata.bge_rx_jumbo_ring_map)
2386                 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2387                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2388
2389         if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
2390             sc->bge_ldata.bge_rx_jumbo_ring)
2391                 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2392                     sc->bge_ldata.bge_rx_jumbo_ring,
2393                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2394
2395         if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2396                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2397
2398         /* Destroy RX return ring. */
2399         if (sc->bge_cdata.bge_rx_return_ring_map)
2400                 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2401                     sc->bge_cdata.bge_rx_return_ring_map);
2402
2403         if (sc->bge_cdata.bge_rx_return_ring_map &&
2404             sc->bge_ldata.bge_rx_return_ring)
2405                 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2406                     sc->bge_ldata.bge_rx_return_ring,
2407                     sc->bge_cdata.bge_rx_return_ring_map);
2408
2409         if (sc->bge_cdata.bge_rx_return_ring_tag)
2410                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2411
2412         /* Destroy TX ring. */
2413         if (sc->bge_cdata.bge_tx_ring_map)
2414                 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2415                     sc->bge_cdata.bge_tx_ring_map);
2416
2417         if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
2418                 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2419                     sc->bge_ldata.bge_tx_ring,
2420                     sc->bge_cdata.bge_tx_ring_map);
2421
2422         if (sc->bge_cdata.bge_tx_ring_tag)
2423                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2424
2425         /* Destroy status block. */
2426         if (sc->bge_cdata.bge_status_map)
2427                 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2428                     sc->bge_cdata.bge_status_map);
2429
2430         if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
2431                 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2432                     sc->bge_ldata.bge_status_block,
2433                     sc->bge_cdata.bge_status_map);
2434
2435         if (sc->bge_cdata.bge_status_tag)
2436                 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2437
2438         /* Destroy statistics block. */
2439         if (sc->bge_cdata.bge_stats_map)
2440                 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2441                     sc->bge_cdata.bge_stats_map);
2442
2443         if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2444                 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2445                     sc->bge_ldata.bge_stats,
2446                     sc->bge_cdata.bge_stats_map);
2447
2448         if (sc->bge_cdata.bge_stats_tag)
2449                 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2450
2451         if (sc->bge_cdata.bge_buffer_tag)
2452                 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
2453
2454         /* Destroy the parent tag. */
2455         if (sc->bge_cdata.bge_parent_tag)
2456                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2457 }
2458
2459 static int
2460 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
2461     bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
2462     bus_addr_t *paddr, const char *msg)
2463 {
2464         struct bge_dmamap_arg ctx;
2465         int error;
2466
2467         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2468             alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2469             NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
2470         if (error != 0) {
2471                 device_printf(sc->bge_dev,
2472                     "could not create %s dma tag\n", msg);
2473                 return (ENOMEM);
2474         }
2475         /* Allocate DMA'able memory for ring. */
2476         error = bus_dmamem_alloc(*tag, (void **)ring,
2477             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
2478         if (error != 0) {
2479                 device_printf(sc->bge_dev,
2480                     "could not allocate DMA'able memory for %s\n", msg);
2481                 return (ENOMEM);
2482         }
2483         /* Load the address of the ring. */
2484         ctx.bge_busaddr = 0;
2485         error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr,
2486             &ctx, BUS_DMA_NOWAIT);
2487         if (error != 0) {
2488                 device_printf(sc->bge_dev,
2489                     "could not load DMA'able memory for %s\n", msg);
2490                 return (ENOMEM);
2491         }
2492         *paddr = ctx.bge_busaddr;
2493         return (0);
2494 }
2495
2496 static int
2497 bge_dma_alloc(struct bge_softc *sc)
2498 {
2499         bus_addr_t lowaddr;
2500         bus_size_t rxmaxsegsz, sbsz, txsegsz, txmaxsegsz;
2501         int i, error;
2502
2503         lowaddr = BUS_SPACE_MAXADDR;
2504         if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2505                 lowaddr = BGE_DMA_MAXADDR;
2506         /*
2507          * Allocate the parent bus DMA tag appropriate for PCI.
2508          */
2509         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2510             1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2511             NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2512             0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2513         if (error != 0) {
2514                 device_printf(sc->bge_dev,
2515                     "could not allocate parent dma tag\n");
2516                 return (ENOMEM);
2517         }
2518
2519         /* Create tag for standard RX ring. */
2520         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
2521             &sc->bge_cdata.bge_rx_std_ring_tag,
2522             (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
2523             &sc->bge_cdata.bge_rx_std_ring_map,
2524             &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
2525         if (error)
2526                 return (error);
2527
2528         /* Create tag for RX return ring. */
2529         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
2530             &sc->bge_cdata.bge_rx_return_ring_tag,
2531             (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
2532             &sc->bge_cdata.bge_rx_return_ring_map,
2533             &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
2534         if (error)
2535                 return (error);
2536
2537         /* Create tag for TX ring. */
2538         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
2539             &sc->bge_cdata.bge_tx_ring_tag,
2540             (uint8_t **)&sc->bge_ldata.bge_tx_ring,
2541             &sc->bge_cdata.bge_tx_ring_map,
2542             &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
2543         if (error)
2544                 return (error);
2545
2546         /*
2547          * Create tag for status block.
2548          * Because we only use single Tx/Rx/Rx return ring, use
2549          * minimum status block size except BCM5700 AX/BX which
2550          * seems to want to see full status block size regardless
2551          * of configured number of ring.
2552          */
2553         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2554             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
2555                 sbsz = BGE_STATUS_BLK_SZ;
2556         else
2557                 sbsz = 32;
2558         error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
2559             &sc->bge_cdata.bge_status_tag,
2560             (uint8_t **)&sc->bge_ldata.bge_status_block,
2561             &sc->bge_cdata.bge_status_map,
2562             &sc->bge_ldata.bge_status_block_paddr, "status block");
2563         if (error)
2564                 return (error);
2565
2566         /* Create tag for statistics block. */
2567         error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
2568             &sc->bge_cdata.bge_stats_tag,
2569             (uint8_t **)&sc->bge_ldata.bge_stats,
2570             &sc->bge_cdata.bge_stats_map,
2571             &sc->bge_ldata.bge_stats_paddr, "statistics block");
2572         if (error)
2573                 return (error);
2574
2575         /* Create tag for jumbo RX ring. */
2576         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2577                 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
2578                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
2579                     (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
2580                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
2581                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
2582                 if (error)
2583                         return (error);
2584         }
2585
2586         /* Create parent tag for buffers. */
2587         if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
2588                 /*
2589                  * XXX
2590                  * watchdog timeout issue was observed on BCM5704 which
2591                  * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge).
2592                  * Both limiting DMA address space to 32bits and flushing
2593                  * mailbox write seem to address the issue.
2594                  */
2595                 if (sc->bge_pcixcap != 0)
2596                         lowaddr = BUS_SPACE_MAXADDR_32BIT;
2597         }
2598         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 1, 0, lowaddr,
2599             BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0,
2600             BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
2601             &sc->bge_cdata.bge_buffer_tag);
2602         if (error != 0) {
2603                 device_printf(sc->bge_dev,
2604                     "could not allocate buffer dma tag\n");
2605                 return (ENOMEM);
2606         }
2607         /* Create tag for Tx mbufs. */
2608         if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2609                 txsegsz = BGE_TSOSEG_SZ;
2610                 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
2611         } else {
2612                 txsegsz = MCLBYTES;
2613                 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
2614         }
2615         error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
2616             0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2617             txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
2618             &sc->bge_cdata.bge_tx_mtag);
2619
2620         if (error) {
2621                 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
2622                 return (ENOMEM);
2623         }
2624
2625         /* Create tag for Rx mbufs. */
2626         if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
2627                 rxmaxsegsz = MJUM9BYTES;
2628         else
2629                 rxmaxsegsz = MCLBYTES;
2630         error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
2631             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1,
2632             rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
2633
2634         if (error) {
2635                 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
2636                 return (ENOMEM);
2637         }
2638
2639         /* Create DMA maps for RX buffers. */
2640         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2641             &sc->bge_cdata.bge_rx_std_sparemap);
2642         if (error) {
2643                 device_printf(sc->bge_dev,
2644                     "can't create spare DMA map for RX\n");
2645                 return (ENOMEM);
2646         }
2647         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2648                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2649                             &sc->bge_cdata.bge_rx_std_dmamap[i]);
2650                 if (error) {
2651                         device_printf(sc->bge_dev,
2652                             "can't create DMA map for RX\n");
2653                         return (ENOMEM);
2654                 }
2655         }
2656
2657         /* Create DMA maps for TX buffers. */
2658         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2659                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
2660                             &sc->bge_cdata.bge_tx_dmamap[i]);
2661                 if (error) {
2662                         device_printf(sc->bge_dev,
2663                             "can't create DMA map for TX\n");
2664                         return (ENOMEM);
2665                 }
2666         }
2667
2668         /* Create tags for jumbo RX buffers. */
2669         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2670                 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
2671                     1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2672                     NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
2673                     0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
2674                 if (error) {
2675                         device_printf(sc->bge_dev,
2676                             "could not allocate jumbo dma tag\n");
2677                         return (ENOMEM);
2678                 }
2679                 /* Create DMA maps for jumbo RX buffers. */
2680                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2681                     0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
2682                 if (error) {
2683                         device_printf(sc->bge_dev,
2684                             "can't create spare DMA map for jumbo RX\n");
2685                         return (ENOMEM);
2686                 }
2687                 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2688                         error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2689                                     0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2690                         if (error) {
2691                                 device_printf(sc->bge_dev,
2692                                     "can't create DMA map for jumbo RX\n");
2693                                 return (ENOMEM);
2694                         }
2695                 }
2696         }
2697
2698         return (0);
2699 }
2700
2701 /*
2702  * Return true if this device has more than one port.
2703  */
2704 static int
2705 bge_has_multiple_ports(struct bge_softc *sc)
2706 {
2707         device_t dev = sc->bge_dev;
2708         u_int b, d, f, fscan, s;
2709
2710         d = pci_get_domain(dev);
2711         b = pci_get_bus(dev);
2712         s = pci_get_slot(dev);
2713         f = pci_get_function(dev);
2714         for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
2715                 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
2716                         return (1);
2717         return (0);
2718 }
2719
2720 /*
2721  * Return true if MSI can be used with this device.
2722  */
2723 static int
2724 bge_can_use_msi(struct bge_softc *sc)
2725 {
2726         int can_use_msi = 0;
2727
2728         if (sc->bge_msi == 0)
2729                 return (0);
2730
2731         /* Disable MSI for polling(4). */
2732 #ifdef DEVICE_POLLING
2733         return (0);
2734 #endif
2735         switch (sc->bge_asicrev) {
2736         case BGE_ASICREV_BCM5714_A0:
2737         case BGE_ASICREV_BCM5714:
2738                 /*
2739                  * Apparently, MSI doesn't work when these chips are
2740                  * configured in single-port mode.
2741                  */
2742                 if (bge_has_multiple_ports(sc))
2743                         can_use_msi = 1;
2744                 break;
2745         case BGE_ASICREV_BCM5750:
2746                 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
2747                     sc->bge_chiprev != BGE_CHIPREV_5750_BX)
2748                         can_use_msi = 1;
2749                 break;
2750         default:
2751                 if (BGE_IS_575X_PLUS(sc))
2752                         can_use_msi = 1;
2753         }
2754         return (can_use_msi);
2755 }
2756
2757 static int
2758 bge_mbox_reorder(struct bge_softc *sc)
2759 {
2760         /* Lists of PCI bridges that are known to reorder mailbox writes. */
2761         static const struct mbox_reorder {
2762                 const uint16_t vendor;
2763                 const uint16_t device;
2764                 const char *desc;
2765         } const mbox_reorder_lists[] = {
2766                 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" },
2767         };
2768         devclass_t pci, pcib;
2769         device_t bus, dev;
2770         int count, i;
2771
2772         count = sizeof(mbox_reorder_lists) / sizeof(mbox_reorder_lists[0]);
2773         pci = devclass_find("pci");
2774         pcib = devclass_find("pcib");
2775         dev = sc->bge_dev;
2776         bus = device_get_parent(dev);
2777         for (;;) {
2778                 dev = device_get_parent(bus);
2779                 bus = device_get_parent(dev);
2780                 device_printf(sc->bge_dev, "dev : %s%d, bus : %s%d\n",
2781                     device_get_name(dev), device_get_unit(dev),
2782                     device_get_name(bus), device_get_unit(bus));
2783                 if (device_get_devclass(dev) != pcib)
2784                         break;
2785                 for (i = 0; i < count; i++) {
2786                         device_printf(sc->bge_dev,
2787                             "probing dev : %s%d, vendor : 0x%04x "
2788                             "device : 0x%04x\n",
2789                             device_get_name(dev), device_get_unit(dev),
2790                             pci_get_vendor(dev), pci_get_device(dev));
2791                         if (pci_get_vendor(dev) ==
2792                             mbox_reorder_lists[i].vendor &&
2793                             pci_get_device(dev) ==
2794                             mbox_reorder_lists[i].device) {
2795                                 device_printf(sc->bge_dev,
2796                                     "enabling MBOX workaround for %s\n",
2797                                     mbox_reorder_lists[i].desc);
2798                                 return (1);
2799                         }
2800                 }
2801                 if (device_get_devclass(bus) != pci)
2802                         break;
2803         }
2804         return (0);
2805 }
2806
2807 static void
2808 bge_devinfo(struct bge_softc *sc)
2809 {
2810         uint32_t cfg, clk;
2811
2812         device_printf(sc->bge_dev,
2813             "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ",
2814             sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev);
2815         if (sc->bge_flags & BGE_FLAG_PCIE)
2816                 printf("PCI-E\n");
2817         else if (sc->bge_flags & BGE_FLAG_PCIX) {
2818                 printf("PCI-X ");
2819                 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
2820                 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE)
2821                         clk = 133;
2822                 else {
2823                         clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
2824                         switch (clk) {
2825                         case 0:
2826                                 clk = 33;
2827                                 break;
2828                         case 2:
2829                                 clk = 50;
2830                                 break;
2831                         case 4:
2832                                 clk = 66;
2833                                 break;
2834                         case 6:
2835                                 clk = 100;
2836                                 break;
2837                         case 7:
2838                                 clk = 133;
2839                                 break;
2840                         }
2841                 }
2842                 printf("%u MHz\n", clk);
2843         } else {
2844                 if (sc->bge_pcixcap != 0)
2845                         printf("PCI on PCI-X ");
2846                 else
2847                         printf("PCI ");
2848                 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
2849                 if (cfg & BGE_PCISTATE_PCI_BUSSPEED)
2850                         clk = 66;
2851                 else
2852                         clk = 33;
2853                 if (cfg & BGE_PCISTATE_32BIT_BUS)
2854                         printf("%u MHz; 32bit\n", clk);
2855                 else
2856                         printf("%u MHz; 64bit\n", clk);
2857         }
2858 }
2859
2860 static int
2861 bge_attach(device_t dev)
2862 {
2863         struct ifnet *ifp;
2864         struct bge_softc *sc;
2865         uint32_t hwcfg = 0, misccfg;
2866         u_char eaddr[ETHER_ADDR_LEN];
2867         int capmask, error, f, msicount, phy_addr, reg, rid, trys;
2868
2869         sc = device_get_softc(dev);
2870         sc->bge_dev = dev;
2871
2872         bge_add_sysctls(sc);
2873
2874         TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
2875
2876         /*
2877          * Map control/status registers.
2878          */
2879         pci_enable_busmaster(dev);
2880
2881         rid = PCIR_BAR(0);
2882         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2883             RF_ACTIVE);
2884
2885         if (sc->bge_res == NULL) {
2886                 device_printf (sc->bge_dev, "couldn't map memory\n");
2887                 error = ENXIO;
2888                 goto fail;
2889         }
2890
2891         /* Save various chip information. */
2892         sc->bge_chipid =
2893             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2894             BGE_PCIMISCCTL_ASICREV_SHIFT;
2895         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) {
2896                 /*
2897                  * Find the ASCI revision.  Different chips use different
2898                  * registers.
2899                  */
2900                 switch (pci_get_device(dev)) {
2901                 case BCOM_DEVICEID_BCM5717:
2902                 case BCOM_DEVICEID_BCM5718:
2903                 case BCOM_DEVICEID_BCM5719:
2904                 case BCOM_DEVICEID_BCM5720:
2905                         sc->bge_chipid = pci_read_config(dev,
2906                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
2907                         break;
2908                 case BCOM_DEVICEID_BCM57761:
2909                 case BCOM_DEVICEID_BCM57765:
2910                 case BCOM_DEVICEID_BCM57781:
2911                 case BCOM_DEVICEID_BCM57785:
2912                 case BCOM_DEVICEID_BCM57791:
2913                 case BCOM_DEVICEID_BCM57795:
2914                         sc->bge_chipid = pci_read_config(dev,
2915                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
2916                         break;
2917                 default:
2918                         sc->bge_chipid = pci_read_config(dev,
2919                             BGE_PCI_PRODID_ASICREV, 4);
2920                 }
2921         }
2922         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2923         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2924
2925         /* Set default PHY address. */
2926         phy_addr = 1;
2927          /*
2928           * PHY address mapping for various devices.
2929           *
2930           *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
2931           * ---------+-------+-------+-------+-------+
2932           * BCM57XX  |   1   |   X   |   X   |   X   |
2933           * BCM5704  |   1   |   X   |   1   |   X   |
2934           * BCM5717  |   1   |   8   |   2   |   9   |
2935           * BCM5719  |   1   |   8   |   2   |   9   |
2936           * BCM5720  |   1   |   8   |   2   |   9   |
2937           *
2938           * Other addresses may respond but they are not
2939           * IEEE compliant PHYs and should be ignored.
2940           */
2941         if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2942             sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2943             sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2944                 f = pci_get_function(dev);
2945                 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) {
2946                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
2947                             BGE_SGDIGSTS_IS_SERDES)
2948                                 phy_addr = f + 8;
2949                         else
2950                                 phy_addr = f + 1;
2951                 } else {
2952                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
2953                             BGE_CPMU_PHY_STRAP_IS_SERDES)
2954                                 phy_addr = f + 8;
2955                         else
2956                                 phy_addr = f + 1;
2957                 }
2958         }
2959
2960         /*
2961          * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the
2962          * 5705 A0 and A1 chips.
2963          */
2964         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2965             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2966             (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2967             sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
2968             sc->bge_asicrev == BGE_ASICREV_BCM5906)
2969                 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
2970
2971         if (bge_has_eaddr(sc))
2972                 sc->bge_flags |= BGE_FLAG_EADDR;
2973
2974         /* Save chipset family. */
2975         switch (sc->bge_asicrev) {
2976         case BGE_ASICREV_BCM5717:
2977         case BGE_ASICREV_BCM5719:
2978         case BGE_ASICREV_BCM5720:
2979         case BGE_ASICREV_BCM57765:
2980                 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
2981                     BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
2982                     BGE_FLAG_JUMBO_FRAME;
2983                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
2984                     sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
2985                         /* Jumbo frame on BCM5719 A0 does not work. */
2986                         sc->bge_flags &= ~BGE_FLAG_JUMBO;
2987                 }
2988                 break;
2989         case BGE_ASICREV_BCM5755:
2990         case BGE_ASICREV_BCM5761:
2991         case BGE_ASICREV_BCM5784:
2992         case BGE_ASICREV_BCM5785:
2993         case BGE_ASICREV_BCM5787:
2994         case BGE_ASICREV_BCM57780:
2995                 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2996                     BGE_FLAG_5705_PLUS;
2997                 break;
2998         case BGE_ASICREV_BCM5700:
2999         case BGE_ASICREV_BCM5701:
3000         case BGE_ASICREV_BCM5703:
3001         case BGE_ASICREV_BCM5704:
3002                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
3003                 break;
3004         case BGE_ASICREV_BCM5714_A0:
3005         case BGE_ASICREV_BCM5780:
3006         case BGE_ASICREV_BCM5714:
3007                 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
3008                 /* FALLTHROUGH */
3009         case BGE_ASICREV_BCM5750:
3010         case BGE_ASICREV_BCM5752:
3011         case BGE_ASICREV_BCM5906:
3012                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
3013                 /* FALLTHROUGH */
3014         case BGE_ASICREV_BCM5705:
3015                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
3016                 break;
3017         }
3018
3019         /* Set various PHY bug flags. */
3020         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
3021             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
3022                 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
3023         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
3024             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
3025                 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
3026         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
3027                 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
3028         if (pci_get_subvendor(dev) == DELL_VENDORID)
3029                 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
3030         if ((BGE_IS_5705_PLUS(sc)) &&
3031             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
3032             sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
3033             sc->bge_asicrev != BGE_ASICREV_BCM5719 &&
3034             sc->bge_asicrev != BGE_ASICREV_BCM5720 &&
3035             sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
3036             sc->bge_asicrev != BGE_ASICREV_BCM57765 &&
3037             sc->bge_asicrev != BGE_ASICREV_BCM57780) {
3038                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
3039                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3040                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3041                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
3042                         if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
3043                             pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
3044                                 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
3045                         if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
3046                                 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
3047                 } else
3048                         sc->bge_phy_flags |= BGE_PHY_BER_BUG;
3049         }
3050
3051         /* Identify the chips that use an CPMU. */
3052         if (BGE_IS_5717_PLUS(sc) ||
3053             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3054             sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3055             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
3056             sc->bge_asicrev == BGE_ASICREV_BCM57780)
3057                 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
3058         if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
3059                 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
3060         else
3061                 sc->bge_mi_mode = BGE_MIMODE_BASE;
3062         /* Enable auto polling for BCM570[0-5]. */
3063         if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
3064                 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
3065
3066         /*
3067          * All Broadcom controllers have 4GB boundary DMA bug.
3068          * Whenever an address crosses a multiple of the 4GB boundary
3069          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3070          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3071          * state machine will lockup and cause the device to hang.
3072          */
3073         sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
3074
3075         /* BCM5755 or higher and BCM5906 have short DMA bug. */
3076         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3077                 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
3078
3079         /*
3080          * BCM5719 cannot handle DMA requests for DMA segments that
3081          * have larger than 4KB in size.  However the maximum DMA
3082          * segment size created in DMA tag is 4KB for TSO, so we
3083          * wouldn't encounter the issue here.
3084          */
3085         if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
3086                 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG;
3087
3088         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3089         if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
3090                 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
3091                     misccfg == BGE_MISCCFG_BOARD_ID_5788M)
3092                         sc->bge_flags |= BGE_FLAG_5788;
3093         }
3094
3095         capmask = BMSR_DEFCAPMASK;
3096         if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
3097             (misccfg == 0x4000 || misccfg == 0x8000)) ||
3098             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3099             pci_get_vendor(dev) == BCOM_VENDORID &&
3100             (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 ||
3101             pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 ||
3102             pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) ||
3103             (pci_get_vendor(dev) == BCOM_VENDORID &&
3104             (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F ||
3105             pci_get_device(dev) == BCOM_DEVICEID_BCM5753F ||
3106             pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) ||
3107             pci_get_device(dev) == BCOM_DEVICEID_BCM57790 ||
3108             sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3109                 /* These chips are 10/100 only. */
3110                 capmask &= ~BMSR_EXTSTAT;
3111         }
3112
3113         /*
3114          * Some controllers seem to require a special firmware to use
3115          * TSO. But the firmware is not available to FreeBSD and Linux
3116          * claims that the TSO performed by the firmware is slower than
3117          * hardware based TSO. Moreover the firmware based TSO has one
3118          * known bug which can't handle TSO if ethernet header + IP/TCP
3119          * header is greater than 80 bytes. The workaround for the TSO
3120          * bug exist but it seems it's too expensive than not using
3121          * TSO at all. Some hardwares also have the TSO bug so limit
3122          * the TSO to the controllers that are not affected TSO issues
3123          * (e.g. 5755 or higher).
3124          */
3125         if (BGE_IS_5717_PLUS(sc)) {
3126                 /* BCM5717 requires different TSO configuration. */
3127                 sc->bge_flags |= BGE_FLAG_TSO3;
3128                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3129                     sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3130                         /* TSO on BCM5719 A0 does not work. */
3131                         sc->bge_flags &= ~BGE_FLAG_TSO3;
3132                 }
3133         } else if (BGE_IS_5755_PLUS(sc)) {
3134                 /*
3135                  * BCM5754 and BCM5787 shares the same ASIC id so
3136                  * explicit device id check is required.
3137                  * Due to unknown reason TSO does not work on BCM5755M.
3138                  */
3139                 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
3140                     pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
3141                     pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
3142                         sc->bge_flags |= BGE_FLAG_TSO;
3143         }
3144
3145         /*
3146          * Check if this is a PCI-X or PCI Express device.
3147          */
3148         if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
3149                 /*
3150                  * Found a PCI Express capabilities register, this
3151                  * must be a PCI Express device.
3152                  */
3153                 sc->bge_flags |= BGE_FLAG_PCIE;
3154                 sc->bge_expcap = reg;
3155                 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3156                     sc->bge_asicrev == BGE_ASICREV_BCM5720)
3157                         pci_set_max_read_req(dev, 2048);
3158                 else if (pci_get_max_read_req(dev) != 4096)
3159                         pci_set_max_read_req(dev, 4096);
3160         } else {
3161                 /*
3162                  * Check if the device is in PCI-X Mode.
3163                  * (This bit is not valid on PCI Express controllers.)
3164                  */
3165                 if (pci_find_cap(dev, PCIY_PCIX, &reg) == 0)
3166                         sc->bge_pcixcap = reg;
3167                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
3168                     BGE_PCISTATE_PCI_BUSMODE) == 0)
3169                         sc->bge_flags |= BGE_FLAG_PCIX;
3170         }
3171
3172         /*
3173          * The 40bit DMA bug applies to the 5714/5715 controllers and is
3174          * not actually a MAC controller bug but an issue with the embedded
3175          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
3176          */
3177         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
3178                 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
3179         /*
3180          * Some PCI-X bridges are known to trigger write reordering to
3181          * the mailbox registers. Typical phenomena is watchdog timeouts
3182          * caused by out-of-order TX completions.  Enable workaround for
3183          * PCI-X devices that live behind these bridges.
3184          * Note, PCI-X controllers can run in PCI mode so we can't use
3185          * BGE_FLAG_PCIX flag to detect PCI-X controllers.
3186          */
3187         if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0)
3188                 sc->bge_flags |= BGE_FLAG_MBOX_REORDER;
3189         /*
3190          * Allocate the interrupt, using MSI if possible.  These devices
3191          * support 8 MSI messages, but only the first one is used in
3192          * normal operation.
3193          */
3194         rid = 0;
3195         if (pci_find_cap(sc->bge_dev, PCIY_MSI, &reg) == 0) {
3196                 sc->bge_msicap = reg;
3197                 if (bge_can_use_msi(sc)) {
3198                         msicount = pci_msi_count(dev);
3199                         if (msicount > 1)
3200                                 msicount = 1;
3201                 } else
3202                         msicount = 0;
3203                 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
3204                         rid = 1;
3205                         sc->bge_flags |= BGE_FLAG_MSI;
3206                 }
3207         }
3208
3209         /*
3210          * All controllers except BCM5700 supports tagged status but
3211          * we use tagged status only for MSI case on BCM5717. Otherwise
3212          * MSI on BCM5717 does not work.
3213          */
3214 #ifndef DEVICE_POLLING
3215         if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
3216                 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
3217 #endif
3218
3219         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3220             RF_SHAREABLE | RF_ACTIVE);
3221
3222         if (sc->bge_irq == NULL) {
3223                 device_printf(sc->bge_dev, "couldn't map interrupt\n");
3224                 error = ENXIO;
3225                 goto fail;
3226         }
3227
3228         bge_devinfo(sc);
3229
3230         BGE_LOCK_INIT(sc, device_get_nameunit(dev));
3231
3232         /* Try to reset the chip. */
3233         if (bge_reset(sc)) {
3234                 device_printf(sc->bge_dev, "chip reset failed\n");
3235                 error = ENXIO;
3236                 goto fail;
3237         }
3238
3239         sc->bge_asf_mode = 0;
3240         if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3241             BGE_SRAM_DATA_SIG_MAGIC)) {
3242                 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG)
3243                     & BGE_HWCFG_ASF) {
3244                         sc->bge_asf_mode |= ASF_ENABLE;
3245                         sc->bge_asf_mode |= ASF_STACKUP;
3246                         if (BGE_IS_575X_PLUS(sc))
3247                                 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3248                 }
3249         }
3250
3251         /* Try to reset the chip again the nice way. */
3252         bge_stop_fw(sc);
3253         bge_sig_pre_reset(sc, BGE_RESET_STOP);
3254         if (bge_reset(sc)) {
3255                 device_printf(sc->bge_dev, "chip reset failed\n");
3256                 error = ENXIO;
3257                 goto fail;
3258         }
3259
3260         bge_sig_legacy(sc, BGE_RESET_STOP);
3261         bge_sig_post_reset(sc, BGE_RESET_STOP);
3262
3263         if (bge_chipinit(sc)) {
3264                 device_printf(sc->bge_dev, "chip initialization failed\n");
3265                 error = ENXIO;
3266                 goto fail;
3267         }
3268
3269         error = bge_get_eaddr(sc, eaddr);
3270         if (error) {
3271                 device_printf(sc->bge_dev,
3272                     "failed to read station address\n");
3273                 error = ENXIO;
3274                 goto fail;
3275         }
3276
3277         /* 5705 limits RX return ring to 512 entries. */
3278         if (BGE_IS_5717_PLUS(sc))
3279                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3280         else if (BGE_IS_5705_PLUS(sc))
3281                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3282         else
3283                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3284
3285         if (bge_dma_alloc(sc)) {
3286                 device_printf(sc->bge_dev,
3287                     "failed to allocate DMA resources\n");
3288                 error = ENXIO;
3289                 goto fail;
3290         }
3291
3292         /* Set default tuneable values. */
3293         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3294         sc->bge_rx_coal_ticks = 150;
3295         sc->bge_tx_coal_ticks = 150;
3296         sc->bge_rx_max_coal_bds = 10;
3297         sc->bge_tx_max_coal_bds = 10;
3298
3299         /* Initialize checksum features to use. */
3300         sc->bge_csum_features = BGE_CSUM_FEATURES;
3301         if (sc->bge_forced_udpcsum != 0)
3302                 sc->bge_csum_features |= CSUM_UDP;
3303
3304         /* Set up ifnet structure */
3305         ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
3306         if (ifp == NULL) {
3307                 device_printf(sc->bge_dev, "failed to if_alloc()\n");
3308                 error = ENXIO;
3309                 goto fail;
3310         }
3311         ifp->if_softc = sc;
3312         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3313         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3314         ifp->if_ioctl = bge_ioctl;
3315         ifp->if_start = bge_start;
3316         ifp->if_init = bge_init;
3317         ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
3318         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
3319         IFQ_SET_READY(&ifp->if_snd);
3320         ifp->if_hwassist = sc->bge_csum_features;
3321         ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3322             IFCAP_VLAN_MTU;
3323         if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3324                 ifp->if_hwassist |= CSUM_TSO;
3325                 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO;
3326         }
3327 #ifdef IFCAP_VLAN_HWCSUM
3328         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
3329 #endif
3330         ifp->if_capenable = ifp->if_capabilities;
3331 #ifdef DEVICE_POLLING
3332         ifp->if_capabilities |= IFCAP_POLLING;
3333 #endif
3334
3335         /*
3336          * 5700 B0 chips do not support checksumming correctly due
3337          * to hardware bugs.
3338          */
3339         if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
3340                 ifp->if_capabilities &= ~IFCAP_HWCSUM;
3341                 ifp->if_capenable &= ~IFCAP_HWCSUM;
3342                 ifp->if_hwassist = 0;
3343         }
3344
3345         /*
3346          * Figure out what sort of media we have by checking the
3347          * hardware config word in the first 32k of NIC internal memory,
3348          * or fall back to examining the EEPROM if necessary.
3349          * Note: on some BCM5700 cards, this value appears to be unset.
3350          * If that's the case, we have to rely on identifying the NIC
3351          * by its PCI subsystem ID, as we do below for the SysKonnect
3352          * SK-9D41.
3353          */
3354         if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
3355                 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3356         else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
3357             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3358                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
3359                     sizeof(hwcfg))) {
3360                         device_printf(sc->bge_dev, "failed to read EEPROM\n");
3361                         error = ENXIO;
3362                         goto fail;
3363                 }
3364                 hwcfg = ntohl(hwcfg);
3365         }
3366
3367         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
3368         if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
3369             SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
3370                 if (BGE_IS_5714_FAMILY(sc))
3371                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
3372                 else
3373                         sc->bge_flags |= BGE_FLAG_TBI;
3374         }
3375
3376         if (sc->bge_flags & BGE_FLAG_TBI) {
3377                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3378                     bge_ifmedia_sts);
3379                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
3380                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
3381                     0, NULL);
3382                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3383                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3384                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3385         } else {
3386                 /*
3387                  * Do transceiver setup and tell the firmware the
3388                  * driver is down so we can try to get access the
3389                  * probe if ASF is running.  Retry a couple of times
3390                  * if we get a conflict with the ASF firmware accessing
3391                  * the PHY.
3392                  */
3393                 trys = 0;
3394                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3395 again:
3396                 bge_asf_driver_up(sc);
3397
3398                 error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd,
3399                     bge_ifmedia_sts, capmask, phy_addr, MII_OFFSET_ANY,
3400                     MIIF_DOPAUSE);
3401                 if (error != 0) {
3402                         if (trys++ < 4) {
3403                                 device_printf(sc->bge_dev, "Try again\n");
3404                                 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR,
3405                                     BMCR_RESET);
3406                                 goto again;
3407                         }
3408                         device_printf(sc->bge_dev, "attaching PHYs failed\n");
3409                         goto fail;
3410                 }
3411
3412                 /*
3413                  * Now tell the firmware we are going up after probing the PHY
3414                  */
3415                 if (sc->bge_asf_mode & ASF_STACKUP)
3416                         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3417         }
3418
3419         /*
3420          * When using the BCM5701 in PCI-X mode, data corruption has
3421          * been observed in the first few bytes of some received packets.
3422          * Aligning the packet buffer in memory eliminates the corruption.
3423          * Unfortunately, this misaligns the packet payloads.  On platforms
3424          * which do not support unaligned accesses, we will realign the
3425          * payloads by copying the received packets.
3426          */
3427         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
3428             sc->bge_flags & BGE_FLAG_PCIX)
3429                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
3430
3431         /*
3432          * Call MI attach routine.
3433          */
3434         ether_ifattach(ifp, eaddr);
3435         callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
3436
3437         /* Tell upper layer we support long frames. */
3438         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
3439
3440         /*
3441          * Hookup IRQ last.
3442          */
3443         if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
3444                 /* Take advantage of single-shot MSI. */
3445                 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
3446                     ~BGE_MSIMODE_ONE_SHOT_DISABLE);
3447                 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
3448                     taskqueue_thread_enqueue, &sc->bge_tq);
3449                 if (sc->bge_tq == NULL) {
3450                         device_printf(dev, "could not create taskqueue.\n");
3451                         ether_ifdetach(ifp);
3452                         error = ENXIO;
3453                         goto fail;
3454                 }
3455                 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq",
3456                     device_get_nameunit(sc->bge_dev));
3457                 error = bus_setup_intr(dev, sc->bge_irq,
3458                     INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
3459                     &sc->bge_intrhand);
3460                 if (error)
3461                         ether_ifdetach(ifp);
3462         } else
3463                 error = bus_setup_intr(dev, sc->bge_irq,
3464                     INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
3465                     &sc->bge_intrhand);
3466
3467         if (error) {
3468                 bge_detach(dev);
3469                 device_printf(sc->bge_dev, "couldn't set up irq\n");
3470         }
3471
3472         return (0);
3473
3474 fail:
3475         bge_release_resources(sc);
3476
3477         return (error);
3478 }
3479
3480 static int
3481 bge_detach(device_t dev)
3482 {
3483         struct bge_softc *sc;
3484         struct ifnet *ifp;
3485
3486         sc = device_get_softc(dev);
3487         ifp = sc->bge_ifp;
3488
3489 #ifdef DEVICE_POLLING
3490         if (ifp->if_capenable & IFCAP_POLLING)
3491                 ether_poll_deregister(ifp);
3492 #endif
3493
3494         BGE_LOCK(sc);
3495         bge_stop(sc);
3496         bge_reset(sc);
3497         BGE_UNLOCK(sc);
3498
3499         callout_drain(&sc->bge_stat_ch);
3500
3501         if (sc->bge_tq)
3502                 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3503         ether_ifdetach(ifp);
3504
3505         if (sc->bge_flags & BGE_FLAG_TBI) {
3506                 ifmedia_removeall(&sc->bge_ifmedia);
3507         } else {
3508                 bus_generic_detach(dev);
3509                 device_delete_child(dev, sc->bge_miibus);
3510         }
3511
3512         bge_release_resources(sc);
3513
3514         return (0);
3515 }
3516
3517 static void
3518 bge_release_resources(struct bge_softc *sc)
3519 {
3520         device_t dev;
3521
3522         dev = sc->bge_dev;
3523
3524         if (sc->bge_tq != NULL)
3525                 taskqueue_free(sc->bge_tq);
3526
3527         if (sc->bge_intrhand != NULL)
3528                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3529
3530         if (sc->bge_irq != NULL)
3531                 bus_release_resource(dev, SYS_RES_IRQ,
3532                     sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
3533
3534         if (sc->bge_flags & BGE_FLAG_MSI)
3535                 pci_release_msi(dev);
3536
3537         if (sc->bge_res != NULL)
3538                 bus_release_resource(dev, SYS_RES_MEMORY,
3539                     PCIR_BAR(0), sc->bge_res);
3540
3541         if (sc->bge_ifp != NULL)
3542                 if_free(sc->bge_ifp);
3543
3544         bge_dma_free(sc);
3545
3546         if (mtx_initialized(&sc->bge_mtx))      /* XXX */
3547                 BGE_LOCK_DESTROY(sc);
3548 }
3549
3550 static int
3551 bge_reset(struct bge_softc *sc)
3552 {
3553         device_t dev;
3554         uint32_t cachesize, command, pcistate, reset, val;
3555         void (*write_op)(struct bge_softc *, int, int);
3556         uint16_t devctl;
3557         int i;
3558
3559         dev = sc->bge_dev;
3560
3561         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
3562             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3563                 if (sc->bge_flags & BGE_FLAG_PCIE)
3564                         write_op = bge_writemem_direct;
3565                 else
3566                         write_op = bge_writemem_ind;
3567         } else
3568                 write_op = bge_writereg_ind;
3569
3570         /* Save some important PCI state. */
3571         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
3572         command = pci_read_config(dev, BGE_PCI_CMD, 4);
3573         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3574
3575         pci_write_config(dev, BGE_PCI_MISC_CTL,
3576             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3577             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3578
3579         /* Disable fastboot on controllers that support it. */
3580         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
3581             BGE_IS_5755_PLUS(sc)) {
3582                 if (bootverbose)
3583                         device_printf(dev, "Disabling fastboot\n");
3584                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
3585         }
3586
3587         /*
3588          * Write the magic number to SRAM at offset 0xB50.
3589          * When firmware finishes its initialization it will
3590          * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
3591          */
3592         bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
3593
3594         reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
3595
3596         /* XXX: Broadcom Linux driver. */
3597         if (sc->bge_flags & BGE_FLAG_PCIE) {
3598                 if (CSR_READ_4(sc, 0x7E2C) == 0x60)     /* PCIE 1.0 */
3599                         CSR_WRITE_4(sc, 0x7E2C, 0x20);
3600                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3601                         /* Prevent PCIE link training during global reset */
3602                         CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
3603                         reset |= 1 << 29;
3604                 }
3605         }
3606
3607         /*
3608          * Set GPHY Power Down Override to leave GPHY
3609          * powered up in D0 uninitialized.
3610          */
3611         if (BGE_IS_5705_PLUS(sc) &&
3612             (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0)
3613                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
3614
3615         /* Issue global reset */
3616         write_op(sc, BGE_MISC_CFG, reset);
3617
3618         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3619                 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3620                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
3621                     val | BGE_VCPU_STATUS_DRV_RESET);
3622                 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
3623                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
3624                     val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
3625         }
3626
3627         DELAY(1000);
3628
3629         /* XXX: Broadcom Linux driver. */
3630         if (sc->bge_flags & BGE_FLAG_PCIE) {
3631                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
3632                         DELAY(500000); /* wait for link training to complete */
3633                         val = pci_read_config(dev, 0xC4, 4);
3634                         pci_write_config(dev, 0xC4, val | (1 << 15), 4);
3635                 }
3636                 devctl = pci_read_config(dev,
3637                     sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
3638                 /* Clear enable no snoop and disable relaxed ordering. */
3639                 devctl &= ~(PCIM_EXP_CTL_RELAXED_ORD_ENABLE |
3640                     PCIM_EXP_CTL_NOSNOOP_ENABLE);
3641                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL,
3642                     devctl, 2);
3643                 /* Clear error status. */
3644                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA,
3645                     PCIM_EXP_STA_CORRECTABLE_ERROR |
3646                     PCIM_EXP_STA_NON_FATAL_ERROR | PCIM_EXP_STA_FATAL_ERROR |
3647                     PCIM_EXP_STA_UNSUPPORTED_REQ, 2);
3648         }
3649
3650         /* Reset some of the PCI state that got zapped by reset. */
3651         pci_write_config(dev, BGE_PCI_MISC_CTL,
3652             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3653             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3654         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
3655         pci_write_config(dev, BGE_PCI_CMD, command, 4);
3656         write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
3657         /*
3658          * Disable PCI-X relaxed ordering to ensure status block update
3659          * comes first then packet buffer DMA. Otherwise driver may
3660          * read stale status block.
3661          */
3662         if (sc->bge_flags & BGE_FLAG_PCIX) {
3663                 devctl = pci_read_config(dev,
3664                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
3665                 devctl &= ~PCIXM_COMMAND_ERO;
3666                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
3667                         devctl &= ~PCIXM_COMMAND_MAX_READ;
3668                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
3669                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3670                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
3671                             PCIXM_COMMAND_MAX_READ);
3672                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
3673                 }
3674                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
3675                     devctl, 2);
3676         }
3677         /* Re-enable MSI, if necessary, and enable the memory arbiter. */
3678         if (BGE_IS_5714_FAMILY(sc)) {
3679                 /* This chip disables MSI on reset. */
3680                 if (sc->bge_flags & BGE_FLAG_MSI) {
3681                         val = pci_read_config(dev,
3682                             sc->bge_msicap + PCIR_MSI_CTRL, 2);
3683                         pci_write_config(dev,
3684                             sc->bge_msicap + PCIR_MSI_CTRL,
3685                             val | PCIM_MSICTRL_MSI_ENABLE, 2);
3686                         val = CSR_READ_4(sc, BGE_MSI_MODE);
3687                         CSR_WRITE_4(sc, BGE_MSI_MODE,
3688                             val | BGE_MSIMODE_ENABLE);
3689                 }
3690                 val = CSR_READ_4(sc, BGE_MARB_MODE);
3691                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
3692         } else
3693                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3694
3695         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3696                 for (i = 0; i < BGE_TIMEOUT; i++) {
3697                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3698                         if (val & BGE_VCPU_STATUS_INIT_DONE)
3699                                 break;
3700                         DELAY(100);
3701                 }
3702                 if (i == BGE_TIMEOUT) {
3703                         device_printf(dev, "reset timed out\n");
3704                         return (1);
3705                 }
3706         } else {
3707                 /*
3708                  * Poll until we see the 1's complement of the magic number.
3709                  * This indicates that the firmware initialization is complete.
3710                  * We expect this to fail if no chip containing the Ethernet
3711                  * address is fitted though.
3712                  */
3713                 for (i = 0; i < BGE_TIMEOUT; i++) {
3714                         DELAY(10);
3715                         val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
3716                         if (val == ~BGE_SRAM_FW_MB_MAGIC)
3717                                 break;
3718                 }
3719
3720                 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
3721                         device_printf(dev,
3722                             "firmware handshake timed out, found 0x%08x\n",
3723                             val);
3724                 /* BCM57765 A0 needs additional time before accessing. */
3725                 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
3726                         DELAY(10 * 1000);       /* XXX */
3727         }
3728
3729         /*
3730          * XXX Wait for the value of the PCISTATE register to
3731          * return to its original pre-reset state. This is a
3732          * fairly good indicator of reset completion. If we don't
3733          * wait for the reset to fully complete, trying to read
3734          * from the device's non-PCI registers may yield garbage
3735          * results.
3736          */
3737         for (i = 0; i < BGE_TIMEOUT; i++) {
3738                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
3739                         break;
3740                 DELAY(10);
3741         }
3742
3743         /* Fix up byte swapping. */
3744         CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
3745
3746         /* Tell the ASF firmware we are up */
3747         if (sc->bge_asf_mode & ASF_STACKUP)
3748                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3749
3750         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
3751
3752         /*
3753          * The 5704 in TBI mode apparently needs some special
3754          * adjustment to insure the SERDES drive level is set
3755          * to 1.2V.
3756          */
3757         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
3758             sc->bge_flags & BGE_FLAG_TBI) {
3759                 val = CSR_READ_4(sc, BGE_SERDES_CFG);
3760                 val = (val & ~0xFFF) | 0x880;
3761                 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
3762         }
3763
3764         /* XXX: Broadcom Linux driver. */
3765         if (sc->bge_flags & BGE_FLAG_PCIE &&
3766             !BGE_IS_5717_PLUS(sc) &&
3767             sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
3768             sc->bge_asicrev != BGE_ASICREV_BCM5785) {
3769                 /* Enable Data FIFO protection. */
3770                 val = CSR_READ_4(sc, 0x7C00);
3771                 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
3772         }
3773         DELAY(10000);
3774
3775         if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
3776                 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
3777                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
3778
3779         return (0);
3780 }
3781
3782 static __inline void
3783 bge_rxreuse_std(struct bge_softc *sc, int i)
3784 {
3785         struct bge_rx_bd *r;
3786
3787         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
3788         r->bge_flags = BGE_RXBDFLAG_END;
3789         r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
3790         r->bge_idx = i;
3791         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3792 }
3793
3794 static __inline void
3795 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
3796 {
3797         struct bge_extrx_bd *r;
3798
3799         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
3800         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
3801         r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
3802         r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
3803         r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
3804         r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
3805         r->bge_idx = i;
3806         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3807 }
3808
3809 /*
3810  * Frame reception handling. This is called if there's a frame
3811  * on the receive return list.
3812  *
3813  * Note: we have to be able to handle two possibilities here:
3814  * 1) the frame is from the jumbo receive ring
3815  * 2) the frame is from the standard receive ring
3816  */
3817
3818 static int
3819 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
3820 {
3821         struct ifnet *ifp;
3822         int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
3823         uint16_t rx_cons;
3824
3825         rx_cons = sc->bge_rx_saved_considx;
3826
3827         /* Nothing to do. */
3828         if (rx_cons == rx_prod)
3829                 return (rx_npkts);
3830
3831         ifp = sc->bge_ifp;
3832
3833         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3834             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
3835         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3836             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
3837         if (BGE_IS_JUMBO_CAPABLE(sc) &&
3838             ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
3839             (MCLBYTES - ETHER_ALIGN))
3840                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3841                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
3842
3843         while (rx_cons != rx_prod) {
3844                 struct bge_rx_bd        *cur_rx;
3845                 uint32_t                rxidx;
3846                 struct mbuf             *m = NULL;
3847                 uint16_t                vlan_tag = 0;
3848                 int                     have_tag = 0;
3849
3850 #ifdef DEVICE_POLLING
3851                 if (ifp->if_capenable & IFCAP_POLLING) {
3852                         if (sc->rxcycles <= 0)
3853                                 break;
3854                         sc->rxcycles--;
3855                 }
3856 #endif
3857
3858                 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
3859
3860                 rxidx = cur_rx->bge_idx;
3861                 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
3862
3863                 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
3864                     cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
3865                         have_tag = 1;
3866                         vlan_tag = cur_rx->bge_vlan_tag;
3867                 }
3868
3869                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
3870                         jumbocnt++;
3871                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
3872                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3873                                 bge_rxreuse_jumbo(sc, rxidx);
3874                                 continue;
3875                         }
3876                         if (bge_newbuf_jumbo(sc, rxidx) != 0) {
3877                                 bge_rxreuse_jumbo(sc, rxidx);
3878                                 ifp->if_iqdrops++;
3879                                 continue;
3880                         }
3881                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3882                 } else {
3883                         stdcnt++;
3884                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
3885                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3886                                 bge_rxreuse_std(sc, rxidx);
3887                                 continue;
3888                         }
3889                         if (bge_newbuf_std(sc, rxidx) != 0) {
3890                                 bge_rxreuse_std(sc, rxidx);
3891                                 ifp->if_iqdrops++;
3892                                 continue;
3893                         }
3894                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3895                 }
3896
3897                 ifp->if_ipackets++;
3898 #ifndef __NO_STRICT_ALIGNMENT
3899                 /*
3900                  * For architectures with strict alignment we must make sure
3901                  * the payload is aligned.
3902                  */
3903                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
3904                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
3905                             cur_rx->bge_len);
3906                         m->m_data += ETHER_ALIGN;
3907                 }
3908 #endif
3909                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3910                 m->m_pkthdr.rcvif = ifp;
3911
3912                 if (ifp->if_capenable & IFCAP_RXCSUM)
3913                         bge_rxcsum(sc, cur_rx, m);
3914
3915                 /*
3916                  * If we received a packet with a vlan tag,
3917                  * attach that information to the packet.
3918                  */
3919                 if (have_tag) {
3920                         m->m_pkthdr.ether_vtag = vlan_tag;
3921                         m->m_flags |= M_VLANTAG;
3922                 }
3923
3924                 if (holdlck != 0) {
3925                         BGE_UNLOCK(sc);
3926                         (*ifp->if_input)(ifp, m);
3927                         BGE_LOCK(sc);
3928                 } else
3929                         (*ifp->if_input)(ifp, m);
3930                 rx_npkts++;
3931
3932                 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
3933                         return (rx_npkts);
3934         }
3935
3936         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3937             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
3938         if (stdcnt > 0)
3939                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3940                     sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
3941
3942         if (jumbocnt > 0)
3943                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3944                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
3945
3946         sc->bge_rx_saved_considx = rx_cons;
3947         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3948         if (stdcnt)
3949                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
3950                     BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT);
3951         if (jumbocnt)
3952                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
3953                     BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT);
3954 #ifdef notyet
3955         /*
3956          * This register wraps very quickly under heavy packet drops.
3957          * If you need correct statistics, you can enable this check.
3958          */
3959         if (BGE_IS_5705_PLUS(sc))
3960                 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3961 #endif
3962         return (rx_npkts);
3963 }
3964
3965 static void
3966 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
3967 {
3968
3969         if (BGE_IS_5717_PLUS(sc)) {
3970                 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
3971                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3972                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3973                                 if ((cur_rx->bge_error_flag &
3974                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
3975                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3976                         }
3977                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
3978                                 m->m_pkthdr.csum_data =
3979                                     cur_rx->bge_tcp_udp_csum;
3980                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
3981                                     CSUM_PSEUDO_HDR;
3982                         }
3983                 }
3984         } else {
3985                 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3986                         m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3987                         if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
3988                                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3989                 }
3990                 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
3991                     m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
3992                         m->m_pkthdr.csum_data =
3993                             cur_rx->bge_tcp_udp_csum;
3994                         m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
3995                             CSUM_PSEUDO_HDR;
3996                 }
3997         }
3998 }
3999
4000 static void
4001 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
4002 {
4003         struct bge_tx_bd *cur_tx;
4004         struct ifnet *ifp;
4005
4006         BGE_LOCK_ASSERT(sc);
4007
4008         /* Nothing to do. */
4009         if (sc->bge_tx_saved_considx == tx_cons)
4010                 return;
4011
4012         ifp = sc->bge_ifp;
4013
4014         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4015             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
4016         /*
4017          * Go through our tx ring and free mbufs for those
4018          * frames that have been sent.
4019          */
4020         while (sc->bge_tx_saved_considx != tx_cons) {
4021                 uint32_t                idx;
4022
4023                 idx = sc->bge_tx_saved_considx;
4024                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
4025                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
4026                         ifp->if_opackets++;
4027                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
4028                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
4029                             sc->bge_cdata.bge_tx_dmamap[idx],
4030                             BUS_DMASYNC_POSTWRITE);
4031                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
4032                             sc->bge_cdata.bge_tx_dmamap[idx]);
4033                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
4034                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
4035                 }
4036                 sc->bge_txcnt--;
4037                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
4038         }
4039
4040         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4041         if (sc->bge_txcnt == 0)
4042                 sc->bge_timer = 0;
4043 }
4044
4045 #ifdef DEVICE_POLLING
4046 static int
4047 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
4048 {
4049         struct bge_softc *sc = ifp->if_softc;
4050         uint16_t rx_prod, tx_cons;
4051         uint32_t statusword;
4052         int rx_npkts = 0;
4053
4054         BGE_LOCK(sc);
4055         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4056                 BGE_UNLOCK(sc);
4057                 return (rx_npkts);
4058         }
4059
4060         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4061             sc->bge_cdata.bge_status_map,
4062             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4063         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4064         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4065
4066         statusword = sc->bge_ldata.bge_status_block->bge_status;
4067         sc->bge_ldata.bge_status_block->bge_status = 0;
4068
4069         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4070             sc->bge_cdata.bge_status_map,
4071             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4072
4073         /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
4074         if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
4075                 sc->bge_link_evt++;
4076
4077         if (cmd == POLL_AND_CHECK_STATUS)
4078                 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4079                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4080                     sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
4081                         bge_link_upd(sc);
4082
4083         sc->rxcycles = count;
4084         rx_npkts = bge_rxeof(sc, rx_prod, 1);
4085         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4086                 BGE_UNLOCK(sc);
4087                 return (rx_npkts);
4088         }
4089         bge_txeof(sc, tx_cons);
4090         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4091                 bge_start_locked(ifp);
4092
4093         BGE_UNLOCK(sc);
4094         return (rx_npkts);
4095 }
4096 #endif /* DEVICE_POLLING */
4097
4098 static int
4099 bge_msi_intr(void *arg)
4100 {
4101         struct bge_softc *sc;
4102
4103         sc = (struct bge_softc *)arg;
4104         /*
4105          * This interrupt is not shared and controller already
4106          * disabled further interrupt.
4107          */
4108         taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
4109         return (FILTER_HANDLED);
4110 }
4111
4112 static void
4113 bge_intr_task(void *arg, int pending)
4114 {
4115         struct bge_softc *sc;
4116         struct ifnet *ifp;
4117         uint32_t status, status_tag;
4118         uint16_t rx_prod, tx_cons;
4119
4120         sc = (struct bge_softc *)arg;
4121         ifp = sc->bge_ifp;
4122
4123         BGE_LOCK(sc);
4124         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
4125                 BGE_UNLOCK(sc);
4126                 return;
4127         }
4128
4129         /* Get updated status block. */
4130         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4131             sc->bge_cdata.bge_status_map,
4132             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4133
4134         /* Save producer/consumer indexess. */
4135         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4136         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4137         status = sc->bge_ldata.bge_status_block->bge_status;
4138         status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
4139         sc->bge_ldata.bge_status_block->bge_status = 0;
4140         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4141             sc->bge_cdata.bge_status_map,
4142             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4143         if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
4144                 status_tag = 0;
4145
4146         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
4147                 bge_link_upd(sc);
4148
4149         /* Let controller work. */
4150         bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
4151
4152         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
4153             sc->bge_rx_saved_considx != rx_prod) {
4154                 /* Check RX return ring producer/consumer. */
4155                 BGE_UNLOCK(sc);
4156                 bge_rxeof(sc, rx_prod, 0);
4157                 BGE_LOCK(sc);
4158         }
4159         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4160                 /* Check TX ring producer/consumer. */
4161                 bge_txeof(sc, tx_cons);
4162                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4163                         bge_start_locked(ifp);
4164         }
4165         BGE_UNLOCK(sc);
4166 }
4167
4168 static void
4169 bge_intr(void *xsc)
4170 {
4171         struct bge_softc *sc;
4172         struct ifnet *ifp;
4173         uint32_t statusword;
4174         uint16_t rx_prod, tx_cons;
4175
4176         sc = xsc;
4177
4178         BGE_LOCK(sc);
4179
4180         ifp = sc->bge_ifp;
4181
4182 #ifdef DEVICE_POLLING
4183         if (ifp->if_capenable & IFCAP_POLLING) {
4184                 BGE_UNLOCK(sc);
4185                 return;
4186         }
4187 #endif
4188
4189         /*
4190          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
4191          * disable interrupts by writing nonzero like we used to, since with
4192          * our current organization this just gives complications and
4193          * pessimizations for re-enabling interrupts.  We used to have races
4194          * instead of the necessary complications.  Disabling interrupts
4195          * would just reduce the chance of a status update while we are
4196          * running (by switching to the interrupt-mode coalescence
4197          * parameters), but this chance is already very low so it is more
4198          * efficient to get another interrupt than prevent it.
4199          *
4200          * We do the ack first to ensure another interrupt if there is a
4201          * status update after the ack.  We don't check for the status
4202          * changing later because it is more efficient to get another
4203          * interrupt than prevent it, not quite as above (not checking is
4204          * a smaller optimization than not toggling the interrupt enable,
4205          * since checking doesn't involve PCI accesses and toggling require
4206          * the status check).  So toggling would probably be a pessimization
4207          * even with MSI.  It would only be needed for using a task queue.
4208          */
4209         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4210
4211         /*
4212          * Do the mandatory PCI flush as well as get the link status.
4213          */
4214         statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
4215
4216         /* Make sure the descriptor ring indexes are coherent. */
4217         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4218             sc->bge_cdata.bge_status_map,
4219             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4220         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4221         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4222         sc->bge_ldata.bge_status_block->bge_status = 0;
4223         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4224             sc->bge_cdata.bge_status_map,
4225             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4226
4227         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4228             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4229             statusword || sc->bge_link_evt)
4230                 bge_link_upd(sc);
4231
4232         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4233                 /* Check RX return ring producer/consumer. */
4234                 bge_rxeof(sc, rx_prod, 1);
4235         }
4236
4237         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4238                 /* Check TX ring producer/consumer. */
4239                 bge_txeof(sc, tx_cons);
4240         }
4241
4242         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
4243             !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4244                 bge_start_locked(ifp);
4245
4246         BGE_UNLOCK(sc);
4247 }
4248
4249 static void
4250 bge_asf_driver_up(struct bge_softc *sc)
4251 {
4252         if (sc->bge_asf_mode & ASF_STACKUP) {
4253                 /* Send ASF heartbeat aprox. every 2s */
4254                 if (sc->bge_asf_count)
4255                         sc->bge_asf_count --;
4256                 else {
4257                         sc->bge_asf_count = 2;
4258                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4259                             BGE_FW_CMD_DRV_ALIVE);
4260                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4261                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
4262                             BGE_FW_HB_TIMEOUT_SEC);
4263                         CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
4264                             CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4265                             BGE_RX_CPU_DRV_EVENT);
4266                 }
4267         }
4268 }
4269
4270 static void
4271 bge_tick(void *xsc)
4272 {
4273         struct bge_softc *sc = xsc;
4274         struct mii_data *mii = NULL;
4275
4276         BGE_LOCK_ASSERT(sc);
4277
4278         /* Synchronize with possible callout reset/stop. */
4279         if (callout_pending(&sc->bge_stat_ch) ||
4280             !callout_active(&sc->bge_stat_ch))
4281                 return;
4282
4283         if (BGE_IS_5705_PLUS(sc))
4284                 bge_stats_update_regs(sc);
4285         else
4286                 bge_stats_update(sc);
4287
4288         if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4289                 mii = device_get_softc(sc->bge_miibus);
4290                 /*
4291                  * Do not touch PHY if we have link up. This could break
4292                  * IPMI/ASF mode or produce extra input errors
4293                  * (extra errors was reported for bcm5701 & bcm5704).
4294                  */
4295                 if (!sc->bge_link)
4296                         mii_tick(mii);
4297         } else {
4298                 /*
4299                  * Since in TBI mode auto-polling can't be used we should poll
4300                  * link status manually. Here we register pending link event
4301                  * and trigger interrupt.
4302                  */
4303 #ifdef DEVICE_POLLING
4304                 /* In polling mode we poll link state in bge_poll(). */
4305                 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
4306 #endif
4307                 {
4308                 sc->bge_link_evt++;
4309                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4310                     sc->bge_flags & BGE_FLAG_5788)
4311                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4312                 else
4313                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4314                 }
4315         }
4316
4317         bge_asf_driver_up(sc);
4318         bge_watchdog(sc);
4319
4320         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4321 }
4322
4323 static void
4324 bge_stats_update_regs(struct bge_softc *sc)
4325 {
4326         struct ifnet *ifp;
4327         struct bge_mac_stats *stats;
4328
4329         ifp = sc->bge_ifp;
4330         stats = &sc->bge_mac_stats;
4331
4332         stats->ifHCOutOctets +=
4333             CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4334         stats->etherStatsCollisions +=
4335             CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4336         stats->outXonSent +=
4337             CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4338         stats->outXoffSent +=
4339             CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4340         stats->dot3StatsInternalMacTransmitErrors +=
4341             CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4342         stats->dot3StatsSingleCollisionFrames +=
4343             CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4344         stats->dot3StatsMultipleCollisionFrames +=
4345             CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4346         stats->dot3StatsDeferredTransmissions +=
4347             CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4348         stats->dot3StatsExcessiveCollisions +=
4349             CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4350         stats->dot3StatsLateCollisions +=
4351             CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4352         stats->ifHCOutUcastPkts +=
4353             CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4354         stats->ifHCOutMulticastPkts +=
4355             CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4356         stats->ifHCOutBroadcastPkts +=
4357             CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4358
4359         stats->ifHCInOctets +=
4360             CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4361         stats->etherStatsFragments +=
4362             CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4363         stats->ifHCInUcastPkts +=
4364             CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4365         stats->ifHCInMulticastPkts +=
4366             CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4367         stats->ifHCInBroadcastPkts +=
4368             CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4369         stats->dot3StatsFCSErrors +=
4370             CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4371         stats->dot3StatsAlignmentErrors +=
4372             CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4373         stats->xonPauseFramesReceived +=
4374             CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4375         stats->xoffPauseFramesReceived +=
4376             CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4377         stats->macControlFramesReceived +=
4378             CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4379         stats->xoffStateEntered +=
4380             CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4381         stats->dot3StatsFramesTooLong +=
4382             CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4383         stats->etherStatsJabbers +=
4384             CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4385         stats->etherStatsUndersizePkts +=
4386             CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4387
4388         stats->FramesDroppedDueToFilters +=
4389             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4390         stats->DmaWriteQueueFull +=
4391             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4392         stats->DmaWriteHighPriQueueFull +=
4393             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4394         stats->NoMoreRxBDs +=
4395             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4396         /*
4397          * XXX
4398          * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS
4399          * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0
4400          * includes number of unwanted multicast frames.  This comes
4401          * from silicon bug and known workaround to get rough(not
4402          * exact) counter is to enable interrupt on MBUF low water
4403          * attention.  This can be accomplished by setting
4404          * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE,
4405          * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and
4406          * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL.
4407          * However that change would generate more interrupts and
4408          * there are still possibilities of losing multiple frames
4409          * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling.
4410          * Given that the workaround still would not get correct
4411          * counter I don't think it's worth to implement it.  So
4412          * ignore reading the counter on controllers that have the
4413          * silicon bug.
4414          */
4415         if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
4416             sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
4417             sc->bge_chipid != BGE_CHIPID_BCM5720_A0)
4418                 stats->InputDiscards +=
4419                     CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4420         stats->InputErrors +=
4421             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4422         stats->RecvThresholdHit +=
4423             CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4424
4425         ifp->if_collisions = (u_long)stats->etherStatsCollisions;
4426         ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards +
4427             stats->InputErrors);
4428 }
4429
4430 static void
4431 bge_stats_clear_regs(struct bge_softc *sc)
4432 {
4433
4434         CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4435         CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4436         CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4437         CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4438         CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4439         CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4440         CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4441         CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4442         CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4443         CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4444         CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4445         CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4446         CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4447
4448         CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4449         CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4450         CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4451         CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4452         CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4453         CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4454         CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4455         CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4456         CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4457         CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4458         CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4459         CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4460         CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4461         CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4462
4463         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4464         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4465         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4466         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4467         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4468         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4469         CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4470 }
4471
4472 static void
4473 bge_stats_update(struct bge_softc *sc)
4474 {
4475         struct ifnet *ifp;
4476         bus_size_t stats;
4477         uint32_t cnt;   /* current register value */
4478
4479         ifp = sc->bge_ifp;
4480
4481         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
4482
4483 #define READ_STAT(sc, stats, stat) \
4484         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
4485
4486         cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
4487         ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
4488         sc->bge_tx_collisions = cnt;
4489
4490         cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo);
4491         ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_nobds);
4492         sc->bge_rx_nobds = cnt;
4493         cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo);
4494         ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_inerrs);
4495         sc->bge_rx_inerrs = cnt;
4496         cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
4497         ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
4498         sc->bge_rx_discards = cnt;
4499
4500         cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
4501         ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
4502         sc->bge_tx_discards = cnt;
4503
4504 #undef  READ_STAT
4505 }
4506
4507 /*
4508  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
4509  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
4510  * but when such padded frames employ the bge IP/TCP checksum offload,
4511  * the hardware checksum assist gives incorrect results (possibly
4512  * from incorporating its own padding into the UDP/TCP checksum; who knows).
4513  * If we pad such runts with zeros, the onboard checksum comes out correct.
4514  */
4515 static __inline int
4516 bge_cksum_pad(struct mbuf *m)
4517 {
4518         int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
4519         struct mbuf *last;
4520
4521         /* If there's only the packet-header and we can pad there, use it. */
4522         if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
4523             M_TRAILINGSPACE(m) >= padlen) {
4524                 last = m;
4525         } else {
4526                 /*
4527                  * Walk packet chain to find last mbuf. We will either
4528                  * pad there, or append a new mbuf and pad it.
4529                  */
4530                 for (last = m; last->m_next != NULL; last = last->m_next);
4531                 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
4532                         /* Allocate new empty mbuf, pad it. Compact later. */
4533                         struct mbuf *n;
4534
4535                         MGET(n, M_DONTWAIT, MT_DATA);
4536                         if (n == NULL)
4537                                 return (ENOBUFS);
4538                         n->m_len = 0;
4539                         last->m_next = n;
4540                         last = n;
4541                 }
4542         }
4543
4544         /* Now zero the pad area, to avoid the bge cksum-assist bug. */
4545         memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
4546         last->m_len += padlen;
4547         m->m_pkthdr.len += padlen;
4548
4549         return (0);
4550 }
4551
4552 static struct mbuf *
4553 bge_check_short_dma(struct mbuf *m)
4554 {
4555         struct mbuf *n;
4556         int found;
4557
4558         /*
4559          * If device receive two back-to-back send BDs with less than
4560          * or equal to 8 total bytes then the device may hang.  The two
4561          * back-to-back send BDs must in the same frame for this failure
4562          * to occur.  Scan mbuf chains and see whether two back-to-back
4563          * send BDs are there. If this is the case, allocate new mbuf
4564          * and copy the frame to workaround the silicon bug.
4565          */
4566         for (n = m, found = 0; n != NULL; n = n->m_next) {
4567                 if (n->m_len < 8) {
4568                         found++;
4569                         if (found > 1)
4570                                 break;
4571                         continue;
4572                 }
4573                 found = 0;
4574         }
4575
4576         if (found > 1) {
4577                 n = m_defrag(m, M_DONTWAIT);
4578                 if (n == NULL)
4579                         m_freem(m);
4580         } else
4581                 n = m;
4582         return (n);
4583 }
4584
4585 static struct mbuf *
4586 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
4587     uint16_t *flags)
4588 {
4589         struct ip *ip;
4590         struct tcphdr *tcp;
4591         struct mbuf *n;
4592         uint16_t hlen;
4593         uint32_t poff;
4594
4595         if (M_WRITABLE(m) == 0) {
4596                 /* Get a writable copy. */
4597                 n = m_dup(m, M_DONTWAIT);
4598                 m_freem(m);
4599                 if (n == NULL)
4600                         return (NULL);
4601                 m = n;
4602         }
4603         m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
4604         if (m == NULL)
4605                 return (NULL);
4606         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
4607         poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
4608         m = m_pullup(m, poff + sizeof(struct tcphdr));
4609         if (m == NULL)
4610                 return (NULL);
4611         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
4612         m = m_pullup(m, poff + (tcp->th_off << 2));
4613         if (m == NULL)
4614                 return (NULL);
4615         /*
4616          * It seems controller doesn't modify IP length and TCP pseudo
4617          * checksum. These checksum computed by upper stack should be 0.
4618          */
4619         *mss = m->m_pkthdr.tso_segsz;
4620         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
4621         ip->ip_sum = 0;
4622         ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
4623         /* Clear pseudo checksum computed by TCP stack. */
4624         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
4625         tcp->th_sum = 0;
4626         /*
4627          * Broadcom controllers uses different descriptor format for
4628          * TSO depending on ASIC revision. Due to TSO-capable firmware
4629          * license issue and lower performance of firmware based TSO
4630          * we only support hardware based TSO.
4631          */
4632         /* Calculate header length, incl. TCP/IP options, in 32 bit units. */
4633         hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
4634         if (sc->bge_flags & BGE_FLAG_TSO3) {
4635                 /*
4636                  * For BCM5717 and newer controllers, hardware based TSO
4637                  * uses the 14 lower bits of the bge_mss field to store the
4638                  * MSS and the upper 2 bits to store the lowest 2 bits of
4639                  * the IP/TCP header length.  The upper 6 bits of the header
4640                  * length are stored in the bge_flags[14:10,4] field.  Jumbo
4641                  * frames are supported.
4642                  */
4643                 *mss |= ((hlen & 0x3) << 14);
4644                 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2);
4645         } else {
4646                 /*
4647                  * For BCM5755 and newer controllers, hardware based TSO uses
4648                  * the lower 11 bits to store the MSS and the upper 5 bits to
4649                  * store the IP/TCP header length. Jumbo frames are not
4650                  * supported.
4651                  */
4652                 *mss |= (hlen << 11);
4653         }
4654         return (m);
4655 }
4656
4657 /*
4658  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
4659  * pointers to descriptors.
4660  */
4661 static int
4662 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
4663 {
4664         bus_dma_segment_t       segs[BGE_NSEG_NEW];
4665         bus_dmamap_t            map;
4666         struct bge_tx_bd        *d;
4667         struct mbuf             *m = *m_head;
4668         uint32_t                idx = *txidx;
4669         uint16_t                csum_flags, mss, vlan_tag;
4670         int                     nsegs, i, error;
4671
4672         csum_flags = 0;
4673         mss = 0;
4674         vlan_tag = 0;
4675         if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
4676             m->m_next != NULL) {
4677                 *m_head = bge_check_short_dma(m);
4678                 if (*m_head == NULL)
4679                         return (ENOBUFS);
4680                 m = *m_head;
4681         }
4682         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
4683                 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
4684                 if (*m_head == NULL)
4685                         return (ENOBUFS);
4686                 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
4687                     BGE_TXBDFLAG_CPU_POST_DMA;
4688         } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
4689                 if (m->m_pkthdr.csum_flags & CSUM_IP)
4690                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
4691                 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
4692                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
4693                         if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
4694                             (error = bge_cksum_pad(m)) != 0) {
4695                                 m_freem(m);
4696                                 *m_head = NULL;
4697                                 return (error);
4698                         }
4699                 }
4700                 if (m->m_flags & M_LASTFRAG)
4701                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
4702                 else if (m->m_flags & M_FRAG)
4703                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
4704         }
4705
4706         if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
4707                 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
4708                     m->m_pkthdr.len > ETHER_MAX_LEN)
4709                         csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME;
4710                 if (sc->bge_forced_collapse > 0 &&
4711                     (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
4712                         /*
4713                          * Forcedly collapse mbuf chains to overcome hardware
4714                          * limitation which only support a single outstanding
4715                          * DMA read operation.
4716                          */
4717                         if (sc->bge_forced_collapse == 1)
4718                                 m = m_defrag(m, M_DONTWAIT);
4719                         else
4720                                 m = m_collapse(m, M_DONTWAIT,
4721                                     sc->bge_forced_collapse);
4722                         if (m == NULL)
4723                                 m = *m_head;
4724                         *m_head = m;
4725                 }
4726         }
4727
4728         map = sc->bge_cdata.bge_tx_dmamap[idx];
4729         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
4730             &nsegs, BUS_DMA_NOWAIT);
4731         if (error == EFBIG) {
4732                 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW);
4733                 if (m == NULL) {
4734                         m_freem(*m_head);
4735                         *m_head = NULL;
4736                         return (ENOBUFS);
4737                 }
4738                 *m_head = m;
4739                 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
4740                     m, segs, &nsegs, BUS_DMA_NOWAIT);
4741                 if (error) {
4742                         m_freem(m);
4743                         *m_head = NULL;
4744                         return (error);
4745                 }
4746         } else if (error != 0)
4747                 return (error);
4748
4749         /* Check if we have enough free send BDs. */
4750         if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
4751                 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
4752                 return (ENOBUFS);
4753         }
4754
4755         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
4756
4757         if (m->m_flags & M_VLANTAG) {
4758                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
4759                 vlan_tag = m->m_pkthdr.ether_vtag;
4760         }
4761         for (i = 0; ; i++) {
4762                 d = &sc->bge_ldata.bge_tx_ring[idx];
4763                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
4764                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
4765                 d->bge_len = segs[i].ds_len;
4766                 d->bge_flags = csum_flags;
4767                 d->bge_vlan_tag = vlan_tag;
4768                 d->bge_mss = mss;
4769                 if (i == nsegs - 1)
4770                         break;
4771                 BGE_INC(idx, BGE_TX_RING_CNT);
4772         }
4773
4774         /* Mark the last segment as end of packet... */
4775         d->bge_flags |= BGE_TXBDFLAG_END;
4776
4777         /*
4778          * Insure that the map for this transmission
4779          * is placed at the array index of the last descriptor
4780          * in this chain.
4781          */
4782         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
4783         sc->bge_cdata.bge_tx_dmamap[idx] = map;
4784         sc->bge_cdata.bge_tx_chain[idx] = m;
4785         sc->bge_txcnt += nsegs;
4786
4787         BGE_INC(idx, BGE_TX_RING_CNT);
4788         *txidx = idx;
4789
4790         return (0);
4791 }
4792
4793 /*
4794  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4795  * to the mbuf data regions directly in the transmit descriptors.
4796  */
4797 static void
4798 bge_start_locked(struct ifnet *ifp)
4799 {
4800         struct bge_softc *sc;
4801         struct mbuf *m_head;
4802         uint32_t prodidx;
4803         int count;
4804
4805         sc = ifp->if_softc;
4806         BGE_LOCK_ASSERT(sc);
4807
4808         if (!sc->bge_link ||
4809             (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4810             IFF_DRV_RUNNING)
4811                 return;
4812
4813         prodidx = sc->bge_tx_prodidx;
4814
4815         for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
4816                 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
4817                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4818                         break;
4819                 }
4820                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
4821                 if (m_head == NULL)
4822                         break;
4823
4824                 /*
4825                  * XXX
4826                  * The code inside the if() block is never reached since we
4827                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
4828                  * requests to checksum TCP/UDP in a fragmented packet.
4829                  *
4830                  * XXX
4831                  * safety overkill.  If this is a fragmented packet chain
4832                  * with delayed TCP/UDP checksums, then only encapsulate
4833                  * it if we have enough descriptors to handle the entire
4834                  * chain at once.
4835                  * (paranoia -- may not actually be needed)
4836                  */
4837                 if (m_head->m_flags & M_FIRSTFRAG &&
4838                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
4839                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
4840                             m_head->m_pkthdr.csum_data + 16) {
4841                                 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4842                                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4843                                 break;
4844                         }
4845                 }
4846
4847                 /*
4848                  * Pack the data into the transmit ring. If we
4849                  * don't have room, set the OACTIVE flag and wait
4850                  * for the NIC to drain the ring.
4851                  */
4852                 if (bge_encap(sc, &m_head, &prodidx)) {
4853                         if (m_head == NULL)
4854                                 break;
4855                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4856                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4857                         break;
4858                 }
4859                 ++count;
4860
4861                 /*
4862                  * If there's a BPF listener, bounce a copy of this frame
4863                  * to him.
4864                  */
4865 #ifdef ETHER_BPF_MTAP
4866                 ETHER_BPF_MTAP(ifp, m_head);
4867 #else
4868                 BPF_MTAP(ifp, m_head);
4869 #endif
4870         }
4871
4872         if (count > 0) {
4873                 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4874                     sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
4875                 /* Transmit. */
4876                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4877                 /* 5700 b2 errata */
4878                 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
4879                         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4880
4881                 sc->bge_tx_prodidx = prodidx;
4882
4883                 /*
4884                  * Set a timeout in case the chip goes out to lunch.
4885                  */
4886                 sc->bge_timer = 5;
4887         }
4888 }
4889
4890 /*
4891  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4892  * to the mbuf data regions directly in the transmit descriptors.
4893  */
4894 static void
4895 bge_start(struct ifnet *ifp)
4896 {
4897         struct bge_softc *sc;
4898
4899         sc = ifp->if_softc;
4900         BGE_LOCK(sc);
4901         bge_start_locked(ifp);
4902         BGE_UNLOCK(sc);
4903 }
4904
4905 static void
4906 bge_init_locked(struct bge_softc *sc)
4907 {
4908         struct ifnet *ifp;
4909         uint16_t *m;
4910         uint32_t mode;
4911
4912         BGE_LOCK_ASSERT(sc);
4913
4914         ifp = sc->bge_ifp;
4915
4916         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4917                 return;
4918
4919         /* Cancel pending I/O and flush buffers. */
4920         bge_stop(sc);
4921
4922         bge_stop_fw(sc);
4923         bge_sig_pre_reset(sc, BGE_RESET_START);
4924         bge_reset(sc);
4925         bge_sig_legacy(sc, BGE_RESET_START);
4926         bge_sig_post_reset(sc, BGE_RESET_START);
4927
4928         bge_chipinit(sc);
4929
4930         /*
4931          * Init the various state machines, ring
4932          * control blocks and firmware.
4933          */
4934         if (bge_blockinit(sc)) {
4935                 device_printf(sc->bge_dev, "initialization failure\n");
4936                 return;
4937         }
4938
4939         ifp = sc->bge_ifp;
4940
4941         /* Specify MTU. */
4942         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
4943             ETHER_HDR_LEN + ETHER_CRC_LEN +
4944             (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
4945
4946         /* Load our MAC address. */
4947         m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
4948         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
4949         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
4950
4951         /* Program promiscuous mode. */
4952         bge_setpromisc(sc);
4953
4954         /* Program multicast filter. */
4955         bge_setmulti(sc);
4956
4957         /* Program VLAN tag stripping. */
4958         bge_setvlan(sc);
4959
4960         /* Override UDP checksum offloading. */
4961         if (sc->bge_forced_udpcsum == 0)
4962                 sc->bge_csum_features &= ~CSUM_UDP;
4963         else
4964                 sc->bge_csum_features |= CSUM_UDP;
4965         if (ifp->if_capabilities & IFCAP_TXCSUM &&
4966             ifp->if_capenable & IFCAP_TXCSUM) {
4967                 ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP);
4968                 ifp->if_hwassist |= sc->bge_csum_features;
4969         }
4970
4971         /* Init RX ring. */
4972         if (bge_init_rx_ring_std(sc) != 0) {
4973                 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
4974                 bge_stop(sc);
4975                 return;
4976         }
4977
4978         /*
4979          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
4980          * memory to insure that the chip has in fact read the first
4981          * entry of the ring.
4982          */
4983         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
4984                 uint32_t                v, i;
4985                 for (i = 0; i < 10; i++) {
4986                         DELAY(20);
4987                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
4988                         if (v == (MCLBYTES - ETHER_ALIGN))
4989                                 break;
4990                 }
4991                 if (i == 10)
4992                         device_printf (sc->bge_dev,
4993                             "5705 A0 chip failed to load RX ring\n");
4994         }
4995
4996         /* Init jumbo RX ring. */
4997         if (BGE_IS_JUMBO_CAPABLE(sc) &&
4998             ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
4999             (MCLBYTES - ETHER_ALIGN)) {
5000                 if (bge_init_rx_ring_jumbo(sc) != 0) {
5001                         device_printf(sc->bge_dev,
5002                             "no memory for jumbo Rx buffers.\n");
5003                         bge_stop(sc);
5004                         return;
5005                 }
5006         }
5007
5008         /* Init our RX return ring index. */
5009         sc->bge_rx_saved_considx = 0;
5010
5011         /* Init our RX/TX stat counters. */
5012         sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
5013
5014         /* Init TX ring. */
5015         bge_init_tx_ring(sc);
5016
5017         /* Enable TX MAC state machine lockup fix. */
5018         mode = CSR_READ_4(sc, BGE_TX_MODE);
5019         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
5020                 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
5021         if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
5022                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5023                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
5024                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5025         }
5026         /* Turn on transmitter. */
5027         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
5028
5029         /* Turn on receiver. */
5030         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
5031
5032         /*
5033          * Set the number of good frames to receive after RX MBUF
5034          * Low Watermark has been reached. After the RX MAC receives
5035          * this number of frames, it will drop subsequent incoming
5036          * frames until the MBUF High Watermark is reached.
5037          */
5038         if (sc->bge_asicrev == BGE_ASICREV_BCM57765)
5039                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
5040         else
5041                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
5042
5043         /* Clear MAC statistics. */
5044         if (BGE_IS_5705_PLUS(sc))
5045                 bge_stats_clear_regs(sc);
5046
5047         /* Tell firmware we're alive. */
5048         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5049
5050 #ifdef DEVICE_POLLING
5051         /* Disable interrupts if we are polling. */
5052         if (ifp->if_capenable & IFCAP_POLLING) {
5053                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5054                     BGE_PCIMISCCTL_MASK_PCI_INTR);
5055                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5056         } else
5057 #endif
5058
5059         /* Enable host interrupts. */
5060         {
5061         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
5062         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5063         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5064         }
5065
5066         bge_ifmedia_upd_locked(ifp);
5067
5068         ifp->if_drv_flags |= IFF_DRV_RUNNING;
5069         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5070
5071         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
5072 }
5073
5074 static void
5075 bge_init(void *xsc)
5076 {
5077         struct bge_softc *sc = xsc;
5078
5079         BGE_LOCK(sc);
5080         bge_init_locked(sc);
5081         BGE_UNLOCK(sc);
5082 }
5083
5084 /*
5085  * Set media options.
5086  */
5087 static int
5088 bge_ifmedia_upd(struct ifnet *ifp)
5089 {
5090         struct bge_softc *sc = ifp->if_softc;
5091         int res;
5092
5093         BGE_LOCK(sc);
5094         res = bge_ifmedia_upd_locked(ifp);
5095         BGE_UNLOCK(sc);
5096
5097         return (res);
5098 }
5099
5100 static int
5101 bge_ifmedia_upd_locked(struct ifnet *ifp)
5102 {
5103         struct bge_softc *sc = ifp->if_softc;
5104         struct mii_data *mii;
5105         struct mii_softc *miisc;
5106         struct ifmedia *ifm;
5107
5108         BGE_LOCK_ASSERT(sc);
5109
5110         ifm = &sc->bge_ifmedia;
5111
5112         /* If this is a 1000baseX NIC, enable the TBI port. */
5113         if (sc->bge_flags & BGE_FLAG_TBI) {
5114                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
5115                         return (EINVAL);
5116                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
5117                 case IFM_AUTO:
5118                         /*
5119                          * The BCM5704 ASIC appears to have a special
5120                          * mechanism for programming the autoneg
5121                          * advertisement registers in TBI mode.
5122                          */
5123                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
5124                                 uint32_t sgdig;
5125                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5126                                 if (sgdig & BGE_SGDIGSTS_DONE) {
5127                                         CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5128                                         sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5129                                         sgdig |= BGE_SGDIGCFG_AUTO |
5130                                             BGE_SGDIGCFG_PAUSE_CAP |
5131                                             BGE_SGDIGCFG_ASYM_PAUSE;
5132                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG,
5133                                             sgdig | BGE_SGDIGCFG_SEND);
5134                                         DELAY(5);
5135                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
5136                                 }
5137                         }
5138                         break;
5139                 case IFM_1000_SX:
5140                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
5141                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
5142                                     BGE_MACMODE_HALF_DUPLEX);
5143                         } else {
5144                                 BGE_SETBIT(sc, BGE_MAC_MODE,
5145                                     BGE_MACMODE_HALF_DUPLEX);
5146                         }
5147                         break;
5148                 default:
5149                         return (EINVAL);
5150                 }
5151                 return (0);
5152         }
5153
5154         sc->bge_link_evt++;
5155         mii = device_get_softc(sc->bge_miibus);
5156         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
5157                 PHY_RESET(miisc);
5158         mii_mediachg(mii);
5159
5160         /*
5161          * Force an interrupt so that we will call bge_link_upd
5162          * if needed and clear any pending link state attention.
5163          * Without this we are not getting any further interrupts
5164          * for link state changes and thus will not UP the link and
5165          * not be able to send in bge_start_locked. The only
5166          * way to get things working was to receive a packet and
5167          * get an RX intr.
5168          * bge_tick should help for fiber cards and we might not
5169          * need to do this here if BGE_FLAG_TBI is set but as
5170          * we poll for fiber anyway it should not harm.
5171          */
5172         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
5173             sc->bge_flags & BGE_FLAG_5788)
5174                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
5175         else
5176                 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
5177
5178         return (0);
5179 }
5180
5181 /*
5182  * Report current media status.
5183  */
5184 static void
5185 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
5186 {
5187         struct bge_softc *sc = ifp->if_softc;
5188         struct mii_data *mii;
5189
5190         BGE_LOCK(sc);
5191
5192         if (sc->bge_flags & BGE_FLAG_TBI) {
5193                 ifmr->ifm_status = IFM_AVALID;
5194                 ifmr->ifm_active = IFM_ETHER;
5195                 if (CSR_READ_4(sc, BGE_MAC_STS) &
5196                     BGE_MACSTAT_TBI_PCS_SYNCHED)
5197                         ifmr->ifm_status |= IFM_ACTIVE;
5198                 else {
5199                         ifmr->ifm_active |= IFM_NONE;
5200                         BGE_UNLOCK(sc);
5201                         return;
5202                 }
5203                 ifmr->ifm_active |= IFM_1000_SX;
5204                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5205                         ifmr->ifm_active |= IFM_HDX;
5206                 else
5207                         ifmr->ifm_active |= IFM_FDX;
5208                 BGE_UNLOCK(sc);
5209                 return;
5210         }
5211
5212         mii = device_get_softc(sc->bge_miibus);
5213         mii_pollstat(mii);
5214         ifmr->ifm_active = mii->mii_media_active;
5215         ifmr->ifm_status = mii->mii_media_status;
5216
5217         BGE_UNLOCK(sc);
5218 }
5219
5220 static int
5221 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
5222 {
5223         struct bge_softc *sc = ifp->if_softc;
5224         struct ifreq *ifr = (struct ifreq *) data;
5225         struct mii_data *mii;
5226         int flags, mask, error = 0;
5227
5228         switch (command) {
5229         case SIOCSIFMTU:
5230                 if (BGE_IS_JUMBO_CAPABLE(sc) ||
5231                     (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
5232                         if (ifr->ifr_mtu < ETHERMIN ||
5233                             ifr->ifr_mtu > BGE_JUMBO_MTU) {
5234                                 error = EINVAL;
5235                                 break;
5236                         }
5237                 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) {
5238                         error = EINVAL;
5239                         break;
5240                 }
5241                 BGE_LOCK(sc);
5242                 if (ifp->if_mtu != ifr->ifr_mtu) {
5243                         ifp->if_mtu = ifr->ifr_mtu;
5244                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5245                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5246                                 bge_init_locked(sc);
5247                         }
5248                 }
5249                 BGE_UNLOCK(sc);
5250                 break;
5251         case SIOCSIFFLAGS:
5252                 BGE_LOCK(sc);
5253                 if (ifp->if_flags & IFF_UP) {
5254                         /*
5255                          * If only the state of the PROMISC flag changed,
5256                          * then just use the 'set promisc mode' command
5257                          * instead of reinitializing the entire NIC. Doing
5258                          * a full re-init means reloading the firmware and
5259                          * waiting for it to start up, which may take a
5260                          * second or two.  Similarly for ALLMULTI.
5261                          */
5262                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5263                                 flags = ifp->if_flags ^ sc->bge_if_flags;
5264                                 if (flags & IFF_PROMISC)
5265                                         bge_setpromisc(sc);
5266                                 if (flags & IFF_ALLMULTI)
5267                                         bge_setmulti(sc);
5268                         } else
5269                                 bge_init_locked(sc);
5270                 } else {
5271                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5272                                 bge_stop(sc);
5273                         }
5274                 }
5275                 sc->bge_if_flags = ifp->if_flags;
5276                 BGE_UNLOCK(sc);
5277                 error = 0;
5278                 break;
5279         case SIOCADDMULTI:
5280         case SIOCDELMULTI:
5281                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5282                         BGE_LOCK(sc);
5283                         bge_setmulti(sc);
5284                         BGE_UNLOCK(sc);
5285                         error = 0;
5286                 }
5287                 break;
5288         case SIOCSIFMEDIA:
5289         case SIOCGIFMEDIA:
5290                 if (sc->bge_flags & BGE_FLAG_TBI) {
5291                         error = ifmedia_ioctl(ifp, ifr,
5292                             &sc->bge_ifmedia, command);
5293                 } else {
5294                         mii = device_get_softc(sc->bge_miibus);
5295                         error = ifmedia_ioctl(ifp, ifr,
5296                             &mii->mii_media, command);
5297                 }
5298                 break;
5299         case SIOCSIFCAP:
5300                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5301 #ifdef DEVICE_POLLING
5302                 if (mask & IFCAP_POLLING) {
5303                         if (ifr->ifr_reqcap & IFCAP_POLLING) {
5304                                 error = ether_poll_register(bge_poll, ifp);
5305                                 if (error)
5306                                         return (error);
5307                                 BGE_LOCK(sc);
5308                                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5309                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
5310                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5311                                 ifp->if_capenable |= IFCAP_POLLING;
5312                                 BGE_UNLOCK(sc);
5313                         } else {
5314                                 error = ether_poll_deregister(ifp);
5315                                 /* Enable interrupt even in error case */
5316                                 BGE_LOCK(sc);
5317                                 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
5318                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
5319                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5320                                 ifp->if_capenable &= ~IFCAP_POLLING;
5321                                 BGE_UNLOCK(sc);
5322                         }
5323                 }
5324 #endif
5325                 if ((mask & IFCAP_TXCSUM) != 0 &&
5326                     (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
5327                         ifp->if_capenable ^= IFCAP_TXCSUM;
5328                         if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
5329                                 ifp->if_hwassist |= sc->bge_csum_features;
5330                         else
5331                                 ifp->if_hwassist &= ~sc->bge_csum_features;
5332                 }
5333
5334                 if ((mask & IFCAP_RXCSUM) != 0 &&
5335                     (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
5336                         ifp->if_capenable ^= IFCAP_RXCSUM;
5337
5338                 if ((mask & IFCAP_TSO4) != 0 &&
5339                     (ifp->if_capabilities & IFCAP_TSO4) != 0) {
5340                         ifp->if_capenable ^= IFCAP_TSO4;
5341                         if ((ifp->if_capenable & IFCAP_TSO4) != 0)
5342                                 ifp->if_hwassist |= CSUM_TSO;
5343                         else
5344                                 ifp->if_hwassist &= ~CSUM_TSO;
5345                 }
5346
5347                 if (mask & IFCAP_VLAN_MTU) {
5348                         ifp->if_capenable ^= IFCAP_VLAN_MTU;
5349                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5350                         bge_init(sc);
5351                 }
5352
5353                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
5354                     (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
5355                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
5356                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
5357                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
5358                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
5359                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
5360                                 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
5361                         BGE_LOCK(sc);
5362                         bge_setvlan(sc);
5363                         BGE_UNLOCK(sc);
5364                 }
5365 #ifdef VLAN_CAPABILITIES
5366                 VLAN_CAPABILITIES(ifp);
5367 #endif
5368                 break;
5369         default:
5370                 error = ether_ioctl(ifp, command, data);
5371                 break;
5372         }
5373
5374         return (error);
5375 }
5376
5377 static void
5378 bge_watchdog(struct bge_softc *sc)
5379 {
5380         struct ifnet *ifp;
5381
5382         BGE_LOCK_ASSERT(sc);
5383
5384         if (sc->bge_timer == 0 || --sc->bge_timer)
5385                 return;
5386
5387         ifp = sc->bge_ifp;
5388
5389         if_printf(ifp, "watchdog timeout -- resetting\n");
5390
5391         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5392         bge_init_locked(sc);
5393
5394         ifp->if_oerrors++;
5395 }
5396
5397 static void
5398 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
5399 {
5400         int i;
5401
5402         BGE_CLRBIT(sc, reg, bit);
5403
5404         for (i = 0; i < BGE_TIMEOUT; i++) {
5405                 if ((CSR_READ_4(sc, reg) & bit) == 0)
5406                         return;
5407                 DELAY(100);
5408         }
5409 }
5410
5411 /*
5412  * Stop the adapter and free any mbufs allocated to the
5413  * RX and TX lists.
5414  */
5415 static void
5416 bge_stop(struct bge_softc *sc)
5417 {
5418         struct ifnet *ifp;
5419
5420         BGE_LOCK_ASSERT(sc);
5421
5422         ifp = sc->bge_ifp;
5423
5424         callout_stop(&sc->bge_stat_ch);
5425
5426         /* Disable host interrupts. */
5427         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5428         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5429
5430         /*
5431          * Tell firmware we're shutting down.
5432          */
5433         bge_stop_fw(sc);
5434         bge_sig_pre_reset(sc, BGE_RESET_STOP);
5435
5436         /*
5437          * Disable all of the receiver blocks.
5438          */
5439         bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
5440         bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
5441         bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
5442         if (BGE_IS_5700_FAMILY(sc))
5443                 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
5444         bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
5445         bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
5446         bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
5447
5448         /*
5449          * Disable all of the transmit blocks.
5450          */
5451         bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
5452         bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
5453         bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
5454         bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
5455         bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
5456         if (BGE_IS_5700_FAMILY(sc))
5457                 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
5458         bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
5459
5460         /*
5461          * Shut down all of the memory managers and related
5462          * state machines.
5463          */
5464         bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
5465         bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
5466         if (BGE_IS_5700_FAMILY(sc))
5467                 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
5468
5469         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
5470         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
5471         if (!(BGE_IS_5705_PLUS(sc))) {
5472                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
5473                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
5474         }
5475         /* Update MAC statistics. */
5476         if (BGE_IS_5705_PLUS(sc))
5477                 bge_stats_update_regs(sc);
5478
5479         bge_reset(sc);
5480         bge_sig_legacy(sc, BGE_RESET_STOP);
5481         bge_sig_post_reset(sc, BGE_RESET_STOP);
5482
5483         /*
5484          * Keep the ASF firmware running if up.
5485          */
5486         if (sc->bge_asf_mode & ASF_STACKUP)
5487                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5488         else
5489                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5490
5491         /* Free the RX lists. */
5492         bge_free_rx_ring_std(sc);
5493
5494         /* Free jumbo RX list. */
5495         if (BGE_IS_JUMBO_CAPABLE(sc))
5496                 bge_free_rx_ring_jumbo(sc);
5497
5498         /* Free TX buffers. */
5499         bge_free_tx_ring(sc);
5500
5501         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
5502
5503         /* Clear MAC's link state (PHY may still have link UP). */
5504         if (bootverbose && sc->bge_link)
5505                 if_printf(sc->bge_ifp, "link DOWN\n");
5506         sc->bge_link = 0;
5507
5508         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
5509 }
5510
5511 /*
5512  * Stop all chip I/O so that the kernel's probe routines don't
5513  * get confused by errant DMAs when rebooting.
5514  */
5515 static int
5516 bge_shutdown(device_t dev)
5517 {
5518         struct bge_softc *sc;
5519
5520         sc = device_get_softc(dev);
5521         BGE_LOCK(sc);
5522         bge_stop(sc);
5523         bge_reset(sc);
5524         BGE_UNLOCK(sc);
5525
5526         return (0);
5527 }
5528
5529 static int
5530 bge_suspend(device_t dev)
5531 {
5532         struct bge_softc *sc;
5533
5534         sc = device_get_softc(dev);
5535         BGE_LOCK(sc);
5536         bge_stop(sc);
5537         BGE_UNLOCK(sc);
5538
5539         return (0);
5540 }
5541
5542 static int
5543 bge_resume(device_t dev)
5544 {
5545         struct bge_softc *sc;
5546         struct ifnet *ifp;
5547
5548         sc = device_get_softc(dev);
5549         BGE_LOCK(sc);
5550         ifp = sc->bge_ifp;
5551         if (ifp->if_flags & IFF_UP) {
5552                 bge_init_locked(sc);
5553                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
5554                         bge_start_locked(ifp);
5555         }
5556         BGE_UNLOCK(sc);
5557
5558         return (0);
5559 }
5560
5561 static void
5562 bge_link_upd(struct bge_softc *sc)
5563 {
5564         struct mii_data *mii;
5565         uint32_t link, status;
5566
5567         BGE_LOCK_ASSERT(sc);
5568
5569         /* Clear 'pending link event' flag. */
5570         sc->bge_link_evt = 0;
5571
5572         /*
5573          * Process link state changes.
5574          * Grrr. The link status word in the status block does
5575          * not work correctly on the BCM5700 rev AX and BX chips,
5576          * according to all available information. Hence, we have
5577          * to enable MII interrupts in order to properly obtain
5578          * async link changes. Unfortunately, this also means that
5579          * we have to read the MAC status register to detect link
5580          * changes, thereby adding an additional register access to
5581          * the interrupt handler.
5582          *
5583          * XXX: perhaps link state detection procedure used for
5584          * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
5585          */
5586
5587         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
5588             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
5589                 status = CSR_READ_4(sc, BGE_MAC_STS);
5590                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
5591                         mii = device_get_softc(sc->bge_miibus);
5592                         mii_pollstat(mii);
5593                         if (!sc->bge_link &&
5594                             mii->mii_media_status & IFM_ACTIVE &&
5595                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5596                                 sc->bge_link++;
5597                                 if (bootverbose)
5598                                         if_printf(sc->bge_ifp, "link UP\n");
5599                         } else if (sc->bge_link &&
5600                             (!(mii->mii_media_status & IFM_ACTIVE) ||
5601                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
5602                                 sc->bge_link = 0;
5603                                 if (bootverbose)
5604                                         if_printf(sc->bge_ifp, "link DOWN\n");
5605                         }
5606
5607                         /* Clear the interrupt. */
5608                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
5609                             BGE_EVTENB_MI_INTERRUPT);
5610                         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
5611                         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
5612                             BRGPHY_INTRS);
5613                 }
5614                 return;
5615         }
5616
5617         if (sc->bge_flags & BGE_FLAG_TBI) {
5618                 status = CSR_READ_4(sc, BGE_MAC_STS);
5619                 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
5620                         if (!sc->bge_link) {
5621                                 sc->bge_link++;
5622                                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
5623                                         BGE_CLRBIT(sc, BGE_MAC_MODE,
5624                                             BGE_MACMODE_TBI_SEND_CFGS);
5625                                 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
5626                                 if (bootverbose)
5627                                         if_printf(sc->bge_ifp, "link UP\n");
5628                                 if_link_state_change(sc->bge_ifp,
5629                                     LINK_STATE_UP);
5630                         }
5631                 } else if (sc->bge_link) {
5632                         sc->bge_link = 0;
5633                         if (bootverbose)
5634                                 if_printf(sc->bge_ifp, "link DOWN\n");
5635                         if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
5636                 }
5637         } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
5638                 /*
5639                  * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
5640                  * in status word always set. Workaround this bug by reading
5641                  * PHY link status directly.
5642                  */
5643                 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
5644
5645                 if (link != sc->bge_link ||
5646                     sc->bge_asicrev == BGE_ASICREV_BCM5700) {
5647                         mii = device_get_softc(sc->bge_miibus);
5648                         mii_pollstat(mii);
5649                         if (!sc->bge_link &&
5650                             mii->mii_media_status & IFM_ACTIVE &&
5651                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5652                                 sc->bge_link++;
5653                                 if (bootverbose)
5654                                         if_printf(sc->bge_ifp, "link UP\n");
5655                         } else if (sc->bge_link &&
5656                             (!(mii->mii_media_status & IFM_ACTIVE) ||
5657                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
5658                                 sc->bge_link = 0;
5659                                 if (bootverbose)
5660                                         if_printf(sc->bge_ifp, "link DOWN\n");
5661                         }
5662                 }
5663         } else {
5664                 /*
5665                  * For controllers that call mii_tick, we have to poll
5666                  * link status.
5667                  */
5668                 mii = device_get_softc(sc->bge_miibus);
5669                 mii_pollstat(mii);
5670                 bge_miibus_statchg(sc->bge_dev);
5671         }
5672
5673         /* Clear the attention. */
5674         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
5675             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
5676             BGE_MACSTAT_LINK_CHANGED);
5677 }
5678
5679 static void
5680 bge_add_sysctls(struct bge_softc *sc)
5681 {
5682         struct sysctl_ctx_list *ctx;
5683         struct sysctl_oid_list *children;
5684         char tn[32];
5685         int unit;
5686
5687         ctx = device_get_sysctl_ctx(sc->bge_dev);
5688         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
5689
5690 #ifdef BGE_REGISTER_DEBUG
5691         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
5692             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
5693             "Debug Information");
5694
5695         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
5696             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
5697             "Register Read");
5698
5699         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
5700             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
5701             "Memory Read");
5702
5703 #endif
5704
5705         unit = device_get_unit(sc->bge_dev);
5706         /*
5707          * A common design characteristic for many Broadcom client controllers
5708          * is that they only support a single outstanding DMA read operation
5709          * on the PCIe bus. This means that it will take twice as long to fetch
5710          * a TX frame that is split into header and payload buffers as it does
5711          * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
5712          * these controllers, coalescing buffers to reduce the number of memory
5713          * reads is effective way to get maximum performance(about 940Mbps).
5714          * Without collapsing TX buffers the maximum TCP bulk transfer
5715          * performance is about 850Mbps. However forcing coalescing mbufs
5716          * consumes a lot of CPU cycles, so leave it off by default.
5717          */
5718         sc->bge_forced_collapse = 0;
5719         snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit);
5720         TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse);
5721         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
5722             CTLFLAG_RW, &sc->bge_forced_collapse, 0,
5723             "Number of fragmented TX buffers of a frame allowed before "
5724             "forced collapsing");
5725
5726         sc->bge_msi = 1;
5727         snprintf(tn, sizeof(tn), "dev.bge.%d.msi", unit);
5728         TUNABLE_INT_FETCH(tn, &sc->bge_msi);
5729         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi",
5730             CTLFLAG_RD, &sc->bge_msi, 0, "Enable MSI");
5731
5732         /*
5733          * It seems all Broadcom controllers have a bug that can generate UDP
5734          * datagrams with checksum value 0 when TX UDP checksum offloading is
5735          * enabled.  Generating UDP checksum value 0 is RFC 768 violation.
5736          * Even though the probability of generating such UDP datagrams is
5737          * low, I don't want to see FreeBSD boxes to inject such datagrams
5738          * into network so disable UDP checksum offloading by default.  Users
5739          * still override this behavior by setting a sysctl variable,
5740          * dev.bge.0.forced_udpcsum.
5741          */
5742         sc->bge_forced_udpcsum = 0;
5743         snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit);
5744         TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum);
5745         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum",
5746             CTLFLAG_RW, &sc->bge_forced_udpcsum, 0,
5747             "Enable UDP checksum offloading even if controller can "
5748             "generate UDP checksum value 0");
5749
5750         if (BGE_IS_5705_PLUS(sc))
5751                 bge_add_sysctl_stats_regs(sc, ctx, children);
5752         else
5753                 bge_add_sysctl_stats(sc, ctx, children);
5754 }
5755
5756 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
5757         SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
5758             sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
5759             desc)
5760
5761 static void
5762 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
5763     struct sysctl_oid_list *parent)
5764 {
5765         struct sysctl_oid *tree;
5766         struct sysctl_oid_list *children, *schildren;
5767
5768         tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
5769             NULL, "BGE Statistics");
5770         schildren = children = SYSCTL_CHILDREN(tree);
5771         BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
5772             children, COSFramesDroppedDueToFilters,
5773             "FramesDroppedDueToFilters");
5774         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
5775             children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
5776         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
5777             children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
5778         BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
5779             children, nicNoMoreRxBDs, "NoMoreRxBDs");
5780         BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
5781             children, ifInDiscards, "InputDiscards");
5782         BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
5783             children, ifInErrors, "InputErrors");
5784         BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
5785             children, nicRecvThresholdHit, "RecvThresholdHit");
5786         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
5787             children, nicDmaReadQueueFull, "DmaReadQueueFull");
5788         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
5789             children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
5790         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
5791             children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
5792         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
5793             children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
5794         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
5795             children, nicRingStatusUpdate, "RingStatusUpdate");
5796         BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
5797             children, nicInterrupts, "Interrupts");
5798         BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
5799             children, nicAvoidedInterrupts, "AvoidedInterrupts");
5800         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
5801             children, nicSendThresholdHit, "SendThresholdHit");
5802
5803         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
5804             NULL, "BGE RX Statistics");
5805         children = SYSCTL_CHILDREN(tree);
5806         BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
5807             children, rxstats.ifHCInOctets, "ifHCInOctets");
5808         BGE_SYSCTL_STAT(sc, ctx, "Fragments",
5809             children, rxstats.etherStatsFragments, "Fragments");
5810         BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
5811             children, rxstats.ifHCInUcastPkts, "UnicastPkts");
5812         BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
5813             children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
5814         BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
5815             children, rxstats.dot3StatsFCSErrors, "FCSErrors");
5816         BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
5817             children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
5818         BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
5819             children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
5820         BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
5821             children, rxstats.xoffPauseFramesReceived,
5822             "xoffPauseFramesReceived");
5823         BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
5824             children, rxstats.macControlFramesReceived,
5825             "ControlFramesReceived");
5826         BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
5827             children, rxstats.xoffStateEntered, "xoffStateEntered");
5828         BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
5829             children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
5830         BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
5831             children, rxstats.etherStatsJabbers, "Jabbers");
5832         BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
5833             children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
5834         BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
5835             children, rxstats.inRangeLengthError, "inRangeLengthError");
5836         BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
5837             children, rxstats.outRangeLengthError, "outRangeLengthError");
5838
5839         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
5840             NULL, "BGE TX Statistics");
5841         children = SYSCTL_CHILDREN(tree);
5842         BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
5843             children, txstats.ifHCOutOctets, "ifHCOutOctets");
5844         BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
5845             children, txstats.etherStatsCollisions, "Collisions");
5846         BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
5847             children, txstats.outXonSent, "XonSent");
5848         BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
5849             children, txstats.outXoffSent, "XoffSent");
5850         BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
5851             children, txstats.flowControlDone, "flowControlDone");
5852         BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
5853             children, txstats.dot3StatsInternalMacTransmitErrors,
5854             "InternalMacTransmitErrors");
5855         BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
5856             children, txstats.dot3StatsSingleCollisionFrames,
5857             "SingleCollisionFrames");
5858         BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
5859             children, txstats.dot3StatsMultipleCollisionFrames,
5860             "MultipleCollisionFrames");
5861         BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
5862             children, txstats.dot3StatsDeferredTransmissions,
5863             "DeferredTransmissions");
5864         BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
5865             children, txstats.dot3StatsExcessiveCollisions,
5866             "ExcessiveCollisions");
5867         BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
5868             children, txstats.dot3StatsLateCollisions,
5869             "LateCollisions");
5870         BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
5871             children, txstats.ifHCOutUcastPkts, "UnicastPkts");
5872         BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
5873             children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
5874         BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
5875             children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
5876         BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
5877             children, txstats.dot3StatsCarrierSenseErrors,
5878             "CarrierSenseErrors");
5879         BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
5880             children, txstats.ifOutDiscards, "Discards");
5881         BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
5882             children, txstats.ifOutErrors, "Errors");
5883 }
5884
5885 #undef BGE_SYSCTL_STAT
5886
5887 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d)    \
5888             SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
5889
5890 static void
5891 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
5892     struct sysctl_oid_list *parent)
5893 {
5894         struct sysctl_oid *tree;
5895         struct sysctl_oid_list *child, *schild;
5896         struct bge_mac_stats *stats;
5897
5898         stats = &sc->bge_mac_stats;
5899         tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
5900             NULL, "BGE Statistics");
5901         schild = child = SYSCTL_CHILDREN(tree);
5902         BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters",
5903             &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters");
5904         BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull",
5905             &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full");
5906         BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull",
5907             &stats->DmaWriteHighPriQueueFull,
5908             "NIC DMA Write High Priority Queue Full");
5909         BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs",
5910             &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors");
5911         BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards",
5912             &stats->InputDiscards, "Discarded Input Frames");
5913         BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors",
5914             &stats->InputErrors, "Input Errors");
5915         BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit",
5916             &stats->RecvThresholdHit, "NIC Recv Threshold Hit");
5917
5918         tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD,
5919             NULL, "BGE RX Statistics");
5920         child = SYSCTL_CHILDREN(tree);
5921         BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets",
5922             &stats->ifHCInOctets, "Inbound Octets");
5923         BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments",
5924             &stats->etherStatsFragments, "Fragments");
5925         BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
5926             &stats->ifHCInUcastPkts, "Inbound Unicast Packets");
5927         BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
5928             &stats->ifHCInMulticastPkts, "Inbound Multicast Packets");
5929         BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
5930             &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets");
5931         BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors",
5932             &stats->dot3StatsFCSErrors, "FCS Errors");
5933         BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors",
5934             &stats->dot3StatsAlignmentErrors, "Alignment Errors");
5935         BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived",
5936             &stats->xonPauseFramesReceived, "XON Pause Frames Received");
5937         BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived",
5938             &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received");
5939         BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived",
5940             &stats->macControlFramesReceived, "MAC Control Frames Received");
5941         BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered",
5942             &stats->xoffStateEntered, "XOFF State Entered");
5943         BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong",
5944             &stats->dot3StatsFramesTooLong, "Frames Too Long");
5945         BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers",
5946             &stats->etherStatsJabbers, "Jabbers");
5947         BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts",
5948             &stats->etherStatsUndersizePkts, "Undersized Packets");
5949
5950         tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD,
5951             NULL, "BGE TX Statistics");
5952         child = SYSCTL_CHILDREN(tree);
5953         BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets",
5954             &stats->ifHCOutOctets, "Outbound Octets");
5955         BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions",
5956             &stats->etherStatsCollisions, "TX Collisions");
5957         BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent",
5958             &stats->outXonSent, "XON Sent");
5959         BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent",
5960             &stats->outXoffSent, "XOFF Sent");
5961         BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors",
5962             &stats->dot3StatsInternalMacTransmitErrors,
5963             "Internal MAC TX Errors");
5964         BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames",
5965             &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames");
5966         BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames",
5967             &stats->dot3StatsMultipleCollisionFrames,
5968             "Multiple Collision Frames");
5969         BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions",
5970             &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions");
5971         BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions",
5972             &stats->dot3StatsExcessiveCollisions, "Excessive Collisions");
5973         BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions",
5974             &stats->dot3StatsLateCollisions, "Late Collisions");
5975         BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
5976             &stats->ifHCOutUcastPkts, "Outbound Unicast Packets");
5977         BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
5978             &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets");
5979         BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
5980             &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets");
5981 }
5982
5983 #undef  BGE_SYSCTL_STAT_ADD64
5984
5985 static int
5986 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
5987 {
5988         struct bge_softc *sc;
5989         uint32_t result;
5990         int offset;
5991
5992         sc = (struct bge_softc *)arg1;
5993         offset = arg2;
5994         result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
5995             offsetof(bge_hostaddr, bge_addr_lo));
5996         return (sysctl_handle_int(oidp, &result, 0, req));
5997 }
5998
5999 #ifdef BGE_REGISTER_DEBUG
6000 static int
6001 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
6002 {
6003         struct bge_softc *sc;
6004         uint16_t *sbdata;
6005         int error, result, sbsz;
6006         int i, j;
6007
6008         result = -1;
6009         error = sysctl_handle_int(oidp, &result, 0, req);
6010         if (error || (req->newptr == NULL))
6011                 return (error);
6012
6013         if (result == 1) {
6014                 sc = (struct bge_softc *)arg1;
6015
6016                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6017                     sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
6018                         sbsz = BGE_STATUS_BLK_SZ;
6019                 else
6020                         sbsz = 32;
6021                 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
6022                 printf("Status Block:\n");
6023                 BGE_LOCK(sc);
6024                 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6025                     sc->bge_cdata.bge_status_map,
6026                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6027                 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) {
6028                         printf("%06x:", i);
6029                         for (j = 0; j < 8; j++)
6030                                 printf(" %04x", sbdata[i++]);
6031                         printf("\n");
6032                 }
6033
6034                 printf("Registers:\n");
6035                 for (i = 0x800; i < 0xA00; ) {
6036                         printf("%06x:", i);
6037                         for (j = 0; j < 8; j++) {
6038                                 printf(" %08x", CSR_READ_4(sc, i));
6039                                 i += 4;
6040                         }
6041                         printf("\n");
6042                 }
6043                 BGE_UNLOCK(sc);
6044
6045                 printf("Hardware Flags:\n");
6046                 if (BGE_IS_5717_PLUS(sc))
6047                         printf(" - 5717 Plus\n");
6048                 if (BGE_IS_5755_PLUS(sc))
6049                         printf(" - 5755 Plus\n");
6050                 if (BGE_IS_575X_PLUS(sc))
6051                         printf(" - 575X Plus\n");
6052                 if (BGE_IS_5705_PLUS(sc))
6053                         printf(" - 5705 Plus\n");
6054                 if (BGE_IS_5714_FAMILY(sc))
6055                         printf(" - 5714 Family\n");
6056                 if (BGE_IS_5700_FAMILY(sc))
6057                         printf(" - 5700 Family\n");
6058                 if (sc->bge_flags & BGE_FLAG_JUMBO)
6059                         printf(" - Supports Jumbo Frames\n");
6060                 if (sc->bge_flags & BGE_FLAG_PCIX)
6061                         printf(" - PCI-X Bus\n");
6062                 if (sc->bge_flags & BGE_FLAG_PCIE)
6063                         printf(" - PCI Express Bus\n");
6064                 if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
6065                         printf(" - No 3 LEDs\n");
6066                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
6067                         printf(" - RX Alignment Bug\n");
6068         }
6069
6070         return (error);
6071 }
6072
6073 static int
6074 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6075 {
6076         struct bge_softc *sc;
6077         int error;
6078         uint16_t result;
6079         uint32_t val;
6080
6081         result = -1;
6082         error = sysctl_handle_int(oidp, &result, 0, req);
6083         if (error || (req->newptr == NULL))
6084                 return (error);
6085
6086         if (result < 0x8000) {
6087                 sc = (struct bge_softc *)arg1;
6088                 val = CSR_READ_4(sc, result);
6089                 printf("reg 0x%06X = 0x%08X\n", result, val);
6090         }
6091
6092         return (error);
6093 }
6094
6095 static int
6096 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
6097 {
6098         struct bge_softc *sc;
6099         int error;
6100         uint16_t result;
6101         uint32_t val;
6102
6103         result = -1;
6104         error = sysctl_handle_int(oidp, &result, 0, req);
6105         if (error || (req->newptr == NULL))
6106                 return (error);
6107
6108         if (result < 0x8000) {
6109                 sc = (struct bge_softc *)arg1;
6110                 val = bge_readmem_ind(sc, result);
6111                 printf("mem 0x%06X = 0x%08X\n", result, val);
6112         }
6113
6114         return (error);
6115 }
6116 #endif
6117
6118 static int
6119 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
6120 {
6121
6122         if (sc->bge_flags & BGE_FLAG_EADDR)
6123                 return (1);
6124
6125 #ifdef __sparc64__
6126         OF_getetheraddr(sc->bge_dev, ether_addr);
6127         return (0);
6128 #endif
6129         return (1);
6130 }
6131
6132 static int
6133 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
6134 {
6135         uint32_t mac_addr;
6136
6137         mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
6138         if ((mac_addr >> 16) == 0x484b) {
6139                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
6140                 ether_addr[1] = (uint8_t)mac_addr;
6141                 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
6142                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
6143                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
6144                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
6145                 ether_addr[5] = (uint8_t)mac_addr;
6146                 return (0);
6147         }
6148         return (1);
6149 }
6150
6151 static int
6152 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
6153 {
6154         int mac_offset = BGE_EE_MAC_OFFSET;
6155
6156         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6157                 mac_offset = BGE_EE_MAC_OFFSET_5906;
6158
6159         return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
6160             ETHER_ADDR_LEN));
6161 }
6162
6163 static int
6164 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
6165 {
6166
6167         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6168                 return (1);
6169
6170         return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
6171            ETHER_ADDR_LEN));
6172 }
6173
6174 static int
6175 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
6176 {
6177         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
6178                 /* NOTE: Order is critical */
6179                 bge_get_eaddr_fw,
6180                 bge_get_eaddr_mem,
6181                 bge_get_eaddr_nvram,
6182                 bge_get_eaddr_eeprom,
6183                 NULL
6184         };
6185         const bge_eaddr_fcn_t *func;
6186
6187         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
6188                 if ((*func)(sc, eaddr) == 0)
6189                         break;
6190         }
6191         return (*func == NULL ? ENXIO : 0);
6192 }