2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet
42 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
45 * frames, highly configurable RX filtering, and 16 RX and TX queues
46 * (which, along with RX filter rules, can be used for QOS applications).
47 * Other features, such as TCP segmentation, may be available as part
48 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
49 * firmware images can be stored in hardware and need not be compiled
52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
55 * The BCM5701 is a single-chip solution incorporating both the BCM5700
56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
57 * does not support external SSRAM.
59 * Broadcom also produces a variation of the BCM5700 under the "Altima"
60 * brand name, which is functionally similar but lacks PCI-X support.
62 * Without external SSRAM, you can only have at most 4 TX rings,
63 * and the use of the mini RX ring is disabled. This seems to imply
64 * that these features are simply not available on the BCM5701. As a
65 * result, this driver does not implement any support for the mini RX
69 #ifdef HAVE_KERNEL_OPTION_HEADERS
70 #include "opt_device_polling.h"
73 #include <sys/param.h>
74 #include <sys/endian.h>
75 #include <sys/systm.h>
76 #include <sys/sockio.h>
78 #include <sys/malloc.h>
79 #include <sys/kernel.h>
80 #include <sys/module.h>
81 #include <sys/socket.h>
82 #include <sys/sysctl.h>
83 #include <sys/taskqueue.h>
86 #include <net/if_var.h>
87 #include <net/if_arp.h>
88 #include <net/ethernet.h>
89 #include <net/if_dl.h>
90 #include <net/if_media.h>
94 #include <net/if_types.h>
95 #include <net/if_vlan_var.h>
97 #include <netinet/in_systm.h>
98 #include <netinet/in.h>
99 #include <netinet/ip.h>
100 #include <netinet/tcp.h>
102 #include <machine/bus.h>
103 #include <machine/resource.h>
105 #include <sys/rman.h>
107 #include <dev/mii/mii.h>
108 #include <dev/mii/miivar.h>
110 #include <dev/mii/brgphyreg.h>
113 #include <dev/ofw/ofw_bus.h>
114 #include <dev/ofw/openfirm.h>
115 #include <machine/ofw_machdep.h>
116 #include <machine/ver.h>
119 #include <dev/pci/pcireg.h>
120 #include <dev/pci/pcivar.h>
122 #include <dev/bge/if_bgereg.h>
124 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP)
125 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
127 MODULE_DEPEND(bge, pci, 1, 1, 1);
128 MODULE_DEPEND(bge, ether, 1, 1, 1);
129 MODULE_DEPEND(bge, miibus, 1, 1, 1);
131 /* "device miibus" required. See GENERIC if you get errors here. */
132 #include "miibus_if.h"
135 * Various supported device vendors/types and their names. Note: the
136 * spec seems to indicate that the hardware still has Alteon's vendor
137 * ID burned into it, though it will always be overriden by the vendor
138 * ID in the EEPROM. Just to be safe, we cover all possibilities.
140 static const struct bge_type {
144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 },
145 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 },
147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 },
148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 },
149 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 },
151 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 },
153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 },
154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 },
155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 },
156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT },
157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X },
158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 },
159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT },
160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X },
161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C },
162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S },
163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT },
164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 },
165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F },
166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K },
167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M },
168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT },
169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C },
170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S },
171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 },
172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S },
173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 },
174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 },
175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 },
176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 },
177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 },
178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 },
179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 },
180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5725 },
181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5727 },
182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 },
183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M },
184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 },
185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F },
186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M },
187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 },
188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M },
189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 },
190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F },
191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M },
192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 },
193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M },
194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 },
195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M },
196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 },
197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 },
198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E },
199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S },
200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE },
201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5762 },
202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 },
203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 },
204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S },
205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 },
206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 },
207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 },
208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F },
209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G },
210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 },
211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 },
212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F },
213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M },
214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 },
215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 },
216 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 },
217 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 },
218 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M },
219 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 },
220 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M },
221 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 },
222 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 },
223 { BCOM_VENDORID, BCOM_DEVICEID_BCM57762 },
224 { BCOM_VENDORID, BCOM_DEVICEID_BCM57764 },
225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 },
226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57766 },
227 { BCOM_VENDORID, BCOM_DEVICEID_BCM57767 },
228 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 },
229 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 },
230 { BCOM_VENDORID, BCOM_DEVICEID_BCM57782 },
231 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 },
232 { BCOM_VENDORID, BCOM_DEVICEID_BCM57786 },
233 { BCOM_VENDORID, BCOM_DEVICEID_BCM57787 },
234 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 },
235 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 },
236 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 },
237 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 },
239 { SK_VENDORID, SK_DEVICEID_ALTIMA },
241 { TC_VENDORID, TC_DEVICEID_3C996 },
243 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 },
244 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 },
245 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 },
250 static const struct bge_vendor {
254 { ALTEON_VENDORID, "Alteon" },
255 { ALTIMA_VENDORID, "Altima" },
256 { APPLE_VENDORID, "Apple" },
257 { BCOM_VENDORID, "Broadcom" },
258 { SK_VENDORID, "SysKonnect" },
259 { TC_VENDORID, "3Com" },
260 { FJTSU_VENDORID, "Fujitsu" },
265 static const struct bge_revision {
268 } bge_revisions[] = {
269 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" },
270 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" },
271 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" },
272 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" },
273 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" },
274 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" },
275 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" },
276 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" },
277 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" },
278 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" },
279 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" },
280 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" },
281 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" },
282 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" },
283 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" },
284 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" },
285 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" },
286 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" },
287 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" },
288 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" },
289 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" },
290 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" },
291 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" },
292 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" },
293 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" },
294 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" },
295 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" },
296 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" },
297 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" },
298 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" },
299 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" },
300 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" },
301 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" },
302 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" },
303 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
304 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
305 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
306 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
307 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
308 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
309 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
310 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
311 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
312 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" },
313 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" },
314 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" },
315 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" },
316 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
317 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
318 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
319 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" },
320 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" },
321 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" },
322 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" },
323 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" },
324 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" },
325 /* 5754 and 5787 share the same ASIC ID */
326 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
327 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
328 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
329 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" },
330 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" },
331 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" },
332 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" },
333 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" },
334 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" },
340 * Some defaults for major revisions, so that newer steppings
341 * that we don't know about have a shot at working.
343 static const struct bge_revision bge_majorrevs[] = {
344 { BGE_ASICREV_BCM5700, "unknown BCM5700" },
345 { BGE_ASICREV_BCM5701, "unknown BCM5701" },
346 { BGE_ASICREV_BCM5703, "unknown BCM5703" },
347 { BGE_ASICREV_BCM5704, "unknown BCM5704" },
348 { BGE_ASICREV_BCM5705, "unknown BCM5705" },
349 { BGE_ASICREV_BCM5750, "unknown BCM5750" },
350 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
351 { BGE_ASICREV_BCM5752, "unknown BCM5752" },
352 { BGE_ASICREV_BCM5780, "unknown BCM5780" },
353 { BGE_ASICREV_BCM5714, "unknown BCM5714" },
354 { BGE_ASICREV_BCM5755, "unknown BCM5755" },
355 { BGE_ASICREV_BCM5761, "unknown BCM5761" },
356 { BGE_ASICREV_BCM5784, "unknown BCM5784" },
357 { BGE_ASICREV_BCM5785, "unknown BCM5785" },
358 /* 5754 and 5787 share the same ASIC ID */
359 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
360 { BGE_ASICREV_BCM5906, "unknown BCM5906" },
361 { BGE_ASICREV_BCM57765, "unknown BCM57765" },
362 { BGE_ASICREV_BCM57766, "unknown BCM57766" },
363 { BGE_ASICREV_BCM57780, "unknown BCM57780" },
364 { BGE_ASICREV_BCM5717, "unknown BCM5717" },
365 { BGE_ASICREV_BCM5719, "unknown BCM5719" },
366 { BGE_ASICREV_BCM5720, "unknown BCM5720" },
367 { BGE_ASICREV_BCM5762, "unknown BCM5762" },
372 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
373 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
374 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
375 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
376 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
377 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
378 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS)
379 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_57765_PLUS)
381 static uint32_t bge_chipid(device_t);
382 static const struct bge_vendor * bge_lookup_vendor(uint16_t);
383 static const struct bge_revision * bge_lookup_rev(uint32_t);
385 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
387 static int bge_probe(device_t);
388 static int bge_attach(device_t);
389 static int bge_detach(device_t);
390 static int bge_suspend(device_t);
391 static int bge_resume(device_t);
392 static void bge_release_resources(struct bge_softc *);
393 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
394 static int bge_dma_alloc(struct bge_softc *);
395 static void bge_dma_free(struct bge_softc *);
396 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t,
397 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
399 static void bge_devinfo(struct bge_softc *);
400 static int bge_mbox_reorder(struct bge_softc *);
402 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
403 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
404 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
405 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
406 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
408 static void bge_txeof(struct bge_softc *, uint16_t);
409 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
410 static int bge_rxeof(struct bge_softc *, uint16_t, int);
412 static void bge_asf_driver_up (struct bge_softc *);
413 static void bge_tick(void *);
414 static void bge_stats_clear_regs(struct bge_softc *);
415 static void bge_stats_update(struct bge_softc *);
416 static void bge_stats_update_regs(struct bge_softc *);
417 static struct mbuf *bge_check_short_dma(struct mbuf *);
418 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
419 uint16_t *, uint16_t *);
420 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
422 static void bge_intr(void *);
423 static int bge_msi_intr(void *);
424 static void bge_intr_task(void *, int);
425 static void bge_start_locked(struct ifnet *);
426 static void bge_start(struct ifnet *);
427 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
428 static void bge_init_locked(struct bge_softc *);
429 static void bge_init(void *);
430 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
431 static void bge_stop(struct bge_softc *);
432 static void bge_watchdog(struct bge_softc *);
433 static int bge_shutdown(device_t);
434 static int bge_ifmedia_upd_locked(struct ifnet *);
435 static int bge_ifmedia_upd(struct ifnet *);
436 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
438 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
439 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
441 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
442 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
444 static void bge_setpromisc(struct bge_softc *);
445 static void bge_setmulti(struct bge_softc *);
446 static void bge_setvlan(struct bge_softc *);
448 static __inline void bge_rxreuse_std(struct bge_softc *, int);
449 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
450 static int bge_newbuf_std(struct bge_softc *, int);
451 static int bge_newbuf_jumbo(struct bge_softc *, int);
452 static int bge_init_rx_ring_std(struct bge_softc *);
453 static void bge_free_rx_ring_std(struct bge_softc *);
454 static int bge_init_rx_ring_jumbo(struct bge_softc *);
455 static void bge_free_rx_ring_jumbo(struct bge_softc *);
456 static void bge_free_tx_ring(struct bge_softc *);
457 static int bge_init_tx_ring(struct bge_softc *);
459 static int bge_chipinit(struct bge_softc *);
460 static int bge_blockinit(struct bge_softc *);
461 static uint32_t bge_dma_swap_options(struct bge_softc *);
463 static int bge_has_eaddr(struct bge_softc *);
464 static uint32_t bge_readmem_ind(struct bge_softc *, int);
465 static void bge_writemem_ind(struct bge_softc *, int, int);
466 static void bge_writembx(struct bge_softc *, int, int);
468 static uint32_t bge_readreg_ind(struct bge_softc *, int);
470 static void bge_writemem_direct(struct bge_softc *, int, int);
471 static void bge_writereg_ind(struct bge_softc *, int, int);
473 static int bge_miibus_readreg(device_t, int, int);
474 static int bge_miibus_writereg(device_t, int, int, int);
475 static void bge_miibus_statchg(device_t);
476 #ifdef DEVICE_POLLING
477 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
480 #define BGE_RESET_SHUTDOWN 0
481 #define BGE_RESET_START 1
482 #define BGE_RESET_SUSPEND 2
483 static void bge_sig_post_reset(struct bge_softc *, int);
484 static void bge_sig_legacy(struct bge_softc *, int);
485 static void bge_sig_pre_reset(struct bge_softc *, int);
486 static void bge_stop_fw(struct bge_softc *);
487 static int bge_reset(struct bge_softc *);
488 static void bge_link_upd(struct bge_softc *);
490 static void bge_ape_lock_init(struct bge_softc *);
491 static void bge_ape_read_fw_ver(struct bge_softc *);
492 static int bge_ape_lock(struct bge_softc *, int);
493 static void bge_ape_unlock(struct bge_softc *, int);
494 static void bge_ape_send_event(struct bge_softc *, uint32_t);
495 static void bge_ape_driver_state_change(struct bge_softc *, int);
498 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may
499 * leak information to untrusted users. It is also known to cause alignment
500 * traps on certain architectures.
502 #ifdef BGE_REGISTER_DEBUG
503 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
504 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
505 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS);
506 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
508 static void bge_add_sysctls(struct bge_softc *);
509 static void bge_add_sysctl_stats_regs(struct bge_softc *,
510 struct sysctl_ctx_list *, struct sysctl_oid_list *);
511 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *,
512 struct sysctl_oid_list *);
513 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
515 static device_method_t bge_methods[] = {
516 /* Device interface */
517 DEVMETHOD(device_probe, bge_probe),
518 DEVMETHOD(device_attach, bge_attach),
519 DEVMETHOD(device_detach, bge_detach),
520 DEVMETHOD(device_shutdown, bge_shutdown),
521 DEVMETHOD(device_suspend, bge_suspend),
522 DEVMETHOD(device_resume, bge_resume),
525 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
526 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
527 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
532 static driver_t bge_driver = {
535 sizeof(struct bge_softc)
538 static devclass_t bge_devclass;
540 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
541 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
543 static int bge_allow_asf = 1;
545 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
547 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
548 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
549 "Allow ASF mode if available");
551 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500"
552 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2"
553 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500"
554 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3"
555 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id"
558 bge_has_eaddr(struct bge_softc *sc)
561 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
568 * The on-board BGEs found in sun4u machines aren't fitted with
569 * an EEPROM which means that we have to obtain the MAC address
570 * via OFW and that some tests will always fail. We distinguish
571 * such BGEs by the subvendor ID, which also has to be obtained
572 * from OFW instead of the PCI configuration space as the latter
573 * indicates Broadcom as the subvendor of the netboot interface.
574 * For early Blade 1500 and 2500 we even have to check the OFW
575 * device path as the subvendor ID always defaults to Broadcom
578 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
579 &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
580 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID))
582 memset(buf, 0, sizeof(buf));
583 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
584 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
585 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
587 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
588 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
596 bge_readmem_ind(struct bge_softc *sc, int off)
601 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
602 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
607 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
608 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
609 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
614 bge_writemem_ind(struct bge_softc *sc, int off, int val)
618 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
619 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
624 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
625 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
626 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
631 bge_readreg_ind(struct bge_softc *sc, int off)
637 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
638 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
643 bge_writereg_ind(struct bge_softc *sc, int off, int val)
649 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
650 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
654 bge_writemem_direct(struct bge_softc *sc, int off, int val)
656 CSR_WRITE_4(sc, off, val);
660 bge_writembx(struct bge_softc *sc, int off, int val)
662 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
663 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
665 CSR_WRITE_4(sc, off, val);
666 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0)
671 * Clear all stale locks and select the lock for this driver instance.
674 bge_ape_lock_init(struct bge_softc *sc)
676 uint32_t bit, regbase;
679 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
680 regbase = BGE_APE_LOCK_GRANT;
682 regbase = BGE_APE_PER_LOCK_GRANT;
684 /* Clear any stale locks. */
685 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
687 case BGE_APE_LOCK_PHY0:
688 case BGE_APE_LOCK_PHY1:
689 case BGE_APE_LOCK_PHY2:
690 case BGE_APE_LOCK_PHY3:
691 bit = BGE_APE_LOCK_GRANT_DRIVER0;
694 if (sc->bge_func_addr == 0)
695 bit = BGE_APE_LOCK_GRANT_DRIVER0;
697 bit = (1 << sc->bge_func_addr);
699 APE_WRITE_4(sc, regbase + 4 * i, bit);
702 /* Select the PHY lock based on the device's function number. */
703 switch (sc->bge_func_addr) {
705 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
708 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
711 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
714 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
717 device_printf(sc->bge_dev,
718 "PHY lock not supported on this function\n");
723 * Check for APE firmware, set flags, and print version info.
726 bge_ape_read_fw_ver(struct bge_softc *sc)
729 uint32_t apedata, features;
731 /* Check for a valid APE signature in shared memory. */
732 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
733 if (apedata != BGE_APE_SEG_SIG_MAGIC) {
734 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE;
738 /* Check if APE firmware is running. */
739 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
740 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) {
741 device_printf(sc->bge_dev, "APE signature found "
742 "but FW status not ready! 0x%08x\n", apedata);
746 sc->bge_mfw_flags |= BGE_MFW_ON_APE;
748 /* Fetch the APE firwmare type and version. */
749 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
750 features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
751 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) {
752 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
754 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) {
755 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
760 /* Print the APE firmware version. */
761 device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n",
763 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT,
764 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT,
765 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT,
766 (apedata & BGE_APE_FW_VERSION_BLDMSK));
770 bge_ape_lock(struct bge_softc *sc, int locknum)
772 uint32_t bit, gnt, req, status;
775 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
778 /* Lock request/grant registers have different bases. */
779 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) {
780 req = BGE_APE_LOCK_REQ;
781 gnt = BGE_APE_LOCK_GRANT;
783 req = BGE_APE_PER_LOCK_REQ;
784 gnt = BGE_APE_PER_LOCK_GRANT;
790 case BGE_APE_LOCK_GPIO:
791 /* Lock required when using GPIO. */
792 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
794 if (sc->bge_func_addr == 0)
795 bit = BGE_APE_LOCK_REQ_DRIVER0;
797 bit = (1 << sc->bge_func_addr);
799 case BGE_APE_LOCK_GRC:
800 /* Lock required to reset the device. */
801 if (sc->bge_func_addr == 0)
802 bit = BGE_APE_LOCK_REQ_DRIVER0;
804 bit = (1 << sc->bge_func_addr);
806 case BGE_APE_LOCK_MEM:
807 /* Lock required when accessing certain APE memory. */
808 if (sc->bge_func_addr == 0)
809 bit = BGE_APE_LOCK_REQ_DRIVER0;
811 bit = (1 << sc->bge_func_addr);
813 case BGE_APE_LOCK_PHY0:
814 case BGE_APE_LOCK_PHY1:
815 case BGE_APE_LOCK_PHY2:
816 case BGE_APE_LOCK_PHY3:
817 /* Lock required when accessing PHYs. */
818 bit = BGE_APE_LOCK_REQ_DRIVER0;
824 /* Request a lock. */
825 APE_WRITE_4(sc, req + off, bit);
827 /* Wait up to 1 second to acquire lock. */
828 for (i = 0; i < 20000; i++) {
829 status = APE_READ_4(sc, gnt + off);
835 /* Handle any errors. */
837 device_printf(sc->bge_dev, "APE lock %d request failed! "
838 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
839 locknum, req + off, bit & 0xFFFF, gnt + off,
841 /* Revoke the lock request. */
842 APE_WRITE_4(sc, gnt + off, bit);
850 bge_ape_unlock(struct bge_softc *sc, int locknum)
855 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
858 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
859 gnt = BGE_APE_LOCK_GRANT;
861 gnt = BGE_APE_PER_LOCK_GRANT;
866 case BGE_APE_LOCK_GPIO:
867 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
869 if (sc->bge_func_addr == 0)
870 bit = BGE_APE_LOCK_GRANT_DRIVER0;
872 bit = (1 << sc->bge_func_addr);
874 case BGE_APE_LOCK_GRC:
875 if (sc->bge_func_addr == 0)
876 bit = BGE_APE_LOCK_GRANT_DRIVER0;
878 bit = (1 << sc->bge_func_addr);
880 case BGE_APE_LOCK_MEM:
881 if (sc->bge_func_addr == 0)
882 bit = BGE_APE_LOCK_GRANT_DRIVER0;
884 bit = (1 << sc->bge_func_addr);
886 case BGE_APE_LOCK_PHY0:
887 case BGE_APE_LOCK_PHY1:
888 case BGE_APE_LOCK_PHY2:
889 case BGE_APE_LOCK_PHY3:
890 bit = BGE_APE_LOCK_GRANT_DRIVER0;
896 APE_WRITE_4(sc, gnt + off, bit);
900 * Send an event to the APE firmware.
903 bge_ape_send_event(struct bge_softc *sc, uint32_t event)
908 /* NCSI does not support APE events. */
909 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
912 /* Wait up to 1ms for APE to service previous event. */
913 for (i = 10; i > 0; i--) {
914 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
916 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
917 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) {
918 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
919 BGE_APE_EVENT_STATUS_EVENT_PENDING);
920 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
921 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
924 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
928 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n",
933 bge_ape_driver_state_change(struct bge_softc *sc, int kind)
935 uint32_t apedata, event;
937 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
941 case BGE_RESET_START:
942 /* If this is the first load, clear the load counter. */
943 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
944 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC)
945 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
947 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
948 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
950 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
951 BGE_APE_HOST_SEG_SIG_MAGIC);
952 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
953 BGE_APE_HOST_SEG_LEN_MAGIC);
955 /* Add some version info if bge(4) supports it. */
956 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
957 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0));
958 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
959 BGE_APE_HOST_BEHAV_NO_PHYLOCK);
960 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
961 BGE_APE_HOST_HEARTBEAT_INT_DISABLE);
962 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
963 BGE_APE_HOST_DRVR_STATE_START);
964 event = BGE_APE_EVENT_STATUS_STATE_START;
966 case BGE_RESET_SHUTDOWN:
967 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
968 BGE_APE_HOST_DRVR_STATE_UNLOAD);
969 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
971 case BGE_RESET_SUSPEND:
972 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
978 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
979 BGE_APE_EVENT_STATUS_STATE_CHNGE);
983 * Map a single buffer address.
987 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
989 struct bge_dmamap_arg *ctx;
994 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
997 ctx->bge_busaddr = segs->ds_addr;
1001 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1003 uint32_t access, byte = 0;
1007 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
1008 for (i = 0; i < 8000; i++) {
1009 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
1016 /* Enable access. */
1017 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
1018 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
1020 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
1021 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
1022 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
1024 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
1030 if (i == BGE_TIMEOUT * 10) {
1031 if_printf(sc->bge_ifp, "nvram read timed out\n");
1036 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
1038 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
1040 /* Disable access. */
1041 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
1044 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
1045 CSR_READ_4(sc, BGE_NVRAM_SWARB);
1051 * Read a sequence of bytes from NVRAM.
1054 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1059 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1062 for (i = 0; i < cnt; i++) {
1063 err = bge_nvram_getbyte(sc, off + i, &byte);
1069 return (err ? 1 : 0);
1073 * Read a byte of data stored in the EEPROM at address 'addr.' The
1074 * BCM570x supports both the traditional bitbang interface and an
1075 * auto access interface for reading the EEPROM. We use the auto
1079 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1085 * Enable use of auto EEPROM access so we can avoid
1086 * having to use the bitbang method.
1088 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
1090 /* Reset the EEPROM, load the clock period. */
1091 CSR_WRITE_4(sc, BGE_EE_ADDR,
1092 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
1095 /* Issue the read EEPROM command. */
1096 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
1098 /* Wait for completion */
1099 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
1101 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1105 if (i == BGE_TIMEOUT * 10) {
1106 device_printf(sc->bge_dev, "EEPROM read timed out\n");
1111 byte = CSR_READ_4(sc, BGE_EE_DATA);
1113 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
1119 * Read a sequence of bytes from the EEPROM.
1122 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1127 for (i = 0; i < cnt; i++) {
1128 error = bge_eeprom_getbyte(sc, off + i, &byte);
1134 return (error ? 1 : 0);
1138 bge_miibus_readreg(device_t dev, int phy, int reg)
1140 struct bge_softc *sc;
1144 sc = device_get_softc(dev);
1146 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1149 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1150 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1151 CSR_WRITE_4(sc, BGE_MI_MODE,
1152 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1156 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
1157 BGE_MIPHY(phy) | BGE_MIREG(reg));
1159 /* Poll for the PHY register access to complete. */
1160 for (i = 0; i < BGE_TIMEOUT; i++) {
1162 val = CSR_READ_4(sc, BGE_MI_COMM);
1163 if ((val & BGE_MICOMM_BUSY) == 0) {
1165 val = CSR_READ_4(sc, BGE_MI_COMM);
1170 if (i == BGE_TIMEOUT) {
1171 device_printf(sc->bge_dev,
1172 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
1177 /* Restore the autopoll bit if necessary. */
1178 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1179 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1183 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1185 if (val & BGE_MICOMM_READFAIL)
1188 return (val & 0xFFFF);
1192 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
1194 struct bge_softc *sc;
1197 sc = device_get_softc(dev);
1199 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1200 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
1203 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1206 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1207 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1208 CSR_WRITE_4(sc, BGE_MI_MODE,
1209 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1213 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
1214 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
1216 for (i = 0; i < BGE_TIMEOUT; i++) {
1218 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
1220 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
1225 /* Restore the autopoll bit if necessary. */
1226 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1227 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1231 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1233 if (i == BGE_TIMEOUT)
1234 device_printf(sc->bge_dev,
1235 "PHY write timed out (phy %d, reg %d, val 0x%04x)\n",
1242 bge_miibus_statchg(device_t dev)
1244 struct bge_softc *sc;
1245 struct mii_data *mii;
1246 uint32_t mac_mode, rx_mode, tx_mode;
1248 sc = device_get_softc(dev);
1249 if ((sc->bge_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1251 mii = device_get_softc(sc->bge_miibus);
1253 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1254 (IFM_ACTIVE | IFM_AVALID)) {
1255 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1263 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1274 if (sc->bge_link == 0)
1278 * APE firmware touches these registers to keep the MAC
1279 * connected to the outside world. Try to keep the
1283 /* Set the port mode (MII/GMII) to match the link speed. */
1284 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
1285 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
1286 tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
1287 rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
1289 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1290 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
1291 mac_mode |= BGE_PORTMODE_GMII;
1293 mac_mode |= BGE_PORTMODE_MII;
1295 /* Set MAC flow control behavior to match link flow control settings. */
1296 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE;
1297 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE;
1298 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1299 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1300 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE;
1301 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1302 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE;
1304 mac_mode |= BGE_MACMODE_HALF_DUPLEX;
1306 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
1308 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
1309 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
1313 * Intialize a standard receive ring descriptor.
1316 bge_newbuf_std(struct bge_softc *sc, int i)
1319 struct bge_rx_bd *r;
1320 bus_dma_segment_t segs[1];
1324 if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
1325 (sc->bge_ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN +
1326 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) {
1327 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1330 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1332 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1335 m->m_len = m->m_pkthdr.len = MCLBYTES;
1337 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1338 m_adj(m, ETHER_ALIGN);
1340 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
1341 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
1346 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1347 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1348 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
1349 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1350 sc->bge_cdata.bge_rx_std_dmamap[i]);
1352 map = sc->bge_cdata.bge_rx_std_dmamap[i];
1353 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
1354 sc->bge_cdata.bge_rx_std_sparemap = map;
1355 sc->bge_cdata.bge_rx_std_chain[i] = m;
1356 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
1357 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
1358 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1359 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1360 r->bge_flags = BGE_RXBDFLAG_END;
1361 r->bge_len = segs[0].ds_len;
1364 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1365 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
1371 * Initialize a jumbo receive ring descriptor. This allocates
1372 * a jumbo buffer from the pool managed internally by the driver.
1375 bge_newbuf_jumbo(struct bge_softc *sc, int i)
1377 bus_dma_segment_t segs[BGE_NSEG_JUMBO];
1379 struct bge_extrx_bd *r;
1383 MGETHDR(m, M_NOWAIT, MT_DATA);
1387 m_cljget(m, M_NOWAIT, MJUM9BYTES);
1388 if (!(m->m_flags & M_EXT)) {
1392 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1393 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1394 m_adj(m, ETHER_ALIGN);
1396 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1397 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1403 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1404 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1405 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1406 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1407 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1409 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1410 sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1411 sc->bge_cdata.bge_rx_jumbo_sparemap;
1412 sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1413 sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1414 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1415 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1416 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1417 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1420 * Fill in the extended RX buffer descriptor.
1422 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1423 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1425 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1428 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1429 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1430 r->bge_len3 = segs[3].ds_len;
1431 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1433 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1434 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1435 r->bge_len2 = segs[2].ds_len;
1436 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1438 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1439 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1440 r->bge_len1 = segs[1].ds_len;
1441 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1443 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1444 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1445 r->bge_len0 = segs[0].ds_len;
1446 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1449 panic("%s: %d segments\n", __func__, nsegs);
1452 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1453 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1459 bge_init_rx_ring_std(struct bge_softc *sc)
1463 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1465 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1466 if ((error = bge_newbuf_std(sc, i)) != 0)
1468 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1471 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1472 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1475 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1481 bge_free_rx_ring_std(struct bge_softc *sc)
1485 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1486 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1487 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1488 sc->bge_cdata.bge_rx_std_dmamap[i],
1489 BUS_DMASYNC_POSTREAD);
1490 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1491 sc->bge_cdata.bge_rx_std_dmamap[i]);
1492 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1493 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1495 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1496 sizeof(struct bge_rx_bd));
1501 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1503 struct bge_rcb *rcb;
1506 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1508 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1509 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1511 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1514 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1515 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1519 /* Enable the jumbo receive producer ring. */
1520 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1521 rcb->bge_maxlen_flags =
1522 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD);
1523 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1525 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1531 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1535 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1536 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1537 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1538 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1539 BUS_DMASYNC_POSTREAD);
1540 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1541 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1542 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1543 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1545 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1546 sizeof(struct bge_extrx_bd));
1551 bge_free_tx_ring(struct bge_softc *sc)
1555 if (sc->bge_ldata.bge_tx_ring == NULL)
1558 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1559 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1560 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1561 sc->bge_cdata.bge_tx_dmamap[i],
1562 BUS_DMASYNC_POSTWRITE);
1563 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1564 sc->bge_cdata.bge_tx_dmamap[i]);
1565 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1566 sc->bge_cdata.bge_tx_chain[i] = NULL;
1568 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1569 sizeof(struct bge_tx_bd));
1574 bge_init_tx_ring(struct bge_softc *sc)
1577 sc->bge_tx_saved_considx = 0;
1579 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1580 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1581 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1583 /* Initialize transmit producer index for host-memory send ring. */
1584 sc->bge_tx_prodidx = 0;
1585 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1587 /* 5700 b2 errata */
1588 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1589 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1591 /* NIC-memory send ring not used; initialize to zero. */
1592 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1593 /* 5700 b2 errata */
1594 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1595 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1601 bge_setpromisc(struct bge_softc *sc)
1605 BGE_LOCK_ASSERT(sc);
1609 /* Enable or disable promiscuous mode as needed. */
1610 if (ifp->if_flags & IFF_PROMISC)
1611 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1613 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1617 bge_setmulti(struct bge_softc *sc)
1620 struct ifmultiaddr *ifma;
1621 uint32_t hashes[4] = { 0, 0, 0, 0 };
1624 BGE_LOCK_ASSERT(sc);
1628 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1629 for (i = 0; i < 4; i++)
1630 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1634 /* First, zot all the existing filters. */
1635 for (i = 0; i < 4; i++)
1636 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1638 /* Now program new ones. */
1639 if_maddr_rlock(ifp);
1640 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1641 if (ifma->ifma_addr->sa_family != AF_LINK)
1643 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1644 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1645 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1647 if_maddr_runlock(ifp);
1649 for (i = 0; i < 4; i++)
1650 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1654 bge_setvlan(struct bge_softc *sc)
1658 BGE_LOCK_ASSERT(sc);
1662 /* Enable or disable VLAN tag stripping as needed. */
1663 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1664 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1666 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1670 bge_sig_pre_reset(struct bge_softc *sc, int type)
1674 * Some chips don't like this so only do this if ASF is enabled
1676 if (sc->bge_asf_mode)
1677 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
1679 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1681 case BGE_RESET_START:
1682 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1683 BGE_FW_DRV_STATE_START);
1685 case BGE_RESET_SHUTDOWN:
1686 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1687 BGE_FW_DRV_STATE_UNLOAD);
1689 case BGE_RESET_SUSPEND:
1690 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1691 BGE_FW_DRV_STATE_SUSPEND);
1696 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
1697 bge_ape_driver_state_change(sc, type);
1701 bge_sig_post_reset(struct bge_softc *sc, int type)
1704 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1706 case BGE_RESET_START:
1707 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1708 BGE_FW_DRV_STATE_START_DONE);
1711 case BGE_RESET_SHUTDOWN:
1712 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1713 BGE_FW_DRV_STATE_UNLOAD_DONE);
1717 if (type == BGE_RESET_SHUTDOWN)
1718 bge_ape_driver_state_change(sc, type);
1722 bge_sig_legacy(struct bge_softc *sc, int type)
1725 if (sc->bge_asf_mode) {
1727 case BGE_RESET_START:
1728 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1729 BGE_FW_DRV_STATE_START);
1731 case BGE_RESET_SHUTDOWN:
1732 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1733 BGE_FW_DRV_STATE_UNLOAD);
1740 bge_stop_fw(struct bge_softc *sc)
1744 if (sc->bge_asf_mode) {
1745 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
1746 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
1747 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
1749 for (i = 0; i < 100; i++ ) {
1750 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1751 BGE_RX_CPU_DRV_EVENT))
1759 bge_dma_swap_options(struct bge_softc *sc)
1761 uint32_t dma_options;
1763 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
1764 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
1765 #if BYTE_ORDER == BIG_ENDIAN
1766 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
1768 return (dma_options);
1772 * Do endian, PCI and DMA initialization.
1775 bge_chipinit(struct bge_softc *sc)
1777 uint32_t dma_rw_ctl, misc_ctl, mode_ctl;
1781 /* Set endianness before we access any non-PCI registers. */
1782 misc_ctl = BGE_INIT;
1783 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1784 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1785 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1788 * Clear the MAC statistics block in the NIC's
1791 for (i = BGE_STATS_BLOCK;
1792 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1793 BGE_MEMWIN_WRITE(sc, i, 0);
1795 for (i = BGE_STATUS_BLOCK;
1796 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1797 BGE_MEMWIN_WRITE(sc, i, 0);
1799 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1801 * Fix data corruption caused by non-qword write with WB.
1802 * Fix master abort in PCI mode.
1803 * Fix PCI latency timer.
1805 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1806 val |= (1 << 10) | (1 << 12) | (1 << 13);
1807 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1810 if (sc->bge_asicrev == BGE_ASICREV_BCM57765 ||
1811 sc->bge_asicrev == BGE_ASICREV_BCM57766) {
1813 * For the 57766 and non Ax versions of 57765, bootcode
1814 * needs to setup the PCIE Fast Training Sequence (FTS)
1815 * value to prevent transmit hangs.
1817 if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) {
1818 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL,
1819 CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) |
1820 BGE_CPMU_PADRNG_CTL_RDIV2);
1825 * Set up the PCI DMA control register.
1827 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1828 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1829 if (sc->bge_flags & BGE_FLAG_PCIE) {
1830 if (sc->bge_mps >= 256)
1831 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1833 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1834 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1835 if (BGE_IS_5714_FAMILY(sc)) {
1836 /* 256 bytes for read and write. */
1837 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1838 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1839 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1840 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1841 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1842 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1844 * In the BCM5703, the DMA read watermark should
1845 * be set to less than or equal to the maximum
1846 * memory read byte count of the PCI-X command
1849 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1850 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1851 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1852 /* 1536 bytes for read, 384 bytes for write. */
1853 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1854 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1856 /* 384 bytes for read and write. */
1857 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1858 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1861 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1862 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1865 /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1866 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1867 if (tmp == 6 || tmp == 7)
1869 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1871 /* Set PCI-X DMA write workaround. */
1872 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1875 /* Conventional PCI bus: 256 bytes for read and write. */
1876 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1877 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1879 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1880 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1883 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1884 sc->bge_asicrev == BGE_ASICREV_BCM5701)
1885 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1886 BGE_PCIDMARWCTL_ASRT_ALL_BE;
1887 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1888 sc->bge_asicrev == BGE_ASICREV_BCM5704)
1889 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1890 if (BGE_IS_5717_PLUS(sc)) {
1891 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1892 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
1893 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1895 * Enable HW workaround for controllers that misinterpret
1896 * a status tag update and leave interrupts permanently
1899 if (!BGE_IS_57765_PLUS(sc) &&
1900 sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
1901 sc->bge_asicrev != BGE_ASICREV_BCM5762)
1902 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1904 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1907 * Set up general mode register.
1909 mode_ctl = bge_dma_swap_options(sc);
1910 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
1911 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
1912 /* Retain Host-2-BMC settings written by APE firmware. */
1913 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
1914 (BGE_MODECTL_BYTESWAP_B2HRX_DATA |
1915 BGE_MODECTL_WORDSWAP_B2HRX_DATA |
1916 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE);
1918 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1919 BGE_MODECTL_TX_NO_PHDR_CSUM;
1922 * BCM5701 B5 have a bug causing data corruption when using
1923 * 64-bit DMA reads, which can be terminated early and then
1924 * completed later as 32-bit accesses, in combination with
1927 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1928 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1929 mode_ctl |= BGE_MODECTL_FORCE_PCI32;
1932 * Tell the firmware the driver is running
1934 if (sc->bge_asf_mode & ASF_STACKUP)
1935 mode_ctl |= BGE_MODECTL_STACKUP;
1937 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1940 * Disable memory write invalidate. Apparently it is not supported
1941 * properly by these devices. Also ensure that INTx isn't disabled,
1942 * as these chips need it even when using MSI.
1944 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1945 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
1947 /* Set the timer prescaler (always 66 MHz). */
1948 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1950 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1951 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1952 DELAY(40); /* XXX */
1954 /* Put PHY into ready state */
1955 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1956 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1964 bge_blockinit(struct bge_softc *sc)
1966 struct bge_rcb *rcb;
1969 uint32_t dmactl, rdmareg, val;
1973 * Initialize the memory window pointer register so that
1974 * we can access the first 32K of internal NIC RAM. This will
1975 * allow us to set up the TX send ring RCBs and the RX return
1976 * ring RCBs, plus other things which live in NIC memory.
1978 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1980 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1982 if (!(BGE_IS_5705_PLUS(sc))) {
1983 /* Configure mbuf memory pool */
1984 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1985 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1986 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1988 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1990 /* Configure DMA resource pool */
1991 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1992 BGE_DMA_DESCRIPTORS);
1993 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1996 /* Configure mbuf pool watermarks */
1997 if (BGE_IS_5717_PLUS(sc)) {
1998 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1999 if (sc->bge_ifp->if_mtu > ETHERMTU) {
2000 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
2001 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
2003 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
2004 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
2006 } else if (!BGE_IS_5705_PLUS(sc)) {
2007 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
2008 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
2009 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2010 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2011 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2012 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
2013 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
2015 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2016 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
2017 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2020 /* Configure DMA resource watermarks */
2021 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
2022 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
2024 /* Enable buffer manager */
2025 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
2027 * Change the arbitration algorithm of TXMBUF read request to
2028 * round-robin instead of priority based for BCM5719. When
2029 * TXFIFO is almost empty, RDMA will hold its request until
2030 * TXFIFO is not almost empty.
2032 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2033 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
2034 CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
2036 /* Poll for buffer manager start indication */
2037 for (i = 0; i < BGE_TIMEOUT; i++) {
2039 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
2043 if (i == BGE_TIMEOUT) {
2044 device_printf(sc->bge_dev, "buffer manager failed to start\n");
2048 /* Enable flow-through queues */
2049 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2050 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2052 /* Wait until queue initialization is complete */
2053 for (i = 0; i < BGE_TIMEOUT; i++) {
2055 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
2059 if (i == BGE_TIMEOUT) {
2060 device_printf(sc->bge_dev, "flow-through queue init failed\n");
2065 * Summary of rings supported by the controller:
2067 * Standard Receive Producer Ring
2068 * - This ring is used to feed receive buffers for "standard"
2069 * sized frames (typically 1536 bytes) to the controller.
2071 * Jumbo Receive Producer Ring
2072 * - This ring is used to feed receive buffers for jumbo sized
2073 * frames (i.e. anything bigger than the "standard" frames)
2074 * to the controller.
2076 * Mini Receive Producer Ring
2077 * - This ring is used to feed receive buffers for "mini"
2078 * sized frames to the controller.
2079 * - This feature required external memory for the controller
2080 * but was never used in a production system. Should always
2083 * Receive Return Ring
2084 * - After the controller has placed an incoming frame into a
2085 * receive buffer that buffer is moved into a receive return
2086 * ring. The driver is then responsible to passing the
2087 * buffer up to the stack. Many versions of the controller
2088 * support multiple RR rings.
2091 * - This ring is used for outgoing frames. Many versions of
2092 * the controller support multiple send rings.
2095 /* Initialize the standard receive producer ring control block. */
2096 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
2097 rcb->bge_hostaddr.bge_addr_lo =
2098 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
2099 rcb->bge_hostaddr.bge_addr_hi =
2100 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
2101 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2102 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
2103 if (BGE_IS_5717_PLUS(sc)) {
2105 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
2106 * Bits 15-2 : Maximum RX frame size
2107 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled
2110 rcb->bge_maxlen_flags =
2111 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
2112 } else if (BGE_IS_5705_PLUS(sc)) {
2114 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
2115 * Bits 15-2 : Reserved (should be 0)
2116 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
2119 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
2122 * Ring size is always XXX entries
2123 * Bits 31-16: Maximum RX frame size
2124 * Bits 15-2 : Reserved (should be 0)
2125 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
2128 rcb->bge_maxlen_flags =
2129 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
2131 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2132 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2133 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2134 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
2136 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
2137 /* Write the standard receive producer ring control block. */
2138 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
2139 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
2140 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
2141 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
2143 /* Reset the standard receive producer ring producer index. */
2144 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
2147 * Initialize the jumbo RX producer ring control
2148 * block. We set the 'ring disabled' bit in the
2149 * flags field until we're actually ready to start
2150 * using this ring (i.e. once we set the MTU
2151 * high enough to require it).
2153 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2154 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
2155 /* Get the jumbo receive producer ring RCB parameters. */
2156 rcb->bge_hostaddr.bge_addr_lo =
2157 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2158 rcb->bge_hostaddr.bge_addr_hi =
2159 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2160 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2161 sc->bge_cdata.bge_rx_jumbo_ring_map,
2162 BUS_DMASYNC_PREREAD);
2163 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
2164 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
2165 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2166 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2167 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2168 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
2170 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
2171 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
2172 rcb->bge_hostaddr.bge_addr_hi);
2173 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
2174 rcb->bge_hostaddr.bge_addr_lo);
2175 /* Program the jumbo receive producer ring RCB parameters. */
2176 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
2177 rcb->bge_maxlen_flags);
2178 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
2179 /* Reset the jumbo receive producer ring producer index. */
2180 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
2183 /* Disable the mini receive producer ring RCB. */
2184 if (BGE_IS_5700_FAMILY(sc)) {
2185 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
2186 rcb->bge_maxlen_flags =
2187 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
2188 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
2189 rcb->bge_maxlen_flags);
2190 /* Reset the mini receive producer ring producer index. */
2191 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
2194 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
2195 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2196 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
2197 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
2198 sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
2199 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
2200 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
2203 * The BD ring replenish thresholds control how often the
2204 * hardware fetches new BD's from the producer rings in host
2205 * memory. Setting the value too low on a busy system can
2206 * starve the hardware and recue the throughpout.
2208 * Set the BD ring replentish thresholds. The recommended
2209 * values are 1/8th the number of descriptors allocated to
2211 * XXX The 5754 requires a lower threshold, so it might be a
2212 * requirement of all 575x family chips. The Linux driver sets
2213 * the lower threshold for all 5705 family chips as well, but there
2214 * are reports that it might not need to be so strict.
2216 * XXX Linux does some extra fiddling here for the 5906 parts as
2219 if (BGE_IS_5705_PLUS(sc))
2222 val = BGE_STD_RX_RING_CNT / 8;
2223 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
2224 if (BGE_IS_JUMBO_CAPABLE(sc))
2225 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
2226 BGE_JUMBO_RX_RING_CNT/8);
2227 if (BGE_IS_5717_PLUS(sc)) {
2228 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
2229 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
2233 * Disable all send rings by setting the 'ring disabled' bit
2234 * in the flags field of all the TX send ring control blocks,
2235 * located in NIC memory.
2237 if (!BGE_IS_5705_PLUS(sc))
2238 /* 5700 to 5704 had 16 send rings. */
2239 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
2240 else if (BGE_IS_57765_PLUS(sc) ||
2241 sc->bge_asicrev == BGE_ASICREV_BCM5762)
2243 else if (BGE_IS_5717_PLUS(sc))
2247 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2248 for (i = 0; i < limit; i++) {
2249 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2250 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
2251 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2252 vrcb += sizeof(struct bge_rcb);
2255 /* Configure send ring RCB 0 (we use only the first ring) */
2256 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2257 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
2258 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2259 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2260 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2261 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2262 sc->bge_asicrev == BGE_ASICREV_BCM5720)
2263 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
2265 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
2266 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
2267 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2268 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
2271 * Disable all receive return rings by setting the
2272 * 'ring diabled' bit in the flags field of all the receive
2273 * return ring control blocks, located in NIC memory.
2275 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2276 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2277 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2278 /* Should be 17, use 16 until we get an SRAM map. */
2280 } else if (!BGE_IS_5705_PLUS(sc))
2281 limit = BGE_RX_RINGS_MAX;
2282 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2283 sc->bge_asicrev == BGE_ASICREV_BCM5762 ||
2284 BGE_IS_57765_PLUS(sc))
2288 /* Disable all receive return rings. */
2289 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2290 for (i = 0; i < limit; i++) {
2291 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
2292 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
2293 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2294 BGE_RCB_FLAG_RING_DISABLED);
2295 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2296 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
2297 (i * (sizeof(uint64_t))), 0);
2298 vrcb += sizeof(struct bge_rcb);
2302 * Set up receive return ring 0. Note that the NIC address
2303 * for RX return rings is 0x0. The return rings live entirely
2304 * within the host, so the nicaddr field in the RCB isn't used.
2306 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2307 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
2308 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2309 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2310 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2311 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2312 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
2314 /* Set random backoff seed for TX */
2315 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
2316 (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
2317 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
2318 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) &
2319 BGE_TX_BACKOFF_SEED_MASK);
2321 /* Set inter-packet gap */
2323 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2324 sc->bge_asicrev == BGE_ASICREV_BCM5762)
2325 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
2326 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
2327 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
2330 * Specify which ring to use for packets that don't match
2333 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
2336 * Configure number of RX lists. One interrupt distribution
2337 * list, sixteen active lists, one bad frames class.
2339 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
2341 /* Inialize RX list placement stats mask. */
2342 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
2343 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
2345 /* Disable host coalescing until we get it set up */
2346 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
2348 /* Poll to make sure it's shut down. */
2349 for (i = 0; i < BGE_TIMEOUT; i++) {
2351 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
2355 if (i == BGE_TIMEOUT) {
2356 device_printf(sc->bge_dev,
2357 "host coalescing engine failed to idle\n");
2361 /* Set up host coalescing defaults */
2362 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
2363 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
2364 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
2365 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
2366 if (!(BGE_IS_5705_PLUS(sc))) {
2367 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
2368 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
2370 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
2371 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
2373 /* Set up address of statistics block */
2374 if (!(BGE_IS_5705_PLUS(sc))) {
2375 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
2376 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
2377 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
2378 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
2379 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
2380 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
2381 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
2384 /* Set up address of status block */
2385 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
2386 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
2387 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
2388 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
2390 /* Set up status block size. */
2391 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2392 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
2393 val = BGE_STATBLKSZ_FULL;
2394 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2396 val = BGE_STATBLKSZ_32BYTE;
2397 bzero(sc->bge_ldata.bge_status_block, 32);
2399 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2400 sc->bge_cdata.bge_status_map,
2401 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2403 /* Turn on host coalescing state machine */
2404 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2406 /* Turn on RX BD completion state machine and enable attentions */
2407 CSR_WRITE_4(sc, BGE_RBDC_MODE,
2408 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
2410 /* Turn on RX list placement state machine */
2411 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2413 /* Turn on RX list selector state machine. */
2414 if (!(BGE_IS_5705_PLUS(sc)))
2415 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2417 /* Turn on DMA, clear stats. */
2418 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
2419 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
2420 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
2421 BGE_MACMODE_FRMHDR_DMA_ENB;
2423 if (sc->bge_flags & BGE_FLAG_TBI)
2424 val |= BGE_PORTMODE_TBI;
2425 else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
2426 val |= BGE_PORTMODE_GMII;
2428 val |= BGE_PORTMODE_MII;
2430 /* Allow APE to send/receive frames. */
2431 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
2432 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
2434 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
2437 /* Set misc. local control, enable interrupts on attentions */
2438 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2441 /* Assert GPIO pins for PHY reset */
2442 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
2443 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
2444 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
2445 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
2448 /* Turn on DMA completion state machine */
2449 if (!(BGE_IS_5705_PLUS(sc)))
2450 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2452 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
2454 /* Enable host coalescing bug fix. */
2455 if (BGE_IS_5755_PLUS(sc))
2456 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
2458 /* Request larger DMA burst size to get better performance. */
2459 if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
2460 val |= BGE_WDMAMODE_BURST_ALL_DATA;
2462 /* Turn on write DMA state machine */
2463 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
2466 /* Turn on read DMA state machine */
2467 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
2469 if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
2470 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
2472 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2473 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2474 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2475 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
2476 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
2477 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
2478 if (sc->bge_flags & BGE_FLAG_PCIE)
2479 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2480 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2481 val |= BGE_RDMAMODE_TSO4_ENABLE;
2482 if (sc->bge_flags & BGE_FLAG_TSO3 ||
2483 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2484 sc->bge_asicrev == BGE_ASICREV_BCM57780)
2485 val |= BGE_RDMAMODE_TSO6_ENABLE;
2488 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2489 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2490 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
2491 BGE_RDMAMODE_H2BNC_VLAN_DET;
2493 * Allow multiple outstanding read requests from
2494 * non-LSO read DMA engine.
2496 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
2499 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2500 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2501 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2502 sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2503 BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) {
2504 if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
2505 rdmareg = BGE_RDMA_RSRVCTRL_REG2;
2507 rdmareg = BGE_RDMA_RSRVCTRL;
2508 dmactl = CSR_READ_4(sc, rdmareg);
2510 * Adjust tx margin to prevent TX data corruption and
2511 * fix internal FIFO overflow.
2513 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 ||
2514 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2515 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2516 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2517 BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2518 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2519 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2520 BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2523 * Enable fix for read DMA FIFO overruns.
2524 * The fix is to limit the number of RX BDs
2525 * the hardware would fetch at a fime.
2527 CSR_WRITE_4(sc, rdmareg, dmactl |
2528 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2531 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2532 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2533 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2534 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2535 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2536 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2538 * Allow 4KB burst length reads for non-LSO frames.
2539 * Enable 512B burst length reads for buffer descriptors.
2541 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2542 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2543 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
2544 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2545 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2546 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2,
2547 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |
2548 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2549 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2552 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2555 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
2556 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) {
2557 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);
2558 if ((val & 0xFFFF) > BGE_FRAMELEN)
2560 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN)
2563 if (i != BGE_NUM_RDMA_CHANNELS / 2) {
2564 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
2565 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2566 val |= BGE_RDMA_TX_LENGTH_WA_5719;
2568 val |= BGE_RDMA_TX_LENGTH_WA_5720;
2569 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
2573 /* Turn on RX data completion state machine */
2574 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2576 /* Turn on RX BD initiator state machine */
2577 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2579 /* Turn on RX data and RX BD initiator state machine */
2580 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2582 /* Turn on Mbuf cluster free state machine */
2583 if (!(BGE_IS_5705_PLUS(sc)))
2584 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2586 /* Turn on send BD completion state machine */
2587 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2589 /* Turn on send data completion state machine */
2590 val = BGE_SDCMODE_ENABLE;
2591 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2592 val |= BGE_SDCMODE_CDELAY;
2593 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2595 /* Turn on send data initiator state machine */
2596 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2597 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2598 BGE_SDIMODE_HW_LSO_PRE_DMA);
2600 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2602 /* Turn on send BD initiator state machine */
2603 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2605 /* Turn on send BD selector state machine */
2606 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2608 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
2609 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
2610 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
2612 /* ack/clear link change events */
2613 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2614 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2615 BGE_MACSTAT_LINK_CHANGED);
2616 CSR_WRITE_4(sc, BGE_MI_STS, 0);
2619 * Enable attention when the link has changed state for
2620 * devices that use auto polling.
2622 if (sc->bge_flags & BGE_FLAG_TBI) {
2623 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
2625 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2626 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
2629 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2630 sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
2631 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2632 BGE_EVTENB_MI_INTERRUPT);
2636 * Clear any pending link state attention.
2637 * Otherwise some link state change events may be lost until attention
2638 * is cleared by bge_intr() -> bge_link_upd() sequence.
2639 * It's not necessary on newer BCM chips - perhaps enabling link
2640 * state change attentions implies clearing pending attention.
2642 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2643 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2644 BGE_MACSTAT_LINK_CHANGED);
2646 /* Enable link state change attentions. */
2647 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2652 static const struct bge_revision *
2653 bge_lookup_rev(uint32_t chipid)
2655 const struct bge_revision *br;
2657 for (br = bge_revisions; br->br_name != NULL; br++) {
2658 if (br->br_chipid == chipid)
2662 for (br = bge_majorrevs; br->br_name != NULL; br++) {
2663 if (br->br_chipid == BGE_ASICREV(chipid))
2670 static const struct bge_vendor *
2671 bge_lookup_vendor(uint16_t vid)
2673 const struct bge_vendor *v;
2675 for (v = bge_vendors; v->v_name != NULL; v++)
2683 bge_chipid(device_t dev)
2687 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2688 BGE_PCIMISCCTL_ASICREV_SHIFT;
2689 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
2691 * Find the ASCI revision. Different chips use different
2694 switch (pci_get_device(dev)) {
2695 case BCOM_DEVICEID_BCM5717:
2696 case BCOM_DEVICEID_BCM5718:
2697 case BCOM_DEVICEID_BCM5719:
2698 case BCOM_DEVICEID_BCM5720:
2699 case BCOM_DEVICEID_BCM5725:
2700 case BCOM_DEVICEID_BCM5727:
2701 case BCOM_DEVICEID_BCM5762:
2702 case BCOM_DEVICEID_BCM57764:
2703 case BCOM_DEVICEID_BCM57767:
2704 case BCOM_DEVICEID_BCM57787:
2705 id = pci_read_config(dev,
2706 BGE_PCI_GEN2_PRODID_ASICREV, 4);
2708 case BCOM_DEVICEID_BCM57761:
2709 case BCOM_DEVICEID_BCM57762:
2710 case BCOM_DEVICEID_BCM57765:
2711 case BCOM_DEVICEID_BCM57766:
2712 case BCOM_DEVICEID_BCM57781:
2713 case BCOM_DEVICEID_BCM57782:
2714 case BCOM_DEVICEID_BCM57785:
2715 case BCOM_DEVICEID_BCM57786:
2716 case BCOM_DEVICEID_BCM57791:
2717 case BCOM_DEVICEID_BCM57795:
2718 id = pci_read_config(dev,
2719 BGE_PCI_GEN15_PRODID_ASICREV, 4);
2722 id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
2729 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
2730 * against our list and return its name if we find a match.
2732 * Note that since the Broadcom controller contains VPD support, we
2733 * try to get the device name string from the controller itself instead
2734 * of the compiled-in string. It guarantees we'll always announce the
2735 * right product name. We fall back to the compiled-in string when
2736 * VPD is unavailable or corrupt.
2739 bge_probe(device_t dev)
2743 const struct bge_revision *br;
2745 struct bge_softc *sc;
2746 const struct bge_type *t = bge_devs;
2747 const struct bge_vendor *v;
2751 sc = device_get_softc(dev);
2753 vid = pci_get_vendor(dev);
2754 did = pci_get_device(dev);
2755 while(t->bge_vid != 0) {
2756 if ((vid == t->bge_vid) && (did == t->bge_did)) {
2757 id = bge_chipid(dev);
2758 br = bge_lookup_rev(id);
2759 if (bge_has_eaddr(sc) &&
2760 pci_get_vpd_ident(dev, &pname) == 0)
2761 snprintf(model, sizeof(model), "%s", pname);
2763 v = bge_lookup_vendor(vid);
2764 snprintf(model, sizeof(model), "%s %s",
2765 v != NULL ? v->v_name : "Unknown",
2766 br != NULL ? br->br_name :
2767 "NetXtreme/NetLink Ethernet Controller");
2769 snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x",
2770 model, br != NULL ? "" : "unknown ", id);
2771 device_set_desc_copy(dev, buf);
2772 return (BUS_PROBE_DEFAULT);
2781 bge_dma_free(struct bge_softc *sc)
2785 /* Destroy DMA maps for RX buffers. */
2786 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2787 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2788 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2789 sc->bge_cdata.bge_rx_std_dmamap[i]);
2791 if (sc->bge_cdata.bge_rx_std_sparemap)
2792 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2793 sc->bge_cdata.bge_rx_std_sparemap);
2795 /* Destroy DMA maps for jumbo RX buffers. */
2796 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2797 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2798 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2799 sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2801 if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2802 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2803 sc->bge_cdata.bge_rx_jumbo_sparemap);
2805 /* Destroy DMA maps for TX buffers. */
2806 for (i = 0; i < BGE_TX_RING_CNT; i++) {
2807 if (sc->bge_cdata.bge_tx_dmamap[i])
2808 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2809 sc->bge_cdata.bge_tx_dmamap[i]);
2812 if (sc->bge_cdata.bge_rx_mtag)
2813 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2814 if (sc->bge_cdata.bge_mtag_jumbo)
2815 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
2816 if (sc->bge_cdata.bge_tx_mtag)
2817 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2819 /* Destroy standard RX ring. */
2820 if (sc->bge_cdata.bge_rx_std_ring_map)
2821 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2822 sc->bge_cdata.bge_rx_std_ring_map);
2823 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
2824 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2825 sc->bge_ldata.bge_rx_std_ring,
2826 sc->bge_cdata.bge_rx_std_ring_map);
2828 if (sc->bge_cdata.bge_rx_std_ring_tag)
2829 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2831 /* Destroy jumbo RX ring. */
2832 if (sc->bge_cdata.bge_rx_jumbo_ring_map)
2833 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2834 sc->bge_cdata.bge_rx_jumbo_ring_map);
2836 if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
2837 sc->bge_ldata.bge_rx_jumbo_ring)
2838 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2839 sc->bge_ldata.bge_rx_jumbo_ring,
2840 sc->bge_cdata.bge_rx_jumbo_ring_map);
2842 if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2843 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2845 /* Destroy RX return ring. */
2846 if (sc->bge_cdata.bge_rx_return_ring_map)
2847 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2848 sc->bge_cdata.bge_rx_return_ring_map);
2850 if (sc->bge_cdata.bge_rx_return_ring_map &&
2851 sc->bge_ldata.bge_rx_return_ring)
2852 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2853 sc->bge_ldata.bge_rx_return_ring,
2854 sc->bge_cdata.bge_rx_return_ring_map);
2856 if (sc->bge_cdata.bge_rx_return_ring_tag)
2857 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2859 /* Destroy TX ring. */
2860 if (sc->bge_cdata.bge_tx_ring_map)
2861 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2862 sc->bge_cdata.bge_tx_ring_map);
2864 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
2865 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2866 sc->bge_ldata.bge_tx_ring,
2867 sc->bge_cdata.bge_tx_ring_map);
2869 if (sc->bge_cdata.bge_tx_ring_tag)
2870 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2872 /* Destroy status block. */
2873 if (sc->bge_cdata.bge_status_map)
2874 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2875 sc->bge_cdata.bge_status_map);
2877 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
2878 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2879 sc->bge_ldata.bge_status_block,
2880 sc->bge_cdata.bge_status_map);
2882 if (sc->bge_cdata.bge_status_tag)
2883 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2885 /* Destroy statistics block. */
2886 if (sc->bge_cdata.bge_stats_map)
2887 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2888 sc->bge_cdata.bge_stats_map);
2890 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2891 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2892 sc->bge_ldata.bge_stats,
2893 sc->bge_cdata.bge_stats_map);
2895 if (sc->bge_cdata.bge_stats_tag)
2896 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2898 if (sc->bge_cdata.bge_buffer_tag)
2899 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
2901 /* Destroy the parent tag. */
2902 if (sc->bge_cdata.bge_parent_tag)
2903 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2907 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
2908 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
2909 bus_addr_t *paddr, const char *msg)
2911 struct bge_dmamap_arg ctx;
2914 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2915 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2916 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
2918 device_printf(sc->bge_dev,
2919 "could not create %s dma tag\n", msg);
2922 /* Allocate DMA'able memory for ring. */
2923 error = bus_dmamem_alloc(*tag, (void **)ring,
2924 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
2926 device_printf(sc->bge_dev,
2927 "could not allocate DMA'able memory for %s\n", msg);
2930 /* Load the address of the ring. */
2931 ctx.bge_busaddr = 0;
2932 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr,
2933 &ctx, BUS_DMA_NOWAIT);
2935 device_printf(sc->bge_dev,
2936 "could not load DMA'able memory for %s\n", msg);
2939 *paddr = ctx.bge_busaddr;
2944 bge_dma_alloc(struct bge_softc *sc)
2947 bus_size_t rxmaxsegsz, sbsz, txsegsz, txmaxsegsz;
2950 lowaddr = BUS_SPACE_MAXADDR;
2951 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2952 lowaddr = BGE_DMA_MAXADDR;
2954 * Allocate the parent bus DMA tag appropriate for PCI.
2956 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2957 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2958 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2959 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2961 device_printf(sc->bge_dev,
2962 "could not allocate parent dma tag\n");
2966 /* Create tag for standard RX ring. */
2967 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
2968 &sc->bge_cdata.bge_rx_std_ring_tag,
2969 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
2970 &sc->bge_cdata.bge_rx_std_ring_map,
2971 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
2975 /* Create tag for RX return ring. */
2976 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
2977 &sc->bge_cdata.bge_rx_return_ring_tag,
2978 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
2979 &sc->bge_cdata.bge_rx_return_ring_map,
2980 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
2984 /* Create tag for TX ring. */
2985 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
2986 &sc->bge_cdata.bge_tx_ring_tag,
2987 (uint8_t **)&sc->bge_ldata.bge_tx_ring,
2988 &sc->bge_cdata.bge_tx_ring_map,
2989 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
2994 * Create tag for status block.
2995 * Because we only use single Tx/Rx/Rx return ring, use
2996 * minimum status block size except BCM5700 AX/BX which
2997 * seems to want to see full status block size regardless
2998 * of configured number of ring.
3000 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3001 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
3002 sbsz = BGE_STATUS_BLK_SZ;
3005 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
3006 &sc->bge_cdata.bge_status_tag,
3007 (uint8_t **)&sc->bge_ldata.bge_status_block,
3008 &sc->bge_cdata.bge_status_map,
3009 &sc->bge_ldata.bge_status_block_paddr, "status block");
3013 /* Create tag for statistics block. */
3014 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
3015 &sc->bge_cdata.bge_stats_tag,
3016 (uint8_t **)&sc->bge_ldata.bge_stats,
3017 &sc->bge_cdata.bge_stats_map,
3018 &sc->bge_ldata.bge_stats_paddr, "statistics block");
3022 /* Create tag for jumbo RX ring. */
3023 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3024 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
3025 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
3026 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
3027 &sc->bge_cdata.bge_rx_jumbo_ring_map,
3028 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
3033 /* Create parent tag for buffers. */
3034 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
3037 * watchdog timeout issue was observed on BCM5704 which
3038 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge).
3039 * Both limiting DMA address space to 32bits and flushing
3040 * mailbox write seem to address the issue.
3042 if (sc->bge_pcixcap != 0)
3043 lowaddr = BUS_SPACE_MAXADDR_32BIT;
3045 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 1, 0, lowaddr,
3046 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0,
3047 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
3048 &sc->bge_cdata.bge_buffer_tag);
3050 device_printf(sc->bge_dev,
3051 "could not allocate buffer dma tag\n");
3054 /* Create tag for Tx mbufs. */
3055 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
3056 txsegsz = BGE_TSOSEG_SZ;
3057 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
3060 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
3062 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
3063 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
3064 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
3065 &sc->bge_cdata.bge_tx_mtag);
3068 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
3072 /* Create tag for Rx mbufs. */
3073 if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
3074 rxmaxsegsz = MJUM9BYTES;
3076 rxmaxsegsz = MCLBYTES;
3077 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
3078 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1,
3079 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
3082 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
3086 /* Create DMA maps for RX buffers. */
3087 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3088 &sc->bge_cdata.bge_rx_std_sparemap);
3090 device_printf(sc->bge_dev,
3091 "can't create spare DMA map for RX\n");
3094 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3095 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3096 &sc->bge_cdata.bge_rx_std_dmamap[i]);
3098 device_printf(sc->bge_dev,
3099 "can't create DMA map for RX\n");
3104 /* Create DMA maps for TX buffers. */
3105 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3106 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
3107 &sc->bge_cdata.bge_tx_dmamap[i]);
3109 device_printf(sc->bge_dev,
3110 "can't create DMA map for TX\n");
3115 /* Create tags for jumbo RX buffers. */
3116 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3117 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
3118 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
3119 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
3120 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
3122 device_printf(sc->bge_dev,
3123 "could not allocate jumbo dma tag\n");
3126 /* Create DMA maps for jumbo RX buffers. */
3127 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3128 0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
3130 device_printf(sc->bge_dev,
3131 "can't create spare DMA map for jumbo RX\n");
3134 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
3135 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3136 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
3138 device_printf(sc->bge_dev,
3139 "can't create DMA map for jumbo RX\n");
3149 * Return true if this device has more than one port.
3152 bge_has_multiple_ports(struct bge_softc *sc)
3154 device_t dev = sc->bge_dev;
3155 u_int b, d, f, fscan, s;
3157 d = pci_get_domain(dev);
3158 b = pci_get_bus(dev);
3159 s = pci_get_slot(dev);
3160 f = pci_get_function(dev);
3161 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
3162 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
3168 * Return true if MSI can be used with this device.
3171 bge_can_use_msi(struct bge_softc *sc)
3173 int can_use_msi = 0;
3175 if (sc->bge_msi == 0)
3178 /* Disable MSI for polling(4). */
3179 #ifdef DEVICE_POLLING
3182 switch (sc->bge_asicrev) {
3183 case BGE_ASICREV_BCM5714_A0:
3184 case BGE_ASICREV_BCM5714:
3186 * Apparently, MSI doesn't work when these chips are
3187 * configured in single-port mode.
3189 if (bge_has_multiple_ports(sc))
3192 case BGE_ASICREV_BCM5750:
3193 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
3194 sc->bge_chiprev != BGE_CHIPREV_5750_BX)
3198 if (BGE_IS_575X_PLUS(sc))
3201 return (can_use_msi);
3205 bge_mbox_reorder(struct bge_softc *sc)
3207 /* Lists of PCI bridges that are known to reorder mailbox writes. */
3208 static const struct mbox_reorder {
3209 const uint16_t vendor;
3210 const uint16_t device;
3212 } mbox_reorder_lists[] = {
3213 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" },
3215 devclass_t pci, pcib;
3219 pci = devclass_find("pci");
3220 pcib = devclass_find("pcib");
3222 bus = device_get_parent(dev);
3224 dev = device_get_parent(bus);
3225 bus = device_get_parent(dev);
3226 if (device_get_devclass(dev) != pcib)
3228 for (i = 0; i < nitems(mbox_reorder_lists); i++) {
3229 if (pci_get_vendor(dev) ==
3230 mbox_reorder_lists[i].vendor &&
3231 pci_get_device(dev) ==
3232 mbox_reorder_lists[i].device) {
3233 device_printf(sc->bge_dev,
3234 "enabling MBOX workaround for %s\n",
3235 mbox_reorder_lists[i].desc);
3239 if (device_get_devclass(bus) != pci)
3246 bge_devinfo(struct bge_softc *sc)
3250 device_printf(sc->bge_dev,
3251 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ",
3252 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev);
3253 if (sc->bge_flags & BGE_FLAG_PCIE)
3255 else if (sc->bge_flags & BGE_FLAG_PCIX) {
3257 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3258 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE)
3261 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
3280 printf("%u MHz\n", clk);
3282 if (sc->bge_pcixcap != 0)
3283 printf("PCI on PCI-X ");
3286 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3287 if (cfg & BGE_PCISTATE_PCI_BUSSPEED)
3291 if (cfg & BGE_PCISTATE_32BIT_BUS)
3292 printf("%u MHz; 32bit\n", clk);
3294 printf("%u MHz; 64bit\n", clk);
3299 bge_attach(device_t dev)
3302 struct bge_softc *sc;
3303 uint32_t hwcfg = 0, misccfg, pcistate;
3304 u_char eaddr[ETHER_ADDR_LEN];
3305 int capmask, error, reg, rid, trys;
3307 sc = device_get_softc(dev);
3310 BGE_LOCK_INIT(sc, device_get_nameunit(dev));
3311 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
3312 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
3314 pci_enable_busmaster(dev);
3317 * Allocate control/status registers.
3320 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3323 if (sc->bge_res == NULL) {
3324 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n");
3329 /* Save various chip information. */
3330 sc->bge_func_addr = pci_get_function(dev);
3331 sc->bge_chipid = bge_chipid(dev);
3332 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
3333 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
3335 /* Set default PHY address. */
3336 sc->bge_phy_addr = 1;
3338 * PHY address mapping for various devices.
3340 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
3341 * ---------+-------+-------+-------+-------+
3342 * BCM57XX | 1 | X | X | X |
3343 * BCM5704 | 1 | X | 1 | X |
3344 * BCM5717 | 1 | 8 | 2 | 9 |
3345 * BCM5719 | 1 | 8 | 2 | 9 |
3346 * BCM5720 | 1 | 8 | 2 | 9 |
3348 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr |
3349 * ---------+-------+-------+-------+-------+
3350 * BCM57XX | X | X | X | X |
3351 * BCM5704 | X | X | X | X |
3352 * BCM5717 | X | X | X | X |
3353 * BCM5719 | 3 | 10 | 4 | 11 |
3354 * BCM5720 | X | X | X | X |
3356 * Other addresses may respond but they are not
3357 * IEEE compliant PHYs and should be ignored.
3359 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
3360 sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3361 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3362 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) {
3363 if (CSR_READ_4(sc, BGE_SGDIG_STS) &
3364 BGE_SGDIGSTS_IS_SERDES)
3365 sc->bge_phy_addr = sc->bge_func_addr + 8;
3367 sc->bge_phy_addr = sc->bge_func_addr + 1;
3369 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
3370 BGE_CPMU_PHY_STRAP_IS_SERDES)
3371 sc->bge_phy_addr = sc->bge_func_addr + 8;
3373 sc->bge_phy_addr = sc->bge_func_addr + 1;
3377 if (bge_has_eaddr(sc))
3378 sc->bge_flags |= BGE_FLAG_EADDR;
3380 /* Save chipset family. */
3381 switch (sc->bge_asicrev) {
3382 case BGE_ASICREV_BCM5762:
3383 case BGE_ASICREV_BCM57765:
3384 case BGE_ASICREV_BCM57766:
3385 sc->bge_flags |= BGE_FLAG_57765_PLUS;
3387 case BGE_ASICREV_BCM5717:
3388 case BGE_ASICREV_BCM5719:
3389 case BGE_ASICREV_BCM5720:
3390 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
3391 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
3392 BGE_FLAG_JUMBO_FRAME;
3393 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3394 sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3396 * Enable work around for DMA engine miscalculation
3397 * of TXMBUF available space.
3399 sc->bge_flags |= BGE_FLAG_RDMA_BUG;
3400 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3401 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3402 /* Jumbo frame on BCM5719 A0 does not work. */
3403 sc->bge_flags &= ~BGE_FLAG_JUMBO;
3407 case BGE_ASICREV_BCM5755:
3408 case BGE_ASICREV_BCM5761:
3409 case BGE_ASICREV_BCM5784:
3410 case BGE_ASICREV_BCM5785:
3411 case BGE_ASICREV_BCM5787:
3412 case BGE_ASICREV_BCM57780:
3413 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
3416 case BGE_ASICREV_BCM5700:
3417 case BGE_ASICREV_BCM5701:
3418 case BGE_ASICREV_BCM5703:
3419 case BGE_ASICREV_BCM5704:
3420 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
3422 case BGE_ASICREV_BCM5714_A0:
3423 case BGE_ASICREV_BCM5780:
3424 case BGE_ASICREV_BCM5714:
3425 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
3427 case BGE_ASICREV_BCM5750:
3428 case BGE_ASICREV_BCM5752:
3429 case BGE_ASICREV_BCM5906:
3430 sc->bge_flags |= BGE_FLAG_575X_PLUS;
3432 case BGE_ASICREV_BCM5705:
3433 sc->bge_flags |= BGE_FLAG_5705_PLUS;
3437 /* Identify chips with APE processor. */
3438 switch (sc->bge_asicrev) {
3439 case BGE_ASICREV_BCM5717:
3440 case BGE_ASICREV_BCM5719:
3441 case BGE_ASICREV_BCM5720:
3442 case BGE_ASICREV_BCM5761:
3443 case BGE_ASICREV_BCM5762:
3444 sc->bge_flags |= BGE_FLAG_APE;
3448 /* Chips with APE need BAR2 access for APE registers/memory. */
3449 if ((sc->bge_flags & BGE_FLAG_APE) != 0) {
3451 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3453 if (sc->bge_res2 == NULL) {
3454 device_printf (sc->bge_dev,
3455 "couldn't map BAR2 memory\n");
3460 /* Enable APE register/memory access by host driver. */
3461 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3462 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
3463 BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
3464 BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
3465 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4);
3467 bge_ape_lock_init(sc);
3468 bge_ape_read_fw_ver(sc);
3471 /* Add SYSCTLs, requires the chipset family to be set. */
3472 bge_add_sysctls(sc);
3474 /* Identify the chips that use an CPMU. */
3475 if (BGE_IS_5717_PLUS(sc) ||
3476 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3477 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3478 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
3479 sc->bge_asicrev == BGE_ASICREV_BCM57780)
3480 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
3481 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
3482 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
3484 sc->bge_mi_mode = BGE_MIMODE_BASE;
3485 /* Enable auto polling for BCM570[0-5]. */
3486 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
3487 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
3490 * All Broadcom controllers have 4GB boundary DMA bug.
3491 * Whenever an address crosses a multiple of the 4GB boundary
3492 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3493 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3494 * state machine will lockup and cause the device to hang.
3496 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
3498 /* BCM5755 or higher and BCM5906 have short DMA bug. */
3499 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3500 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
3503 * BCM5719 cannot handle DMA requests for DMA segments that
3504 * have larger than 4KB in size. However the maximum DMA
3505 * segment size created in DMA tag is 4KB for TSO, so we
3506 * wouldn't encounter the issue here.
3508 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
3509 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG;
3511 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3512 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
3513 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
3514 misccfg == BGE_MISCCFG_BOARD_ID_5788M)
3515 sc->bge_flags |= BGE_FLAG_5788;
3518 capmask = BMSR_DEFCAPMASK;
3519 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
3520 (misccfg == 0x4000 || misccfg == 0x8000)) ||
3521 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3522 pci_get_vendor(dev) == BCOM_VENDORID &&
3523 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 ||
3524 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 ||
3525 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) ||
3526 (pci_get_vendor(dev) == BCOM_VENDORID &&
3527 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F ||
3528 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F ||
3529 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) ||
3530 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 ||
3531 pci_get_device(dev) == BCOM_DEVICEID_BCM57791 ||
3532 pci_get_device(dev) == BCOM_DEVICEID_BCM57795 ||
3533 sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3534 /* These chips are 10/100 only. */
3535 capmask &= ~BMSR_EXTSTAT;
3536 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3540 * Some controllers seem to require a special firmware to use
3541 * TSO. But the firmware is not available to FreeBSD and Linux
3542 * claims that the TSO performed by the firmware is slower than
3543 * hardware based TSO. Moreover the firmware based TSO has one
3544 * known bug which can't handle TSO if Ethernet header + IP/TCP
3545 * header is greater than 80 bytes. A workaround for the TSO
3546 * bug exist but it seems it's too expensive than not using
3547 * TSO at all. Some hardwares also have the TSO bug so limit
3548 * the TSO to the controllers that are not affected TSO issues
3549 * (e.g. 5755 or higher).
3551 if (BGE_IS_5717_PLUS(sc)) {
3552 /* BCM5717 requires different TSO configuration. */
3553 sc->bge_flags |= BGE_FLAG_TSO3;
3554 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3555 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3556 /* TSO on BCM5719 A0 does not work. */
3557 sc->bge_flags &= ~BGE_FLAG_TSO3;
3559 } else if (BGE_IS_5755_PLUS(sc)) {
3561 * BCM5754 and BCM5787 shares the same ASIC id so
3562 * explicit device id check is required.
3563 * Due to unknown reason TSO does not work on BCM5755M.
3565 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
3566 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
3567 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
3568 sc->bge_flags |= BGE_FLAG_TSO;
3572 * Check if this is a PCI-X or PCI Express device.
3574 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
3576 * Found a PCI Express capabilities register, this
3577 * must be a PCI Express device.
3579 sc->bge_flags |= BGE_FLAG_PCIE;
3580 sc->bge_expcap = reg;
3581 /* Extract supported maximum payload size. */
3582 sc->bge_mps = pci_read_config(dev, sc->bge_expcap +
3583 PCIER_DEVICE_CAP, 2);
3584 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD);
3585 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3586 sc->bge_asicrev == BGE_ASICREV_BCM5720)
3587 sc->bge_expmrq = 2048;
3589 sc->bge_expmrq = 4096;
3590 pci_set_max_read_req(dev, sc->bge_expmrq);
3593 * Check if the device is in PCI-X Mode.
3594 * (This bit is not valid on PCI Express controllers.)
3596 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0)
3597 sc->bge_pcixcap = reg;
3598 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
3599 BGE_PCISTATE_PCI_BUSMODE) == 0)
3600 sc->bge_flags |= BGE_FLAG_PCIX;
3604 * The 40bit DMA bug applies to the 5714/5715 controllers and is
3605 * not actually a MAC controller bug but an issue with the embedded
3606 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
3608 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
3609 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
3611 * Some PCI-X bridges are known to trigger write reordering to
3612 * the mailbox registers. Typical phenomena is watchdog timeouts
3613 * caused by out-of-order TX completions. Enable workaround for
3614 * PCI-X devices that live behind these bridges.
3615 * Note, PCI-X controllers can run in PCI mode so we can't use
3616 * BGE_FLAG_PCIX flag to detect PCI-X controllers.
3618 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0)
3619 sc->bge_flags |= BGE_FLAG_MBOX_REORDER;
3621 * Allocate the interrupt, using MSI if possible. These devices
3622 * support 8 MSI messages, but only the first one is used in
3626 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) {
3627 sc->bge_msicap = reg;
3629 if (bge_can_use_msi(sc) && pci_alloc_msi(dev, ®) == 0) {
3631 sc->bge_flags |= BGE_FLAG_MSI;
3636 * All controllers except BCM5700 supports tagged status but
3637 * we use tagged status only for MSI case on BCM5717. Otherwise
3638 * MSI on BCM5717 does not work.
3640 #ifndef DEVICE_POLLING
3641 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
3642 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
3645 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3646 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
3648 if (sc->bge_irq == NULL) {
3649 device_printf(sc->bge_dev, "couldn't map interrupt\n");
3656 sc->bge_asf_mode = 0;
3657 /* No ASF if APE present. */
3658 if ((sc->bge_flags & BGE_FLAG_APE) == 0) {
3659 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3660 BGE_SRAM_DATA_SIG_MAGIC)) {
3661 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
3663 sc->bge_asf_mode |= ASF_ENABLE;
3664 sc->bge_asf_mode |= ASF_STACKUP;
3665 if (BGE_IS_575X_PLUS(sc))
3666 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3672 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
3673 if (bge_reset(sc)) {
3674 device_printf(sc->bge_dev, "chip reset failed\n");
3679 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
3680 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
3682 if (bge_chipinit(sc)) {
3683 device_printf(sc->bge_dev, "chip initialization failed\n");
3688 error = bge_get_eaddr(sc, eaddr);
3690 device_printf(sc->bge_dev,
3691 "failed to read station address\n");
3696 /* 5705 limits RX return ring to 512 entries. */
3697 if (BGE_IS_5717_PLUS(sc))
3698 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3699 else if (BGE_IS_5705_PLUS(sc))
3700 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3702 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3704 if (bge_dma_alloc(sc)) {
3705 device_printf(sc->bge_dev,
3706 "failed to allocate DMA resources\n");
3711 /* Set default tuneable values. */
3712 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3713 sc->bge_rx_coal_ticks = 150;
3714 sc->bge_tx_coal_ticks = 150;
3715 sc->bge_rx_max_coal_bds = 10;
3716 sc->bge_tx_max_coal_bds = 10;
3718 /* Initialize checksum features to use. */
3719 sc->bge_csum_features = BGE_CSUM_FEATURES;
3720 if (sc->bge_forced_udpcsum != 0)
3721 sc->bge_csum_features |= CSUM_UDP;
3723 /* Set up ifnet structure */
3724 ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
3726 device_printf(sc->bge_dev, "failed to if_alloc()\n");
3731 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3732 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3733 ifp->if_ioctl = bge_ioctl;
3734 ifp->if_start = bge_start;
3735 ifp->if_init = bge_init;
3736 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
3737 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
3738 IFQ_SET_READY(&ifp->if_snd);
3739 ifp->if_hwassist = sc->bge_csum_features;
3740 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3742 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3743 ifp->if_hwassist |= CSUM_TSO;
3744 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO;
3746 #ifdef IFCAP_VLAN_HWCSUM
3747 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
3749 ifp->if_capenable = ifp->if_capabilities;
3750 #ifdef DEVICE_POLLING
3751 ifp->if_capabilities |= IFCAP_POLLING;
3755 * 5700 B0 chips do not support checksumming correctly due
3758 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
3759 ifp->if_capabilities &= ~IFCAP_HWCSUM;
3760 ifp->if_capenable &= ~IFCAP_HWCSUM;
3761 ifp->if_hwassist = 0;
3765 * Figure out what sort of media we have by checking the
3766 * hardware config word in the first 32k of NIC internal memory,
3767 * or fall back to examining the EEPROM if necessary.
3768 * Note: on some BCM5700 cards, this value appears to be unset.
3769 * If that's the case, we have to rely on identifying the NIC
3770 * by its PCI subsystem ID, as we do below for the SysKonnect
3773 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
3774 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3775 else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
3776 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3777 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
3779 device_printf(sc->bge_dev, "failed to read EEPROM\n");
3783 hwcfg = ntohl(hwcfg);
3786 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
3787 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
3788 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
3789 if (BGE_IS_5705_PLUS(sc)) {
3790 sc->bge_flags |= BGE_FLAG_MII_SERDES;
3791 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3793 sc->bge_flags |= BGE_FLAG_TBI;
3796 /* Set various PHY bug flags. */
3797 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
3798 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
3799 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
3800 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
3801 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
3802 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
3803 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
3804 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
3805 if (pci_get_subvendor(dev) == DELL_VENDORID)
3806 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
3807 if ((BGE_IS_5705_PLUS(sc)) &&
3808 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
3809 sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
3810 sc->bge_asicrev != BGE_ASICREV_BCM57780 &&
3811 !BGE_IS_5717_PLUS(sc)) {
3812 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
3813 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3814 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3815 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
3816 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
3817 pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
3818 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
3819 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
3820 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
3822 sc->bge_phy_flags |= BGE_PHY_BER_BUG;
3826 * Don't enable Ethernet@WireSpeed for the 5700 or the
3827 * 5705 A0 and A1 chips.
3829 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3830 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3831 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
3832 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)))
3833 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3835 if (sc->bge_flags & BGE_FLAG_TBI) {
3836 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3838 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
3839 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
3841 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3842 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3843 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3846 * Do transceiver setup and tell the firmware the
3847 * driver is down so we can try to get access the
3848 * probe if ASF is running. Retry a couple of times
3849 * if we get a conflict with the ASF firmware accessing
3853 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3855 bge_asf_driver_up(sc);
3857 error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd,
3858 bge_ifmedia_sts, capmask, sc->bge_phy_addr, MII_OFFSET_ANY,
3862 device_printf(sc->bge_dev, "Try again\n");
3863 bge_miibus_writereg(sc->bge_dev,
3864 sc->bge_phy_addr, MII_BMCR, BMCR_RESET);
3867 device_printf(sc->bge_dev, "attaching PHYs failed\n");
3872 * Now tell the firmware we are going up after probing the PHY
3874 if (sc->bge_asf_mode & ASF_STACKUP)
3875 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3879 * When using the BCM5701 in PCI-X mode, data corruption has
3880 * been observed in the first few bytes of some received packets.
3881 * Aligning the packet buffer in memory eliminates the corruption.
3882 * Unfortunately, this misaligns the packet payloads. On platforms
3883 * which do not support unaligned accesses, we will realign the
3884 * payloads by copying the received packets.
3886 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
3887 sc->bge_flags & BGE_FLAG_PCIX)
3888 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
3891 * Call MI attach routine.
3893 ether_ifattach(ifp, eaddr);
3895 /* Tell upper layer we support long frames. */
3896 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
3901 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
3902 /* Take advantage of single-shot MSI. */
3903 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
3904 ~BGE_MSIMODE_ONE_SHOT_DISABLE);
3905 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
3906 taskqueue_thread_enqueue, &sc->bge_tq);
3907 if (sc->bge_tq == NULL) {
3908 device_printf(dev, "could not create taskqueue.\n");
3909 ether_ifdetach(ifp);
3913 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET,
3914 "%s taskq", device_get_nameunit(sc->bge_dev));
3916 device_printf(dev, "could not start threads.\n");
3917 ether_ifdetach(ifp);
3920 error = bus_setup_intr(dev, sc->bge_irq,
3921 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
3924 error = bus_setup_intr(dev, sc->bge_irq,
3925 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
3929 ether_ifdetach(ifp);
3930 device_printf(sc->bge_dev, "couldn't set up irq\n");
3940 bge_detach(device_t dev)
3942 struct bge_softc *sc;
3945 sc = device_get_softc(dev);
3948 #ifdef DEVICE_POLLING
3949 if (ifp->if_capenable & IFCAP_POLLING)
3950 ether_poll_deregister(ifp);
3953 if (device_is_attached(dev)) {
3954 ether_ifdetach(ifp);
3958 callout_drain(&sc->bge_stat_ch);
3962 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3964 if (sc->bge_flags & BGE_FLAG_TBI)
3965 ifmedia_removeall(&sc->bge_ifmedia);
3966 else if (sc->bge_miibus != NULL) {
3967 bus_generic_detach(dev);
3968 device_delete_child(dev, sc->bge_miibus);
3971 bge_release_resources(sc);
3977 bge_release_resources(struct bge_softc *sc)
3983 if (sc->bge_tq != NULL)
3984 taskqueue_free(sc->bge_tq);
3986 if (sc->bge_intrhand != NULL)
3987 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3989 if (sc->bge_irq != NULL) {
3990 bus_release_resource(dev, SYS_RES_IRQ,
3991 rman_get_rid(sc->bge_irq), sc->bge_irq);
3992 pci_release_msi(dev);
3995 if (sc->bge_res != NULL)
3996 bus_release_resource(dev, SYS_RES_MEMORY,
3997 rman_get_rid(sc->bge_res), sc->bge_res);
3999 if (sc->bge_res2 != NULL)
4000 bus_release_resource(dev, SYS_RES_MEMORY,
4001 rman_get_rid(sc->bge_res2), sc->bge_res2);
4003 if (sc->bge_ifp != NULL)
4004 if_free(sc->bge_ifp);
4008 if (mtx_initialized(&sc->bge_mtx)) /* XXX */
4009 BGE_LOCK_DESTROY(sc);
4013 bge_reset(struct bge_softc *sc)
4016 uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val;
4017 void (*write_op)(struct bge_softc *, int, int);
4023 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
4024 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4025 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
4026 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
4028 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
4029 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
4030 if (sc->bge_flags & BGE_FLAG_PCIE)
4031 write_op = bge_writemem_direct;
4033 write_op = bge_writemem_ind;
4035 write_op = bge_writereg_ind;
4037 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
4038 sc->bge_asicrev != BGE_ASICREV_BCM5701) {
4039 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
4040 for (i = 0; i < 8000; i++) {
4041 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
4042 BGE_NVRAMSWARB_GNT1)
4048 device_printf(dev, "NVRAM lock timedout!\n");
4051 /* Take APE lock when performing reset. */
4052 bge_ape_lock(sc, BGE_APE_LOCK_GRC);
4054 /* Save some important PCI state. */
4055 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
4056 command = pci_read_config(dev, BGE_PCI_CMD, 4);
4058 pci_write_config(dev, BGE_PCI_MISC_CTL,
4059 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4060 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4062 /* Disable fastboot on controllers that support it. */
4063 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
4064 BGE_IS_5755_PLUS(sc)) {
4066 device_printf(dev, "Disabling fastboot\n");
4067 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
4071 * Write the magic number to SRAM at offset 0xB50.
4072 * When firmware finishes its initialization it will
4073 * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
4075 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
4077 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
4079 /* XXX: Broadcom Linux driver. */
4080 if (sc->bge_flags & BGE_FLAG_PCIE) {
4081 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
4082 (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) {
4083 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */
4084 CSR_WRITE_4(sc, 0x7E2C, 0x20);
4086 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
4087 /* Prevent PCIE link training during global reset */
4088 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
4093 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4094 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4095 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
4096 val | BGE_VCPU_STATUS_DRV_RESET);
4097 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
4098 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
4099 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
4103 * Set GPHY Power Down Override to leave GPHY
4104 * powered up in D0 uninitialized.
4106 if (BGE_IS_5705_PLUS(sc) &&
4107 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0)
4108 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
4110 /* Issue global reset */
4111 write_op(sc, BGE_MISC_CFG, reset);
4113 if (sc->bge_flags & BGE_FLAG_PCIE)
4118 /* XXX: Broadcom Linux driver. */
4119 if (sc->bge_flags & BGE_FLAG_PCIE) {
4120 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
4121 DELAY(500000); /* wait for link training to complete */
4122 val = pci_read_config(dev, 0xC4, 4);
4123 pci_write_config(dev, 0xC4, val | (1 << 15), 4);
4125 devctl = pci_read_config(dev,
4126 sc->bge_expcap + PCIER_DEVICE_CTL, 2);
4127 /* Clear enable no snoop and disable relaxed ordering. */
4128 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE |
4129 PCIEM_CTL_NOSNOOP_ENABLE);
4130 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL,
4132 pci_set_max_read_req(dev, sc->bge_expmrq);
4133 /* Clear error status. */
4134 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA,
4135 PCIEM_STA_CORRECTABLE_ERROR |
4136 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
4137 PCIEM_STA_UNSUPPORTED_REQ, 2);
4140 /* Reset some of the PCI state that got zapped by reset. */
4141 pci_write_config(dev, BGE_PCI_MISC_CTL,
4142 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4143 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4144 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
4145 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
4146 (sc->bge_flags & BGE_FLAG_PCIX) != 0)
4147 val |= BGE_PCISTATE_RETRY_SAME_DMA;
4148 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4149 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
4150 BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
4151 BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
4152 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4);
4153 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
4154 pci_write_config(dev, BGE_PCI_CMD, command, 4);
4156 * Disable PCI-X relaxed ordering to ensure status block update
4157 * comes first then packet buffer DMA. Otherwise driver may
4158 * read stale status block.
4160 if (sc->bge_flags & BGE_FLAG_PCIX) {
4161 devctl = pci_read_config(dev,
4162 sc->bge_pcixcap + PCIXR_COMMAND, 2);
4163 devctl &= ~PCIXM_COMMAND_ERO;
4164 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
4165 devctl &= ~PCIXM_COMMAND_MAX_READ;
4166 devctl |= PCIXM_COMMAND_MAX_READ_2048;
4167 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4168 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
4169 PCIXM_COMMAND_MAX_READ);
4170 devctl |= PCIXM_COMMAND_MAX_READ_2048;
4172 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
4175 /* Re-enable MSI, if necessary, and enable the memory arbiter. */
4176 if (BGE_IS_5714_FAMILY(sc)) {
4177 /* This chip disables MSI on reset. */
4178 if (sc->bge_flags & BGE_FLAG_MSI) {
4179 val = pci_read_config(dev,
4180 sc->bge_msicap + PCIR_MSI_CTRL, 2);
4181 pci_write_config(dev,
4182 sc->bge_msicap + PCIR_MSI_CTRL,
4183 val | PCIM_MSICTRL_MSI_ENABLE, 2);
4184 val = CSR_READ_4(sc, BGE_MSI_MODE);
4185 CSR_WRITE_4(sc, BGE_MSI_MODE,
4186 val | BGE_MSIMODE_ENABLE);
4188 val = CSR_READ_4(sc, BGE_MARB_MODE);
4189 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
4191 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4193 /* Fix up byte swapping. */
4194 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
4196 val = CSR_READ_4(sc, BGE_MAC_MODE);
4197 val = (val & ~mac_mode_mask) | mac_mode;
4198 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
4201 bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
4203 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4204 for (i = 0; i < BGE_TIMEOUT; i++) {
4205 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4206 if (val & BGE_VCPU_STATUS_INIT_DONE)
4210 if (i == BGE_TIMEOUT) {
4211 device_printf(dev, "reset timed out\n");
4216 * Poll until we see the 1's complement of the magic number.
4217 * This indicates that the firmware initialization is complete.
4218 * We expect this to fail if no chip containing the Ethernet
4219 * address is fitted though.
4221 for (i = 0; i < BGE_TIMEOUT; i++) {
4223 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
4224 if (val == ~BGE_SRAM_FW_MB_MAGIC)
4228 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
4230 "firmware handshake timed out, found 0x%08x\n",
4232 /* BCM57765 A0 needs additional time before accessing. */
4233 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
4234 DELAY(10 * 1000); /* XXX */
4238 * The 5704 in TBI mode apparently needs some special
4239 * adjustment to insure the SERDES drive level is set
4242 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
4243 sc->bge_flags & BGE_FLAG_TBI) {
4244 val = CSR_READ_4(sc, BGE_SERDES_CFG);
4245 val = (val & ~0xFFF) | 0x880;
4246 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
4249 /* XXX: Broadcom Linux driver. */
4250 if (sc->bge_flags & BGE_FLAG_PCIE &&
4251 !BGE_IS_5717_PLUS(sc) &&
4252 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
4253 sc->bge_asicrev != BGE_ASICREV_BCM5785) {
4254 /* Enable Data FIFO protection. */
4255 val = CSR_READ_4(sc, 0x7C00);
4256 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
4259 if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
4260 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
4261 CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
4266 static __inline void
4267 bge_rxreuse_std(struct bge_softc *sc, int i)
4269 struct bge_rx_bd *r;
4271 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
4272 r->bge_flags = BGE_RXBDFLAG_END;
4273 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
4275 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4278 static __inline void
4279 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
4281 struct bge_extrx_bd *r;
4283 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
4284 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
4285 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
4286 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
4287 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
4288 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
4290 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4294 * Frame reception handling. This is called if there's a frame
4295 * on the receive return list.
4297 * Note: we have to be able to handle two possibilities here:
4298 * 1) the frame is from the jumbo receive ring
4299 * 2) the frame is from the standard receive ring
4303 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
4306 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
4309 rx_cons = sc->bge_rx_saved_considx;
4311 /* Nothing to do. */
4312 if (rx_cons == rx_prod)
4317 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4318 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
4319 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4320 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
4321 if (BGE_IS_JUMBO_CAPABLE(sc) &&
4322 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
4323 (MCLBYTES - ETHER_ALIGN))
4324 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4325 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
4327 while (rx_cons != rx_prod) {
4328 struct bge_rx_bd *cur_rx;
4330 struct mbuf *m = NULL;
4331 uint16_t vlan_tag = 0;
4334 #ifdef DEVICE_POLLING
4335 if (ifp->if_capenable & IFCAP_POLLING) {
4336 if (sc->rxcycles <= 0)
4342 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
4344 rxidx = cur_rx->bge_idx;
4345 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
4347 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
4348 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
4350 vlan_tag = cur_rx->bge_vlan_tag;
4353 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
4355 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
4356 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4357 bge_rxreuse_jumbo(sc, rxidx);
4360 if (bge_newbuf_jumbo(sc, rxidx) != 0) {
4361 bge_rxreuse_jumbo(sc, rxidx);
4365 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4368 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
4369 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4370 bge_rxreuse_std(sc, rxidx);
4373 if (bge_newbuf_std(sc, rxidx) != 0) {
4374 bge_rxreuse_std(sc, rxidx);
4378 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4382 #ifndef __NO_STRICT_ALIGNMENT
4384 * For architectures with strict alignment we must make sure
4385 * the payload is aligned.
4387 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
4388 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
4390 m->m_data += ETHER_ALIGN;
4393 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
4394 m->m_pkthdr.rcvif = ifp;
4396 if (ifp->if_capenable & IFCAP_RXCSUM)
4397 bge_rxcsum(sc, cur_rx, m);
4400 * If we received a packet with a vlan tag,
4401 * attach that information to the packet.
4404 m->m_pkthdr.ether_vtag = vlan_tag;
4405 m->m_flags |= M_VLANTAG;
4410 (*ifp->if_input)(ifp, m);
4413 (*ifp->if_input)(ifp, m);
4416 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
4420 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4421 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
4423 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4424 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
4427 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4428 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
4430 sc->bge_rx_saved_considx = rx_cons;
4431 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
4433 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
4434 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT);
4436 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
4437 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT);
4440 * This register wraps very quickly under heavy packet drops.
4441 * If you need correct statistics, you can enable this check.
4443 if (BGE_IS_5705_PLUS(sc))
4444 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4450 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
4453 if (BGE_IS_5717_PLUS(sc)) {
4454 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
4455 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4456 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4457 if ((cur_rx->bge_error_flag &
4458 BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
4459 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4461 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
4462 m->m_pkthdr.csum_data =
4463 cur_rx->bge_tcp_udp_csum;
4464 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4469 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4470 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4471 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
4472 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4474 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
4475 m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
4476 m->m_pkthdr.csum_data =
4477 cur_rx->bge_tcp_udp_csum;
4478 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4485 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
4487 struct bge_tx_bd *cur_tx;
4490 BGE_LOCK_ASSERT(sc);
4492 /* Nothing to do. */
4493 if (sc->bge_tx_saved_considx == tx_cons)
4498 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4499 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
4501 * Go through our tx ring and free mbufs for those
4502 * frames that have been sent.
4504 while (sc->bge_tx_saved_considx != tx_cons) {
4507 idx = sc->bge_tx_saved_considx;
4508 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
4509 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
4511 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
4512 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
4513 sc->bge_cdata.bge_tx_dmamap[idx],
4514 BUS_DMASYNC_POSTWRITE);
4515 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
4516 sc->bge_cdata.bge_tx_dmamap[idx]);
4517 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
4518 sc->bge_cdata.bge_tx_chain[idx] = NULL;
4521 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
4524 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4525 if (sc->bge_txcnt == 0)
4529 #ifdef DEVICE_POLLING
4531 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
4533 struct bge_softc *sc = ifp->if_softc;
4534 uint16_t rx_prod, tx_cons;
4535 uint32_t statusword;
4539 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4544 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4545 sc->bge_cdata.bge_status_map,
4546 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4547 /* Fetch updates from the status block. */
4548 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4549 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4551 statusword = sc->bge_ldata.bge_status_block->bge_status;
4552 /* Clear the status so the next pass only sees the changes. */
4553 sc->bge_ldata.bge_status_block->bge_status = 0;
4555 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4556 sc->bge_cdata.bge_status_map,
4557 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4559 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
4560 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
4563 if (cmd == POLL_AND_CHECK_STATUS)
4564 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4565 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4566 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
4569 sc->rxcycles = count;
4570 rx_npkts = bge_rxeof(sc, rx_prod, 1);
4571 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4575 bge_txeof(sc, tx_cons);
4576 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4577 bge_start_locked(ifp);
4582 #endif /* DEVICE_POLLING */
4585 bge_msi_intr(void *arg)
4587 struct bge_softc *sc;
4589 sc = (struct bge_softc *)arg;
4591 * This interrupt is not shared and controller already
4592 * disabled further interrupt.
4594 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
4595 return (FILTER_HANDLED);
4599 bge_intr_task(void *arg, int pending)
4601 struct bge_softc *sc;
4603 uint32_t status, status_tag;
4604 uint16_t rx_prod, tx_cons;
4606 sc = (struct bge_softc *)arg;
4610 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
4615 /* Get updated status block. */
4616 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4617 sc->bge_cdata.bge_status_map,
4618 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4620 /* Save producer/consumer indices. */
4621 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4622 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4623 status = sc->bge_ldata.bge_status_block->bge_status;
4624 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
4625 /* Dirty the status flag. */
4626 sc->bge_ldata.bge_status_block->bge_status = 0;
4627 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4628 sc->bge_cdata.bge_status_map,
4629 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4630 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
4633 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
4636 /* Let controller work. */
4637 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
4639 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
4640 sc->bge_rx_saved_considx != rx_prod) {
4641 /* Check RX return ring producer/consumer. */
4643 bge_rxeof(sc, rx_prod, 0);
4646 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4647 /* Check TX ring producer/consumer. */
4648 bge_txeof(sc, tx_cons);
4649 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4650 bge_start_locked(ifp);
4658 struct bge_softc *sc;
4660 uint32_t statusword;
4661 uint16_t rx_prod, tx_cons;
4669 #ifdef DEVICE_POLLING
4670 if (ifp->if_capenable & IFCAP_POLLING) {
4677 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
4678 * disable interrupts by writing nonzero like we used to, since with
4679 * our current organization this just gives complications and
4680 * pessimizations for re-enabling interrupts. We used to have races
4681 * instead of the necessary complications. Disabling interrupts
4682 * would just reduce the chance of a status update while we are
4683 * running (by switching to the interrupt-mode coalescence
4684 * parameters), but this chance is already very low so it is more
4685 * efficient to get another interrupt than prevent it.
4687 * We do the ack first to ensure another interrupt if there is a
4688 * status update after the ack. We don't check for the status
4689 * changing later because it is more efficient to get another
4690 * interrupt than prevent it, not quite as above (not checking is
4691 * a smaller optimization than not toggling the interrupt enable,
4692 * since checking doesn't involve PCI accesses and toggling require
4693 * the status check). So toggling would probably be a pessimization
4694 * even with MSI. It would only be needed for using a task queue.
4696 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4699 * Do the mandatory PCI flush as well as get the link status.
4701 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
4703 /* Make sure the descriptor ring indexes are coherent. */
4704 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4705 sc->bge_cdata.bge_status_map,
4706 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4707 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4708 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4709 sc->bge_ldata.bge_status_block->bge_status = 0;
4710 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4711 sc->bge_cdata.bge_status_map,
4712 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4714 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4715 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4716 statusword || sc->bge_link_evt)
4719 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4720 /* Check RX return ring producer/consumer. */
4721 bge_rxeof(sc, rx_prod, 1);
4724 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4725 /* Check TX ring producer/consumer. */
4726 bge_txeof(sc, tx_cons);
4729 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
4730 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
4731 bge_start_locked(ifp);
4737 bge_asf_driver_up(struct bge_softc *sc)
4739 if (sc->bge_asf_mode & ASF_STACKUP) {
4740 /* Send ASF heartbeat aprox. every 2s */
4741 if (sc->bge_asf_count)
4742 sc->bge_asf_count --;
4744 sc->bge_asf_count = 2;
4745 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4746 BGE_FW_CMD_DRV_ALIVE);
4747 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4748 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
4749 BGE_FW_HB_TIMEOUT_SEC);
4750 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
4751 CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4752 BGE_RX_CPU_DRV_EVENT);
4760 struct bge_softc *sc = xsc;
4761 struct mii_data *mii = NULL;
4763 BGE_LOCK_ASSERT(sc);
4765 /* Synchronize with possible callout reset/stop. */
4766 if (callout_pending(&sc->bge_stat_ch) ||
4767 !callout_active(&sc->bge_stat_ch))
4770 if (BGE_IS_5705_PLUS(sc))
4771 bge_stats_update_regs(sc);
4773 bge_stats_update(sc);
4775 /* XXX Add APE heartbeat check here? */
4777 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4778 mii = device_get_softc(sc->bge_miibus);
4780 * Do not touch PHY if we have link up. This could break
4781 * IPMI/ASF mode or produce extra input errors
4782 * (extra errors was reported for bcm5701 & bcm5704).
4788 * Since in TBI mode auto-polling can't be used we should poll
4789 * link status manually. Here we register pending link event
4790 * and trigger interrupt.
4792 #ifdef DEVICE_POLLING
4793 /* In polling mode we poll link state in bge_poll(). */
4794 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
4798 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4799 sc->bge_flags & BGE_FLAG_5788)
4800 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4802 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4806 bge_asf_driver_up(sc);
4809 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4813 bge_stats_update_regs(struct bge_softc *sc)
4816 struct bge_mac_stats *stats;
4820 stats = &sc->bge_mac_stats;
4822 stats->ifHCOutOctets +=
4823 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4824 stats->etherStatsCollisions +=
4825 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4826 stats->outXonSent +=
4827 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4828 stats->outXoffSent +=
4829 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4830 stats->dot3StatsInternalMacTransmitErrors +=
4831 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4832 stats->dot3StatsSingleCollisionFrames +=
4833 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4834 stats->dot3StatsMultipleCollisionFrames +=
4835 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4836 stats->dot3StatsDeferredTransmissions +=
4837 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4838 stats->dot3StatsExcessiveCollisions +=
4839 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4840 stats->dot3StatsLateCollisions +=
4841 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4842 stats->ifHCOutUcastPkts +=
4843 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4844 stats->ifHCOutMulticastPkts +=
4845 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4846 stats->ifHCOutBroadcastPkts +=
4847 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4849 stats->ifHCInOctets +=
4850 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4851 stats->etherStatsFragments +=
4852 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4853 stats->ifHCInUcastPkts +=
4854 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4855 stats->ifHCInMulticastPkts +=
4856 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4857 stats->ifHCInBroadcastPkts +=
4858 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4859 stats->dot3StatsFCSErrors +=
4860 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4861 stats->dot3StatsAlignmentErrors +=
4862 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4863 stats->xonPauseFramesReceived +=
4864 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4865 stats->xoffPauseFramesReceived +=
4866 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4867 stats->macControlFramesReceived +=
4868 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4869 stats->xoffStateEntered +=
4870 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4871 stats->dot3StatsFramesTooLong +=
4872 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4873 stats->etherStatsJabbers +=
4874 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4875 stats->etherStatsUndersizePkts +=
4876 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4878 stats->FramesDroppedDueToFilters +=
4879 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4880 stats->DmaWriteQueueFull +=
4881 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4882 stats->DmaWriteHighPriQueueFull +=
4883 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4884 stats->NoMoreRxBDs +=
4885 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4888 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS
4889 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0
4890 * includes number of unwanted multicast frames. This comes
4891 * from silicon bug and known workaround to get rough(not
4892 * exact) counter is to enable interrupt on MBUF low water
4893 * attention. This can be accomplished by setting
4894 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE,
4895 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and
4896 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL.
4897 * However that change would generate more interrupts and
4898 * there are still possibilities of losing multiple frames
4899 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling.
4900 * Given that the workaround still would not get correct
4901 * counter I don't think it's worth to implement it. So
4902 * ignore reading the counter on controllers that have the
4905 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
4906 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
4907 sc->bge_chipid != BGE_CHIPID_BCM5720_A0)
4908 stats->InputDiscards +=
4909 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4910 stats->InputErrors +=
4911 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4912 stats->RecvThresholdHit +=
4913 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4915 ifp->if_collisions = (u_long)stats->etherStatsCollisions;
4916 ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards +
4917 stats->InputErrors);
4919 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
4921 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS
4922 * frames, it's safe to disable workaround for DMA engine's
4923 * miscalculation of TXMBUF space.
4925 if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts +
4926 stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) {
4927 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
4928 if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
4929 val &= ~BGE_RDMA_TX_LENGTH_WA_5719;
4931 val &= ~BGE_RDMA_TX_LENGTH_WA_5720;
4932 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
4933 sc->bge_flags &= ~BGE_FLAG_RDMA_BUG;
4939 bge_stats_clear_regs(struct bge_softc *sc)
4942 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4943 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4944 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4945 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4946 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4947 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4948 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4949 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4950 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4951 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4952 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4953 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4954 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4956 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4957 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4958 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4959 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4960 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4961 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4962 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4963 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4964 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4965 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4966 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4967 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4968 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4969 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4971 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4972 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4973 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4974 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4975 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4976 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4977 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4981 bge_stats_update(struct bge_softc *sc)
4985 uint32_t cnt; /* current register value */
4989 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
4991 #define READ_STAT(sc, stats, stat) \
4992 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
4994 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
4995 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
4996 sc->bge_tx_collisions = cnt;
4998 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo);
4999 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_nobds);
5000 sc->bge_rx_nobds = cnt;
5001 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo);
5002 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_inerrs);
5003 sc->bge_rx_inerrs = cnt;
5004 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
5005 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
5006 sc->bge_rx_discards = cnt;
5008 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
5009 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
5010 sc->bge_tx_discards = cnt;
5016 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
5017 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
5018 * but when such padded frames employ the bge IP/TCP checksum offload,
5019 * the hardware checksum assist gives incorrect results (possibly
5020 * from incorporating its own padding into the UDP/TCP checksum; who knows).
5021 * If we pad such runts with zeros, the onboard checksum comes out correct.
5024 bge_cksum_pad(struct mbuf *m)
5026 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
5029 /* If there's only the packet-header and we can pad there, use it. */
5030 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
5031 M_TRAILINGSPACE(m) >= padlen) {
5035 * Walk packet chain to find last mbuf. We will either
5036 * pad there, or append a new mbuf and pad it.
5038 for (last = m; last->m_next != NULL; last = last->m_next);
5039 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
5040 /* Allocate new empty mbuf, pad it. Compact later. */
5043 MGET(n, M_NOWAIT, MT_DATA);
5052 /* Now zero the pad area, to avoid the bge cksum-assist bug. */
5053 memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
5054 last->m_len += padlen;
5055 m->m_pkthdr.len += padlen;
5060 static struct mbuf *
5061 bge_check_short_dma(struct mbuf *m)
5067 * If device receive two back-to-back send BDs with less than
5068 * or equal to 8 total bytes then the device may hang. The two
5069 * back-to-back send BDs must in the same frame for this failure
5070 * to occur. Scan mbuf chains and see whether two back-to-back
5071 * send BDs are there. If this is the case, allocate new mbuf
5072 * and copy the frame to workaround the silicon bug.
5074 for (n = m, found = 0; n != NULL; n = n->m_next) {
5085 n = m_defrag(m, M_NOWAIT);
5093 static struct mbuf *
5094 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
5103 if (M_WRITABLE(m) == 0) {
5104 /* Get a writable copy. */
5105 n = m_dup(m, M_NOWAIT);
5111 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
5114 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5115 poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
5116 m = m_pullup(m, poff + sizeof(struct tcphdr));
5119 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5120 m = m_pullup(m, poff + (tcp->th_off << 2));
5124 * It seems controller doesn't modify IP length and TCP pseudo
5125 * checksum. These checksum computed by upper stack should be 0.
5127 *mss = m->m_pkthdr.tso_segsz;
5128 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5130 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
5131 /* Clear pseudo checksum computed by TCP stack. */
5132 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5135 * Broadcom controllers uses different descriptor format for
5136 * TSO depending on ASIC revision. Due to TSO-capable firmware
5137 * license issue and lower performance of firmware based TSO
5138 * we only support hardware based TSO.
5140 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */
5141 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
5142 if (sc->bge_flags & BGE_FLAG_TSO3) {
5144 * For BCM5717 and newer controllers, hardware based TSO
5145 * uses the 14 lower bits of the bge_mss field to store the
5146 * MSS and the upper 2 bits to store the lowest 2 bits of
5147 * the IP/TCP header length. The upper 6 bits of the header
5148 * length are stored in the bge_flags[14:10,4] field. Jumbo
5149 * frames are supported.
5151 *mss |= ((hlen & 0x3) << 14);
5152 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2);
5155 * For BCM5755 and newer controllers, hardware based TSO uses
5156 * the lower 11 bits to store the MSS and the upper 5 bits to
5157 * store the IP/TCP header length. Jumbo frames are not
5160 *mss |= (hlen << 11);
5166 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
5167 * pointers to descriptors.
5170 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
5172 bus_dma_segment_t segs[BGE_NSEG_NEW];
5174 struct bge_tx_bd *d;
5175 struct mbuf *m = *m_head;
5176 uint32_t idx = *txidx;
5177 uint16_t csum_flags, mss, vlan_tag;
5178 int nsegs, i, error;
5183 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
5184 m->m_next != NULL) {
5185 *m_head = bge_check_short_dma(m);
5186 if (*m_head == NULL)
5190 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5191 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
5192 if (*m_head == NULL)
5194 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
5195 BGE_TXBDFLAG_CPU_POST_DMA;
5196 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
5197 if (m->m_pkthdr.csum_flags & CSUM_IP)
5198 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
5199 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
5200 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
5201 if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
5202 (error = bge_cksum_pad(m)) != 0) {
5210 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
5211 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
5212 m->m_pkthdr.len > ETHER_MAX_LEN)
5213 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME;
5214 if (sc->bge_forced_collapse > 0 &&
5215 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
5217 * Forcedly collapse mbuf chains to overcome hardware
5218 * limitation which only support a single outstanding
5219 * DMA read operation.
5221 if (sc->bge_forced_collapse == 1)
5222 m = m_defrag(m, M_NOWAIT);
5224 m = m_collapse(m, M_NOWAIT,
5225 sc->bge_forced_collapse);
5232 map = sc->bge_cdata.bge_tx_dmamap[idx];
5233 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
5234 &nsegs, BUS_DMA_NOWAIT);
5235 if (error == EFBIG) {
5236 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW);
5243 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
5244 m, segs, &nsegs, BUS_DMA_NOWAIT);
5250 } else if (error != 0)
5253 /* Check if we have enough free send BDs. */
5254 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
5255 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5259 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
5261 if (m->m_flags & M_VLANTAG) {
5262 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
5263 vlan_tag = m->m_pkthdr.ether_vtag;
5266 if (sc->bge_asicrev == BGE_ASICREV_BCM5762 &&
5267 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5269 * 5725 family of devices corrupts TSO packets when TSO DMA
5270 * buffers cross into regions which are within MSS bytes of
5271 * a 4GB boundary. If we encounter the condition, drop the
5274 for (i = 0; ; i++) {
5275 d = &sc->bge_ldata.bge_tx_ring[idx];
5276 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5277 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5278 d->bge_len = segs[i].ds_len;
5279 if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss <
5280 d->bge_addr.bge_addr_lo)
5282 d->bge_flags = csum_flags;
5283 d->bge_vlan_tag = vlan_tag;
5287 BGE_INC(idx, BGE_TX_RING_CNT);
5289 if (i != nsegs - 1) {
5290 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map,
5291 BUS_DMASYNC_POSTWRITE);
5292 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5298 for (i = 0; ; i++) {
5299 d = &sc->bge_ldata.bge_tx_ring[idx];
5300 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5301 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5302 d->bge_len = segs[i].ds_len;
5303 d->bge_flags = csum_flags;
5304 d->bge_vlan_tag = vlan_tag;
5308 BGE_INC(idx, BGE_TX_RING_CNT);
5312 /* Mark the last segment as end of packet... */
5313 d->bge_flags |= BGE_TXBDFLAG_END;
5316 * Insure that the map for this transmission
5317 * is placed at the array index of the last descriptor
5320 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
5321 sc->bge_cdata.bge_tx_dmamap[idx] = map;
5322 sc->bge_cdata.bge_tx_chain[idx] = m;
5323 sc->bge_txcnt += nsegs;
5325 BGE_INC(idx, BGE_TX_RING_CNT);
5332 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5333 * to the mbuf data regions directly in the transmit descriptors.
5336 bge_start_locked(struct ifnet *ifp)
5338 struct bge_softc *sc;
5339 struct mbuf *m_head;
5344 BGE_LOCK_ASSERT(sc);
5346 if (!sc->bge_link ||
5347 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
5351 prodidx = sc->bge_tx_prodidx;
5353 for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
5354 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
5355 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
5358 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
5363 * Pack the data into the transmit ring. If we
5364 * don't have room, set the OACTIVE flag and wait
5365 * for the NIC to drain the ring.
5367 if (bge_encap(sc, &m_head, &prodidx)) {
5370 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
5371 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
5377 * If there's a BPF listener, bounce a copy of this frame
5380 #ifdef ETHER_BPF_MTAP
5381 ETHER_BPF_MTAP(ifp, m_head);
5383 BPF_MTAP(ifp, m_head);
5388 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
5389 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
5391 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5392 /* 5700 b2 errata */
5393 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
5394 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5396 sc->bge_tx_prodidx = prodidx;
5399 * Set a timeout in case the chip goes out to lunch.
5401 sc->bge_timer = BGE_TX_TIMEOUT;
5406 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5407 * to the mbuf data regions directly in the transmit descriptors.
5410 bge_start(struct ifnet *ifp)
5412 struct bge_softc *sc;
5416 bge_start_locked(ifp);
5421 bge_init_locked(struct bge_softc *sc)
5427 BGE_LOCK_ASSERT(sc);
5431 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
5434 /* Cancel pending I/O and flush buffers. */
5438 bge_sig_pre_reset(sc, BGE_RESET_START);
5440 bge_sig_legacy(sc, BGE_RESET_START);
5441 bge_sig_post_reset(sc, BGE_RESET_START);
5446 * Init the various state machines, ring
5447 * control blocks and firmware.
5449 if (bge_blockinit(sc)) {
5450 device_printf(sc->bge_dev, "initialization failure\n");
5457 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
5458 ETHER_HDR_LEN + ETHER_CRC_LEN +
5459 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
5461 /* Load our MAC address. */
5462 m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
5463 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
5464 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
5466 /* Program promiscuous mode. */
5469 /* Program multicast filter. */
5472 /* Program VLAN tag stripping. */
5475 /* Override UDP checksum offloading. */
5476 if (sc->bge_forced_udpcsum == 0)
5477 sc->bge_csum_features &= ~CSUM_UDP;
5479 sc->bge_csum_features |= CSUM_UDP;
5480 if (ifp->if_capabilities & IFCAP_TXCSUM &&
5481 ifp->if_capenable & IFCAP_TXCSUM) {
5482 ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP);
5483 ifp->if_hwassist |= sc->bge_csum_features;
5487 if (bge_init_rx_ring_std(sc) != 0) {
5488 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
5494 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
5495 * memory to insure that the chip has in fact read the first
5496 * entry of the ring.
5498 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
5500 for (i = 0; i < 10; i++) {
5502 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
5503 if (v == (MCLBYTES - ETHER_ALIGN))
5507 device_printf (sc->bge_dev,
5508 "5705 A0 chip failed to load RX ring\n");
5511 /* Init jumbo RX ring. */
5512 if (BGE_IS_JUMBO_CAPABLE(sc) &&
5513 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
5514 (MCLBYTES - ETHER_ALIGN)) {
5515 if (bge_init_rx_ring_jumbo(sc) != 0) {
5516 device_printf(sc->bge_dev,
5517 "no memory for jumbo Rx buffers.\n");
5523 /* Init our RX return ring index. */
5524 sc->bge_rx_saved_considx = 0;
5526 /* Init our RX/TX stat counters. */
5527 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
5530 bge_init_tx_ring(sc);
5532 /* Enable TX MAC state machine lockup fix. */
5533 mode = CSR_READ_4(sc, BGE_TX_MODE);
5534 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
5535 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
5536 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
5537 sc->bge_asicrev == BGE_ASICREV_BCM5762) {
5538 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5539 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
5540 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5542 /* Turn on transmitter. */
5543 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
5546 /* Turn on receiver. */
5547 mode = CSR_READ_4(sc, BGE_RX_MODE);
5548 if (BGE_IS_5755_PLUS(sc))
5549 mode |= BGE_RXMODE_IPV6_ENABLE;
5550 if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
5551 mode |= BGE_RXMODE_IPV4_FRAG_FIX;
5552 CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
5556 * Set the number of good frames to receive after RX MBUF
5557 * Low Watermark has been reached. After the RX MAC receives
5558 * this number of frames, it will drop subsequent incoming
5559 * frames until the MBUF High Watermark is reached.
5561 if (BGE_IS_57765_PLUS(sc))
5562 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
5564 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
5566 /* Clear MAC statistics. */
5567 if (BGE_IS_5705_PLUS(sc))
5568 bge_stats_clear_regs(sc);
5570 /* Tell firmware we're alive. */
5571 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5573 #ifdef DEVICE_POLLING
5574 /* Disable interrupts if we are polling. */
5575 if (ifp->if_capenable & IFCAP_POLLING) {
5576 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5577 BGE_PCIMISCCTL_MASK_PCI_INTR);
5578 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5582 /* Enable host interrupts. */
5584 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
5585 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5586 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5589 ifp->if_drv_flags |= IFF_DRV_RUNNING;
5590 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5592 bge_ifmedia_upd_locked(ifp);
5594 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
5600 struct bge_softc *sc = xsc;
5603 bge_init_locked(sc);
5608 * Set media options.
5611 bge_ifmedia_upd(struct ifnet *ifp)
5613 struct bge_softc *sc = ifp->if_softc;
5617 res = bge_ifmedia_upd_locked(ifp);
5624 bge_ifmedia_upd_locked(struct ifnet *ifp)
5626 struct bge_softc *sc = ifp->if_softc;
5627 struct mii_data *mii;
5628 struct mii_softc *miisc;
5629 struct ifmedia *ifm;
5631 BGE_LOCK_ASSERT(sc);
5633 ifm = &sc->bge_ifmedia;
5635 /* If this is a 1000baseX NIC, enable the TBI port. */
5636 if (sc->bge_flags & BGE_FLAG_TBI) {
5637 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
5639 switch(IFM_SUBTYPE(ifm->ifm_media)) {
5642 * The BCM5704 ASIC appears to have a special
5643 * mechanism for programming the autoneg
5644 * advertisement registers in TBI mode.
5646 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
5648 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5649 if (sgdig & BGE_SGDIGSTS_DONE) {
5650 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5651 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5652 sgdig |= BGE_SGDIGCFG_AUTO |
5653 BGE_SGDIGCFG_PAUSE_CAP |
5654 BGE_SGDIGCFG_ASYM_PAUSE;
5655 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
5656 sgdig | BGE_SGDIGCFG_SEND);
5658 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
5663 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
5664 BGE_CLRBIT(sc, BGE_MAC_MODE,
5665 BGE_MACMODE_HALF_DUPLEX);
5667 BGE_SETBIT(sc, BGE_MAC_MODE,
5668 BGE_MACMODE_HALF_DUPLEX);
5679 mii = device_get_softc(sc->bge_miibus);
5680 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
5685 * Force an interrupt so that we will call bge_link_upd
5686 * if needed and clear any pending link state attention.
5687 * Without this we are not getting any further interrupts
5688 * for link state changes and thus will not UP the link and
5689 * not be able to send in bge_start_locked. The only
5690 * way to get things working was to receive a packet and
5692 * bge_tick should help for fiber cards and we might not
5693 * need to do this here if BGE_FLAG_TBI is set but as
5694 * we poll for fiber anyway it should not harm.
5696 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
5697 sc->bge_flags & BGE_FLAG_5788)
5698 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
5700 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
5706 * Report current media status.
5709 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
5711 struct bge_softc *sc = ifp->if_softc;
5712 struct mii_data *mii;
5716 if ((ifp->if_flags & IFF_UP) == 0) {
5720 if (sc->bge_flags & BGE_FLAG_TBI) {
5721 ifmr->ifm_status = IFM_AVALID;
5722 ifmr->ifm_active = IFM_ETHER;
5723 if (CSR_READ_4(sc, BGE_MAC_STS) &
5724 BGE_MACSTAT_TBI_PCS_SYNCHED)
5725 ifmr->ifm_status |= IFM_ACTIVE;
5727 ifmr->ifm_active |= IFM_NONE;
5731 ifmr->ifm_active |= IFM_1000_SX;
5732 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5733 ifmr->ifm_active |= IFM_HDX;
5735 ifmr->ifm_active |= IFM_FDX;
5740 mii = device_get_softc(sc->bge_miibus);
5742 ifmr->ifm_active = mii->mii_media_active;
5743 ifmr->ifm_status = mii->mii_media_status;
5749 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
5751 struct bge_softc *sc = ifp->if_softc;
5752 struct ifreq *ifr = (struct ifreq *) data;
5753 struct mii_data *mii;
5754 int flags, mask, error = 0;
5758 if (BGE_IS_JUMBO_CAPABLE(sc) ||
5759 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
5760 if (ifr->ifr_mtu < ETHERMIN ||
5761 ifr->ifr_mtu > BGE_JUMBO_MTU) {
5765 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) {
5770 if (ifp->if_mtu != ifr->ifr_mtu) {
5771 ifp->if_mtu = ifr->ifr_mtu;
5772 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5773 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5774 bge_init_locked(sc);
5781 if (ifp->if_flags & IFF_UP) {
5783 * If only the state of the PROMISC flag changed,
5784 * then just use the 'set promisc mode' command
5785 * instead of reinitializing the entire NIC. Doing
5786 * a full re-init means reloading the firmware and
5787 * waiting for it to start up, which may take a
5788 * second or two. Similarly for ALLMULTI.
5790 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5791 flags = ifp->if_flags ^ sc->bge_if_flags;
5792 if (flags & IFF_PROMISC)
5794 if (flags & IFF_ALLMULTI)
5797 bge_init_locked(sc);
5799 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5803 sc->bge_if_flags = ifp->if_flags;
5809 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
5818 if (sc->bge_flags & BGE_FLAG_TBI) {
5819 error = ifmedia_ioctl(ifp, ifr,
5820 &sc->bge_ifmedia, command);
5822 mii = device_get_softc(sc->bge_miibus);
5823 error = ifmedia_ioctl(ifp, ifr,
5824 &mii->mii_media, command);
5828 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5829 #ifdef DEVICE_POLLING
5830 if (mask & IFCAP_POLLING) {
5831 if (ifr->ifr_reqcap & IFCAP_POLLING) {
5832 error = ether_poll_register(bge_poll, ifp);
5836 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5837 BGE_PCIMISCCTL_MASK_PCI_INTR);
5838 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5839 ifp->if_capenable |= IFCAP_POLLING;
5842 error = ether_poll_deregister(ifp);
5843 /* Enable interrupt even in error case */
5845 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
5846 BGE_PCIMISCCTL_MASK_PCI_INTR);
5847 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5848 ifp->if_capenable &= ~IFCAP_POLLING;
5853 if ((mask & IFCAP_TXCSUM) != 0 &&
5854 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
5855 ifp->if_capenable ^= IFCAP_TXCSUM;
5856 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
5857 ifp->if_hwassist |= sc->bge_csum_features;
5859 ifp->if_hwassist &= ~sc->bge_csum_features;
5862 if ((mask & IFCAP_RXCSUM) != 0 &&
5863 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
5864 ifp->if_capenable ^= IFCAP_RXCSUM;
5866 if ((mask & IFCAP_TSO4) != 0 &&
5867 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
5868 ifp->if_capenable ^= IFCAP_TSO4;
5869 if ((ifp->if_capenable & IFCAP_TSO4) != 0)
5870 ifp->if_hwassist |= CSUM_TSO;
5872 ifp->if_hwassist &= ~CSUM_TSO;
5875 if (mask & IFCAP_VLAN_MTU) {
5876 ifp->if_capenable ^= IFCAP_VLAN_MTU;
5877 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5881 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
5882 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
5883 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
5884 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
5885 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
5886 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
5887 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
5888 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
5893 #ifdef VLAN_CAPABILITIES
5894 VLAN_CAPABILITIES(ifp);
5898 error = ether_ioctl(ifp, command, data);
5906 bge_watchdog(struct bge_softc *sc)
5911 BGE_LOCK_ASSERT(sc);
5913 if (sc->bge_timer == 0 || --sc->bge_timer)
5916 /* If pause frames are active then don't reset the hardware. */
5917 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) {
5918 status = CSR_READ_4(sc, BGE_RX_STS);
5919 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) {
5921 * If link partner has us in XOFF state then wait for
5922 * the condition to clear.
5924 CSR_WRITE_4(sc, BGE_RX_STS, status);
5925 sc->bge_timer = BGE_TX_TIMEOUT;
5927 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 &&
5928 (status & BGE_RXSTAT_RCVD_XON) != 0) {
5930 * If link partner has us in XOFF state then wait for
5931 * the condition to clear.
5933 CSR_WRITE_4(sc, BGE_RX_STS, status);
5934 sc->bge_timer = BGE_TX_TIMEOUT;
5938 * Any other condition is unexpected and the controller
5945 if_printf(ifp, "watchdog timeout -- resetting\n");
5947 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5948 bge_init_locked(sc);
5954 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
5958 BGE_CLRBIT(sc, reg, bit);
5960 for (i = 0; i < BGE_TIMEOUT; i++) {
5961 if ((CSR_READ_4(sc, reg) & bit) == 0)
5968 * Stop the adapter and free any mbufs allocated to the
5972 bge_stop(struct bge_softc *sc)
5976 BGE_LOCK_ASSERT(sc);
5980 callout_stop(&sc->bge_stat_ch);
5982 /* Disable host interrupts. */
5983 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5984 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5987 * Tell firmware we're shutting down.
5990 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
5993 * Disable all of the receiver blocks.
5995 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
5996 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
5997 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
5998 if (BGE_IS_5700_FAMILY(sc))
5999 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
6000 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
6001 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
6002 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
6005 * Disable all of the transmit blocks.
6007 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
6008 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
6009 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
6010 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
6011 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
6012 if (BGE_IS_5700_FAMILY(sc))
6013 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
6014 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
6017 * Shut down all of the memory managers and related
6020 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
6021 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
6022 if (BGE_IS_5700_FAMILY(sc))
6023 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
6025 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
6026 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
6027 if (!(BGE_IS_5705_PLUS(sc))) {
6028 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
6029 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
6031 /* Update MAC statistics. */
6032 if (BGE_IS_5705_PLUS(sc))
6033 bge_stats_update_regs(sc);
6036 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
6037 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
6040 * Keep the ASF firmware running if up.
6042 if (sc->bge_asf_mode & ASF_STACKUP)
6043 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6045 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6047 /* Free the RX lists. */
6048 bge_free_rx_ring_std(sc);
6050 /* Free jumbo RX list. */
6051 if (BGE_IS_JUMBO_CAPABLE(sc))
6052 bge_free_rx_ring_jumbo(sc);
6054 /* Free TX buffers. */
6055 bge_free_tx_ring(sc);
6057 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
6059 /* Clear MAC's link state (PHY may still have link UP). */
6060 if (bootverbose && sc->bge_link)
6061 if_printf(sc->bge_ifp, "link DOWN\n");
6064 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
6068 * Stop all chip I/O so that the kernel's probe routines don't
6069 * get confused by errant DMAs when rebooting.
6072 bge_shutdown(device_t dev)
6074 struct bge_softc *sc;
6076 sc = device_get_softc(dev);
6085 bge_suspend(device_t dev)
6087 struct bge_softc *sc;
6089 sc = device_get_softc(dev);
6098 bge_resume(device_t dev)
6100 struct bge_softc *sc;
6103 sc = device_get_softc(dev);
6106 if (ifp->if_flags & IFF_UP) {
6107 bge_init_locked(sc);
6108 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
6109 bge_start_locked(ifp);
6117 bge_link_upd(struct bge_softc *sc)
6119 struct mii_data *mii;
6120 uint32_t link, status;
6122 BGE_LOCK_ASSERT(sc);
6124 /* Clear 'pending link event' flag. */
6125 sc->bge_link_evt = 0;
6128 * Process link state changes.
6129 * Grrr. The link status word in the status block does
6130 * not work correctly on the BCM5700 rev AX and BX chips,
6131 * according to all available information. Hence, we have
6132 * to enable MII interrupts in order to properly obtain
6133 * async link changes. Unfortunately, this also means that
6134 * we have to read the MAC status register to detect link
6135 * changes, thereby adding an additional register access to
6136 * the interrupt handler.
6138 * XXX: perhaps link state detection procedure used for
6139 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
6142 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6143 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
6144 status = CSR_READ_4(sc, BGE_MAC_STS);
6145 if (status & BGE_MACSTAT_MI_INTERRUPT) {
6146 mii = device_get_softc(sc->bge_miibus);
6148 if (!sc->bge_link &&
6149 mii->mii_media_status & IFM_ACTIVE &&
6150 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6153 if_printf(sc->bge_ifp, "link UP\n");
6154 } else if (sc->bge_link &&
6155 (!(mii->mii_media_status & IFM_ACTIVE) ||
6156 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6159 if_printf(sc->bge_ifp, "link DOWN\n");
6162 /* Clear the interrupt. */
6163 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
6164 BGE_EVTENB_MI_INTERRUPT);
6165 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
6167 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
6168 BRGPHY_MII_IMR, BRGPHY_INTRS);
6173 if (sc->bge_flags & BGE_FLAG_TBI) {
6174 status = CSR_READ_4(sc, BGE_MAC_STS);
6175 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
6176 if (!sc->bge_link) {
6178 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
6179 BGE_CLRBIT(sc, BGE_MAC_MODE,
6180 BGE_MACMODE_TBI_SEND_CFGS);
6183 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
6185 if_printf(sc->bge_ifp, "link UP\n");
6186 if_link_state_change(sc->bge_ifp,
6189 } else if (sc->bge_link) {
6192 if_printf(sc->bge_ifp, "link DOWN\n");
6193 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
6195 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
6197 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
6198 * in status word always set. Workaround this bug by reading
6199 * PHY link status directly.
6201 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
6203 if (link != sc->bge_link ||
6204 sc->bge_asicrev == BGE_ASICREV_BCM5700) {
6205 mii = device_get_softc(sc->bge_miibus);
6207 if (!sc->bge_link &&
6208 mii->mii_media_status & IFM_ACTIVE &&
6209 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6212 if_printf(sc->bge_ifp, "link UP\n");
6213 } else if (sc->bge_link &&
6214 (!(mii->mii_media_status & IFM_ACTIVE) ||
6215 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6218 if_printf(sc->bge_ifp, "link DOWN\n");
6223 * For controllers that call mii_tick, we have to poll
6226 mii = device_get_softc(sc->bge_miibus);
6228 bge_miibus_statchg(sc->bge_dev);
6231 /* Disable MAC attention when link is up. */
6232 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
6233 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
6234 BGE_MACSTAT_LINK_CHANGED);
6238 bge_add_sysctls(struct bge_softc *sc)
6240 struct sysctl_ctx_list *ctx;
6241 struct sysctl_oid_list *children;
6245 ctx = device_get_sysctl_ctx(sc->bge_dev);
6246 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
6248 #ifdef BGE_REGISTER_DEBUG
6249 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
6250 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
6251 "Debug Information");
6253 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
6254 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
6255 "MAC Register Read");
6257 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read",
6258 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I",
6259 "APE Register Read");
6261 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
6262 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
6267 unit = device_get_unit(sc->bge_dev);
6269 * A common design characteristic for many Broadcom client controllers
6270 * is that they only support a single outstanding DMA read operation
6271 * on the PCIe bus. This means that it will take twice as long to fetch
6272 * a TX frame that is split into header and payload buffers as it does
6273 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
6274 * these controllers, coalescing buffers to reduce the number of memory
6275 * reads is effective way to get maximum performance(about 940Mbps).
6276 * Without collapsing TX buffers the maximum TCP bulk transfer
6277 * performance is about 850Mbps. However forcing coalescing mbufs
6278 * consumes a lot of CPU cycles, so leave it off by default.
6280 sc->bge_forced_collapse = 0;
6281 snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit);
6282 TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse);
6283 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
6284 CTLFLAG_RW, &sc->bge_forced_collapse, 0,
6285 "Number of fragmented TX buffers of a frame allowed before "
6286 "forced collapsing");
6289 snprintf(tn, sizeof(tn), "dev.bge.%d.msi", unit);
6290 TUNABLE_INT_FETCH(tn, &sc->bge_msi);
6291 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi",
6292 CTLFLAG_RD, &sc->bge_msi, 0, "Enable MSI");
6295 * It seems all Broadcom controllers have a bug that can generate UDP
6296 * datagrams with checksum value 0 when TX UDP checksum offloading is
6297 * enabled. Generating UDP checksum value 0 is RFC 768 violation.
6298 * Even though the probability of generating such UDP datagrams is
6299 * low, I don't want to see FreeBSD boxes to inject such datagrams
6300 * into network so disable UDP checksum offloading by default. Users
6301 * still override this behavior by setting a sysctl variable,
6302 * dev.bge.0.forced_udpcsum.
6304 sc->bge_forced_udpcsum = 0;
6305 snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit);
6306 TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum);
6307 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum",
6308 CTLFLAG_RW, &sc->bge_forced_udpcsum, 0,
6309 "Enable UDP checksum offloading even if controller can "
6310 "generate UDP checksum value 0");
6312 if (BGE_IS_5705_PLUS(sc))
6313 bge_add_sysctl_stats_regs(sc, ctx, children);
6315 bge_add_sysctl_stats(sc, ctx, children);
6318 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
6319 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
6320 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
6324 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6325 struct sysctl_oid_list *parent)
6327 struct sysctl_oid *tree;
6328 struct sysctl_oid_list *children, *schildren;
6330 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6331 NULL, "BGE Statistics");
6332 schildren = children = SYSCTL_CHILDREN(tree);
6333 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
6334 children, COSFramesDroppedDueToFilters,
6335 "FramesDroppedDueToFilters");
6336 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
6337 children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
6338 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
6339 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
6340 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
6341 children, nicNoMoreRxBDs, "NoMoreRxBDs");
6342 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
6343 children, ifInDiscards, "InputDiscards");
6344 BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
6345 children, ifInErrors, "InputErrors");
6346 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
6347 children, nicRecvThresholdHit, "RecvThresholdHit");
6348 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
6349 children, nicDmaReadQueueFull, "DmaReadQueueFull");
6350 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
6351 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
6352 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
6353 children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
6354 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
6355 children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
6356 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
6357 children, nicRingStatusUpdate, "RingStatusUpdate");
6358 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
6359 children, nicInterrupts, "Interrupts");
6360 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
6361 children, nicAvoidedInterrupts, "AvoidedInterrupts");
6362 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
6363 children, nicSendThresholdHit, "SendThresholdHit");
6365 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
6366 NULL, "BGE RX Statistics");
6367 children = SYSCTL_CHILDREN(tree);
6368 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
6369 children, rxstats.ifHCInOctets, "ifHCInOctets");
6370 BGE_SYSCTL_STAT(sc, ctx, "Fragments",
6371 children, rxstats.etherStatsFragments, "Fragments");
6372 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
6373 children, rxstats.ifHCInUcastPkts, "UnicastPkts");
6374 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
6375 children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
6376 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
6377 children, rxstats.dot3StatsFCSErrors, "FCSErrors");
6378 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
6379 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
6380 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
6381 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
6382 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
6383 children, rxstats.xoffPauseFramesReceived,
6384 "xoffPauseFramesReceived");
6385 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
6386 children, rxstats.macControlFramesReceived,
6387 "ControlFramesReceived");
6388 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
6389 children, rxstats.xoffStateEntered, "xoffStateEntered");
6390 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
6391 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
6392 BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
6393 children, rxstats.etherStatsJabbers, "Jabbers");
6394 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
6395 children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
6396 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
6397 children, rxstats.inRangeLengthError, "inRangeLengthError");
6398 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
6399 children, rxstats.outRangeLengthError, "outRangeLengthError");
6401 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
6402 NULL, "BGE TX Statistics");
6403 children = SYSCTL_CHILDREN(tree);
6404 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
6405 children, txstats.ifHCOutOctets, "ifHCOutOctets");
6406 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
6407 children, txstats.etherStatsCollisions, "Collisions");
6408 BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
6409 children, txstats.outXonSent, "XonSent");
6410 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
6411 children, txstats.outXoffSent, "XoffSent");
6412 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
6413 children, txstats.flowControlDone, "flowControlDone");
6414 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
6415 children, txstats.dot3StatsInternalMacTransmitErrors,
6416 "InternalMacTransmitErrors");
6417 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
6418 children, txstats.dot3StatsSingleCollisionFrames,
6419 "SingleCollisionFrames");
6420 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
6421 children, txstats.dot3StatsMultipleCollisionFrames,
6422 "MultipleCollisionFrames");
6423 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
6424 children, txstats.dot3StatsDeferredTransmissions,
6425 "DeferredTransmissions");
6426 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
6427 children, txstats.dot3StatsExcessiveCollisions,
6428 "ExcessiveCollisions");
6429 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
6430 children, txstats.dot3StatsLateCollisions,
6432 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
6433 children, txstats.ifHCOutUcastPkts, "UnicastPkts");
6434 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
6435 children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
6436 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
6437 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
6438 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
6439 children, txstats.dot3StatsCarrierSenseErrors,
6440 "CarrierSenseErrors");
6441 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
6442 children, txstats.ifOutDiscards, "Discards");
6443 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
6444 children, txstats.ifOutErrors, "Errors");
6447 #undef BGE_SYSCTL_STAT
6449 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
6450 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
6453 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6454 struct sysctl_oid_list *parent)
6456 struct sysctl_oid *tree;
6457 struct sysctl_oid_list *child, *schild;
6458 struct bge_mac_stats *stats;
6460 stats = &sc->bge_mac_stats;
6461 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6462 NULL, "BGE Statistics");
6463 schild = child = SYSCTL_CHILDREN(tree);
6464 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters",
6465 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters");
6466 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull",
6467 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full");
6468 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull",
6469 &stats->DmaWriteHighPriQueueFull,
6470 "NIC DMA Write High Priority Queue Full");
6471 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs",
6472 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors");
6473 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards",
6474 &stats->InputDiscards, "Discarded Input Frames");
6475 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors",
6476 &stats->InputErrors, "Input Errors");
6477 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit",
6478 &stats->RecvThresholdHit, "NIC Recv Threshold Hit");
6480 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD,
6481 NULL, "BGE RX Statistics");
6482 child = SYSCTL_CHILDREN(tree);
6483 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets",
6484 &stats->ifHCInOctets, "Inbound Octets");
6485 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments",
6486 &stats->etherStatsFragments, "Fragments");
6487 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6488 &stats->ifHCInUcastPkts, "Inbound Unicast Packets");
6489 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6490 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets");
6491 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6492 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets");
6493 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors",
6494 &stats->dot3StatsFCSErrors, "FCS Errors");
6495 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors",
6496 &stats->dot3StatsAlignmentErrors, "Alignment Errors");
6497 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived",
6498 &stats->xonPauseFramesReceived, "XON Pause Frames Received");
6499 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived",
6500 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received");
6501 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived",
6502 &stats->macControlFramesReceived, "MAC Control Frames Received");
6503 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered",
6504 &stats->xoffStateEntered, "XOFF State Entered");
6505 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong",
6506 &stats->dot3StatsFramesTooLong, "Frames Too Long");
6507 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers",
6508 &stats->etherStatsJabbers, "Jabbers");
6509 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts",
6510 &stats->etherStatsUndersizePkts, "Undersized Packets");
6512 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD,
6513 NULL, "BGE TX Statistics");
6514 child = SYSCTL_CHILDREN(tree);
6515 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets",
6516 &stats->ifHCOutOctets, "Outbound Octets");
6517 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions",
6518 &stats->etherStatsCollisions, "TX Collisions");
6519 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent",
6520 &stats->outXonSent, "XON Sent");
6521 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent",
6522 &stats->outXoffSent, "XOFF Sent");
6523 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors",
6524 &stats->dot3StatsInternalMacTransmitErrors,
6525 "Internal MAC TX Errors");
6526 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames",
6527 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames");
6528 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames",
6529 &stats->dot3StatsMultipleCollisionFrames,
6530 "Multiple Collision Frames");
6531 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions",
6532 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions");
6533 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions",
6534 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions");
6535 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions",
6536 &stats->dot3StatsLateCollisions, "Late Collisions");
6537 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6538 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets");
6539 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6540 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets");
6541 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6542 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets");
6545 #undef BGE_SYSCTL_STAT_ADD64
6548 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
6550 struct bge_softc *sc;
6554 sc = (struct bge_softc *)arg1;
6556 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
6557 offsetof(bge_hostaddr, bge_addr_lo));
6558 return (sysctl_handle_int(oidp, &result, 0, req));
6561 #ifdef BGE_REGISTER_DEBUG
6563 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
6565 struct bge_softc *sc;
6567 int error, result, sbsz;
6571 error = sysctl_handle_int(oidp, &result, 0, req);
6572 if (error || (req->newptr == NULL))
6576 sc = (struct bge_softc *)arg1;
6578 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6579 sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
6580 sbsz = BGE_STATUS_BLK_SZ;
6583 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
6584 printf("Status Block:\n");
6586 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6587 sc->bge_cdata.bge_status_map,
6588 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6589 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) {
6591 for (j = 0; j < 8; j++)
6592 printf(" %04x", sbdata[i++]);
6596 printf("Registers:\n");
6597 for (i = 0x800; i < 0xA00; ) {
6599 for (j = 0; j < 8; j++) {
6600 printf(" %08x", CSR_READ_4(sc, i));
6607 printf("Hardware Flags:\n");
6608 if (BGE_IS_5717_PLUS(sc))
6609 printf(" - 5717 Plus\n");
6610 if (BGE_IS_5755_PLUS(sc))
6611 printf(" - 5755 Plus\n");
6612 if (BGE_IS_575X_PLUS(sc))
6613 printf(" - 575X Plus\n");
6614 if (BGE_IS_5705_PLUS(sc))
6615 printf(" - 5705 Plus\n");
6616 if (BGE_IS_5714_FAMILY(sc))
6617 printf(" - 5714 Family\n");
6618 if (BGE_IS_5700_FAMILY(sc))
6619 printf(" - 5700 Family\n");
6620 if (sc->bge_flags & BGE_FLAG_JUMBO)
6621 printf(" - Supports Jumbo Frames\n");
6622 if (sc->bge_flags & BGE_FLAG_PCIX)
6623 printf(" - PCI-X Bus\n");
6624 if (sc->bge_flags & BGE_FLAG_PCIE)
6625 printf(" - PCI Express Bus\n");
6626 if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
6627 printf(" - No 3 LEDs\n");
6628 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
6629 printf(" - RX Alignment Bug\n");
6636 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6638 struct bge_softc *sc;
6644 error = sysctl_handle_int(oidp, &result, 0, req);
6645 if (error || (req->newptr == NULL))
6648 if (result < 0x8000) {
6649 sc = (struct bge_softc *)arg1;
6650 val = CSR_READ_4(sc, result);
6651 printf("reg 0x%06X = 0x%08X\n", result, val);
6658 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS)
6660 struct bge_softc *sc;
6666 error = sysctl_handle_int(oidp, &result, 0, req);
6667 if (error || (req->newptr == NULL))
6670 if (result < 0x8000) {
6671 sc = (struct bge_softc *)arg1;
6672 val = APE_READ_4(sc, result);
6673 printf("reg 0x%06X = 0x%08X\n", result, val);
6680 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
6682 struct bge_softc *sc;
6688 error = sysctl_handle_int(oidp, &result, 0, req);
6689 if (error || (req->newptr == NULL))
6692 if (result < 0x8000) {
6693 sc = (struct bge_softc *)arg1;
6694 val = bge_readmem_ind(sc, result);
6695 printf("mem 0x%06X = 0x%08X\n", result, val);
6703 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
6706 if (sc->bge_flags & BGE_FLAG_EADDR)
6710 OF_getetheraddr(sc->bge_dev, ether_addr);
6717 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
6721 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
6722 if ((mac_addr >> 16) == 0x484b) {
6723 ether_addr[0] = (uint8_t)(mac_addr >> 8);
6724 ether_addr[1] = (uint8_t)mac_addr;
6725 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
6726 ether_addr[2] = (uint8_t)(mac_addr >> 24);
6727 ether_addr[3] = (uint8_t)(mac_addr >> 16);
6728 ether_addr[4] = (uint8_t)(mac_addr >> 8);
6729 ether_addr[5] = (uint8_t)mac_addr;
6736 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
6738 int mac_offset = BGE_EE_MAC_OFFSET;
6740 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6741 mac_offset = BGE_EE_MAC_OFFSET_5906;
6743 return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
6748 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
6751 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6754 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
6759 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
6761 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
6762 /* NOTE: Order is critical */
6765 bge_get_eaddr_nvram,
6766 bge_get_eaddr_eeprom,
6769 const bge_eaddr_fcn_t *func;
6771 for (func = bge_eaddr_funcs; *func != NULL; ++func) {
6772 if ((*func)(sc, eaddr) == 0)
6775 return (*func == NULL ? ENXIO : 0);