sys/dev/bge/if_bge.c

   1 /*-
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/cdefs.h>
  35 __FBSDID("$FreeBSD$");
  36
  37 /*
  38  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  39  *
  40  * The Broadcom BCM5700 is based on technology originally developed by
  41  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  42  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  43  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  44  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  45  * frames, highly configurable RX filtering, and 16 RX and TX queues
  46  * (which, along with RX filter rules, can be used for QOS applications).
  47  * Other features, such as TCP segmentation, may be available as part
  48  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  49  * firmware images can be stored in hardware and need not be compiled
  50  * into the driver.
  51  *
  52  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  53  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  54  *
  55  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  56  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  57  * does not support external SSRAM.
  58  *
  59  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  60  * brand name, which is functionally similar but lacks PCI-X support.
  61  *
  62  * Without external SSRAM, you can only have at most 4 TX rings,
  63  * and the use of the mini RX ring is disabled. This seems to imply
  64  * that these features are simply not available on the BCM5701. As a
  65  * result, this driver does not implement any support for the mini RX
  66  * ring.
  67  */
  68
  69 #ifdef HAVE_KERNEL_OPTION_HEADERS
  70 #include "opt_device_polling.h"
  71 #endif
  72
  73 #include <sys/param.h>
  74 #include <sys/endian.h>
  75 #include <sys/systm.h>
  76 #include <sys/sockio.h>
  77 #include <sys/mbuf.h>
  78 #include <sys/malloc.h>
  79 #include <sys/kernel.h>
  80 #include <sys/module.h>
  81 #include <sys/socket.h>
  82 #include <sys/sysctl.h>
  83 #include <sys/taskqueue.h>
  84
  85 #include <net/if.h>
  86 #include <net/if_arp.h>
  87 #include <net/ethernet.h>
  88 #include <net/if_dl.h>
  89 #include <net/if_media.h>
  90
  91 #include <net/bpf.h>
  92
  93 #include <net/if_types.h>
  94 #include <net/if_vlan_var.h>
  95
  96 #include <netinet/in_systm.h>
  97 #include <netinet/in.h>
  98 #include <netinet/ip.h>
  99 #include <netinet/tcp.h>
 100
 101 #include <machine/bus.h>
 102 #include <machine/resource.h>
 103 #include <sys/bus.h>
 104 #include <sys/rman.h>
 105
 106 #include <dev/mii/mii.h>
 107 #include <dev/mii/miivar.h>
 108 #include "miidevs.h"
 109 #include <dev/mii/brgphyreg.h>
 110
 111 #ifdef __sparc64__
 112 #include <dev/ofw/ofw_bus.h>
 113 #include <dev/ofw/openfirm.h>
 114 #include <machine/ofw_machdep.h>
 115 #include <machine/ver.h>
 116 #endif
 117
 118 #include <dev/pci/pcireg.h>
 119 #include <dev/pci/pcivar.h>
 120
 121 #include <dev/bge/if_bgereg.h>
 122
 123 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 124 #define ETHER_MIN_NOPAD         (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
 125
 126 MODULE_DEPEND(bge, pci, 1, 1, 1);
 127 MODULE_DEPEND(bge, ether, 1, 1, 1);
 128 MODULE_DEPEND(bge, miibus, 1, 1, 1);
 129
 130 /* "device miibus" required.  See GENERIC if you get errors here. */
 131 #include "miibus_if.h"
 132
 133 /*
 134  * Various supported device vendors/types and their names. Note: the
 135  * spec seems to indicate that the hardware still has Alteon's vendor
 136  * ID burned into it, though it will always be overriden by the vendor
 137  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 138  */
 139 static const struct bge_type {
 140         uint16_t        bge_vid;
 141         uint16_t        bge_did;
 142 } bge_devs[] = {
 143         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5700 },
 144         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5701 },
 145
 146         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1000 },
 147         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1002 },
 148         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC9100 },
 149
 150         { APPLE_VENDORID,       APPLE_DEVICE_BCM5701 },
 151
 152         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5700 },
 153         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5701 },
 154         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702 },
 155         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702_ALT },
 156         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702X },
 157         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703 },
 158         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703_ALT },
 159         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703X },
 160         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704C },
 161         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S },
 162         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S_ALT },
 163         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705 },
 164         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705F },
 165         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705K },
 166         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M },
 167         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M_ALT },
 168         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714C },
 169         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714S },
 170         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715 },
 171         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715S },
 172         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5720 },
 173         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5721 },
 174         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5722 },
 175         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5723 },
 176         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750 },
 177         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750M },
 178         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751 },
 179         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751F },
 180         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751M },
 181         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752 },
 182         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752M },
 183         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753 },
 184         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753F },
 185         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753M },
 186         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754 },
 187         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754M },
 188         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755 },
 189         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755M },
 190         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761 },
 191         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761E },
 192         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761S },
 193         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761SE },
 194         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5764 },
 195         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780 },
 196         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780S },
 197         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5781 },
 198         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5782 },
 199         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5784 },
 200         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785F },
 201         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785G },
 202         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5786 },
 203         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787 },
 204         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787F },
 205         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787M },
 206         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5788 },
 207         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5789 },
 208         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901 },
 209         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901A2 },
 210         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5903M },
 211         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906 },
 212         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906M },
 213         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57760 },
 214         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57780 },
 215         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57788 },
 216         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57790 },
 217
 218         { SK_VENDORID,          SK_DEVICEID_ALTIMA },
 219
 220         { TC_VENDORID,          TC_DEVICEID_3C996 },
 221
 222         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE4 },
 223         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE5 },
 224         { FJTSU_VENDORID,       FJTSU_DEVICEID_PP250450 },
 225
 226         { 0, 0 }
 227 };
 228
 229 static const struct bge_vendor {
 230         uint16_t        v_id;
 231         const char      *v_name;
 232 } bge_vendors[] = {
 233         { ALTEON_VENDORID,      "Alteon" },
 234         { ALTIMA_VENDORID,      "Altima" },
 235         { APPLE_VENDORID,       "Apple" },
 236         { BCOM_VENDORID,        "Broadcom" },
 237         { SK_VENDORID,          "SysKonnect" },
 238         { TC_VENDORID,          "3Com" },
 239         { FJTSU_VENDORID,       "Fujitsu" },
 240
 241         { 0, NULL }
 242 };
 243
 244 static const struct bge_revision {
 245         uint32_t        br_chipid;
 246         const char      *br_name;
 247 } bge_revisions[] = {
 248         { BGE_CHIPID_BCM5700_A0,        "BCM5700 A0" },
 249         { BGE_CHIPID_BCM5700_A1,        "BCM5700 A1" },
 250         { BGE_CHIPID_BCM5700_B0,        "BCM5700 B0" },
 251         { BGE_CHIPID_BCM5700_B1,        "BCM5700 B1" },
 252         { BGE_CHIPID_BCM5700_B2,        "BCM5700 B2" },
 253         { BGE_CHIPID_BCM5700_B3,        "BCM5700 B3" },
 254         { BGE_CHIPID_BCM5700_ALTIMA,    "BCM5700 Altima" },
 255         { BGE_CHIPID_BCM5700_C0,        "BCM5700 C0" },
 256         { BGE_CHIPID_BCM5701_A0,        "BCM5701 A0" },
 257         { BGE_CHIPID_BCM5701_B0,        "BCM5701 B0" },
 258         { BGE_CHIPID_BCM5701_B2,        "BCM5701 B2" },
 259         { BGE_CHIPID_BCM5701_B5,        "BCM5701 B5" },
 260         { BGE_CHIPID_BCM5703_A0,        "BCM5703 A0" },
 261         { BGE_CHIPID_BCM5703_A1,        "BCM5703 A1" },
 262         { BGE_CHIPID_BCM5703_A2,        "BCM5703 A2" },
 263         { BGE_CHIPID_BCM5703_A3,        "BCM5703 A3" },
 264         { BGE_CHIPID_BCM5703_B0,        "BCM5703 B0" },
 265         { BGE_CHIPID_BCM5704_A0,        "BCM5704 A0" },
 266         { BGE_CHIPID_BCM5704_A1,        "BCM5704 A1" },
 267         { BGE_CHIPID_BCM5704_A2,        "BCM5704 A2" },
 268         { BGE_CHIPID_BCM5704_A3,        "BCM5704 A3" },
 269         { BGE_CHIPID_BCM5704_B0,        "BCM5704 B0" },
 270         { BGE_CHIPID_BCM5705_A0,        "BCM5705 A0" },
 271         { BGE_CHIPID_BCM5705_A1,        "BCM5705 A1" },
 272         { BGE_CHIPID_BCM5705_A2,        "BCM5705 A2" },
 273         { BGE_CHIPID_BCM5705_A3,        "BCM5705 A3" },
 274         { BGE_CHIPID_BCM5750_A0,        "BCM5750 A0" },
 275         { BGE_CHIPID_BCM5750_A1,        "BCM5750 A1" },
 276         { BGE_CHIPID_BCM5750_A3,        "BCM5750 A3" },
 277         { BGE_CHIPID_BCM5750_B0,        "BCM5750 B0" },
 278         { BGE_CHIPID_BCM5750_B1,        "BCM5750 B1" },
 279         { BGE_CHIPID_BCM5750_C0,        "BCM5750 C0" },
 280         { BGE_CHIPID_BCM5750_C1,        "BCM5750 C1" },
 281         { BGE_CHIPID_BCM5750_C2,        "BCM5750 C2" },
 282         { BGE_CHIPID_BCM5714_A0,        "BCM5714 A0" },
 283         { BGE_CHIPID_BCM5752_A0,        "BCM5752 A0" },
 284         { BGE_CHIPID_BCM5752_A1,        "BCM5752 A1" },
 285         { BGE_CHIPID_BCM5752_A2,        "BCM5752 A2" },
 286         { BGE_CHIPID_BCM5714_B0,        "BCM5714 B0" },
 287         { BGE_CHIPID_BCM5714_B3,        "BCM5714 B3" },
 288         { BGE_CHIPID_BCM5715_A0,        "BCM5715 A0" },
 289         { BGE_CHIPID_BCM5715_A1,        "BCM5715 A1" },
 290         { BGE_CHIPID_BCM5715_A3,        "BCM5715 A3" },
 291         { BGE_CHIPID_BCM5755_A0,        "BCM5755 A0" },
 292         { BGE_CHIPID_BCM5755_A1,        "BCM5755 A1" },
 293         { BGE_CHIPID_BCM5755_A2,        "BCM5755 A2" },
 294         { BGE_CHIPID_BCM5722_A0,        "BCM5722 A0" },
 295         { BGE_CHIPID_BCM5761_A0,        "BCM5761 A0" },
 296         { BGE_CHIPID_BCM5761_A1,        "BCM5761 A1" },
 297         { BGE_CHIPID_BCM5784_A0,        "BCM5784 A0" },
 298         { BGE_CHIPID_BCM5784_A1,        "BCM5784 A1" },
 299         /* 5754 and 5787 share the same ASIC ID */
 300         { BGE_CHIPID_BCM5787_A0,        "BCM5754/5787 A0" },
 301         { BGE_CHIPID_BCM5787_A1,        "BCM5754/5787 A1" },
 302         { BGE_CHIPID_BCM5787_A2,        "BCM5754/5787 A2" },
 303         { BGE_CHIPID_BCM5906_A1,        "BCM5906 A1" },
 304         { BGE_CHIPID_BCM5906_A2,        "BCM5906 A2" },
 305         { BGE_CHIPID_BCM57780_A0,       "BCM57780 A0" },
 306         { BGE_CHIPID_BCM57780_A1,       "BCM57780 A1" },
 307
 308         { 0, NULL }
 309 };
 310
 311 /*
 312  * Some defaults for major revisions, so that newer steppings
 313  * that we don't know about have a shot at working.
 314  */
 315 static const struct bge_revision bge_majorrevs[] = {
 316         { BGE_ASICREV_BCM5700,          "unknown BCM5700" },
 317         { BGE_ASICREV_BCM5701,          "unknown BCM5701" },
 318         { BGE_ASICREV_BCM5703,          "unknown BCM5703" },
 319         { BGE_ASICREV_BCM5704,          "unknown BCM5704" },
 320         { BGE_ASICREV_BCM5705,          "unknown BCM5705" },
 321         { BGE_ASICREV_BCM5750,          "unknown BCM5750" },
 322         { BGE_ASICREV_BCM5714_A0,       "unknown BCM5714" },
 323         { BGE_ASICREV_BCM5752,          "unknown BCM5752" },
 324         { BGE_ASICREV_BCM5780,          "unknown BCM5780" },
 325         { BGE_ASICREV_BCM5714,          "unknown BCM5714" },
 326         { BGE_ASICREV_BCM5755,          "unknown BCM5755" },
 327         { BGE_ASICREV_BCM5761,          "unknown BCM5761" },
 328         { BGE_ASICREV_BCM5784,          "unknown BCM5784" },
 329         { BGE_ASICREV_BCM5785,          "unknown BCM5785" },
 330         /* 5754 and 5787 share the same ASIC ID */
 331         { BGE_ASICREV_BCM5787,          "unknown BCM5754/5787" },
 332         { BGE_ASICREV_BCM5906,          "unknown BCM5906" },
 333         { BGE_ASICREV_BCM57780,         "unknown BCM57780" },
 334
 335         { 0, NULL }
 336 };
 337
 338 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 339 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 340 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 341 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 342 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 343 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 344
 345 const struct bge_revision * bge_lookup_rev(uint32_t);
 346 const struct bge_vendor * bge_lookup_vendor(uint16_t);
 347
 348 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 349
 350 static int bge_probe(device_t);
 351 static int bge_attach(device_t);
 352 static int bge_detach(device_t);
 353 static int bge_suspend(device_t);
 354 static int bge_resume(device_t);
 355 static void bge_release_resources(struct bge_softc *);
 356 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 357 static int bge_dma_alloc(device_t);
 358 static void bge_dma_free(struct bge_softc *);
 359
 360 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
 361 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 362 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 363 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 364 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
 365
 366 static void bge_txeof(struct bge_softc *, uint16_t);
 367 static int bge_rxeof(struct bge_softc *, uint16_t, int);
 368
 369 static void bge_asf_driver_up (struct bge_softc *);
 370 static void bge_tick(void *);
 371 static void bge_stats_update(struct bge_softc *);
 372 static void bge_stats_update_regs(struct bge_softc *);
 373 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
 374     uint16_t *);
 375 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 376
 377 static void bge_intr(void *);
 378 static int bge_msi_intr(void *);
 379 static void bge_intr_task(void *, int);
 380 static void bge_start_locked(struct ifnet *);
 381 static void bge_start(struct ifnet *);
 382 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
 383 static void bge_init_locked(struct bge_softc *);
 384 static void bge_init(void *);
 385 static void bge_stop(struct bge_softc *);
 386 static void bge_watchdog(struct bge_softc *);
 387 static int bge_shutdown(device_t);
 388 static int bge_ifmedia_upd_locked(struct ifnet *);
 389 static int bge_ifmedia_upd(struct ifnet *);
 390 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 391
 392 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 393 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 394
 395 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
 396 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
 397
 398 static void bge_setpromisc(struct bge_softc *);
 399 static void bge_setmulti(struct bge_softc *);
 400 static void bge_setvlan(struct bge_softc *);
 401
 402 static int bge_newbuf_std(struct bge_softc *, int);
 403 static int bge_newbuf_jumbo(struct bge_softc *, int);
 404 static int bge_init_rx_ring_std(struct bge_softc *);
 405 static void bge_free_rx_ring_std(struct bge_softc *);
 406 static int bge_init_rx_ring_jumbo(struct bge_softc *);
 407 static void bge_free_rx_ring_jumbo(struct bge_softc *);
 408 static void bge_free_tx_ring(struct bge_softc *);
 409 static int bge_init_tx_ring(struct bge_softc *);
 410
 411 static int bge_chipinit(struct bge_softc *);
 412 static int bge_blockinit(struct bge_softc *);
 413
 414 static int bge_has_eaddr(struct bge_softc *);
 415 static uint32_t bge_readmem_ind(struct bge_softc *, int);
 416 static void bge_writemem_ind(struct bge_softc *, int, int);
 417 static void bge_writembx(struct bge_softc *, int, int);
 418 #ifdef notdef
 419 static uint32_t bge_readreg_ind(struct bge_softc *, int);
 420 #endif
 421 static void bge_writemem_direct(struct bge_softc *, int, int);
 422 static void bge_writereg_ind(struct bge_softc *, int, int);
 423 static void bge_set_max_readrq(struct bge_softc *);
 424
 425 static int bge_miibus_readreg(device_t, int, int);
 426 static int bge_miibus_writereg(device_t, int, int, int);
 427 static void bge_miibus_statchg(device_t);
 428 #ifdef DEVICE_POLLING
 429 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 430 #endif
 431
 432 #define BGE_RESET_START 1
 433 #define BGE_RESET_STOP  2
 434 static void bge_sig_post_reset(struct bge_softc *, int);
 435 static void bge_sig_legacy(struct bge_softc *, int);
 436 static void bge_sig_pre_reset(struct bge_softc *, int);
 437 static int bge_reset(struct bge_softc *);
 438 static void bge_link_upd(struct bge_softc *);
 439
 440 /*
 441  * The BGE_REGISTER_DEBUG option is only for low-level debugging.  It may
 442  * leak information to untrusted users.  It is also known to cause alignment
 443  * traps on certain architectures.
 444  */
 445 #ifdef BGE_REGISTER_DEBUG
 446 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 447 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
 448 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
 449 #endif
 450 static void bge_add_sysctls(struct bge_softc *);
 451 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
 452
 453 static device_method_t bge_methods[] = {
 454         /* Device interface */
 455         DEVMETHOD(device_probe,         bge_probe),
 456         DEVMETHOD(device_attach,        bge_attach),
 457         DEVMETHOD(device_detach,        bge_detach),
 458         DEVMETHOD(device_shutdown,      bge_shutdown),
 459         DEVMETHOD(device_suspend,       bge_suspend),
 460         DEVMETHOD(device_resume,        bge_resume),
 461
 462         /* bus interface */
 463         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 464         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 465
 466         /* MII interface */
 467         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 468         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 469         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 470
 471         { 0, 0 }
 472 };
 473
 474 static driver_t bge_driver = {
 475         "bge",
 476         bge_methods,
 477         sizeof(struct bge_softc)
 478 };
 479
 480 static devclass_t bge_devclass;
 481
 482 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
 483 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 484
 485 static int bge_allow_asf = 1;
 486
 487 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
 488
 489 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
 490 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
 491         "Allow ASF mode if available");
 492
 493 #define SPARC64_BLADE_1500_MODEL        "SUNW,Sun-Blade-1500"
 494 #define SPARC64_BLADE_1500_PATH_BGE     "/pci@1f,700000/network@2"
 495 #define SPARC64_BLADE_2500_MODEL        "SUNW,Sun-Blade-2500"
 496 #define SPARC64_BLADE_2500_PATH_BGE     "/pci@1c,600000/network@3"
 497 #define SPARC64_OFW_SUBVENDOR           "subsystem-vendor-id"
 498
 499 static int
 500 bge_has_eaddr(struct bge_softc *sc)
 501 {
 502 #ifdef __sparc64__
 503         char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
 504         device_t dev;
 505         uint32_t subvendor;
 506
 507         dev = sc->bge_dev;
 508
 509         /*
 510          * The on-board BGEs found in sun4u machines aren't fitted with
 511          * an EEPROM which means that we have to obtain the MAC address
 512          * via OFW and that some tests will always fail.  We distinguish
 513          * such BGEs by the subvendor ID, which also has to be obtained
 514          * from OFW instead of the PCI configuration space as the latter
 515          * indicates Broadcom as the subvendor of the netboot interface.
 516          * For early Blade 1500 and 2500 we even have to check the OFW
 517          * device path as the subvendor ID always defaults to Broadcom
 518          * there.
 519          */
 520         if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
 521             &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
 522             subvendor == SUN_VENDORID)
 523                 return (0);
 524         memset(buf, 0, sizeof(buf));
 525         if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
 526                 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
 527                     strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
 528                         return (0);
 529                 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
 530                     strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
 531                         return (0);
 532         }
 533 #endif
 534         return (1);
 535 }
 536
 537 static uint32_t
 538 bge_readmem_ind(struct bge_softc *sc, int off)
 539 {
 540         device_t dev;
 541         uint32_t val;
 542
 543         dev = sc->bge_dev;
 544
 545         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 546         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 547         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 548         return (val);
 549 }
 550
 551 static void
 552 bge_writemem_ind(struct bge_softc *sc, int off, int val)
 553 {
 554         device_t dev;
 555
 556         dev = sc->bge_dev;
 557
 558         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 559         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 560         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 561 }
 562
 563 /*
 564  * PCI Express only
 565  */
 566 static void
 567 bge_set_max_readrq(struct bge_softc *sc)
 568 {
 569         device_t dev;
 570         uint16_t val;
 571
 572         dev = sc->bge_dev;
 573
 574         val = pci_read_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
 575         if ((val & PCIM_EXP_CTL_MAX_READ_REQUEST) !=
 576             BGE_PCIE_DEVCTL_MAX_READRQ_4096) {
 577                 if (bootverbose)
 578                         device_printf(dev, "adjust device control 0x%04x ",
 579                             val);
 580                 val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST;
 581                 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096;
 582                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL,
 583                     val, 2);
 584                 if (bootverbose)
 585                         printf("-> 0x%04x\n", val);
 586         }
 587 }
 588
 589 #ifdef notdef
 590 static uint32_t
 591 bge_readreg_ind(struct bge_softc *sc, int off)
 592 {
 593         device_t dev;
 594
 595         dev = sc->bge_dev;
 596
 597         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 598         return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 599 }
 600 #endif
 601
 602 static void
 603 bge_writereg_ind(struct bge_softc *sc, int off, int val)
 604 {
 605         device_t dev;
 606
 607         dev = sc->bge_dev;
 608
 609         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 610         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 611 }
 612
 613 static void
 614 bge_writemem_direct(struct bge_softc *sc, int off, int val)
 615 {
 616         CSR_WRITE_4(sc, off, val);
 617 }
 618
 619 static void
 620 bge_writembx(struct bge_softc *sc, int off, int val)
 621 {
 622         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 623                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 624
 625         CSR_WRITE_4(sc, off, val);
 626 }
 627
 628 /*
 629  * Map a single buffer address.
 630  */
 631
 632 static void
 633 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 634 {
 635         struct bge_dmamap_arg *ctx;
 636
 637         if (error)
 638                 return;
 639
 640         ctx = arg;
 641
 642         if (nseg > ctx->bge_maxsegs) {
 643                 ctx->bge_maxsegs = 0;
 644                 return;
 645         }
 646
 647         ctx->bge_busaddr = segs->ds_addr;
 648 }
 649
 650 static uint8_t
 651 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 652 {
 653         uint32_t access, byte = 0;
 654         int i;
 655
 656         /* Lock. */
 657         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 658         for (i = 0; i < 8000; i++) {
 659                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 660                         break;
 661                 DELAY(20);
 662         }
 663         if (i == 8000)
 664                 return (1);
 665
 666         /* Enable access. */
 667         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 668         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 669
 670         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 671         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 672         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 673                 DELAY(10);
 674                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 675                         DELAY(10);
 676                         break;
 677                 }
 678         }
 679
 680         if (i == BGE_TIMEOUT * 10) {
 681                 if_printf(sc->bge_ifp, "nvram read timed out\n");
 682                 return (1);
 683         }
 684
 685         /* Get result. */
 686         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 687
 688         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 689
 690         /* Disable access. */
 691         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 692
 693         /* Unlock. */
 694         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 695         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 696
 697         return (0);
 698 }
 699
 700 /*
 701  * Read a sequence of bytes from NVRAM.
 702  */
 703 static int
 704 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 705 {
 706         int err = 0, i;
 707         uint8_t byte = 0;
 708
 709         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 710                 return (1);
 711
 712         for (i = 0; i < cnt; i++) {
 713                 err = bge_nvram_getbyte(sc, off + i, &byte);
 714                 if (err)
 715                         break;
 716                 *(dest + i) = byte;
 717         }
 718
 719         return (err ? 1 : 0);
 720 }
 721
 722 /*
 723  * Read a byte of data stored in the EEPROM at address 'addr.' The
 724  * BCM570x supports both the traditional bitbang interface and an
 725  * auto access interface for reading the EEPROM. We use the auto
 726  * access method.
 727  */
 728 static uint8_t
 729 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 730 {
 731         int i;
 732         uint32_t byte = 0;
 733
 734         /*
 735          * Enable use of auto EEPROM access so we can avoid
 736          * having to use the bitbang method.
 737          */
 738         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 739
 740         /* Reset the EEPROM, load the clock period. */
 741         CSR_WRITE_4(sc, BGE_EE_ADDR,
 742             BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 743         DELAY(20);
 744
 745         /* Issue the read EEPROM command. */
 746         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 747
 748         /* Wait for completion */
 749         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 750                 DELAY(10);
 751                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 752                         break;
 753         }
 754
 755         if (i == BGE_TIMEOUT * 10) {
 756                 device_printf(sc->bge_dev, "EEPROM read timed out\n");
 757                 return (1);
 758         }
 759
 760         /* Get result. */
 761         byte = CSR_READ_4(sc, BGE_EE_DATA);
 762
 763         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 764
 765         return (0);
 766 }
 767
 768 /*
 769  * Read a sequence of bytes from the EEPROM.
 770  */
 771 static int
 772 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 773 {
 774         int i, error = 0;
 775         uint8_t byte = 0;
 776
 777         for (i = 0; i < cnt; i++) {
 778                 error = bge_eeprom_getbyte(sc, off + i, &byte);
 779                 if (error)
 780                         break;
 781                 *(dest + i) = byte;
 782         }
 783
 784         return (error ? 1 : 0);
 785 }
 786
 787 static int
 788 bge_miibus_readreg(device_t dev, int phy, int reg)
 789 {
 790         struct bge_softc *sc;
 791         uint32_t val, autopoll;
 792         int i;
 793
 794         sc = device_get_softc(dev);
 795
 796         /*
 797          * Broadcom's own driver always assumes the internal
 798          * PHY is at GMII address 1. On some chips, the PHY responds
 799          * to accesses at all addresses, which could cause us to
 800          * bogusly attach the PHY 32 times at probe type. Always
 801          * restricting the lookup to address 1 is simpler than
 802          * trying to figure out which chips revisions should be
 803          * special-cased.
 804          */
 805         if (phy != 1)
 806                 return (0);
 807
 808         /* Reading with autopolling on may trigger PCI errors */
 809         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 810         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 811                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 812                 DELAY(40);
 813         }
 814
 815         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 816             BGE_MIPHY(phy) | BGE_MIREG(reg));
 817
 818         for (i = 0; i < BGE_TIMEOUT; i++) {
 819                 DELAY(10);
 820                 val = CSR_READ_4(sc, BGE_MI_COMM);
 821                 if (!(val & BGE_MICOMM_BUSY))
 822                         break;
 823         }
 824
 825         if (i == BGE_TIMEOUT) {
 826                 device_printf(sc->bge_dev,
 827                     "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
 828                     phy, reg, val);
 829                 val = 0;
 830                 goto done;
 831         }
 832
 833         DELAY(5);
 834         val = CSR_READ_4(sc, BGE_MI_COMM);
 835
 836 done:
 837         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 838                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 839                 DELAY(40);
 840         }
 841
 842         if (val & BGE_MICOMM_READFAIL)
 843                 return (0);
 844
 845         return (val & 0xFFFF);
 846 }
 847
 848 static int
 849 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 850 {
 851         struct bge_softc *sc;
 852         uint32_t autopoll;
 853         int i;
 854
 855         sc = device_get_softc(dev);
 856
 857         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 858             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 859                 return(0);
 860
 861         /* Reading with autopolling on may trigger PCI errors */
 862         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 863         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 864                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 865                 DELAY(40);
 866         }
 867
 868         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 869             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 870
 871         for (i = 0; i < BGE_TIMEOUT; i++) {
 872                 DELAY(10);
 873                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 874                         DELAY(5);
 875                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 876                         break;
 877                 }
 878         }
 879
 880         if (i == BGE_TIMEOUT) {
 881                 device_printf(sc->bge_dev,
 882                     "PHY write timed out (phy %d, reg %d, val %d)\n",
 883                     phy, reg, val);
 884                 return (0);
 885         }
 886
 887         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 888                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 889                 DELAY(40);
 890         }
 891
 892         return (0);
 893 }
 894
 895 static void
 896 bge_miibus_statchg(device_t dev)
 897 {
 898         struct bge_softc *sc;
 899         struct mii_data *mii;
 900         sc = device_get_softc(dev);
 901         mii = device_get_softc(sc->bge_miibus);
 902
 903         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 904         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
 905                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 906         else
 907                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 908
 909         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
 910                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 911         else
 912                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 913 }
 914
 915 /*
 916  * Intialize a standard receive ring descriptor.
 917  */
 918 static int
 919 bge_newbuf_std(struct bge_softc *sc, int i)
 920 {
 921         struct mbuf *m;
 922         struct bge_rx_bd *r;
 923         bus_dma_segment_t segs[1];
 924         bus_dmamap_t map;
 925         int error, nsegs;
 926
 927         m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
 928         if (m == NULL)
 929                 return (ENOBUFS);
 930         m->m_len = m->m_pkthdr.len = MCLBYTES;
 931         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 932                 m_adj(m, ETHER_ALIGN);
 933
 934         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
 935             sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
 936         if (error != 0) {
 937                 m_freem(m);
 938                 return (error);
 939         }
 940         if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 941                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 942                     sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
 943                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 944                     sc->bge_cdata.bge_rx_std_dmamap[i]);
 945         }
 946         map = sc->bge_cdata.bge_rx_std_dmamap[i];
 947         sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
 948         sc->bge_cdata.bge_rx_std_sparemap = map;
 949         sc->bge_cdata.bge_rx_std_chain[i] = m;
 950         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
 951         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
 952         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
 953         r->bge_flags = BGE_RXBDFLAG_END;
 954         r->bge_len = segs[0].ds_len;
 955         r->bge_idx = i;
 956
 957         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 958             sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
 959
 960         return (0);
 961 }
 962
 963 /*
 964  * Initialize a jumbo receive ring descriptor. This allocates
 965  * a jumbo buffer from the pool managed internally by the driver.
 966  */
 967 static int
 968 bge_newbuf_jumbo(struct bge_softc *sc, int i)
 969 {
 970         bus_dma_segment_t segs[BGE_NSEG_JUMBO];
 971         bus_dmamap_t map;
 972         struct bge_extrx_bd *r;
 973         struct mbuf *m;
 974         int error, nsegs;
 975
 976         MGETHDR(m, M_DONTWAIT, MT_DATA);
 977         if (m == NULL)
 978                 return (ENOBUFS);
 979
 980         m_cljget(m, M_DONTWAIT, MJUM9BYTES);
 981         if (!(m->m_flags & M_EXT)) {
 982                 m_freem(m);
 983                 return (ENOBUFS);
 984         }
 985         m->m_len = m->m_pkthdr.len = MJUM9BYTES;
 986         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 987                 m_adj(m, ETHER_ALIGN);
 988
 989         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
 990             sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
 991         if (error != 0) {
 992                 m_freem(m);
 993                 return (error);
 994         }
 995
 996         if (sc->bge_cdata.bge_rx_jumbo_chain[i] == NULL) {
 997                 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
 998                     sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
 999                 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1000                     sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1001         }
1002         map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1003         sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1004             sc->bge_cdata.bge_rx_jumbo_sparemap;
1005         sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1006         sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1007         /*
1008          * Fill in the extended RX buffer descriptor.
1009          */
1010         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1011         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1012         r->bge_idx = i;
1013         r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1014         switch (nsegs) {
1015         case 4:
1016                 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1017                 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1018                 r->bge_len3 = segs[3].ds_len;
1019         case 3:
1020                 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1021                 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1022                 r->bge_len2 = segs[2].ds_len;
1023         case 2:
1024                 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1025                 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1026                 r->bge_len1 = segs[1].ds_len;
1027         case 1:
1028                 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1029                 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1030                 r->bge_len0 = segs[0].ds_len;
1031                 break;
1032         default:
1033                 panic("%s: %d segments\n", __func__, nsegs);
1034         }
1035
1036         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1037             sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1038
1039         return (0);
1040 }
1041
1042 /*
1043  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1044  * that's 1MB or memory, which is a lot. For now, we fill only the first
1045  * 256 ring entries and hope that our CPU is fast enough to keep up with
1046  * the NIC.
1047  */
1048 static int
1049 bge_init_rx_ring_std(struct bge_softc *sc)
1050 {
1051         int error, i;
1052
1053         bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1054         sc->bge_std = 0;
1055         for (i = 0; i < BGE_SSLOTS; i++) {
1056                 if ((error = bge_newbuf_std(sc, i)) != 0)
1057                         return (error);
1058                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1059         };
1060
1061         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1062             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1063
1064         sc->bge_std = i - 1;
1065         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1066
1067         return (0);
1068 }
1069
1070 static void
1071 bge_free_rx_ring_std(struct bge_softc *sc)
1072 {
1073         int i;
1074
1075         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1076                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1077                         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1078                             sc->bge_cdata.bge_rx_std_dmamap[i],
1079                             BUS_DMASYNC_POSTREAD);
1080                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1081                             sc->bge_cdata.bge_rx_std_dmamap[i]);
1082                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1083                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1084                 }
1085                 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1086                     sizeof(struct bge_rx_bd));
1087         }
1088 }
1089
1090 static int
1091 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1092 {
1093         struct bge_rcb *rcb;
1094         int error, i;
1095
1096         bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1097         sc->bge_jumbo = 0;
1098         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1099                 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1100                         return (error);
1101                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1102         };
1103
1104         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1105             sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1106
1107         sc->bge_jumbo = i - 1;
1108
1109         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1110         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1111                                     BGE_RCB_FLAG_USE_EXT_RX_BD);
1112         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1113
1114         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1115
1116         return (0);
1117 }
1118
1119 static void
1120 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1121 {
1122         int i;
1123
1124         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1125                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1126                         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1127                             sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1128                             BUS_DMASYNC_POSTREAD);
1129                         bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1130                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1131                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1132                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1133                 }
1134                 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1135                     sizeof(struct bge_extrx_bd));
1136         }
1137 }
1138
1139 static void
1140 bge_free_tx_ring(struct bge_softc *sc)
1141 {
1142         int i;
1143
1144         if (sc->bge_ldata.bge_tx_ring == NULL)
1145                 return;
1146
1147         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1148                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1149                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1150                             sc->bge_cdata.bge_tx_dmamap[i],
1151                             BUS_DMASYNC_POSTWRITE);
1152                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1153                             sc->bge_cdata.bge_tx_dmamap[i]);
1154                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1155                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1156                 }
1157                 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1158                     sizeof(struct bge_tx_bd));
1159         }
1160 }
1161
1162 static int
1163 bge_init_tx_ring(struct bge_softc *sc)
1164 {
1165         sc->bge_txcnt = 0;
1166         sc->bge_tx_saved_considx = 0;
1167
1168         bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1169         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1170             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1171
1172         /* Initialize transmit producer index for host-memory send ring. */
1173         sc->bge_tx_prodidx = 0;
1174         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1175
1176         /* 5700 b2 errata */
1177         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1178                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1179
1180         /* NIC-memory send ring not used; initialize to zero. */
1181         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1182         /* 5700 b2 errata */
1183         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1184                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1185
1186         return (0);
1187 }
1188
1189 static void
1190 bge_setpromisc(struct bge_softc *sc)
1191 {
1192         struct ifnet *ifp;
1193
1194         BGE_LOCK_ASSERT(sc);
1195
1196         ifp = sc->bge_ifp;
1197
1198         /* Enable or disable promiscuous mode as needed. */
1199         if (ifp->if_flags & IFF_PROMISC)
1200                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1201         else
1202                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1203 }
1204
1205 static void
1206 bge_setmulti(struct bge_softc *sc)
1207 {
1208         struct ifnet *ifp;
1209         struct ifmultiaddr *ifma;
1210         uint32_t hashes[4] = { 0, 0, 0, 0 };
1211         int h, i;
1212
1213         BGE_LOCK_ASSERT(sc);
1214
1215         ifp = sc->bge_ifp;
1216
1217         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1218                 for (i = 0; i < 4; i++)
1219                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1220                 return;
1221         }
1222
1223         /* First, zot all the existing filters. */
1224         for (i = 0; i < 4; i++)
1225                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1226
1227         /* Now program new ones. */
1228         if_maddr_rlock(ifp);
1229         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1230                 if (ifma->ifma_addr->sa_family != AF_LINK)
1231                         continue;
1232                 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1233                     ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1234                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1235         }
1236         if_maddr_runlock(ifp);
1237
1238         for (i = 0; i < 4; i++)
1239                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1240 }
1241
1242 static void
1243 bge_setvlan(struct bge_softc *sc)
1244 {
1245         struct ifnet *ifp;
1246
1247         BGE_LOCK_ASSERT(sc);
1248
1249         ifp = sc->bge_ifp;
1250
1251         /* Enable or disable VLAN tag stripping as needed. */
1252         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1253                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1254         else
1255                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1256 }
1257
1258 static void
1259 bge_sig_pre_reset(sc, type)
1260         struct bge_softc *sc;
1261         int type;
1262 {
1263         /*
1264          * Some chips don't like this so only do this if ASF is enabled
1265          */
1266         if (sc->bge_asf_mode)
1267                 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1268
1269         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1270                 switch (type) {
1271                 case BGE_RESET_START:
1272                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1273                         break;
1274                 case BGE_RESET_STOP:
1275                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1276                         break;
1277                 }
1278         }
1279 }
1280
1281 static void
1282 bge_sig_post_reset(sc, type)
1283         struct bge_softc *sc;
1284         int type;
1285 {
1286         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1287                 switch (type) {
1288                 case BGE_RESET_START:
1289                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001);
1290                         /* START DONE */
1291                         break;
1292                 case BGE_RESET_STOP:
1293                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002);
1294                         break;
1295                 }
1296         }
1297 }
1298
1299 static void
1300 bge_sig_legacy(sc, type)
1301         struct bge_softc *sc;
1302         int type;
1303 {
1304         if (sc->bge_asf_mode) {
1305                 switch (type) {
1306                 case BGE_RESET_START:
1307                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1308                         break;
1309                 case BGE_RESET_STOP:
1310                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1311                         break;
1312                 }
1313         }
1314 }
1315
1316 void bge_stop_fw(struct bge_softc *);
1317 void
1318 bge_stop_fw(sc)
1319         struct bge_softc *sc;
1320 {
1321         int i;
1322
1323         if (sc->bge_asf_mode) {
1324                 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE);
1325                 CSR_WRITE_4(sc, BGE_CPU_EVENT,
1326                     CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
1327
1328                 for (i = 0; i < 100; i++ ) {
1329                         if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14)))
1330                                 break;
1331                         DELAY(10);
1332                 }
1333         }
1334 }
1335
1336 /*
1337  * Do endian, PCI and DMA initialization.
1338  */
1339 static int
1340 bge_chipinit(struct bge_softc *sc)
1341 {
1342         uint32_t dma_rw_ctl;
1343         int i;
1344
1345         /* Set endianness before we access any non-PCI registers. */
1346         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1347
1348         /* Clear the MAC control register */
1349         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1350
1351         /*
1352          * Clear the MAC statistics block in the NIC's
1353          * internal memory.
1354          */
1355         for (i = BGE_STATS_BLOCK;
1356             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1357                 BGE_MEMWIN_WRITE(sc, i, 0);
1358
1359         for (i = BGE_STATUS_BLOCK;
1360             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1361                 BGE_MEMWIN_WRITE(sc, i, 0);
1362
1363         /*
1364          * Set up the PCI DMA control register.
1365          */
1366         dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1367             BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1368         if (sc->bge_flags & BGE_FLAG_PCIE) {
1369                 /* Read watermark not used, 128 bytes for write. */
1370                 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1371         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1372                 if (BGE_IS_5714_FAMILY(sc)) {
1373                         /* 256 bytes for read and write. */
1374                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1375                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1376                         dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1377                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1378                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1379                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1380                         /* 1536 bytes for read, 384 bytes for write. */
1381                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1382                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1383                 } else {
1384                         /* 384 bytes for read and write. */
1385                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1386                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1387                             0x0F;
1388                 }
1389                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1390                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1391                         uint32_t tmp;
1392
1393                         /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1394                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1395                         if (tmp == 6 || tmp == 7)
1396                                 dma_rw_ctl |=
1397                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1398
1399                         /* Set PCI-X DMA write workaround. */
1400                         dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1401                 }
1402         } else {
1403                 /* Conventional PCI bus: 256 bytes for read and write. */
1404                 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1405                     BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1406
1407                 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1408                     sc->bge_asicrev != BGE_ASICREV_BCM5750)
1409                         dma_rw_ctl |= 0x0F;
1410         }
1411         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1412             sc->bge_asicrev == BGE_ASICREV_BCM5701)
1413                 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1414                     BGE_PCIDMARWCTL_ASRT_ALL_BE;
1415         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1416             sc->bge_asicrev == BGE_ASICREV_BCM5704)
1417                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1418         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1419
1420         /*
1421          * Set up general mode register.
1422          */
1423         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
1424             BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1425             BGE_MODECTL_TX_NO_PHDR_CSUM);
1426
1427         /*
1428          * BCM5701 B5 have a bug causing data corruption when using
1429          * 64-bit DMA reads, which can be terminated early and then
1430          * completed later as 32-bit accesses, in combination with
1431          * certain bridges.
1432          */
1433         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1434             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1435                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1436
1437         /*
1438          * Tell the firmware the driver is running
1439          */
1440         if (sc->bge_asf_mode & ASF_STACKUP)
1441                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
1442
1443         /*
1444          * Disable memory write invalidate.  Apparently it is not supported
1445          * properly by these devices.  Also ensure that INTx isn't disabled,
1446          * as these chips need it even when using MSI.
1447          */
1448         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1449             PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
1450
1451         /* Set the timer prescaler (always 66Mhz) */
1452         CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1453
1454         /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1455         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1456                 DELAY(40);      /* XXX */
1457
1458                 /* Put PHY into ready state */
1459                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1460                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1461                 DELAY(40);
1462         }
1463
1464         return (0);
1465 }
1466
1467 static int
1468 bge_blockinit(struct bge_softc *sc)
1469 {
1470         struct bge_rcb *rcb;
1471         bus_size_t vrcb;
1472         bge_hostaddr taddr;
1473         uint32_t val;
1474         int i;
1475
1476         /*
1477          * Initialize the memory window pointer register so that
1478          * we can access the first 32K of internal NIC RAM. This will
1479          * allow us to set up the TX send ring RCBs and the RX return
1480          * ring RCBs, plus other things which live in NIC memory.
1481          */
1482         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1483
1484         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1485
1486         if (!(BGE_IS_5705_PLUS(sc))) {
1487                 /* Configure mbuf memory pool */
1488                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1489                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1490                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1491                 else
1492                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1493
1494                 /* Configure DMA resource pool */
1495                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1496                     BGE_DMA_DESCRIPTORS);
1497                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1498         }
1499
1500         /* Configure mbuf pool watermarks */
1501         if (!BGE_IS_5705_PLUS(sc)) {
1502                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1503                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1504                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1505         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1506                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1507                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1508                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1509         } else {
1510                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1511                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1512                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1513         }
1514
1515         /* Configure DMA resource watermarks */
1516         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1517         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1518
1519         /* Enable buffer manager */
1520         if (!(BGE_IS_5705_PLUS(sc))) {
1521                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1522                     BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN);
1523
1524                 /* Poll for buffer manager start indication */
1525                 for (i = 0; i < BGE_TIMEOUT; i++) {
1526                         DELAY(10);
1527                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1528                                 break;
1529                 }
1530
1531                 if (i == BGE_TIMEOUT) {
1532                         device_printf(sc->bge_dev,
1533                             "buffer manager failed to start\n");
1534                         return (ENXIO);
1535                 }
1536         }
1537
1538         /* Enable flow-through queues */
1539         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1540         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1541
1542         /* Wait until queue initialization is complete */
1543         for (i = 0; i < BGE_TIMEOUT; i++) {
1544                 DELAY(10);
1545                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1546                         break;
1547         }
1548
1549         if (i == BGE_TIMEOUT) {
1550                 device_printf(sc->bge_dev, "flow-through queue init failed\n");
1551                 return (ENXIO);
1552         }
1553
1554         /* Initialize the standard RX ring control block */
1555         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1556         rcb->bge_hostaddr.bge_addr_lo =
1557             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1558         rcb->bge_hostaddr.bge_addr_hi =
1559             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1560         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1561             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1562         if (BGE_IS_5705_PLUS(sc))
1563                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1564         else
1565                 rcb->bge_maxlen_flags =
1566                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1567         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1568         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1569         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1570
1571         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1572         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1573
1574         /*
1575          * Initialize the jumbo RX ring control block
1576          * We set the 'ring disabled' bit in the flags
1577          * field until we're actually ready to start
1578          * using this ring (i.e. once we set the MTU
1579          * high enough to require it).
1580          */
1581         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1582                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1583
1584                 rcb->bge_hostaddr.bge_addr_lo =
1585                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1586                 rcb->bge_hostaddr.bge_addr_hi =
1587                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1588                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1589                     sc->bge_cdata.bge_rx_jumbo_ring_map,
1590                     BUS_DMASYNC_PREREAD);
1591                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1592                     BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1593                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1594                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1595                     rcb->bge_hostaddr.bge_addr_hi);
1596                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1597                     rcb->bge_hostaddr.bge_addr_lo);
1598
1599                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1600                     rcb->bge_maxlen_flags);
1601                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1602
1603                 /* Set up dummy disabled mini ring RCB */
1604                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1605                 rcb->bge_maxlen_flags =
1606                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1607                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1608                     rcb->bge_maxlen_flags);
1609         }
1610
1611         /*
1612          * Set the BD ring replentish thresholds. The recommended
1613          * values are 1/8th the number of descriptors allocated to
1614          * each ring.
1615          * XXX The 5754 requires a lower threshold, so it might be a
1616          * requirement of all 575x family chips.  The Linux driver sets
1617          * the lower threshold for all 5705 family chips as well, but there
1618          * are reports that it might not need to be so strict.
1619          *
1620          * XXX Linux does some extra fiddling here for the 5906 parts as
1621          * well.
1622          */
1623         if (BGE_IS_5705_PLUS(sc))
1624                 val = 8;
1625         else
1626                 val = BGE_STD_RX_RING_CNT / 8;
1627         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1628         CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1629
1630         /*
1631          * Disable all unused send rings by setting the 'ring disabled'
1632          * bit in the flags field of all the TX send ring control blocks.
1633          * These are located in NIC memory.
1634          */
1635         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1636         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1637                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1638                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1639                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1640                 vrcb += sizeof(struct bge_rcb);
1641         }
1642
1643         /* Configure TX RCB 0 (we use only the first ring) */
1644         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1645         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1646         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1647         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1648         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1649             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1650         if (!(BGE_IS_5705_PLUS(sc)))
1651                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1652                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1653
1654         /* Disable all unused RX return rings */
1655         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1656         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1657                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1658                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1659                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1660                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1661                     BGE_RCB_FLAG_RING_DISABLED));
1662                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1663                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1664                     (i * (sizeof(uint64_t))), 0);
1665                 vrcb += sizeof(struct bge_rcb);
1666         }
1667
1668         /* Initialize RX ring indexes */
1669         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1670         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1671         bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1672
1673         /*
1674          * Set up RX return ring 0
1675          * Note that the NIC address for RX return rings is 0x00000000.
1676          * The return rings live entirely within the host, so the
1677          * nicaddr field in the RCB isn't used.
1678          */
1679         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1680         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1681         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1682         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1683         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1684         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1685             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1686
1687         /* Set random backoff seed for TX */
1688         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1689             IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1690             IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1691             IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1692             BGE_TX_BACKOFF_SEED_MASK);
1693
1694         /* Set inter-packet gap */
1695         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1696
1697         /*
1698          * Specify which ring to use for packets that don't match
1699          * any RX rules.
1700          */
1701         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1702
1703         /*
1704          * Configure number of RX lists. One interrupt distribution
1705          * list, sixteen active lists, one bad frames class.
1706          */
1707         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1708
1709         /* Inialize RX list placement stats mask. */
1710         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1711         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1712
1713         /* Disable host coalescing until we get it set up */
1714         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1715
1716         /* Poll to make sure it's shut down. */
1717         for (i = 0; i < BGE_TIMEOUT; i++) {
1718                 DELAY(10);
1719                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1720                         break;
1721         }
1722
1723         if (i == BGE_TIMEOUT) {
1724                 device_printf(sc->bge_dev,
1725                     "host coalescing engine failed to idle\n");
1726                 return (ENXIO);
1727         }
1728
1729         /* Set up host coalescing defaults */
1730         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1731         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1732         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1733         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1734         if (!(BGE_IS_5705_PLUS(sc))) {
1735                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1736                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1737         }
1738         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1739         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1740
1741         /* Set up address of statistics block */
1742         if (!(BGE_IS_5705_PLUS(sc))) {
1743                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1744                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1745                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1746                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1747                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1748                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1749                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1750         }
1751
1752         /* Set up address of status block */
1753         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1754             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1755         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1756             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1757         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1758         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1759
1760         /* Set up status block size. */
1761         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1762             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
1763                 val = BGE_STATBLKSZ_FULL;
1764         else
1765                 val = BGE_STATBLKSZ_32BYTE;
1766
1767         /* Turn on host coalescing state machine */
1768         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1769
1770         /* Turn on RX BD completion state machine and enable attentions */
1771         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1772             BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
1773
1774         /* Turn on RX list placement state machine */
1775         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1776
1777         /* Turn on RX list selector state machine. */
1778         if (!(BGE_IS_5705_PLUS(sc)))
1779                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1780
1781         /* Turn on DMA, clear stats */
1782         CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB |
1783             BGE_MACMODE_RXDMA_ENB | BGE_MACMODE_RX_STATS_CLEAR |
1784             BGE_MACMODE_TX_STATS_CLEAR | BGE_MACMODE_RX_STATS_ENB |
1785             BGE_MACMODE_TX_STATS_ENB | BGE_MACMODE_FRMHDR_DMA_ENB |
1786             ((sc->bge_flags & BGE_FLAG_TBI) ?
1787             BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1788
1789         /* Set misc. local control, enable interrupts on attentions */
1790         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1791
1792 #ifdef notdef
1793         /* Assert GPIO pins for PHY reset */
1794         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
1795             BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
1796         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
1797             BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
1798 #endif
1799
1800         /* Turn on DMA completion state machine */
1801         if (!(BGE_IS_5705_PLUS(sc)))
1802                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1803
1804         val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
1805
1806         /* Enable host coalescing bug fix. */
1807         if (BGE_IS_5755_PLUS(sc))
1808                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1809
1810         /* Turn on write DMA state machine */
1811         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1812         DELAY(40);
1813
1814         /* Turn on read DMA state machine */
1815         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1816         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1817             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1818             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1819                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1820                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1821                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1822         if (sc->bge_flags & BGE_FLAG_PCIE)
1823                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1824         if (sc->bge_flags & BGE_FLAG_TSO)
1825                 val |= BGE_RDMAMODE_TSO4_ENABLE;
1826         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1827         DELAY(40);
1828
1829         /* Turn on RX data completion state machine */
1830         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1831
1832         /* Turn on RX BD initiator state machine */
1833         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1834
1835         /* Turn on RX data and RX BD initiator state machine */
1836         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1837
1838         /* Turn on Mbuf cluster free state machine */
1839         if (!(BGE_IS_5705_PLUS(sc)))
1840                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1841
1842         /* Turn on send BD completion state machine */
1843         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1844
1845         /* Turn on send data completion state machine */
1846         val = BGE_SDCMODE_ENABLE;
1847         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1848                 val |= BGE_SDCMODE_CDELAY;
1849         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1850
1851         /* Turn on send data initiator state machine */
1852         if (sc->bge_flags & BGE_FLAG_TSO)
1853                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08);
1854         else
1855                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1856
1857         /* Turn on send BD initiator state machine */
1858         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1859
1860         /* Turn on send BD selector state machine */
1861         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1862
1863         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1864         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1865             BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
1866
1867         /* ack/clear link change events */
1868         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1869             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1870             BGE_MACSTAT_LINK_CHANGED);
1871         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1872
1873         /* Enable PHY auto polling (for MII/GMII only) */
1874         if (sc->bge_flags & BGE_FLAG_TBI) {
1875                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1876         } else {
1877                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16));
1878                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1879                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
1880                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1881                             BGE_EVTENB_MI_INTERRUPT);
1882         }
1883
1884         /*
1885          * Clear any pending link state attention.
1886          * Otherwise some link state change events may be lost until attention
1887          * is cleared by bge_intr() -> bge_link_upd() sequence.
1888          * It's not necessary on newer BCM chips - perhaps enabling link
1889          * state change attentions implies clearing pending attention.
1890          */
1891         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1892             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1893             BGE_MACSTAT_LINK_CHANGED);
1894
1895         /* Enable link state change attentions. */
1896         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1897
1898         return (0);
1899 }
1900
1901 const struct bge_revision *
1902 bge_lookup_rev(uint32_t chipid)
1903 {
1904         const struct bge_revision *br;
1905
1906         for (br = bge_revisions; br->br_name != NULL; br++) {
1907                 if (br->br_chipid == chipid)
1908                         return (br);
1909         }
1910
1911         for (br = bge_majorrevs; br->br_name != NULL; br++) {
1912                 if (br->br_chipid == BGE_ASICREV(chipid))
1913                         return (br);
1914         }
1915
1916         return (NULL);
1917 }
1918
1919 const struct bge_vendor *
1920 bge_lookup_vendor(uint16_t vid)
1921 {
1922         const struct bge_vendor *v;
1923
1924         for (v = bge_vendors; v->v_name != NULL; v++)
1925                 if (v->v_id == vid)
1926                         return (v);
1927
1928         panic("%s: unknown vendor %d", __func__, vid);
1929         return (NULL);
1930 }
1931
1932 /*
1933  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1934  * against our list and return its name if we find a match.
1935  *
1936  * Note that since the Broadcom controller contains VPD support, we
1937  * try to get the device name string from the controller itself instead
1938  * of the compiled-in string. It guarantees we'll always announce the
1939  * right product name. We fall back to the compiled-in string when
1940  * VPD is unavailable or corrupt.
1941  */
1942 static int
1943 bge_probe(device_t dev)
1944 {
1945         const struct bge_type *t = bge_devs;
1946         struct bge_softc *sc = device_get_softc(dev);
1947         uint16_t vid, did;
1948
1949         sc->bge_dev = dev;
1950         vid = pci_get_vendor(dev);
1951         did = pci_get_device(dev);
1952         while(t->bge_vid != 0) {
1953                 if ((vid == t->bge_vid) && (did == t->bge_did)) {
1954                         char model[64], buf[96];
1955                         const struct bge_revision *br;
1956                         const struct bge_vendor *v;
1957                         uint32_t id;
1958
1959                         id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1960                             BGE_PCIMISCCTL_ASICREV_SHIFT;
1961                         if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG)
1962                                 id = pci_read_config(dev,
1963                                     BGE_PCI_PRODID_ASICREV, 4);
1964                         br = bge_lookup_rev(id);
1965                         v = bge_lookup_vendor(vid);
1966                         {
1967 #if __FreeBSD_version > 700024
1968                                 const char *pname;
1969
1970                                 if (bge_has_eaddr(sc) &&
1971                                     pci_get_vpd_ident(dev, &pname) == 0)
1972                                         snprintf(model, 64, "%s", pname);
1973                                 else
1974 #endif
1975                                         snprintf(model, 64, "%s %s",
1976                                             v->v_name,
1977                                             br != NULL ? br->br_name :
1978                                             "NetXtreme Ethernet Controller");
1979                         }
1980                         snprintf(buf, 96, "%s, %sASIC rev. %#08x", model,
1981                             br != NULL ? "" : "unknown ", id);
1982                         device_set_desc_copy(dev, buf);
1983                         if (pci_get_subvendor(dev) == DELL_VENDORID)
1984                                 sc->bge_flags |= BGE_FLAG_NO_3LED;
1985                         if (did == BCOM_DEVICEID_BCM5755M)
1986                                 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1987                         return (0);
1988                 }
1989                 t++;
1990         }
1991
1992         return (ENXIO);
1993 }
1994
1995 static void
1996 bge_dma_free(struct bge_softc *sc)
1997 {
1998         int i;
1999
2000         /* Destroy DMA maps for RX buffers. */
2001         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2002                 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2003                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2004                             sc->bge_cdata.bge_rx_std_dmamap[i]);
2005         }
2006         if (sc->bge_cdata.bge_rx_std_sparemap)
2007                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2008                     sc->bge_cdata.bge_rx_std_sparemap);
2009
2010         /* Destroy DMA maps for jumbo RX buffers. */
2011         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2012                 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2013                         bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2014                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2015         }
2016         if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2017                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2018                     sc->bge_cdata.bge_rx_jumbo_sparemap);
2019
2020         /* Destroy DMA maps for TX buffers. */
2021         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2022                 if (sc->bge_cdata.bge_tx_dmamap[i])
2023                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2024                             sc->bge_cdata.bge_tx_dmamap[i]);
2025         }
2026
2027         if (sc->bge_cdata.bge_rx_mtag)
2028                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2029         if (sc->bge_cdata.bge_tx_mtag)
2030                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2031
2032
2033         /* Destroy standard RX ring. */
2034         if (sc->bge_cdata.bge_rx_std_ring_map)
2035                 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2036                     sc->bge_cdata.bge_rx_std_ring_map);
2037         if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
2038                 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2039                     sc->bge_ldata.bge_rx_std_ring,
2040                     sc->bge_cdata.bge_rx_std_ring_map);
2041
2042         if (sc->bge_cdata.bge_rx_std_ring_tag)
2043                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2044
2045         /* Destroy jumbo RX ring. */
2046         if (sc->bge_cdata.bge_rx_jumbo_ring_map)
2047                 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2048                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2049
2050         if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
2051             sc->bge_ldata.bge_rx_jumbo_ring)
2052                 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2053                     sc->bge_ldata.bge_rx_jumbo_ring,
2054                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2055
2056         if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2057                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2058
2059         /* Destroy RX return ring. */
2060         if (sc->bge_cdata.bge_rx_return_ring_map)
2061                 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2062                     sc->bge_cdata.bge_rx_return_ring_map);
2063
2064         if (sc->bge_cdata.bge_rx_return_ring_map &&
2065             sc->bge_ldata.bge_rx_return_ring)
2066                 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2067                     sc->bge_ldata.bge_rx_return_ring,
2068                     sc->bge_cdata.bge_rx_return_ring_map);
2069
2070         if (sc->bge_cdata.bge_rx_return_ring_tag)
2071                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2072
2073         /* Destroy TX ring. */
2074         if (sc->bge_cdata.bge_tx_ring_map)
2075                 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2076                     sc->bge_cdata.bge_tx_ring_map);
2077
2078         if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
2079                 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2080                     sc->bge_ldata.bge_tx_ring,
2081                     sc->bge_cdata.bge_tx_ring_map);
2082
2083         if (sc->bge_cdata.bge_tx_ring_tag)
2084                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2085
2086         /* Destroy status block. */
2087         if (sc->bge_cdata.bge_status_map)
2088                 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2089                     sc->bge_cdata.bge_status_map);
2090
2091         if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
2092                 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2093                     sc->bge_ldata.bge_status_block,
2094                     sc->bge_cdata.bge_status_map);
2095
2096         if (sc->bge_cdata.bge_status_tag)
2097                 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2098
2099         /* Destroy statistics block. */
2100         if (sc->bge_cdata.bge_stats_map)
2101                 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2102                     sc->bge_cdata.bge_stats_map);
2103
2104         if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2105                 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2106                     sc->bge_ldata.bge_stats,
2107                     sc->bge_cdata.bge_stats_map);
2108
2109         if (sc->bge_cdata.bge_stats_tag)
2110                 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2111
2112         /* Destroy the parent tag. */
2113         if (sc->bge_cdata.bge_parent_tag)
2114                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2115 }
2116
2117 static int
2118 bge_dma_alloc(device_t dev)
2119 {
2120         struct bge_dmamap_arg ctx;
2121         struct bge_softc *sc;
2122         bus_addr_t lowaddr;
2123         bus_size_t sbsz, txsegsz, txmaxsegsz;
2124         int i, error;
2125
2126         sc = device_get_softc(dev);
2127
2128         lowaddr = BUS_SPACE_MAXADDR;
2129         if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2130                 lowaddr = BGE_DMA_MAXADDR;
2131         if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0)
2132                 lowaddr = BUS_SPACE_MAXADDR_32BIT;
2133         /*
2134          * Allocate the parent bus DMA tag appropriate for PCI.
2135          */
2136         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2137             1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2138             NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2139             0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2140
2141         if (error != 0) {
2142                 device_printf(sc->bge_dev,
2143                     "could not allocate parent dma tag\n");
2144                 return (ENOMEM);
2145         }
2146
2147         /*
2148          * Create tag for Tx mbufs.
2149          */
2150         if (sc->bge_flags & BGE_FLAG_TSO) {
2151                 txsegsz = BGE_TSOSEG_SZ;
2152                 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
2153         } else {
2154                 txsegsz = MCLBYTES;
2155                 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
2156         }
2157         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1,
2158             0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2159             txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
2160             &sc->bge_cdata.bge_tx_mtag);
2161
2162         if (error) {
2163                 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
2164                 return (ENOMEM);
2165         }
2166
2167         /*
2168          * Create tag for Rx mbufs.
2169          */
2170         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
2171             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
2172             MCLBYTES, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
2173
2174         if (error) {
2175                 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
2176                 return (ENOMEM);
2177         }
2178
2179         /* Create DMA maps for RX buffers. */
2180         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2181             &sc->bge_cdata.bge_rx_std_sparemap);
2182         if (error) {
2183                 device_printf(sc->bge_dev,
2184                     "can't create spare DMA map for RX\n");
2185                 return (ENOMEM);
2186         }
2187         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2188                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2189                             &sc->bge_cdata.bge_rx_std_dmamap[i]);
2190                 if (error) {
2191                         device_printf(sc->bge_dev,
2192                             "can't create DMA map for RX\n");
2193                         return (ENOMEM);
2194                 }
2195         }
2196
2197         /* Create DMA maps for TX buffers. */
2198         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2199                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
2200                             &sc->bge_cdata.bge_tx_dmamap[i]);
2201                 if (error) {
2202                         device_printf(sc->bge_dev,
2203                             "can't create DMA map for TX\n");
2204                         return (ENOMEM);
2205                 }
2206         }
2207
2208         /* Create tag for standard RX ring. */
2209         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2210             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2211             NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0,
2212             NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag);
2213
2214         if (error) {
2215                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2216                 return (ENOMEM);
2217         }
2218
2219         /* Allocate DMA'able memory for standard RX ring. */
2220         error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag,
2221             (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT,
2222             &sc->bge_cdata.bge_rx_std_ring_map);
2223         if (error)
2224                 return (ENOMEM);
2225
2226         bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
2227
2228         /* Load the address of the standard RX ring. */
2229         ctx.bge_maxsegs = 1;
2230         ctx.sc = sc;
2231
2232         error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag,
2233             sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring,
2234             BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2235
2236         if (error)
2237                 return (ENOMEM);
2238
2239         sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr;
2240
2241         /* Create tags for jumbo mbufs. */
2242         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2243                 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2244                     1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2245                     NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
2246                     0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
2247                 if (error) {
2248                         device_printf(sc->bge_dev,
2249                             "could not allocate jumbo dma tag\n");
2250                         return (ENOMEM);
2251                 }
2252
2253                 /* Create tag for jumbo RX ring. */
2254                 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2255                     PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2256                     NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0,
2257                     NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag);
2258
2259                 if (error) {
2260                         device_printf(sc->bge_dev,
2261                             "could not allocate jumbo ring dma tag\n");
2262                         return (ENOMEM);
2263                 }
2264
2265                 /* Allocate DMA'able memory for jumbo RX ring. */
2266                 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2267                     (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
2268                     BUS_DMA_NOWAIT | BUS_DMA_ZERO,
2269                     &sc->bge_cdata.bge_rx_jumbo_ring_map);
2270                 if (error)
2271                         return (ENOMEM);
2272
2273                 /* Load the address of the jumbo RX ring. */
2274                 ctx.bge_maxsegs = 1;
2275                 ctx.sc = sc;
2276
2277                 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2278                     sc->bge_cdata.bge_rx_jumbo_ring_map,
2279                     sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ,
2280                     bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2281
2282                 if (error)
2283                         return (ENOMEM);
2284
2285                 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr;
2286
2287                 /* Create DMA maps for jumbo RX buffers. */
2288                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2289                     0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
2290                 if (error) {
2291                         device_printf(sc->bge_dev,
2292                             "can't create spare DMA map for jumbo RX\n");
2293                         return (ENOMEM);
2294                 }
2295                 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2296                         error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2297                                     0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2298                         if (error) {
2299                                 device_printf(sc->bge_dev,
2300                                     "can't create DMA map for jumbo RX\n");
2301                                 return (ENOMEM);
2302                         }
2303                 }
2304
2305         }
2306
2307         /* Create tag for RX return ring. */
2308         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2309             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2310             NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0,
2311             NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag);
2312
2313         if (error) {
2314                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2315                 return (ENOMEM);
2316         }
2317
2318         /* Allocate DMA'able memory for RX return ring. */
2319         error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag,
2320             (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT,
2321             &sc->bge_cdata.bge_rx_return_ring_map);
2322         if (error)
2323                 return (ENOMEM);
2324
2325         bzero((char *)sc->bge_ldata.bge_rx_return_ring,
2326             BGE_RX_RTN_RING_SZ(sc));
2327
2328         /* Load the address of the RX return ring. */
2329         ctx.bge_maxsegs = 1;
2330         ctx.sc = sc;
2331
2332         error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag,
2333             sc->bge_cdata.bge_rx_return_ring_map,
2334             sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc),
2335             bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2336
2337         if (error)
2338                 return (ENOMEM);
2339
2340         sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr;
2341
2342         /* Create tag for TX ring. */
2343         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2344             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2345             NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL,
2346             &sc->bge_cdata.bge_tx_ring_tag);
2347
2348         if (error) {
2349                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2350                 return (ENOMEM);
2351         }
2352
2353         /* Allocate DMA'able memory for TX ring. */
2354         error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag,
2355             (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT,
2356             &sc->bge_cdata.bge_tx_ring_map);
2357         if (error)
2358                 return (ENOMEM);
2359
2360         bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
2361
2362         /* Load the address of the TX ring. */
2363         ctx.bge_maxsegs = 1;
2364         ctx.sc = sc;
2365
2366         error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag,
2367             sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring,
2368             BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2369
2370         if (error)
2371                 return (ENOMEM);
2372
2373         sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr;
2374
2375         /*
2376          * Create tag for status block.
2377          * Because we only use single Tx/Rx/Rx return ring, use
2378          * minimum status block size except BCM5700 AX/BX which
2379          * seems to want to see full status block size regardless
2380          * of configured number of ring.
2381          */
2382         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2383             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
2384                 sbsz = BGE_STATUS_BLK_SZ;
2385         else
2386                 sbsz = 32;
2387         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2388             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2389             NULL, sbsz, 1, sbsz, 0, NULL, NULL, &sc->bge_cdata.bge_status_tag);
2390
2391         if (error) {
2392                 device_printf(sc->bge_dev,
2393                     "could not allocate status dma tag\n");
2394                 return (ENOMEM);
2395         }
2396
2397         /* Allocate DMA'able memory for status block. */
2398         error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag,
2399             (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT,
2400             &sc->bge_cdata.bge_status_map);
2401         if (error)
2402                 return (ENOMEM);
2403
2404         bzero((char *)sc->bge_ldata.bge_status_block, sbsz);
2405
2406         /* Load the address of the status block. */
2407         ctx.sc = sc;
2408         ctx.bge_maxsegs = 1;
2409
2410         error = bus_dmamap_load(sc->bge_cdata.bge_status_tag,
2411             sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block,
2412             sbsz, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2413
2414         if (error)
2415                 return (ENOMEM);
2416
2417         sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr;
2418
2419         /* Create tag for statistics block. */
2420         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2421             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2422             NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL,
2423             &sc->bge_cdata.bge_stats_tag);
2424
2425         if (error) {
2426                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2427                 return (ENOMEM);
2428         }
2429
2430         /* Allocate DMA'able memory for statistics block. */
2431         error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag,
2432             (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT,
2433             &sc->bge_cdata.bge_stats_map);
2434         if (error)
2435                 return (ENOMEM);
2436
2437         bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ);
2438
2439         /* Load the address of the statstics block. */
2440         ctx.sc = sc;
2441         ctx.bge_maxsegs = 1;
2442
2443         error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag,
2444             sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats,
2445             BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2446
2447         if (error)
2448                 return (ENOMEM);
2449
2450         sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr;
2451
2452         return (0);
2453 }
2454
2455 /*
2456  * Return true if this device has more than one port.
2457  */
2458 static int
2459 bge_has_multiple_ports(struct bge_softc *sc)
2460 {
2461         device_t dev = sc->bge_dev;
2462         u_int b, d, f, fscan, s;
2463
2464         d = pci_get_domain(dev);
2465         b = pci_get_bus(dev);
2466         s = pci_get_slot(dev);
2467         f = pci_get_function(dev);
2468         for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
2469                 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
2470                         return (1);
2471         return (0);
2472 }
2473
2474 /*
2475  * Return true if MSI can be used with this device.
2476  */
2477 static int
2478 bge_can_use_msi(struct bge_softc *sc)
2479 {
2480         int can_use_msi = 0;
2481
2482         switch (sc->bge_asicrev) {
2483         case BGE_ASICREV_BCM5714_A0:
2484         case BGE_ASICREV_BCM5714:
2485                 /*
2486                  * Apparently, MSI doesn't work when these chips are
2487                  * configured in single-port mode.
2488                  */
2489                 if (bge_has_multiple_ports(sc))
2490                         can_use_msi = 1;
2491                 break;
2492         case BGE_ASICREV_BCM5750:
2493                 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
2494                     sc->bge_chiprev != BGE_CHIPREV_5750_BX)
2495                         can_use_msi = 1;
2496                 break;
2497         default:
2498                 if (BGE_IS_575X_PLUS(sc))
2499                         can_use_msi = 1;
2500         }
2501         return (can_use_msi);
2502 }
2503
2504 static int
2505 bge_attach(device_t dev)
2506 {
2507         struct ifnet *ifp;
2508         struct bge_softc *sc;
2509         uint32_t hwcfg = 0, misccfg;
2510         u_char eaddr[ETHER_ADDR_LEN];
2511         int error, msicount, reg, rid, trys;
2512
2513         sc = device_get_softc(dev);
2514         sc->bge_dev = dev;
2515
2516         TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
2517
2518         /*
2519          * Map control/status registers.
2520          */
2521         pci_enable_busmaster(dev);
2522
2523         rid = BGE_PCI_BAR0;
2524         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2525             RF_ACTIVE);
2526
2527         if (sc->bge_res == NULL) {
2528                 device_printf (sc->bge_dev, "couldn't map memory\n");
2529                 error = ENXIO;
2530                 goto fail;
2531         }
2532
2533         /* Save various chip information. */
2534         sc->bge_chipid =
2535             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2536             BGE_PCIMISCCTL_ASICREV_SHIFT;
2537         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
2538                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV,
2539                     4);
2540         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2541         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2542
2543         /*
2544          * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the
2545          * 5705 A0 and A1 chips.
2546          */
2547         if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
2548             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2549             sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2550             sc->bge_chipid != BGE_CHIPID_BCM5705_A1)
2551                 sc->bge_flags |= BGE_FLAG_WIRESPEED;
2552
2553         if (bge_has_eaddr(sc))
2554                 sc->bge_flags |= BGE_FLAG_EADDR;
2555
2556         /* Save chipset family. */
2557         switch (sc->bge_asicrev) {
2558         case BGE_ASICREV_BCM5755:
2559         case BGE_ASICREV_BCM5761:
2560         case BGE_ASICREV_BCM5784:
2561         case BGE_ASICREV_BCM5785:
2562         case BGE_ASICREV_BCM5787:
2563         case BGE_ASICREV_BCM57780:
2564                 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2565                     BGE_FLAG_5705_PLUS;
2566                 break;
2567         case BGE_ASICREV_BCM5700:
2568         case BGE_ASICREV_BCM5701:
2569         case BGE_ASICREV_BCM5703:
2570         case BGE_ASICREV_BCM5704:
2571                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2572                 break;
2573         case BGE_ASICREV_BCM5714_A0:
2574         case BGE_ASICREV_BCM5780:
2575         case BGE_ASICREV_BCM5714:
2576                 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */;
2577                 /* FALLTHROUGH */
2578         case BGE_ASICREV_BCM5750:
2579         case BGE_ASICREV_BCM5752:
2580         case BGE_ASICREV_BCM5906:
2581                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2582                 /* FALLTHROUGH */
2583         case BGE_ASICREV_BCM5705:
2584                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2585                 break;
2586         }
2587
2588         /* Set various bug flags. */
2589         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2590             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2591                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
2592         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2593             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2594                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
2595         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2596                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
2597         if (BGE_IS_5705_PLUS(sc) &&
2598             !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) {
2599                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2600                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2601                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2602                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2603                         if (sc->bge_chipid != BGE_CHIPID_BCM5722_A0)
2604                                 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
2605                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
2606                         sc->bge_flags |= BGE_FLAG_BER_BUG;
2607         }
2608
2609         /*
2610          * All controllers that are not 5755 or higher have 4GB
2611          * boundary DMA bug.
2612          * Whenever an address crosses a multiple of the 4GB boundary
2613          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
2614          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
2615          * state machine will lockup and cause the device to hang.
2616          */
2617         if (BGE_IS_5755_PLUS(sc) == 0)
2618                 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
2619
2620         /*
2621          * We could possibly check for BCOM_DEVICEID_BCM5788 in bge_probe()
2622          * but I do not know the DEVICEID for the 5788M.
2623          */
2624         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID;
2625         if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2626             misccfg == BGE_MISCCFG_BOARD_ID_5788M)
2627                 sc->bge_flags |= BGE_FLAG_5788;
2628
2629         /*
2630          * Some controllers seem to require a special firmware to use
2631          * TSO. But the firmware is not available to FreeBSD and Linux
2632          * claims that the TSO performed by the firmware is slower than
2633          * hardware based TSO. Moreover the firmware based TSO has one
2634          * known bug which can't handle TSO if ethernet header + IP/TCP
2635          * header is greater than 80 bytes. The workaround for the TSO
2636          * bug exist but it seems it's too expensive than not using
2637          * TSO at all. Some hardwares also have the TSO bug so limit
2638          * the TSO to the controllers that are not affected TSO issues
2639          * (e.g. 5755 or higher).
2640          */
2641         if (BGE_IS_5755_PLUS(sc))
2642                 sc->bge_flags |= BGE_FLAG_TSO;
2643
2644         /*
2645          * Check if this is a PCI-X or PCI Express device.
2646          */
2647         if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {
2648                 /*
2649                  * Found a PCI Express capabilities register, this
2650                  * must be a PCI Express device.
2651                  */
2652                 sc->bge_flags |= BGE_FLAG_PCIE;
2653                 sc->bge_expcap = reg;
2654                 bge_set_max_readrq(sc);
2655         } else {
2656                 /*
2657                  * Check if the device is in PCI-X Mode.
2658                  * (This bit is not valid on PCI Express controllers.)
2659                  */
2660                 if (pci_find_extcap(dev, PCIY_PCIX, &reg) == 0)
2661                         sc->bge_pcixcap = reg;
2662                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
2663                     BGE_PCISTATE_PCI_BUSMODE) == 0)
2664                         sc->bge_flags |= BGE_FLAG_PCIX;
2665         }
2666
2667         /*
2668          * The 40bit DMA bug applies to the 5714/5715 controllers and is
2669          * not actually a MAC controller bug but an issue with the embedded
2670          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2671          */
2672         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
2673                 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
2674         /*
2675          * Allocate the interrupt, using MSI if possible.  These devices
2676          * support 8 MSI messages, but only the first one is used in
2677          * normal operation.
2678          */
2679         rid = 0;
2680         if (pci_find_extcap(sc->bge_dev, PCIY_MSI, &reg) != 0) {
2681                 sc->bge_msicap = reg;
2682                 if (bge_can_use_msi(sc)) {
2683                         msicount = pci_msi_count(dev);
2684                         if (msicount > 1)
2685                                 msicount = 1;
2686                 } else
2687                         msicount = 0;
2688                 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
2689                         rid = 1;
2690                         sc->bge_flags |= BGE_FLAG_MSI;
2691                 }
2692         }
2693
2694         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2695             RF_SHAREABLE | RF_ACTIVE);
2696
2697         if (sc->bge_irq == NULL) {
2698                 device_printf(sc->bge_dev, "couldn't map interrupt\n");
2699                 error = ENXIO;
2700                 goto fail;
2701         }
2702
2703         if (bootverbose)
2704                 device_printf(dev,
2705                     "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2706                     sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2707                     (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" :
2708                     ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI"));
2709
2710         BGE_LOCK_INIT(sc, device_get_nameunit(dev));
2711
2712         /* Try to reset the chip. */
2713         if (bge_reset(sc)) {
2714                 device_printf(sc->bge_dev, "chip reset failed\n");
2715                 error = ENXIO;
2716                 goto fail;
2717         }
2718
2719         sc->bge_asf_mode = 0;
2720         if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG)
2721             == BGE_MAGIC_NUMBER)) {
2722                 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG)
2723                     & BGE_HWCFG_ASF) {
2724                         sc->bge_asf_mode |= ASF_ENABLE;
2725                         sc->bge_asf_mode |= ASF_STACKUP;
2726                         if (sc->bge_asicrev == BGE_ASICREV_BCM5750) {
2727                                 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
2728                         }
2729                 }
2730         }
2731
2732         /* Try to reset the chip again the nice way. */
2733         bge_stop_fw(sc);
2734         bge_sig_pre_reset(sc, BGE_RESET_STOP);
2735         if (bge_reset(sc)) {
2736                 device_printf(sc->bge_dev, "chip reset failed\n");
2737                 error = ENXIO;
2738                 goto fail;
2739         }
2740
2741         bge_sig_legacy(sc, BGE_RESET_STOP);
2742         bge_sig_post_reset(sc, BGE_RESET_STOP);
2743
2744         if (bge_chipinit(sc)) {
2745                 device_printf(sc->bge_dev, "chip initialization failed\n");
2746                 error = ENXIO;
2747                 goto fail;
2748         }
2749
2750         error = bge_get_eaddr(sc, eaddr);
2751         if (error) {
2752                 device_printf(sc->bge_dev,
2753                     "failed to read station address\n");
2754                 error = ENXIO;
2755                 goto fail;
2756         }
2757
2758         /* 5705 limits RX return ring to 512 entries. */
2759         if (BGE_IS_5705_PLUS(sc))
2760                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2761         else
2762                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2763
2764         if (bge_dma_alloc(dev)) {
2765                 device_printf(sc->bge_dev,
2766                     "failed to allocate DMA resources\n");
2767                 error = ENXIO;
2768                 goto fail;
2769         }
2770
2771         /* Set default tuneable values. */
2772         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2773         sc->bge_rx_coal_ticks = 150;
2774         sc->bge_tx_coal_ticks = 150;
2775         sc->bge_rx_max_coal_bds = 10;
2776         sc->bge_tx_max_coal_bds = 10;
2777
2778         /* Set up ifnet structure */
2779         ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
2780         if (ifp == NULL) {
2781                 device_printf(sc->bge_dev, "failed to if_alloc()\n");
2782                 error = ENXIO;
2783                 goto fail;
2784         }
2785         ifp->if_softc = sc;
2786         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2787         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2788         ifp->if_ioctl = bge_ioctl;
2789         ifp->if_start = bge_start;
2790         ifp->if_init = bge_init;
2791         ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
2792         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2793         IFQ_SET_READY(&ifp->if_snd);
2794         ifp->if_hwassist = BGE_CSUM_FEATURES;
2795         ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
2796             IFCAP_VLAN_MTU;
2797         if ((sc->bge_flags & BGE_FLAG_TSO) != 0) {
2798                 ifp->if_hwassist |= CSUM_TSO;
2799                 ifp->if_capabilities |= IFCAP_TSO4;
2800         }
2801 #ifdef IFCAP_VLAN_HWCSUM
2802         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
2803 #endif
2804         ifp->if_capenable = ifp->if_capabilities;
2805 #ifdef DEVICE_POLLING
2806         ifp->if_capabilities |= IFCAP_POLLING;
2807 #endif
2808
2809         /*
2810          * 5700 B0 chips do not support checksumming correctly due
2811          * to hardware bugs.
2812          */
2813         if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
2814                 ifp->if_capabilities &= ~IFCAP_HWCSUM;
2815                 ifp->if_capenable &= ~IFCAP_HWCSUM;
2816                 ifp->if_hwassist = 0;
2817         }
2818
2819         /*
2820          * Figure out what sort of media we have by checking the
2821          * hardware config word in the first 32k of NIC internal memory,
2822          * or fall back to examining the EEPROM if necessary.
2823          * Note: on some BCM5700 cards, this value appears to be unset.
2824          * If that's the case, we have to rely on identifying the NIC
2825          * by its PCI subsystem ID, as we do below for the SysKonnect
2826          * SK-9D41.
2827          */
2828         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2829                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2830         else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
2831             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
2832                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2833                     sizeof(hwcfg))) {
2834                         device_printf(sc->bge_dev, "failed to read EEPROM\n");
2835                         error = ENXIO;
2836                         goto fail;
2837                 }
2838                 hwcfg = ntohl(hwcfg);
2839         }
2840
2841         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2842                 sc->bge_flags |= BGE_FLAG_TBI;
2843
2844         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2845         if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41)
2846                 sc->bge_flags |= BGE_FLAG_TBI;
2847
2848         if (sc->bge_flags & BGE_FLAG_TBI) {
2849                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
2850                     bge_ifmedia_sts);
2851                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
2852                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2853                     0, NULL);
2854                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
2855                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
2856                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2857         } else {
2858                 /*
2859                  * Do transceiver setup and tell the firmware the
2860                  * driver is down so we can try to get access the
2861                  * probe if ASF is running.  Retry a couple of times
2862                  * if we get a conflict with the ASF firmware accessing
2863                  * the PHY.
2864                  */
2865                 trys = 0;
2866                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2867 again:
2868                 bge_asf_driver_up(sc);
2869
2870                 if (mii_phy_probe(dev, &sc->bge_miibus,
2871                     bge_ifmedia_upd, bge_ifmedia_sts)) {
2872                         if (trys++ < 4) {
2873                                 device_printf(sc->bge_dev, "Try again\n");
2874                                 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR,
2875                                     BMCR_RESET);
2876                                 goto again;
2877                         }
2878
2879                         device_printf(sc->bge_dev, "MII without any PHY!\n");
2880                         error = ENXIO;
2881                         goto fail;
2882                 }
2883
2884                 /*
2885                  * Now tell the firmware we are going up after probing the PHY
2886                  */
2887                 if (sc->bge_asf_mode & ASF_STACKUP)
2888                         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2889         }
2890
2891         /*
2892          * When using the BCM5701 in PCI-X mode, data corruption has
2893          * been observed in the first few bytes of some received packets.
2894          * Aligning the packet buffer in memory eliminates the corruption.
2895          * Unfortunately, this misaligns the packet payloads.  On platforms
2896          * which do not support unaligned accesses, we will realign the
2897          * payloads by copying the received packets.
2898          */
2899         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2900             sc->bge_flags & BGE_FLAG_PCIX)
2901                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2902
2903         /*
2904          * Call MI attach routine.
2905          */
2906         ether_ifattach(ifp, eaddr);
2907         callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
2908
2909         /* Tell upper layer we support long frames. */
2910         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2911
2912         /*
2913          * Hookup IRQ last.
2914          */
2915 #if __FreeBSD_version > 700030
2916         if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
2917                 /* Take advantage of single-shot MSI. */
2918                 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
2919                     ~BGE_MSIMODE_ONE_SHOT_DISABLE);
2920                 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
2921                     taskqueue_thread_enqueue, &sc->bge_tq);
2922                 if (sc->bge_tq == NULL) {
2923                         device_printf(dev, "could not create taskqueue.\n");
2924                         ether_ifdetach(ifp);
2925                         error = ENXIO;
2926                         goto fail;
2927                 }
2928                 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq",
2929                     device_get_nameunit(sc->bge_dev));
2930                 error = bus_setup_intr(dev, sc->bge_irq,
2931                     INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
2932                     &sc->bge_intrhand);
2933                 if (error)
2934                         ether_ifdetach(ifp);
2935         } else
2936                 error = bus_setup_intr(dev, sc->bge_irq,
2937                     INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
2938                     &sc->bge_intrhand);
2939 #else
2940         error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2941            bge_intr, sc, &sc->bge_intrhand);
2942 #endif
2943
2944         if (error) {
2945                 bge_detach(dev);
2946                 device_printf(sc->bge_dev, "couldn't set up irq\n");
2947         }
2948
2949         bge_add_sysctls(sc);
2950
2951         return (0);
2952
2953 fail:
2954         bge_release_resources(sc);
2955
2956         return (error);
2957 }
2958
2959 static int
2960 bge_detach(device_t dev)
2961 {
2962         struct bge_softc *sc;
2963         struct ifnet *ifp;
2964
2965         sc = device_get_softc(dev);
2966         ifp = sc->bge_ifp;
2967
2968 #ifdef DEVICE_POLLING
2969         if (ifp->if_capenable & IFCAP_POLLING)
2970                 ether_poll_deregister(ifp);
2971 #endif
2972
2973         BGE_LOCK(sc);
2974         bge_stop(sc);
2975         bge_reset(sc);
2976         BGE_UNLOCK(sc);
2977
2978         callout_drain(&sc->bge_stat_ch);
2979
2980         if (sc->bge_tq)
2981                 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
2982         ether_ifdetach(ifp);
2983
2984         if (sc->bge_flags & BGE_FLAG_TBI) {
2985                 ifmedia_removeall(&sc->bge_ifmedia);
2986         } else {
2987                 bus_generic_detach(dev);
2988                 device_delete_child(dev, sc->bge_miibus);
2989         }
2990
2991         bge_release_resources(sc);
2992
2993         return (0);
2994 }
2995
2996 static void
2997 bge_release_resources(struct bge_softc *sc)
2998 {
2999         device_t dev;
3000
3001         dev = sc->bge_dev;
3002
3003         if (sc->bge_tq != NULL)
3004                 taskqueue_free(sc->bge_tq);
3005
3006         if (sc->bge_intrhand != NULL)
3007                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3008
3009         if (sc->bge_irq != NULL)
3010                 bus_release_resource(dev, SYS_RES_IRQ,
3011                     sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
3012
3013         if (sc->bge_flags & BGE_FLAG_MSI)
3014                 pci_release_msi(dev);
3015
3016         if (sc->bge_res != NULL)
3017                 bus_release_resource(dev, SYS_RES_MEMORY,
3018                     BGE_PCI_BAR0, sc->bge_res);
3019
3020         if (sc->bge_ifp != NULL)
3021                 if_free(sc->bge_ifp);
3022
3023         bge_dma_free(sc);
3024
3025         if (mtx_initialized(&sc->bge_mtx))      /* XXX */
3026                 BGE_LOCK_DESTROY(sc);
3027 }
3028
3029 static int
3030 bge_reset(struct bge_softc *sc)
3031 {
3032         device_t dev;
3033         uint32_t cachesize, command, pcistate, reset, val;
3034         void (*write_op)(struct bge_softc *, int, int);
3035         uint16_t devctl;
3036         int i;
3037
3038         dev = sc->bge_dev;
3039
3040         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
3041             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3042                 if (sc->bge_flags & BGE_FLAG_PCIE)
3043                         write_op = bge_writemem_direct;
3044                 else
3045                         write_op = bge_writemem_ind;
3046         } else
3047                 write_op = bge_writereg_ind;
3048
3049         /* Save some important PCI state. */
3050         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
3051         command = pci_read_config(dev, BGE_PCI_CMD, 4);
3052         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3053
3054         pci_write_config(dev, BGE_PCI_MISC_CTL,
3055             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3056             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3057
3058         /* Disable fastboot on controllers that support it. */
3059         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
3060             BGE_IS_5755_PLUS(sc)) {
3061                 if (bootverbose)
3062                         device_printf(sc->bge_dev, "Disabling fastboot\n");
3063                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
3064         }
3065
3066         /*
3067          * Write the magic number to SRAM at offset 0xB50.
3068          * When firmware finishes its initialization it will
3069          * write ~BGE_MAGIC_NUMBER to the same location.
3070          */
3071         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
3072
3073         reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
3074
3075         /* XXX: Broadcom Linux driver. */
3076         if (sc->bge_flags & BGE_FLAG_PCIE) {
3077                 if (CSR_READ_4(sc, 0x7E2C) == 0x60)     /* PCIE 1.0 */
3078                         CSR_WRITE_4(sc, 0x7E2C, 0x20);
3079                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3080                         /* Prevent PCIE link training during global reset */
3081                         CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
3082                         reset |= 1 << 29;
3083                 }
3084         }
3085
3086         /*
3087          * Set GPHY Power Down Override to leave GPHY
3088          * powered up in D0 uninitialized.
3089          */
3090         if (BGE_IS_5705_PLUS(sc))
3091                 reset |= 0x04000000;
3092
3093         /* Issue global reset */
3094         write_op(sc, BGE_MISC_CFG, reset);
3095
3096         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3097                 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3098                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
3099                     val | BGE_VCPU_STATUS_DRV_RESET);
3100                 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
3101                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
3102                     val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
3103         }
3104
3105         DELAY(1000);
3106
3107         /* XXX: Broadcom Linux driver. */
3108         if (sc->bge_flags & BGE_FLAG_PCIE) {
3109                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
3110                         DELAY(500000); /* wait for link training to complete */
3111                         val = pci_read_config(dev, 0xC4, 4);
3112                         pci_write_config(dev, 0xC4, val | (1 << 15), 4);
3113                 }
3114                 devctl = pci_read_config(dev,
3115                     sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
3116                 /* Clear enable no snoop and disable relaxed ordering. */
3117                 devctl &= ~(0x0010 | 0x0800);
3118                 /* Set PCIE max payload size to 128. */
3119                 devctl &= ~PCIM_EXP_CTL_MAX_PAYLOAD;
3120                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL,
3121                     devctl, 2);
3122                 /* Clear error status. */
3123                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA,
3124                     0, 2);
3125         }
3126
3127         /* Reset some of the PCI state that got zapped by reset. */
3128         pci_write_config(dev, BGE_PCI_MISC_CTL,
3129             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3130             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3131         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
3132         pci_write_config(dev, BGE_PCI_CMD, command, 4);
3133         write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
3134
3135         /* Re-enable MSI, if neccesary, and enable the memory arbiter. */
3136         if (BGE_IS_5714_FAMILY(sc)) {
3137                 /* This chip disables MSI on reset. */
3138                 if (sc->bge_flags & BGE_FLAG_MSI) {
3139                         val = pci_read_config(dev,
3140                             sc->bge_msicap + PCIR_MSI_CTRL, 2);
3141                         pci_write_config(dev,
3142                             sc->bge_msicap + PCIR_MSI_CTRL,
3143                             val | PCIM_MSICTRL_MSI_ENABLE, 2);
3144                         val = CSR_READ_4(sc, BGE_MSI_MODE);
3145                         CSR_WRITE_4(sc, BGE_MSI_MODE,
3146                             val | BGE_MSIMODE_ENABLE);
3147                 }
3148                 val = CSR_READ_4(sc, BGE_MARB_MODE);
3149                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
3150         } else
3151                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3152
3153         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3154                 for (i = 0; i < BGE_TIMEOUT; i++) {
3155                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3156                         if (val & BGE_VCPU_STATUS_INIT_DONE)
3157                                 break;
3158                         DELAY(100);
3159                 }
3160                 if (i == BGE_TIMEOUT) {
3161                         device_printf(sc->bge_dev, "reset timed out\n");
3162                         return (1);
3163                 }
3164         } else {
3165                 /*
3166                  * Poll until we see the 1's complement of the magic number.
3167                  * This indicates that the firmware initialization is complete.
3168                  * We expect this to fail if no chip containing the Ethernet
3169                  * address is fitted though.
3170                  */
3171                 for (i = 0; i < BGE_TIMEOUT; i++) {
3172                         DELAY(10);
3173                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
3174                         if (val == ~BGE_MAGIC_NUMBER)
3175                                 break;
3176                 }
3177
3178                 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
3179                         device_printf(sc->bge_dev, "firmware handshake timed out, "
3180                             "found 0x%08x\n", val);
3181         }
3182
3183         /*
3184          * XXX Wait for the value of the PCISTATE register to
3185          * return to its original pre-reset state. This is a
3186          * fairly good indicator of reset completion. If we don't
3187          * wait for the reset to fully complete, trying to read
3188          * from the device's non-PCI registers may yield garbage
3189          * results.
3190          */
3191         for (i = 0; i < BGE_TIMEOUT; i++) {
3192                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
3193                         break;
3194                 DELAY(10);
3195         }
3196
3197         if (sc->bge_flags & BGE_FLAG_PCIE) {
3198                 reset = bge_readmem_ind(sc, 0x7C00);
3199                 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25));
3200         }
3201
3202         /* Fix up byte swapping. */
3203         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
3204             BGE_MODECTL_BYTESWAP_DATA);
3205
3206         /* Tell the ASF firmware we are up */
3207         if (sc->bge_asf_mode & ASF_STACKUP)
3208                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3209
3210         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
3211
3212         /*
3213          * The 5704 in TBI mode apparently needs some special
3214          * adjustment to insure the SERDES drive level is set
3215          * to 1.2V.
3216          */
3217         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
3218             sc->bge_flags & BGE_FLAG_TBI) {
3219                 val = CSR_READ_4(sc, BGE_SERDES_CFG);
3220                 val = (val & ~0xFFF) | 0x880;
3221                 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
3222         }
3223
3224         /* XXX: Broadcom Linux driver. */
3225         if (sc->bge_flags & BGE_FLAG_PCIE &&
3226             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3227                 val = CSR_READ_4(sc, 0x7C00);
3228                 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
3229         }
3230         DELAY(10000);
3231
3232         return(0);
3233 }
3234
3235 /*
3236  * Frame reception handling. This is called if there's a frame
3237  * on the receive return list.
3238  *
3239  * Note: we have to be able to handle two possibilities here:
3240  * 1) the frame is from the jumbo receive ring
3241  * 2) the frame is from the standard receive ring
3242  */
3243
3244 static int
3245 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
3246 {
3247         struct ifnet *ifp;
3248         int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
3249         uint16_t rx_cons;
3250
3251         rx_cons = sc->bge_rx_saved_considx;
3252
3253         /* Nothing to do. */
3254         if (rx_cons == rx_prod)
3255                 return (rx_npkts);
3256
3257         ifp = sc->bge_ifp;
3258
3259         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3260             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
3261         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3262             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
3263         if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
3264             (MCLBYTES - ETHER_ALIGN))
3265                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3266                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
3267
3268         while (rx_cons != rx_prod) {
3269                 struct bge_rx_bd        *cur_rx;
3270                 uint32_t                rxidx;
3271                 struct mbuf             *m = NULL;
3272                 uint16_t                vlan_tag = 0;
3273                 int                     have_tag = 0;
3274
3275 #ifdef DEVICE_POLLING
3276                 if (ifp->if_capenable & IFCAP_POLLING) {
3277                         if (sc->rxcycles <= 0)
3278                                 break;
3279                         sc->rxcycles--;
3280                 }
3281 #endif
3282
3283                 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
3284
3285                 rxidx = cur_rx->bge_idx;
3286                 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
3287
3288                 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
3289                     cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
3290                         have_tag = 1;
3291                         vlan_tag = cur_rx->bge_vlan_tag;
3292                 }
3293
3294                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
3295                         jumbocnt++;
3296                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
3297                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3298                                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3299                                 continue;
3300                         }
3301                         if (bge_newbuf_jumbo(sc, rxidx) != 0) {
3302                                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3303                                 ifp->if_iqdrops++;
3304                                 continue;
3305                         }
3306                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3307                 } else {
3308                         stdcnt++;
3309                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3310                                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3311                                 continue;
3312                         }
3313                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
3314                         if (bge_newbuf_std(sc, rxidx) != 0) {
3315                                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3316                                 ifp->if_iqdrops++;
3317                                 continue;
3318                         }
3319                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3320                 }
3321
3322                 ifp->if_ipackets++;
3323 #ifndef __NO_STRICT_ALIGNMENT
3324                 /*
3325                  * For architectures with strict alignment we must make sure
3326                  * the payload is aligned.
3327                  */
3328                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
3329                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
3330                             cur_rx->bge_len);
3331                         m->m_data += ETHER_ALIGN;
3332                 }
3333 #endif
3334                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3335                 m->m_pkthdr.rcvif = ifp;
3336
3337                 if (ifp->if_capenable & IFCAP_RXCSUM) {
3338                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3339                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3340                                 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
3341                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3342                         }
3343                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
3344                             m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
3345                                 m->m_pkthdr.csum_data =
3346                                     cur_rx->bge_tcp_udp_csum;
3347                                 m->m_pkthdr.csum_flags |=
3348                                     CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
3349                         }
3350                 }
3351
3352                 /*
3353                  * If we received a packet with a vlan tag,
3354                  * attach that information to the packet.
3355                  */
3356                 if (have_tag) {
3357 #if __FreeBSD_version > 700022
3358                         m->m_pkthdr.ether_vtag = vlan_tag;
3359                         m->m_flags |= M_VLANTAG;
3360 #else
3361                         VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag);
3362                         if (m == NULL)
3363                                 continue;
3364 #endif
3365                 }
3366
3367                 if (holdlck != 0) {
3368                         BGE_UNLOCK(sc);
3369                         (*ifp->if_input)(ifp, m);
3370                         BGE_LOCK(sc);
3371                 } else
3372                         (*ifp->if_input)(ifp, m);
3373                 rx_npkts++;
3374
3375                 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
3376                         return (rx_npkts);
3377         }
3378
3379         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3380             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
3381         if (stdcnt > 0)
3382                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3383                     sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
3384
3385         if (jumbocnt > 0)
3386                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3387                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
3388
3389         sc->bge_rx_saved_considx = rx_cons;
3390         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3391         if (stdcnt)
3392                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
3393         if (jumbocnt)
3394                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
3395 #ifdef notyet
3396         /*
3397          * This register wraps very quickly under heavy packet drops.
3398          * If you need correct statistics, you can enable this check.
3399          */
3400         if (BGE_IS_5705_PLUS(sc))
3401                 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3402 #endif
3403         return (rx_npkts);
3404 }
3405
3406 static void
3407 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
3408 {
3409         struct bge_tx_bd *cur_tx = NULL;
3410         struct ifnet *ifp;
3411
3412         BGE_LOCK_ASSERT(sc);
3413
3414         /* Nothing to do. */
3415         if (sc->bge_tx_saved_considx == tx_cons)
3416                 return;
3417
3418         ifp = sc->bge_ifp;
3419
3420         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
3421             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
3422         /*
3423          * Go through our tx ring and free mbufs for those
3424          * frames that have been sent.
3425          */
3426         while (sc->bge_tx_saved_considx != tx_cons) {
3427                 uint32_t                idx = 0;
3428
3429                 idx = sc->bge_tx_saved_considx;
3430                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
3431                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
3432                         ifp->if_opackets++;
3433                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
3434                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
3435                             sc->bge_cdata.bge_tx_dmamap[idx],
3436                             BUS_DMASYNC_POSTWRITE);
3437                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
3438                             sc->bge_cdata.bge_tx_dmamap[idx]);
3439                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
3440                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
3441                 }
3442                 sc->bge_txcnt--;
3443                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3444         }
3445
3446         if (cur_tx != NULL)
3447                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3448         if (sc->bge_txcnt == 0)
3449                 sc->bge_timer = 0;
3450 }
3451
3452 #ifdef DEVICE_POLLING
3453 static int
3454 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3455 {
3456         struct bge_softc *sc = ifp->if_softc;
3457         uint16_t rx_prod, tx_cons;
3458         uint32_t statusword;
3459         int rx_npkts = 0;
3460
3461         BGE_LOCK(sc);
3462         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3463                 BGE_UNLOCK(sc);
3464                 return (rx_npkts);
3465         }
3466
3467         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3468             sc->bge_cdata.bge_status_map,
3469             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3470         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3471         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3472
3473         statusword = atomic_readandclear_32(
3474             &sc->bge_ldata.bge_status_block->bge_status);
3475
3476         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3477             sc->bge_cdata.bge_status_map,
3478             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3479
3480         /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
3481         if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
3482                 sc->bge_link_evt++;
3483
3484         if (cmd == POLL_AND_CHECK_STATUS)
3485                 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3486                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3487                     sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
3488                         bge_link_upd(sc);
3489
3490         sc->rxcycles = count;
3491         rx_npkts = bge_rxeof(sc, rx_prod, 1);
3492         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3493                 BGE_UNLOCK(sc);
3494                 return (rx_npkts);
3495         }
3496         bge_txeof(sc, tx_cons);
3497         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3498                 bge_start_locked(ifp);
3499
3500         BGE_UNLOCK(sc);
3501         return (rx_npkts);
3502 }
3503 #endif /* DEVICE_POLLING */
3504
3505 static int
3506 bge_msi_intr(void *arg)
3507 {
3508         struct bge_softc *sc;
3509
3510         sc = (struct bge_softc *)arg;
3511         /*
3512          * This interrupt is not shared and controller already
3513          * disabled further interrupt.
3514          */
3515         taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
3516         return (FILTER_HANDLED);
3517 }
3518
3519 static void
3520 bge_intr_task(void *arg, int pending)
3521 {
3522         struct bge_softc *sc;
3523         struct ifnet *ifp;
3524         uint32_t status;
3525         uint16_t rx_prod, tx_cons;
3526
3527         sc = (struct bge_softc *)arg;
3528         ifp = sc->bge_ifp;
3529
3530         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3531                 return;
3532
3533         /* Get updated status block. */
3534         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3535             sc->bge_cdata.bge_status_map,
3536             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3537
3538         /* Save producer/consumer indexess. */
3539         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3540         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3541         status = sc->bge_ldata.bge_status_block->bge_status;
3542         sc->bge_ldata.bge_status_block->bge_status = 0;
3543         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3544             sc->bge_cdata.bge_status_map,
3545             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3546         /* Let controller work. */
3547         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3548
3549         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) {
3550                 BGE_LOCK(sc);
3551                 bge_link_upd(sc);
3552                 BGE_UNLOCK(sc);
3553         }
3554         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3555                 /* Check RX return ring producer/consumer. */
3556                 bge_rxeof(sc, rx_prod, 0);
3557         }
3558         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3559                 BGE_LOCK(sc);
3560                 /* Check TX ring producer/consumer. */
3561                 bge_txeof(sc, tx_cons);
3562                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3563                         bge_start_locked(ifp);
3564                 BGE_UNLOCK(sc);
3565         }
3566 }
3567
3568 static void
3569 bge_intr(void *xsc)
3570 {
3571         struct bge_softc *sc;
3572         struct ifnet *ifp;
3573         uint32_t statusword;
3574         uint16_t rx_prod, tx_cons;
3575
3576         sc = xsc;
3577
3578         BGE_LOCK(sc);
3579
3580         ifp = sc->bge_ifp;
3581
3582 #ifdef DEVICE_POLLING
3583         if (ifp->if_capenable & IFCAP_POLLING) {
3584                 BGE_UNLOCK(sc);
3585                 return;
3586         }
3587 #endif
3588
3589         /*
3590          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
3591          * disable interrupts by writing nonzero like we used to, since with
3592          * our current organization this just gives complications and
3593          * pessimizations for re-enabling interrupts.  We used to have races
3594          * instead of the necessary complications.  Disabling interrupts
3595          * would just reduce the chance of a status update while we are
3596          * running (by switching to the interrupt-mode coalescence
3597          * parameters), but this chance is already very low so it is more
3598          * efficient to get another interrupt than prevent it.
3599          *
3600          * We do the ack first to ensure another interrupt if there is a
3601          * status update after the ack.  We don't check for the status
3602          * changing later because it is more efficient to get another
3603          * interrupt than prevent it, not quite as above (not checking is
3604          * a smaller optimization than not toggling the interrupt enable,
3605          * since checking doesn't involve PCI accesses and toggling require
3606          * the status check).  So toggling would probably be a pessimization
3607          * even with MSI.  It would only be needed for using a task queue.
3608          */
3609         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3610
3611         /*
3612          * Do the mandatory PCI flush as well as get the link status.
3613          */
3614         statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
3615
3616         /* Make sure the descriptor ring indexes are coherent. */
3617         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3618             sc->bge_cdata.bge_status_map,
3619             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3620         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3621         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3622         sc->bge_ldata.bge_status_block->bge_status = 0;
3623         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3624             sc->bge_cdata.bge_status_map,
3625             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3626
3627         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3628             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3629             statusword || sc->bge_link_evt)
3630                 bge_link_upd(sc);
3631
3632         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3633                 /* Check RX return ring producer/consumer. */
3634                 bge_rxeof(sc, rx_prod, 1);
3635         }
3636
3637         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3638                 /* Check TX ring producer/consumer. */
3639                 bge_txeof(sc, tx_cons);
3640         }
3641
3642         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3643             !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3644                 bge_start_locked(ifp);
3645
3646         BGE_UNLOCK(sc);
3647 }
3648
3649 static void
3650 bge_asf_driver_up(struct bge_softc *sc)
3651 {
3652         if (sc->bge_asf_mode & ASF_STACKUP) {
3653                 /* Send ASF heartbeat aprox. every 2s */
3654                 if (sc->bge_asf_count)
3655                         sc->bge_asf_count --;
3656                 else {
3657                         sc->bge_asf_count = 5;
3658                         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW,
3659                             BGE_FW_DRV_ALIVE);
3660                         bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4);
3661                         bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3);
3662                         CSR_WRITE_4(sc, BGE_CPU_EVENT,
3663                             CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
3664                 }
3665         }
3666 }
3667
3668 static void
3669 bge_tick(void *xsc)
3670 {
3671         struct bge_softc *sc = xsc;
3672         struct mii_data *mii = NULL;
3673
3674         BGE_LOCK_ASSERT(sc);
3675
3676         /* Synchronize with possible callout reset/stop. */
3677         if (callout_pending(&sc->bge_stat_ch) ||
3678             !callout_active(&sc->bge_stat_ch))
3679                 return;
3680
3681         if (BGE_IS_5705_PLUS(sc))
3682                 bge_stats_update_regs(sc);
3683         else
3684                 bge_stats_update(sc);
3685
3686         if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
3687                 mii = device_get_softc(sc->bge_miibus);
3688                 /*
3689                  * Do not touch PHY if we have link up. This could break
3690                  * IPMI/ASF mode or produce extra input errors
3691                  * (extra errors was reported for bcm5701 & bcm5704).
3692                  */
3693                 if (!sc->bge_link)
3694                         mii_tick(mii);
3695         } else {
3696                 /*
3697                  * Since in TBI mode auto-polling can't be used we should poll
3698                  * link status manually. Here we register pending link event
3699                  * and trigger interrupt.
3700                  */
3701 #ifdef DEVICE_POLLING
3702                 /* In polling mode we poll link state in bge_poll(). */
3703                 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
3704 #endif
3705                 {
3706                 sc->bge_link_evt++;
3707                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3708                     sc->bge_flags & BGE_FLAG_5788)
3709                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3710                 else
3711                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3712                 }
3713         }
3714
3715         bge_asf_driver_up(sc);
3716         bge_watchdog(sc);
3717
3718         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
3719 }
3720
3721 static void
3722 bge_stats_update_regs(struct bge_softc *sc)
3723 {
3724         struct ifnet *ifp;
3725
3726         ifp = sc->bge_ifp;
3727
3728         ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS +
3729             offsetof(struct bge_mac_stats_regs, etherStatsCollisions));
3730
3731         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
3732         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3733         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
3734 }
3735
3736 static void
3737 bge_stats_update(struct bge_softc *sc)
3738 {
3739         struct ifnet *ifp;
3740         bus_size_t stats;
3741         uint32_t cnt;   /* current register value */
3742
3743         ifp = sc->bge_ifp;
3744
3745         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3746
3747 #define READ_STAT(sc, stats, stat) \
3748         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3749
3750         cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
3751         ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
3752         sc->bge_tx_collisions = cnt;
3753
3754         cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
3755         ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
3756         sc->bge_rx_discards = cnt;
3757
3758         cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
3759         ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
3760         sc->bge_tx_discards = cnt;
3761
3762 #undef  READ_STAT
3763 }
3764
3765 /*
3766  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
3767  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
3768  * but when such padded frames employ the bge IP/TCP checksum offload,
3769  * the hardware checksum assist gives incorrect results (possibly
3770  * from incorporating its own padding into the UDP/TCP checksum; who knows).
3771  * If we pad such runts with zeros, the onboard checksum comes out correct.
3772  */
3773 static __inline int
3774 bge_cksum_pad(struct mbuf *m)
3775 {
3776         int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
3777         struct mbuf *last;
3778
3779         /* If there's only the packet-header and we can pad there, use it. */
3780         if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
3781             M_TRAILINGSPACE(m) >= padlen) {
3782                 last = m;
3783         } else {
3784                 /*
3785                  * Walk packet chain to find last mbuf. We will either
3786                  * pad there, or append a new mbuf and pad it.
3787                  */
3788                 for (last = m; last->m_next != NULL; last = last->m_next);
3789                 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
3790                         /* Allocate new empty mbuf, pad it. Compact later. */
3791                         struct mbuf *n;
3792
3793                         MGET(n, M_DONTWAIT, MT_DATA);
3794                         if (n == NULL)
3795                                 return (ENOBUFS);
3796                         n->m_len = 0;
3797                         last->m_next = n;
3798                         last = n;
3799                 }
3800         }
3801
3802         /* Now zero the pad area, to avoid the bge cksum-assist bug. */
3803         memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
3804         last->m_len += padlen;
3805         m->m_pkthdr.len += padlen;
3806
3807         return (0);
3808 }
3809
3810 static struct mbuf *
3811 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss)
3812 {
3813         struct ether_header *eh;
3814         struct ip *ip;
3815         struct tcphdr *tcp;
3816         struct mbuf *n;
3817         uint16_t hlen;
3818         uint32_t ip_off, poff;
3819
3820         if (M_WRITABLE(m) == 0) {
3821                 /* Get a writable copy. */
3822                 n = m_dup(m, M_DONTWAIT);
3823                 m_freem(m);
3824                 if (n == NULL)
3825                         return (NULL);
3826                 m = n;
3827         }
3828         ip_off = sizeof(struct ether_header);
3829         m = m_pullup(m, ip_off);
3830         if (m == NULL)
3831                 return (NULL);
3832         eh = mtod(m, struct ether_header *);
3833         /* Check the existence of VLAN tag. */
3834         if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
3835                 ip_off = sizeof(struct ether_vlan_header);
3836                 m = m_pullup(m, ip_off);
3837                 if (m == NULL)
3838                         return (NULL);
3839         }
3840         m = m_pullup(m, ip_off + sizeof(struct ip));
3841         if (m == NULL)
3842                 return (NULL);
3843         ip = (struct ip *)(mtod(m, char *) + ip_off);
3844         poff = ip_off + (ip->ip_hl << 2);
3845         m = m_pullup(m, poff + sizeof(struct tcphdr));
3846         if (m == NULL)
3847                 return (NULL);
3848         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
3849         m = m_pullup(m, poff + sizeof(struct tcphdr) + tcp->th_off);
3850         if (m == NULL)
3851                 return (NULL);
3852         /*
3853          * It seems controller doesn't modify IP length and TCP pseudo
3854          * checksum. These checksum computed by upper stack should be 0.
3855          */
3856         *mss = m->m_pkthdr.tso_segsz;
3857         ip->ip_sum = 0;
3858         ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
3859         /* Clear pseudo checksum computed by TCP stack. */
3860         tcp->th_sum = 0;
3861         /*
3862          * Broadcom controllers uses different descriptor format for
3863          * TSO depending on ASIC revision. Due to TSO-capable firmware
3864          * license issue and lower performance of firmware based TSO
3865          * we only support hardware based TSO which is applicable for
3866          * BCM5755 or newer controllers. Hardware based TSO uses 11
3867          * bits to store MSS and upper 5 bits are used to store IP/TCP
3868          * header length(including IP/TCP options). The header length
3869          * is expressed as 32 bits unit.
3870          */
3871         hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
3872         *mss |= (hlen << 11);
3873         return (m);
3874 }
3875
3876 /*
3877  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
3878  * pointers to descriptors.
3879  */
3880 static int
3881 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
3882 {
3883         bus_dma_segment_t       segs[BGE_NSEG_NEW];
3884         bus_dmamap_t            map;
3885         struct bge_tx_bd        *d;
3886         struct mbuf             *m = *m_head;
3887         uint32_t                idx = *txidx;
3888         uint16_t                csum_flags, mss, vlan_tag;
3889         int                     nsegs, i, error;
3890
3891         csum_flags = 0;
3892         mss = 0;
3893         vlan_tag = 0;
3894         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
3895                 *m_head = m = bge_setup_tso(sc, m, &mss);
3896                 if (*m_head == NULL)
3897                         return (ENOBUFS);
3898                 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
3899                     BGE_TXBDFLAG_CPU_POST_DMA;
3900         } else if ((m->m_pkthdr.csum_flags & BGE_CSUM_FEATURES) != 0) {
3901                 if (m->m_pkthdr.csum_flags & CSUM_IP)
3902                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3903                 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
3904                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3905                         if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
3906                             (error = bge_cksum_pad(m)) != 0) {
3907                                 m_freem(m);
3908                                 *m_head = NULL;
3909                                 return (error);
3910                         }
3911                 }
3912                 if (m->m_flags & M_LASTFRAG)
3913                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3914                 else if (m->m_flags & M_FRAG)
3915                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3916         }
3917
3918         map = sc->bge_cdata.bge_tx_dmamap[idx];
3919         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
3920             &nsegs, BUS_DMA_NOWAIT);
3921         if (error == EFBIG) {
3922                 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW);
3923                 if (m == NULL) {
3924                         m_freem(*m_head);
3925                         *m_head = NULL;
3926                         return (ENOBUFS);
3927                 }
3928                 *m_head = m;
3929                 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
3930                     m, segs, &nsegs, BUS_DMA_NOWAIT);
3931                 if (error) {
3932                         m_freem(m);
3933                         *m_head = NULL;
3934                         return (error);
3935                 }
3936         } else if (error != 0)
3937                 return (error);
3938
3939         /* Check if we have enough free send BDs. */
3940         if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
3941                 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
3942                 return (ENOBUFS);
3943         }
3944
3945         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3946
3947 #if __FreeBSD_version > 700022
3948         if (m->m_flags & M_VLANTAG) {
3949                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
3950                 vlan_tag = m->m_pkthdr.ether_vtag;
3951         }
3952 #else
3953         {
3954                 struct m_tag            *mtag;
3955
3956                 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) {
3957                         csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
3958                         vlan_tag = VLAN_TAG_VALUE(mtag);
3959                 }
3960         }
3961 #endif
3962         for (i = 0; ; i++) {
3963                 d = &sc->bge_ldata.bge_tx_ring[idx];
3964                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3965                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3966                 d->bge_len = segs[i].ds_len;
3967                 d->bge_flags = csum_flags;
3968                 d->bge_vlan_tag = vlan_tag;
3969                 d->bge_mss = mss;
3970                 if (i == nsegs - 1)
3971                         break;
3972                 BGE_INC(idx, BGE_TX_RING_CNT);
3973         }
3974
3975         /* Mark the last segment as end of packet... */
3976         d->bge_flags |= BGE_TXBDFLAG_END;
3977
3978         /*
3979          * Insure that the map for this transmission
3980          * is placed at the array index of the last descriptor
3981          * in this chain.
3982          */
3983         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
3984         sc->bge_cdata.bge_tx_dmamap[idx] = map;
3985         sc->bge_cdata.bge_tx_chain[idx] = m;
3986         sc->bge_txcnt += nsegs;
3987
3988         BGE_INC(idx, BGE_TX_RING_CNT);
3989         *txidx = idx;
3990
3991         return (0);
3992 }
3993
3994 /*
3995  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3996  * to the mbuf data regions directly in the transmit descriptors.
3997  */
3998 static void
3999 bge_start_locked(struct ifnet *ifp)
4000 {
4001         struct bge_softc *sc;
4002         struct mbuf *m_head;
4003         uint32_t prodidx;
4004         int count;
4005
4006         sc = ifp->if_softc;
4007         BGE_LOCK_ASSERT(sc);
4008
4009         if (!sc->bge_link ||
4010             (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4011             IFF_DRV_RUNNING)
4012                 return;
4013
4014         prodidx = sc->bge_tx_prodidx;
4015
4016         for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
4017                 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
4018                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4019                         break;
4020                 }
4021                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
4022                 if (m_head == NULL)
4023                         break;
4024
4025                 /*
4026                  * XXX
4027                  * The code inside the if() block is never reached since we
4028                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
4029                  * requests to checksum TCP/UDP in a fragmented packet.
4030                  *
4031                  * XXX
4032                  * safety overkill.  If this is a fragmented packet chain
4033                  * with delayed TCP/UDP checksums, then only encapsulate
4034                  * it if we have enough descriptors to handle the entire
4035                  * chain at once.
4036                  * (paranoia -- may not actually be needed)
4037                  */
4038                 if (m_head->m_flags & M_FIRSTFRAG &&
4039                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
4040                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
4041                             m_head->m_pkthdr.csum_data + 16) {
4042                                 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4043                                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4044                                 break;
4045                         }
4046                 }
4047
4048                 /*
4049                  * Pack the data into the transmit ring. If we
4050                  * don't have room, set the OACTIVE flag and wait
4051                  * for the NIC to drain the ring.
4052                  */
4053                 if (bge_encap(sc, &m_head, &prodidx)) {
4054                         if (m_head == NULL)
4055                                 break;
4056                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4057                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4058                         break;
4059                 }
4060                 ++count;
4061
4062                 /*
4063                  * If there's a BPF listener, bounce a copy of this frame
4064                  * to him.
4065                  */
4066 #ifdef ETHER_BPF_MTAP
4067                 ETHER_BPF_MTAP(ifp, m_head);
4068 #else
4069                 BPF_MTAP(ifp, m_head);
4070 #endif
4071         }
4072
4073         if (count > 0) {
4074                 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4075                     sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
4076                 /* Transmit. */
4077                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4078                 /* 5700 b2 errata */
4079                 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
4080                         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4081
4082                 sc->bge_tx_prodidx = prodidx;
4083
4084                 /*
4085                  * Set a timeout in case the chip goes out to lunch.
4086                  */
4087                 sc->bge_timer = 5;
4088         }
4089 }
4090
4091 /*
4092  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4093  * to the mbuf data regions directly in the transmit descriptors.
4094  */
4095 static void
4096 bge_start(struct ifnet *ifp)
4097 {
4098         struct bge_softc *sc;
4099
4100         sc = ifp->if_softc;
4101         BGE_LOCK(sc);
4102         bge_start_locked(ifp);
4103         BGE_UNLOCK(sc);
4104 }
4105
4106 static void
4107 bge_init_locked(struct bge_softc *sc)
4108 {
4109         struct ifnet *ifp;
4110         uint16_t *m;
4111
4112         BGE_LOCK_ASSERT(sc);
4113
4114         ifp = sc->bge_ifp;
4115
4116         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4117                 return;
4118
4119         /* Cancel pending I/O and flush buffers. */
4120         bge_stop(sc);
4121
4122         bge_stop_fw(sc);
4123         bge_sig_pre_reset(sc, BGE_RESET_START);
4124         bge_reset(sc);
4125         bge_sig_legacy(sc, BGE_RESET_START);
4126         bge_sig_post_reset(sc, BGE_RESET_START);
4127
4128         bge_chipinit(sc);
4129
4130         /*
4131          * Init the various state machines, ring
4132          * control blocks and firmware.
4133          */
4134         if (bge_blockinit(sc)) {
4135                 device_printf(sc->bge_dev, "initialization failure\n");
4136                 return;
4137         }
4138
4139         ifp = sc->bge_ifp;
4140
4141         /* Specify MTU. */
4142         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
4143             ETHER_HDR_LEN + ETHER_CRC_LEN +
4144             (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
4145
4146         /* Load our MAC address. */
4147         m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
4148         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
4149         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
4150
4151         /* Program promiscuous mode. */
4152         bge_setpromisc(sc);
4153
4154         /* Program multicast filter. */
4155         bge_setmulti(sc);
4156
4157         /* Program VLAN tag stripping. */
4158         bge_setvlan(sc);
4159
4160         /* Init RX ring. */
4161         if (bge_init_rx_ring_std(sc) != 0) {
4162                 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
4163                 bge_stop(sc);
4164                 return;
4165         }
4166
4167         /*
4168          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
4169          * memory to insure that the chip has in fact read the first
4170          * entry of the ring.
4171          */
4172         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
4173                 uint32_t                v, i;
4174                 for (i = 0; i < 10; i++) {
4175                         DELAY(20);
4176                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
4177                         if (v == (MCLBYTES - ETHER_ALIGN))
4178                                 break;
4179                 }
4180                 if (i == 10)
4181                         device_printf (sc->bge_dev,
4182                             "5705 A0 chip failed to load RX ring\n");
4183         }
4184
4185         /* Init jumbo RX ring. */
4186         if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
4187             (MCLBYTES - ETHER_ALIGN)) {
4188                 if (bge_init_rx_ring_jumbo(sc) != 0) {
4189                         device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
4190                         bge_stop(sc);
4191                         return;
4192                 }
4193         }
4194
4195         /* Init our RX return ring index. */
4196         sc->bge_rx_saved_considx = 0;
4197
4198         /* Init our RX/TX stat counters. */
4199         sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
4200
4201         /* Init TX ring. */
4202         bge_init_tx_ring(sc);
4203
4204         /* Turn on transmitter. */
4205         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
4206
4207         /* Turn on receiver. */
4208         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4209
4210         /* Tell firmware we're alive. */
4211         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4212
4213 #ifdef DEVICE_POLLING
4214         /* Disable interrupts if we are polling. */
4215         if (ifp->if_capenable & IFCAP_POLLING) {
4216                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4217                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4218                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4219         } else
4220 #endif
4221
4222         /* Enable host interrupts. */
4223         {
4224         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
4225         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4226         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4227         }
4228
4229         bge_ifmedia_upd_locked(ifp);
4230
4231         ifp->if_drv_flags |= IFF_DRV_RUNNING;
4232         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4233
4234         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4235 }
4236
4237 static void
4238 bge_init(void *xsc)
4239 {
4240         struct bge_softc *sc = xsc;
4241
4242         BGE_LOCK(sc);
4243         bge_init_locked(sc);
4244         BGE_UNLOCK(sc);
4245 }
4246
4247 /*
4248  * Set media options.
4249  */
4250 static int
4251 bge_ifmedia_upd(struct ifnet *ifp)
4252 {
4253         struct bge_softc *sc = ifp->if_softc;
4254         int res;
4255
4256         BGE_LOCK(sc);
4257         res = bge_ifmedia_upd_locked(ifp);
4258         BGE_UNLOCK(sc);
4259
4260         return (res);
4261 }
4262
4263 static int
4264 bge_ifmedia_upd_locked(struct ifnet *ifp)
4265 {
4266         struct bge_softc *sc = ifp->if_softc;
4267         struct mii_data *mii;
4268         struct mii_softc *miisc;
4269         struct ifmedia *ifm;
4270
4271         BGE_LOCK_ASSERT(sc);
4272
4273         ifm = &sc->bge_ifmedia;
4274
4275         /* If this is a 1000baseX NIC, enable the TBI port. */
4276         if (sc->bge_flags & BGE_FLAG_TBI) {
4277                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
4278                         return (EINVAL);
4279                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
4280                 case IFM_AUTO:
4281                         /*
4282                          * The BCM5704 ASIC appears to have a special
4283                          * mechanism for programming the autoneg
4284                          * advertisement registers in TBI mode.
4285                          */
4286                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4287                                 uint32_t sgdig;
4288                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
4289                                 if (sgdig & BGE_SGDIGSTS_DONE) {
4290                                         CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
4291                                         sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
4292                                         sgdig |= BGE_SGDIGCFG_AUTO |
4293                                             BGE_SGDIGCFG_PAUSE_CAP |
4294                                             BGE_SGDIGCFG_ASYM_PAUSE;
4295                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG,
4296                                             sgdig | BGE_SGDIGCFG_SEND);
4297                                         DELAY(5);
4298                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
4299                                 }
4300                         }
4301                         break;
4302                 case IFM_1000_SX:
4303                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
4304                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
4305                                     BGE_MACMODE_HALF_DUPLEX);
4306                         } else {
4307                                 BGE_SETBIT(sc, BGE_MAC_MODE,
4308                                     BGE_MACMODE_HALF_DUPLEX);
4309                         }
4310                         break;
4311                 default:
4312                         return (EINVAL);
4313                 }
4314                 return (0);
4315         }
4316
4317         sc->bge_link_evt++;
4318         mii = device_get_softc(sc->bge_miibus);
4319         if (mii->mii_instance)
4320                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4321                         mii_phy_reset(miisc);
4322         mii_mediachg(mii);
4323
4324         /*
4325          * Force an interrupt so that we will call bge_link_upd
4326          * if needed and clear any pending link state attention.
4327          * Without this we are not getting any further interrupts
4328          * for link state changes and thus will not UP the link and
4329          * not be able to send in bge_start_locked. The only
4330          * way to get things working was to receive a packet and
4331          * get an RX intr.
4332          * bge_tick should help for fiber cards and we might not
4333          * need to do this here if BGE_FLAG_TBI is set but as
4334          * we poll for fiber anyway it should not harm.
4335          */
4336         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4337             sc->bge_flags & BGE_FLAG_5788)
4338                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4339         else
4340                 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4341
4342         return (0);
4343 }
4344
4345 /*
4346  * Report current media status.
4347  */
4348 static void
4349 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4350 {
4351         struct bge_softc *sc = ifp->if_softc;
4352         struct mii_data *mii;
4353
4354         BGE_LOCK(sc);
4355
4356         if (sc->bge_flags & BGE_FLAG_TBI) {
4357                 ifmr->ifm_status = IFM_AVALID;
4358                 ifmr->ifm_active = IFM_ETHER;
4359                 if (CSR_READ_4(sc, BGE_MAC_STS) &
4360                     BGE_MACSTAT_TBI_PCS_SYNCHED)
4361                         ifmr->ifm_status |= IFM_ACTIVE;
4362                 else {
4363                         ifmr->ifm_active |= IFM_NONE;
4364                         BGE_UNLOCK(sc);
4365                         return;
4366                 }
4367                 ifmr->ifm_active |= IFM_1000_SX;
4368                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
4369                         ifmr->ifm_active |= IFM_HDX;
4370                 else
4371                         ifmr->ifm_active |= IFM_FDX;
4372                 BGE_UNLOCK(sc);
4373                 return;
4374         }
4375
4376         mii = device_get_softc(sc->bge_miibus);
4377         mii_pollstat(mii);
4378         ifmr->ifm_active = mii->mii_media_active;
4379         ifmr->ifm_status = mii->mii_media_status;
4380
4381         BGE_UNLOCK(sc);
4382 }
4383
4384 static int
4385 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
4386 {
4387         struct bge_softc *sc = ifp->if_softc;
4388         struct ifreq *ifr = (struct ifreq *) data;
4389         struct mii_data *mii;
4390         int flags, mask, error = 0;
4391
4392         switch (command) {
4393         case SIOCSIFMTU:
4394                 if (ifr->ifr_mtu < ETHERMIN ||
4395                     ((BGE_IS_JUMBO_CAPABLE(sc)) &&
4396                     ifr->ifr_mtu > BGE_JUMBO_MTU) ||
4397                     ((!BGE_IS_JUMBO_CAPABLE(sc)) &&
4398                     ifr->ifr_mtu > ETHERMTU))
4399                         error = EINVAL;
4400                 else if (ifp->if_mtu != ifr->ifr_mtu) {
4401                         ifp->if_mtu = ifr->ifr_mtu;
4402                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4403                         bge_init(sc);
4404                 }
4405                 break;
4406         case SIOCSIFFLAGS:
4407                 BGE_LOCK(sc);
4408                 if (ifp->if_flags & IFF_UP) {
4409                         /*
4410                          * If only the state of the PROMISC flag changed,
4411                          * then just use the 'set promisc mode' command
4412                          * instead of reinitializing the entire NIC. Doing
4413                          * a full re-init means reloading the firmware and
4414                          * waiting for it to start up, which may take a
4415                          * second or two.  Similarly for ALLMULTI.
4416                          */
4417                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4418                                 flags = ifp->if_flags ^ sc->bge_if_flags;
4419                                 if (flags & IFF_PROMISC)
4420                                         bge_setpromisc(sc);
4421                                 if (flags & IFF_ALLMULTI)
4422                                         bge_setmulti(sc);
4423                         } else
4424                                 bge_init_locked(sc);
4425                 } else {
4426                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4427                                 bge_stop(sc);
4428                         }
4429                 }
4430                 sc->bge_if_flags = ifp->if_flags;
4431                 BGE_UNLOCK(sc);
4432                 error = 0;
4433                 break;
4434         case SIOCADDMULTI:
4435         case SIOCDELMULTI:
4436                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4437                         BGE_LOCK(sc);
4438                         bge_setmulti(sc);
4439                         BGE_UNLOCK(sc);
4440                         error = 0;
4441                 }
4442                 break;
4443         case SIOCSIFMEDIA:
4444         case SIOCGIFMEDIA:
4445                 if (sc->bge_flags & BGE_FLAG_TBI) {
4446                         error = ifmedia_ioctl(ifp, ifr,
4447                             &sc->bge_ifmedia, command);
4448                 } else {
4449                         mii = device_get_softc(sc->bge_miibus);
4450                         error = ifmedia_ioctl(ifp, ifr,
4451                             &mii->mii_media, command);
4452                 }
4453                 break;
4454         case SIOCSIFCAP:
4455                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
4456 #ifdef DEVICE_POLLING
4457                 if (mask & IFCAP_POLLING) {
4458                         if (ifr->ifr_reqcap & IFCAP_POLLING) {
4459                                 error = ether_poll_register(bge_poll, ifp);
4460                                 if (error)
4461                                         return (error);
4462                                 BGE_LOCK(sc);
4463                                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4464                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4465                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4466                                 ifp->if_capenable |= IFCAP_POLLING;
4467                                 BGE_UNLOCK(sc);
4468                         } else {
4469                                 error = ether_poll_deregister(ifp);
4470                                 /* Enable interrupt even in error case */
4471                                 BGE_LOCK(sc);
4472                                 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
4473                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4474                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4475                                 ifp->if_capenable &= ~IFCAP_POLLING;
4476                                 BGE_UNLOCK(sc);
4477                         }
4478                 }
4479 #endif
4480                 if (mask & IFCAP_HWCSUM) {
4481                         ifp->if_capenable ^= IFCAP_HWCSUM;
4482                         if (IFCAP_HWCSUM & ifp->if_capenable &&
4483                             IFCAP_HWCSUM & ifp->if_capabilities)
4484                                 ifp->if_hwassist |= BGE_CSUM_FEATURES;
4485                         else
4486                                 ifp->if_hwassist &= ~BGE_CSUM_FEATURES;
4487 #ifdef VLAN_CAPABILITIES
4488                         VLAN_CAPABILITIES(ifp);
4489 #endif
4490                 }
4491
4492                 if ((mask & IFCAP_TSO4) != 0 &&
4493                     (ifp->if_capabilities & IFCAP_TSO4) != 0) {
4494                         ifp->if_capenable ^= IFCAP_TSO4;
4495                         if ((ifp->if_capenable & IFCAP_TSO4) != 0)
4496                                 ifp->if_hwassist |= CSUM_TSO;
4497                         else
4498                                 ifp->if_hwassist &= ~CSUM_TSO;
4499                 }
4500
4501                 if (mask & IFCAP_VLAN_MTU) {
4502                         ifp->if_capenable ^= IFCAP_VLAN_MTU;
4503                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4504                         bge_init(sc);
4505                 }
4506
4507                 if (mask & IFCAP_VLAN_HWTAGGING) {
4508                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
4509                         BGE_LOCK(sc);
4510                         bge_setvlan(sc);
4511                         BGE_UNLOCK(sc);
4512 #ifdef VLAN_CAPABILITIES
4513                         VLAN_CAPABILITIES(ifp);
4514 #endif
4515                 }
4516
4517                 break;
4518         default:
4519                 error = ether_ioctl(ifp, command, data);
4520                 break;
4521         }
4522
4523         return (error);
4524 }
4525
4526 static void
4527 bge_watchdog(struct bge_softc *sc)
4528 {
4529         struct ifnet *ifp;
4530
4531         BGE_LOCK_ASSERT(sc);
4532
4533         if (sc->bge_timer == 0 || --sc->bge_timer)
4534                 return;
4535
4536         ifp = sc->bge_ifp;
4537
4538         if_printf(ifp, "watchdog timeout -- resetting\n");
4539
4540         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4541         bge_init_locked(sc);
4542
4543         ifp->if_oerrors++;
4544 }
4545
4546 /*
4547  * Stop the adapter and free any mbufs allocated to the
4548  * RX and TX lists.
4549  */
4550 static void
4551 bge_stop(struct bge_softc *sc)
4552 {
4553         struct ifnet *ifp;
4554         struct ifmedia_entry *ifm;
4555         struct mii_data *mii = NULL;
4556         int mtmp, itmp;
4557
4558         BGE_LOCK_ASSERT(sc);
4559
4560         ifp = sc->bge_ifp;
4561
4562         if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
4563                 mii = device_get_softc(sc->bge_miibus);
4564
4565         callout_stop(&sc->bge_stat_ch);
4566
4567         /* Disable host interrupts. */
4568         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4569         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4570
4571         /*
4572          * Tell firmware we're shutting down.
4573          */
4574         bge_stop_fw(sc);
4575         bge_sig_pre_reset(sc, BGE_RESET_STOP);
4576
4577         /*
4578          * Disable all of the receiver blocks.
4579          */
4580         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4581         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
4582         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
4583         if (!(BGE_IS_5705_PLUS(sc)))
4584                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
4585         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
4586         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
4587         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
4588
4589         /*
4590          * Disable all of the transmit blocks.
4591          */
4592         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
4593         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
4594         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
4595         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
4596         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
4597         if (!(BGE_IS_5705_PLUS(sc)))
4598                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
4599         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
4600
4601         /*
4602          * Shut down all of the memory managers and related
4603          * state machines.
4604          */
4605         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
4606         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
4607         if (!(BGE_IS_5705_PLUS(sc)))
4608                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
4609         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
4610         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
4611         if (!(BGE_IS_5705_PLUS(sc))) {
4612                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
4613                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4614         }
4615
4616         bge_reset(sc);
4617         bge_sig_legacy(sc, BGE_RESET_STOP);
4618         bge_sig_post_reset(sc, BGE_RESET_STOP);
4619
4620         /*
4621          * Keep the ASF firmware running if up.
4622          */
4623         if (sc->bge_asf_mode & ASF_STACKUP)
4624                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4625         else
4626                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4627
4628         /* Free the RX lists. */
4629         bge_free_rx_ring_std(sc);
4630
4631         /* Free jumbo RX list. */
4632         if (BGE_IS_JUMBO_CAPABLE(sc))
4633                 bge_free_rx_ring_jumbo(sc);
4634
4635         /* Free TX buffers. */
4636         bge_free_tx_ring(sc);
4637
4638         /*
4639          * Isolate/power down the PHY, but leave the media selection
4640          * unchanged so that things will be put back to normal when
4641          * we bring the interface back up.
4642          */
4643         if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4644                 itmp = ifp->if_flags;
4645                 ifp->if_flags |= IFF_UP;
4646                 /*
4647                  * If we are called from bge_detach(), mii is already NULL.
4648                  */
4649                 if (mii != NULL) {
4650                         ifm = mii->mii_media.ifm_cur;
4651                         mtmp = ifm->ifm_media;
4652                         ifm->ifm_media = IFM_ETHER | IFM_NONE;
4653                         mii_mediachg(mii);
4654                         ifm->ifm_media = mtmp;
4655                 }
4656                 ifp->if_flags = itmp;
4657         }
4658
4659         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
4660
4661         /* Clear MAC's link state (PHY may still have link UP). */
4662         if (bootverbose && sc->bge_link)
4663                 if_printf(sc->bge_ifp, "link DOWN\n");
4664         sc->bge_link = 0;
4665
4666         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4667 }
4668
4669 /*
4670  * Stop all chip I/O so that the kernel's probe routines don't
4671  * get confused by errant DMAs when rebooting.
4672  */
4673 static int
4674 bge_shutdown(device_t dev)
4675 {
4676         struct bge_softc *sc;
4677
4678         sc = device_get_softc(dev);
4679         BGE_LOCK(sc);
4680         bge_stop(sc);
4681         bge_reset(sc);
4682         BGE_UNLOCK(sc);
4683
4684         return (0);
4685 }
4686
4687 static int
4688 bge_suspend(device_t dev)
4689 {
4690         struct bge_softc *sc;
4691
4692         sc = device_get_softc(dev);
4693         BGE_LOCK(sc);
4694         bge_stop(sc);
4695         BGE_UNLOCK(sc);
4696
4697         return (0);
4698 }
4699
4700 static int
4701 bge_resume(device_t dev)
4702 {
4703         struct bge_softc *sc;
4704         struct ifnet *ifp;
4705
4706         sc = device_get_softc(dev);
4707         BGE_LOCK(sc);
4708         ifp = sc->bge_ifp;
4709         if (ifp->if_flags & IFF_UP) {
4710                 bge_init_locked(sc);
4711                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4712                         bge_start_locked(ifp);
4713         }
4714         BGE_UNLOCK(sc);
4715
4716         return (0);
4717 }
4718
4719 static void
4720 bge_link_upd(struct bge_softc *sc)
4721 {
4722         struct mii_data *mii;
4723         uint32_t link, status;
4724
4725         BGE_LOCK_ASSERT(sc);
4726
4727         /* Clear 'pending link event' flag. */
4728         sc->bge_link_evt = 0;
4729
4730         /*
4731          * Process link state changes.
4732          * Grrr. The link status word in the status block does
4733          * not work correctly on the BCM5700 rev AX and BX chips,
4734          * according to all available information. Hence, we have
4735          * to enable MII interrupts in order to properly obtain
4736          * async link changes. Unfortunately, this also means that
4737          * we have to read the MAC status register to detect link
4738          * changes, thereby adding an additional register access to
4739          * the interrupt handler.
4740          *
4741          * XXX: perhaps link state detection procedure used for
4742          * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
4743          */
4744
4745         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4746             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
4747                 status = CSR_READ_4(sc, BGE_MAC_STS);
4748                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
4749                         mii = device_get_softc(sc->bge_miibus);
4750                         mii_pollstat(mii);
4751                         if (!sc->bge_link &&
4752                             mii->mii_media_status & IFM_ACTIVE &&
4753                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4754                                 sc->bge_link++;
4755                                 if (bootverbose)
4756                                         if_printf(sc->bge_ifp, "link UP\n");
4757                         } else if (sc->bge_link &&
4758                             (!(mii->mii_media_status & IFM_ACTIVE) ||
4759                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4760                                 sc->bge_link = 0;
4761                                 if (bootverbose)
4762                                         if_printf(sc->bge_ifp, "link DOWN\n");
4763                         }
4764
4765                         /* Clear the interrupt. */
4766                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
4767                             BGE_EVTENB_MI_INTERRUPT);
4768                         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4769                         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
4770                             BRGPHY_INTRS);
4771                 }
4772                 return;
4773         }
4774
4775         if (sc->bge_flags & BGE_FLAG_TBI) {
4776                 status = CSR_READ_4(sc, BGE_MAC_STS);
4777                 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4778                         if (!sc->bge_link) {
4779                                 sc->bge_link++;
4780                                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
4781                                         BGE_CLRBIT(sc, BGE_MAC_MODE,
4782                                             BGE_MACMODE_TBI_SEND_CFGS);
4783                                 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4784                                 if (bootverbose)
4785                                         if_printf(sc->bge_ifp, "link UP\n");
4786                                 if_link_state_change(sc->bge_ifp,
4787                                     LINK_STATE_UP);
4788                         }
4789                 } else if (sc->bge_link) {
4790                         sc->bge_link = 0;
4791                         if (bootverbose)
4792                                 if_printf(sc->bge_ifp, "link DOWN\n");
4793                         if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
4794                 }
4795         } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
4796                 /*
4797                  * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
4798                  * in status word always set. Workaround this bug by reading
4799                  * PHY link status directly.
4800                  */
4801                 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
4802
4803                 if (link != sc->bge_link ||
4804                     sc->bge_asicrev == BGE_ASICREV_BCM5700) {
4805                         mii = device_get_softc(sc->bge_miibus);
4806                         mii_pollstat(mii);
4807                         if (!sc->bge_link &&
4808                             mii->mii_media_status & IFM_ACTIVE &&
4809                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4810                                 sc->bge_link++;
4811                                 if (bootverbose)
4812                                         if_printf(sc->bge_ifp, "link UP\n");
4813                         } else if (sc->bge_link &&
4814                             (!(mii->mii_media_status & IFM_ACTIVE) ||
4815                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4816                                 sc->bge_link = 0;
4817                                 if (bootverbose)
4818                                         if_printf(sc->bge_ifp, "link DOWN\n");
4819                         }
4820                 }
4821         } else {
4822                 /*
4823                  * Discard link events for MII/GMII controllers
4824                  * if MI auto-polling is disabled.
4825                  */
4826         }
4827
4828         /* Clear the attention. */
4829         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4830             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4831             BGE_MACSTAT_LINK_CHANGED);
4832 }
4833
4834 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
4835         SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
4836             sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
4837             desc)
4838
4839 static void
4840 bge_add_sysctls(struct bge_softc *sc)
4841 {
4842         struct sysctl_ctx_list *ctx;
4843         struct sysctl_oid_list *children, *schildren;
4844         struct sysctl_oid *tree;
4845
4846         ctx = device_get_sysctl_ctx(sc->bge_dev);
4847         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
4848
4849 #ifdef BGE_REGISTER_DEBUG
4850         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
4851             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
4852             "Debug Information");
4853
4854         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
4855             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
4856             "Register Read");
4857
4858         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
4859             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
4860             "Memory Read");
4861
4862 #endif
4863
4864         if (BGE_IS_5705_PLUS(sc))
4865                 return;
4866
4867         tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
4868             NULL, "BGE Statistics");
4869         schildren = children = SYSCTL_CHILDREN(tree);
4870         BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
4871             children, COSFramesDroppedDueToFilters,
4872             "FramesDroppedDueToFilters");
4873         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
4874             children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
4875         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
4876             children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
4877         BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
4878             children, nicNoMoreRxBDs, "NoMoreRxBDs");
4879         BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
4880             children, ifInDiscards, "InputDiscards");
4881         BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
4882             children, ifInErrors, "InputErrors");
4883         BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
4884             children, nicRecvThresholdHit, "RecvThresholdHit");
4885         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
4886             children, nicDmaReadQueueFull, "DmaReadQueueFull");
4887         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
4888             children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
4889         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
4890             children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
4891         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
4892             children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
4893         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
4894             children, nicRingStatusUpdate, "RingStatusUpdate");
4895         BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
4896             children, nicInterrupts, "Interrupts");
4897         BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
4898             children, nicAvoidedInterrupts, "AvoidedInterrupts");
4899         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
4900             children, nicSendThresholdHit, "SendThresholdHit");
4901
4902         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
4903             NULL, "BGE RX Statistics");
4904         children = SYSCTL_CHILDREN(tree);
4905         BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
4906             children, rxstats.ifHCInOctets, "Octets");
4907         BGE_SYSCTL_STAT(sc, ctx, "Fragments",
4908             children, rxstats.etherStatsFragments, "Fragments");
4909         BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
4910             children, rxstats.ifHCInUcastPkts, "UcastPkts");
4911         BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
4912             children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
4913         BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
4914             children, rxstats.dot3StatsFCSErrors, "FCSErrors");
4915         BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
4916             children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
4917         BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
4918             children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
4919         BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
4920             children, rxstats.xoffPauseFramesReceived,
4921             "xoffPauseFramesReceived");
4922         BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
4923             children, rxstats.macControlFramesReceived,
4924             "ControlFramesReceived");
4925         BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
4926             children, rxstats.xoffStateEntered, "xoffStateEntered");
4927         BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
4928             children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
4929         BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
4930             children, rxstats.etherStatsJabbers, "Jabbers");
4931         BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
4932             children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
4933         BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
4934             children, rxstats.inRangeLengthError, "inRangeLengthError");
4935         BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
4936             children, rxstats.outRangeLengthError, "outRangeLengthError");
4937
4938         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
4939             NULL, "BGE TX Statistics");
4940         children = SYSCTL_CHILDREN(tree);
4941         BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
4942             children, txstats.ifHCOutOctets, "Octets");
4943         BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
4944             children, txstats.etherStatsCollisions, "Collisions");
4945         BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
4946             children, txstats.outXonSent, "XonSent");
4947         BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
4948             children, txstats.outXoffSent, "XoffSent");
4949         BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
4950             children, txstats.flowControlDone, "flowControlDone");
4951         BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
4952             children, txstats.dot3StatsInternalMacTransmitErrors,
4953             "InternalMacTransmitErrors");
4954         BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
4955             children, txstats.dot3StatsSingleCollisionFrames,
4956             "SingleCollisionFrames");
4957         BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
4958             children, txstats.dot3StatsMultipleCollisionFrames,
4959             "MultipleCollisionFrames");
4960         BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
4961             children, txstats.dot3StatsDeferredTransmissions,
4962             "DeferredTransmissions");
4963         BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
4964             children, txstats.dot3StatsExcessiveCollisions,
4965             "ExcessiveCollisions");
4966         BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
4967             children, txstats.dot3StatsLateCollisions,
4968             "LateCollisions");
4969         BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
4970             children, txstats.ifHCOutUcastPkts, "UcastPkts");
4971         BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
4972             children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
4973         BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
4974             children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
4975         BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
4976             children, txstats.dot3StatsCarrierSenseErrors,
4977             "CarrierSenseErrors");
4978         BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
4979             children, txstats.ifOutDiscards, "Discards");
4980         BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
4981             children, txstats.ifOutErrors, "Errors");
4982 }
4983
4984 static int
4985 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
4986 {
4987         struct bge_softc *sc;
4988         uint32_t result;
4989         int offset;
4990
4991         sc = (struct bge_softc *)arg1;
4992         offset = arg2;
4993         result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
4994             offsetof(bge_hostaddr, bge_addr_lo));
4995         return (sysctl_handle_int(oidp, &result, 0, req));
4996 }
4997
4998 #ifdef BGE_REGISTER_DEBUG
4999 static int
5000 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
5001 {
5002         struct bge_softc *sc;
5003         uint16_t *sbdata;
5004         int error;
5005         int result;
5006         int i, j;
5007
5008         result = -1;
5009         error = sysctl_handle_int(oidp, &result, 0, req);
5010         if (error || (req->newptr == NULL))
5011                 return (error);
5012
5013         if (result == 1) {
5014                 sc = (struct bge_softc *)arg1;
5015
5016                 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
5017                 printf("Status Block:\n");
5018                 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) {
5019                         printf("%06x:", i);
5020                         for (j = 0; j < 8; j++) {
5021                                 printf(" %04x", sbdata[i]);
5022                                 i += 4;
5023                         }
5024                         printf("\n");
5025                 }
5026
5027                 printf("Registers:\n");
5028                 for (i = 0x800; i < 0xA00; ) {
5029                         printf("%06x:", i);
5030                         for (j = 0; j < 8; j++) {
5031                                 printf(" %08x", CSR_READ_4(sc, i));
5032                                 i += 4;
5033                         }
5034                         printf("\n");
5035                 }
5036
5037                 printf("Hardware Flags:\n");
5038                 if (BGE_IS_5755_PLUS(sc))
5039                         printf(" - 5755 Plus\n");
5040                 if (BGE_IS_575X_PLUS(sc))
5041                         printf(" - 575X Plus\n");
5042                 if (BGE_IS_5705_PLUS(sc))
5043                         printf(" - 5705 Plus\n");
5044                 if (BGE_IS_5714_FAMILY(sc))
5045                         printf(" - 5714 Family\n");
5046                 if (BGE_IS_5700_FAMILY(sc))
5047                         printf(" - 5700 Family\n");
5048                 if (sc->bge_flags & BGE_FLAG_JUMBO)
5049                         printf(" - Supports Jumbo Frames\n");
5050                 if (sc->bge_flags & BGE_FLAG_PCIX)
5051                         printf(" - PCI-X Bus\n");
5052                 if (sc->bge_flags & BGE_FLAG_PCIE)
5053                         printf(" - PCI Express Bus\n");
5054                 if (sc->bge_flags & BGE_FLAG_NO_3LED)
5055                         printf(" - No 3 LEDs\n");
5056                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
5057                         printf(" - RX Alignment Bug\n");
5058         }
5059
5060         return (error);
5061 }
5062
5063 static int
5064 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5065 {
5066         struct bge_softc *sc;
5067         int error;
5068         uint16_t result;
5069         uint32_t val;
5070
5071         result = -1;
5072         error = sysctl_handle_int(oidp, &result, 0, req);
5073         if (error || (req->newptr == NULL))
5074                 return (error);
5075
5076         if (result < 0x8000) {
5077                 sc = (struct bge_softc *)arg1;
5078                 val = CSR_READ_4(sc, result);
5079                 printf("reg 0x%06X = 0x%08X\n", result, val);
5080         }
5081
5082         return (error);
5083 }
5084
5085 static int
5086 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
5087 {
5088         struct bge_softc *sc;
5089         int error;
5090         uint16_t result;
5091         uint32_t val;
5092
5093         result = -1;
5094         error = sysctl_handle_int(oidp, &result, 0, req);
5095         if (error || (req->newptr == NULL))
5096                 return (error);
5097
5098         if (result < 0x8000) {
5099                 sc = (struct bge_softc *)arg1;
5100                 val = bge_readmem_ind(sc, result);
5101                 printf("mem 0x%06X = 0x%08X\n", result, val);
5102         }
5103
5104         return (error);
5105 }
5106 #endif
5107
5108 static int
5109 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
5110 {
5111
5112         if (sc->bge_flags & BGE_FLAG_EADDR)
5113                 return (1);
5114
5115 #ifdef __sparc64__
5116         OF_getetheraddr(sc->bge_dev, ether_addr);
5117         return (0);
5118 #endif
5119         return (1);
5120 }
5121
5122 static int
5123 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
5124 {
5125         uint32_t mac_addr;
5126
5127         mac_addr = bge_readmem_ind(sc, 0x0c14);
5128         if ((mac_addr >> 16) == 0x484b) {
5129                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
5130                 ether_addr[1] = (uint8_t)mac_addr;
5131                 mac_addr = bge_readmem_ind(sc, 0x0c18);
5132                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
5133                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
5134                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
5135                 ether_addr[5] = (uint8_t)mac_addr;
5136                 return (0);
5137         }
5138         return (1);
5139 }
5140
5141 static int
5142 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
5143 {
5144         int mac_offset = BGE_EE_MAC_OFFSET;
5145
5146         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
5147                 mac_offset = BGE_EE_MAC_OFFSET_5906;
5148
5149         return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
5150             ETHER_ADDR_LEN));
5151 }
5152
5153 static int
5154 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
5155 {
5156
5157         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
5158                 return (1);
5159
5160         return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
5161            ETHER_ADDR_LEN));
5162 }
5163
5164 static int
5165 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
5166 {
5167         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
5168                 /* NOTE: Order is critical */
5169                 bge_get_eaddr_fw,
5170                 bge_get_eaddr_mem,
5171                 bge_get_eaddr_nvram,
5172                 bge_get_eaddr_eeprom,
5173                 NULL
5174         };
5175         const bge_eaddr_fcn_t *func;
5176
5177         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
5178                 if ((*func)(sc, eaddr) == 0)
5179                         break;
5180         }
5181         return (*func == NULL ? ENXIO : 0);
5182 }