sys/dev/bge/if_bge.c

   1 /*-
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/cdefs.h>
  35 __FBSDID("$FreeBSD$");
  36
  37 /*
  38  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  39  *
  40  * The Broadcom BCM5700 is based on technology originally developed by
  41  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  42  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  43  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  44  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  45  * frames, highly configurable RX filtering, and 16 RX and TX queues
  46  * (which, along with RX filter rules, can be used for QOS applications).
  47  * Other features, such as TCP segmentation, may be available as part
  48  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  49  * firmware images can be stored in hardware and need not be compiled
  50  * into the driver.
  51  *
  52  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  53  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  54  *
  55  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  56  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  57  * does not support external SSRAM.
  58  *
  59  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  60  * brand name, which is functionally similar but lacks PCI-X support.
  61  *
  62  * Without external SSRAM, you can only have at most 4 TX rings,
  63  * and the use of the mini RX ring is disabled. This seems to imply
  64  * that these features are simply not available on the BCM5701. As a
  65  * result, this driver does not implement any support for the mini RX
  66  * ring.
  67  */
  68
  69 #ifdef HAVE_KERNEL_OPTION_HEADERS
  70 #include "opt_device_polling.h"
  71 #endif
  72
  73 #include <sys/param.h>
  74 #include <sys/endian.h>
  75 #include <sys/systm.h>
  76 #include <sys/sockio.h>
  77 #include <sys/mbuf.h>
  78 #include <sys/malloc.h>
  79 #include <sys/kernel.h>
  80 #include <sys/module.h>
  81 #include <sys/socket.h>
  82 #include <sys/sysctl.h>
  83 #include <sys/taskqueue.h>
  84
  85 #include <net/if.h>
  86 #include <net/if_arp.h>
  87 #include <net/ethernet.h>
  88 #include <net/if_dl.h>
  89 #include <net/if_media.h>
  90
  91 #include <net/bpf.h>
  92
  93 #include <net/if_types.h>
  94 #include <net/if_vlan_var.h>
  95
  96 #include <netinet/in_systm.h>
  97 #include <netinet/in.h>
  98 #include <netinet/ip.h>
  99 #include <netinet/tcp.h>
 100
 101 #include <machine/bus.h>
 102 #include <machine/resource.h>
 103 #include <sys/bus.h>
 104 #include <sys/rman.h>
 105
 106 #include <dev/mii/mii.h>
 107 #include <dev/mii/miivar.h>
 108 #include "miidevs.h"
 109 #include <dev/mii/brgphyreg.h>
 110
 111 #ifdef __sparc64__
 112 #include <dev/ofw/ofw_bus.h>
 113 #include <dev/ofw/openfirm.h>
 114 #include <machine/ofw_machdep.h>
 115 #include <machine/ver.h>
 116 #endif
 117
 118 #include <dev/pci/pcireg.h>
 119 #include <dev/pci/pcivar.h>
 120
 121 #include <dev/bge/if_bgereg.h>
 122
 123 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 124 #define ETHER_MIN_NOPAD         (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
 125
 126 MODULE_DEPEND(bge, pci, 1, 1, 1);
 127 MODULE_DEPEND(bge, ether, 1, 1, 1);
 128 MODULE_DEPEND(bge, miibus, 1, 1, 1);
 129
 130 /* "device miibus" required.  See GENERIC if you get errors here. */
 131 #include "miibus_if.h"
 132
 133 /*
 134  * Various supported device vendors/types and their names. Note: the
 135  * spec seems to indicate that the hardware still has Alteon's vendor
 136  * ID burned into it, though it will always be overriden by the vendor
 137  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 138  */
 139 static const struct bge_type {
 140         uint16_t        bge_vid;
 141         uint16_t        bge_did;
 142 } bge_devs[] = {
 143         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5700 },
 144         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5701 },
 145
 146         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1000 },
 147         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1002 },
 148         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC9100 },
 149
 150         { APPLE_VENDORID,       APPLE_DEVICE_BCM5701 },
 151
 152         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5700 },
 153         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5701 },
 154         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702 },
 155         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702_ALT },
 156         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702X },
 157         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703 },
 158         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703_ALT },
 159         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703X },
 160         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704C },
 161         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S },
 162         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S_ALT },
 163         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705 },
 164         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705F },
 165         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705K },
 166         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M },
 167         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M_ALT },
 168         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714C },
 169         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714S },
 170         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715 },
 171         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715S },
 172         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5720 },
 173         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5721 },
 174         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5722 },
 175         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5723 },
 176         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750 },
 177         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750M },
 178         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751 },
 179         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751F },
 180         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751M },
 181         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752 },
 182         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752M },
 183         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753 },
 184         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753F },
 185         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753M },
 186         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754 },
 187         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754M },
 188         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755 },
 189         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755M },
 190         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5756 },
 191         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761 },
 192         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761E },
 193         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761S },
 194         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761SE },
 195         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5764 },
 196         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780 },
 197         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780S },
 198         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5781 },
 199         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5782 },
 200         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5784 },
 201         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785F },
 202         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785G },
 203         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5786 },
 204         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787 },
 205         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787F },
 206         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787M },
 207         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5788 },
 208         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5789 },
 209         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901 },
 210         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901A2 },
 211         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5903M },
 212         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906 },
 213         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906M },
 214         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57760 },
 215         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57780 },
 216         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57788 },
 217         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57790 },
 218
 219         { SK_VENDORID,          SK_DEVICEID_ALTIMA },
 220
 221         { TC_VENDORID,          TC_DEVICEID_3C996 },
 222
 223         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE4 },
 224         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE5 },
 225         { FJTSU_VENDORID,       FJTSU_DEVICEID_PP250450 },
 226
 227         { 0, 0 }
 228 };
 229
 230 static const struct bge_vendor {
 231         uint16_t        v_id;
 232         const char      *v_name;
 233 } bge_vendors[] = {
 234         { ALTEON_VENDORID,      "Alteon" },
 235         { ALTIMA_VENDORID,      "Altima" },
 236         { APPLE_VENDORID,       "Apple" },
 237         { BCOM_VENDORID,        "Broadcom" },
 238         { SK_VENDORID,          "SysKonnect" },
 239         { TC_VENDORID,          "3Com" },
 240         { FJTSU_VENDORID,       "Fujitsu" },
 241
 242         { 0, NULL }
 243 };
 244
 245 static const struct bge_revision {
 246         uint32_t        br_chipid;
 247         const char      *br_name;
 248 } bge_revisions[] = {
 249         { BGE_CHIPID_BCM5700_A0,        "BCM5700 A0" },
 250         { BGE_CHIPID_BCM5700_A1,        "BCM5700 A1" },
 251         { BGE_CHIPID_BCM5700_B0,        "BCM5700 B0" },
 252         { BGE_CHIPID_BCM5700_B1,        "BCM5700 B1" },
 253         { BGE_CHIPID_BCM5700_B2,        "BCM5700 B2" },
 254         { BGE_CHIPID_BCM5700_B3,        "BCM5700 B3" },
 255         { BGE_CHIPID_BCM5700_ALTIMA,    "BCM5700 Altima" },
 256         { BGE_CHIPID_BCM5700_C0,        "BCM5700 C0" },
 257         { BGE_CHIPID_BCM5701_A0,        "BCM5701 A0" },
 258         { BGE_CHIPID_BCM5701_B0,        "BCM5701 B0" },
 259         { BGE_CHIPID_BCM5701_B2,        "BCM5701 B2" },
 260         { BGE_CHIPID_BCM5701_B5,        "BCM5701 B5" },
 261         { BGE_CHIPID_BCM5703_A0,        "BCM5703 A0" },
 262         { BGE_CHIPID_BCM5703_A1,        "BCM5703 A1" },
 263         { BGE_CHIPID_BCM5703_A2,        "BCM5703 A2" },
 264         { BGE_CHIPID_BCM5703_A3,        "BCM5703 A3" },
 265         { BGE_CHIPID_BCM5703_B0,        "BCM5703 B0" },
 266         { BGE_CHIPID_BCM5704_A0,        "BCM5704 A0" },
 267         { BGE_CHIPID_BCM5704_A1,        "BCM5704 A1" },
 268         { BGE_CHIPID_BCM5704_A2,        "BCM5704 A2" },
 269         { BGE_CHIPID_BCM5704_A3,        "BCM5704 A3" },
 270         { BGE_CHIPID_BCM5704_B0,        "BCM5704 B0" },
 271         { BGE_CHIPID_BCM5705_A0,        "BCM5705 A0" },
 272         { BGE_CHIPID_BCM5705_A1,        "BCM5705 A1" },
 273         { BGE_CHIPID_BCM5705_A2,        "BCM5705 A2" },
 274         { BGE_CHIPID_BCM5705_A3,        "BCM5705 A3" },
 275         { BGE_CHIPID_BCM5750_A0,        "BCM5750 A0" },
 276         { BGE_CHIPID_BCM5750_A1,        "BCM5750 A1" },
 277         { BGE_CHIPID_BCM5750_A3,        "BCM5750 A3" },
 278         { BGE_CHIPID_BCM5750_B0,        "BCM5750 B0" },
 279         { BGE_CHIPID_BCM5750_B1,        "BCM5750 B1" },
 280         { BGE_CHIPID_BCM5750_C0,        "BCM5750 C0" },
 281         { BGE_CHIPID_BCM5750_C1,        "BCM5750 C1" },
 282         { BGE_CHIPID_BCM5750_C2,        "BCM5750 C2" },
 283         { BGE_CHIPID_BCM5714_A0,        "BCM5714 A0" },
 284         { BGE_CHIPID_BCM5752_A0,        "BCM5752 A0" },
 285         { BGE_CHIPID_BCM5752_A1,        "BCM5752 A1" },
 286         { BGE_CHIPID_BCM5752_A2,        "BCM5752 A2" },
 287         { BGE_CHIPID_BCM5714_B0,        "BCM5714 B0" },
 288         { BGE_CHIPID_BCM5714_B3,        "BCM5714 B3" },
 289         { BGE_CHIPID_BCM5715_A0,        "BCM5715 A0" },
 290         { BGE_CHIPID_BCM5715_A1,        "BCM5715 A1" },
 291         { BGE_CHIPID_BCM5715_A3,        "BCM5715 A3" },
 292         { BGE_CHIPID_BCM5755_A0,        "BCM5755 A0" },
 293         { BGE_CHIPID_BCM5755_A1,        "BCM5755 A1" },
 294         { BGE_CHIPID_BCM5755_A2,        "BCM5755 A2" },
 295         { BGE_CHIPID_BCM5722_A0,        "BCM5722 A0" },
 296         { BGE_CHIPID_BCM5761_A0,        "BCM5761 A0" },
 297         { BGE_CHIPID_BCM5761_A1,        "BCM5761 A1" },
 298         { BGE_CHIPID_BCM5784_A0,        "BCM5784 A0" },
 299         { BGE_CHIPID_BCM5784_A1,        "BCM5784 A1" },
 300         /* 5754 and 5787 share the same ASIC ID */
 301         { BGE_CHIPID_BCM5787_A0,        "BCM5754/5787 A0" },
 302         { BGE_CHIPID_BCM5787_A1,        "BCM5754/5787 A1" },
 303         { BGE_CHIPID_BCM5787_A2,        "BCM5754/5787 A2" },
 304         { BGE_CHIPID_BCM5906_A1,        "BCM5906 A1" },
 305         { BGE_CHIPID_BCM5906_A2,        "BCM5906 A2" },
 306         { BGE_CHIPID_BCM57780_A0,       "BCM57780 A0" },
 307         { BGE_CHIPID_BCM57780_A1,       "BCM57780 A1" },
 308
 309         { 0, NULL }
 310 };
 311
 312 /*
 313  * Some defaults for major revisions, so that newer steppings
 314  * that we don't know about have a shot at working.
 315  */
 316 static const struct bge_revision bge_majorrevs[] = {
 317         { BGE_ASICREV_BCM5700,          "unknown BCM5700" },
 318         { BGE_ASICREV_BCM5701,          "unknown BCM5701" },
 319         { BGE_ASICREV_BCM5703,          "unknown BCM5703" },
 320         { BGE_ASICREV_BCM5704,          "unknown BCM5704" },
 321         { BGE_ASICREV_BCM5705,          "unknown BCM5705" },
 322         { BGE_ASICREV_BCM5750,          "unknown BCM5750" },
 323         { BGE_ASICREV_BCM5714_A0,       "unknown BCM5714" },
 324         { BGE_ASICREV_BCM5752,          "unknown BCM5752" },
 325         { BGE_ASICREV_BCM5780,          "unknown BCM5780" },
 326         { BGE_ASICREV_BCM5714,          "unknown BCM5714" },
 327         { BGE_ASICREV_BCM5755,          "unknown BCM5755" },
 328         { BGE_ASICREV_BCM5761,          "unknown BCM5761" },
 329         { BGE_ASICREV_BCM5784,          "unknown BCM5784" },
 330         { BGE_ASICREV_BCM5785,          "unknown BCM5785" },
 331         /* 5754 and 5787 share the same ASIC ID */
 332         { BGE_ASICREV_BCM5787,          "unknown BCM5754/5787" },
 333         { BGE_ASICREV_BCM5906,          "unknown BCM5906" },
 334         { BGE_ASICREV_BCM57780,         "unknown BCM57780" },
 335
 336         { 0, NULL }
 337 };
 338
 339 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 340 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 341 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 342 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 343 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 344 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 345
 346 const struct bge_revision * bge_lookup_rev(uint32_t);
 347 const struct bge_vendor * bge_lookup_vendor(uint16_t);
 348
 349 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 350
 351 static int bge_probe(device_t);
 352 static int bge_attach(device_t);
 353 static int bge_detach(device_t);
 354 static int bge_suspend(device_t);
 355 static int bge_resume(device_t);
 356 static void bge_release_resources(struct bge_softc *);
 357 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 358 static int bge_dma_alloc(device_t);
 359 static void bge_dma_free(struct bge_softc *);
 360
 361 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
 362 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 363 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 364 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 365 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
 366
 367 static void bge_txeof(struct bge_softc *, uint16_t);
 368 static int bge_rxeof(struct bge_softc *, uint16_t, int);
 369
 370 static void bge_asf_driver_up (struct bge_softc *);
 371 static void bge_tick(void *);
 372 static void bge_stats_update(struct bge_softc *);
 373 static void bge_stats_update_regs(struct bge_softc *);
 374 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
 375     uint16_t *);
 376 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 377
 378 static void bge_intr(void *);
 379 static int bge_msi_intr(void *);
 380 static void bge_intr_task(void *, int);
 381 static void bge_start_locked(struct ifnet *);
 382 static void bge_start(struct ifnet *);
 383 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
 384 static void bge_init_locked(struct bge_softc *);
 385 static void bge_init(void *);
 386 static void bge_stop(struct bge_softc *);
 387 static void bge_watchdog(struct bge_softc *);
 388 static int bge_shutdown(device_t);
 389 static int bge_ifmedia_upd_locked(struct ifnet *);
 390 static int bge_ifmedia_upd(struct ifnet *);
 391 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 392
 393 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 394 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 395
 396 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
 397 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
 398
 399 static void bge_setpromisc(struct bge_softc *);
 400 static void bge_setmulti(struct bge_softc *);
 401 static void bge_setvlan(struct bge_softc *);
 402
 403 static int bge_newbuf_std(struct bge_softc *, int);
 404 static int bge_newbuf_jumbo(struct bge_softc *, int);
 405 static int bge_init_rx_ring_std(struct bge_softc *);
 406 static void bge_free_rx_ring_std(struct bge_softc *);
 407 static int bge_init_rx_ring_jumbo(struct bge_softc *);
 408 static void bge_free_rx_ring_jumbo(struct bge_softc *);
 409 static void bge_free_tx_ring(struct bge_softc *);
 410 static int bge_init_tx_ring(struct bge_softc *);
 411
 412 static int bge_chipinit(struct bge_softc *);
 413 static int bge_blockinit(struct bge_softc *);
 414
 415 static int bge_has_eaddr(struct bge_softc *);
 416 static uint32_t bge_readmem_ind(struct bge_softc *, int);
 417 static void bge_writemem_ind(struct bge_softc *, int, int);
 418 static void bge_writembx(struct bge_softc *, int, int);
 419 #ifdef notdef
 420 static uint32_t bge_readreg_ind(struct bge_softc *, int);
 421 #endif
 422 static void bge_writemem_direct(struct bge_softc *, int, int);
 423 static void bge_writereg_ind(struct bge_softc *, int, int);
 424 static void bge_set_max_readrq(struct bge_softc *);
 425
 426 static int bge_miibus_readreg(device_t, int, int);
 427 static int bge_miibus_writereg(device_t, int, int, int);
 428 static void bge_miibus_statchg(device_t);
 429 #ifdef DEVICE_POLLING
 430 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 431 #endif
 432
 433 #define BGE_RESET_START 1
 434 #define BGE_RESET_STOP  2
 435 static void bge_sig_post_reset(struct bge_softc *, int);
 436 static void bge_sig_legacy(struct bge_softc *, int);
 437 static void bge_sig_pre_reset(struct bge_softc *, int);
 438 static int bge_reset(struct bge_softc *);
 439 static void bge_link_upd(struct bge_softc *);
 440
 441 /*
 442  * The BGE_REGISTER_DEBUG option is only for low-level debugging.  It may
 443  * leak information to untrusted users.  It is also known to cause alignment
 444  * traps on certain architectures.
 445  */
 446 #ifdef BGE_REGISTER_DEBUG
 447 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 448 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
 449 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
 450 #endif
 451 static void bge_add_sysctls(struct bge_softc *);
 452 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
 453
 454 static device_method_t bge_methods[] = {
 455         /* Device interface */
 456         DEVMETHOD(device_probe,         bge_probe),
 457         DEVMETHOD(device_attach,        bge_attach),
 458         DEVMETHOD(device_detach,        bge_detach),
 459         DEVMETHOD(device_shutdown,      bge_shutdown),
 460         DEVMETHOD(device_suspend,       bge_suspend),
 461         DEVMETHOD(device_resume,        bge_resume),
 462
 463         /* bus interface */
 464         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 465         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 466
 467         /* MII interface */
 468         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 469         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 470         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 471
 472         { 0, 0 }
 473 };
 474
 475 static driver_t bge_driver = {
 476         "bge",
 477         bge_methods,
 478         sizeof(struct bge_softc)
 479 };
 480
 481 static devclass_t bge_devclass;
 482
 483 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
 484 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 485
 486 static int bge_allow_asf = 1;
 487
 488 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
 489
 490 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
 491 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
 492         "Allow ASF mode if available");
 493
 494 #define SPARC64_BLADE_1500_MODEL        "SUNW,Sun-Blade-1500"
 495 #define SPARC64_BLADE_1500_PATH_BGE     "/pci@1f,700000/network@2"
 496 #define SPARC64_BLADE_2500_MODEL        "SUNW,Sun-Blade-2500"
 497 #define SPARC64_BLADE_2500_PATH_BGE     "/pci@1c,600000/network@3"
 498 #define SPARC64_OFW_SUBVENDOR           "subsystem-vendor-id"
 499
 500 static int
 501 bge_has_eaddr(struct bge_softc *sc)
 502 {
 503 #ifdef __sparc64__
 504         char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
 505         device_t dev;
 506         uint32_t subvendor;
 507
 508         dev = sc->bge_dev;
 509
 510         /*
 511          * The on-board BGEs found in sun4u machines aren't fitted with
 512          * an EEPROM which means that we have to obtain the MAC address
 513          * via OFW and that some tests will always fail.  We distinguish
 514          * such BGEs by the subvendor ID, which also has to be obtained
 515          * from OFW instead of the PCI configuration space as the latter
 516          * indicates Broadcom as the subvendor of the netboot interface.
 517          * For early Blade 1500 and 2500 we even have to check the OFW
 518          * device path as the subvendor ID always defaults to Broadcom
 519          * there.
 520          */
 521         if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
 522             &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
 523             subvendor == SUN_VENDORID)
 524                 return (0);
 525         memset(buf, 0, sizeof(buf));
 526         if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
 527                 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
 528                     strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
 529                         return (0);
 530                 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
 531                     strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
 532                         return (0);
 533         }
 534 #endif
 535         return (1);
 536 }
 537
 538 static uint32_t
 539 bge_readmem_ind(struct bge_softc *sc, int off)
 540 {
 541         device_t dev;
 542         uint32_t val;
 543
 544         dev = sc->bge_dev;
 545
 546         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 547         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 548         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 549         return (val);
 550 }
 551
 552 static void
 553 bge_writemem_ind(struct bge_softc *sc, int off, int val)
 554 {
 555         device_t dev;
 556
 557         dev = sc->bge_dev;
 558
 559         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 560         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 561         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 562 }
 563
 564 /*
 565  * PCI Express only
 566  */
 567 static void
 568 bge_set_max_readrq(struct bge_softc *sc)
 569 {
 570         device_t dev;
 571         uint16_t val;
 572
 573         dev = sc->bge_dev;
 574
 575         val = pci_read_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
 576         if ((val & PCIM_EXP_CTL_MAX_READ_REQUEST) !=
 577             BGE_PCIE_DEVCTL_MAX_READRQ_4096) {
 578                 if (bootverbose)
 579                         device_printf(dev, "adjust device control 0x%04x ",
 580                             val);
 581                 val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST;
 582                 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096;
 583                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL,
 584                     val, 2);
 585                 if (bootverbose)
 586                         printf("-> 0x%04x\n", val);
 587         }
 588 }
 589
 590 #ifdef notdef
 591 static uint32_t
 592 bge_readreg_ind(struct bge_softc *sc, int off)
 593 {
 594         device_t dev;
 595
 596         dev = sc->bge_dev;
 597
 598         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 599         return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 600 }
 601 #endif
 602
 603 static void
 604 bge_writereg_ind(struct bge_softc *sc, int off, int val)
 605 {
 606         device_t dev;
 607
 608         dev = sc->bge_dev;
 609
 610         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 611         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 612 }
 613
 614 static void
 615 bge_writemem_direct(struct bge_softc *sc, int off, int val)
 616 {
 617         CSR_WRITE_4(sc, off, val);
 618 }
 619
 620 static void
 621 bge_writembx(struct bge_softc *sc, int off, int val)
 622 {
 623         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 624                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 625
 626         CSR_WRITE_4(sc, off, val);
 627 }
 628
 629 /*
 630  * Map a single buffer address.
 631  */
 632
 633 static void
 634 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 635 {
 636         struct bge_dmamap_arg *ctx;
 637
 638         if (error)
 639                 return;
 640
 641         ctx = arg;
 642
 643         if (nseg > ctx->bge_maxsegs) {
 644                 ctx->bge_maxsegs = 0;
 645                 return;
 646         }
 647
 648         ctx->bge_busaddr = segs->ds_addr;
 649 }
 650
 651 static uint8_t
 652 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 653 {
 654         uint32_t access, byte = 0;
 655         int i;
 656
 657         /* Lock. */
 658         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 659         for (i = 0; i < 8000; i++) {
 660                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 661                         break;
 662                 DELAY(20);
 663         }
 664         if (i == 8000)
 665                 return (1);
 666
 667         /* Enable access. */
 668         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 669         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 670
 671         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 672         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 673         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 674                 DELAY(10);
 675                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 676                         DELAY(10);
 677                         break;
 678                 }
 679         }
 680
 681         if (i == BGE_TIMEOUT * 10) {
 682                 if_printf(sc->bge_ifp, "nvram read timed out\n");
 683                 return (1);
 684         }
 685
 686         /* Get result. */
 687         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 688
 689         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 690
 691         /* Disable access. */
 692         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 693
 694         /* Unlock. */
 695         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 696         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 697
 698         return (0);
 699 }
 700
 701 /*
 702  * Read a sequence of bytes from NVRAM.
 703  */
 704 static int
 705 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 706 {
 707         int err = 0, i;
 708         uint8_t byte = 0;
 709
 710         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 711                 return (1);
 712
 713         for (i = 0; i < cnt; i++) {
 714                 err = bge_nvram_getbyte(sc, off + i, &byte);
 715                 if (err)
 716                         break;
 717                 *(dest + i) = byte;
 718         }
 719
 720         return (err ? 1 : 0);
 721 }
 722
 723 /*
 724  * Read a byte of data stored in the EEPROM at address 'addr.' The
 725  * BCM570x supports both the traditional bitbang interface and an
 726  * auto access interface for reading the EEPROM. We use the auto
 727  * access method.
 728  */
 729 static uint8_t
 730 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 731 {
 732         int i;
 733         uint32_t byte = 0;
 734
 735         /*
 736          * Enable use of auto EEPROM access so we can avoid
 737          * having to use the bitbang method.
 738          */
 739         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 740
 741         /* Reset the EEPROM, load the clock period. */
 742         CSR_WRITE_4(sc, BGE_EE_ADDR,
 743             BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 744         DELAY(20);
 745
 746         /* Issue the read EEPROM command. */
 747         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 748
 749         /* Wait for completion */
 750         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 751                 DELAY(10);
 752                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 753                         break;
 754         }
 755
 756         if (i == BGE_TIMEOUT * 10) {
 757                 device_printf(sc->bge_dev, "EEPROM read timed out\n");
 758                 return (1);
 759         }
 760
 761         /* Get result. */
 762         byte = CSR_READ_4(sc, BGE_EE_DATA);
 763
 764         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 765
 766         return (0);
 767 }
 768
 769 /*
 770  * Read a sequence of bytes from the EEPROM.
 771  */
 772 static int
 773 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 774 {
 775         int i, error = 0;
 776         uint8_t byte = 0;
 777
 778         for (i = 0; i < cnt; i++) {
 779                 error = bge_eeprom_getbyte(sc, off + i, &byte);
 780                 if (error)
 781                         break;
 782                 *(dest + i) = byte;
 783         }
 784
 785         return (error ? 1 : 0);
 786 }
 787
 788 static int
 789 bge_miibus_readreg(device_t dev, int phy, int reg)
 790 {
 791         struct bge_softc *sc;
 792         uint32_t val, autopoll;
 793         int i;
 794
 795         sc = device_get_softc(dev);
 796
 797         /*
 798          * Broadcom's own driver always assumes the internal
 799          * PHY is at GMII address 1. On some chips, the PHY responds
 800          * to accesses at all addresses, which could cause us to
 801          * bogusly attach the PHY 32 times at probe type. Always
 802          * restricting the lookup to address 1 is simpler than
 803          * trying to figure out which chips revisions should be
 804          * special-cased.
 805          */
 806         if (phy != 1)
 807                 return (0);
 808
 809         /* Reading with autopolling on may trigger PCI errors */
 810         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 811         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 812                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 813                 DELAY(40);
 814         }
 815
 816         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 817             BGE_MIPHY(phy) | BGE_MIREG(reg));
 818
 819         for (i = 0; i < BGE_TIMEOUT; i++) {
 820                 DELAY(10);
 821                 val = CSR_READ_4(sc, BGE_MI_COMM);
 822                 if (!(val & BGE_MICOMM_BUSY))
 823                         break;
 824         }
 825
 826         if (i == BGE_TIMEOUT) {
 827                 device_printf(sc->bge_dev,
 828                     "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
 829                     phy, reg, val);
 830                 val = 0;
 831                 goto done;
 832         }
 833
 834         DELAY(5);
 835         val = CSR_READ_4(sc, BGE_MI_COMM);
 836
 837 done:
 838         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 839                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 840                 DELAY(40);
 841         }
 842
 843         if (val & BGE_MICOMM_READFAIL)
 844                 return (0);
 845
 846         return (val & 0xFFFF);
 847 }
 848
 849 static int
 850 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 851 {
 852         struct bge_softc *sc;
 853         uint32_t autopoll;
 854         int i;
 855
 856         sc = device_get_softc(dev);
 857
 858         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 859             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 860                 return(0);
 861
 862         /* Reading with autopolling on may trigger PCI errors */
 863         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 864         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 865                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 866                 DELAY(40);
 867         }
 868
 869         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 870             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 871
 872         for (i = 0; i < BGE_TIMEOUT; i++) {
 873                 DELAY(10);
 874                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 875                         DELAY(5);
 876                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 877                         break;
 878                 }
 879         }
 880
 881         if (i == BGE_TIMEOUT) {
 882                 device_printf(sc->bge_dev,
 883                     "PHY write timed out (phy %d, reg %d, val %d)\n",
 884                     phy, reg, val);
 885                 return (0);
 886         }
 887
 888         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 889                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 890                 DELAY(40);
 891         }
 892
 893         return (0);
 894 }
 895
 896 static void
 897 bge_miibus_statchg(device_t dev)
 898 {
 899         struct bge_softc *sc;
 900         struct mii_data *mii;
 901         sc = device_get_softc(dev);
 902         mii = device_get_softc(sc->bge_miibus);
 903
 904         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 905         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 906             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
 907                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 908         else
 909                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 910
 911         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
 912                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 913         else
 914                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 915 }
 916
 917 /*
 918  * Intialize a standard receive ring descriptor.
 919  */
 920 static int
 921 bge_newbuf_std(struct bge_softc *sc, int i)
 922 {
 923         struct mbuf *m;
 924         struct bge_rx_bd *r;
 925         bus_dma_segment_t segs[1];
 926         bus_dmamap_t map;
 927         int error, nsegs;
 928
 929         m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
 930         if (m == NULL)
 931                 return (ENOBUFS);
 932         m->m_len = m->m_pkthdr.len = MCLBYTES;
 933         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 934                 m_adj(m, ETHER_ALIGN);
 935
 936         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
 937             sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
 938         if (error != 0) {
 939                 m_freem(m);
 940                 return (error);
 941         }
 942         if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 943                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 944                     sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
 945                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 946                     sc->bge_cdata.bge_rx_std_dmamap[i]);
 947         }
 948         map = sc->bge_cdata.bge_rx_std_dmamap[i];
 949         sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
 950         sc->bge_cdata.bge_rx_std_sparemap = map;
 951         sc->bge_cdata.bge_rx_std_chain[i] = m;
 952         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
 953         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
 954         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
 955         r->bge_flags = BGE_RXBDFLAG_END;
 956         r->bge_len = segs[0].ds_len;
 957         r->bge_idx = i;
 958
 959         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 960             sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
 961
 962         return (0);
 963 }
 964
 965 /*
 966  * Initialize a jumbo receive ring descriptor. This allocates
 967  * a jumbo buffer from the pool managed internally by the driver.
 968  */
 969 static int
 970 bge_newbuf_jumbo(struct bge_softc *sc, int i)
 971 {
 972         bus_dma_segment_t segs[BGE_NSEG_JUMBO];
 973         bus_dmamap_t map;
 974         struct bge_extrx_bd *r;
 975         struct mbuf *m;
 976         int error, nsegs;
 977
 978         MGETHDR(m, M_DONTWAIT, MT_DATA);
 979         if (m == NULL)
 980                 return (ENOBUFS);
 981
 982         m_cljget(m, M_DONTWAIT, MJUM9BYTES);
 983         if (!(m->m_flags & M_EXT)) {
 984                 m_freem(m);
 985                 return (ENOBUFS);
 986         }
 987         m->m_len = m->m_pkthdr.len = MJUM9BYTES;
 988         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 989                 m_adj(m, ETHER_ALIGN);
 990
 991         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
 992             sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
 993         if (error != 0) {
 994                 m_freem(m);
 995                 return (error);
 996         }
 997
 998         if (sc->bge_cdata.bge_rx_jumbo_chain[i] == NULL) {
 999                 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1000                     sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1001                 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1002                     sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1003         }
1004         map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1005         sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1006             sc->bge_cdata.bge_rx_jumbo_sparemap;
1007         sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1008         sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1009         /*
1010          * Fill in the extended RX buffer descriptor.
1011          */
1012         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1013         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1014         r->bge_idx = i;
1015         r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1016         switch (nsegs) {
1017         case 4:
1018                 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1019                 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1020                 r->bge_len3 = segs[3].ds_len;
1021         case 3:
1022                 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1023                 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1024                 r->bge_len2 = segs[2].ds_len;
1025         case 2:
1026                 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1027                 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1028                 r->bge_len1 = segs[1].ds_len;
1029         case 1:
1030                 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1031                 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1032                 r->bge_len0 = segs[0].ds_len;
1033                 break;
1034         default:
1035                 panic("%s: %d segments\n", __func__, nsegs);
1036         }
1037
1038         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1039             sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1040
1041         return (0);
1042 }
1043
1044 /*
1045  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1046  * that's 1MB or memory, which is a lot. For now, we fill only the first
1047  * 256 ring entries and hope that our CPU is fast enough to keep up with
1048  * the NIC.
1049  */
1050 static int
1051 bge_init_rx_ring_std(struct bge_softc *sc)
1052 {
1053         int error, i;
1054
1055         bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1056         sc->bge_std = 0;
1057         for (i = 0; i < BGE_SSLOTS; i++) {
1058                 if ((error = bge_newbuf_std(sc, i)) != 0)
1059                         return (error);
1060                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1061         };
1062
1063         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1064             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1065
1066         sc->bge_std = i - 1;
1067         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1068
1069         return (0);
1070 }
1071
1072 static void
1073 bge_free_rx_ring_std(struct bge_softc *sc)
1074 {
1075         int i;
1076
1077         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1078                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1079                         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1080                             sc->bge_cdata.bge_rx_std_dmamap[i],
1081                             BUS_DMASYNC_POSTREAD);
1082                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1083                             sc->bge_cdata.bge_rx_std_dmamap[i]);
1084                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1085                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1086                 }
1087                 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1088                     sizeof(struct bge_rx_bd));
1089         }
1090 }
1091
1092 static int
1093 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1094 {
1095         struct bge_rcb *rcb;
1096         int error, i;
1097
1098         bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1099         sc->bge_jumbo = 0;
1100         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1101                 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1102                         return (error);
1103                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1104         };
1105
1106         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1107             sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1108
1109         sc->bge_jumbo = i - 1;
1110
1111         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1112         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1113                                     BGE_RCB_FLAG_USE_EXT_RX_BD);
1114         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1115
1116         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1117
1118         return (0);
1119 }
1120
1121 static void
1122 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1123 {
1124         int i;
1125
1126         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1127                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1128                         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1129                             sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1130                             BUS_DMASYNC_POSTREAD);
1131                         bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1132                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1133                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1134                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1135                 }
1136                 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1137                     sizeof(struct bge_extrx_bd));
1138         }
1139 }
1140
1141 static void
1142 bge_free_tx_ring(struct bge_softc *sc)
1143 {
1144         int i;
1145
1146         if (sc->bge_ldata.bge_tx_ring == NULL)
1147                 return;
1148
1149         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1150                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1151                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1152                             sc->bge_cdata.bge_tx_dmamap[i],
1153                             BUS_DMASYNC_POSTWRITE);
1154                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1155                             sc->bge_cdata.bge_tx_dmamap[i]);
1156                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1157                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1158                 }
1159                 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1160                     sizeof(struct bge_tx_bd));
1161         }
1162 }
1163
1164 static int
1165 bge_init_tx_ring(struct bge_softc *sc)
1166 {
1167         sc->bge_txcnt = 0;
1168         sc->bge_tx_saved_considx = 0;
1169
1170         bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1171         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1172             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1173
1174         /* Initialize transmit producer index for host-memory send ring. */
1175         sc->bge_tx_prodidx = 0;
1176         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1177
1178         /* 5700 b2 errata */
1179         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1180                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1181
1182         /* NIC-memory send ring not used; initialize to zero. */
1183         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1184         /* 5700 b2 errata */
1185         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1186                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1187
1188         return (0);
1189 }
1190
1191 static void
1192 bge_setpromisc(struct bge_softc *sc)
1193 {
1194         struct ifnet *ifp;
1195
1196         BGE_LOCK_ASSERT(sc);
1197
1198         ifp = sc->bge_ifp;
1199
1200         /* Enable or disable promiscuous mode as needed. */
1201         if (ifp->if_flags & IFF_PROMISC)
1202                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1203         else
1204                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1205 }
1206
1207 static void
1208 bge_setmulti(struct bge_softc *sc)
1209 {
1210         struct ifnet *ifp;
1211         struct ifmultiaddr *ifma;
1212         uint32_t hashes[4] = { 0, 0, 0, 0 };
1213         int h, i;
1214
1215         BGE_LOCK_ASSERT(sc);
1216
1217         ifp = sc->bge_ifp;
1218
1219         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1220                 for (i = 0; i < 4; i++)
1221                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1222                 return;
1223         }
1224
1225         /* First, zot all the existing filters. */
1226         for (i = 0; i < 4; i++)
1227                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1228
1229         /* Now program new ones. */
1230         if_maddr_rlock(ifp);
1231         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1232                 if (ifma->ifma_addr->sa_family != AF_LINK)
1233                         continue;
1234                 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1235                     ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1236                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1237         }
1238         if_maddr_runlock(ifp);
1239
1240         for (i = 0; i < 4; i++)
1241                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1242 }
1243
1244 static void
1245 bge_setvlan(struct bge_softc *sc)
1246 {
1247         struct ifnet *ifp;
1248
1249         BGE_LOCK_ASSERT(sc);
1250
1251         ifp = sc->bge_ifp;
1252
1253         /* Enable or disable VLAN tag stripping as needed. */
1254         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1255                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1256         else
1257                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1258 }
1259
1260 static void
1261 bge_sig_pre_reset(sc, type)
1262         struct bge_softc *sc;
1263         int type;
1264 {
1265         /*
1266          * Some chips don't like this so only do this if ASF is enabled
1267          */
1268         if (sc->bge_asf_mode)
1269                 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1270
1271         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1272                 switch (type) {
1273                 case BGE_RESET_START:
1274                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1275                         break;
1276                 case BGE_RESET_STOP:
1277                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1278                         break;
1279                 }
1280         }
1281 }
1282
1283 static void
1284 bge_sig_post_reset(sc, type)
1285         struct bge_softc *sc;
1286         int type;
1287 {
1288         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1289                 switch (type) {
1290                 case BGE_RESET_START:
1291                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001);
1292                         /* START DONE */
1293                         break;
1294                 case BGE_RESET_STOP:
1295                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002);
1296                         break;
1297                 }
1298         }
1299 }
1300
1301 static void
1302 bge_sig_legacy(sc, type)
1303         struct bge_softc *sc;
1304         int type;
1305 {
1306         if (sc->bge_asf_mode) {
1307                 switch (type) {
1308                 case BGE_RESET_START:
1309                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1310                         break;
1311                 case BGE_RESET_STOP:
1312                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1313                         break;
1314                 }
1315         }
1316 }
1317
1318 void bge_stop_fw(struct bge_softc *);
1319 void
1320 bge_stop_fw(sc)
1321         struct bge_softc *sc;
1322 {
1323         int i;
1324
1325         if (sc->bge_asf_mode) {
1326                 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE);
1327                 CSR_WRITE_4(sc, BGE_CPU_EVENT,
1328                     CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
1329
1330                 for (i = 0; i < 100; i++ ) {
1331                         if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14)))
1332                                 break;
1333                         DELAY(10);
1334                 }
1335         }
1336 }
1337
1338 /*
1339  * Do endian, PCI and DMA initialization.
1340  */
1341 static int
1342 bge_chipinit(struct bge_softc *sc)
1343 {
1344         uint32_t dma_rw_ctl;
1345         int i;
1346
1347         /* Set endianness before we access any non-PCI registers. */
1348         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1349
1350         /* Clear the MAC control register */
1351         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1352
1353         /*
1354          * Clear the MAC statistics block in the NIC's
1355          * internal memory.
1356          */
1357         for (i = BGE_STATS_BLOCK;
1358             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1359                 BGE_MEMWIN_WRITE(sc, i, 0);
1360
1361         for (i = BGE_STATUS_BLOCK;
1362             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1363                 BGE_MEMWIN_WRITE(sc, i, 0);
1364
1365         /*
1366          * Set up the PCI DMA control register.
1367          */
1368         dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1369             BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1370         if (sc->bge_flags & BGE_FLAG_PCIE) {
1371                 /* Read watermark not used, 128 bytes for write. */
1372                 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1373         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1374                 if (BGE_IS_5714_FAMILY(sc)) {
1375                         /* 256 bytes for read and write. */
1376                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1377                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1378                         dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1379                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1380                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1381                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1382                         /* 1536 bytes for read, 384 bytes for write. */
1383                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1384                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1385                 } else {
1386                         /* 384 bytes for read and write. */
1387                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1388                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1389                             0x0F;
1390                 }
1391                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1392                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1393                         uint32_t tmp;
1394
1395                         /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1396                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1397                         if (tmp == 6 || tmp == 7)
1398                                 dma_rw_ctl |=
1399                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1400
1401                         /* Set PCI-X DMA write workaround. */
1402                         dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1403                 }
1404         } else {
1405                 /* Conventional PCI bus: 256 bytes for read and write. */
1406                 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1407                     BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1408
1409                 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1410                     sc->bge_asicrev != BGE_ASICREV_BCM5750)
1411                         dma_rw_ctl |= 0x0F;
1412         }
1413         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1414             sc->bge_asicrev == BGE_ASICREV_BCM5701)
1415                 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1416                     BGE_PCIDMARWCTL_ASRT_ALL_BE;
1417         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1418             sc->bge_asicrev == BGE_ASICREV_BCM5704)
1419                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1420         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1421
1422         /*
1423          * Set up general mode register.
1424          */
1425         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
1426             BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1427             BGE_MODECTL_TX_NO_PHDR_CSUM);
1428
1429         /*
1430          * BCM5701 B5 have a bug causing data corruption when using
1431          * 64-bit DMA reads, which can be terminated early and then
1432          * completed later as 32-bit accesses, in combination with
1433          * certain bridges.
1434          */
1435         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1436             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1437                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1438
1439         /*
1440          * Tell the firmware the driver is running
1441          */
1442         if (sc->bge_asf_mode & ASF_STACKUP)
1443                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
1444
1445         /*
1446          * Disable memory write invalidate.  Apparently it is not supported
1447          * properly by these devices.  Also ensure that INTx isn't disabled,
1448          * as these chips need it even when using MSI.
1449          */
1450         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1451             PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
1452
1453         /* Set the timer prescaler (always 66Mhz) */
1454         CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1455
1456         /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1457         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1458                 DELAY(40);      /* XXX */
1459
1460                 /* Put PHY into ready state */
1461                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1462                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1463                 DELAY(40);
1464         }
1465
1466         return (0);
1467 }
1468
1469 static int
1470 bge_blockinit(struct bge_softc *sc)
1471 {
1472         struct bge_rcb *rcb;
1473         bus_size_t vrcb;
1474         bge_hostaddr taddr;
1475         uint32_t val;
1476         int i;
1477
1478         /*
1479          * Initialize the memory window pointer register so that
1480          * we can access the first 32K of internal NIC RAM. This will
1481          * allow us to set up the TX send ring RCBs and the RX return
1482          * ring RCBs, plus other things which live in NIC memory.
1483          */
1484         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1485
1486         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1487
1488         if (!(BGE_IS_5705_PLUS(sc))) {
1489                 /* Configure mbuf memory pool */
1490                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1491                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1492                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1493                 else
1494                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1495
1496                 /* Configure DMA resource pool */
1497                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1498                     BGE_DMA_DESCRIPTORS);
1499                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1500         }
1501
1502         /* Configure mbuf pool watermarks */
1503         if (!BGE_IS_5705_PLUS(sc)) {
1504                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1505                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1506                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1507         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1508                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1509                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1510                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1511         } else {
1512                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1513                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1514                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1515         }
1516
1517         /* Configure DMA resource watermarks */
1518         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1519         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1520
1521         /* Enable buffer manager */
1522         if (!(BGE_IS_5705_PLUS(sc))) {
1523                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1524                     BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN);
1525
1526                 /* Poll for buffer manager start indication */
1527                 for (i = 0; i < BGE_TIMEOUT; i++) {
1528                         DELAY(10);
1529                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1530                                 break;
1531                 }
1532
1533                 if (i == BGE_TIMEOUT) {
1534                         device_printf(sc->bge_dev,
1535                             "buffer manager failed to start\n");
1536                         return (ENXIO);
1537                 }
1538         }
1539
1540         /* Enable flow-through queues */
1541         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1542         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1543
1544         /* Wait until queue initialization is complete */
1545         for (i = 0; i < BGE_TIMEOUT; i++) {
1546                 DELAY(10);
1547                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1548                         break;
1549         }
1550
1551         if (i == BGE_TIMEOUT) {
1552                 device_printf(sc->bge_dev, "flow-through queue init failed\n");
1553                 return (ENXIO);
1554         }
1555
1556         /* Initialize the standard RX ring control block */
1557         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1558         rcb->bge_hostaddr.bge_addr_lo =
1559             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1560         rcb->bge_hostaddr.bge_addr_hi =
1561             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1562         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1563             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1564         if (BGE_IS_5705_PLUS(sc))
1565                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1566         else
1567                 rcb->bge_maxlen_flags =
1568                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1569         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1570         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1571         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1572
1573         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1574         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1575
1576         /*
1577          * Initialize the jumbo RX ring control block
1578          * We set the 'ring disabled' bit in the flags
1579          * field until we're actually ready to start
1580          * using this ring (i.e. once we set the MTU
1581          * high enough to require it).
1582          */
1583         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1584                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1585
1586                 rcb->bge_hostaddr.bge_addr_lo =
1587                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1588                 rcb->bge_hostaddr.bge_addr_hi =
1589                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1590                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1591                     sc->bge_cdata.bge_rx_jumbo_ring_map,
1592                     BUS_DMASYNC_PREREAD);
1593                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1594                     BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1595                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1596                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1597                     rcb->bge_hostaddr.bge_addr_hi);
1598                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1599                     rcb->bge_hostaddr.bge_addr_lo);
1600
1601                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1602                     rcb->bge_maxlen_flags);
1603                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1604
1605                 /* Set up dummy disabled mini ring RCB */
1606                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1607                 rcb->bge_maxlen_flags =
1608                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1609                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1610                     rcb->bge_maxlen_flags);
1611         }
1612
1613         /*
1614          * Set the BD ring replentish thresholds. The recommended
1615          * values are 1/8th the number of descriptors allocated to
1616          * each ring.
1617          * XXX The 5754 requires a lower threshold, so it might be a
1618          * requirement of all 575x family chips.  The Linux driver sets
1619          * the lower threshold for all 5705 family chips as well, but there
1620          * are reports that it might not need to be so strict.
1621          *
1622          * XXX Linux does some extra fiddling here for the 5906 parts as
1623          * well.
1624          */
1625         if (BGE_IS_5705_PLUS(sc))
1626                 val = 8;
1627         else
1628                 val = BGE_STD_RX_RING_CNT / 8;
1629         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1630         if (BGE_IS_JUMBO_CAPABLE(sc))
1631                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1632                     BGE_JUMBO_RX_RING_CNT/8);
1633
1634         /*
1635          * Disable all unused send rings by setting the 'ring disabled'
1636          * bit in the flags field of all the TX send ring control blocks.
1637          * These are located in NIC memory.
1638          */
1639         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1640         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1641                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1642                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1643                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1644                 vrcb += sizeof(struct bge_rcb);
1645         }
1646
1647         /* Configure TX RCB 0 (we use only the first ring) */
1648         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1649         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1650         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1651         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1652         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1653             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1654         if (!(BGE_IS_5705_PLUS(sc)))
1655                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1656                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1657
1658         /* Disable all unused RX return rings */
1659         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1660         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1661                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1662                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1663                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1664                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1665                     BGE_RCB_FLAG_RING_DISABLED));
1666                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1667                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1668                     (i * (sizeof(uint64_t))), 0);
1669                 vrcb += sizeof(struct bge_rcb);
1670         }
1671
1672         /* Initialize RX ring indexes */
1673         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1674         if (BGE_IS_JUMBO_CAPABLE(sc))
1675                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1676         if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1677                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1678
1679         /*
1680          * Set up RX return ring 0
1681          * Note that the NIC address for RX return rings is 0x00000000.
1682          * The return rings live entirely within the host, so the
1683          * nicaddr field in the RCB isn't used.
1684          */
1685         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1686         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1687         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1688         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1689         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1690         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1691             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1692
1693         /* Set random backoff seed for TX */
1694         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1695             IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1696             IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1697             IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1698             BGE_TX_BACKOFF_SEED_MASK);
1699
1700         /* Set inter-packet gap */
1701         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1702
1703         /*
1704          * Specify which ring to use for packets that don't match
1705          * any RX rules.
1706          */
1707         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1708
1709         /*
1710          * Configure number of RX lists. One interrupt distribution
1711          * list, sixteen active lists, one bad frames class.
1712          */
1713         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1714
1715         /* Inialize RX list placement stats mask. */
1716         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1717         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1718
1719         /* Disable host coalescing until we get it set up */
1720         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1721
1722         /* Poll to make sure it's shut down. */
1723         for (i = 0; i < BGE_TIMEOUT; i++) {
1724                 DELAY(10);
1725                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1726                         break;
1727         }
1728
1729         if (i == BGE_TIMEOUT) {
1730                 device_printf(sc->bge_dev,
1731                     "host coalescing engine failed to idle\n");
1732                 return (ENXIO);
1733         }
1734
1735         /* Set up host coalescing defaults */
1736         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1737         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1738         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1739         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1740         if (!(BGE_IS_5705_PLUS(sc))) {
1741                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1742                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1743         }
1744         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1745         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1746
1747         /* Set up address of statistics block */
1748         if (!(BGE_IS_5705_PLUS(sc))) {
1749                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1750                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1751                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1752                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1753                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1754                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1755                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1756         }
1757
1758         /* Set up address of status block */
1759         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1760             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1761         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1762             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1763         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1764         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1765
1766         /* Set up status block size. */
1767         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1768             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
1769                 val = BGE_STATBLKSZ_FULL;
1770         else
1771                 val = BGE_STATBLKSZ_32BYTE;
1772
1773         /* Turn on host coalescing state machine */
1774         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1775
1776         /* Turn on RX BD completion state machine and enable attentions */
1777         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1778             BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
1779
1780         /* Turn on RX list placement state machine */
1781         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1782
1783         /* Turn on RX list selector state machine. */
1784         if (!(BGE_IS_5705_PLUS(sc)))
1785                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1786
1787         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1788             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1789             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1790             BGE_MACMODE_FRMHDR_DMA_ENB;
1791
1792         if (sc->bge_flags & BGE_FLAG_TBI)
1793                 val |= BGE_PORTMODE_TBI;
1794         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1795                 val |= BGE_PORTMODE_GMII;
1796         else
1797                 val |= BGE_PORTMODE_MII;
1798
1799         /* Turn on DMA, clear stats */
1800         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1801
1802         /* Set misc. local control, enable interrupts on attentions */
1803         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1804
1805 #ifdef notdef
1806         /* Assert GPIO pins for PHY reset */
1807         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
1808             BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
1809         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
1810             BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
1811 #endif
1812
1813         /* Turn on DMA completion state machine */
1814         if (!(BGE_IS_5705_PLUS(sc)))
1815                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1816
1817         val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
1818
1819         /* Enable host coalescing bug fix. */
1820         if (BGE_IS_5755_PLUS(sc))
1821                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1822
1823         /* Turn on write DMA state machine */
1824         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1825         DELAY(40);
1826
1827         /* Turn on read DMA state machine */
1828         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1829         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1830             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1831             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1832                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1833                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1834                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1835         if (sc->bge_flags & BGE_FLAG_PCIE)
1836                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1837         if (sc->bge_flags & BGE_FLAG_TSO)
1838                 val |= BGE_RDMAMODE_TSO4_ENABLE;
1839         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1840         DELAY(40);
1841
1842         /* Turn on RX data completion state machine */
1843         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1844
1845         /* Turn on RX BD initiator state machine */
1846         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1847
1848         /* Turn on RX data and RX BD initiator state machine */
1849         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1850
1851         /* Turn on Mbuf cluster free state machine */
1852         if (!(BGE_IS_5705_PLUS(sc)))
1853                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1854
1855         /* Turn on send BD completion state machine */
1856         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1857
1858         /* Turn on send data completion state machine */
1859         val = BGE_SDCMODE_ENABLE;
1860         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1861                 val |= BGE_SDCMODE_CDELAY;
1862         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1863
1864         /* Turn on send data initiator state machine */
1865         if (sc->bge_flags & BGE_FLAG_TSO)
1866                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08);
1867         else
1868                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1869
1870         /* Turn on send BD initiator state machine */
1871         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1872
1873         /* Turn on send BD selector state machine */
1874         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1875
1876         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1877         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1878             BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
1879
1880         /* ack/clear link change events */
1881         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1882             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1883             BGE_MACSTAT_LINK_CHANGED);
1884         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1885
1886         /* Enable PHY auto polling (for MII/GMII only) */
1887         if (sc->bge_flags & BGE_FLAG_TBI) {
1888                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1889         } else {
1890                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16));
1891                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1892                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
1893                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1894                             BGE_EVTENB_MI_INTERRUPT);
1895         }
1896
1897         /*
1898          * Clear any pending link state attention.
1899          * Otherwise some link state change events may be lost until attention
1900          * is cleared by bge_intr() -> bge_link_upd() sequence.
1901          * It's not necessary on newer BCM chips - perhaps enabling link
1902          * state change attentions implies clearing pending attention.
1903          */
1904         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1905             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1906             BGE_MACSTAT_LINK_CHANGED);
1907
1908         /* Enable link state change attentions. */
1909         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1910
1911         return (0);
1912 }
1913
1914 const struct bge_revision *
1915 bge_lookup_rev(uint32_t chipid)
1916 {
1917         const struct bge_revision *br;
1918
1919         for (br = bge_revisions; br->br_name != NULL; br++) {
1920                 if (br->br_chipid == chipid)
1921                         return (br);
1922         }
1923
1924         for (br = bge_majorrevs; br->br_name != NULL; br++) {
1925                 if (br->br_chipid == BGE_ASICREV(chipid))
1926                         return (br);
1927         }
1928
1929         return (NULL);
1930 }
1931
1932 const struct bge_vendor *
1933 bge_lookup_vendor(uint16_t vid)
1934 {
1935         const struct bge_vendor *v;
1936
1937         for (v = bge_vendors; v->v_name != NULL; v++)
1938                 if (v->v_id == vid)
1939                         return (v);
1940
1941         panic("%s: unknown vendor %d", __func__, vid);
1942         return (NULL);
1943 }
1944
1945 /*
1946  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1947  * against our list and return its name if we find a match.
1948  *
1949  * Note that since the Broadcom controller contains VPD support, we
1950  * try to get the device name string from the controller itself instead
1951  * of the compiled-in string. It guarantees we'll always announce the
1952  * right product name. We fall back to the compiled-in string when
1953  * VPD is unavailable or corrupt.
1954  */
1955 static int
1956 bge_probe(device_t dev)
1957 {
1958         const struct bge_type *t = bge_devs;
1959         struct bge_softc *sc = device_get_softc(dev);
1960         uint16_t vid, did;
1961
1962         sc->bge_dev = dev;
1963         vid = pci_get_vendor(dev);
1964         did = pci_get_device(dev);
1965         while(t->bge_vid != 0) {
1966                 if ((vid == t->bge_vid) && (did == t->bge_did)) {
1967                         char model[64], buf[96];
1968                         const struct bge_revision *br;
1969                         const struct bge_vendor *v;
1970                         uint32_t id;
1971
1972                         id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1973                             BGE_PCIMISCCTL_ASICREV_SHIFT;
1974                         if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG)
1975                                 id = pci_read_config(dev,
1976                                     BGE_PCI_PRODID_ASICREV, 4);
1977                         br = bge_lookup_rev(id);
1978                         v = bge_lookup_vendor(vid);
1979                         {
1980 #if __FreeBSD_version > 700024
1981                                 const char *pname;
1982
1983                                 if (bge_has_eaddr(sc) &&
1984                                     pci_get_vpd_ident(dev, &pname) == 0)
1985                                         snprintf(model, 64, "%s", pname);
1986                                 else
1987 #endif
1988                                         snprintf(model, 64, "%s %s",
1989                                             v->v_name,
1990                                             br != NULL ? br->br_name :
1991                                             "NetXtreme Ethernet Controller");
1992                         }
1993                         snprintf(buf, 96, "%s, %sASIC rev. %#08x", model,
1994                             br != NULL ? "" : "unknown ", id);
1995                         device_set_desc_copy(dev, buf);
1996                         return (0);
1997                 }
1998                 t++;
1999         }
2000
2001         return (ENXIO);
2002 }
2003
2004 static void
2005 bge_dma_free(struct bge_softc *sc)
2006 {
2007         int i;
2008
2009         /* Destroy DMA maps for RX buffers. */
2010         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2011                 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2012                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2013                             sc->bge_cdata.bge_rx_std_dmamap[i]);
2014         }
2015         if (sc->bge_cdata.bge_rx_std_sparemap)
2016                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2017                     sc->bge_cdata.bge_rx_std_sparemap);
2018
2019         /* Destroy DMA maps for jumbo RX buffers. */
2020         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2021                 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2022                         bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2023                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2024         }
2025         if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2026                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2027                     sc->bge_cdata.bge_rx_jumbo_sparemap);
2028
2029         /* Destroy DMA maps for TX buffers. */
2030         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2031                 if (sc->bge_cdata.bge_tx_dmamap[i])
2032                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2033                             sc->bge_cdata.bge_tx_dmamap[i]);
2034         }
2035
2036         if (sc->bge_cdata.bge_rx_mtag)
2037                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2038         if (sc->bge_cdata.bge_tx_mtag)
2039                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2040
2041
2042         /* Destroy standard RX ring. */
2043         if (sc->bge_cdata.bge_rx_std_ring_map)
2044                 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2045                     sc->bge_cdata.bge_rx_std_ring_map);
2046         if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
2047                 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2048                     sc->bge_ldata.bge_rx_std_ring,
2049                     sc->bge_cdata.bge_rx_std_ring_map);
2050
2051         if (sc->bge_cdata.bge_rx_std_ring_tag)
2052                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2053
2054         /* Destroy jumbo RX ring. */
2055         if (sc->bge_cdata.bge_rx_jumbo_ring_map)
2056                 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2057                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2058
2059         if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
2060             sc->bge_ldata.bge_rx_jumbo_ring)
2061                 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2062                     sc->bge_ldata.bge_rx_jumbo_ring,
2063                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2064
2065         if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2066                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2067
2068         /* Destroy RX return ring. */
2069         if (sc->bge_cdata.bge_rx_return_ring_map)
2070                 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2071                     sc->bge_cdata.bge_rx_return_ring_map);
2072
2073         if (sc->bge_cdata.bge_rx_return_ring_map &&
2074             sc->bge_ldata.bge_rx_return_ring)
2075                 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2076                     sc->bge_ldata.bge_rx_return_ring,
2077                     sc->bge_cdata.bge_rx_return_ring_map);
2078
2079         if (sc->bge_cdata.bge_rx_return_ring_tag)
2080                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2081
2082         /* Destroy TX ring. */
2083         if (sc->bge_cdata.bge_tx_ring_map)
2084                 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2085                     sc->bge_cdata.bge_tx_ring_map);
2086
2087         if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
2088                 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2089                     sc->bge_ldata.bge_tx_ring,
2090                     sc->bge_cdata.bge_tx_ring_map);
2091
2092         if (sc->bge_cdata.bge_tx_ring_tag)
2093                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2094
2095         /* Destroy status block. */
2096         if (sc->bge_cdata.bge_status_map)
2097                 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2098                     sc->bge_cdata.bge_status_map);
2099
2100         if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
2101                 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2102                     sc->bge_ldata.bge_status_block,
2103                     sc->bge_cdata.bge_status_map);
2104
2105         if (sc->bge_cdata.bge_status_tag)
2106                 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2107
2108         /* Destroy statistics block. */
2109         if (sc->bge_cdata.bge_stats_map)
2110                 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2111                     sc->bge_cdata.bge_stats_map);
2112
2113         if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2114                 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2115                     sc->bge_ldata.bge_stats,
2116                     sc->bge_cdata.bge_stats_map);
2117
2118         if (sc->bge_cdata.bge_stats_tag)
2119                 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2120
2121         /* Destroy the parent tag. */
2122         if (sc->bge_cdata.bge_parent_tag)
2123                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2124 }
2125
2126 static int
2127 bge_dma_alloc(device_t dev)
2128 {
2129         struct bge_dmamap_arg ctx;
2130         struct bge_softc *sc;
2131         bus_addr_t lowaddr;
2132         bus_size_t sbsz, txsegsz, txmaxsegsz;
2133         int i, error;
2134
2135         sc = device_get_softc(dev);
2136
2137         lowaddr = BUS_SPACE_MAXADDR;
2138         if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2139                 lowaddr = BGE_DMA_MAXADDR;
2140         if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0)
2141                 lowaddr = BUS_SPACE_MAXADDR_32BIT;
2142         /*
2143          * Allocate the parent bus DMA tag appropriate for PCI.
2144          */
2145         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2146             1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2147             NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2148             0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2149
2150         if (error != 0) {
2151                 device_printf(sc->bge_dev,
2152                     "could not allocate parent dma tag\n");
2153                 return (ENOMEM);
2154         }
2155
2156         /*
2157          * Create tag for Tx mbufs.
2158          */
2159         if (sc->bge_flags & BGE_FLAG_TSO) {
2160                 txsegsz = BGE_TSOSEG_SZ;
2161                 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
2162         } else {
2163                 txsegsz = MCLBYTES;
2164                 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
2165         }
2166         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1,
2167             0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2168             txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
2169             &sc->bge_cdata.bge_tx_mtag);
2170
2171         if (error) {
2172                 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
2173                 return (ENOMEM);
2174         }
2175
2176         /*
2177          * Create tag for Rx mbufs.
2178          */
2179         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
2180             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
2181             MCLBYTES, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
2182
2183         if (error) {
2184                 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
2185                 return (ENOMEM);
2186         }
2187
2188         /* Create DMA maps for RX buffers. */
2189         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2190             &sc->bge_cdata.bge_rx_std_sparemap);
2191         if (error) {
2192                 device_printf(sc->bge_dev,
2193                     "can't create spare DMA map for RX\n");
2194                 return (ENOMEM);
2195         }
2196         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2197                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2198                             &sc->bge_cdata.bge_rx_std_dmamap[i]);
2199                 if (error) {
2200                         device_printf(sc->bge_dev,
2201                             "can't create DMA map for RX\n");
2202                         return (ENOMEM);
2203                 }
2204         }
2205
2206         /* Create DMA maps for TX buffers. */
2207         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2208                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
2209                             &sc->bge_cdata.bge_tx_dmamap[i]);
2210                 if (error) {
2211                         device_printf(sc->bge_dev,
2212                             "can't create DMA map for TX\n");
2213                         return (ENOMEM);
2214                 }
2215         }
2216
2217         /* Create tag for standard RX ring. */
2218         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2219             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2220             NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0,
2221             NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag);
2222
2223         if (error) {
2224                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2225                 return (ENOMEM);
2226         }
2227
2228         /* Allocate DMA'able memory for standard RX ring. */
2229         error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag,
2230             (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT,
2231             &sc->bge_cdata.bge_rx_std_ring_map);
2232         if (error)
2233                 return (ENOMEM);
2234
2235         bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
2236
2237         /* Load the address of the standard RX ring. */
2238         ctx.bge_maxsegs = 1;
2239         ctx.sc = sc;
2240
2241         error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag,
2242             sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring,
2243             BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2244
2245         if (error)
2246                 return (ENOMEM);
2247
2248         sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr;
2249
2250         /* Create tags for jumbo mbufs. */
2251         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2252                 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2253                     1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2254                     NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
2255                     0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
2256                 if (error) {
2257                         device_printf(sc->bge_dev,
2258                             "could not allocate jumbo dma tag\n");
2259                         return (ENOMEM);
2260                 }
2261
2262                 /* Create tag for jumbo RX ring. */
2263                 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2264                     PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2265                     NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0,
2266                     NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag);
2267
2268                 if (error) {
2269                         device_printf(sc->bge_dev,
2270                             "could not allocate jumbo ring dma tag\n");
2271                         return (ENOMEM);
2272                 }
2273
2274                 /* Allocate DMA'able memory for jumbo RX ring. */
2275                 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2276                     (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
2277                     BUS_DMA_NOWAIT | BUS_DMA_ZERO,
2278                     &sc->bge_cdata.bge_rx_jumbo_ring_map);
2279                 if (error)
2280                         return (ENOMEM);
2281
2282                 /* Load the address of the jumbo RX ring. */
2283                 ctx.bge_maxsegs = 1;
2284                 ctx.sc = sc;
2285
2286                 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2287                     sc->bge_cdata.bge_rx_jumbo_ring_map,
2288                     sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ,
2289                     bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2290
2291                 if (error)
2292                         return (ENOMEM);
2293
2294                 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr;
2295
2296                 /* Create DMA maps for jumbo RX buffers. */
2297                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2298                     0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
2299                 if (error) {
2300                         device_printf(sc->bge_dev,
2301                             "can't create spare DMA map for jumbo RX\n");
2302                         return (ENOMEM);
2303                 }
2304                 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2305                         error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2306                                     0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2307                         if (error) {
2308                                 device_printf(sc->bge_dev,
2309                                     "can't create DMA map for jumbo RX\n");
2310                                 return (ENOMEM);
2311                         }
2312                 }
2313
2314         }
2315
2316         /* Create tag for RX return ring. */
2317         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2318             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2319             NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0,
2320             NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag);
2321
2322         if (error) {
2323                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2324                 return (ENOMEM);
2325         }
2326
2327         /* Allocate DMA'able memory for RX return ring. */
2328         error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag,
2329             (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT,
2330             &sc->bge_cdata.bge_rx_return_ring_map);
2331         if (error)
2332                 return (ENOMEM);
2333
2334         bzero((char *)sc->bge_ldata.bge_rx_return_ring,
2335             BGE_RX_RTN_RING_SZ(sc));
2336
2337         /* Load the address of the RX return ring. */
2338         ctx.bge_maxsegs = 1;
2339         ctx.sc = sc;
2340
2341         error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag,
2342             sc->bge_cdata.bge_rx_return_ring_map,
2343             sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc),
2344             bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2345
2346         if (error)
2347                 return (ENOMEM);
2348
2349         sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr;
2350
2351         /* Create tag for TX ring. */
2352         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2353             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2354             NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL,
2355             &sc->bge_cdata.bge_tx_ring_tag);
2356
2357         if (error) {
2358                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2359                 return (ENOMEM);
2360         }
2361
2362         /* Allocate DMA'able memory for TX ring. */
2363         error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag,
2364             (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT,
2365             &sc->bge_cdata.bge_tx_ring_map);
2366         if (error)
2367                 return (ENOMEM);
2368
2369         bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
2370
2371         /* Load the address of the TX ring. */
2372         ctx.bge_maxsegs = 1;
2373         ctx.sc = sc;
2374
2375         error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag,
2376             sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring,
2377             BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2378
2379         if (error)
2380                 return (ENOMEM);
2381
2382         sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr;
2383
2384         /*
2385          * Create tag for status block.
2386          * Because we only use single Tx/Rx/Rx return ring, use
2387          * minimum status block size except BCM5700 AX/BX which
2388          * seems to want to see full status block size regardless
2389          * of configured number of ring.
2390          */
2391         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2392             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
2393                 sbsz = BGE_STATUS_BLK_SZ;
2394         else
2395                 sbsz = 32;
2396         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2397             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2398             NULL, sbsz, 1, sbsz, 0, NULL, NULL, &sc->bge_cdata.bge_status_tag);
2399
2400         if (error) {
2401                 device_printf(sc->bge_dev,
2402                     "could not allocate status dma tag\n");
2403                 return (ENOMEM);
2404         }
2405
2406         /* Allocate DMA'able memory for status block. */
2407         error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag,
2408             (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT,
2409             &sc->bge_cdata.bge_status_map);
2410         if (error)
2411                 return (ENOMEM);
2412
2413         bzero((char *)sc->bge_ldata.bge_status_block, sbsz);
2414
2415         /* Load the address of the status block. */
2416         ctx.sc = sc;
2417         ctx.bge_maxsegs = 1;
2418
2419         error = bus_dmamap_load(sc->bge_cdata.bge_status_tag,
2420             sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block,
2421             sbsz, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2422
2423         if (error)
2424                 return (ENOMEM);
2425
2426         sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr;
2427
2428         /* Create tag for statistics block. */
2429         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2430             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2431             NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL,
2432             &sc->bge_cdata.bge_stats_tag);
2433
2434         if (error) {
2435                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2436                 return (ENOMEM);
2437         }
2438
2439         /* Allocate DMA'able memory for statistics block. */
2440         error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag,
2441             (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT,
2442             &sc->bge_cdata.bge_stats_map);
2443         if (error)
2444                 return (ENOMEM);
2445
2446         bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ);
2447
2448         /* Load the address of the statstics block. */
2449         ctx.sc = sc;
2450         ctx.bge_maxsegs = 1;
2451
2452         error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag,
2453             sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats,
2454             BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2455
2456         if (error)
2457                 return (ENOMEM);
2458
2459         sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr;
2460
2461         return (0);
2462 }
2463
2464 /*
2465  * Return true if this device has more than one port.
2466  */
2467 static int
2468 bge_has_multiple_ports(struct bge_softc *sc)
2469 {
2470         device_t dev = sc->bge_dev;
2471         u_int b, d, f, fscan, s;
2472
2473         d = pci_get_domain(dev);
2474         b = pci_get_bus(dev);
2475         s = pci_get_slot(dev);
2476         f = pci_get_function(dev);
2477         for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
2478                 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
2479                         return (1);
2480         return (0);
2481 }
2482
2483 /*
2484  * Return true if MSI can be used with this device.
2485  */
2486 static int
2487 bge_can_use_msi(struct bge_softc *sc)
2488 {
2489         int can_use_msi = 0;
2490
2491         switch (sc->bge_asicrev) {
2492         case BGE_ASICREV_BCM5714_A0:
2493         case BGE_ASICREV_BCM5714:
2494                 /*
2495                  * Apparently, MSI doesn't work when these chips are
2496                  * configured in single-port mode.
2497                  */
2498                 if (bge_has_multiple_ports(sc))
2499                         can_use_msi = 1;
2500                 break;
2501         case BGE_ASICREV_BCM5750:
2502                 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
2503                     sc->bge_chiprev != BGE_CHIPREV_5750_BX)
2504                         can_use_msi = 1;
2505                 break;
2506         default:
2507                 if (BGE_IS_575X_PLUS(sc))
2508                         can_use_msi = 1;
2509         }
2510         return (can_use_msi);
2511 }
2512
2513 static int
2514 bge_attach(device_t dev)
2515 {
2516         struct ifnet *ifp;
2517         struct bge_softc *sc;
2518         uint32_t hwcfg = 0, misccfg;
2519         u_char eaddr[ETHER_ADDR_LEN];
2520         int error, msicount, reg, rid, trys;
2521
2522         sc = device_get_softc(dev);
2523         sc->bge_dev = dev;
2524
2525         TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
2526
2527         /*
2528          * Map control/status registers.
2529          */
2530         pci_enable_busmaster(dev);
2531
2532         rid = BGE_PCI_BAR0;
2533         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2534             RF_ACTIVE);
2535
2536         if (sc->bge_res == NULL) {
2537                 device_printf (sc->bge_dev, "couldn't map memory\n");
2538                 error = ENXIO;
2539                 goto fail;
2540         }
2541
2542         /* Save various chip information. */
2543         sc->bge_chipid =
2544             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2545             BGE_PCIMISCCTL_ASICREV_SHIFT;
2546         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
2547                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV,
2548                     4);
2549         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2550         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2551
2552         /*
2553          * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the
2554          * 5705 A0 and A1 chips.
2555          */
2556         if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
2557             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2558             sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2559             sc->bge_chipid != BGE_CHIPID_BCM5705_A1)
2560                 sc->bge_flags |= BGE_FLAG_WIRESPEED;
2561
2562         if (bge_has_eaddr(sc))
2563                 sc->bge_flags |= BGE_FLAG_EADDR;
2564
2565         /* Save chipset family. */
2566         switch (sc->bge_asicrev) {
2567         case BGE_ASICREV_BCM5755:
2568         case BGE_ASICREV_BCM5761:
2569         case BGE_ASICREV_BCM5784:
2570         case BGE_ASICREV_BCM5785:
2571         case BGE_ASICREV_BCM5787:
2572         case BGE_ASICREV_BCM57780:
2573                 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2574                     BGE_FLAG_5705_PLUS;
2575                 break;
2576         case BGE_ASICREV_BCM5700:
2577         case BGE_ASICREV_BCM5701:
2578         case BGE_ASICREV_BCM5703:
2579         case BGE_ASICREV_BCM5704:
2580                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2581                 break;
2582         case BGE_ASICREV_BCM5714_A0:
2583         case BGE_ASICREV_BCM5780:
2584         case BGE_ASICREV_BCM5714:
2585                 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */;
2586                 /* FALLTHROUGH */
2587         case BGE_ASICREV_BCM5750:
2588         case BGE_ASICREV_BCM5752:
2589         case BGE_ASICREV_BCM5906:
2590                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2591                 /* FALLTHROUGH */
2592         case BGE_ASICREV_BCM5705:
2593                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2594                 break;
2595         }
2596
2597         /* Set various bug flags. */
2598         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2599             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2600                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
2601         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2602             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2603                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
2604         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2605                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
2606         if (pci_get_subvendor(dev) == DELL_VENDORID)
2607                 sc->bge_flags |= BGE_FLAG_NO_3LED;
2608         if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
2609                 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
2610         if (BGE_IS_5705_PLUS(sc) &&
2611             !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) {
2612                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2613                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2614                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2615                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2616                         if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
2617                             pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
2618                                 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
2619                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
2620                         sc->bge_flags |= BGE_FLAG_BER_BUG;
2621         }
2622
2623         /*
2624          * All controllers that are not 5755 or higher have 4GB
2625          * boundary DMA bug.
2626          * Whenever an address crosses a multiple of the 4GB boundary
2627          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
2628          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
2629          * state machine will lockup and cause the device to hang.
2630          */
2631         if (BGE_IS_5755_PLUS(sc) == 0)
2632                 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
2633
2634         /*
2635          * We could possibly check for BCOM_DEVICEID_BCM5788 in bge_probe()
2636          * but I do not know the DEVICEID for the 5788M.
2637          */
2638         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID;
2639         if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2640             misccfg == BGE_MISCCFG_BOARD_ID_5788M)
2641                 sc->bge_flags |= BGE_FLAG_5788;
2642
2643         /*
2644          * Some controllers seem to require a special firmware to use
2645          * TSO. But the firmware is not available to FreeBSD and Linux
2646          * claims that the TSO performed by the firmware is slower than
2647          * hardware based TSO. Moreover the firmware based TSO has one
2648          * known bug which can't handle TSO if ethernet header + IP/TCP
2649          * header is greater than 80 bytes. The workaround for the TSO
2650          * bug exist but it seems it's too expensive than not using
2651          * TSO at all. Some hardwares also have the TSO bug so limit
2652          * the TSO to the controllers that are not affected TSO issues
2653          * (e.g. 5755 or higher).
2654          */
2655         if (BGE_IS_5755_PLUS(sc)) {
2656                 /*
2657                  * BCM5754 and BCM5787 shares the same ASIC id so
2658                  * explicit device id check is required.
2659                  * Due to unknown reason TSO does not work on BCM5755M.
2660                  */
2661                 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
2662                     pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
2663                     pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
2664                         sc->bge_flags |= BGE_FLAG_TSO;
2665         }
2666
2667         /*
2668          * Check if this is a PCI-X or PCI Express device.
2669          */
2670         if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {
2671                 /*
2672                  * Found a PCI Express capabilities register, this
2673                  * must be a PCI Express device.
2674                  */
2675                 sc->bge_flags |= BGE_FLAG_PCIE;
2676                 sc->bge_expcap = reg;
2677                 bge_set_max_readrq(sc);
2678         } else {
2679                 /*
2680                  * Check if the device is in PCI-X Mode.
2681                  * (This bit is not valid on PCI Express controllers.)
2682                  */
2683                 if (pci_find_extcap(dev, PCIY_PCIX, &reg) == 0)
2684                         sc->bge_pcixcap = reg;
2685                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
2686                     BGE_PCISTATE_PCI_BUSMODE) == 0)
2687                         sc->bge_flags |= BGE_FLAG_PCIX;
2688         }
2689
2690         /*
2691          * The 40bit DMA bug applies to the 5714/5715 controllers and is
2692          * not actually a MAC controller bug but an issue with the embedded
2693          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2694          */
2695         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
2696                 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
2697         /*
2698          * Allocate the interrupt, using MSI if possible.  These devices
2699          * support 8 MSI messages, but only the first one is used in
2700          * normal operation.
2701          */
2702         rid = 0;
2703         if (pci_find_extcap(sc->bge_dev, PCIY_MSI, &reg) == 0) {
2704                 sc->bge_msicap = reg;
2705                 if (bge_can_use_msi(sc)) {
2706                         msicount = pci_msi_count(dev);
2707                         if (msicount > 1)
2708                                 msicount = 1;
2709                 } else
2710                         msicount = 0;
2711                 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
2712                         rid = 1;
2713                         sc->bge_flags |= BGE_FLAG_MSI;
2714                 }
2715         }
2716
2717         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2718             RF_SHAREABLE | RF_ACTIVE);
2719
2720         if (sc->bge_irq == NULL) {
2721                 device_printf(sc->bge_dev, "couldn't map interrupt\n");
2722                 error = ENXIO;
2723                 goto fail;
2724         }
2725
2726         if (bootverbose)
2727                 device_printf(dev,
2728                     "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2729                     sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2730                     (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" :
2731                     ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI"));
2732
2733         BGE_LOCK_INIT(sc, device_get_nameunit(dev));
2734
2735         /* Try to reset the chip. */
2736         if (bge_reset(sc)) {
2737                 device_printf(sc->bge_dev, "chip reset failed\n");
2738                 error = ENXIO;
2739                 goto fail;
2740         }
2741
2742         sc->bge_asf_mode = 0;
2743         if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG)
2744             == BGE_MAGIC_NUMBER)) {
2745                 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG)
2746                     & BGE_HWCFG_ASF) {
2747                         sc->bge_asf_mode |= ASF_ENABLE;
2748                         sc->bge_asf_mode |= ASF_STACKUP;
2749                         if (BGE_IS_575X_PLUS(sc))
2750                                 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
2751                 }
2752         }
2753
2754         /* Try to reset the chip again the nice way. */
2755         bge_stop_fw(sc);
2756         bge_sig_pre_reset(sc, BGE_RESET_STOP);
2757         if (bge_reset(sc)) {
2758                 device_printf(sc->bge_dev, "chip reset failed\n");
2759                 error = ENXIO;
2760                 goto fail;
2761         }
2762
2763         bge_sig_legacy(sc, BGE_RESET_STOP);
2764         bge_sig_post_reset(sc, BGE_RESET_STOP);
2765
2766         if (bge_chipinit(sc)) {
2767                 device_printf(sc->bge_dev, "chip initialization failed\n");
2768                 error = ENXIO;
2769                 goto fail;
2770         }
2771
2772         error = bge_get_eaddr(sc, eaddr);
2773         if (error) {
2774                 device_printf(sc->bge_dev,
2775                     "failed to read station address\n");
2776                 error = ENXIO;
2777                 goto fail;
2778         }
2779
2780         /* 5705 limits RX return ring to 512 entries. */
2781         if (BGE_IS_5705_PLUS(sc))
2782                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2783         else
2784                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2785
2786         if (bge_dma_alloc(dev)) {
2787                 device_printf(sc->bge_dev,
2788                     "failed to allocate DMA resources\n");
2789                 error = ENXIO;
2790                 goto fail;
2791         }
2792
2793         /* Set default tuneable values. */
2794         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2795         sc->bge_rx_coal_ticks = 150;
2796         sc->bge_tx_coal_ticks = 150;
2797         sc->bge_rx_max_coal_bds = 10;
2798         sc->bge_tx_max_coal_bds = 10;
2799
2800         /* Set up ifnet structure */
2801         ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
2802         if (ifp == NULL) {
2803                 device_printf(sc->bge_dev, "failed to if_alloc()\n");
2804                 error = ENXIO;
2805                 goto fail;
2806         }
2807         ifp->if_softc = sc;
2808         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2809         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2810         ifp->if_ioctl = bge_ioctl;
2811         ifp->if_start = bge_start;
2812         ifp->if_init = bge_init;
2813         ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
2814         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2815         IFQ_SET_READY(&ifp->if_snd);
2816         ifp->if_hwassist = BGE_CSUM_FEATURES;
2817         ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
2818             IFCAP_VLAN_MTU;
2819         if ((sc->bge_flags & BGE_FLAG_TSO) != 0) {
2820                 ifp->if_hwassist |= CSUM_TSO;
2821                 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO;
2822         }
2823 #ifdef IFCAP_VLAN_HWCSUM
2824         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
2825 #endif
2826         ifp->if_capenable = ifp->if_capabilities;
2827 #ifdef DEVICE_POLLING
2828         ifp->if_capabilities |= IFCAP_POLLING;
2829 #endif
2830
2831         /*
2832          * 5700 B0 chips do not support checksumming correctly due
2833          * to hardware bugs.
2834          */
2835         if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
2836                 ifp->if_capabilities &= ~IFCAP_HWCSUM;
2837                 ifp->if_capenable &= ~IFCAP_HWCSUM;
2838                 ifp->if_hwassist = 0;
2839         }
2840
2841         /*
2842          * Figure out what sort of media we have by checking the
2843          * hardware config word in the first 32k of NIC internal memory,
2844          * or fall back to examining the EEPROM if necessary.
2845          * Note: on some BCM5700 cards, this value appears to be unset.
2846          * If that's the case, we have to rely on identifying the NIC
2847          * by its PCI subsystem ID, as we do below for the SysKonnect
2848          * SK-9D41.
2849          */
2850         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2851                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2852         else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
2853             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
2854                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2855                     sizeof(hwcfg))) {
2856                         device_printf(sc->bge_dev, "failed to read EEPROM\n");
2857                         error = ENXIO;
2858                         goto fail;
2859                 }
2860                 hwcfg = ntohl(hwcfg);
2861         }
2862
2863         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2864         if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
2865             SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2866                 if (BGE_IS_5714_FAMILY(sc))
2867                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
2868                 else
2869                         sc->bge_flags |= BGE_FLAG_TBI;
2870         }
2871
2872         if (sc->bge_flags & BGE_FLAG_TBI) {
2873                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
2874                     bge_ifmedia_sts);
2875                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
2876                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2877                     0, NULL);
2878                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
2879                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
2880                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2881         } else {
2882                 /*
2883                  * Do transceiver setup and tell the firmware the
2884                  * driver is down so we can try to get access the
2885                  * probe if ASF is running.  Retry a couple of times
2886                  * if we get a conflict with the ASF firmware accessing
2887                  * the PHY.
2888                  */
2889                 trys = 0;
2890                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2891 again:
2892                 bge_asf_driver_up(sc);
2893
2894                 if (mii_phy_probe(dev, &sc->bge_miibus,
2895                     bge_ifmedia_upd, bge_ifmedia_sts)) {
2896                         if (trys++ < 4) {
2897                                 device_printf(sc->bge_dev, "Try again\n");
2898                                 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR,
2899                                     BMCR_RESET);
2900                                 goto again;
2901                         }
2902
2903                         device_printf(sc->bge_dev, "MII without any PHY!\n");
2904                         error = ENXIO;
2905                         goto fail;
2906                 }
2907
2908                 /*
2909                  * Now tell the firmware we are going up after probing the PHY
2910                  */
2911                 if (sc->bge_asf_mode & ASF_STACKUP)
2912                         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2913         }
2914
2915         /*
2916          * When using the BCM5701 in PCI-X mode, data corruption has
2917          * been observed in the first few bytes of some received packets.
2918          * Aligning the packet buffer in memory eliminates the corruption.
2919          * Unfortunately, this misaligns the packet payloads.  On platforms
2920          * which do not support unaligned accesses, we will realign the
2921          * payloads by copying the received packets.
2922          */
2923         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2924             sc->bge_flags & BGE_FLAG_PCIX)
2925                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2926
2927         /*
2928          * Call MI attach routine.
2929          */
2930         ether_ifattach(ifp, eaddr);
2931         callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
2932
2933         /* Tell upper layer we support long frames. */
2934         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2935
2936         /*
2937          * Hookup IRQ last.
2938          */
2939 #if __FreeBSD_version > 700030
2940         if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
2941                 /* Take advantage of single-shot MSI. */
2942                 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
2943                     ~BGE_MSIMODE_ONE_SHOT_DISABLE);
2944                 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
2945                     taskqueue_thread_enqueue, &sc->bge_tq);
2946                 if (sc->bge_tq == NULL) {
2947                         device_printf(dev, "could not create taskqueue.\n");
2948                         ether_ifdetach(ifp);
2949                         error = ENXIO;
2950                         goto fail;
2951                 }
2952                 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq",
2953                     device_get_nameunit(sc->bge_dev));
2954                 error = bus_setup_intr(dev, sc->bge_irq,
2955                     INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
2956                     &sc->bge_intrhand);
2957                 if (error)
2958                         ether_ifdetach(ifp);
2959         } else
2960                 error = bus_setup_intr(dev, sc->bge_irq,
2961                     INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
2962                     &sc->bge_intrhand);
2963 #else
2964         error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2965            bge_intr, sc, &sc->bge_intrhand);
2966 #endif
2967
2968         if (error) {
2969                 bge_detach(dev);
2970                 device_printf(sc->bge_dev, "couldn't set up irq\n");
2971         }
2972
2973         bge_add_sysctls(sc);
2974
2975         return (0);
2976
2977 fail:
2978         bge_release_resources(sc);
2979
2980         return (error);
2981 }
2982
2983 static int
2984 bge_detach(device_t dev)
2985 {
2986         struct bge_softc *sc;
2987         struct ifnet *ifp;
2988
2989         sc = device_get_softc(dev);
2990         ifp = sc->bge_ifp;
2991
2992 #ifdef DEVICE_POLLING
2993         if (ifp->if_capenable & IFCAP_POLLING)
2994                 ether_poll_deregister(ifp);
2995 #endif
2996
2997         BGE_LOCK(sc);
2998         bge_stop(sc);
2999         bge_reset(sc);
3000         BGE_UNLOCK(sc);
3001
3002         callout_drain(&sc->bge_stat_ch);
3003
3004         if (sc->bge_tq)
3005                 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3006         ether_ifdetach(ifp);
3007
3008         if (sc->bge_flags & BGE_FLAG_TBI) {
3009                 ifmedia_removeall(&sc->bge_ifmedia);
3010         } else {
3011                 bus_generic_detach(dev);
3012                 device_delete_child(dev, sc->bge_miibus);
3013         }
3014
3015         bge_release_resources(sc);
3016
3017         return (0);
3018 }
3019
3020 static void
3021 bge_release_resources(struct bge_softc *sc)
3022 {
3023         device_t dev;
3024
3025         dev = sc->bge_dev;
3026
3027         if (sc->bge_tq != NULL)
3028                 taskqueue_free(sc->bge_tq);
3029
3030         if (sc->bge_intrhand != NULL)
3031                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3032
3033         if (sc->bge_irq != NULL)
3034                 bus_release_resource(dev, SYS_RES_IRQ,
3035                     sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
3036
3037         if (sc->bge_flags & BGE_FLAG_MSI)
3038                 pci_release_msi(dev);
3039
3040         if (sc->bge_res != NULL)
3041                 bus_release_resource(dev, SYS_RES_MEMORY,
3042                     BGE_PCI_BAR0, sc->bge_res);
3043
3044         if (sc->bge_ifp != NULL)
3045                 if_free(sc->bge_ifp);
3046
3047         bge_dma_free(sc);
3048
3049         if (mtx_initialized(&sc->bge_mtx))      /* XXX */
3050                 BGE_LOCK_DESTROY(sc);
3051 }
3052
3053 static int
3054 bge_reset(struct bge_softc *sc)
3055 {
3056         device_t dev;
3057         uint32_t cachesize, command, pcistate, reset, val;
3058         void (*write_op)(struct bge_softc *, int, int);
3059         uint16_t devctl;
3060         int i;
3061
3062         dev = sc->bge_dev;
3063
3064         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
3065             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3066                 if (sc->bge_flags & BGE_FLAG_PCIE)
3067                         write_op = bge_writemem_direct;
3068                 else
3069                         write_op = bge_writemem_ind;
3070         } else
3071                 write_op = bge_writereg_ind;
3072
3073         /* Save some important PCI state. */
3074         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
3075         command = pci_read_config(dev, BGE_PCI_CMD, 4);
3076         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3077
3078         pci_write_config(dev, BGE_PCI_MISC_CTL,
3079             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3080             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3081
3082         /* Disable fastboot on controllers that support it. */
3083         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
3084             BGE_IS_5755_PLUS(sc)) {
3085                 if (bootverbose)
3086                         device_printf(sc->bge_dev, "Disabling fastboot\n");
3087                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
3088         }
3089
3090         /*
3091          * Write the magic number to SRAM at offset 0xB50.
3092          * When firmware finishes its initialization it will
3093          * write ~BGE_MAGIC_NUMBER to the same location.
3094          */
3095         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
3096
3097         reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
3098
3099         /* XXX: Broadcom Linux driver. */
3100         if (sc->bge_flags & BGE_FLAG_PCIE) {
3101                 if (CSR_READ_4(sc, 0x7E2C) == 0x60)     /* PCIE 1.0 */
3102                         CSR_WRITE_4(sc, 0x7E2C, 0x20);
3103                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3104                         /* Prevent PCIE link training during global reset */
3105                         CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
3106                         reset |= 1 << 29;
3107                 }
3108         }
3109
3110         /*
3111          * Set GPHY Power Down Override to leave GPHY
3112          * powered up in D0 uninitialized.
3113          */
3114         if (BGE_IS_5705_PLUS(sc))
3115                 reset |= 0x04000000;
3116
3117         /* Issue global reset */
3118         write_op(sc, BGE_MISC_CFG, reset);
3119
3120         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3121                 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3122                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
3123                     val | BGE_VCPU_STATUS_DRV_RESET);
3124                 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
3125                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
3126                     val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
3127         }
3128
3129         DELAY(1000);
3130
3131         /* XXX: Broadcom Linux driver. */
3132         if (sc->bge_flags & BGE_FLAG_PCIE) {
3133                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
3134                         DELAY(500000); /* wait for link training to complete */
3135                         val = pci_read_config(dev, 0xC4, 4);
3136                         pci_write_config(dev, 0xC4, val | (1 << 15), 4);
3137                 }
3138                 devctl = pci_read_config(dev,
3139                     sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
3140                 /* Clear enable no snoop and disable relaxed ordering. */
3141                 devctl &= ~(PCIM_EXP_CTL_RELAXED_ORD_ENABLE |
3142                     PCIM_EXP_CTL_NOSNOOP_ENABLE);
3143                 /* Set PCIE max payload size to 128. */
3144                 devctl &= ~PCIM_EXP_CTL_MAX_PAYLOAD;
3145                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL,
3146                     devctl, 2);
3147                 /* Clear error status. */
3148                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA,
3149                     PCIM_EXP_STA_CORRECTABLE_ERROR |
3150                     PCIM_EXP_STA_NON_FATAL_ERROR | PCIM_EXP_STA_FATAL_ERROR |
3151                     PCIM_EXP_STA_UNSUPPORTED_REQ, 2);
3152         }
3153
3154         /* Reset some of the PCI state that got zapped by reset. */
3155         pci_write_config(dev, BGE_PCI_MISC_CTL,
3156             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3157             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3158         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
3159         pci_write_config(dev, BGE_PCI_CMD, command, 4);
3160         write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
3161
3162         /* Re-enable MSI, if neccesary, and enable the memory arbiter. */
3163         if (BGE_IS_5714_FAMILY(sc)) {
3164                 /* This chip disables MSI on reset. */
3165                 if (sc->bge_flags & BGE_FLAG_MSI) {
3166                         val = pci_read_config(dev,
3167                             sc->bge_msicap + PCIR_MSI_CTRL, 2);
3168                         pci_write_config(dev,
3169                             sc->bge_msicap + PCIR_MSI_CTRL,
3170                             val | PCIM_MSICTRL_MSI_ENABLE, 2);
3171                         val = CSR_READ_4(sc, BGE_MSI_MODE);
3172                         CSR_WRITE_4(sc, BGE_MSI_MODE,
3173                             val | BGE_MSIMODE_ENABLE);
3174                 }
3175                 val = CSR_READ_4(sc, BGE_MARB_MODE);
3176                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
3177         } else
3178                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3179
3180         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3181                 for (i = 0; i < BGE_TIMEOUT; i++) {
3182                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3183                         if (val & BGE_VCPU_STATUS_INIT_DONE)
3184                                 break;
3185                         DELAY(100);
3186                 }
3187                 if (i == BGE_TIMEOUT) {
3188                         device_printf(sc->bge_dev, "reset timed out\n");
3189                         return (1);
3190                 }
3191         } else {
3192                 /*
3193                  * Poll until we see the 1's complement of the magic number.
3194                  * This indicates that the firmware initialization is complete.
3195                  * We expect this to fail if no chip containing the Ethernet
3196                  * address is fitted though.
3197                  */
3198                 for (i = 0; i < BGE_TIMEOUT; i++) {
3199                         DELAY(10);
3200                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
3201                         if (val == ~BGE_MAGIC_NUMBER)
3202                                 break;
3203                 }
3204
3205                 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
3206                         device_printf(sc->bge_dev, "firmware handshake timed out, "
3207                             "found 0x%08x\n", val);
3208         }
3209
3210         /*
3211          * XXX Wait for the value of the PCISTATE register to
3212          * return to its original pre-reset state. This is a
3213          * fairly good indicator of reset completion. If we don't
3214          * wait for the reset to fully complete, trying to read
3215          * from the device's non-PCI registers may yield garbage
3216          * results.
3217          */
3218         for (i = 0; i < BGE_TIMEOUT; i++) {
3219                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
3220                         break;
3221                 DELAY(10);
3222         }
3223
3224         if (sc->bge_flags & BGE_FLAG_PCIE) {
3225                 reset = bge_readmem_ind(sc, 0x7C00);
3226                 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25));
3227         }
3228
3229         /* Fix up byte swapping. */
3230         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
3231             BGE_MODECTL_BYTESWAP_DATA);
3232
3233         /* Tell the ASF firmware we are up */
3234         if (sc->bge_asf_mode & ASF_STACKUP)
3235                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3236
3237         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
3238
3239         /*
3240          * The 5704 in TBI mode apparently needs some special
3241          * adjustment to insure the SERDES drive level is set
3242          * to 1.2V.
3243          */
3244         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
3245             sc->bge_flags & BGE_FLAG_TBI) {
3246                 val = CSR_READ_4(sc, BGE_SERDES_CFG);
3247                 val = (val & ~0xFFF) | 0x880;
3248                 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
3249         }
3250
3251         /* XXX: Broadcom Linux driver. */
3252         if (sc->bge_flags & BGE_FLAG_PCIE &&
3253             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3254                 val = CSR_READ_4(sc, 0x7C00);
3255                 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
3256         }
3257         DELAY(10000);
3258
3259         return(0);
3260 }
3261
3262 /*
3263  * Frame reception handling. This is called if there's a frame
3264  * on the receive return list.
3265  *
3266  * Note: we have to be able to handle two possibilities here:
3267  * 1) the frame is from the jumbo receive ring
3268  * 2) the frame is from the standard receive ring
3269  */
3270
3271 static int
3272 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
3273 {
3274         struct ifnet *ifp;
3275         int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
3276         uint16_t rx_cons;
3277
3278         rx_cons = sc->bge_rx_saved_considx;
3279
3280         /* Nothing to do. */
3281         if (rx_cons == rx_prod)
3282                 return (rx_npkts);
3283
3284         ifp = sc->bge_ifp;
3285
3286         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3287             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
3288         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3289             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
3290         if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
3291             (MCLBYTES - ETHER_ALIGN))
3292                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3293                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
3294
3295         while (rx_cons != rx_prod) {
3296                 struct bge_rx_bd        *cur_rx;
3297                 uint32_t                rxidx;
3298                 struct mbuf             *m = NULL;
3299                 uint16_t                vlan_tag = 0;
3300                 int                     have_tag = 0;
3301
3302 #ifdef DEVICE_POLLING
3303                 if (ifp->if_capenable & IFCAP_POLLING) {
3304                         if (sc->rxcycles <= 0)
3305                                 break;
3306                         sc->rxcycles--;
3307                 }
3308 #endif
3309
3310                 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
3311
3312                 rxidx = cur_rx->bge_idx;
3313                 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
3314
3315                 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
3316                     cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
3317                         have_tag = 1;
3318                         vlan_tag = cur_rx->bge_vlan_tag;
3319                 }
3320
3321                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
3322                         jumbocnt++;
3323                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
3324                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3325                                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3326                                 continue;
3327                         }
3328                         if (bge_newbuf_jumbo(sc, rxidx) != 0) {
3329                                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3330                                 ifp->if_iqdrops++;
3331                                 continue;
3332                         }
3333                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3334                 } else {
3335                         stdcnt++;
3336                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3337                                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3338                                 continue;
3339                         }
3340                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
3341                         if (bge_newbuf_std(sc, rxidx) != 0) {
3342                                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3343                                 ifp->if_iqdrops++;
3344                                 continue;
3345                         }
3346                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3347                 }
3348
3349                 ifp->if_ipackets++;
3350 #ifndef __NO_STRICT_ALIGNMENT
3351                 /*
3352                  * For architectures with strict alignment we must make sure
3353                  * the payload is aligned.
3354                  */
3355                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
3356                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
3357                             cur_rx->bge_len);
3358                         m->m_data += ETHER_ALIGN;
3359                 }
3360 #endif
3361                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3362                 m->m_pkthdr.rcvif = ifp;
3363
3364                 if (ifp->if_capenable & IFCAP_RXCSUM) {
3365                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3366                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3367                                 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
3368                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3369                         }
3370                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
3371                             m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
3372                                 m->m_pkthdr.csum_data =
3373                                     cur_rx->bge_tcp_udp_csum;
3374                                 m->m_pkthdr.csum_flags |=
3375                                     CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
3376                         }
3377                 }
3378
3379                 /*
3380                  * If we received a packet with a vlan tag,
3381                  * attach that information to the packet.
3382                  */
3383                 if (have_tag) {
3384 #if __FreeBSD_version > 700022
3385                         m->m_pkthdr.ether_vtag = vlan_tag;
3386                         m->m_flags |= M_VLANTAG;
3387 #else
3388                         VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag);
3389                         if (m == NULL)
3390                                 continue;
3391 #endif
3392                 }
3393
3394                 if (holdlck != 0) {
3395                         BGE_UNLOCK(sc);
3396                         (*ifp->if_input)(ifp, m);
3397                         BGE_LOCK(sc);
3398                 } else
3399                         (*ifp->if_input)(ifp, m);
3400                 rx_npkts++;
3401
3402                 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
3403                         return (rx_npkts);
3404         }
3405
3406         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3407             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
3408         if (stdcnt > 0)
3409                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3410                     sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
3411
3412         if (jumbocnt > 0)
3413                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3414                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
3415
3416         sc->bge_rx_saved_considx = rx_cons;
3417         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3418         if (stdcnt)
3419                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
3420         if (jumbocnt)
3421                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
3422 #ifdef notyet
3423         /*
3424          * This register wraps very quickly under heavy packet drops.
3425          * If you need correct statistics, you can enable this check.
3426          */
3427         if (BGE_IS_5705_PLUS(sc))
3428                 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3429 #endif
3430         return (rx_npkts);
3431 }
3432
3433 static void
3434 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
3435 {
3436         struct bge_tx_bd *cur_tx = NULL;
3437         struct ifnet *ifp;
3438
3439         BGE_LOCK_ASSERT(sc);
3440
3441         /* Nothing to do. */
3442         if (sc->bge_tx_saved_considx == tx_cons)
3443                 return;
3444
3445         ifp = sc->bge_ifp;
3446
3447         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
3448             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
3449         /*
3450          * Go through our tx ring and free mbufs for those
3451          * frames that have been sent.
3452          */
3453         while (sc->bge_tx_saved_considx != tx_cons) {
3454                 uint32_t                idx = 0;
3455
3456                 idx = sc->bge_tx_saved_considx;
3457                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
3458                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
3459                         ifp->if_opackets++;
3460                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
3461                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
3462                             sc->bge_cdata.bge_tx_dmamap[idx],
3463                             BUS_DMASYNC_POSTWRITE);
3464                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
3465                             sc->bge_cdata.bge_tx_dmamap[idx]);
3466                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
3467                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
3468                 }
3469                 sc->bge_txcnt--;
3470                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3471         }
3472
3473         if (cur_tx != NULL)
3474                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3475         if (sc->bge_txcnt == 0)
3476                 sc->bge_timer = 0;
3477 }
3478
3479 #ifdef DEVICE_POLLING
3480 static int
3481 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3482 {
3483         struct bge_softc *sc = ifp->if_softc;
3484         uint16_t rx_prod, tx_cons;
3485         uint32_t statusword;
3486         int rx_npkts = 0;
3487
3488         BGE_LOCK(sc);
3489         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3490                 BGE_UNLOCK(sc);
3491                 return (rx_npkts);
3492         }
3493
3494         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3495             sc->bge_cdata.bge_status_map,
3496             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3497         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3498         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3499
3500         statusword = atomic_readandclear_32(
3501             &sc->bge_ldata.bge_status_block->bge_status);
3502
3503         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3504             sc->bge_cdata.bge_status_map,
3505             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3506
3507         /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
3508         if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
3509                 sc->bge_link_evt++;
3510
3511         if (cmd == POLL_AND_CHECK_STATUS)
3512                 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3513                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3514                     sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
3515                         bge_link_upd(sc);
3516
3517         sc->rxcycles = count;
3518         rx_npkts = bge_rxeof(sc, rx_prod, 1);
3519         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3520                 BGE_UNLOCK(sc);
3521                 return (rx_npkts);
3522         }
3523         bge_txeof(sc, tx_cons);
3524         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3525                 bge_start_locked(ifp);
3526
3527         BGE_UNLOCK(sc);
3528         return (rx_npkts);
3529 }
3530 #endif /* DEVICE_POLLING */
3531
3532 static int
3533 bge_msi_intr(void *arg)
3534 {
3535         struct bge_softc *sc;
3536
3537         sc = (struct bge_softc *)arg;
3538         /*
3539          * This interrupt is not shared and controller already
3540          * disabled further interrupt.
3541          */
3542         taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
3543         return (FILTER_HANDLED);
3544 }
3545
3546 static void
3547 bge_intr_task(void *arg, int pending)
3548 {
3549         struct bge_softc *sc;
3550         struct ifnet *ifp;
3551         uint32_t status;
3552         uint16_t rx_prod, tx_cons;
3553
3554         sc = (struct bge_softc *)arg;
3555         ifp = sc->bge_ifp;
3556
3557         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3558                 return;
3559
3560         /* Get updated status block. */
3561         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3562             sc->bge_cdata.bge_status_map,
3563             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3564
3565         /* Save producer/consumer indexess. */
3566         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3567         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3568         status = sc->bge_ldata.bge_status_block->bge_status;
3569         sc->bge_ldata.bge_status_block->bge_status = 0;
3570         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3571             sc->bge_cdata.bge_status_map,
3572             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3573         /* Let controller work. */
3574         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3575
3576         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) {
3577                 BGE_LOCK(sc);
3578                 bge_link_upd(sc);
3579                 BGE_UNLOCK(sc);
3580         }
3581         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3582                 /* Check RX return ring producer/consumer. */
3583                 bge_rxeof(sc, rx_prod, 0);
3584         }
3585         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3586                 BGE_LOCK(sc);
3587                 /* Check TX ring producer/consumer. */
3588                 bge_txeof(sc, tx_cons);
3589                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3590                         bge_start_locked(ifp);
3591                 BGE_UNLOCK(sc);
3592         }
3593 }
3594
3595 static void
3596 bge_intr(void *xsc)
3597 {
3598         struct bge_softc *sc;
3599         struct ifnet *ifp;
3600         uint32_t statusword;
3601         uint16_t rx_prod, tx_cons;
3602
3603         sc = xsc;
3604
3605         BGE_LOCK(sc);
3606
3607         ifp = sc->bge_ifp;
3608
3609 #ifdef DEVICE_POLLING
3610         if (ifp->if_capenable & IFCAP_POLLING) {
3611                 BGE_UNLOCK(sc);
3612                 return;
3613         }
3614 #endif
3615
3616         /*
3617          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
3618          * disable interrupts by writing nonzero like we used to, since with
3619          * our current organization this just gives complications and
3620          * pessimizations for re-enabling interrupts.  We used to have races
3621          * instead of the necessary complications.  Disabling interrupts
3622          * would just reduce the chance of a status update while we are
3623          * running (by switching to the interrupt-mode coalescence
3624          * parameters), but this chance is already very low so it is more
3625          * efficient to get another interrupt than prevent it.
3626          *
3627          * We do the ack first to ensure another interrupt if there is a
3628          * status update after the ack.  We don't check for the status
3629          * changing later because it is more efficient to get another
3630          * interrupt than prevent it, not quite as above (not checking is
3631          * a smaller optimization than not toggling the interrupt enable,
3632          * since checking doesn't involve PCI accesses and toggling require
3633          * the status check).  So toggling would probably be a pessimization
3634          * even with MSI.  It would only be needed for using a task queue.
3635          */
3636         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3637
3638         /*
3639          * Do the mandatory PCI flush as well as get the link status.
3640          */
3641         statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
3642
3643         /* Make sure the descriptor ring indexes are coherent. */
3644         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3645             sc->bge_cdata.bge_status_map,
3646             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3647         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3648         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3649         sc->bge_ldata.bge_status_block->bge_status = 0;
3650         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3651             sc->bge_cdata.bge_status_map,
3652             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3653
3654         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3655             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3656             statusword || sc->bge_link_evt)
3657                 bge_link_upd(sc);
3658
3659         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3660                 /* Check RX return ring producer/consumer. */
3661                 bge_rxeof(sc, rx_prod, 1);
3662         }
3663
3664         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3665                 /* Check TX ring producer/consumer. */
3666                 bge_txeof(sc, tx_cons);
3667         }
3668
3669         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3670             !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3671                 bge_start_locked(ifp);
3672
3673         BGE_UNLOCK(sc);
3674 }
3675
3676 static void
3677 bge_asf_driver_up(struct bge_softc *sc)
3678 {
3679         if (sc->bge_asf_mode & ASF_STACKUP) {
3680                 /* Send ASF heartbeat aprox. every 2s */
3681                 if (sc->bge_asf_count)
3682                         sc->bge_asf_count --;
3683                 else {
3684                         sc->bge_asf_count = 2;
3685                         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW,
3686                             BGE_FW_DRV_ALIVE);
3687                         bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4);
3688                         bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3);
3689                         CSR_WRITE_4(sc, BGE_CPU_EVENT,
3690                             CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
3691                 }
3692         }
3693 }
3694
3695 static void
3696 bge_tick(void *xsc)
3697 {
3698         struct bge_softc *sc = xsc;
3699         struct mii_data *mii = NULL;
3700
3701         BGE_LOCK_ASSERT(sc);
3702
3703         /* Synchronize with possible callout reset/stop. */
3704         if (callout_pending(&sc->bge_stat_ch) ||
3705             !callout_active(&sc->bge_stat_ch))
3706                 return;
3707
3708         if (BGE_IS_5705_PLUS(sc))
3709                 bge_stats_update_regs(sc);
3710         else
3711                 bge_stats_update(sc);
3712
3713         if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
3714                 mii = device_get_softc(sc->bge_miibus);
3715                 /*
3716                  * Do not touch PHY if we have link up. This could break
3717                  * IPMI/ASF mode or produce extra input errors
3718                  * (extra errors was reported for bcm5701 & bcm5704).
3719                  */
3720                 if (!sc->bge_link)
3721                         mii_tick(mii);
3722         } else {
3723                 /*
3724                  * Since in TBI mode auto-polling can't be used we should poll
3725                  * link status manually. Here we register pending link event
3726                  * and trigger interrupt.
3727                  */
3728 #ifdef DEVICE_POLLING
3729                 /* In polling mode we poll link state in bge_poll(). */
3730                 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
3731 #endif
3732                 {
3733                 sc->bge_link_evt++;
3734                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3735                     sc->bge_flags & BGE_FLAG_5788)
3736                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3737                 else
3738                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3739                 }
3740         }
3741
3742         bge_asf_driver_up(sc);
3743         bge_watchdog(sc);
3744
3745         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
3746 }
3747
3748 static void
3749 bge_stats_update_regs(struct bge_softc *sc)
3750 {
3751         struct ifnet *ifp;
3752
3753         ifp = sc->bge_ifp;
3754
3755         ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS +
3756             offsetof(struct bge_mac_stats_regs, etherStatsCollisions));
3757
3758         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
3759         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3760         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
3761 }
3762
3763 static void
3764 bge_stats_update(struct bge_softc *sc)
3765 {
3766         struct ifnet *ifp;
3767         bus_size_t stats;
3768         uint32_t cnt;   /* current register value */
3769
3770         ifp = sc->bge_ifp;
3771
3772         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3773
3774 #define READ_STAT(sc, stats, stat) \
3775         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3776
3777         cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
3778         ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
3779         sc->bge_tx_collisions = cnt;
3780
3781         cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
3782         ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
3783         sc->bge_rx_discards = cnt;
3784
3785         cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
3786         ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
3787         sc->bge_tx_discards = cnt;
3788
3789 #undef  READ_STAT
3790 }
3791
3792 /*
3793  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
3794  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
3795  * but when such padded frames employ the bge IP/TCP checksum offload,
3796  * the hardware checksum assist gives incorrect results (possibly
3797  * from incorporating its own padding into the UDP/TCP checksum; who knows).
3798  * If we pad such runts with zeros, the onboard checksum comes out correct.
3799  */
3800 static __inline int
3801 bge_cksum_pad(struct mbuf *m)
3802 {
3803         int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
3804         struct mbuf *last;
3805
3806         /* If there's only the packet-header and we can pad there, use it. */
3807         if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
3808             M_TRAILINGSPACE(m) >= padlen) {
3809                 last = m;
3810         } else {
3811                 /*
3812                  * Walk packet chain to find last mbuf. We will either
3813                  * pad there, or append a new mbuf and pad it.
3814                  */
3815                 for (last = m; last->m_next != NULL; last = last->m_next);
3816                 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
3817                         /* Allocate new empty mbuf, pad it. Compact later. */
3818                         struct mbuf *n;
3819
3820                         MGET(n, M_DONTWAIT, MT_DATA);
3821                         if (n == NULL)
3822                                 return (ENOBUFS);
3823                         n->m_len = 0;
3824                         last->m_next = n;
3825                         last = n;
3826                 }
3827         }
3828
3829         /* Now zero the pad area, to avoid the bge cksum-assist bug. */
3830         memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
3831         last->m_len += padlen;
3832         m->m_pkthdr.len += padlen;
3833
3834         return (0);
3835 }
3836
3837 static struct mbuf *
3838 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss)
3839 {
3840         struct ip *ip;
3841         struct tcphdr *tcp;
3842         struct mbuf *n;
3843         uint16_t hlen;
3844         uint32_t poff;
3845
3846         if (M_WRITABLE(m) == 0) {
3847                 /* Get a writable copy. */
3848                 n = m_dup(m, M_DONTWAIT);
3849                 m_freem(m);
3850                 if (n == NULL)
3851                         return (NULL);
3852                 m = n;
3853         }
3854         m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
3855         if (m == NULL)
3856                 return (NULL);
3857         ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
3858         poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
3859         m = m_pullup(m, poff + sizeof(struct tcphdr));
3860         if (m == NULL)
3861                 return (NULL);
3862         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
3863         m = m_pullup(m, poff + (tcp->th_off << 2));
3864         if (m == NULL)
3865                 return (NULL);
3866         /*
3867          * It seems controller doesn't modify IP length and TCP pseudo
3868          * checksum. These checksum computed by upper stack should be 0.
3869          */
3870         *mss = m->m_pkthdr.tso_segsz;
3871         ip->ip_sum = 0;
3872         ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
3873         /* Clear pseudo checksum computed by TCP stack. */
3874         tcp->th_sum = 0;
3875         /*
3876          * Broadcom controllers uses different descriptor format for
3877          * TSO depending on ASIC revision. Due to TSO-capable firmware
3878          * license issue and lower performance of firmware based TSO
3879          * we only support hardware based TSO which is applicable for
3880          * BCM5755 or newer controllers. Hardware based TSO uses 11
3881          * bits to store MSS and upper 5 bits are used to store IP/TCP
3882          * header length(including IP/TCP options). The header length
3883          * is expressed as 32 bits unit.
3884          */
3885         hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
3886         *mss |= (hlen << 11);
3887         return (m);
3888 }
3889
3890 /*
3891  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
3892  * pointers to descriptors.
3893  */
3894 static int
3895 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
3896 {
3897         bus_dma_segment_t       segs[BGE_NSEG_NEW];
3898         bus_dmamap_t            map;
3899         struct bge_tx_bd        *d;
3900         struct mbuf             *m = *m_head;
3901         uint32_t                idx = *txidx;
3902         uint16_t                csum_flags, mss, vlan_tag;
3903         int                     nsegs, i, error;
3904
3905         csum_flags = 0;
3906         mss = 0;
3907         vlan_tag = 0;
3908         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
3909                 *m_head = m = bge_setup_tso(sc, m, &mss);
3910                 if (*m_head == NULL)
3911                         return (ENOBUFS);
3912                 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
3913                     BGE_TXBDFLAG_CPU_POST_DMA;
3914         } else if ((m->m_pkthdr.csum_flags & BGE_CSUM_FEATURES) != 0) {
3915                 if (m->m_pkthdr.csum_flags & CSUM_IP)
3916                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3917                 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
3918                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3919                         if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
3920                             (error = bge_cksum_pad(m)) != 0) {
3921                                 m_freem(m);
3922                                 *m_head = NULL;
3923                                 return (error);
3924                         }
3925                 }
3926                 if (m->m_flags & M_LASTFRAG)
3927                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3928                 else if (m->m_flags & M_FRAG)
3929                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3930         }
3931
3932         if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
3933             sc->bge_forced_collapse > 0 &&
3934             (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
3935                 /*
3936                  * Forcedly collapse mbuf chains to overcome hardware
3937                  * limitation which only support a single outstanding
3938                  * DMA read operation.
3939                  */
3940                 if (sc->bge_forced_collapse == 1)
3941                         m = m_defrag(m, M_DONTWAIT);
3942                 else
3943                         m = m_collapse(m, M_DONTWAIT, sc->bge_forced_collapse);
3944                 if (m == NULL)
3945                         m = *m_head;
3946                 *m_head = m;
3947         }
3948
3949         map = sc->bge_cdata.bge_tx_dmamap[idx];
3950         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
3951             &nsegs, BUS_DMA_NOWAIT);
3952         if (error == EFBIG) {
3953                 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW);
3954                 if (m == NULL) {
3955                         m_freem(*m_head);
3956                         *m_head = NULL;
3957                         return (ENOBUFS);
3958                 }
3959                 *m_head = m;
3960                 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
3961                     m, segs, &nsegs, BUS_DMA_NOWAIT);
3962                 if (error) {
3963                         m_freem(m);
3964                         *m_head = NULL;
3965                         return (error);
3966                 }
3967         } else if (error != 0)
3968                 return (error);
3969
3970         /* Check if we have enough free send BDs. */
3971         if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
3972                 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
3973                 return (ENOBUFS);
3974         }
3975
3976         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3977
3978 #if __FreeBSD_version > 700022
3979         if (m->m_flags & M_VLANTAG) {
3980                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
3981                 vlan_tag = m->m_pkthdr.ether_vtag;
3982         }
3983 #else
3984         {
3985                 struct m_tag            *mtag;
3986
3987                 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) {
3988                         csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
3989                         vlan_tag = VLAN_TAG_VALUE(mtag);
3990                 }
3991         }
3992 #endif
3993         for (i = 0; ; i++) {
3994                 d = &sc->bge_ldata.bge_tx_ring[idx];
3995                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3996                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3997                 d->bge_len = segs[i].ds_len;
3998                 d->bge_flags = csum_flags;
3999                 d->bge_vlan_tag = vlan_tag;
4000                 d->bge_mss = mss;
4001                 if (i == nsegs - 1)
4002                         break;
4003                 BGE_INC(idx, BGE_TX_RING_CNT);
4004         }
4005
4006         /* Mark the last segment as end of packet... */
4007         d->bge_flags |= BGE_TXBDFLAG_END;
4008
4009         /*
4010          * Insure that the map for this transmission
4011          * is placed at the array index of the last descriptor
4012          * in this chain.
4013          */
4014         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
4015         sc->bge_cdata.bge_tx_dmamap[idx] = map;
4016         sc->bge_cdata.bge_tx_chain[idx] = m;
4017         sc->bge_txcnt += nsegs;
4018
4019         BGE_INC(idx, BGE_TX_RING_CNT);
4020         *txidx = idx;
4021
4022         return (0);
4023 }
4024
4025 /*
4026  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4027  * to the mbuf data regions directly in the transmit descriptors.
4028  */
4029 static void
4030 bge_start_locked(struct ifnet *ifp)
4031 {
4032         struct bge_softc *sc;
4033         struct mbuf *m_head;
4034         uint32_t prodidx;
4035         int count;
4036
4037         sc = ifp->if_softc;
4038         BGE_LOCK_ASSERT(sc);
4039
4040         if (!sc->bge_link ||
4041             (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4042             IFF_DRV_RUNNING)
4043                 return;
4044
4045         prodidx = sc->bge_tx_prodidx;
4046
4047         for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
4048                 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
4049                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4050                         break;
4051                 }
4052                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
4053                 if (m_head == NULL)
4054                         break;
4055
4056                 /*
4057                  * XXX
4058                  * The code inside the if() block is never reached since we
4059                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
4060                  * requests to checksum TCP/UDP in a fragmented packet.
4061                  *
4062                  * XXX
4063                  * safety overkill.  If this is a fragmented packet chain
4064                  * with delayed TCP/UDP checksums, then only encapsulate
4065                  * it if we have enough descriptors to handle the entire
4066                  * chain at once.
4067                  * (paranoia -- may not actually be needed)
4068                  */
4069                 if (m_head->m_flags & M_FIRSTFRAG &&
4070                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
4071                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
4072                             m_head->m_pkthdr.csum_data + 16) {
4073                                 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4074                                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4075                                 break;
4076                         }
4077                 }
4078
4079                 /*
4080                  * Pack the data into the transmit ring. If we
4081                  * don't have room, set the OACTIVE flag and wait
4082                  * for the NIC to drain the ring.
4083                  */
4084                 if (bge_encap(sc, &m_head, &prodidx)) {
4085                         if (m_head == NULL)
4086                                 break;
4087                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4088                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4089                         break;
4090                 }
4091                 ++count;
4092
4093                 /*
4094                  * If there's a BPF listener, bounce a copy of this frame
4095                  * to him.
4096                  */
4097 #ifdef ETHER_BPF_MTAP
4098                 ETHER_BPF_MTAP(ifp, m_head);
4099 #else
4100                 BPF_MTAP(ifp, m_head);
4101 #endif
4102         }
4103
4104         if (count > 0) {
4105                 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4106                     sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
4107                 /* Transmit. */
4108                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4109                 /* 5700 b2 errata */
4110                 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
4111                         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4112
4113                 sc->bge_tx_prodidx = prodidx;
4114
4115                 /*
4116                  * Set a timeout in case the chip goes out to lunch.
4117                  */
4118                 sc->bge_timer = 5;
4119         }
4120 }
4121
4122 /*
4123  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4124  * to the mbuf data regions directly in the transmit descriptors.
4125  */
4126 static void
4127 bge_start(struct ifnet *ifp)
4128 {
4129         struct bge_softc *sc;
4130
4131         sc = ifp->if_softc;
4132         BGE_LOCK(sc);
4133         bge_start_locked(ifp);
4134         BGE_UNLOCK(sc);
4135 }
4136
4137 static void
4138 bge_init_locked(struct bge_softc *sc)
4139 {
4140         struct ifnet *ifp;
4141         uint16_t *m;
4142
4143         BGE_LOCK_ASSERT(sc);
4144
4145         ifp = sc->bge_ifp;
4146
4147         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4148                 return;
4149
4150         /* Cancel pending I/O and flush buffers. */
4151         bge_stop(sc);
4152
4153         bge_stop_fw(sc);
4154         bge_sig_pre_reset(sc, BGE_RESET_START);
4155         bge_reset(sc);
4156         bge_sig_legacy(sc, BGE_RESET_START);
4157         bge_sig_post_reset(sc, BGE_RESET_START);
4158
4159         bge_chipinit(sc);
4160
4161         /*
4162          * Init the various state machines, ring
4163          * control blocks and firmware.
4164          */
4165         if (bge_blockinit(sc)) {
4166                 device_printf(sc->bge_dev, "initialization failure\n");
4167                 return;
4168         }
4169
4170         ifp = sc->bge_ifp;
4171
4172         /* Specify MTU. */
4173         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
4174             ETHER_HDR_LEN + ETHER_CRC_LEN +
4175             (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
4176
4177         /* Load our MAC address. */
4178         m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
4179         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
4180         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
4181
4182         /* Program promiscuous mode. */
4183         bge_setpromisc(sc);
4184
4185         /* Program multicast filter. */
4186         bge_setmulti(sc);
4187
4188         /* Program VLAN tag stripping. */
4189         bge_setvlan(sc);
4190
4191         /* Init RX ring. */
4192         if (bge_init_rx_ring_std(sc) != 0) {
4193                 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
4194                 bge_stop(sc);
4195                 return;
4196         }
4197
4198         /*
4199          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
4200          * memory to insure that the chip has in fact read the first
4201          * entry of the ring.
4202          */
4203         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
4204                 uint32_t                v, i;
4205                 for (i = 0; i < 10; i++) {
4206                         DELAY(20);
4207                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
4208                         if (v == (MCLBYTES - ETHER_ALIGN))
4209                                 break;
4210                 }
4211                 if (i == 10)
4212                         device_printf (sc->bge_dev,
4213                             "5705 A0 chip failed to load RX ring\n");
4214         }
4215
4216         /* Init jumbo RX ring. */
4217         if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
4218             (MCLBYTES - ETHER_ALIGN)) {
4219                 if (bge_init_rx_ring_jumbo(sc) != 0) {
4220                         device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
4221                         bge_stop(sc);
4222                         return;
4223                 }
4224         }
4225
4226         /* Init our RX return ring index. */
4227         sc->bge_rx_saved_considx = 0;
4228
4229         /* Init our RX/TX stat counters. */
4230         sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
4231
4232         /* Init TX ring. */
4233         bge_init_tx_ring(sc);
4234
4235         /* Turn on transmitter. */
4236         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
4237
4238         /* Turn on receiver. */
4239         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4240
4241         /* Tell firmware we're alive. */
4242         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4243
4244 #ifdef DEVICE_POLLING
4245         /* Disable interrupts if we are polling. */
4246         if (ifp->if_capenable & IFCAP_POLLING) {
4247                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4248                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4249                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4250         } else
4251 #endif
4252
4253         /* Enable host interrupts. */
4254         {
4255         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
4256         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4257         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4258         }
4259
4260         bge_ifmedia_upd_locked(ifp);
4261
4262         ifp->if_drv_flags |= IFF_DRV_RUNNING;
4263         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4264
4265         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4266 }
4267
4268 static void
4269 bge_init(void *xsc)
4270 {
4271         struct bge_softc *sc = xsc;
4272
4273         BGE_LOCK(sc);
4274         bge_init_locked(sc);
4275         BGE_UNLOCK(sc);
4276 }
4277
4278 /*
4279  * Set media options.
4280  */
4281 static int
4282 bge_ifmedia_upd(struct ifnet *ifp)
4283 {
4284         struct bge_softc *sc = ifp->if_softc;
4285         int res;
4286
4287         BGE_LOCK(sc);
4288         res = bge_ifmedia_upd_locked(ifp);
4289         BGE_UNLOCK(sc);
4290
4291         return (res);
4292 }
4293
4294 static int
4295 bge_ifmedia_upd_locked(struct ifnet *ifp)
4296 {
4297         struct bge_softc *sc = ifp->if_softc;
4298         struct mii_data *mii;
4299         struct mii_softc *miisc;
4300         struct ifmedia *ifm;
4301
4302         BGE_LOCK_ASSERT(sc);
4303
4304         ifm = &sc->bge_ifmedia;
4305
4306         /* If this is a 1000baseX NIC, enable the TBI port. */
4307         if (sc->bge_flags & BGE_FLAG_TBI) {
4308                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
4309                         return (EINVAL);
4310                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
4311                 case IFM_AUTO:
4312                         /*
4313                          * The BCM5704 ASIC appears to have a special
4314                          * mechanism for programming the autoneg
4315                          * advertisement registers in TBI mode.
4316                          */
4317                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4318                                 uint32_t sgdig;
4319                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
4320                                 if (sgdig & BGE_SGDIGSTS_DONE) {
4321                                         CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
4322                                         sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
4323                                         sgdig |= BGE_SGDIGCFG_AUTO |
4324                                             BGE_SGDIGCFG_PAUSE_CAP |
4325                                             BGE_SGDIGCFG_ASYM_PAUSE;
4326                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG,
4327                                             sgdig | BGE_SGDIGCFG_SEND);
4328                                         DELAY(5);
4329                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
4330                                 }
4331                         }
4332                         break;
4333                 case IFM_1000_SX:
4334                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
4335                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
4336                                     BGE_MACMODE_HALF_DUPLEX);
4337                         } else {
4338                                 BGE_SETBIT(sc, BGE_MAC_MODE,
4339                                     BGE_MACMODE_HALF_DUPLEX);
4340                         }
4341                         break;
4342                 default:
4343                         return (EINVAL);
4344                 }
4345                 return (0);
4346         }
4347
4348         sc->bge_link_evt++;
4349         mii = device_get_softc(sc->bge_miibus);
4350         if (mii->mii_instance)
4351                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4352                         mii_phy_reset(miisc);
4353         mii_mediachg(mii);
4354
4355         /*
4356          * Force an interrupt so that we will call bge_link_upd
4357          * if needed and clear any pending link state attention.
4358          * Without this we are not getting any further interrupts
4359          * for link state changes and thus will not UP the link and
4360          * not be able to send in bge_start_locked. The only
4361          * way to get things working was to receive a packet and
4362          * get an RX intr.
4363          * bge_tick should help for fiber cards and we might not
4364          * need to do this here if BGE_FLAG_TBI is set but as
4365          * we poll for fiber anyway it should not harm.
4366          */
4367         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4368             sc->bge_flags & BGE_FLAG_5788)
4369                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4370         else
4371                 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4372
4373         return (0);
4374 }
4375
4376 /*
4377  * Report current media status.
4378  */
4379 static void
4380 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4381 {
4382         struct bge_softc *sc = ifp->if_softc;
4383         struct mii_data *mii;
4384
4385         BGE_LOCK(sc);
4386
4387         if (sc->bge_flags & BGE_FLAG_TBI) {
4388                 ifmr->ifm_status = IFM_AVALID;
4389                 ifmr->ifm_active = IFM_ETHER;
4390                 if (CSR_READ_4(sc, BGE_MAC_STS) &
4391                     BGE_MACSTAT_TBI_PCS_SYNCHED)
4392                         ifmr->ifm_status |= IFM_ACTIVE;
4393                 else {
4394                         ifmr->ifm_active |= IFM_NONE;
4395                         BGE_UNLOCK(sc);
4396                         return;
4397                 }
4398                 ifmr->ifm_active |= IFM_1000_SX;
4399                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
4400                         ifmr->ifm_active |= IFM_HDX;
4401                 else
4402                         ifmr->ifm_active |= IFM_FDX;
4403                 BGE_UNLOCK(sc);
4404                 return;
4405         }
4406
4407         mii = device_get_softc(sc->bge_miibus);
4408         mii_pollstat(mii);
4409         ifmr->ifm_active = mii->mii_media_active;
4410         ifmr->ifm_status = mii->mii_media_status;
4411
4412         BGE_UNLOCK(sc);
4413 }
4414
4415 static int
4416 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
4417 {
4418         struct bge_softc *sc = ifp->if_softc;
4419         struct ifreq *ifr = (struct ifreq *) data;
4420         struct mii_data *mii;
4421         int flags, mask, error = 0;
4422
4423         switch (command) {
4424         case SIOCSIFMTU:
4425                 if (ifr->ifr_mtu < ETHERMIN ||
4426                     ((BGE_IS_JUMBO_CAPABLE(sc)) &&
4427                     ifr->ifr_mtu > BGE_JUMBO_MTU) ||
4428                     ((!BGE_IS_JUMBO_CAPABLE(sc)) &&
4429                     ifr->ifr_mtu > ETHERMTU))
4430                         error = EINVAL;
4431                 else if (ifp->if_mtu != ifr->ifr_mtu) {
4432                         ifp->if_mtu = ifr->ifr_mtu;
4433                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4434                         bge_init(sc);
4435                 }
4436                 break;
4437         case SIOCSIFFLAGS:
4438                 BGE_LOCK(sc);
4439                 if (ifp->if_flags & IFF_UP) {
4440                         /*
4441                          * If only the state of the PROMISC flag changed,
4442                          * then just use the 'set promisc mode' command
4443                          * instead of reinitializing the entire NIC. Doing
4444                          * a full re-init means reloading the firmware and
4445                          * waiting for it to start up, which may take a
4446                          * second or two.  Similarly for ALLMULTI.
4447                          */
4448                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4449                                 flags = ifp->if_flags ^ sc->bge_if_flags;
4450                                 if (flags & IFF_PROMISC)
4451                                         bge_setpromisc(sc);
4452                                 if (flags & IFF_ALLMULTI)
4453                                         bge_setmulti(sc);
4454                         } else
4455                                 bge_init_locked(sc);
4456                 } else {
4457                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4458                                 bge_stop(sc);
4459                         }
4460                 }
4461                 sc->bge_if_flags = ifp->if_flags;
4462                 BGE_UNLOCK(sc);
4463                 error = 0;
4464                 break;
4465         case SIOCADDMULTI:
4466         case SIOCDELMULTI:
4467                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4468                         BGE_LOCK(sc);
4469                         bge_setmulti(sc);
4470                         BGE_UNLOCK(sc);
4471                         error = 0;
4472                 }
4473                 break;
4474         case SIOCSIFMEDIA:
4475         case SIOCGIFMEDIA:
4476                 if (sc->bge_flags & BGE_FLAG_TBI) {
4477                         error = ifmedia_ioctl(ifp, ifr,
4478                             &sc->bge_ifmedia, command);
4479                 } else {
4480                         mii = device_get_softc(sc->bge_miibus);
4481                         error = ifmedia_ioctl(ifp, ifr,
4482                             &mii->mii_media, command);
4483                 }
4484                 break;
4485         case SIOCSIFCAP:
4486                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
4487 #ifdef DEVICE_POLLING
4488                 if (mask & IFCAP_POLLING) {
4489                         if (ifr->ifr_reqcap & IFCAP_POLLING) {
4490                                 error = ether_poll_register(bge_poll, ifp);
4491                                 if (error)
4492                                         return (error);
4493                                 BGE_LOCK(sc);
4494                                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4495                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4496                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4497                                 ifp->if_capenable |= IFCAP_POLLING;
4498                                 BGE_UNLOCK(sc);
4499                         } else {
4500                                 error = ether_poll_deregister(ifp);
4501                                 /* Enable interrupt even in error case */
4502                                 BGE_LOCK(sc);
4503                                 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
4504                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4505                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4506                                 ifp->if_capenable &= ~IFCAP_POLLING;
4507                                 BGE_UNLOCK(sc);
4508                         }
4509                 }
4510 #endif
4511                 if (mask & IFCAP_HWCSUM) {
4512                         ifp->if_capenable ^= IFCAP_HWCSUM;
4513                         if (IFCAP_HWCSUM & ifp->if_capenable &&
4514                             IFCAP_HWCSUM & ifp->if_capabilities)
4515                                 ifp->if_hwassist |= BGE_CSUM_FEATURES;
4516                         else
4517                                 ifp->if_hwassist &= ~BGE_CSUM_FEATURES;
4518                 }
4519
4520                 if ((mask & IFCAP_TSO4) != 0 &&
4521                     (ifp->if_capabilities & IFCAP_TSO4) != 0) {
4522                         ifp->if_capenable ^= IFCAP_TSO4;
4523                         if ((ifp->if_capenable & IFCAP_TSO4) != 0)
4524                                 ifp->if_hwassist |= CSUM_TSO;
4525                         else
4526                                 ifp->if_hwassist &= ~CSUM_TSO;
4527                 }
4528
4529                 if (mask & IFCAP_VLAN_MTU) {
4530                         ifp->if_capenable ^= IFCAP_VLAN_MTU;
4531                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4532                         bge_init(sc);
4533                 }
4534
4535                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
4536                     (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
4537                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
4538                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
4539                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
4540                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
4541                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
4542                                 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
4543                         BGE_LOCK(sc);
4544                         bge_setvlan(sc);
4545                         BGE_UNLOCK(sc);
4546                 }
4547 #ifdef VLAN_CAPABILITIES
4548                 VLAN_CAPABILITIES(ifp);
4549 #endif
4550                 break;
4551         default:
4552                 error = ether_ioctl(ifp, command, data);
4553                 break;
4554         }
4555
4556         return (error);
4557 }
4558
4559 static void
4560 bge_watchdog(struct bge_softc *sc)
4561 {
4562         struct ifnet *ifp;
4563
4564         BGE_LOCK_ASSERT(sc);
4565
4566         if (sc->bge_timer == 0 || --sc->bge_timer)
4567                 return;
4568
4569         ifp = sc->bge_ifp;
4570
4571         if_printf(ifp, "watchdog timeout -- resetting\n");
4572
4573         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4574         bge_init_locked(sc);
4575
4576         ifp->if_oerrors++;
4577 }
4578
4579 /*
4580  * Stop the adapter and free any mbufs allocated to the
4581  * RX and TX lists.
4582  */
4583 static void
4584 bge_stop(struct bge_softc *sc)
4585 {
4586         struct ifnet *ifp;
4587
4588         BGE_LOCK_ASSERT(sc);
4589
4590         ifp = sc->bge_ifp;
4591
4592         callout_stop(&sc->bge_stat_ch);
4593
4594         /* Disable host interrupts. */
4595         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4596         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4597
4598         /*
4599          * Tell firmware we're shutting down.
4600          */
4601         bge_stop_fw(sc);
4602         bge_sig_pre_reset(sc, BGE_RESET_STOP);
4603
4604         /*
4605          * Disable all of the receiver blocks.
4606          */
4607         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4608         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
4609         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
4610         if (!(BGE_IS_5705_PLUS(sc)))
4611                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
4612         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
4613         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
4614         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
4615
4616         /*
4617          * Disable all of the transmit blocks.
4618          */
4619         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
4620         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
4621         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
4622         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
4623         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
4624         if (!(BGE_IS_5705_PLUS(sc)))
4625                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
4626         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
4627
4628         /*
4629          * Shut down all of the memory managers and related
4630          * state machines.
4631          */
4632         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
4633         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
4634         if (!(BGE_IS_5705_PLUS(sc)))
4635                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
4636         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
4637         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
4638         if (!(BGE_IS_5705_PLUS(sc))) {
4639                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
4640                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4641         }
4642
4643         bge_reset(sc);
4644         bge_sig_legacy(sc, BGE_RESET_STOP);
4645         bge_sig_post_reset(sc, BGE_RESET_STOP);
4646
4647         /*
4648          * Keep the ASF firmware running if up.
4649          */
4650         if (sc->bge_asf_mode & ASF_STACKUP)
4651                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4652         else
4653                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4654
4655         /* Free the RX lists. */
4656         bge_free_rx_ring_std(sc);
4657
4658         /* Free jumbo RX list. */
4659         if (BGE_IS_JUMBO_CAPABLE(sc))
4660                 bge_free_rx_ring_jumbo(sc);
4661
4662         /* Free TX buffers. */
4663         bge_free_tx_ring(sc);
4664
4665         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
4666
4667         /* Clear MAC's link state (PHY may still have link UP). */
4668         if (bootverbose && sc->bge_link)
4669                 if_printf(sc->bge_ifp, "link DOWN\n");
4670         sc->bge_link = 0;
4671
4672         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4673 }
4674
4675 /*
4676  * Stop all chip I/O so that the kernel's probe routines don't
4677  * get confused by errant DMAs when rebooting.
4678  */
4679 static int
4680 bge_shutdown(device_t dev)
4681 {
4682         struct bge_softc *sc;
4683
4684         sc = device_get_softc(dev);
4685         BGE_LOCK(sc);
4686         bge_stop(sc);
4687         bge_reset(sc);
4688         BGE_UNLOCK(sc);
4689
4690         return (0);
4691 }
4692
4693 static int
4694 bge_suspend(device_t dev)
4695 {
4696         struct bge_softc *sc;
4697
4698         sc = device_get_softc(dev);
4699         BGE_LOCK(sc);
4700         bge_stop(sc);
4701         BGE_UNLOCK(sc);
4702
4703         return (0);
4704 }
4705
4706 static int
4707 bge_resume(device_t dev)
4708 {
4709         struct bge_softc *sc;
4710         struct ifnet *ifp;
4711
4712         sc = device_get_softc(dev);
4713         BGE_LOCK(sc);
4714         ifp = sc->bge_ifp;
4715         if (ifp->if_flags & IFF_UP) {
4716                 bge_init_locked(sc);
4717                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4718                         bge_start_locked(ifp);
4719         }
4720         BGE_UNLOCK(sc);
4721
4722         return (0);
4723 }
4724
4725 static void
4726 bge_link_upd(struct bge_softc *sc)
4727 {
4728         struct mii_data *mii;
4729         uint32_t link, status;
4730
4731         BGE_LOCK_ASSERT(sc);
4732
4733         /* Clear 'pending link event' flag. */
4734         sc->bge_link_evt = 0;
4735
4736         /*
4737          * Process link state changes.
4738          * Grrr. The link status word in the status block does
4739          * not work correctly on the BCM5700 rev AX and BX chips,
4740          * according to all available information. Hence, we have
4741          * to enable MII interrupts in order to properly obtain
4742          * async link changes. Unfortunately, this also means that
4743          * we have to read the MAC status register to detect link
4744          * changes, thereby adding an additional register access to
4745          * the interrupt handler.
4746          *
4747          * XXX: perhaps link state detection procedure used for
4748          * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
4749          */
4750
4751         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4752             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
4753                 status = CSR_READ_4(sc, BGE_MAC_STS);
4754                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
4755                         mii = device_get_softc(sc->bge_miibus);
4756                         mii_pollstat(mii);
4757                         if (!sc->bge_link &&
4758                             mii->mii_media_status & IFM_ACTIVE &&
4759                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4760                                 sc->bge_link++;
4761                                 if (bootverbose)
4762                                         if_printf(sc->bge_ifp, "link UP\n");
4763                         } else if (sc->bge_link &&
4764                             (!(mii->mii_media_status & IFM_ACTIVE) ||
4765                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4766                                 sc->bge_link = 0;
4767                                 if (bootverbose)
4768                                         if_printf(sc->bge_ifp, "link DOWN\n");
4769                         }
4770
4771                         /* Clear the interrupt. */
4772                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
4773                             BGE_EVTENB_MI_INTERRUPT);
4774                         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4775                         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
4776                             BRGPHY_INTRS);
4777                 }
4778                 return;
4779         }
4780
4781         if (sc->bge_flags & BGE_FLAG_TBI) {
4782                 status = CSR_READ_4(sc, BGE_MAC_STS);
4783                 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4784                         if (!sc->bge_link) {
4785                                 sc->bge_link++;
4786                                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
4787                                         BGE_CLRBIT(sc, BGE_MAC_MODE,
4788                                             BGE_MACMODE_TBI_SEND_CFGS);
4789                                 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4790                                 if (bootverbose)
4791                                         if_printf(sc->bge_ifp, "link UP\n");
4792                                 if_link_state_change(sc->bge_ifp,
4793                                     LINK_STATE_UP);
4794                         }
4795                 } else if (sc->bge_link) {
4796                         sc->bge_link = 0;
4797                         if (bootverbose)
4798                                 if_printf(sc->bge_ifp, "link DOWN\n");
4799                         if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
4800                 }
4801         } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
4802                 /*
4803                  * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
4804                  * in status word always set. Workaround this bug by reading
4805                  * PHY link status directly.
4806                  */
4807                 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
4808
4809                 if (link != sc->bge_link ||
4810                     sc->bge_asicrev == BGE_ASICREV_BCM5700) {
4811                         mii = device_get_softc(sc->bge_miibus);
4812                         mii_pollstat(mii);
4813                         if (!sc->bge_link &&
4814                             mii->mii_media_status & IFM_ACTIVE &&
4815                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4816                                 sc->bge_link++;
4817                                 if (bootverbose)
4818                                         if_printf(sc->bge_ifp, "link UP\n");
4819                         } else if (sc->bge_link &&
4820                             (!(mii->mii_media_status & IFM_ACTIVE) ||
4821                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4822                                 sc->bge_link = 0;
4823                                 if (bootverbose)
4824                                         if_printf(sc->bge_ifp, "link DOWN\n");
4825                         }
4826                 }
4827         } else {
4828                 /*
4829                  * Discard link events for MII/GMII controllers
4830                  * if MI auto-polling is disabled.
4831                  */
4832         }
4833
4834         /* Clear the attention. */
4835         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4836             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4837             BGE_MACSTAT_LINK_CHANGED);
4838 }
4839
4840 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
4841         SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
4842             sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
4843             desc)
4844
4845 static void
4846 bge_add_sysctls(struct bge_softc *sc)
4847 {
4848         struct sysctl_ctx_list *ctx;
4849         struct sysctl_oid_list *children, *schildren;
4850         struct sysctl_oid *tree;
4851
4852         ctx = device_get_sysctl_ctx(sc->bge_dev);
4853         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
4854
4855 #ifdef BGE_REGISTER_DEBUG
4856         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
4857             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
4858             "Debug Information");
4859
4860         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
4861             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
4862             "Register Read");
4863
4864         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
4865             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
4866             "Memory Read");
4867
4868 #endif
4869
4870         /*
4871          * A common design characteristic for many Broadcom client controllers
4872          * is that they only support a single outstanding DMA read operation
4873          * on the PCIe bus. This means that it will take twice as long to fetch
4874          * a TX frame that is split into header and payload buffers as it does
4875          * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
4876          * these controllers, coalescing buffers to reduce the number of memory
4877          * reads is effective way to get maximum performance(about 940Mbps).
4878          * Without collapsing TX buffers the maximum TCP bulk transfer
4879          * performance is about 850Mbps. However forcing coalescing mbufs
4880          * consumes a lot of CPU cycles, so leave it off by default.
4881          */
4882         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
4883             CTLFLAG_RW, &sc->bge_forced_collapse, 0,
4884             "Number of fragmented TX buffers of a frame allowed before "
4885             "forced collapsing");
4886         resource_int_value(device_get_name(sc->bge_dev),
4887             device_get_unit(sc->bge_dev), "forced_collapse",
4888             &sc->bge_forced_collapse);
4889
4890         if (BGE_IS_5705_PLUS(sc))
4891                 return;
4892
4893         tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
4894             NULL, "BGE Statistics");
4895         schildren = children = SYSCTL_CHILDREN(tree);
4896         BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
4897             children, COSFramesDroppedDueToFilters,
4898             "FramesDroppedDueToFilters");
4899         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
4900             children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
4901         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
4902             children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
4903         BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
4904             children, nicNoMoreRxBDs, "NoMoreRxBDs");
4905         BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
4906             children, ifInDiscards, "InputDiscards");
4907         BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
4908             children, ifInErrors, "InputErrors");
4909         BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
4910             children, nicRecvThresholdHit, "RecvThresholdHit");
4911         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
4912             children, nicDmaReadQueueFull, "DmaReadQueueFull");
4913         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
4914             children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
4915         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
4916             children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
4917         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
4918             children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
4919         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
4920             children, nicRingStatusUpdate, "RingStatusUpdate");
4921         BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
4922             children, nicInterrupts, "Interrupts");
4923         BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
4924             children, nicAvoidedInterrupts, "AvoidedInterrupts");
4925         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
4926             children, nicSendThresholdHit, "SendThresholdHit");
4927
4928         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
4929             NULL, "BGE RX Statistics");
4930         children = SYSCTL_CHILDREN(tree);
4931         BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
4932             children, rxstats.ifHCInOctets, "Octets");
4933         BGE_SYSCTL_STAT(sc, ctx, "Fragments",
4934             children, rxstats.etherStatsFragments, "Fragments");
4935         BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
4936             children, rxstats.ifHCInUcastPkts, "UcastPkts");
4937         BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
4938             children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
4939         BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
4940             children, rxstats.dot3StatsFCSErrors, "FCSErrors");
4941         BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
4942             children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
4943         BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
4944             children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
4945         BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
4946             children, rxstats.xoffPauseFramesReceived,
4947             "xoffPauseFramesReceived");
4948         BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
4949             children, rxstats.macControlFramesReceived,
4950             "ControlFramesReceived");
4951         BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
4952             children, rxstats.xoffStateEntered, "xoffStateEntered");
4953         BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
4954             children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
4955         BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
4956             children, rxstats.etherStatsJabbers, "Jabbers");
4957         BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
4958             children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
4959         BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
4960             children, rxstats.inRangeLengthError, "inRangeLengthError");
4961         BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
4962             children, rxstats.outRangeLengthError, "outRangeLengthError");
4963
4964         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
4965             NULL, "BGE TX Statistics");
4966         children = SYSCTL_CHILDREN(tree);
4967         BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
4968             children, txstats.ifHCOutOctets, "Octets");
4969         BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
4970             children, txstats.etherStatsCollisions, "Collisions");
4971         BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
4972             children, txstats.outXonSent, "XonSent");
4973         BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
4974             children, txstats.outXoffSent, "XoffSent");
4975         BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
4976             children, txstats.flowControlDone, "flowControlDone");
4977         BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
4978             children, txstats.dot3StatsInternalMacTransmitErrors,
4979             "InternalMacTransmitErrors");
4980         BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
4981             children, txstats.dot3StatsSingleCollisionFrames,
4982             "SingleCollisionFrames");
4983         BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
4984             children, txstats.dot3StatsMultipleCollisionFrames,
4985             "MultipleCollisionFrames");
4986         BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
4987             children, txstats.dot3StatsDeferredTransmissions,
4988             "DeferredTransmissions");
4989         BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
4990             children, txstats.dot3StatsExcessiveCollisions,
4991             "ExcessiveCollisions");
4992         BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
4993             children, txstats.dot3StatsLateCollisions,
4994             "LateCollisions");
4995         BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
4996             children, txstats.ifHCOutUcastPkts, "UcastPkts");
4997         BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
4998             children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
4999         BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
5000             children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
5001         BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
5002             children, txstats.dot3StatsCarrierSenseErrors,
5003             "CarrierSenseErrors");
5004         BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
5005             children, txstats.ifOutDiscards, "Discards");
5006         BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
5007             children, txstats.ifOutErrors, "Errors");
5008 }
5009
5010 static int
5011 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
5012 {
5013         struct bge_softc *sc;
5014         uint32_t result;
5015         int offset;
5016
5017         sc = (struct bge_softc *)arg1;
5018         offset = arg2;
5019         result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
5020             offsetof(bge_hostaddr, bge_addr_lo));
5021         return (sysctl_handle_int(oidp, &result, 0, req));
5022 }
5023
5024 #ifdef BGE_REGISTER_DEBUG
5025 static int
5026 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
5027 {
5028         struct bge_softc *sc;
5029         uint16_t *sbdata;
5030         int error;
5031         int result;
5032         int i, j;
5033
5034         result = -1;
5035         error = sysctl_handle_int(oidp, &result, 0, req);
5036         if (error || (req->newptr == NULL))
5037                 return (error);
5038
5039         if (result == 1) {
5040                 sc = (struct bge_softc *)arg1;
5041
5042                 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
5043                 printf("Status Block:\n");
5044                 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) {
5045                         printf("%06x:", i);
5046                         for (j = 0; j < 8; j++) {
5047                                 printf(" %04x", sbdata[i]);
5048                                 i += 4;
5049                         }
5050                         printf("\n");
5051                 }
5052
5053                 printf("Registers:\n");
5054                 for (i = 0x800; i < 0xA00; ) {
5055                         printf("%06x:", i);
5056                         for (j = 0; j < 8; j++) {
5057                                 printf(" %08x", CSR_READ_4(sc, i));
5058                                 i += 4;
5059                         }
5060                         printf("\n");
5061                 }
5062
5063                 printf("Hardware Flags:\n");
5064                 if (BGE_IS_5755_PLUS(sc))
5065                         printf(" - 5755 Plus\n");
5066                 if (BGE_IS_575X_PLUS(sc))
5067                         printf(" - 575X Plus\n");
5068                 if (BGE_IS_5705_PLUS(sc))
5069                         printf(" - 5705 Plus\n");
5070                 if (BGE_IS_5714_FAMILY(sc))
5071                         printf(" - 5714 Family\n");
5072                 if (BGE_IS_5700_FAMILY(sc))
5073                         printf(" - 5700 Family\n");
5074                 if (sc->bge_flags & BGE_FLAG_JUMBO)
5075                         printf(" - Supports Jumbo Frames\n");
5076                 if (sc->bge_flags & BGE_FLAG_PCIX)
5077                         printf(" - PCI-X Bus\n");
5078                 if (sc->bge_flags & BGE_FLAG_PCIE)
5079                         printf(" - PCI Express Bus\n");
5080                 if (sc->bge_flags & BGE_FLAG_NO_3LED)
5081                         printf(" - No 3 LEDs\n");
5082                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
5083                         printf(" - RX Alignment Bug\n");
5084         }
5085
5086         return (error);
5087 }
5088
5089 static int
5090 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5091 {
5092         struct bge_softc *sc;
5093         int error;
5094         uint16_t result;
5095         uint32_t val;
5096
5097         result = -1;
5098         error = sysctl_handle_int(oidp, &result, 0, req);
5099         if (error || (req->newptr == NULL))
5100                 return (error);
5101
5102         if (result < 0x8000) {
5103                 sc = (struct bge_softc *)arg1;
5104                 val = CSR_READ_4(sc, result);
5105                 printf("reg 0x%06X = 0x%08X\n", result, val);
5106         }
5107
5108         return (error);
5109 }
5110
5111 static int
5112 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
5113 {
5114         struct bge_softc *sc;
5115         int error;
5116         uint16_t result;
5117         uint32_t val;
5118
5119         result = -1;
5120         error = sysctl_handle_int(oidp, &result, 0, req);
5121         if (error || (req->newptr == NULL))
5122                 return (error);
5123
5124         if (result < 0x8000) {
5125                 sc = (struct bge_softc *)arg1;
5126                 val = bge_readmem_ind(sc, result);
5127                 printf("mem 0x%06X = 0x%08X\n", result, val);
5128         }
5129
5130         return (error);
5131 }
5132 #endif
5133
5134 static int
5135 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
5136 {
5137
5138         if (sc->bge_flags & BGE_FLAG_EADDR)
5139                 return (1);
5140
5141 #ifdef __sparc64__
5142         OF_getetheraddr(sc->bge_dev, ether_addr);
5143         return (0);
5144 #endif
5145         return (1);
5146 }
5147
5148 static int
5149 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
5150 {
5151         uint32_t mac_addr;
5152
5153         mac_addr = bge_readmem_ind(sc, 0x0c14);
5154         if ((mac_addr >> 16) == 0x484b) {
5155                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
5156                 ether_addr[1] = (uint8_t)mac_addr;
5157                 mac_addr = bge_readmem_ind(sc, 0x0c18);
5158                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
5159                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
5160                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
5161                 ether_addr[5] = (uint8_t)mac_addr;
5162                 return (0);
5163         }
5164         return (1);
5165 }
5166
5167 static int
5168 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
5169 {
5170         int mac_offset = BGE_EE_MAC_OFFSET;
5171
5172         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
5173                 mac_offset = BGE_EE_MAC_OFFSET_5906;
5174
5175         return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
5176             ETHER_ADDR_LEN));
5177 }
5178
5179 static int
5180 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
5181 {
5182
5183         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
5184                 return (1);
5185
5186         return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
5187            ETHER_ADDR_LEN));
5188 }
5189
5190 static int
5191 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
5192 {
5193         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
5194                 /* NOTE: Order is critical */
5195                 bge_get_eaddr_fw,
5196                 bge_get_eaddr_mem,
5197                 bge_get_eaddr_nvram,
5198                 bge_get_eaddr_eeprom,
5199                 NULL
5200         };
5201         const bge_eaddr_fcn_t *func;
5202
5203         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
5204                 if ((*func)(sc, eaddr) == 0)
5205                         break;
5206         }
5207         return (*func == NULL ? ENXIO : 0);
5208 }