sys/dev/bge/if_bge.c

   1 /*-
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/cdefs.h>
  35 __FBSDID("$FreeBSD$");
  36
  37 /*
  38  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  39  *
  40  * The Broadcom BCM5700 is based on technology originally developed by
  41  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  42  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  43  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  44  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  45  * frames, highly configurable RX filtering, and 16 RX and TX queues
  46  * (which, along with RX filter rules, can be used for QOS applications).
  47  * Other features, such as TCP segmentation, may be available as part
  48  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  49  * firmware images can be stored in hardware and need not be compiled
  50  * into the driver.
  51  *
  52  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  53  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  54  *
  55  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  56  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  57  * does not support external SSRAM.
  58  *
  59  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  60  * brand name, which is functionally similar but lacks PCI-X support.
  61  *
  62  * Without external SSRAM, you can only have at most 4 TX rings,
  63  * and the use of the mini RX ring is disabled. This seems to imply
  64  * that these features are simply not available on the BCM5701. As a
  65  * result, this driver does not implement any support for the mini RX
  66  * ring.
  67  */
  68
  69 #ifdef HAVE_KERNEL_OPTION_HEADERS
  70 #include "opt_device_polling.h"
  71 #endif
  72
  73 #include <sys/param.h>
  74 #include <sys/endian.h>
  75 #include <sys/systm.h>
  76 #include <sys/sockio.h>
  77 #include <sys/mbuf.h>
  78 #include <sys/malloc.h>
  79 #include <sys/kernel.h>
  80 #include <sys/module.h>
  81 #include <sys/socket.h>
  82 #include <sys/sysctl.h>
  83 #include <sys/taskqueue.h>
  84
  85 #include <net/if.h>
  86 #include <net/if_arp.h>
  87 #include <net/ethernet.h>
  88 #include <net/if_dl.h>
  89 #include <net/if_media.h>
  90
  91 #include <net/bpf.h>
  92
  93 #include <net/if_types.h>
  94 #include <net/if_vlan_var.h>
  95
  96 #include <netinet/in_systm.h>
  97 #include <netinet/in.h>
  98 #include <netinet/ip.h>
  99 #include <netinet/tcp.h>
 100
 101 #include <machine/bus.h>
 102 #include <machine/resource.h>
 103 #include <sys/bus.h>
 104 #include <sys/rman.h>
 105
 106 #include <dev/mii/mii.h>
 107 #include <dev/mii/miivar.h>
 108 #include "miidevs.h"
 109 #include <dev/mii/brgphyreg.h>
 110
 111 #ifdef __sparc64__
 112 #include <dev/ofw/ofw_bus.h>
 113 #include <dev/ofw/openfirm.h>
 114 #include <machine/ofw_machdep.h>
 115 #include <machine/ver.h>
 116 #endif
 117
 118 #include <dev/pci/pcireg.h>
 119 #include <dev/pci/pcivar.h>
 120
 121 #include <dev/bge/if_bgereg.h>
 122
 123 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 124 #define ETHER_MIN_NOPAD         (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
 125
 126 MODULE_DEPEND(bge, pci, 1, 1, 1);
 127 MODULE_DEPEND(bge, ether, 1, 1, 1);
 128 MODULE_DEPEND(bge, miibus, 1, 1, 1);
 129
 130 /* "device miibus" required.  See GENERIC if you get errors here. */
 131 #include "miibus_if.h"
 132
 133 /*
 134  * Various supported device vendors/types and their names. Note: the
 135  * spec seems to indicate that the hardware still has Alteon's vendor
 136  * ID burned into it, though it will always be overriden by the vendor
 137  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 138  */
 139 static const struct bge_type {
 140         uint16_t        bge_vid;
 141         uint16_t        bge_did;
 142 } bge_devs[] = {
 143         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5700 },
 144         { ALTEON_VENDORID,      ALTEON_DEVICEID_BCM5701 },
 145
 146         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1000 },
 147         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC1002 },
 148         { ALTIMA_VENDORID,      ALTIMA_DEVICE_AC9100 },
 149
 150         { APPLE_VENDORID,       APPLE_DEVICE_BCM5701 },
 151
 152         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5700 },
 153         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5701 },
 154         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702 },
 155         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702_ALT },
 156         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5702X },
 157         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703 },
 158         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703_ALT },
 159         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5703X },
 160         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704C },
 161         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S },
 162         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5704S_ALT },
 163         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705 },
 164         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705F },
 165         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705K },
 166         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M },
 167         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5705M_ALT },
 168         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714C },
 169         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5714S },
 170         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715 },
 171         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5715S },
 172         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5720 },
 173         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5721 },
 174         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5722 },
 175         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5723 },
 176         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750 },
 177         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5750M },
 178         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751 },
 179         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751F },
 180         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5751M },
 181         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752 },
 182         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5752M },
 183         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753 },
 184         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753F },
 185         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5753M },
 186         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754 },
 187         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5754M },
 188         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755 },
 189         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5755M },
 190         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5756 },
 191         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761 },
 192         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761E },
 193         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761S },
 194         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5761SE },
 195         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5764 },
 196         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780 },
 197         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5780S },
 198         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5781 },
 199         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5782 },
 200         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5784 },
 201         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785F },
 202         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5785G },
 203         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5786 },
 204         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787 },
 205         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787F },
 206         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5787M },
 207         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5788 },
 208         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5789 },
 209         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901 },
 210         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5901A2 },
 211         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5903M },
 212         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906 },
 213         { BCOM_VENDORID,        BCOM_DEVICEID_BCM5906M },
 214         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57760 },
 215         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57780 },
 216         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57788 },
 217         { BCOM_VENDORID,        BCOM_DEVICEID_BCM57790 },
 218
 219         { SK_VENDORID,          SK_DEVICEID_ALTIMA },
 220
 221         { TC_VENDORID,          TC_DEVICEID_3C996 },
 222
 223         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE4 },
 224         { FJTSU_VENDORID,       FJTSU_DEVICEID_PW008GE5 },
 225         { FJTSU_VENDORID,       FJTSU_DEVICEID_PP250450 },
 226
 227         { 0, 0 }
 228 };
 229
 230 static const struct bge_vendor {
 231         uint16_t        v_id;
 232         const char      *v_name;
 233 } bge_vendors[] = {
 234         { ALTEON_VENDORID,      "Alteon" },
 235         { ALTIMA_VENDORID,      "Altima" },
 236         { APPLE_VENDORID,       "Apple" },
 237         { BCOM_VENDORID,        "Broadcom" },
 238         { SK_VENDORID,          "SysKonnect" },
 239         { TC_VENDORID,          "3Com" },
 240         { FJTSU_VENDORID,       "Fujitsu" },
 241
 242         { 0, NULL }
 243 };
 244
 245 static const struct bge_revision {
 246         uint32_t        br_chipid;
 247         const char      *br_name;
 248 } bge_revisions[] = {
 249         { BGE_CHIPID_BCM5700_A0,        "BCM5700 A0" },
 250         { BGE_CHIPID_BCM5700_A1,        "BCM5700 A1" },
 251         { BGE_CHIPID_BCM5700_B0,        "BCM5700 B0" },
 252         { BGE_CHIPID_BCM5700_B1,        "BCM5700 B1" },
 253         { BGE_CHIPID_BCM5700_B2,        "BCM5700 B2" },
 254         { BGE_CHIPID_BCM5700_B3,        "BCM5700 B3" },
 255         { BGE_CHIPID_BCM5700_ALTIMA,    "BCM5700 Altima" },
 256         { BGE_CHIPID_BCM5700_C0,        "BCM5700 C0" },
 257         { BGE_CHIPID_BCM5701_A0,        "BCM5701 A0" },
 258         { BGE_CHIPID_BCM5701_B0,        "BCM5701 B0" },
 259         { BGE_CHIPID_BCM5701_B2,        "BCM5701 B2" },
 260         { BGE_CHIPID_BCM5701_B5,        "BCM5701 B5" },
 261         { BGE_CHIPID_BCM5703_A0,        "BCM5703 A0" },
 262         { BGE_CHIPID_BCM5703_A1,        "BCM5703 A1" },
 263         { BGE_CHIPID_BCM5703_A2,        "BCM5703 A2" },
 264         { BGE_CHIPID_BCM5703_A3,        "BCM5703 A3" },
 265         { BGE_CHIPID_BCM5703_B0,        "BCM5703 B0" },
 266         { BGE_CHIPID_BCM5704_A0,        "BCM5704 A0" },
 267         { BGE_CHIPID_BCM5704_A1,        "BCM5704 A1" },
 268         { BGE_CHIPID_BCM5704_A2,        "BCM5704 A2" },
 269         { BGE_CHIPID_BCM5704_A3,        "BCM5704 A3" },
 270         { BGE_CHIPID_BCM5704_B0,        "BCM5704 B0" },
 271         { BGE_CHIPID_BCM5705_A0,        "BCM5705 A0" },
 272         { BGE_CHIPID_BCM5705_A1,        "BCM5705 A1" },
 273         { BGE_CHIPID_BCM5705_A2,        "BCM5705 A2" },
 274         { BGE_CHIPID_BCM5705_A3,        "BCM5705 A3" },
 275         { BGE_CHIPID_BCM5750_A0,        "BCM5750 A0" },
 276         { BGE_CHIPID_BCM5750_A1,        "BCM5750 A1" },
 277         { BGE_CHIPID_BCM5750_A3,        "BCM5750 A3" },
 278         { BGE_CHIPID_BCM5750_B0,        "BCM5750 B0" },
 279         { BGE_CHIPID_BCM5750_B1,        "BCM5750 B1" },
 280         { BGE_CHIPID_BCM5750_C0,        "BCM5750 C0" },
 281         { BGE_CHIPID_BCM5750_C1,        "BCM5750 C1" },
 282         { BGE_CHIPID_BCM5750_C2,        "BCM5750 C2" },
 283         { BGE_CHIPID_BCM5714_A0,        "BCM5714 A0" },
 284         { BGE_CHIPID_BCM5752_A0,        "BCM5752 A0" },
 285         { BGE_CHIPID_BCM5752_A1,        "BCM5752 A1" },
 286         { BGE_CHIPID_BCM5752_A2,        "BCM5752 A2" },
 287         { BGE_CHIPID_BCM5714_B0,        "BCM5714 B0" },
 288         { BGE_CHIPID_BCM5714_B3,        "BCM5714 B3" },
 289         { BGE_CHIPID_BCM5715_A0,        "BCM5715 A0" },
 290         { BGE_CHIPID_BCM5715_A1,        "BCM5715 A1" },
 291         { BGE_CHIPID_BCM5715_A3,        "BCM5715 A3" },
 292         { BGE_CHIPID_BCM5755_A0,        "BCM5755 A0" },
 293         { BGE_CHIPID_BCM5755_A1,        "BCM5755 A1" },
 294         { BGE_CHIPID_BCM5755_A2,        "BCM5755 A2" },
 295         { BGE_CHIPID_BCM5722_A0,        "BCM5722 A0" },
 296         { BGE_CHIPID_BCM5761_A0,        "BCM5761 A0" },
 297         { BGE_CHIPID_BCM5761_A1,        "BCM5761 A1" },
 298         { BGE_CHIPID_BCM5784_A0,        "BCM5784 A0" },
 299         { BGE_CHIPID_BCM5784_A1,        "BCM5784 A1" },
 300         /* 5754 and 5787 share the same ASIC ID */
 301         { BGE_CHIPID_BCM5787_A0,        "BCM5754/5787 A0" },
 302         { BGE_CHIPID_BCM5787_A1,        "BCM5754/5787 A1" },
 303         { BGE_CHIPID_BCM5787_A2,        "BCM5754/5787 A2" },
 304         { BGE_CHIPID_BCM5906_A1,        "BCM5906 A1" },
 305         { BGE_CHIPID_BCM5906_A2,        "BCM5906 A2" },
 306         { BGE_CHIPID_BCM57780_A0,       "BCM57780 A0" },
 307         { BGE_CHIPID_BCM57780_A1,       "BCM57780 A1" },
 308
 309         { 0, NULL }
 310 };
 311
 312 /*
 313  * Some defaults for major revisions, so that newer steppings
 314  * that we don't know about have a shot at working.
 315  */
 316 static const struct bge_revision bge_majorrevs[] = {
 317         { BGE_ASICREV_BCM5700,          "unknown BCM5700" },
 318         { BGE_ASICREV_BCM5701,          "unknown BCM5701" },
 319         { BGE_ASICREV_BCM5703,          "unknown BCM5703" },
 320         { BGE_ASICREV_BCM5704,          "unknown BCM5704" },
 321         { BGE_ASICREV_BCM5705,          "unknown BCM5705" },
 322         { BGE_ASICREV_BCM5750,          "unknown BCM5750" },
 323         { BGE_ASICREV_BCM5714_A0,       "unknown BCM5714" },
 324         { BGE_ASICREV_BCM5752,          "unknown BCM5752" },
 325         { BGE_ASICREV_BCM5780,          "unknown BCM5780" },
 326         { BGE_ASICREV_BCM5714,          "unknown BCM5714" },
 327         { BGE_ASICREV_BCM5755,          "unknown BCM5755" },
 328         { BGE_ASICREV_BCM5761,          "unknown BCM5761" },
 329         { BGE_ASICREV_BCM5784,          "unknown BCM5784" },
 330         { BGE_ASICREV_BCM5785,          "unknown BCM5785" },
 331         /* 5754 and 5787 share the same ASIC ID */
 332         { BGE_ASICREV_BCM5787,          "unknown BCM5754/5787" },
 333         { BGE_ASICREV_BCM5906,          "unknown BCM5906" },
 334         { BGE_ASICREV_BCM57780,         "unknown BCM57780" },
 335
 336         { 0, NULL }
 337 };
 338
 339 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 340 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 341 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 342 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 343 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 344 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
 345
 346 const struct bge_revision * bge_lookup_rev(uint32_t);
 347 const struct bge_vendor * bge_lookup_vendor(uint16_t);
 348
 349 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
 350
 351 static int bge_probe(device_t);
 352 static int bge_attach(device_t);
 353 static int bge_detach(device_t);
 354 static int bge_suspend(device_t);
 355 static int bge_resume(device_t);
 356 static void bge_release_resources(struct bge_softc *);
 357 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 358 static int bge_dma_alloc(device_t);
 359 static void bge_dma_free(struct bge_softc *);
 360
 361 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
 362 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
 363 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
 364 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
 365 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
 366
 367 static void bge_txeof(struct bge_softc *, uint16_t);
 368 static int bge_rxeof(struct bge_softc *, uint16_t, int);
 369
 370 static void bge_asf_driver_up (struct bge_softc *);
 371 static void bge_tick(void *);
 372 static void bge_stats_update(struct bge_softc *);
 373 static void bge_stats_update_regs(struct bge_softc *);
 374 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
 375     uint16_t *);
 376 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
 377
 378 static void bge_intr(void *);
 379 static int bge_msi_intr(void *);
 380 static void bge_intr_task(void *, int);
 381 static void bge_start_locked(struct ifnet *);
 382 static void bge_start(struct ifnet *);
 383 static int bge_ioctl(struct ifnet *, u_long, caddr_t);
 384 static void bge_init_locked(struct bge_softc *);
 385 static void bge_init(void *);
 386 static void bge_stop(struct bge_softc *);
 387 static void bge_watchdog(struct bge_softc *);
 388 static int bge_shutdown(device_t);
 389 static int bge_ifmedia_upd_locked(struct ifnet *);
 390 static int bge_ifmedia_upd(struct ifnet *);
 391 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 392
 393 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
 394 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
 395
 396 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
 397 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
 398
 399 static void bge_setpromisc(struct bge_softc *);
 400 static void bge_setmulti(struct bge_softc *);
 401 static void bge_setvlan(struct bge_softc *);
 402
 403 static int bge_newbuf_std(struct bge_softc *, int);
 404 static int bge_newbuf_jumbo(struct bge_softc *, int);
 405 static int bge_init_rx_ring_std(struct bge_softc *);
 406 static void bge_free_rx_ring_std(struct bge_softc *);
 407 static int bge_init_rx_ring_jumbo(struct bge_softc *);
 408 static void bge_free_rx_ring_jumbo(struct bge_softc *);
 409 static void bge_free_tx_ring(struct bge_softc *);
 410 static int bge_init_tx_ring(struct bge_softc *);
 411
 412 static int bge_chipinit(struct bge_softc *);
 413 static int bge_blockinit(struct bge_softc *);
 414
 415 static int bge_has_eaddr(struct bge_softc *);
 416 static uint32_t bge_readmem_ind(struct bge_softc *, int);
 417 static void bge_writemem_ind(struct bge_softc *, int, int);
 418 static void bge_writembx(struct bge_softc *, int, int);
 419 #ifdef notdef
 420 static uint32_t bge_readreg_ind(struct bge_softc *, int);
 421 #endif
 422 static void bge_writemem_direct(struct bge_softc *, int, int);
 423 static void bge_writereg_ind(struct bge_softc *, int, int);
 424 static void bge_set_max_readrq(struct bge_softc *);
 425
 426 static int bge_miibus_readreg(device_t, int, int);
 427 static int bge_miibus_writereg(device_t, int, int, int);
 428 static void bge_miibus_statchg(device_t);
 429 #ifdef DEVICE_POLLING
 430 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 431 #endif
 432
 433 #define BGE_RESET_START 1
 434 #define BGE_RESET_STOP  2
 435 static void bge_sig_post_reset(struct bge_softc *, int);
 436 static void bge_sig_legacy(struct bge_softc *, int);
 437 static void bge_sig_pre_reset(struct bge_softc *, int);
 438 static int bge_reset(struct bge_softc *);
 439 static void bge_link_upd(struct bge_softc *);
 440
 441 /*
 442  * The BGE_REGISTER_DEBUG option is only for low-level debugging.  It may
 443  * leak information to untrusted users.  It is also known to cause alignment
 444  * traps on certain architectures.
 445  */
 446 #ifdef BGE_REGISTER_DEBUG
 447 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
 448 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
 449 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
 450 #endif
 451 static void bge_add_sysctls(struct bge_softc *);
 452 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
 453
 454 static device_method_t bge_methods[] = {
 455         /* Device interface */
 456         DEVMETHOD(device_probe,         bge_probe),
 457         DEVMETHOD(device_attach,        bge_attach),
 458         DEVMETHOD(device_detach,        bge_detach),
 459         DEVMETHOD(device_shutdown,      bge_shutdown),
 460         DEVMETHOD(device_suspend,       bge_suspend),
 461         DEVMETHOD(device_resume,        bge_resume),
 462
 463         /* bus interface */
 464         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 465         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 466
 467         /* MII interface */
 468         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 469         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 470         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 471
 472         { 0, 0 }
 473 };
 474
 475 static driver_t bge_driver = {
 476         "bge",
 477         bge_methods,
 478         sizeof(struct bge_softc)
 479 };
 480
 481 static devclass_t bge_devclass;
 482
 483 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
 484 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 485
 486 static int bge_allow_asf = 1;
 487
 488 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
 489
 490 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
 491 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0,
 492         "Allow ASF mode if available");
 493
 494 #define SPARC64_BLADE_1500_MODEL        "SUNW,Sun-Blade-1500"
 495 #define SPARC64_BLADE_1500_PATH_BGE     "/pci@1f,700000/network@2"
 496 #define SPARC64_BLADE_2500_MODEL        "SUNW,Sun-Blade-2500"
 497 #define SPARC64_BLADE_2500_PATH_BGE     "/pci@1c,600000/network@3"
 498 #define SPARC64_OFW_SUBVENDOR           "subsystem-vendor-id"
 499
 500 static int
 501 bge_has_eaddr(struct bge_softc *sc)
 502 {
 503 #ifdef __sparc64__
 504         char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)];
 505         device_t dev;
 506         uint32_t subvendor;
 507
 508         dev = sc->bge_dev;
 509
 510         /*
 511          * The on-board BGEs found in sun4u machines aren't fitted with
 512          * an EEPROM which means that we have to obtain the MAC address
 513          * via OFW and that some tests will always fail.  We distinguish
 514          * such BGEs by the subvendor ID, which also has to be obtained
 515          * from OFW instead of the PCI configuration space as the latter
 516          * indicates Broadcom as the subvendor of the netboot interface.
 517          * For early Blade 1500 and 2500 we even have to check the OFW
 518          * device path as the subvendor ID always defaults to Broadcom
 519          * there.
 520          */
 521         if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR,
 522             &subvendor, sizeof(subvendor)) == sizeof(subvendor) &&
 523             subvendor == SUN_VENDORID)
 524                 return (0);
 525         memset(buf, 0, sizeof(buf));
 526         if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) {
 527                 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 &&
 528                     strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0)
 529                         return (0);
 530                 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 &&
 531                     strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0)
 532                         return (0);
 533         }
 534 #endif
 535         return (1);
 536 }
 537
 538 static uint32_t
 539 bge_readmem_ind(struct bge_softc *sc, int off)
 540 {
 541         device_t dev;
 542         uint32_t val;
 543
 544         dev = sc->bge_dev;
 545
 546         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 547         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 548         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 549         return (val);
 550 }
 551
 552 static void
 553 bge_writemem_ind(struct bge_softc *sc, int off, int val)
 554 {
 555         device_t dev;
 556
 557         dev = sc->bge_dev;
 558
 559         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 560         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 561         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 562 }
 563
 564 /*
 565  * PCI Express only
 566  */
 567 static void
 568 bge_set_max_readrq(struct bge_softc *sc)
 569 {
 570         device_t dev;
 571         uint16_t val;
 572
 573         dev = sc->bge_dev;
 574
 575         val = pci_read_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
 576         if ((val & PCIM_EXP_CTL_MAX_READ_REQUEST) !=
 577             BGE_PCIE_DEVCTL_MAX_READRQ_4096) {
 578                 if (bootverbose)
 579                         device_printf(dev, "adjust device control 0x%04x ",
 580                             val);
 581                 val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST;
 582                 val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096;
 583                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL,
 584                     val, 2);
 585                 if (bootverbose)
 586                         printf("-> 0x%04x\n", val);
 587         }
 588 }
 589
 590 #ifdef notdef
 591 static uint32_t
 592 bge_readreg_ind(struct bge_softc *sc, int off)
 593 {
 594         device_t dev;
 595
 596         dev = sc->bge_dev;
 597
 598         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 599         return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 600 }
 601 #endif
 602
 603 static void
 604 bge_writereg_ind(struct bge_softc *sc, int off, int val)
 605 {
 606         device_t dev;
 607
 608         dev = sc->bge_dev;
 609
 610         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 611         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 612 }
 613
 614 static void
 615 bge_writemem_direct(struct bge_softc *sc, int off, int val)
 616 {
 617         CSR_WRITE_4(sc, off, val);
 618 }
 619
 620 static void
 621 bge_writembx(struct bge_softc *sc, int off, int val)
 622 {
 623         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 624                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 625
 626         CSR_WRITE_4(sc, off, val);
 627 }
 628
 629 /*
 630  * Map a single buffer address.
 631  */
 632
 633 static void
 634 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 635 {
 636         struct bge_dmamap_arg *ctx;
 637
 638         if (error)
 639                 return;
 640
 641         ctx = arg;
 642
 643         if (nseg > ctx->bge_maxsegs) {
 644                 ctx->bge_maxsegs = 0;
 645                 return;
 646         }
 647
 648         ctx->bge_busaddr = segs->ds_addr;
 649 }
 650
 651 static uint8_t
 652 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 653 {
 654         uint32_t access, byte = 0;
 655         int i;
 656
 657         /* Lock. */
 658         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 659         for (i = 0; i < 8000; i++) {
 660                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 661                         break;
 662                 DELAY(20);
 663         }
 664         if (i == 8000)
 665                 return (1);
 666
 667         /* Enable access. */
 668         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 669         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 670
 671         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 672         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 673         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 674                 DELAY(10);
 675                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 676                         DELAY(10);
 677                         break;
 678                 }
 679         }
 680
 681         if (i == BGE_TIMEOUT * 10) {
 682                 if_printf(sc->bge_ifp, "nvram read timed out\n");
 683                 return (1);
 684         }
 685
 686         /* Get result. */
 687         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 688
 689         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 690
 691         /* Disable access. */
 692         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 693
 694         /* Unlock. */
 695         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 696         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 697
 698         return (0);
 699 }
 700
 701 /*
 702  * Read a sequence of bytes from NVRAM.
 703  */
 704 static int
 705 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 706 {
 707         int err = 0, i;
 708         uint8_t byte = 0;
 709
 710         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
 711                 return (1);
 712
 713         for (i = 0; i < cnt; i++) {
 714                 err = bge_nvram_getbyte(sc, off + i, &byte);
 715                 if (err)
 716                         break;
 717                 *(dest + i) = byte;
 718         }
 719
 720         return (err ? 1 : 0);
 721 }
 722
 723 /*
 724  * Read a byte of data stored in the EEPROM at address 'addr.' The
 725  * BCM570x supports both the traditional bitbang interface and an
 726  * auto access interface for reading the EEPROM. We use the auto
 727  * access method.
 728  */
 729 static uint8_t
 730 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
 731 {
 732         int i;
 733         uint32_t byte = 0;
 734
 735         /*
 736          * Enable use of auto EEPROM access so we can avoid
 737          * having to use the bitbang method.
 738          */
 739         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 740
 741         /* Reset the EEPROM, load the clock period. */
 742         CSR_WRITE_4(sc, BGE_EE_ADDR,
 743             BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 744         DELAY(20);
 745
 746         /* Issue the read EEPROM command. */
 747         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 748
 749         /* Wait for completion */
 750         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 751                 DELAY(10);
 752                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 753                         break;
 754         }
 755
 756         if (i == BGE_TIMEOUT * 10) {
 757                 device_printf(sc->bge_dev, "EEPROM read timed out\n");
 758                 return (1);
 759         }
 760
 761         /* Get result. */
 762         byte = CSR_READ_4(sc, BGE_EE_DATA);
 763
 764         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 765
 766         return (0);
 767 }
 768
 769 /*
 770  * Read a sequence of bytes from the EEPROM.
 771  */
 772 static int
 773 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
 774 {
 775         int i, error = 0;
 776         uint8_t byte = 0;
 777
 778         for (i = 0; i < cnt; i++) {
 779                 error = bge_eeprom_getbyte(sc, off + i, &byte);
 780                 if (error)
 781                         break;
 782                 *(dest + i) = byte;
 783         }
 784
 785         return (error ? 1 : 0);
 786 }
 787
 788 static int
 789 bge_miibus_readreg(device_t dev, int phy, int reg)
 790 {
 791         struct bge_softc *sc;
 792         uint32_t val, autopoll;
 793         int i;
 794
 795         sc = device_get_softc(dev);
 796
 797         /*
 798          * Broadcom's own driver always assumes the internal
 799          * PHY is at GMII address 1. On some chips, the PHY responds
 800          * to accesses at all addresses, which could cause us to
 801          * bogusly attach the PHY 32 times at probe type. Always
 802          * restricting the lookup to address 1 is simpler than
 803          * trying to figure out which chips revisions should be
 804          * special-cased.
 805          */
 806         if (phy != 1)
 807                 return (0);
 808
 809         /* Reading with autopolling on may trigger PCI errors */
 810         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 811         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 812                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 813                 DELAY(40);
 814         }
 815
 816         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 817             BGE_MIPHY(phy) | BGE_MIREG(reg));
 818
 819         for (i = 0; i < BGE_TIMEOUT; i++) {
 820                 DELAY(10);
 821                 val = CSR_READ_4(sc, BGE_MI_COMM);
 822                 if (!(val & BGE_MICOMM_BUSY))
 823                         break;
 824         }
 825
 826         if (i == BGE_TIMEOUT) {
 827                 device_printf(sc->bge_dev,
 828                     "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
 829                     phy, reg, val);
 830                 val = 0;
 831                 goto done;
 832         }
 833
 834         DELAY(5);
 835         val = CSR_READ_4(sc, BGE_MI_COMM);
 836
 837 done:
 838         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 839                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 840                 DELAY(40);
 841         }
 842
 843         if (val & BGE_MICOMM_READFAIL)
 844                 return (0);
 845
 846         return (val & 0xFFFF);
 847 }
 848
 849 static int
 850 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 851 {
 852         struct bge_softc *sc;
 853         uint32_t autopoll;
 854         int i;
 855
 856         sc = device_get_softc(dev);
 857
 858         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 859             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 860                 return(0);
 861
 862         /* Reading with autopolling on may trigger PCI errors */
 863         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 864         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 865                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 866                 DELAY(40);
 867         }
 868
 869         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 870             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 871
 872         for (i = 0; i < BGE_TIMEOUT; i++) {
 873                 DELAY(10);
 874                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 875                         DELAY(5);
 876                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 877                         break;
 878                 }
 879         }
 880
 881         if (i == BGE_TIMEOUT) {
 882                 device_printf(sc->bge_dev,
 883                     "PHY write timed out (phy %d, reg %d, val %d)\n",
 884                     phy, reg, val);
 885                 return (0);
 886         }
 887
 888         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 889                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 890                 DELAY(40);
 891         }
 892
 893         return (0);
 894 }
 895
 896 static void
 897 bge_miibus_statchg(device_t dev)
 898 {
 899         struct bge_softc *sc;
 900         struct mii_data *mii;
 901         sc = device_get_softc(dev);
 902         mii = device_get_softc(sc->bge_miibus);
 903
 904         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 905         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 906             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
 907                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 908         else
 909                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 910
 911         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
 912                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 913         else
 914                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 915 }
 916
 917 /*
 918  * Intialize a standard receive ring descriptor.
 919  */
 920 static int
 921 bge_newbuf_std(struct bge_softc *sc, int i)
 922 {
 923         struct mbuf *m;
 924         struct bge_rx_bd *r;
 925         bus_dma_segment_t segs[1];
 926         bus_dmamap_t map;
 927         int error, nsegs;
 928
 929         m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
 930         if (m == NULL)
 931                 return (ENOBUFS);
 932         m->m_len = m->m_pkthdr.len = MCLBYTES;
 933         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 934                 m_adj(m, ETHER_ALIGN);
 935
 936         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
 937             sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
 938         if (error != 0) {
 939                 m_freem(m);
 940                 return (error);
 941         }
 942         if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 943                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 944                     sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
 945                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 946                     sc->bge_cdata.bge_rx_std_dmamap[i]);
 947         }
 948         map = sc->bge_cdata.bge_rx_std_dmamap[i];
 949         sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
 950         sc->bge_cdata.bge_rx_std_sparemap = map;
 951         sc->bge_cdata.bge_rx_std_chain[i] = m;
 952         r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
 953         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
 954         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
 955         r->bge_flags = BGE_RXBDFLAG_END;
 956         r->bge_len = segs[0].ds_len;
 957         r->bge_idx = i;
 958
 959         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 960             sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
 961
 962         return (0);
 963 }
 964
 965 /*
 966  * Initialize a jumbo receive ring descriptor. This allocates
 967  * a jumbo buffer from the pool managed internally by the driver.
 968  */
 969 static int
 970 bge_newbuf_jumbo(struct bge_softc *sc, int i)
 971 {
 972         bus_dma_segment_t segs[BGE_NSEG_JUMBO];
 973         bus_dmamap_t map;
 974         struct bge_extrx_bd *r;
 975         struct mbuf *m;
 976         int error, nsegs;
 977
 978         MGETHDR(m, M_DONTWAIT, MT_DATA);
 979         if (m == NULL)
 980                 return (ENOBUFS);
 981
 982         m_cljget(m, M_DONTWAIT, MJUM9BYTES);
 983         if (!(m->m_flags & M_EXT)) {
 984                 m_freem(m);
 985                 return (ENOBUFS);
 986         }
 987         m->m_len = m->m_pkthdr.len = MJUM9BYTES;
 988         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 989                 m_adj(m, ETHER_ALIGN);
 990
 991         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
 992             sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
 993         if (error != 0) {
 994                 m_freem(m);
 995                 return (error);
 996         }
 997
 998         if (sc->bge_cdata.bge_rx_jumbo_chain[i] == NULL) {
 999                 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1000                     sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1001                 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1002                     sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1003         }
1004         map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1005         sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1006             sc->bge_cdata.bge_rx_jumbo_sparemap;
1007         sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1008         sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1009         /*
1010          * Fill in the extended RX buffer descriptor.
1011          */
1012         r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1013         r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1014         r->bge_idx = i;
1015         r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1016         switch (nsegs) {
1017         case 4:
1018                 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1019                 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1020                 r->bge_len3 = segs[3].ds_len;
1021         case 3:
1022                 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1023                 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1024                 r->bge_len2 = segs[2].ds_len;
1025         case 2:
1026                 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1027                 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1028                 r->bge_len1 = segs[1].ds_len;
1029         case 1:
1030                 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1031                 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1032                 r->bge_len0 = segs[0].ds_len;
1033                 break;
1034         default:
1035                 panic("%s: %d segments\n", __func__, nsegs);
1036         }
1037
1038         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1039             sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1040
1041         return (0);
1042 }
1043
1044 /*
1045  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
1046  * that's 1MB or memory, which is a lot. For now, we fill only the first
1047  * 256 ring entries and hope that our CPU is fast enough to keep up with
1048  * the NIC.
1049  */
1050 static int
1051 bge_init_rx_ring_std(struct bge_softc *sc)
1052 {
1053         int error, i;
1054
1055         bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1056         sc->bge_std = 0;
1057         for (i = 0; i < BGE_SSLOTS; i++) {
1058                 if ((error = bge_newbuf_std(sc, i)) != 0)
1059                         return (error);
1060                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1061         };
1062
1063         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1064             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1065
1066         sc->bge_std = i - 1;
1067         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1068
1069         return (0);
1070 }
1071
1072 static void
1073 bge_free_rx_ring_std(struct bge_softc *sc)
1074 {
1075         int i;
1076
1077         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1078                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1079                         bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1080                             sc->bge_cdata.bge_rx_std_dmamap[i],
1081                             BUS_DMASYNC_POSTREAD);
1082                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1083                             sc->bge_cdata.bge_rx_std_dmamap[i]);
1084                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1085                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1086                 }
1087                 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1088                     sizeof(struct bge_rx_bd));
1089         }
1090 }
1091
1092 static int
1093 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1094 {
1095         struct bge_rcb *rcb;
1096         int error, i;
1097
1098         bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1099         sc->bge_jumbo = 0;
1100         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1101                 if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1102                         return (error);
1103                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1104         };
1105
1106         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1107             sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1108
1109         sc->bge_jumbo = i - 1;
1110
1111         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1112         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1113                                     BGE_RCB_FLAG_USE_EXT_RX_BD);
1114         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1115
1116         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1117
1118         return (0);
1119 }
1120
1121 static void
1122 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1123 {
1124         int i;
1125
1126         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1127                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1128                         bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1129                             sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1130                             BUS_DMASYNC_POSTREAD);
1131                         bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1132                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1133                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1134                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1135                 }
1136                 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1137                     sizeof(struct bge_extrx_bd));
1138         }
1139 }
1140
1141 static void
1142 bge_free_tx_ring(struct bge_softc *sc)
1143 {
1144         int i;
1145
1146         if (sc->bge_ldata.bge_tx_ring == NULL)
1147                 return;
1148
1149         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1150                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1151                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1152                             sc->bge_cdata.bge_tx_dmamap[i],
1153                             BUS_DMASYNC_POSTWRITE);
1154                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1155                             sc->bge_cdata.bge_tx_dmamap[i]);
1156                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1157                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1158                 }
1159                 bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1160                     sizeof(struct bge_tx_bd));
1161         }
1162 }
1163
1164 static int
1165 bge_init_tx_ring(struct bge_softc *sc)
1166 {
1167         sc->bge_txcnt = 0;
1168         sc->bge_tx_saved_considx = 0;
1169
1170         bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1171         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1172             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1173
1174         /* Initialize transmit producer index for host-memory send ring. */
1175         sc->bge_tx_prodidx = 0;
1176         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1177
1178         /* 5700 b2 errata */
1179         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1180                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1181
1182         /* NIC-memory send ring not used; initialize to zero. */
1183         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1184         /* 5700 b2 errata */
1185         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1186                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1187
1188         return (0);
1189 }
1190
1191 static void
1192 bge_setpromisc(struct bge_softc *sc)
1193 {
1194         struct ifnet *ifp;
1195
1196         BGE_LOCK_ASSERT(sc);
1197
1198         ifp = sc->bge_ifp;
1199
1200         /* Enable or disable promiscuous mode as needed. */
1201         if (ifp->if_flags & IFF_PROMISC)
1202                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1203         else
1204                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1205 }
1206
1207 static void
1208 bge_setmulti(struct bge_softc *sc)
1209 {
1210         struct ifnet *ifp;
1211         struct ifmultiaddr *ifma;
1212         uint32_t hashes[4] = { 0, 0, 0, 0 };
1213         int h, i;
1214
1215         BGE_LOCK_ASSERT(sc);
1216
1217         ifp = sc->bge_ifp;
1218
1219         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1220                 for (i = 0; i < 4; i++)
1221                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1222                 return;
1223         }
1224
1225         /* First, zot all the existing filters. */
1226         for (i = 0; i < 4; i++)
1227                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1228
1229         /* Now program new ones. */
1230         if_maddr_rlock(ifp);
1231         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1232                 if (ifma->ifma_addr->sa_family != AF_LINK)
1233                         continue;
1234                 h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1235                     ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;
1236                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1237         }
1238         if_maddr_runlock(ifp);
1239
1240         for (i = 0; i < 4; i++)
1241                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1242 }
1243
1244 static void
1245 bge_setvlan(struct bge_softc *sc)
1246 {
1247         struct ifnet *ifp;
1248
1249         BGE_LOCK_ASSERT(sc);
1250
1251         ifp = sc->bge_ifp;
1252
1253         /* Enable or disable VLAN tag stripping as needed. */
1254         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1255                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1256         else
1257                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1258 }
1259
1260 static void
1261 bge_sig_pre_reset(sc, type)
1262         struct bge_softc *sc;
1263         int type;
1264 {
1265         /*
1266          * Some chips don't like this so only do this if ASF is enabled
1267          */
1268         if (sc->bge_asf_mode)
1269                 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1270
1271         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1272                 switch (type) {
1273                 case BGE_RESET_START:
1274                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1275                         break;
1276                 case BGE_RESET_STOP:
1277                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1278                         break;
1279                 }
1280         }
1281 }
1282
1283 static void
1284 bge_sig_post_reset(sc, type)
1285         struct bge_softc *sc;
1286         int type;
1287 {
1288         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1289                 switch (type) {
1290                 case BGE_RESET_START:
1291                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001);
1292                         /* START DONE */
1293                         break;
1294                 case BGE_RESET_STOP:
1295                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002);
1296                         break;
1297                 }
1298         }
1299 }
1300
1301 static void
1302 bge_sig_legacy(sc, type)
1303         struct bge_softc *sc;
1304         int type;
1305 {
1306         if (sc->bge_asf_mode) {
1307                 switch (type) {
1308                 case BGE_RESET_START:
1309                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
1310                         break;
1311                 case BGE_RESET_STOP:
1312                         bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
1313                         break;
1314                 }
1315         }
1316 }
1317
1318 void bge_stop_fw(struct bge_softc *);
1319 void
1320 bge_stop_fw(sc)
1321         struct bge_softc *sc;
1322 {
1323         int i;
1324
1325         if (sc->bge_asf_mode) {
1326                 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE);
1327                 CSR_WRITE_4(sc, BGE_CPU_EVENT,
1328                     CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
1329
1330                 for (i = 0; i < 100; i++ ) {
1331                         if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14)))
1332                                 break;
1333                         DELAY(10);
1334                 }
1335         }
1336 }
1337
1338 /*
1339  * Do endian, PCI and DMA initialization.
1340  */
1341 static int
1342 bge_chipinit(struct bge_softc *sc)
1343 {
1344         uint32_t dma_rw_ctl;
1345         int i;
1346
1347         /* Set endianness before we access any non-PCI registers. */
1348         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1349
1350         /* Clear the MAC control register */
1351         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1352
1353         /*
1354          * Clear the MAC statistics block in the NIC's
1355          * internal memory.
1356          */
1357         for (i = BGE_STATS_BLOCK;
1358             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1359                 BGE_MEMWIN_WRITE(sc, i, 0);
1360
1361         for (i = BGE_STATUS_BLOCK;
1362             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1363                 BGE_MEMWIN_WRITE(sc, i, 0);
1364
1365         /*
1366          * Set up the PCI DMA control register.
1367          */
1368         dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1369             BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1370         if (sc->bge_flags & BGE_FLAG_PCIE) {
1371                 /* Read watermark not used, 128 bytes for write. */
1372                 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1373         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1374                 if (BGE_IS_5714_FAMILY(sc)) {
1375                         /* 256 bytes for read and write. */
1376                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1377                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1378                         dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1379                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1380                             BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1381                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1382                         /* 1536 bytes for read, 384 bytes for write. */
1383                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1384                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1385                 } else {
1386                         /* 384 bytes for read and write. */
1387                         dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1388                             BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1389                             0x0F;
1390                 }
1391                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1392                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1393                         uint32_t tmp;
1394
1395                         /* Set ONE_DMA_AT_ONCE for hardware workaround. */
1396                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1397                         if (tmp == 6 || tmp == 7)
1398                                 dma_rw_ctl |=
1399                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1400
1401                         /* Set PCI-X DMA write workaround. */
1402                         dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1403                 }
1404         } else {
1405                 /* Conventional PCI bus: 256 bytes for read and write. */
1406                 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1407                     BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1408
1409                 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1410                     sc->bge_asicrev != BGE_ASICREV_BCM5750)
1411                         dma_rw_ctl |= 0x0F;
1412         }
1413         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1414             sc->bge_asicrev == BGE_ASICREV_BCM5701)
1415                 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1416                     BGE_PCIDMARWCTL_ASRT_ALL_BE;
1417         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1418             sc->bge_asicrev == BGE_ASICREV_BCM5704)
1419                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1420         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1421
1422         /*
1423          * Set up general mode register.
1424          */
1425         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
1426             BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1427             BGE_MODECTL_TX_NO_PHDR_CSUM);
1428
1429         /*
1430          * BCM5701 B5 have a bug causing data corruption when using
1431          * 64-bit DMA reads, which can be terminated early and then
1432          * completed later as 32-bit accesses, in combination with
1433          * certain bridges.
1434          */
1435         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1436             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1437                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1438
1439         /*
1440          * Tell the firmware the driver is running
1441          */
1442         if (sc->bge_asf_mode & ASF_STACKUP)
1443                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
1444
1445         /*
1446          * Disable memory write invalidate.  Apparently it is not supported
1447          * properly by these devices.  Also ensure that INTx isn't disabled,
1448          * as these chips need it even when using MSI.
1449          */
1450         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1451             PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4);
1452
1453         /* Set the timer prescaler (always 66Mhz) */
1454         CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1455
1456         /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1457         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1458                 DELAY(40);      /* XXX */
1459
1460                 /* Put PHY into ready state */
1461                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1462                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1463                 DELAY(40);
1464         }
1465
1466         return (0);
1467 }
1468
1469 static int
1470 bge_blockinit(struct bge_softc *sc)
1471 {
1472         struct bge_rcb *rcb;
1473         bus_size_t vrcb;
1474         bge_hostaddr taddr;
1475         uint32_t val;
1476         int i;
1477
1478         /*
1479          * Initialize the memory window pointer register so that
1480          * we can access the first 32K of internal NIC RAM. This will
1481          * allow us to set up the TX send ring RCBs and the RX return
1482          * ring RCBs, plus other things which live in NIC memory.
1483          */
1484         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1485
1486         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1487
1488         if (!(BGE_IS_5705_PLUS(sc))) {
1489                 /* Configure mbuf memory pool */
1490                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1491                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1492                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1493                 else
1494                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1495
1496                 /* Configure DMA resource pool */
1497                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1498                     BGE_DMA_DESCRIPTORS);
1499                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1500         }
1501
1502         /* Configure mbuf pool watermarks */
1503         if (!BGE_IS_5705_PLUS(sc)) {
1504                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1505                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1506                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1507         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1508                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1509                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1510                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1511         } else {
1512                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1513                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1514                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1515         }
1516
1517         /* Configure DMA resource watermarks */
1518         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1519         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1520
1521         /* Enable buffer manager */
1522         if (!(BGE_IS_5705_PLUS(sc))) {
1523                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1524                     BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN);
1525
1526                 /* Poll for buffer manager start indication */
1527                 for (i = 0; i < BGE_TIMEOUT; i++) {
1528                         DELAY(10);
1529                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1530                                 break;
1531                 }
1532
1533                 if (i == BGE_TIMEOUT) {
1534                         device_printf(sc->bge_dev,
1535                             "buffer manager failed to start\n");
1536                         return (ENXIO);
1537                 }
1538         }
1539
1540         /* Enable flow-through queues */
1541         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1542         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1543
1544         /* Wait until queue initialization is complete */
1545         for (i = 0; i < BGE_TIMEOUT; i++) {
1546                 DELAY(10);
1547                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1548                         break;
1549         }
1550
1551         if (i == BGE_TIMEOUT) {
1552                 device_printf(sc->bge_dev, "flow-through queue init failed\n");
1553                 return (ENXIO);
1554         }
1555
1556         /* Initialize the standard RX ring control block */
1557         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1558         rcb->bge_hostaddr.bge_addr_lo =
1559             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1560         rcb->bge_hostaddr.bge_addr_hi =
1561             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1562         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1563             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1564         if (BGE_IS_5705_PLUS(sc))
1565                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1566         else
1567                 rcb->bge_maxlen_flags =
1568                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1569         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1570         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1571         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1572
1573         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1574         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1575
1576         /*
1577          * Initialize the jumbo RX ring control block
1578          * We set the 'ring disabled' bit in the flags
1579          * field until we're actually ready to start
1580          * using this ring (i.e. once we set the MTU
1581          * high enough to require it).
1582          */
1583         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1584                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1585
1586                 rcb->bge_hostaddr.bge_addr_lo =
1587                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1588                 rcb->bge_hostaddr.bge_addr_hi =
1589                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1590                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1591                     sc->bge_cdata.bge_rx_jumbo_ring_map,
1592                     BUS_DMASYNC_PREREAD);
1593                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
1594                     BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
1595                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1596                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1597                     rcb->bge_hostaddr.bge_addr_hi);
1598                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1599                     rcb->bge_hostaddr.bge_addr_lo);
1600
1601                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1602                     rcb->bge_maxlen_flags);
1603                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1604
1605                 /* Set up dummy disabled mini ring RCB */
1606                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1607                 rcb->bge_maxlen_flags =
1608                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1609                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1610                     rcb->bge_maxlen_flags);
1611         }
1612
1613         /*
1614          * Set the BD ring replentish thresholds. The recommended
1615          * values are 1/8th the number of descriptors allocated to
1616          * each ring.
1617          * XXX The 5754 requires a lower threshold, so it might be a
1618          * requirement of all 575x family chips.  The Linux driver sets
1619          * the lower threshold for all 5705 family chips as well, but there
1620          * are reports that it might not need to be so strict.
1621          *
1622          * XXX Linux does some extra fiddling here for the 5906 parts as
1623          * well.
1624          */
1625         if (BGE_IS_5705_PLUS(sc))
1626                 val = 8;
1627         else
1628                 val = BGE_STD_RX_RING_CNT / 8;
1629         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1630         if (BGE_IS_JUMBO_CAPABLE(sc))
1631                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1632                     BGE_JUMBO_RX_RING_CNT/8);
1633
1634         /*
1635          * Disable all unused send rings by setting the 'ring disabled'
1636          * bit in the flags field of all the TX send ring control blocks.
1637          * These are located in NIC memory.
1638          */
1639         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1640         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1641                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1642                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1643                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1644                 vrcb += sizeof(struct bge_rcb);
1645         }
1646
1647         /* Configure TX RCB 0 (we use only the first ring) */
1648         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1649         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1650         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1651         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1652         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1653             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1654         if (!(BGE_IS_5705_PLUS(sc)))
1655                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1656                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1657
1658         /* Disable all unused RX return rings */
1659         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1660         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1661                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1662                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1663                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1664                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1665                     BGE_RCB_FLAG_RING_DISABLED));
1666                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1667                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1668                     (i * (sizeof(uint64_t))), 0);
1669                 vrcb += sizeof(struct bge_rcb);
1670         }
1671
1672         /* Initialize RX ring indexes */
1673         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1674         if (BGE_IS_JUMBO_CAPABLE(sc))
1675                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1676         if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1677                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1678
1679         /*
1680          * Set up RX return ring 0
1681          * Note that the NIC address for RX return rings is 0x00000000.
1682          * The return rings live entirely within the host, so the
1683          * nicaddr field in the RCB isn't used.
1684          */
1685         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1686         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1687         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1688         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1689         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1690         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1691             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1692
1693         /* Set random backoff seed for TX */
1694         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1695             IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1696             IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1697             IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1698             BGE_TX_BACKOFF_SEED_MASK);
1699
1700         /* Set inter-packet gap */
1701         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1702
1703         /*
1704          * Specify which ring to use for packets that don't match
1705          * any RX rules.
1706          */
1707         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1708
1709         /*
1710          * Configure number of RX lists. One interrupt distribution
1711          * list, sixteen active lists, one bad frames class.
1712          */
1713         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1714
1715         /* Inialize RX list placement stats mask. */
1716         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1717         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1718
1719         /* Disable host coalescing until we get it set up */
1720         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1721
1722         /* Poll to make sure it's shut down. */
1723         for (i = 0; i < BGE_TIMEOUT; i++) {
1724                 DELAY(10);
1725                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1726                         break;
1727         }
1728
1729         if (i == BGE_TIMEOUT) {
1730                 device_printf(sc->bge_dev,
1731                     "host coalescing engine failed to idle\n");
1732                 return (ENXIO);
1733         }
1734
1735         /* Set up host coalescing defaults */
1736         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1737         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1738         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1739         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1740         if (!(BGE_IS_5705_PLUS(sc))) {
1741                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1742                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1743         }
1744         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1745         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1746
1747         /* Set up address of statistics block */
1748         if (!(BGE_IS_5705_PLUS(sc))) {
1749                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1750                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1751                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1752                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1753                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1754                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1755                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1756         }
1757
1758         /* Set up address of status block */
1759         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1760             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1761         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1762             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1763         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1764         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1765
1766         /* Set up status block size. */
1767         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1768             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
1769                 val = BGE_STATBLKSZ_FULL;
1770         else
1771                 val = BGE_STATBLKSZ_32BYTE;
1772
1773         /* Turn on host coalescing state machine */
1774         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1775
1776         /* Turn on RX BD completion state machine and enable attentions */
1777         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1778             BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
1779
1780         /* Turn on RX list placement state machine */
1781         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1782
1783         /* Turn on RX list selector state machine. */
1784         if (!(BGE_IS_5705_PLUS(sc)))
1785                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1786
1787         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1788             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1789             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1790             BGE_MACMODE_FRMHDR_DMA_ENB;
1791
1792         if (sc->bge_flags & BGE_FLAG_TBI)
1793                 val |= BGE_PORTMODE_TBI;
1794         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1795                 val |= BGE_PORTMODE_GMII;
1796         else
1797                 val |= BGE_PORTMODE_MII;
1798
1799         /* Turn on DMA, clear stats */
1800         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1801
1802         /* Set misc. local control, enable interrupts on attentions */
1803         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1804
1805 #ifdef notdef
1806         /* Assert GPIO pins for PHY reset */
1807         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
1808             BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
1809         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
1810             BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
1811 #endif
1812
1813         /* Turn on DMA completion state machine */
1814         if (!(BGE_IS_5705_PLUS(sc)))
1815                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1816
1817         val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
1818
1819         /* Enable host coalescing bug fix. */
1820         if (BGE_IS_5755_PLUS(sc))
1821                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1822
1823         /* Turn on write DMA state machine */
1824         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1825         DELAY(40);
1826
1827         /* Turn on read DMA state machine */
1828         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1829         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1830             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1831             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1832                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1833                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1834                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1835         if (sc->bge_flags & BGE_FLAG_PCIE)
1836                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1837         if (sc->bge_flags & BGE_FLAG_TSO)
1838                 val |= BGE_RDMAMODE_TSO4_ENABLE;
1839         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1840         DELAY(40);
1841
1842         /* Turn on RX data completion state machine */
1843         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1844
1845         /* Turn on RX BD initiator state machine */
1846         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1847
1848         /* Turn on RX data and RX BD initiator state machine */
1849         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1850
1851         /* Turn on Mbuf cluster free state machine */
1852         if (!(BGE_IS_5705_PLUS(sc)))
1853                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1854
1855         /* Turn on send BD completion state machine */
1856         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1857
1858         /* Turn on send data completion state machine */
1859         val = BGE_SDCMODE_ENABLE;
1860         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1861                 val |= BGE_SDCMODE_CDELAY;
1862         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1863
1864         /* Turn on send data initiator state machine */
1865         if (sc->bge_flags & BGE_FLAG_TSO)
1866                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08);
1867         else
1868                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1869
1870         /* Turn on send BD initiator state machine */
1871         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1872
1873         /* Turn on send BD selector state machine */
1874         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1875
1876         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1877         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1878             BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
1879
1880         /* ack/clear link change events */
1881         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1882             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1883             BGE_MACSTAT_LINK_CHANGED);
1884         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1885
1886         /* Enable PHY auto polling (for MII/GMII only) */
1887         if (sc->bge_flags & BGE_FLAG_TBI) {
1888                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1889         } else {
1890                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16));
1891                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1892                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
1893                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1894                             BGE_EVTENB_MI_INTERRUPT);
1895         }
1896
1897         /*
1898          * Clear any pending link state attention.
1899          * Otherwise some link state change events may be lost until attention
1900          * is cleared by bge_intr() -> bge_link_upd() sequence.
1901          * It's not necessary on newer BCM chips - perhaps enabling link
1902          * state change attentions implies clearing pending attention.
1903          */
1904         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
1905             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
1906             BGE_MACSTAT_LINK_CHANGED);
1907
1908         /* Enable link state change attentions. */
1909         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1910
1911         return (0);
1912 }
1913
1914 const struct bge_revision *
1915 bge_lookup_rev(uint32_t chipid)
1916 {
1917         const struct bge_revision *br;
1918
1919         for (br = bge_revisions; br->br_name != NULL; br++) {
1920                 if (br->br_chipid == chipid)
1921                         return (br);
1922         }
1923
1924         for (br = bge_majorrevs; br->br_name != NULL; br++) {
1925                 if (br->br_chipid == BGE_ASICREV(chipid))
1926                         return (br);
1927         }
1928
1929         return (NULL);
1930 }
1931
1932 const struct bge_vendor *
1933 bge_lookup_vendor(uint16_t vid)
1934 {
1935         const struct bge_vendor *v;
1936
1937         for (v = bge_vendors; v->v_name != NULL; v++)
1938                 if (v->v_id == vid)
1939                         return (v);
1940
1941         panic("%s: unknown vendor %d", __func__, vid);
1942         return (NULL);
1943 }
1944
1945 /*
1946  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1947  * against our list and return its name if we find a match.
1948  *
1949  * Note that since the Broadcom controller contains VPD support, we
1950  * try to get the device name string from the controller itself instead
1951  * of the compiled-in string. It guarantees we'll always announce the
1952  * right product name. We fall back to the compiled-in string when
1953  * VPD is unavailable or corrupt.
1954  */
1955 static int
1956 bge_probe(device_t dev)
1957 {
1958         const struct bge_type *t = bge_devs;
1959         struct bge_softc *sc = device_get_softc(dev);
1960         uint16_t vid, did;
1961
1962         sc->bge_dev = dev;
1963         vid = pci_get_vendor(dev);
1964         did = pci_get_device(dev);
1965         while(t->bge_vid != 0) {
1966                 if ((vid == t->bge_vid) && (did == t->bge_did)) {
1967                         char model[64], buf[96];
1968                         const struct bge_revision *br;
1969                         const struct bge_vendor *v;
1970                         uint32_t id;
1971
1972                         id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1973                             BGE_PCIMISCCTL_ASICREV_SHIFT;
1974                         if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG)
1975                                 id = pci_read_config(dev,
1976                                     BGE_PCI_PRODID_ASICREV, 4);
1977                         br = bge_lookup_rev(id);
1978                         v = bge_lookup_vendor(vid);
1979                         {
1980 #if __FreeBSD_version > 700024
1981                                 const char *pname;
1982
1983                                 if (bge_has_eaddr(sc) &&
1984                                     pci_get_vpd_ident(dev, &pname) == 0)
1985                                         snprintf(model, 64, "%s", pname);
1986                                 else
1987 #endif
1988                                         snprintf(model, 64, "%s %s",
1989                                             v->v_name,
1990                                             br != NULL ? br->br_name :
1991                                             "NetXtreme Ethernet Controller");
1992                         }
1993                         snprintf(buf, 96, "%s, %sASIC rev. %#08x", model,
1994                             br != NULL ? "" : "unknown ", id);
1995                         device_set_desc_copy(dev, buf);
1996                         if (pci_get_subvendor(dev) == DELL_VENDORID)
1997                                 sc->bge_flags |= BGE_FLAG_NO_3LED;
1998                         if (did == BCOM_DEVICEID_BCM5755M)
1999                                 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
2000                         return (0);
2001                 }
2002                 t++;
2003         }
2004
2005         return (ENXIO);
2006 }
2007
2008 static void
2009 bge_dma_free(struct bge_softc *sc)
2010 {
2011         int i;
2012
2013         /* Destroy DMA maps for RX buffers. */
2014         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2015                 if (sc->bge_cdata.bge_rx_std_dmamap[i])
2016                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2017                             sc->bge_cdata.bge_rx_std_dmamap[i]);
2018         }
2019         if (sc->bge_cdata.bge_rx_std_sparemap)
2020                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2021                     sc->bge_cdata.bge_rx_std_sparemap);
2022
2023         /* Destroy DMA maps for jumbo RX buffers. */
2024         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2025                 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2026                         bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2027                             sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2028         }
2029         if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2030                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2031                     sc->bge_cdata.bge_rx_jumbo_sparemap);
2032
2033         /* Destroy DMA maps for TX buffers. */
2034         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2035                 if (sc->bge_cdata.bge_tx_dmamap[i])
2036                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2037                             sc->bge_cdata.bge_tx_dmamap[i]);
2038         }
2039
2040         if (sc->bge_cdata.bge_rx_mtag)
2041                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2042         if (sc->bge_cdata.bge_tx_mtag)
2043                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2044
2045
2046         /* Destroy standard RX ring. */
2047         if (sc->bge_cdata.bge_rx_std_ring_map)
2048                 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2049                     sc->bge_cdata.bge_rx_std_ring_map);
2050         if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring)
2051                 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2052                     sc->bge_ldata.bge_rx_std_ring,
2053                     sc->bge_cdata.bge_rx_std_ring_map);
2054
2055         if (sc->bge_cdata.bge_rx_std_ring_tag)
2056                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2057
2058         /* Destroy jumbo RX ring. */
2059         if (sc->bge_cdata.bge_rx_jumbo_ring_map)
2060                 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2061                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2062
2063         if (sc->bge_cdata.bge_rx_jumbo_ring_map &&
2064             sc->bge_ldata.bge_rx_jumbo_ring)
2065                 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2066                     sc->bge_ldata.bge_rx_jumbo_ring,
2067                     sc->bge_cdata.bge_rx_jumbo_ring_map);
2068
2069         if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2070                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2071
2072         /* Destroy RX return ring. */
2073         if (sc->bge_cdata.bge_rx_return_ring_map)
2074                 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2075                     sc->bge_cdata.bge_rx_return_ring_map);
2076
2077         if (sc->bge_cdata.bge_rx_return_ring_map &&
2078             sc->bge_ldata.bge_rx_return_ring)
2079                 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2080                     sc->bge_ldata.bge_rx_return_ring,
2081                     sc->bge_cdata.bge_rx_return_ring_map);
2082
2083         if (sc->bge_cdata.bge_rx_return_ring_tag)
2084                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2085
2086         /* Destroy TX ring. */
2087         if (sc->bge_cdata.bge_tx_ring_map)
2088                 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2089                     sc->bge_cdata.bge_tx_ring_map);
2090
2091         if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring)
2092                 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2093                     sc->bge_ldata.bge_tx_ring,
2094                     sc->bge_cdata.bge_tx_ring_map);
2095
2096         if (sc->bge_cdata.bge_tx_ring_tag)
2097                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2098
2099         /* Destroy status block. */
2100         if (sc->bge_cdata.bge_status_map)
2101                 bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2102                     sc->bge_cdata.bge_status_map);
2103
2104         if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block)
2105                 bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2106                     sc->bge_ldata.bge_status_block,
2107                     sc->bge_cdata.bge_status_map);
2108
2109         if (sc->bge_cdata.bge_status_tag)
2110                 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2111
2112         /* Destroy statistics block. */
2113         if (sc->bge_cdata.bge_stats_map)
2114                 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2115                     sc->bge_cdata.bge_stats_map);
2116
2117         if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats)
2118                 bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2119                     sc->bge_ldata.bge_stats,
2120                     sc->bge_cdata.bge_stats_map);
2121
2122         if (sc->bge_cdata.bge_stats_tag)
2123                 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2124
2125         /* Destroy the parent tag. */
2126         if (sc->bge_cdata.bge_parent_tag)
2127                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2128 }
2129
2130 static int
2131 bge_dma_alloc(device_t dev)
2132 {
2133         struct bge_dmamap_arg ctx;
2134         struct bge_softc *sc;
2135         bus_addr_t lowaddr;
2136         bus_size_t sbsz, txsegsz, txmaxsegsz;
2137         int i, error;
2138
2139         sc = device_get_softc(dev);
2140
2141         lowaddr = BUS_SPACE_MAXADDR;
2142         if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2143                 lowaddr = BGE_DMA_MAXADDR;
2144         if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0)
2145                 lowaddr = BUS_SPACE_MAXADDR_32BIT;
2146         /*
2147          * Allocate the parent bus DMA tag appropriate for PCI.
2148          */
2149         error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2150             1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2151             NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2152             0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2153
2154         if (error != 0) {
2155                 device_printf(sc->bge_dev,
2156                     "could not allocate parent dma tag\n");
2157                 return (ENOMEM);
2158         }
2159
2160         /*
2161          * Create tag for Tx mbufs.
2162          */
2163         if (sc->bge_flags & BGE_FLAG_TSO) {
2164                 txsegsz = BGE_TSOSEG_SZ;
2165                 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
2166         } else {
2167                 txsegsz = MCLBYTES;
2168                 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
2169         }
2170         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1,
2171             0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
2172             txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
2173             &sc->bge_cdata.bge_tx_mtag);
2174
2175         if (error) {
2176                 device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
2177                 return (ENOMEM);
2178         }
2179
2180         /*
2181          * Create tag for Rx mbufs.
2182          */
2183         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
2184             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
2185             MCLBYTES, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
2186
2187         if (error) {
2188                 device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
2189                 return (ENOMEM);
2190         }
2191
2192         /* Create DMA maps for RX buffers. */
2193         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2194             &sc->bge_cdata.bge_rx_std_sparemap);
2195         if (error) {
2196                 device_printf(sc->bge_dev,
2197                     "can't create spare DMA map for RX\n");
2198                 return (ENOMEM);
2199         }
2200         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2201                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
2202                             &sc->bge_cdata.bge_rx_std_dmamap[i]);
2203                 if (error) {
2204                         device_printf(sc->bge_dev,
2205                             "can't create DMA map for RX\n");
2206                         return (ENOMEM);
2207                 }
2208         }
2209
2210         /* Create DMA maps for TX buffers. */
2211         for (i = 0; i < BGE_TX_RING_CNT; i++) {
2212                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
2213                             &sc->bge_cdata.bge_tx_dmamap[i]);
2214                 if (error) {
2215                         device_printf(sc->bge_dev,
2216                             "can't create DMA map for TX\n");
2217                         return (ENOMEM);
2218                 }
2219         }
2220
2221         /* Create tag for standard RX ring. */
2222         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2223             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2224             NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0,
2225             NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag);
2226
2227         if (error) {
2228                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2229                 return (ENOMEM);
2230         }
2231
2232         /* Allocate DMA'able memory for standard RX ring. */
2233         error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag,
2234             (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT,
2235             &sc->bge_cdata.bge_rx_std_ring_map);
2236         if (error)
2237                 return (ENOMEM);
2238
2239         bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
2240
2241         /* Load the address of the standard RX ring. */
2242         ctx.bge_maxsegs = 1;
2243         ctx.sc = sc;
2244
2245         error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag,
2246             sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring,
2247             BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2248
2249         if (error)
2250                 return (ENOMEM);
2251
2252         sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr;
2253
2254         /* Create tags for jumbo mbufs. */
2255         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2256                 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2257                     1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2258                     NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
2259                     0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
2260                 if (error) {
2261                         device_printf(sc->bge_dev,
2262                             "could not allocate jumbo dma tag\n");
2263                         return (ENOMEM);
2264                 }
2265
2266                 /* Create tag for jumbo RX ring. */
2267                 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2268                     PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2269                     NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0,
2270                     NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag);
2271
2272                 if (error) {
2273                         device_printf(sc->bge_dev,
2274                             "could not allocate jumbo ring dma tag\n");
2275                         return (ENOMEM);
2276                 }
2277
2278                 /* Allocate DMA'able memory for jumbo RX ring. */
2279                 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2280                     (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
2281                     BUS_DMA_NOWAIT | BUS_DMA_ZERO,
2282                     &sc->bge_cdata.bge_rx_jumbo_ring_map);
2283                 if (error)
2284                         return (ENOMEM);
2285
2286                 /* Load the address of the jumbo RX ring. */
2287                 ctx.bge_maxsegs = 1;
2288                 ctx.sc = sc;
2289
2290                 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2291                     sc->bge_cdata.bge_rx_jumbo_ring_map,
2292                     sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ,
2293                     bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2294
2295                 if (error)
2296                         return (ENOMEM);
2297
2298                 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr;
2299
2300                 /* Create DMA maps for jumbo RX buffers. */
2301                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2302                     0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
2303                 if (error) {
2304                         device_printf(sc->bge_dev,
2305                             "can't create spare DMA map for jumbo RX\n");
2306                         return (ENOMEM);
2307                 }
2308                 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2309                         error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
2310                                     0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2311                         if (error) {
2312                                 device_printf(sc->bge_dev,
2313                                     "can't create DMA map for jumbo RX\n");
2314                                 return (ENOMEM);
2315                         }
2316                 }
2317
2318         }
2319
2320         /* Create tag for RX return ring. */
2321         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2322             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2323             NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0,
2324             NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag);
2325
2326         if (error) {
2327                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2328                 return (ENOMEM);
2329         }
2330
2331         /* Allocate DMA'able memory for RX return ring. */
2332         error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag,
2333             (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT,
2334             &sc->bge_cdata.bge_rx_return_ring_map);
2335         if (error)
2336                 return (ENOMEM);
2337
2338         bzero((char *)sc->bge_ldata.bge_rx_return_ring,
2339             BGE_RX_RTN_RING_SZ(sc));
2340
2341         /* Load the address of the RX return ring. */
2342         ctx.bge_maxsegs = 1;
2343         ctx.sc = sc;
2344
2345         error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag,
2346             sc->bge_cdata.bge_rx_return_ring_map,
2347             sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc),
2348             bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2349
2350         if (error)
2351                 return (ENOMEM);
2352
2353         sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr;
2354
2355         /* Create tag for TX ring. */
2356         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2357             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2358             NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL,
2359             &sc->bge_cdata.bge_tx_ring_tag);
2360
2361         if (error) {
2362                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2363                 return (ENOMEM);
2364         }
2365
2366         /* Allocate DMA'able memory for TX ring. */
2367         error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag,
2368             (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT,
2369             &sc->bge_cdata.bge_tx_ring_map);
2370         if (error)
2371                 return (ENOMEM);
2372
2373         bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
2374
2375         /* Load the address of the TX ring. */
2376         ctx.bge_maxsegs = 1;
2377         ctx.sc = sc;
2378
2379         error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag,
2380             sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring,
2381             BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2382
2383         if (error)
2384                 return (ENOMEM);
2385
2386         sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr;
2387
2388         /*
2389          * Create tag for status block.
2390          * Because we only use single Tx/Rx/Rx return ring, use
2391          * minimum status block size except BCM5700 AX/BX which
2392          * seems to want to see full status block size regardless
2393          * of configured number of ring.
2394          */
2395         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2396             sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
2397                 sbsz = BGE_STATUS_BLK_SZ;
2398         else
2399                 sbsz = 32;
2400         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2401             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2402             NULL, sbsz, 1, sbsz, 0, NULL, NULL, &sc->bge_cdata.bge_status_tag);
2403
2404         if (error) {
2405                 device_printf(sc->bge_dev,
2406                     "could not allocate status dma tag\n");
2407                 return (ENOMEM);
2408         }
2409
2410         /* Allocate DMA'able memory for status block. */
2411         error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag,
2412             (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT,
2413             &sc->bge_cdata.bge_status_map);
2414         if (error)
2415                 return (ENOMEM);
2416
2417         bzero((char *)sc->bge_ldata.bge_status_block, sbsz);
2418
2419         /* Load the address of the status block. */
2420         ctx.sc = sc;
2421         ctx.bge_maxsegs = 1;
2422
2423         error = bus_dmamap_load(sc->bge_cdata.bge_status_tag,
2424             sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block,
2425             sbsz, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2426
2427         if (error)
2428                 return (ENOMEM);
2429
2430         sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr;
2431
2432         /* Create tag for statistics block. */
2433         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2434             PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
2435             NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL,
2436             &sc->bge_cdata.bge_stats_tag);
2437
2438         if (error) {
2439                 device_printf(sc->bge_dev, "could not allocate dma tag\n");
2440                 return (ENOMEM);
2441         }
2442
2443         /* Allocate DMA'able memory for statistics block. */
2444         error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag,
2445             (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT,
2446             &sc->bge_cdata.bge_stats_map);
2447         if (error)
2448                 return (ENOMEM);
2449
2450         bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ);
2451
2452         /* Load the address of the statstics block. */
2453         ctx.sc = sc;
2454         ctx.bge_maxsegs = 1;
2455
2456         error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag,
2457             sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats,
2458             BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2459
2460         if (error)
2461                 return (ENOMEM);
2462
2463         sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr;
2464
2465         return (0);
2466 }
2467
2468 /*
2469  * Return true if this device has more than one port.
2470  */
2471 static int
2472 bge_has_multiple_ports(struct bge_softc *sc)
2473 {
2474         device_t dev = sc->bge_dev;
2475         u_int b, d, f, fscan, s;
2476
2477         d = pci_get_domain(dev);
2478         b = pci_get_bus(dev);
2479         s = pci_get_slot(dev);
2480         f = pci_get_function(dev);
2481         for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
2482                 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
2483                         return (1);
2484         return (0);
2485 }
2486
2487 /*
2488  * Return true if MSI can be used with this device.
2489  */
2490 static int
2491 bge_can_use_msi(struct bge_softc *sc)
2492 {
2493         int can_use_msi = 0;
2494
2495         switch (sc->bge_asicrev) {
2496         case BGE_ASICREV_BCM5714_A0:
2497         case BGE_ASICREV_BCM5714:
2498                 /*
2499                  * Apparently, MSI doesn't work when these chips are
2500                  * configured in single-port mode.
2501                  */
2502                 if (bge_has_multiple_ports(sc))
2503                         can_use_msi = 1;
2504                 break;
2505         case BGE_ASICREV_BCM5750:
2506                 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
2507                     sc->bge_chiprev != BGE_CHIPREV_5750_BX)
2508                         can_use_msi = 1;
2509                 break;
2510         default:
2511                 if (BGE_IS_575X_PLUS(sc))
2512                         can_use_msi = 1;
2513         }
2514         return (can_use_msi);
2515 }
2516
2517 static int
2518 bge_attach(device_t dev)
2519 {
2520         struct ifnet *ifp;
2521         struct bge_softc *sc;
2522         uint32_t hwcfg = 0, misccfg;
2523         u_char eaddr[ETHER_ADDR_LEN];
2524         int error, msicount, reg, rid, trys;
2525
2526         sc = device_get_softc(dev);
2527         sc->bge_dev = dev;
2528
2529         TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
2530
2531         /*
2532          * Map control/status registers.
2533          */
2534         pci_enable_busmaster(dev);
2535
2536         rid = BGE_PCI_BAR0;
2537         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2538             RF_ACTIVE);
2539
2540         if (sc->bge_res == NULL) {
2541                 device_printf (sc->bge_dev, "couldn't map memory\n");
2542                 error = ENXIO;
2543                 goto fail;
2544         }
2545
2546         /* Save various chip information. */
2547         sc->bge_chipid =
2548             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2549             BGE_PCIMISCCTL_ASICREV_SHIFT;
2550         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
2551                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV,
2552                     4);
2553         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2554         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2555
2556         /*
2557          * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the
2558          * 5705 A0 and A1 chips.
2559          */
2560         if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
2561             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2562             sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2563             sc->bge_chipid != BGE_CHIPID_BCM5705_A1)
2564                 sc->bge_flags |= BGE_FLAG_WIRESPEED;
2565
2566         if (bge_has_eaddr(sc))
2567                 sc->bge_flags |= BGE_FLAG_EADDR;
2568
2569         /* Save chipset family. */
2570         switch (sc->bge_asicrev) {
2571         case BGE_ASICREV_BCM5755:
2572         case BGE_ASICREV_BCM5761:
2573         case BGE_ASICREV_BCM5784:
2574         case BGE_ASICREV_BCM5785:
2575         case BGE_ASICREV_BCM5787:
2576         case BGE_ASICREV_BCM57780:
2577                 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2578                     BGE_FLAG_5705_PLUS;
2579                 break;
2580         case BGE_ASICREV_BCM5700:
2581         case BGE_ASICREV_BCM5701:
2582         case BGE_ASICREV_BCM5703:
2583         case BGE_ASICREV_BCM5704:
2584                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2585                 break;
2586         case BGE_ASICREV_BCM5714_A0:
2587         case BGE_ASICREV_BCM5780:
2588         case BGE_ASICREV_BCM5714:
2589                 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */;
2590                 /* FALLTHROUGH */
2591         case BGE_ASICREV_BCM5750:
2592         case BGE_ASICREV_BCM5752:
2593         case BGE_ASICREV_BCM5906:
2594                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2595                 /* FALLTHROUGH */
2596         case BGE_ASICREV_BCM5705:
2597                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2598                 break;
2599         }
2600
2601         /* Set various bug flags. */
2602         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2603             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2604                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
2605         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2606             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2607                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
2608         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2609                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
2610         if (BGE_IS_5705_PLUS(sc) &&
2611             !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) {
2612                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2613                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2614                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2615                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2616                         if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
2617                             pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
2618                                 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
2619                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
2620                         sc->bge_flags |= BGE_FLAG_BER_BUG;
2621         }
2622
2623         /*
2624          * All controllers that are not 5755 or higher have 4GB
2625          * boundary DMA bug.
2626          * Whenever an address crosses a multiple of the 4GB boundary
2627          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
2628          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
2629          * state machine will lockup and cause the device to hang.
2630          */
2631         if (BGE_IS_5755_PLUS(sc) == 0)
2632                 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
2633
2634         /*
2635          * We could possibly check for BCOM_DEVICEID_BCM5788 in bge_probe()
2636          * but I do not know the DEVICEID for the 5788M.
2637          */
2638         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID;
2639         if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2640             misccfg == BGE_MISCCFG_BOARD_ID_5788M)
2641                 sc->bge_flags |= BGE_FLAG_5788;
2642
2643         /*
2644          * Some controllers seem to require a special firmware to use
2645          * TSO. But the firmware is not available to FreeBSD and Linux
2646          * claims that the TSO performed by the firmware is slower than
2647          * hardware based TSO. Moreover the firmware based TSO has one
2648          * known bug which can't handle TSO if ethernet header + IP/TCP
2649          * header is greater than 80 bytes. The workaround for the TSO
2650          * bug exist but it seems it's too expensive than not using
2651          * TSO at all. Some hardwares also have the TSO bug so limit
2652          * the TSO to the controllers that are not affected TSO issues
2653          * (e.g. 5755 or higher).
2654          */
2655         if (BGE_IS_5755_PLUS(sc)) {
2656                 /*
2657                  * BCM5754 and BCM5787 shares the same ASIC id so
2658                  * explicit device id check is required.
2659                  */
2660                 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
2661                     pci_get_device(dev) != BCOM_DEVICEID_BCM5754M)
2662                         sc->bge_flags |= BGE_FLAG_TSO;
2663         }
2664
2665         /*
2666          * Check if this is a PCI-X or PCI Express device.
2667          */
2668         if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {
2669                 /*
2670                  * Found a PCI Express capabilities register, this
2671                  * must be a PCI Express device.
2672                  */
2673                 sc->bge_flags |= BGE_FLAG_PCIE;
2674                 sc->bge_expcap = reg;
2675                 bge_set_max_readrq(sc);
2676         } else {
2677                 /*
2678                  * Check if the device is in PCI-X Mode.
2679                  * (This bit is not valid on PCI Express controllers.)
2680                  */
2681                 if (pci_find_extcap(dev, PCIY_PCIX, &reg) == 0)
2682                         sc->bge_pcixcap = reg;
2683                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
2684                     BGE_PCISTATE_PCI_BUSMODE) == 0)
2685                         sc->bge_flags |= BGE_FLAG_PCIX;
2686         }
2687
2688         /*
2689          * The 40bit DMA bug applies to the 5714/5715 controllers and is
2690          * not actually a MAC controller bug but an issue with the embedded
2691          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2692          */
2693         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
2694                 sc->bge_flags |= BGE_FLAG_40BIT_BUG;
2695         /*
2696          * Allocate the interrupt, using MSI if possible.  These devices
2697          * support 8 MSI messages, but only the first one is used in
2698          * normal operation.
2699          */
2700         rid = 0;
2701         if (pci_find_extcap(sc->bge_dev, PCIY_MSI, &reg) == 0) {
2702                 sc->bge_msicap = reg;
2703                 if (bge_can_use_msi(sc)) {
2704                         msicount = pci_msi_count(dev);
2705                         if (msicount > 1)
2706                                 msicount = 1;
2707                 } else
2708                         msicount = 0;
2709                 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) {
2710                         rid = 1;
2711                         sc->bge_flags |= BGE_FLAG_MSI;
2712                 }
2713         }
2714
2715         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2716             RF_SHAREABLE | RF_ACTIVE);
2717
2718         if (sc->bge_irq == NULL) {
2719                 device_printf(sc->bge_dev, "couldn't map interrupt\n");
2720                 error = ENXIO;
2721                 goto fail;
2722         }
2723
2724         if (bootverbose)
2725                 device_printf(dev,
2726                     "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2727                     sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2728                     (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" :
2729                     ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI"));
2730
2731         BGE_LOCK_INIT(sc, device_get_nameunit(dev));
2732
2733         /* Try to reset the chip. */
2734         if (bge_reset(sc)) {
2735                 device_printf(sc->bge_dev, "chip reset failed\n");
2736                 error = ENXIO;
2737                 goto fail;
2738         }
2739
2740         sc->bge_asf_mode = 0;
2741         if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG)
2742             == BGE_MAGIC_NUMBER)) {
2743                 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG)
2744                     & BGE_HWCFG_ASF) {
2745                         sc->bge_asf_mode |= ASF_ENABLE;
2746                         sc->bge_asf_mode |= ASF_STACKUP;
2747                         if (sc->bge_asicrev == BGE_ASICREV_BCM5750) {
2748                                 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
2749                         }
2750                 }
2751         }
2752
2753         /* Try to reset the chip again the nice way. */
2754         bge_stop_fw(sc);
2755         bge_sig_pre_reset(sc, BGE_RESET_STOP);
2756         if (bge_reset(sc)) {
2757                 device_printf(sc->bge_dev, "chip reset failed\n");
2758                 error = ENXIO;
2759                 goto fail;
2760         }
2761
2762         bge_sig_legacy(sc, BGE_RESET_STOP);
2763         bge_sig_post_reset(sc, BGE_RESET_STOP);
2764
2765         if (bge_chipinit(sc)) {
2766                 device_printf(sc->bge_dev, "chip initialization failed\n");
2767                 error = ENXIO;
2768                 goto fail;
2769         }
2770
2771         error = bge_get_eaddr(sc, eaddr);
2772         if (error) {
2773                 device_printf(sc->bge_dev,
2774                     "failed to read station address\n");
2775                 error = ENXIO;
2776                 goto fail;
2777         }
2778
2779         /* 5705 limits RX return ring to 512 entries. */
2780         if (BGE_IS_5705_PLUS(sc))
2781                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2782         else
2783                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2784
2785         if (bge_dma_alloc(dev)) {
2786                 device_printf(sc->bge_dev,
2787                     "failed to allocate DMA resources\n");
2788                 error = ENXIO;
2789                 goto fail;
2790         }
2791
2792         /* Set default tuneable values. */
2793         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2794         sc->bge_rx_coal_ticks = 150;
2795         sc->bge_tx_coal_ticks = 150;
2796         sc->bge_rx_max_coal_bds = 10;
2797         sc->bge_tx_max_coal_bds = 10;
2798
2799         /* Set up ifnet structure */
2800         ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
2801         if (ifp == NULL) {
2802                 device_printf(sc->bge_dev, "failed to if_alloc()\n");
2803                 error = ENXIO;
2804                 goto fail;
2805         }
2806         ifp->if_softc = sc;
2807         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2808         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2809         ifp->if_ioctl = bge_ioctl;
2810         ifp->if_start = bge_start;
2811         ifp->if_init = bge_init;
2812         ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1;
2813         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2814         IFQ_SET_READY(&ifp->if_snd);
2815         ifp->if_hwassist = BGE_CSUM_FEATURES;
2816         ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
2817             IFCAP_VLAN_MTU;
2818         if ((sc->bge_flags & BGE_FLAG_TSO) != 0) {
2819                 ifp->if_hwassist |= CSUM_TSO;
2820                 ifp->if_capabilities |= IFCAP_TSO4;
2821         }
2822 #ifdef IFCAP_VLAN_HWCSUM
2823         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
2824 #endif
2825         ifp->if_capenable = ifp->if_capabilities;
2826 #ifdef DEVICE_POLLING
2827         ifp->if_capabilities |= IFCAP_POLLING;
2828 #endif
2829
2830         /*
2831          * 5700 B0 chips do not support checksumming correctly due
2832          * to hardware bugs.
2833          */
2834         if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
2835                 ifp->if_capabilities &= ~IFCAP_HWCSUM;
2836                 ifp->if_capenable &= ~IFCAP_HWCSUM;
2837                 ifp->if_hwassist = 0;
2838         }
2839
2840         /*
2841          * Figure out what sort of media we have by checking the
2842          * hardware config word in the first 32k of NIC internal memory,
2843          * or fall back to examining the EEPROM if necessary.
2844          * Note: on some BCM5700 cards, this value appears to be unset.
2845          * If that's the case, we have to rely on identifying the NIC
2846          * by its PCI subsystem ID, as we do below for the SysKonnect
2847          * SK-9D41.
2848          */
2849         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2850                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2851         else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
2852             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
2853                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2854                     sizeof(hwcfg))) {
2855                         device_printf(sc->bge_dev, "failed to read EEPROM\n");
2856                         error = ENXIO;
2857                         goto fail;
2858                 }
2859                 hwcfg = ntohl(hwcfg);
2860         }
2861
2862         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2863         if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
2864             SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2865                 if (BGE_IS_5714_FAMILY(sc))
2866                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
2867                 else
2868                         sc->bge_flags |= BGE_FLAG_TBI;
2869         }
2870
2871         if (sc->bge_flags & BGE_FLAG_TBI) {
2872                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
2873                     bge_ifmedia_sts);
2874                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
2875                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2876                     0, NULL);
2877                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
2878                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
2879                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2880         } else {
2881                 /*
2882                  * Do transceiver setup and tell the firmware the
2883                  * driver is down so we can try to get access the
2884                  * probe if ASF is running.  Retry a couple of times
2885                  * if we get a conflict with the ASF firmware accessing
2886                  * the PHY.
2887                  */
2888                 trys = 0;
2889                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2890 again:
2891                 bge_asf_driver_up(sc);
2892
2893                 if (mii_phy_probe(dev, &sc->bge_miibus,
2894                     bge_ifmedia_upd, bge_ifmedia_sts)) {
2895                         if (trys++ < 4) {
2896                                 device_printf(sc->bge_dev, "Try again\n");
2897                                 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR,
2898                                     BMCR_RESET);
2899                                 goto again;
2900                         }
2901
2902                         device_printf(sc->bge_dev, "MII without any PHY!\n");
2903                         error = ENXIO;
2904                         goto fail;
2905                 }
2906
2907                 /*
2908                  * Now tell the firmware we are going up after probing the PHY
2909                  */
2910                 if (sc->bge_asf_mode & ASF_STACKUP)
2911                         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2912         }
2913
2914         /*
2915          * When using the BCM5701 in PCI-X mode, data corruption has
2916          * been observed in the first few bytes of some received packets.
2917          * Aligning the packet buffer in memory eliminates the corruption.
2918          * Unfortunately, this misaligns the packet payloads.  On platforms
2919          * which do not support unaligned accesses, we will realign the
2920          * payloads by copying the received packets.
2921          */
2922         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2923             sc->bge_flags & BGE_FLAG_PCIX)
2924                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2925
2926         /*
2927          * Call MI attach routine.
2928          */
2929         ether_ifattach(ifp, eaddr);
2930         callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
2931
2932         /* Tell upper layer we support long frames. */
2933         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2934
2935         /*
2936          * Hookup IRQ last.
2937          */
2938 #if __FreeBSD_version > 700030
2939         if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
2940                 /* Take advantage of single-shot MSI. */
2941                 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
2942                     ~BGE_MSIMODE_ONE_SHOT_DISABLE);
2943                 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
2944                     taskqueue_thread_enqueue, &sc->bge_tq);
2945                 if (sc->bge_tq == NULL) {
2946                         device_printf(dev, "could not create taskqueue.\n");
2947                         ether_ifdetach(ifp);
2948                         error = ENXIO;
2949                         goto fail;
2950                 }
2951                 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq",
2952                     device_get_nameunit(sc->bge_dev));
2953                 error = bus_setup_intr(dev, sc->bge_irq,
2954                     INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
2955                     &sc->bge_intrhand);
2956                 if (error)
2957                         ether_ifdetach(ifp);
2958         } else
2959                 error = bus_setup_intr(dev, sc->bge_irq,
2960                     INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
2961                     &sc->bge_intrhand);
2962 #else
2963         error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE,
2964            bge_intr, sc, &sc->bge_intrhand);
2965 #endif
2966
2967         if (error) {
2968                 bge_detach(dev);
2969                 device_printf(sc->bge_dev, "couldn't set up irq\n");
2970         }
2971
2972         bge_add_sysctls(sc);
2973
2974         return (0);
2975
2976 fail:
2977         bge_release_resources(sc);
2978
2979         return (error);
2980 }
2981
2982 static int
2983 bge_detach(device_t dev)
2984 {
2985         struct bge_softc *sc;
2986         struct ifnet *ifp;
2987
2988         sc = device_get_softc(dev);
2989         ifp = sc->bge_ifp;
2990
2991 #ifdef DEVICE_POLLING
2992         if (ifp->if_capenable & IFCAP_POLLING)
2993                 ether_poll_deregister(ifp);
2994 #endif
2995
2996         BGE_LOCK(sc);
2997         bge_stop(sc);
2998         bge_reset(sc);
2999         BGE_UNLOCK(sc);
3000
3001         callout_drain(&sc->bge_stat_ch);
3002
3003         if (sc->bge_tq)
3004                 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3005         ether_ifdetach(ifp);
3006
3007         if (sc->bge_flags & BGE_FLAG_TBI) {
3008                 ifmedia_removeall(&sc->bge_ifmedia);
3009         } else {
3010                 bus_generic_detach(dev);
3011                 device_delete_child(dev, sc->bge_miibus);
3012         }
3013
3014         bge_release_resources(sc);
3015
3016         return (0);
3017 }
3018
3019 static void
3020 bge_release_resources(struct bge_softc *sc)
3021 {
3022         device_t dev;
3023
3024         dev = sc->bge_dev;
3025
3026         if (sc->bge_tq != NULL)
3027                 taskqueue_free(sc->bge_tq);
3028
3029         if (sc->bge_intrhand != NULL)
3030                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3031
3032         if (sc->bge_irq != NULL)
3033                 bus_release_resource(dev, SYS_RES_IRQ,
3034                     sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq);
3035
3036         if (sc->bge_flags & BGE_FLAG_MSI)
3037                 pci_release_msi(dev);
3038
3039         if (sc->bge_res != NULL)
3040                 bus_release_resource(dev, SYS_RES_MEMORY,
3041                     BGE_PCI_BAR0, sc->bge_res);
3042
3043         if (sc->bge_ifp != NULL)
3044                 if_free(sc->bge_ifp);
3045
3046         bge_dma_free(sc);
3047
3048         if (mtx_initialized(&sc->bge_mtx))      /* XXX */
3049                 BGE_LOCK_DESTROY(sc);
3050 }
3051
3052 static int
3053 bge_reset(struct bge_softc *sc)
3054 {
3055         device_t dev;
3056         uint32_t cachesize, command, pcistate, reset, val;
3057         void (*write_op)(struct bge_softc *, int, int);
3058         uint16_t devctl;
3059         int i;
3060
3061         dev = sc->bge_dev;
3062
3063         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
3064             (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3065                 if (sc->bge_flags & BGE_FLAG_PCIE)
3066                         write_op = bge_writemem_direct;
3067                 else
3068                         write_op = bge_writemem_ind;
3069         } else
3070                 write_op = bge_writereg_ind;
3071
3072         /* Save some important PCI state. */
3073         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
3074         command = pci_read_config(dev, BGE_PCI_CMD, 4);
3075         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3076
3077         pci_write_config(dev, BGE_PCI_MISC_CTL,
3078             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3079             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3080
3081         /* Disable fastboot on controllers that support it. */
3082         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
3083             BGE_IS_5755_PLUS(sc)) {
3084                 if (bootverbose)
3085                         device_printf(sc->bge_dev, "Disabling fastboot\n");
3086                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
3087         }
3088
3089         /*
3090          * Write the magic number to SRAM at offset 0xB50.
3091          * When firmware finishes its initialization it will
3092          * write ~BGE_MAGIC_NUMBER to the same location.
3093          */
3094         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
3095
3096         reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
3097
3098         /* XXX: Broadcom Linux driver. */
3099         if (sc->bge_flags & BGE_FLAG_PCIE) {
3100                 if (CSR_READ_4(sc, 0x7E2C) == 0x60)     /* PCIE 1.0 */
3101                         CSR_WRITE_4(sc, 0x7E2C, 0x20);
3102                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3103                         /* Prevent PCIE link training during global reset */
3104                         CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
3105                         reset |= 1 << 29;
3106                 }
3107         }
3108
3109         /*
3110          * Set GPHY Power Down Override to leave GPHY
3111          * powered up in D0 uninitialized.
3112          */
3113         if (BGE_IS_5705_PLUS(sc))
3114                 reset |= 0x04000000;
3115
3116         /* Issue global reset */
3117         write_op(sc, BGE_MISC_CFG, reset);
3118
3119         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3120                 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3121                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
3122                     val | BGE_VCPU_STATUS_DRV_RESET);
3123                 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
3124                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
3125                     val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
3126         }
3127
3128         DELAY(1000);
3129
3130         /* XXX: Broadcom Linux driver. */
3131         if (sc->bge_flags & BGE_FLAG_PCIE) {
3132                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
3133                         DELAY(500000); /* wait for link training to complete */
3134                         val = pci_read_config(dev, 0xC4, 4);
3135                         pci_write_config(dev, 0xC4, val | (1 << 15), 4);
3136                 }
3137                 devctl = pci_read_config(dev,
3138                     sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2);
3139                 /* Clear enable no snoop and disable relaxed ordering. */
3140                 devctl &= ~(0x0010 | 0x0800);
3141                 /* Set PCIE max payload size to 128. */
3142                 devctl &= ~PCIM_EXP_CTL_MAX_PAYLOAD;
3143                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL,
3144                     devctl, 2);
3145                 /* Clear error status. */
3146                 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA,
3147                     0, 2);
3148         }
3149
3150         /* Reset some of the PCI state that got zapped by reset. */
3151         pci_write_config(dev, BGE_PCI_MISC_CTL,
3152             BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
3153             BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
3154         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
3155         pci_write_config(dev, BGE_PCI_CMD, command, 4);
3156         write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
3157
3158         /* Re-enable MSI, if neccesary, and enable the memory arbiter. */
3159         if (BGE_IS_5714_FAMILY(sc)) {
3160                 /* This chip disables MSI on reset. */
3161                 if (sc->bge_flags & BGE_FLAG_MSI) {
3162                         val = pci_read_config(dev,
3163                             sc->bge_msicap + PCIR_MSI_CTRL, 2);
3164                         pci_write_config(dev,
3165                             sc->bge_msicap + PCIR_MSI_CTRL,
3166                             val | PCIM_MSICTRL_MSI_ENABLE, 2);
3167                         val = CSR_READ_4(sc, BGE_MSI_MODE);
3168                         CSR_WRITE_4(sc, BGE_MSI_MODE,
3169                             val | BGE_MSIMODE_ENABLE);
3170                 }
3171                 val = CSR_READ_4(sc, BGE_MARB_MODE);
3172                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
3173         } else
3174                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3175
3176         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3177                 for (i = 0; i < BGE_TIMEOUT; i++) {
3178                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
3179                         if (val & BGE_VCPU_STATUS_INIT_DONE)
3180                                 break;
3181                         DELAY(100);
3182                 }
3183                 if (i == BGE_TIMEOUT) {
3184                         device_printf(sc->bge_dev, "reset timed out\n");
3185                         return (1);
3186                 }
3187         } else {
3188                 /*
3189                  * Poll until we see the 1's complement of the magic number.
3190                  * This indicates that the firmware initialization is complete.
3191                  * We expect this to fail if no chip containing the Ethernet
3192                  * address is fitted though.
3193                  */
3194                 for (i = 0; i < BGE_TIMEOUT; i++) {
3195                         DELAY(10);
3196                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
3197                         if (val == ~BGE_MAGIC_NUMBER)
3198                                 break;
3199                 }
3200
3201                 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
3202                         device_printf(sc->bge_dev, "firmware handshake timed out, "
3203                             "found 0x%08x\n", val);
3204         }
3205
3206         /*
3207          * XXX Wait for the value of the PCISTATE register to
3208          * return to its original pre-reset state. This is a
3209          * fairly good indicator of reset completion. If we don't
3210          * wait for the reset to fully complete, trying to read
3211          * from the device's non-PCI registers may yield garbage
3212          * results.
3213          */
3214         for (i = 0; i < BGE_TIMEOUT; i++) {
3215                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
3216                         break;
3217                 DELAY(10);
3218         }
3219
3220         if (sc->bge_flags & BGE_FLAG_PCIE) {
3221                 reset = bge_readmem_ind(sc, 0x7C00);
3222                 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25));
3223         }
3224
3225         /* Fix up byte swapping. */
3226         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
3227             BGE_MODECTL_BYTESWAP_DATA);
3228
3229         /* Tell the ASF firmware we are up */
3230         if (sc->bge_asf_mode & ASF_STACKUP)
3231                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3232
3233         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
3234
3235         /*
3236          * The 5704 in TBI mode apparently needs some special
3237          * adjustment to insure the SERDES drive level is set
3238          * to 1.2V.
3239          */
3240         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
3241             sc->bge_flags & BGE_FLAG_TBI) {
3242                 val = CSR_READ_4(sc, BGE_SERDES_CFG);
3243                 val = (val & ~0xFFF) | 0x880;
3244                 CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
3245         }
3246
3247         /* XXX: Broadcom Linux driver. */
3248         if (sc->bge_flags & BGE_FLAG_PCIE &&
3249             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
3250                 val = CSR_READ_4(sc, 0x7C00);
3251                 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
3252         }
3253         DELAY(10000);
3254
3255         return(0);
3256 }
3257
3258 /*
3259  * Frame reception handling. This is called if there's a frame
3260  * on the receive return list.
3261  *
3262  * Note: we have to be able to handle two possibilities here:
3263  * 1) the frame is from the jumbo receive ring
3264  * 2) the frame is from the standard receive ring
3265  */
3266
3267 static int
3268 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
3269 {
3270         struct ifnet *ifp;
3271         int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
3272         uint16_t rx_cons;
3273
3274         rx_cons = sc->bge_rx_saved_considx;
3275
3276         /* Nothing to do. */
3277         if (rx_cons == rx_prod)
3278                 return (rx_npkts);
3279
3280         ifp = sc->bge_ifp;
3281
3282         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3283             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
3284         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3285             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
3286         if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
3287             (MCLBYTES - ETHER_ALIGN))
3288                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3289                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
3290
3291         while (rx_cons != rx_prod) {
3292                 struct bge_rx_bd        *cur_rx;
3293                 uint32_t                rxidx;
3294                 struct mbuf             *m = NULL;
3295                 uint16_t                vlan_tag = 0;
3296                 int                     have_tag = 0;
3297
3298 #ifdef DEVICE_POLLING
3299                 if (ifp->if_capenable & IFCAP_POLLING) {
3300                         if (sc->rxcycles <= 0)
3301                                 break;
3302                         sc->rxcycles--;
3303                 }
3304 #endif
3305
3306                 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
3307
3308                 rxidx = cur_rx->bge_idx;
3309                 BGE_INC(rx_cons, sc->bge_return_ring_cnt);
3310
3311                 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING &&
3312                     cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
3313                         have_tag = 1;
3314                         vlan_tag = cur_rx->bge_vlan_tag;
3315                 }
3316
3317                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
3318                         jumbocnt++;
3319                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
3320                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3321                                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3322                                 continue;
3323                         }
3324                         if (bge_newbuf_jumbo(sc, rxidx) != 0) {
3325                                 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3326                                 ifp->if_iqdrops++;
3327                                 continue;
3328                         }
3329                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3330                 } else {
3331                         stdcnt++;
3332                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3333                                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3334                                 continue;
3335                         }
3336                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
3337                         if (bge_newbuf_std(sc, rxidx) != 0) {
3338                                 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3339                                 ifp->if_iqdrops++;
3340                                 continue;
3341                         }
3342                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3343                 }
3344
3345                 ifp->if_ipackets++;
3346 #ifndef __NO_STRICT_ALIGNMENT
3347                 /*
3348                  * For architectures with strict alignment we must make sure
3349                  * the payload is aligned.
3350                  */
3351                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
3352                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
3353                             cur_rx->bge_len);
3354                         m->m_data += ETHER_ALIGN;
3355                 }
3356 #endif
3357                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3358                 m->m_pkthdr.rcvif = ifp;
3359
3360                 if (ifp->if_capenable & IFCAP_RXCSUM) {
3361                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3362                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3363                                 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
3364                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3365                         }
3366                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
3367                             m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
3368                                 m->m_pkthdr.csum_data =
3369                                     cur_rx->bge_tcp_udp_csum;
3370                                 m->m_pkthdr.csum_flags |=
3371                                     CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
3372                         }
3373                 }
3374
3375                 /*
3376                  * If we received a packet with a vlan tag,
3377                  * attach that information to the packet.
3378                  */
3379                 if (have_tag) {
3380 #if __FreeBSD_version > 700022
3381                         m->m_pkthdr.ether_vtag = vlan_tag;
3382                         m->m_flags |= M_VLANTAG;
3383 #else
3384                         VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag);
3385                         if (m == NULL)
3386                                 continue;
3387 #endif
3388                 }
3389
3390                 if (holdlck != 0) {
3391                         BGE_UNLOCK(sc);
3392                         (*ifp->if_input)(ifp, m);
3393                         BGE_LOCK(sc);
3394                 } else
3395                         (*ifp->if_input)(ifp, m);
3396                 rx_npkts++;
3397
3398                 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
3399                         return (rx_npkts);
3400         }
3401
3402         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
3403             sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
3404         if (stdcnt > 0)
3405                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
3406                     sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
3407
3408         if (jumbocnt > 0)
3409                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
3410                     sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
3411
3412         sc->bge_rx_saved_considx = rx_cons;
3413         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3414         if (stdcnt)
3415                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
3416         if (jumbocnt)
3417                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
3418 #ifdef notyet
3419         /*
3420          * This register wraps very quickly under heavy packet drops.
3421          * If you need correct statistics, you can enable this check.
3422          */
3423         if (BGE_IS_5705_PLUS(sc))
3424                 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3425 #endif
3426         return (rx_npkts);
3427 }
3428
3429 static void
3430 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
3431 {
3432         struct bge_tx_bd *cur_tx = NULL;
3433         struct ifnet *ifp;
3434
3435         BGE_LOCK_ASSERT(sc);
3436
3437         /* Nothing to do. */
3438         if (sc->bge_tx_saved_considx == tx_cons)
3439                 return;
3440
3441         ifp = sc->bge_ifp;
3442
3443         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
3444             sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
3445         /*
3446          * Go through our tx ring and free mbufs for those
3447          * frames that have been sent.
3448          */
3449         while (sc->bge_tx_saved_considx != tx_cons) {
3450                 uint32_t                idx = 0;
3451
3452                 idx = sc->bge_tx_saved_considx;
3453                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
3454                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
3455                         ifp->if_opackets++;
3456                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
3457                         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
3458                             sc->bge_cdata.bge_tx_dmamap[idx],
3459                             BUS_DMASYNC_POSTWRITE);
3460                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
3461                             sc->bge_cdata.bge_tx_dmamap[idx]);
3462                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
3463                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
3464                 }
3465                 sc->bge_txcnt--;
3466                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3467         }
3468
3469         if (cur_tx != NULL)
3470                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3471         if (sc->bge_txcnt == 0)
3472                 sc->bge_timer = 0;
3473 }
3474
3475 #ifdef DEVICE_POLLING
3476 static int
3477 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3478 {
3479         struct bge_softc *sc = ifp->if_softc;
3480         uint16_t rx_prod, tx_cons;
3481         uint32_t statusword;
3482         int rx_npkts = 0;
3483
3484         BGE_LOCK(sc);
3485         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3486                 BGE_UNLOCK(sc);
3487                 return (rx_npkts);
3488         }
3489
3490         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3491             sc->bge_cdata.bge_status_map,
3492             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3493         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3494         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3495
3496         statusword = atomic_readandclear_32(
3497             &sc->bge_ldata.bge_status_block->bge_status);
3498
3499         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3500             sc->bge_cdata.bge_status_map,
3501             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3502
3503         /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
3504         if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
3505                 sc->bge_link_evt++;
3506
3507         if (cmd == POLL_AND_CHECK_STATUS)
3508                 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3509                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3510                     sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
3511                         bge_link_upd(sc);
3512
3513         sc->rxcycles = count;
3514         rx_npkts = bge_rxeof(sc, rx_prod, 1);
3515         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3516                 BGE_UNLOCK(sc);
3517                 return (rx_npkts);
3518         }
3519         bge_txeof(sc, tx_cons);
3520         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3521                 bge_start_locked(ifp);
3522
3523         BGE_UNLOCK(sc);
3524         return (rx_npkts);
3525 }
3526 #endif /* DEVICE_POLLING */
3527
3528 static int
3529 bge_msi_intr(void *arg)
3530 {
3531         struct bge_softc *sc;
3532
3533         sc = (struct bge_softc *)arg;
3534         /*
3535          * This interrupt is not shared and controller already
3536          * disabled further interrupt.
3537          */
3538         taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
3539         return (FILTER_HANDLED);
3540 }
3541
3542 static void
3543 bge_intr_task(void *arg, int pending)
3544 {
3545         struct bge_softc *sc;
3546         struct ifnet *ifp;
3547         uint32_t status;
3548         uint16_t rx_prod, tx_cons;
3549
3550         sc = (struct bge_softc *)arg;
3551         ifp = sc->bge_ifp;
3552
3553         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3554                 return;
3555
3556         /* Get updated status block. */
3557         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3558             sc->bge_cdata.bge_status_map,
3559             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3560
3561         /* Save producer/consumer indexess. */
3562         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3563         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3564         status = sc->bge_ldata.bge_status_block->bge_status;
3565         sc->bge_ldata.bge_status_block->bge_status = 0;
3566         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3567             sc->bge_cdata.bge_status_map,
3568             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3569         /* Let controller work. */
3570         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3571
3572         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) {
3573                 BGE_LOCK(sc);
3574                 bge_link_upd(sc);
3575                 BGE_UNLOCK(sc);
3576         }
3577         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3578                 /* Check RX return ring producer/consumer. */
3579                 bge_rxeof(sc, rx_prod, 0);
3580         }
3581         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3582                 BGE_LOCK(sc);
3583                 /* Check TX ring producer/consumer. */
3584                 bge_txeof(sc, tx_cons);
3585                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3586                         bge_start_locked(ifp);
3587                 BGE_UNLOCK(sc);
3588         }
3589 }
3590
3591 static void
3592 bge_intr(void *xsc)
3593 {
3594         struct bge_softc *sc;
3595         struct ifnet *ifp;
3596         uint32_t statusword;
3597         uint16_t rx_prod, tx_cons;
3598
3599         sc = xsc;
3600
3601         BGE_LOCK(sc);
3602
3603         ifp = sc->bge_ifp;
3604
3605 #ifdef DEVICE_POLLING
3606         if (ifp->if_capenable & IFCAP_POLLING) {
3607                 BGE_UNLOCK(sc);
3608                 return;
3609         }
3610 #endif
3611
3612         /*
3613          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
3614          * disable interrupts by writing nonzero like we used to, since with
3615          * our current organization this just gives complications and
3616          * pessimizations for re-enabling interrupts.  We used to have races
3617          * instead of the necessary complications.  Disabling interrupts
3618          * would just reduce the chance of a status update while we are
3619          * running (by switching to the interrupt-mode coalescence
3620          * parameters), but this chance is already very low so it is more
3621          * efficient to get another interrupt than prevent it.
3622          *
3623          * We do the ack first to ensure another interrupt if there is a
3624          * status update after the ack.  We don't check for the status
3625          * changing later because it is more efficient to get another
3626          * interrupt than prevent it, not quite as above (not checking is
3627          * a smaller optimization than not toggling the interrupt enable,
3628          * since checking doesn't involve PCI accesses and toggling require
3629          * the status check).  So toggling would probably be a pessimization
3630          * even with MSI.  It would only be needed for using a task queue.
3631          */
3632         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3633
3634         /*
3635          * Do the mandatory PCI flush as well as get the link status.
3636          */
3637         statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
3638
3639         /* Make sure the descriptor ring indexes are coherent. */
3640         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3641             sc->bge_cdata.bge_status_map,
3642             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3643         rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
3644         tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
3645         sc->bge_ldata.bge_status_block->bge_status = 0;
3646         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
3647             sc->bge_cdata.bge_status_map,
3648             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3649
3650         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
3651             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
3652             statusword || sc->bge_link_evt)
3653                 bge_link_upd(sc);
3654
3655         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3656                 /* Check RX return ring producer/consumer. */
3657                 bge_rxeof(sc, rx_prod, 1);
3658         }
3659
3660         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3661                 /* Check TX ring producer/consumer. */
3662                 bge_txeof(sc, tx_cons);
3663         }
3664
3665         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3666             !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3667                 bge_start_locked(ifp);
3668
3669         BGE_UNLOCK(sc);
3670 }
3671
3672 static void
3673 bge_asf_driver_up(struct bge_softc *sc)
3674 {
3675         if (sc->bge_asf_mode & ASF_STACKUP) {
3676                 /* Send ASF heartbeat aprox. every 2s */
3677                 if (sc->bge_asf_count)
3678                         sc->bge_asf_count --;
3679                 else {
3680                         sc->bge_asf_count = 5;
3681                         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW,
3682                             BGE_FW_DRV_ALIVE);
3683                         bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4);
3684                         bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3);
3685                         CSR_WRITE_4(sc, BGE_CPU_EVENT,
3686                             CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
3687                 }
3688         }
3689 }
3690
3691 static void
3692 bge_tick(void *xsc)
3693 {
3694         struct bge_softc *sc = xsc;
3695         struct mii_data *mii = NULL;
3696
3697         BGE_LOCK_ASSERT(sc);
3698
3699         /* Synchronize with possible callout reset/stop. */
3700         if (callout_pending(&sc->bge_stat_ch) ||
3701             !callout_active(&sc->bge_stat_ch))
3702                 return;
3703
3704         if (BGE_IS_5705_PLUS(sc))
3705                 bge_stats_update_regs(sc);
3706         else
3707                 bge_stats_update(sc);
3708
3709         if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
3710                 mii = device_get_softc(sc->bge_miibus);
3711                 /*
3712                  * Do not touch PHY if we have link up. This could break
3713                  * IPMI/ASF mode or produce extra input errors
3714                  * (extra errors was reported for bcm5701 & bcm5704).
3715                  */
3716                 if (!sc->bge_link)
3717                         mii_tick(mii);
3718         } else {
3719                 /*
3720                  * Since in TBI mode auto-polling can't be used we should poll
3721                  * link status manually. Here we register pending link event
3722                  * and trigger interrupt.
3723                  */
3724 #ifdef DEVICE_POLLING
3725                 /* In polling mode we poll link state in bge_poll(). */
3726                 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING))
3727 #endif
3728                 {
3729                 sc->bge_link_evt++;
3730                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3731                     sc->bge_flags & BGE_FLAG_5788)
3732                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3733                 else
3734                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3735                 }
3736         }
3737
3738         bge_asf_driver_up(sc);
3739         bge_watchdog(sc);
3740
3741         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
3742 }
3743
3744 static void
3745 bge_stats_update_regs(struct bge_softc *sc)
3746 {
3747         struct ifnet *ifp;
3748
3749         ifp = sc->bge_ifp;
3750
3751         ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS +
3752             offsetof(struct bge_mac_stats_regs, etherStatsCollisions));
3753
3754         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
3755         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
3756         ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
3757 }
3758
3759 static void
3760 bge_stats_update(struct bge_softc *sc)
3761 {
3762         struct ifnet *ifp;
3763         bus_size_t stats;
3764         uint32_t cnt;   /* current register value */
3765
3766         ifp = sc->bge_ifp;
3767
3768         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3769
3770 #define READ_STAT(sc, stats, stat) \
3771         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3772
3773         cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
3774         ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions);
3775         sc->bge_tx_collisions = cnt;
3776
3777         cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
3778         ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards);
3779         sc->bge_rx_discards = cnt;
3780
3781         cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
3782         ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards);
3783         sc->bge_tx_discards = cnt;
3784
3785 #undef  READ_STAT
3786 }
3787
3788 /*
3789  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
3790  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
3791  * but when such padded frames employ the bge IP/TCP checksum offload,
3792  * the hardware checksum assist gives incorrect results (possibly
3793  * from incorporating its own padding into the UDP/TCP checksum; who knows).
3794  * If we pad such runts with zeros, the onboard checksum comes out correct.
3795  */
3796 static __inline int
3797 bge_cksum_pad(struct mbuf *m)
3798 {
3799         int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
3800         struct mbuf *last;
3801
3802         /* If there's only the packet-header and we can pad there, use it. */
3803         if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
3804             M_TRAILINGSPACE(m) >= padlen) {
3805                 last = m;
3806         } else {
3807                 /*
3808                  * Walk packet chain to find last mbuf. We will either
3809                  * pad there, or append a new mbuf and pad it.
3810                  */
3811                 for (last = m; last->m_next != NULL; last = last->m_next);
3812                 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
3813                         /* Allocate new empty mbuf, pad it. Compact later. */
3814                         struct mbuf *n;
3815
3816                         MGET(n, M_DONTWAIT, MT_DATA);
3817                         if (n == NULL)
3818                                 return (ENOBUFS);
3819                         n->m_len = 0;
3820                         last->m_next = n;
3821                         last = n;
3822                 }
3823         }
3824
3825         /* Now zero the pad area, to avoid the bge cksum-assist bug. */
3826         memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
3827         last->m_len += padlen;
3828         m->m_pkthdr.len += padlen;
3829
3830         return (0);
3831 }
3832
3833 static struct mbuf *
3834 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss)
3835 {
3836         struct ether_header *eh;
3837         struct ip *ip;
3838         struct tcphdr *tcp;
3839         struct mbuf *n;
3840         uint16_t hlen;
3841         uint32_t ip_off, poff;
3842
3843         if (M_WRITABLE(m) == 0) {
3844                 /* Get a writable copy. */
3845                 n = m_dup(m, M_DONTWAIT);
3846                 m_freem(m);
3847                 if (n == NULL)
3848                         return (NULL);
3849                 m = n;
3850         }
3851         ip_off = sizeof(struct ether_header);
3852         m = m_pullup(m, ip_off);
3853         if (m == NULL)
3854                 return (NULL);
3855         eh = mtod(m, struct ether_header *);
3856         /* Check the existence of VLAN tag. */
3857         if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
3858                 ip_off = sizeof(struct ether_vlan_header);
3859                 m = m_pullup(m, ip_off);
3860                 if (m == NULL)
3861                         return (NULL);
3862         }
3863         m = m_pullup(m, ip_off + sizeof(struct ip));
3864         if (m == NULL)
3865                 return (NULL);
3866         ip = (struct ip *)(mtod(m, char *) + ip_off);
3867         poff = ip_off + (ip->ip_hl << 2);
3868         m = m_pullup(m, poff + sizeof(struct tcphdr));
3869         if (m == NULL)
3870                 return (NULL);
3871         tcp = (struct tcphdr *)(mtod(m, char *) + poff);
3872         m = m_pullup(m, poff + sizeof(struct tcphdr) + tcp->th_off);
3873         if (m == NULL)
3874                 return (NULL);
3875         /*
3876          * It seems controller doesn't modify IP length and TCP pseudo
3877          * checksum. These checksum computed by upper stack should be 0.
3878          */
3879         *mss = m->m_pkthdr.tso_segsz;
3880         ip->ip_sum = 0;
3881         ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
3882         /* Clear pseudo checksum computed by TCP stack. */
3883         tcp->th_sum = 0;
3884         /*
3885          * Broadcom controllers uses different descriptor format for
3886          * TSO depending on ASIC revision. Due to TSO-capable firmware
3887          * license issue and lower performance of firmware based TSO
3888          * we only support hardware based TSO which is applicable for
3889          * BCM5755 or newer controllers. Hardware based TSO uses 11
3890          * bits to store MSS and upper 5 bits are used to store IP/TCP
3891          * header length(including IP/TCP options). The header length
3892          * is expressed as 32 bits unit.
3893          */
3894         hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
3895         *mss |= (hlen << 11);
3896         return (m);
3897 }
3898
3899 /*
3900  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
3901  * pointers to descriptors.
3902  */
3903 static int
3904 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
3905 {
3906         bus_dma_segment_t       segs[BGE_NSEG_NEW];
3907         bus_dmamap_t            map;
3908         struct bge_tx_bd        *d;
3909         struct mbuf             *m = *m_head;
3910         uint32_t                idx = *txidx;
3911         uint16_t                csum_flags, mss, vlan_tag;
3912         int                     nsegs, i, error;
3913
3914         csum_flags = 0;
3915         mss = 0;
3916         vlan_tag = 0;
3917         if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
3918                 *m_head = m = bge_setup_tso(sc, m, &mss);
3919                 if (*m_head == NULL)
3920                         return (ENOBUFS);
3921                 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
3922                     BGE_TXBDFLAG_CPU_POST_DMA;
3923         } else if ((m->m_pkthdr.csum_flags & BGE_CSUM_FEATURES) != 0) {
3924                 if (m->m_pkthdr.csum_flags & CSUM_IP)
3925                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3926                 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
3927                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3928                         if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
3929                             (error = bge_cksum_pad(m)) != 0) {
3930                                 m_freem(m);
3931                                 *m_head = NULL;
3932                                 return (error);
3933                         }
3934                 }
3935                 if (m->m_flags & M_LASTFRAG)
3936                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3937                 else if (m->m_flags & M_FRAG)
3938                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3939         }
3940
3941         if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
3942             sc->bge_forced_collapse > 0 &&
3943             (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
3944                 /*
3945                  * Forcedly collapse mbuf chains to overcome hardware
3946                  * limitation which only support a single outstanding
3947                  * DMA read operation.
3948                  */
3949                 if (sc->bge_forced_collapse == 1)
3950                         m = m_defrag(m, M_DONTWAIT);
3951                 else
3952                         m = m_collapse(m, M_DONTWAIT, sc->bge_forced_collapse);
3953                 if (m == NULL) {
3954                         m_freem(*m_head);
3955                         *m_head = NULL;
3956                         return (ENOBUFS);
3957                 }
3958                 *m_head = m;
3959         }
3960
3961         map = sc->bge_cdata.bge_tx_dmamap[idx];
3962         error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
3963             &nsegs, BUS_DMA_NOWAIT);
3964         if (error == EFBIG) {
3965                 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW);
3966                 if (m == NULL) {
3967                         m_freem(*m_head);
3968                         *m_head = NULL;
3969                         return (ENOBUFS);
3970                 }
3971                 *m_head = m;
3972                 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
3973                     m, segs, &nsegs, BUS_DMA_NOWAIT);
3974                 if (error) {
3975                         m_freem(m);
3976                         *m_head = NULL;
3977                         return (error);
3978                 }
3979         } else if (error != 0)
3980                 return (error);
3981
3982         /* Check if we have enough free send BDs. */
3983         if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
3984                 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
3985                 return (ENOBUFS);
3986         }
3987
3988         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3989
3990 #if __FreeBSD_version > 700022
3991         if (m->m_flags & M_VLANTAG) {
3992                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
3993                 vlan_tag = m->m_pkthdr.ether_vtag;
3994         }
3995 #else
3996         {
3997                 struct m_tag            *mtag;
3998
3999                 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) {
4000                         csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
4001                         vlan_tag = VLAN_TAG_VALUE(mtag);
4002                 }
4003         }
4004 #endif
4005         for (i = 0; ; i++) {
4006                 d = &sc->bge_ldata.bge_tx_ring[idx];
4007                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
4008                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
4009                 d->bge_len = segs[i].ds_len;
4010                 d->bge_flags = csum_flags;
4011                 d->bge_vlan_tag = vlan_tag;
4012                 d->bge_mss = mss;
4013                 if (i == nsegs - 1)
4014                         break;
4015                 BGE_INC(idx, BGE_TX_RING_CNT);
4016         }
4017
4018         /* Mark the last segment as end of packet... */
4019         d->bge_flags |= BGE_TXBDFLAG_END;
4020
4021         /*
4022          * Insure that the map for this transmission
4023          * is placed at the array index of the last descriptor
4024          * in this chain.
4025          */
4026         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
4027         sc->bge_cdata.bge_tx_dmamap[idx] = map;
4028         sc->bge_cdata.bge_tx_chain[idx] = m;
4029         sc->bge_txcnt += nsegs;
4030
4031         BGE_INC(idx, BGE_TX_RING_CNT);
4032         *txidx = idx;
4033
4034         return (0);
4035 }
4036
4037 /*
4038  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4039  * to the mbuf data regions directly in the transmit descriptors.
4040  */
4041 static void
4042 bge_start_locked(struct ifnet *ifp)
4043 {
4044         struct bge_softc *sc;
4045         struct mbuf *m_head;
4046         uint32_t prodidx;
4047         int count;
4048
4049         sc = ifp->if_softc;
4050         BGE_LOCK_ASSERT(sc);
4051
4052         if (!sc->bge_link ||
4053             (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4054             IFF_DRV_RUNNING)
4055                 return;
4056
4057         prodidx = sc->bge_tx_prodidx;
4058
4059         for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) {
4060                 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
4061                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4062                         break;
4063                 }
4064                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
4065                 if (m_head == NULL)
4066                         break;
4067
4068                 /*
4069                  * XXX
4070                  * The code inside the if() block is never reached since we
4071                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
4072                  * requests to checksum TCP/UDP in a fragmented packet.
4073                  *
4074                  * XXX
4075                  * safety overkill.  If this is a fragmented packet chain
4076                  * with delayed TCP/UDP checksums, then only encapsulate
4077                  * it if we have enough descriptors to handle the entire
4078                  * chain at once.
4079                  * (paranoia -- may not actually be needed)
4080                  */
4081                 if (m_head->m_flags & M_FIRSTFRAG &&
4082                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
4083                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
4084                             m_head->m_pkthdr.csum_data + 16) {
4085                                 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4086                                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4087                                 break;
4088                         }
4089                 }
4090
4091                 /*
4092                  * Pack the data into the transmit ring. If we
4093                  * don't have room, set the OACTIVE flag and wait
4094                  * for the NIC to drain the ring.
4095                  */
4096                 if (bge_encap(sc, &m_head, &prodidx)) {
4097                         if (m_head == NULL)
4098                                 break;
4099                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
4100                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4101                         break;
4102                 }
4103                 ++count;
4104
4105                 /*
4106                  * If there's a BPF listener, bounce a copy of this frame
4107                  * to him.
4108                  */
4109 #ifdef ETHER_BPF_MTAP
4110                 ETHER_BPF_MTAP(ifp, m_head);
4111 #else
4112                 BPF_MTAP(ifp, m_head);
4113 #endif
4114         }
4115
4116         if (count > 0) {
4117                 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4118                     sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
4119                 /* Transmit. */
4120                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4121                 /* 5700 b2 errata */
4122                 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
4123                         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
4124
4125                 sc->bge_tx_prodidx = prodidx;
4126
4127                 /*
4128                  * Set a timeout in case the chip goes out to lunch.
4129                  */
4130                 sc->bge_timer = 5;
4131         }
4132 }
4133
4134 /*
4135  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
4136  * to the mbuf data regions directly in the transmit descriptors.
4137  */
4138 static void
4139 bge_start(struct ifnet *ifp)
4140 {
4141         struct bge_softc *sc;
4142
4143         sc = ifp->if_softc;
4144         BGE_LOCK(sc);
4145         bge_start_locked(ifp);
4146         BGE_UNLOCK(sc);
4147 }
4148
4149 static void
4150 bge_init_locked(struct bge_softc *sc)
4151 {
4152         struct ifnet *ifp;
4153         uint16_t *m;
4154
4155         BGE_LOCK_ASSERT(sc);
4156
4157         ifp = sc->bge_ifp;
4158
4159         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4160                 return;
4161
4162         /* Cancel pending I/O and flush buffers. */
4163         bge_stop(sc);
4164
4165         bge_stop_fw(sc);
4166         bge_sig_pre_reset(sc, BGE_RESET_START);
4167         bge_reset(sc);
4168         bge_sig_legacy(sc, BGE_RESET_START);
4169         bge_sig_post_reset(sc, BGE_RESET_START);
4170
4171         bge_chipinit(sc);
4172
4173         /*
4174          * Init the various state machines, ring
4175          * control blocks and firmware.
4176          */
4177         if (bge_blockinit(sc)) {
4178                 device_printf(sc->bge_dev, "initialization failure\n");
4179                 return;
4180         }
4181
4182         ifp = sc->bge_ifp;
4183
4184         /* Specify MTU. */
4185         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
4186             ETHER_HDR_LEN + ETHER_CRC_LEN +
4187             (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
4188
4189         /* Load our MAC address. */
4190         m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
4191         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
4192         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
4193
4194         /* Program promiscuous mode. */
4195         bge_setpromisc(sc);
4196
4197         /* Program multicast filter. */
4198         bge_setmulti(sc);
4199
4200         /* Program VLAN tag stripping. */
4201         bge_setvlan(sc);
4202
4203         /* Init RX ring. */
4204         if (bge_init_rx_ring_std(sc) != 0) {
4205                 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
4206                 bge_stop(sc);
4207                 return;
4208         }
4209
4210         /*
4211          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
4212          * memory to insure that the chip has in fact read the first
4213          * entry of the ring.
4214          */
4215         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
4216                 uint32_t                v, i;
4217                 for (i = 0; i < 10; i++) {
4218                         DELAY(20);
4219                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
4220                         if (v == (MCLBYTES - ETHER_ALIGN))
4221                                 break;
4222                 }
4223                 if (i == 10)
4224                         device_printf (sc->bge_dev,
4225                             "5705 A0 chip failed to load RX ring\n");
4226         }
4227
4228         /* Init jumbo RX ring. */
4229         if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN >
4230             (MCLBYTES - ETHER_ALIGN)) {
4231                 if (bge_init_rx_ring_jumbo(sc) != 0) {
4232                         device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
4233                         bge_stop(sc);
4234                         return;
4235                 }
4236         }
4237
4238         /* Init our RX return ring index. */
4239         sc->bge_rx_saved_considx = 0;
4240
4241         /* Init our RX/TX stat counters. */
4242         sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
4243
4244         /* Init TX ring. */
4245         bge_init_tx_ring(sc);
4246
4247         /* Turn on transmitter. */
4248         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
4249
4250         /* Turn on receiver. */
4251         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4252
4253         /* Tell firmware we're alive. */
4254         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4255
4256 #ifdef DEVICE_POLLING
4257         /* Disable interrupts if we are polling. */
4258         if (ifp->if_capenable & IFCAP_POLLING) {
4259                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4260                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4261                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4262         } else
4263 #endif
4264
4265         /* Enable host interrupts. */
4266         {
4267         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
4268         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4269         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4270         }
4271
4272         bge_ifmedia_upd_locked(ifp);
4273
4274         ifp->if_drv_flags |= IFF_DRV_RUNNING;
4275         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4276
4277         callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4278 }
4279
4280 static void
4281 bge_init(void *xsc)
4282 {
4283         struct bge_softc *sc = xsc;
4284
4285         BGE_LOCK(sc);
4286         bge_init_locked(sc);
4287         BGE_UNLOCK(sc);
4288 }
4289
4290 /*
4291  * Set media options.
4292  */
4293 static int
4294 bge_ifmedia_upd(struct ifnet *ifp)
4295 {
4296         struct bge_softc *sc = ifp->if_softc;
4297         int res;
4298
4299         BGE_LOCK(sc);
4300         res = bge_ifmedia_upd_locked(ifp);
4301         BGE_UNLOCK(sc);
4302
4303         return (res);
4304 }
4305
4306 static int
4307 bge_ifmedia_upd_locked(struct ifnet *ifp)
4308 {
4309         struct bge_softc *sc = ifp->if_softc;
4310         struct mii_data *mii;
4311         struct mii_softc *miisc;
4312         struct ifmedia *ifm;
4313
4314         BGE_LOCK_ASSERT(sc);
4315
4316         ifm = &sc->bge_ifmedia;
4317
4318         /* If this is a 1000baseX NIC, enable the TBI port. */
4319         if (sc->bge_flags & BGE_FLAG_TBI) {
4320                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
4321                         return (EINVAL);
4322                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
4323                 case IFM_AUTO:
4324                         /*
4325                          * The BCM5704 ASIC appears to have a special
4326                          * mechanism for programming the autoneg
4327                          * advertisement registers in TBI mode.
4328                          */
4329                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4330                                 uint32_t sgdig;
4331                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
4332                                 if (sgdig & BGE_SGDIGSTS_DONE) {
4333                                         CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
4334                                         sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
4335                                         sgdig |= BGE_SGDIGCFG_AUTO |
4336                                             BGE_SGDIGCFG_PAUSE_CAP |
4337                                             BGE_SGDIGCFG_ASYM_PAUSE;
4338                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG,
4339                                             sgdig | BGE_SGDIGCFG_SEND);
4340                                         DELAY(5);
4341                                         CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
4342                                 }
4343                         }
4344                         break;
4345                 case IFM_1000_SX:
4346                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
4347                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
4348                                     BGE_MACMODE_HALF_DUPLEX);
4349                         } else {
4350                                 BGE_SETBIT(sc, BGE_MAC_MODE,
4351                                     BGE_MACMODE_HALF_DUPLEX);
4352                         }
4353                         break;
4354                 default:
4355                         return (EINVAL);
4356                 }
4357                 return (0);
4358         }
4359
4360         sc->bge_link_evt++;
4361         mii = device_get_softc(sc->bge_miibus);
4362         if (mii->mii_instance)
4363                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4364                         mii_phy_reset(miisc);
4365         mii_mediachg(mii);
4366
4367         /*
4368          * Force an interrupt so that we will call bge_link_upd
4369          * if needed and clear any pending link state attention.
4370          * Without this we are not getting any further interrupts
4371          * for link state changes and thus will not UP the link and
4372          * not be able to send in bge_start_locked. The only
4373          * way to get things working was to receive a packet and
4374          * get an RX intr.
4375          * bge_tick should help for fiber cards and we might not
4376          * need to do this here if BGE_FLAG_TBI is set but as
4377          * we poll for fiber anyway it should not harm.
4378          */
4379         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4380             sc->bge_flags & BGE_FLAG_5788)
4381                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4382         else
4383                 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4384
4385         return (0);
4386 }
4387
4388 /*
4389  * Report current media status.
4390  */
4391 static void
4392 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4393 {
4394         struct bge_softc *sc = ifp->if_softc;
4395         struct mii_data *mii;
4396
4397         BGE_LOCK(sc);
4398
4399         if (sc->bge_flags & BGE_FLAG_TBI) {
4400                 ifmr->ifm_status = IFM_AVALID;
4401                 ifmr->ifm_active = IFM_ETHER;
4402                 if (CSR_READ_4(sc, BGE_MAC_STS) &
4403                     BGE_MACSTAT_TBI_PCS_SYNCHED)
4404                         ifmr->ifm_status |= IFM_ACTIVE;
4405                 else {
4406                         ifmr->ifm_active |= IFM_NONE;
4407                         BGE_UNLOCK(sc);
4408                         return;
4409                 }
4410                 ifmr->ifm_active |= IFM_1000_SX;
4411                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
4412                         ifmr->ifm_active |= IFM_HDX;
4413                 else
4414                         ifmr->ifm_active |= IFM_FDX;
4415                 BGE_UNLOCK(sc);
4416                 return;
4417         }
4418
4419         mii = device_get_softc(sc->bge_miibus);
4420         mii_pollstat(mii);
4421         ifmr->ifm_active = mii->mii_media_active;
4422         ifmr->ifm_status = mii->mii_media_status;
4423
4424         BGE_UNLOCK(sc);
4425 }
4426
4427 static int
4428 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
4429 {
4430         struct bge_softc *sc = ifp->if_softc;
4431         struct ifreq *ifr = (struct ifreq *) data;
4432         struct mii_data *mii;
4433         int flags, mask, error = 0;
4434
4435         switch (command) {
4436         case SIOCSIFMTU:
4437                 if (ifr->ifr_mtu < ETHERMIN ||
4438                     ((BGE_IS_JUMBO_CAPABLE(sc)) &&
4439                     ifr->ifr_mtu > BGE_JUMBO_MTU) ||
4440                     ((!BGE_IS_JUMBO_CAPABLE(sc)) &&
4441                     ifr->ifr_mtu > ETHERMTU))
4442                         error = EINVAL;
4443                 else if (ifp->if_mtu != ifr->ifr_mtu) {
4444                         ifp->if_mtu = ifr->ifr_mtu;
4445                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4446                         bge_init(sc);
4447                 }
4448                 break;
4449         case SIOCSIFFLAGS:
4450                 BGE_LOCK(sc);
4451                 if (ifp->if_flags & IFF_UP) {
4452                         /*
4453                          * If only the state of the PROMISC flag changed,
4454                          * then just use the 'set promisc mode' command
4455                          * instead of reinitializing the entire NIC. Doing
4456                          * a full re-init means reloading the firmware and
4457                          * waiting for it to start up, which may take a
4458                          * second or two.  Similarly for ALLMULTI.
4459                          */
4460                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4461                                 flags = ifp->if_flags ^ sc->bge_if_flags;
4462                                 if (flags & IFF_PROMISC)
4463                                         bge_setpromisc(sc);
4464                                 if (flags & IFF_ALLMULTI)
4465                                         bge_setmulti(sc);
4466                         } else
4467                                 bge_init_locked(sc);
4468                 } else {
4469                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4470                                 bge_stop(sc);
4471                         }
4472                 }
4473                 sc->bge_if_flags = ifp->if_flags;
4474                 BGE_UNLOCK(sc);
4475                 error = 0;
4476                 break;
4477         case SIOCADDMULTI:
4478         case SIOCDELMULTI:
4479                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4480                         BGE_LOCK(sc);
4481                         bge_setmulti(sc);
4482                         BGE_UNLOCK(sc);
4483                         error = 0;
4484                 }
4485                 break;
4486         case SIOCSIFMEDIA:
4487         case SIOCGIFMEDIA:
4488                 if (sc->bge_flags & BGE_FLAG_TBI) {
4489                         error = ifmedia_ioctl(ifp, ifr,
4490                             &sc->bge_ifmedia, command);
4491                 } else {
4492                         mii = device_get_softc(sc->bge_miibus);
4493                         error = ifmedia_ioctl(ifp, ifr,
4494                             &mii->mii_media, command);
4495                 }
4496                 break;
4497         case SIOCSIFCAP:
4498                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
4499 #ifdef DEVICE_POLLING
4500                 if (mask & IFCAP_POLLING) {
4501                         if (ifr->ifr_reqcap & IFCAP_POLLING) {
4502                                 error = ether_poll_register(bge_poll, ifp);
4503                                 if (error)
4504                                         return (error);
4505                                 BGE_LOCK(sc);
4506                                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
4507                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4508                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4509                                 ifp->if_capenable |= IFCAP_POLLING;
4510                                 BGE_UNLOCK(sc);
4511                         } else {
4512                                 error = ether_poll_deregister(ifp);
4513                                 /* Enable interrupt even in error case */
4514                                 BGE_LOCK(sc);
4515                                 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
4516                                     BGE_PCIMISCCTL_MASK_PCI_INTR);
4517                                 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4518                                 ifp->if_capenable &= ~IFCAP_POLLING;
4519                                 BGE_UNLOCK(sc);
4520                         }
4521                 }
4522 #endif
4523                 if (mask & IFCAP_HWCSUM) {
4524                         ifp->if_capenable ^= IFCAP_HWCSUM;
4525                         if (IFCAP_HWCSUM & ifp->if_capenable &&
4526                             IFCAP_HWCSUM & ifp->if_capabilities)
4527                                 ifp->if_hwassist |= BGE_CSUM_FEATURES;
4528                         else
4529                                 ifp->if_hwassist &= ~BGE_CSUM_FEATURES;
4530 #ifdef VLAN_CAPABILITIES
4531                         VLAN_CAPABILITIES(ifp);
4532 #endif
4533                 }
4534
4535                 if ((mask & IFCAP_TSO4) != 0 &&
4536                     (ifp->if_capabilities & IFCAP_TSO4) != 0) {
4537                         ifp->if_capenable ^= IFCAP_TSO4;
4538                         if ((ifp->if_capenable & IFCAP_TSO4) != 0)
4539                                 ifp->if_hwassist |= CSUM_TSO;
4540                         else
4541                                 ifp->if_hwassist &= ~CSUM_TSO;
4542                 }
4543
4544                 if (mask & IFCAP_VLAN_MTU) {
4545                         ifp->if_capenable ^= IFCAP_VLAN_MTU;
4546                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4547                         bge_init(sc);
4548                 }
4549
4550                 if (mask & IFCAP_VLAN_HWTAGGING) {
4551                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
4552                         BGE_LOCK(sc);
4553                         bge_setvlan(sc);
4554                         BGE_UNLOCK(sc);
4555 #ifdef VLAN_CAPABILITIES
4556                         VLAN_CAPABILITIES(ifp);
4557 #endif
4558                 }
4559
4560                 break;
4561         default:
4562                 error = ether_ioctl(ifp, command, data);
4563                 break;
4564         }
4565
4566         return (error);
4567 }
4568
4569 static void
4570 bge_watchdog(struct bge_softc *sc)
4571 {
4572         struct ifnet *ifp;
4573
4574         BGE_LOCK_ASSERT(sc);
4575
4576         if (sc->bge_timer == 0 || --sc->bge_timer)
4577                 return;
4578
4579         ifp = sc->bge_ifp;
4580
4581         if_printf(ifp, "watchdog timeout -- resetting\n");
4582
4583         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4584         bge_init_locked(sc);
4585
4586         ifp->if_oerrors++;
4587 }
4588
4589 /*
4590  * Stop the adapter and free any mbufs allocated to the
4591  * RX and TX lists.
4592  */
4593 static void
4594 bge_stop(struct bge_softc *sc)
4595 {
4596         struct ifnet *ifp;
4597
4598         BGE_LOCK_ASSERT(sc);
4599
4600         ifp = sc->bge_ifp;
4601
4602         callout_stop(&sc->bge_stat_ch);
4603
4604         /* Disable host interrupts. */
4605         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
4606         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4607
4608         /*
4609          * Tell firmware we're shutting down.
4610          */
4611         bge_stop_fw(sc);
4612         bge_sig_pre_reset(sc, BGE_RESET_STOP);
4613
4614         /*
4615          * Disable all of the receiver blocks.
4616          */
4617         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4618         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
4619         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
4620         if (!(BGE_IS_5705_PLUS(sc)))
4621                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
4622         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
4623         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
4624         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
4625
4626         /*
4627          * Disable all of the transmit blocks.
4628          */
4629         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
4630         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
4631         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
4632         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
4633         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
4634         if (!(BGE_IS_5705_PLUS(sc)))
4635                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
4636         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
4637
4638         /*
4639          * Shut down all of the memory managers and related
4640          * state machines.
4641          */
4642         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
4643         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
4644         if (!(BGE_IS_5705_PLUS(sc)))
4645                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
4646         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
4647         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
4648         if (!(BGE_IS_5705_PLUS(sc))) {
4649                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
4650                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4651         }
4652
4653         bge_reset(sc);
4654         bge_sig_legacy(sc, BGE_RESET_STOP);
4655         bge_sig_post_reset(sc, BGE_RESET_STOP);
4656
4657         /*
4658          * Keep the ASF firmware running if up.
4659          */
4660         if (sc->bge_asf_mode & ASF_STACKUP)
4661                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4662         else
4663                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4664
4665         /* Free the RX lists. */
4666         bge_free_rx_ring_std(sc);
4667
4668         /* Free jumbo RX list. */
4669         if (BGE_IS_JUMBO_CAPABLE(sc))
4670                 bge_free_rx_ring_jumbo(sc);
4671
4672         /* Free TX buffers. */
4673         bge_free_tx_ring(sc);
4674
4675         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
4676
4677         /* Clear MAC's link state (PHY may still have link UP). */
4678         if (bootverbose && sc->bge_link)
4679                 if_printf(sc->bge_ifp, "link DOWN\n");
4680         sc->bge_link = 0;
4681
4682         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4683 }
4684
4685 /*
4686  * Stop all chip I/O so that the kernel's probe routines don't
4687  * get confused by errant DMAs when rebooting.
4688  */
4689 static int
4690 bge_shutdown(device_t dev)
4691 {
4692         struct bge_softc *sc;
4693
4694         sc = device_get_softc(dev);
4695         BGE_LOCK(sc);
4696         bge_stop(sc);
4697         bge_reset(sc);
4698         BGE_UNLOCK(sc);
4699
4700         return (0);
4701 }
4702
4703 static int
4704 bge_suspend(device_t dev)
4705 {
4706         struct bge_softc *sc;
4707
4708         sc = device_get_softc(dev);
4709         BGE_LOCK(sc);
4710         bge_stop(sc);
4711         BGE_UNLOCK(sc);
4712
4713         return (0);
4714 }
4715
4716 static int
4717 bge_resume(device_t dev)
4718 {
4719         struct bge_softc *sc;
4720         struct ifnet *ifp;
4721
4722         sc = device_get_softc(dev);
4723         BGE_LOCK(sc);
4724         ifp = sc->bge_ifp;
4725         if (ifp->if_flags & IFF_UP) {
4726                 bge_init_locked(sc);
4727                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4728                         bge_start_locked(ifp);
4729         }
4730         BGE_UNLOCK(sc);
4731
4732         return (0);
4733 }
4734
4735 static void
4736 bge_link_upd(struct bge_softc *sc)
4737 {
4738         struct mii_data *mii;
4739         uint32_t link, status;
4740
4741         BGE_LOCK_ASSERT(sc);
4742
4743         /* Clear 'pending link event' flag. */
4744         sc->bge_link_evt = 0;
4745
4746         /*
4747          * Process link state changes.
4748          * Grrr. The link status word in the status block does
4749          * not work correctly on the BCM5700 rev AX and BX chips,
4750          * according to all available information. Hence, we have
4751          * to enable MII interrupts in order to properly obtain
4752          * async link changes. Unfortunately, this also means that
4753          * we have to read the MAC status register to detect link
4754          * changes, thereby adding an additional register access to
4755          * the interrupt handler.
4756          *
4757          * XXX: perhaps link state detection procedure used for
4758          * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
4759          */
4760
4761         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4762             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
4763                 status = CSR_READ_4(sc, BGE_MAC_STS);
4764                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
4765                         mii = device_get_softc(sc->bge_miibus);
4766                         mii_pollstat(mii);
4767                         if (!sc->bge_link &&
4768                             mii->mii_media_status & IFM_ACTIVE &&
4769                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4770                                 sc->bge_link++;
4771                                 if (bootverbose)
4772                                         if_printf(sc->bge_ifp, "link UP\n");
4773                         } else if (sc->bge_link &&
4774                             (!(mii->mii_media_status & IFM_ACTIVE) ||
4775                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4776                                 sc->bge_link = 0;
4777                                 if (bootverbose)
4778                                         if_printf(sc->bge_ifp, "link DOWN\n");
4779                         }
4780
4781                         /* Clear the interrupt. */
4782                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
4783                             BGE_EVTENB_MI_INTERRUPT);
4784                         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4785                         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
4786                             BRGPHY_INTRS);
4787                 }
4788                 return;
4789         }
4790
4791         if (sc->bge_flags & BGE_FLAG_TBI) {
4792                 status = CSR_READ_4(sc, BGE_MAC_STS);
4793                 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4794                         if (!sc->bge_link) {
4795                                 sc->bge_link++;
4796                                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
4797                                         BGE_CLRBIT(sc, BGE_MAC_MODE,
4798                                             BGE_MACMODE_TBI_SEND_CFGS);
4799                                 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4800                                 if (bootverbose)
4801                                         if_printf(sc->bge_ifp, "link UP\n");
4802                                 if_link_state_change(sc->bge_ifp,
4803                                     LINK_STATE_UP);
4804                         }
4805                 } else if (sc->bge_link) {
4806                         sc->bge_link = 0;
4807                         if (bootverbose)
4808                                 if_printf(sc->bge_ifp, "link DOWN\n");
4809                         if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
4810                 }
4811         } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
4812                 /*
4813                  * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
4814                  * in status word always set. Workaround this bug by reading
4815                  * PHY link status directly.
4816                  */
4817                 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
4818
4819                 if (link != sc->bge_link ||
4820                     sc->bge_asicrev == BGE_ASICREV_BCM5700) {
4821                         mii = device_get_softc(sc->bge_miibus);
4822                         mii_pollstat(mii);
4823                         if (!sc->bge_link &&
4824                             mii->mii_media_status & IFM_ACTIVE &&
4825                             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4826                                 sc->bge_link++;
4827                                 if (bootverbose)
4828                                         if_printf(sc->bge_ifp, "link UP\n");
4829                         } else if (sc->bge_link &&
4830                             (!(mii->mii_media_status & IFM_ACTIVE) ||
4831                             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4832                                 sc->bge_link = 0;
4833                                 if (bootverbose)
4834                                         if_printf(sc->bge_ifp, "link DOWN\n");
4835                         }
4836                 }
4837         } else {
4838                 /*
4839                  * Discard link events for MII/GMII controllers
4840                  * if MI auto-polling is disabled.
4841                  */
4842         }
4843
4844         /* Clear the attention. */
4845         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4846             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4847             BGE_MACSTAT_LINK_CHANGED);
4848 }
4849
4850 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
4851         SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
4852             sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
4853             desc)
4854
4855 static void
4856 bge_add_sysctls(struct bge_softc *sc)
4857 {
4858         struct sysctl_ctx_list *ctx;
4859         struct sysctl_oid_list *children, *schildren;
4860         struct sysctl_oid *tree;
4861
4862         ctx = device_get_sysctl_ctx(sc->bge_dev);
4863         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
4864
4865 #ifdef BGE_REGISTER_DEBUG
4866         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
4867             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
4868             "Debug Information");
4869
4870         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
4871             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
4872             "Register Read");
4873
4874         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
4875             CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
4876             "Memory Read");
4877
4878 #endif
4879
4880         /*
4881          * A common design characteristic for many Broadcom client controllers
4882          * is that they only support a single outstanding DMA read operation
4883          * on the PCIe bus. This means that it will take twice as long to fetch
4884          * a TX frame that is split into header and payload buffers as it does
4885          * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
4886          * these controllers, coalescing buffers to reduce the number of memory
4887          * reads is effective way to get maximum performance(about 940Mbps).
4888          * Without collapsing TX buffers the maximum TCP bulk transfer
4889          * performance is about 850Mbps. However forcing coalescing mbufs
4890          * consumes a lot of CPU cycles, so leave it off by default.
4891          */
4892         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
4893             CTLFLAG_RW, &sc->bge_forced_collapse, 0,
4894             "Number of fragmented TX buffers of a frame allowed before "
4895             "forced collapsing");
4896         resource_int_value(device_get_name(sc->bge_dev),
4897             device_get_unit(sc->bge_dev), "forced_collapse",
4898             &sc->bge_forced_collapse);
4899
4900         if (BGE_IS_5705_PLUS(sc))
4901                 return;
4902
4903         tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
4904             NULL, "BGE Statistics");
4905         schildren = children = SYSCTL_CHILDREN(tree);
4906         BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
4907             children, COSFramesDroppedDueToFilters,
4908             "FramesDroppedDueToFilters");
4909         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
4910             children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
4911         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
4912             children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
4913         BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
4914             children, nicNoMoreRxBDs, "NoMoreRxBDs");
4915         BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
4916             children, ifInDiscards, "InputDiscards");
4917         BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
4918             children, ifInErrors, "InputErrors");
4919         BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
4920             children, nicRecvThresholdHit, "RecvThresholdHit");
4921         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
4922             children, nicDmaReadQueueFull, "DmaReadQueueFull");
4923         BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
4924             children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
4925         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
4926             children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
4927         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
4928             children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
4929         BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
4930             children, nicRingStatusUpdate, "RingStatusUpdate");
4931         BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
4932             children, nicInterrupts, "Interrupts");
4933         BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
4934             children, nicAvoidedInterrupts, "AvoidedInterrupts");
4935         BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
4936             children, nicSendThresholdHit, "SendThresholdHit");
4937
4938         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
4939             NULL, "BGE RX Statistics");
4940         children = SYSCTL_CHILDREN(tree);
4941         BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
4942             children, rxstats.ifHCInOctets, "Octets");
4943         BGE_SYSCTL_STAT(sc, ctx, "Fragments",
4944             children, rxstats.etherStatsFragments, "Fragments");
4945         BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
4946             children, rxstats.ifHCInUcastPkts, "UcastPkts");
4947         BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
4948             children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
4949         BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
4950             children, rxstats.dot3StatsFCSErrors, "FCSErrors");
4951         BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
4952             children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
4953         BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
4954             children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
4955         BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
4956             children, rxstats.xoffPauseFramesReceived,
4957             "xoffPauseFramesReceived");
4958         BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
4959             children, rxstats.macControlFramesReceived,
4960             "ControlFramesReceived");
4961         BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
4962             children, rxstats.xoffStateEntered, "xoffStateEntered");
4963         BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
4964             children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
4965         BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
4966             children, rxstats.etherStatsJabbers, "Jabbers");
4967         BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
4968             children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
4969         BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
4970             children, rxstats.inRangeLengthError, "inRangeLengthError");
4971         BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
4972             children, rxstats.outRangeLengthError, "outRangeLengthError");
4973
4974         tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
4975             NULL, "BGE TX Statistics");
4976         children = SYSCTL_CHILDREN(tree);
4977         BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
4978             children, txstats.ifHCOutOctets, "Octets");
4979         BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
4980             children, txstats.etherStatsCollisions, "Collisions");
4981         BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
4982             children, txstats.outXonSent, "XonSent");
4983         BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
4984             children, txstats.outXoffSent, "XoffSent");
4985         BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
4986             children, txstats.flowControlDone, "flowControlDone");
4987         BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
4988             children, txstats.dot3StatsInternalMacTransmitErrors,
4989             "InternalMacTransmitErrors");
4990         BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
4991             children, txstats.dot3StatsSingleCollisionFrames,
4992             "SingleCollisionFrames");
4993         BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
4994             children, txstats.dot3StatsMultipleCollisionFrames,
4995             "MultipleCollisionFrames");
4996         BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
4997             children, txstats.dot3StatsDeferredTransmissions,
4998             "DeferredTransmissions");
4999         BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
5000             children, txstats.dot3StatsExcessiveCollisions,
5001             "ExcessiveCollisions");
5002         BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
5003             children, txstats.dot3StatsLateCollisions,
5004             "LateCollisions");
5005         BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
5006             children, txstats.ifHCOutUcastPkts, "UcastPkts");
5007         BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
5008             children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
5009         BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
5010             children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
5011         BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
5012             children, txstats.dot3StatsCarrierSenseErrors,
5013             "CarrierSenseErrors");
5014         BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
5015             children, txstats.ifOutDiscards, "Discards");
5016         BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
5017             children, txstats.ifOutErrors, "Errors");
5018 }
5019
5020 static int
5021 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
5022 {
5023         struct bge_softc *sc;
5024         uint32_t result;
5025         int offset;
5026
5027         sc = (struct bge_softc *)arg1;
5028         offset = arg2;
5029         result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
5030             offsetof(bge_hostaddr, bge_addr_lo));
5031         return (sysctl_handle_int(oidp, &result, 0, req));
5032 }
5033
5034 #ifdef BGE_REGISTER_DEBUG
5035 static int
5036 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
5037 {
5038         struct bge_softc *sc;
5039         uint16_t *sbdata;
5040         int error;
5041         int result;
5042         int i, j;
5043
5044         result = -1;
5045         error = sysctl_handle_int(oidp, &result, 0, req);
5046         if (error || (req->newptr == NULL))
5047                 return (error);
5048
5049         if (result == 1) {
5050                 sc = (struct bge_softc *)arg1;
5051
5052                 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
5053                 printf("Status Block:\n");
5054                 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) {
5055                         printf("%06x:", i);
5056                         for (j = 0; j < 8; j++) {
5057                                 printf(" %04x", sbdata[i]);
5058                                 i += 4;
5059                         }
5060                         printf("\n");
5061                 }
5062
5063                 printf("Registers:\n");
5064                 for (i = 0x800; i < 0xA00; ) {
5065                         printf("%06x:", i);
5066                         for (j = 0; j < 8; j++) {
5067                                 printf(" %08x", CSR_READ_4(sc, i));
5068                                 i += 4;
5069                         }
5070                         printf("\n");
5071                 }
5072
5073                 printf("Hardware Flags:\n");
5074                 if (BGE_IS_5755_PLUS(sc))
5075                         printf(" - 5755 Plus\n");
5076                 if (BGE_IS_575X_PLUS(sc))
5077                         printf(" - 575X Plus\n");
5078                 if (BGE_IS_5705_PLUS(sc))
5079                         printf(" - 5705 Plus\n");
5080                 if (BGE_IS_5714_FAMILY(sc))
5081                         printf(" - 5714 Family\n");
5082                 if (BGE_IS_5700_FAMILY(sc))
5083                         printf(" - 5700 Family\n");
5084                 if (sc->bge_flags & BGE_FLAG_JUMBO)
5085                         printf(" - Supports Jumbo Frames\n");
5086                 if (sc->bge_flags & BGE_FLAG_PCIX)
5087                         printf(" - PCI-X Bus\n");
5088                 if (sc->bge_flags & BGE_FLAG_PCIE)
5089                         printf(" - PCI Express Bus\n");
5090                 if (sc->bge_flags & BGE_FLAG_NO_3LED)
5091                         printf(" - No 3 LEDs\n");
5092                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
5093                         printf(" - RX Alignment Bug\n");
5094         }
5095
5096         return (error);
5097 }
5098
5099 static int
5100 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5101 {
5102         struct bge_softc *sc;
5103         int error;
5104         uint16_t result;
5105         uint32_t val;
5106
5107         result = -1;
5108         error = sysctl_handle_int(oidp, &result, 0, req);
5109         if (error || (req->newptr == NULL))
5110                 return (error);
5111
5112         if (result < 0x8000) {
5113                 sc = (struct bge_softc *)arg1;
5114                 val = CSR_READ_4(sc, result);
5115                 printf("reg 0x%06X = 0x%08X\n", result, val);
5116         }
5117
5118         return (error);
5119 }
5120
5121 static int
5122 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
5123 {
5124         struct bge_softc *sc;
5125         int error;
5126         uint16_t result;
5127         uint32_t val;
5128
5129         result = -1;
5130         error = sysctl_handle_int(oidp, &result, 0, req);
5131         if (error || (req->newptr == NULL))
5132                 return (error);
5133
5134         if (result < 0x8000) {
5135                 sc = (struct bge_softc *)arg1;
5136                 val = bge_readmem_ind(sc, result);
5137                 printf("mem 0x%06X = 0x%08X\n", result, val);
5138         }
5139
5140         return (error);
5141 }
5142 #endif
5143
5144 static int
5145 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
5146 {
5147
5148         if (sc->bge_flags & BGE_FLAG_EADDR)
5149                 return (1);
5150
5151 #ifdef __sparc64__
5152         OF_getetheraddr(sc->bge_dev, ether_addr);
5153         return (0);
5154 #endif
5155         return (1);
5156 }
5157
5158 static int
5159 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
5160 {
5161         uint32_t mac_addr;
5162
5163         mac_addr = bge_readmem_ind(sc, 0x0c14);
5164         if ((mac_addr >> 16) == 0x484b) {
5165                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
5166                 ether_addr[1] = (uint8_t)mac_addr;
5167                 mac_addr = bge_readmem_ind(sc, 0x0c18);
5168                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
5169                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
5170                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
5171                 ether_addr[5] = (uint8_t)mac_addr;
5172                 return (0);
5173         }
5174         return (1);
5175 }
5176
5177 static int
5178 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
5179 {
5180         int mac_offset = BGE_EE_MAC_OFFSET;
5181
5182         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
5183                 mac_offset = BGE_EE_MAC_OFFSET_5906;
5184
5185         return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
5186             ETHER_ADDR_LEN));
5187 }
5188
5189 static int
5190 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
5191 {
5192
5193         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
5194                 return (1);
5195
5196         return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
5197            ETHER_ADDR_LEN));
5198 }
5199
5200 static int
5201 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
5202 {
5203         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
5204                 /* NOTE: Order is critical */
5205                 bge_get_eaddr_fw,
5206                 bge_get_eaddr_mem,
5207                 bge_get_eaddr_nvram,
5208                 bge_get_eaddr_eeprom,
5209                 NULL
5210         };
5211         const bge_eaddr_fcn_t *func;
5212
5213         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
5214                 if ((*func)(sc, eaddr) == 0)
5215                         break;
5216         }
5217         return (*func == NULL ? ENXIO : 0);
5218 }