2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
37 * BCM570x memory map. The internal memory layout varies somewhat
38 * depending on whether or not we have external SSRAM attached.
39 * The BCM5700 can have up to 16MB of external memory. The BCM5701
40 * is apparently not designed to use external SSRAM. The mappings
41 * up to the first 4 send rings are the same for both internal and
42 * external memory configurations. Note that mini RX ring space is
43 * only available with external SSRAM configurations, which means
44 * the mini RX ring is not supported on the BCM5701.
46 * The NIC's memory can be accessed by the host in one of 3 ways:
48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA
49 * registers in PCI config space can be used to read any 32-bit
50 * address within the NIC's memory.
52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config
53 * space can be used in conjunction with the memory window in the
54 * device register space at offset 0x8000 to read any 32K chunk
57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is
58 * set, the device I/O mapping consumes 32MB of host address space,
59 * allowing all of the registers and internal NIC memory to be
60 * accessed directly. NIC memory addresses are offset by 0x01000000.
61 * Flat mode consumes so much host address space that it is not
64 #define BGE_PAGE_ZERO 0x00000000
65 #define BGE_PAGE_ZERO_END 0x000000FF
66 #define BGE_SEND_RING_RCB 0x00000100
67 #define BGE_SEND_RING_RCB_END 0x000001FF
68 #define BGE_RX_RETURN_RING_RCB 0x00000200
69 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF
70 #define BGE_STATS_BLOCK 0x00000300
71 #define BGE_STATS_BLOCK_END 0x00000AFF
72 #define BGE_STATUS_BLOCK 0x00000B00
73 #define BGE_STATUS_BLOCK_END 0x00000B4F
74 #define BGE_SOFTWARE_GENCOMM 0x00000B50
75 #define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54
76 #define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58
77 #define BGE_SOFTWARE_GENCOMM_FW 0x00000B78
78 #define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C
79 #define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80
80 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF
81 #define BGE_UNMAPPED 0x00001000
82 #define BGE_UNMAPPED_END 0x00001FFF
83 #define BGE_DMA_DESCRIPTORS 0x00002000
84 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF
85 #define BGE_SEND_RING_1_TO_4 0x00004000
86 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF
88 /* Firmware interface */
89 #define BGE_FW_DRV_ALIVE 0x00000001
90 #define BGE_FW_PAUSE 0x00000002
92 /* Mappings for internal memory configuration */
93 #define BGE_STD_RX_RINGS 0x00006000
94 #define BGE_STD_RX_RINGS_END 0x00006FFF
95 #define BGE_JUMBO_RX_RINGS 0x00007000
96 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF
97 #define BGE_BUFFPOOL_1 0x00008000
98 #define BGE_BUFFPOOL_1_END 0x0000FFFF
99 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */
100 #define BGE_BUFFPOOL_2_END 0x00017FFF
101 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */
102 #define BGE_BUFFPOOL_3_END 0x0001FFFF
104 /* Mappings for external SSRAM configurations */
105 #define BGE_SEND_RING_5_TO_6 0x00006000
106 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF
107 #define BGE_SEND_RING_7_TO_8 0x00007000
108 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF
109 #define BGE_SEND_RING_9_TO_16 0x00008000
110 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF
111 #define BGE_EXT_STD_RX_RINGS 0x0000C000
112 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF
113 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000
114 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF
115 #define BGE_MINI_RX_RINGS 0x0000E000
116 #define BGE_MINI_RX_RINGS_END 0x0000FFFF
117 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */
118 #define BGE_AVAIL_REGION1_END 0x00017FFF
119 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */
120 #define BGE_AVAIL_REGION2_END 0x0001FFFF
121 #define BGE_EXT_SSRAM 0x00020000
122 #define BGE_EXT_SSRAM_END 0x000FFFFF
126 * BCM570x register offsets. These are memory mapped registers
127 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
128 * Each register must be accessed using 32 bit operations.
130 * All registers are accessed through a 32K shared memory block.
131 * The first group of registers are actually copies of the PCI
132 * configuration space registers.
136 * PCI registers defined in the PCI 2.2 spec.
138 #define BGE_PCI_VID 0x00
139 #define BGE_PCI_DID 0x02
140 #define BGE_PCI_CMD 0x04
141 #define BGE_PCI_STS 0x06
142 #define BGE_PCI_REV 0x08
143 #define BGE_PCI_CLASS 0x09
144 #define BGE_PCI_CACHESZ 0x0C
145 #define BGE_PCI_LATTIMER 0x0D
146 #define BGE_PCI_HDRTYPE 0x0E
147 #define BGE_PCI_BIST 0x0F
148 #define BGE_PCI_BAR0 0x10
149 #define BGE_PCI_BAR1 0x14
150 #define BGE_PCI_SUBSYS 0x2C
151 #define BGE_PCI_SUBVID 0x2E
152 #define BGE_PCI_ROMBASE 0x30
153 #define BGE_PCI_CAPPTR 0x34
154 #define BGE_PCI_INTLINE 0x3C
155 #define BGE_PCI_INTPIN 0x3D
156 #define BGE_PCI_MINGNT 0x3E
157 #define BGE_PCI_MAXLAT 0x3F
158 #define BGE_PCI_PCIXCAP 0x40
159 #define BGE_PCI_NEXTPTR_PM 0x41
160 #define BGE_PCI_PCIX_CMD 0x42
161 #define BGE_PCI_PCIX_STS 0x44
162 #define BGE_PCI_PWRMGMT_CAPID 0x48
163 #define BGE_PCI_NEXTPTR_VPD 0x49
164 #define BGE_PCI_PWRMGMT_CAPS 0x4A
165 #define BGE_PCI_PWRMGMT_CMD 0x4C
166 #define BGE_PCI_PWRMGMT_STS 0x4D
167 #define BGE_PCI_PWRMGMT_DATA 0x4F
168 #define BGE_PCI_VPD_CAPID 0x50
169 #define BGE_PCI_NEXTPTR_MSI 0x51
170 #define BGE_PCI_VPD_ADDR 0x52
171 #define BGE_PCI_VPD_DATA 0x54
172 #define BGE_PCI_MSI_CAPID 0x58
173 #define BGE_PCI_NEXTPTR_NONE 0x59
174 #define BGE_PCI_MSI_CTL 0x5A
175 #define BGE_PCI_MSI_ADDR_HI 0x5C
176 #define BGE_PCI_MSI_ADDR_LO 0x60
177 #define BGE_PCI_MSI_DATA 0x64
180 #define BGE_PCIE_CAPID_REG 0xD0
181 #define BGE_PCIE_CAPID 0x10
184 * PCI registers specific to the BCM570x family.
186 #define BGE_PCI_MISC_CTL 0x68
187 #define BGE_PCI_DMA_RW_CTL 0x6C
188 #define BGE_PCI_PCISTATE 0x70
189 #define BGE_PCI_CLKCTL 0x74
190 #define BGE_PCI_REG_BASEADDR 0x78
191 #define BGE_PCI_MEMWIN_BASEADDR 0x7C
192 #define BGE_PCI_REG_DATA 0x80
193 #define BGE_PCI_MEMWIN_DATA 0x84
194 #define BGE_PCI_MODECTL 0x88
195 #define BGE_PCI_MISC_CFG 0x8C
196 #define BGE_PCI_MISC_LOCALCTL 0x90
197 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98
198 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C
199 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0
200 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4
201 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8
202 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC
203 #define BGE_PCI_ISR_MBX_HI 0xB0
204 #define BGE_PCI_ISR_MBX_LO 0xB4
206 /* PCI Misc. Host control register */
207 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001
208 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002
209 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004
210 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008
211 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010
212 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020
213 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040
214 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080
215 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000
217 #define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP)
218 #if BYTE_ORDER == LITTLE_ENDIAN
219 #define BGE_DMA_SWAP_OPTIONS \
220 BGE_MODECTL_WORDSWAP_NONFRAME| \
221 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA
223 #define BGE_DMA_SWAP_OPTIONS \
224 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \
225 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA
229 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \
230 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS)
232 #define BGE_CHIPID_TIGON_I 0x40000000
233 #define BGE_CHIPID_TIGON_II 0x60000000
234 #define BGE_CHIPID_BCM5700_A0 0x70000000
235 #define BGE_CHIPID_BCM5700_A1 0x70010000
236 #define BGE_CHIPID_BCM5700_B0 0x71000000
237 #define BGE_CHIPID_BCM5700_B1 0x71010000
238 #define BGE_CHIPID_BCM5700_B2 0x71020000
239 #define BGE_CHIPID_BCM5700_B3 0x71030000
240 #define BGE_CHIPID_BCM5700_ALTIMA 0x71040000
241 #define BGE_CHIPID_BCM5700_C0 0x72000000
242 #define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */
243 #define BGE_CHIPID_BCM5701_B0 0x01000000
244 #define BGE_CHIPID_BCM5701_B2 0x01020000
245 #define BGE_CHIPID_BCM5701_B5 0x01050000
246 #define BGE_CHIPID_BCM5703_A0 0x10000000
247 #define BGE_CHIPID_BCM5703_A1 0x10010000
248 #define BGE_CHIPID_BCM5703_A2 0x10020000
249 #define BGE_CHIPID_BCM5703_A3 0x10030000
250 #define BGE_CHIPID_BCM5703_B0 0x11000000
251 #define BGE_CHIPID_BCM5704_A0 0x20000000
252 #define BGE_CHIPID_BCM5704_A1 0x20010000
253 #define BGE_CHIPID_BCM5704_A2 0x20020000
254 #define BGE_CHIPID_BCM5704_A3 0x20030000
255 #define BGE_CHIPID_BCM5704_B0 0x21000000
256 #define BGE_CHIPID_BCM5705_A0 0x30000000
257 #define BGE_CHIPID_BCM5705_A1 0x30010000
258 #define BGE_CHIPID_BCM5705_A2 0x30020000
259 #define BGE_CHIPID_BCM5705_A3 0x30030000
260 #define BGE_CHIPID_BCM5750_A0 0x40000000
261 #define BGE_CHIPID_BCM5750_A1 0x40010000
262 #define BGE_CHIPID_BCM5750_A3 0x40030000
263 #define BGE_CHIPID_BCM5750_B0 0x41000000
264 #define BGE_CHIPID_BCM5750_B1 0x41010000
265 #define BGE_CHIPID_BCM5750_C0 0x42000000
266 #define BGE_CHIPID_BCM5750_C1 0x42010000
267 #define BGE_CHIPID_BCM5750_C2 0x42020000
268 #define BGE_CHIPID_BCM5714_A0 0x50000000
269 #define BGE_CHIPID_BCM5752_A0 0x60000000
270 #define BGE_CHIPID_BCM5752_A1 0x60010000
271 #define BGE_CHIPID_BCM5752_A2 0x60020000
272 #define BGE_CHIPID_BCM5714_B0 0x80000000
273 #define BGE_CHIPID_BCM5714_B3 0x80030000
274 #define BGE_CHIPID_BCM5715_A0 0x90000000
275 #define BGE_CHIPID_BCM5715_A1 0x90010000
276 #define BGE_CHIPID_BCM5715_A3 0x90030000
277 #define BGE_CHIPID_BCM5755_A0 0xa0000000
278 #define BGE_CHIPID_BCM5755_A1 0xa0010000
279 #define BGE_CHIPID_BCM5755_A2 0xa0020000
280 #define BGE_CHIPID_BCM5722_A0 0xa2000000
281 #define BGE_CHIPID_BCM5754_A0 0xb0000000
282 #define BGE_CHIPID_BCM5754_A1 0xb0010000
283 #define BGE_CHIPID_BCM5754_A2 0xb0020000
284 #define BGE_CHIPID_BCM5787_A0 0xb0000000
285 #define BGE_CHIPID_BCM5787_A1 0xb0010000
286 #define BGE_CHIPID_BCM5787_A2 0xb0020000
287 #define BGE_CHIPID_BCM5906_A1 0xc0010000
288 #define BGE_CHIPID_BCM5906_A2 0xc0020000
291 #define BGE_ASICREV(x) ((x) >> 28)
292 #define BGE_ASICREV_BCM5701 0x00
293 #define BGE_ASICREV_BCM5703 0x01
294 #define BGE_ASICREV_BCM5704 0x02
295 #define BGE_ASICREV_BCM5705 0x03
296 #define BGE_ASICREV_BCM5750 0x04
297 #define BGE_ASICREV_BCM5714_A0 0x05
298 #define BGE_ASICREV_BCM5752 0x06
299 #define BGE_ASICREV_BCM5700 0x07
300 #define BGE_ASICREV_BCM5780 0x08
301 #define BGE_ASICREV_BCM5714 0x09
302 #define BGE_ASICREV_BCM5755 0x0a
303 #define BGE_ASICREV_BCM5754 0x0b
304 #define BGE_ASICREV_BCM5787 0x0b
305 #define BGE_ASICREV_BCM5906 0x0c
308 #define BGE_CHIPREV(x) ((x) >> 24)
309 #define BGE_CHIPREV_5700_AX 0x70
310 #define BGE_CHIPREV_5700_BX 0x71
311 #define BGE_CHIPREV_5700_CX 0x72
312 #define BGE_CHIPREV_5701_AX 0x00
313 #define BGE_CHIPREV_5703_AX 0x10
314 #define BGE_CHIPREV_5704_AX 0x20
315 #define BGE_CHIPREV_5704_BX 0x21
316 #define BGE_CHIPREV_5750_AX 0x40
317 #define BGE_CHIPREV_5750_BX 0x41
319 /* PCI DMA Read/Write Control register */
320 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF
321 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700
322 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800
323 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000
324 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000
325 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000
326 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000
327 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000
328 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000
329 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000
330 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000
331 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000
333 #define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16)
334 #define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19)
335 #define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24)
336 #define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28)
338 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000
339 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100
340 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200
341 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300
342 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400
343 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500
344 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600
345 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700
347 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000
348 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800
349 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000
350 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800
351 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000
352 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800
353 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000
354 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800
357 * PCI state register -- note, this register is read only
358 * unless the PCISTATE_WR bit of the PCI Misc. Host Control
361 #define BGE_PCISTATE_FORCE_RESET 0x00000001
362 #define BGE_PCISTATE_INTR_STATE 0x00000002
363 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */
364 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */
365 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */
366 #define BGE_PCISTATE_WANT_EXPROM 0x00000020
367 #define BGE_PCISTATE_EXPROM_RETRY 0x00000040
368 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100
369 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00
372 * PCI Clock Control register -- note, this register is read only
373 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control
376 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F
377 #define BGE_PCICLOCKCTL_M66EN 0x00000080
378 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200
379 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400
380 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800
381 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000
382 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000
383 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000
384 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000
385 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000
388 #ifndef PCIM_CMD_MWIEN
389 #define PCIM_CMD_MWIEN 0x0010
393 * High priority mailbox registers
394 * Each mailbox is 64-bits wide, though we only use the
395 * lower 32 bits. To write a 64-bit value, write the upper 32 bits
396 * first. The NIC will load the mailbox after the lower 32 bit word
399 #define BGE_MBX_IRQ0_HI 0x0200
400 #define BGE_MBX_IRQ0_LO 0x0204
401 #define BGE_MBX_IRQ1_HI 0x0208
402 #define BGE_MBX_IRQ1_LO 0x020C
403 #define BGE_MBX_IRQ2_HI 0x0210
404 #define BGE_MBX_IRQ2_LO 0x0214
405 #define BGE_MBX_IRQ3_HI 0x0218
406 #define BGE_MBX_IRQ3_LO 0x021C
407 #define BGE_MBX_GEN0_HI 0x0220
408 #define BGE_MBX_GEN0_LO 0x0224
409 #define BGE_MBX_GEN1_HI 0x0228
410 #define BGE_MBX_GEN1_LO 0x022C
411 #define BGE_MBX_GEN2_HI 0x0230
412 #define BGE_MBX_GEN2_LO 0x0234
413 #define BGE_MBX_GEN3_HI 0x0228
414 #define BGE_MBX_GEN3_LO 0x022C
415 #define BGE_MBX_GEN4_HI 0x0240
416 #define BGE_MBX_GEN4_LO 0x0244
417 #define BGE_MBX_GEN5_HI 0x0248
418 #define BGE_MBX_GEN5_LO 0x024C
419 #define BGE_MBX_GEN6_HI 0x0250
420 #define BGE_MBX_GEN6_LO 0x0254
421 #define BGE_MBX_GEN7_HI 0x0258
422 #define BGE_MBX_GEN7_LO 0x025C
423 #define BGE_MBX_RELOAD_STATS_HI 0x0260
424 #define BGE_MBX_RELOAD_STATS_LO 0x0264
425 #define BGE_MBX_RX_STD_PROD_HI 0x0268
426 #define BGE_MBX_RX_STD_PROD_LO 0x026C
427 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270
428 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274
429 #define BGE_MBX_RX_MINI_PROD_HI 0x0278
430 #define BGE_MBX_RX_MINI_PROD_LO 0x027C
431 #define BGE_MBX_RX_CONS0_HI 0x0280
432 #define BGE_MBX_RX_CONS0_LO 0x0284
433 #define BGE_MBX_RX_CONS1_HI 0x0288
434 #define BGE_MBX_RX_CONS1_LO 0x028C
435 #define BGE_MBX_RX_CONS2_HI 0x0290
436 #define BGE_MBX_RX_CONS2_LO 0x0294
437 #define BGE_MBX_RX_CONS3_HI 0x0298
438 #define BGE_MBX_RX_CONS3_LO 0x029C
439 #define BGE_MBX_RX_CONS4_HI 0x02A0
440 #define BGE_MBX_RX_CONS4_LO 0x02A4
441 #define BGE_MBX_RX_CONS5_HI 0x02A8
442 #define BGE_MBX_RX_CONS5_LO 0x02AC
443 #define BGE_MBX_RX_CONS6_HI 0x02B0
444 #define BGE_MBX_RX_CONS6_LO 0x02B4
445 #define BGE_MBX_RX_CONS7_HI 0x02B8
446 #define BGE_MBX_RX_CONS7_LO 0x02BC
447 #define BGE_MBX_RX_CONS8_HI 0x02C0
448 #define BGE_MBX_RX_CONS8_LO 0x02C4
449 #define BGE_MBX_RX_CONS9_HI 0x02C8
450 #define BGE_MBX_RX_CONS9_LO 0x02CC
451 #define BGE_MBX_RX_CONS10_HI 0x02D0
452 #define BGE_MBX_RX_CONS10_LO 0x02D4
453 #define BGE_MBX_RX_CONS11_HI 0x02D8
454 #define BGE_MBX_RX_CONS11_LO 0x02DC
455 #define BGE_MBX_RX_CONS12_HI 0x02E0
456 #define BGE_MBX_RX_CONS12_LO 0x02E4
457 #define BGE_MBX_RX_CONS13_HI 0x02E8
458 #define BGE_MBX_RX_CONS13_LO 0x02EC
459 #define BGE_MBX_RX_CONS14_HI 0x02F0
460 #define BGE_MBX_RX_CONS14_LO 0x02F4
461 #define BGE_MBX_RX_CONS15_HI 0x02F8
462 #define BGE_MBX_RX_CONS15_LO 0x02FC
463 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300
464 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304
465 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308
466 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C
467 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310
468 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314
469 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318
470 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C
471 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320
472 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324
473 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328
474 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C
475 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330
476 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334
477 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338
478 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C
479 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340
480 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344
481 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348
482 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C
483 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350
484 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354
485 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358
486 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C
487 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360
488 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364
489 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368
490 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C
491 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370
492 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374
493 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378
494 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C
495 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380
496 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384
497 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388
498 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C
499 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390
500 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394
501 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398
502 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C
503 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0
504 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4
505 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8
506 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC
507 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0
508 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4
509 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8
510 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC
511 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0
512 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4
513 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8
514 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC
515 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0
516 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4
517 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8
518 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC
519 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0
520 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4
521 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8
522 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC
523 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0
524 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4
525 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8
526 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC
528 #define BGE_TX_RINGS_MAX 4
529 #define BGE_TX_RINGS_EXTSSRAM_MAX 16
530 #define BGE_RX_RINGS_MAX 16
532 /* Ethernet MAC control registers */
533 #define BGE_MAC_MODE 0x0400
534 #define BGE_MAC_STS 0x0404
535 #define BGE_MAC_EVT_ENB 0x0408
536 #define BGE_MAC_LED_CTL 0x040C
537 #define BGE_MAC_ADDR1_LO 0x0410
538 #define BGE_MAC_ADDR1_HI 0x0414
539 #define BGE_MAC_ADDR2_LO 0x0418
540 #define BGE_MAC_ADDR2_HI 0x041C
541 #define BGE_MAC_ADDR3_LO 0x0420
542 #define BGE_MAC_ADDR3_HI 0x0424
543 #define BGE_MAC_ADDR4_LO 0x0428
544 #define BGE_MAC_ADDR4_HI 0x042C
545 #define BGE_WOL_PATPTR 0x0430
546 #define BGE_WOL_PATCFG 0x0434
547 #define BGE_TX_RANDOM_BACKOFF 0x0438
548 #define BGE_RX_MTU 0x043C
549 #define BGE_GBIT_PCS_TEST 0x0440
550 #define BGE_TX_TBI_AUTONEG 0x0444
551 #define BGE_RX_TBI_AUTONEG 0x0448
552 #define BGE_MI_COMM 0x044C
553 #define BGE_MI_STS 0x0450
554 #define BGE_MI_MODE 0x0454
555 #define BGE_AUTOPOLL_STS 0x0458
556 #define BGE_TX_MODE 0x045C
557 #define BGE_TX_STS 0x0460
558 #define BGE_TX_LENGTHS 0x0464
559 #define BGE_RX_MODE 0x0468
560 #define BGE_RX_STS 0x046C
561 #define BGE_MAR0 0x0470
562 #define BGE_MAR1 0x0474
563 #define BGE_MAR2 0x0478
564 #define BGE_MAR3 0x047C
565 #define BGE_RX_BD_RULES_CTL0 0x0480
566 #define BGE_RX_BD_RULES_MASKVAL0 0x0484
567 #define BGE_RX_BD_RULES_CTL1 0x0488
568 #define BGE_RX_BD_RULES_MASKVAL1 0x048C
569 #define BGE_RX_BD_RULES_CTL2 0x0490
570 #define BGE_RX_BD_RULES_MASKVAL2 0x0494
571 #define BGE_RX_BD_RULES_CTL3 0x0498
572 #define BGE_RX_BD_RULES_MASKVAL3 0x049C
573 #define BGE_RX_BD_RULES_CTL4 0x04A0
574 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4
575 #define BGE_RX_BD_RULES_CTL5 0x04A8
576 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC
577 #define BGE_RX_BD_RULES_CTL6 0x04B0
578 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4
579 #define BGE_RX_BD_RULES_CTL7 0x04B8
580 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC
581 #define BGE_RX_BD_RULES_CTL8 0x04C0
582 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4
583 #define BGE_RX_BD_RULES_CTL9 0x04C8
584 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC
585 #define BGE_RX_BD_RULES_CTL10 0x04D0
586 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4
587 #define BGE_RX_BD_RULES_CTL11 0x04D8
588 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC
589 #define BGE_RX_BD_RULES_CTL12 0x04E0
590 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4
591 #define BGE_RX_BD_RULES_CTL13 0x04E8
592 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC
593 #define BGE_RX_BD_RULES_CTL14 0x04F0
594 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4
595 #define BGE_RX_BD_RULES_CTL15 0x04F8
596 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC
597 #define BGE_RX_RULES_CFG 0x0500
598 #define BGE_SERDES_CFG 0x0590
599 #define BGE_SERDES_STS 0x0594
600 #define BGE_SGDIG_CFG 0x05B0
601 #define BGE_SGDIG_STS 0x05B4
602 #define BGE_MAC_STATS 0x0800
604 /* Ethernet MAC Mode register */
605 #define BGE_MACMODE_RESET 0x00000001
606 #define BGE_MACMODE_HALF_DUPLEX 0x00000002
607 #define BGE_MACMODE_PORTMODE 0x0000000C
608 #define BGE_MACMODE_LOOPBACK 0x00000010
609 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080
610 #define BGE_MACMODE_TX_BURST_ENB 0x00000100
611 #define BGE_MACMODE_MAX_DEFER 0x00000200
612 #define BGE_MACMODE_LINK_POLARITY 0x00000400
613 #define BGE_MACMODE_RX_STATS_ENB 0x00000800
614 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000
615 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000
616 #define BGE_MACMODE_TX_STATS_ENB 0x00004000
617 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000
618 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000
619 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000
620 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000
621 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000
622 #define BGE_MACMODE_MIP_ENB 0x00100000
623 #define BGE_MACMODE_TXDMA_ENB 0x00200000
624 #define BGE_MACMODE_RXDMA_ENB 0x00400000
625 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000
627 #define BGE_PORTMODE_NONE 0x00000000
628 #define BGE_PORTMODE_MII 0x00000004
629 #define BGE_PORTMODE_GMII 0x00000008
630 #define BGE_PORTMODE_TBI 0x0000000C
632 /* MAC Status register */
633 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001
634 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002
635 #define BGE_MACSTAT_RX_CFG 0x00000004
636 #define BGE_MACSTAT_CFG_CHANGED 0x00000008
637 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010
638 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400
639 #define BGE_MACSTAT_LINK_CHANGED 0x00001000
640 #define BGE_MACSTAT_MI_COMPLETE 0x00400000
641 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000
642 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000
643 #define BGE_MACSTAT_ODI_ERROR 0x02000000
644 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000
645 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000
647 /* MAC Event Enable Register */
648 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400
649 #define BGE_EVTENB_LINK_CHANGED 0x00001000
650 #define BGE_EVTENB_MI_COMPLETE 0x00400000
651 #define BGE_EVTENB_MI_INTERRUPT 0x00800000
652 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000
653 #define BGE_EVTENB_ODI_ERROR 0x02000000
654 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000
655 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000
657 /* LED Control Register */
658 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001
659 #define BGE_LEDCTL_1000MBPS_LED 0x00000002
660 #define BGE_LEDCTL_100MBPS_LED 0x00000004
661 #define BGE_LEDCTL_10MBPS_LED 0x00000008
662 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010
663 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020
664 #define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040
665 #define BGE_LEDCTL_1000MBPS_STS 0x00000080
666 #define BGE_LEDCTL_100MBPS_STS 0x00000100
667 #define BGE_LEDCTL_10MBPS_STS 0x00000200
668 #define BGE_LEDCTL_TRADLED_STS 0x00000400
669 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000
670 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000
672 /* TX backoff seed register */
673 #define BGE_TX_BACKOFF_SEED_MASK 0x3F
675 /* Autopoll status register */
676 #define BGE_AUTOPOLLSTS_ERROR 0x00000001
678 /* Transmit MAC mode register */
679 #define BGE_TXMODE_RESET 0x00000001
680 #define BGE_TXMODE_ENABLE 0x00000002
681 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010
682 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020
683 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040
685 /* Transmit MAC status register */
686 #define BGE_TXSTAT_RX_XOFFED 0x00000001
687 #define BGE_TXSTAT_SENT_XOFF 0x00000002
688 #define BGE_TXSTAT_SENT_XON 0x00000004
689 #define BGE_TXSTAT_LINK_UP 0x00000008
690 #define BGE_TXSTAT_ODI_UFLOW 0x00000010
691 #define BGE_TXSTAT_ODI_OFLOW 0x00000020
693 /* Transmit MAC lengths register */
694 #define BGE_TXLEN_SLOTTIME 0x000000FF
695 #define BGE_TXLEN_IPG 0x00000F00
696 #define BGE_TXLEN_CRS 0x00003000
698 /* Receive MAC mode register */
699 #define BGE_RXMODE_RESET 0x00000001
700 #define BGE_RXMODE_ENABLE 0x00000002
701 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004
702 #define BGE_RXMODE_RX_GIANTS 0x00000020
703 #define BGE_RXMODE_RX_RUNTS 0x00000040
704 #define BGE_RXMODE_8022_LENCHECK 0x00000080
705 #define BGE_RXMODE_RX_PROMISC 0x00000100
706 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200
707 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400
709 /* Receive MAC status register */
710 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001
711 #define BGE_RXSTAT_RCVD_XOFF 0x00000002
712 #define BGE_RXSTAT_RCVD_XON 0x00000004
714 /* Receive Rules Control register */
715 #define BGE_RXRULECTL_OFFSET 0x000000FF
716 #define BGE_RXRULECTL_CLASS 0x00001F00
717 #define BGE_RXRULECTL_HDRTYPE 0x0000E000
718 #define BGE_RXRULECTL_COMPARE_OP 0x00030000
719 #define BGE_RXRULECTL_MAP 0x01000000
720 #define BGE_RXRULECTL_DISCARD 0x02000000
721 #define BGE_RXRULECTL_MASK 0x04000000
722 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000
723 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000
724 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000
725 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000
727 /* Receive Rules Mask register */
728 #define BGE_RXRULEMASK_VALUE 0x0000FFFF
729 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000
731 /* SERDES configuration register */
732 #define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */
733 #define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */
734 #define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */
735 #define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */
736 #define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */
737 #define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */
738 #define BGE_SERDESCFG_TXMODE 0x00001000
739 #define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */
740 #define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */
741 #define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */
742 #define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */
743 #define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */
744 #define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */
745 #define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */
746 #define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */
747 #define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */
749 /* SERDES status register */
750 #define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */
751 #define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */
753 /* SGDIG config (not documented) */
754 #define BGE_SGDIGCFG_PAUSE_CAP 0x00000800
755 #define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000
756 #define BGE_SGDIGCFG_SEND 0x40000000
757 #define BGE_SGDIGCFG_AUTO 0x80000000
759 /* SGDIG status (not documented) */
760 #define BGE_SGDIGSTS_PAUSE_CAP 0x00080000
761 #define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000
762 #define BGE_SGDIGSTS_DONE 0x00000002
765 /* MI communication register */
766 #define BGE_MICOMM_DATA 0x0000FFFF
767 #define BGE_MICOMM_REG 0x001F0000
768 #define BGE_MICOMM_PHY 0x03E00000
769 #define BGE_MICOMM_CMD 0x0C000000
770 #define BGE_MICOMM_READFAIL 0x10000000
771 #define BGE_MICOMM_BUSY 0x20000000
773 #define BGE_MIREG(x) ((x & 0x1F) << 16)
774 #define BGE_MIPHY(x) ((x & 0x1F) << 21)
775 #define BGE_MICMD_WRITE 0x04000000
776 #define BGE_MICMD_READ 0x08000000
778 /* MI status register */
779 #define BGE_MISTS_LINK 0x00000001
780 #define BGE_MISTS_10MBPS 0x00000002
782 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002
783 #define BGE_MIMODE_AUTOPOLL 0x00000010
784 #define BGE_MIMODE_CLKCNT 0x001F0000
788 * Send data initiator control registers.
790 #define BGE_SDI_MODE 0x0C00
791 #define BGE_SDI_STATUS 0x0C04
792 #define BGE_SDI_STATS_CTL 0x0C08
793 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C
794 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10
795 #define BGE_LOCSTATS_COS0 0x0C80
796 #define BGE_LOCSTATS_COS1 0x0C84
797 #define BGE_LOCSTATS_COS2 0x0C88
798 #define BGE_LOCSTATS_COS3 0x0C8C
799 #define BGE_LOCSTATS_COS4 0x0C90
800 #define BGE_LOCSTATS_COS5 0x0C84
801 #define BGE_LOCSTATS_COS6 0x0C98
802 #define BGE_LOCSTATS_COS7 0x0C9C
803 #define BGE_LOCSTATS_COS8 0x0CA0
804 #define BGE_LOCSTATS_COS9 0x0CA4
805 #define BGE_LOCSTATS_COS10 0x0CA8
806 #define BGE_LOCSTATS_COS11 0x0CAC
807 #define BGE_LOCSTATS_COS12 0x0CB0
808 #define BGE_LOCSTATS_COS13 0x0CB4
809 #define BGE_LOCSTATS_COS14 0x0CB8
810 #define BGE_LOCSTATS_COS15 0x0CBC
811 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0
812 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4
813 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8
814 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC
815 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0
816 #define BGE_LOCSTATS_IRQS 0x0CD4
817 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8
818 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC
820 /* Send Data Initiator mode register */
821 #define BGE_SDIMODE_RESET 0x00000001
822 #define BGE_SDIMODE_ENABLE 0x00000002
823 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004
825 /* Send Data Initiator stats register */
826 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004
828 /* Send Data Initiator stats control register */
829 #define BGE_SDISTATSCTL_ENABLE 0x00000001
830 #define BGE_SDISTATSCTL_FASTER 0x00000002
831 #define BGE_SDISTATSCTL_CLEAR 0x00000004
832 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008
833 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010
836 * Send Data Completion Control registers
838 #define BGE_SDC_MODE 0x1000
839 #define BGE_SDC_STATUS 0x1004
841 /* Send Data completion mode register */
842 #define BGE_SDCMODE_RESET 0x00000001
843 #define BGE_SDCMODE_ENABLE 0x00000002
844 #define BGE_SDCMODE_ATTN 0x00000004
846 /* Send Data completion status register */
847 #define BGE_SDCSTAT_ATTN 0x00000004
850 * Send BD Ring Selector Control registers
852 #define BGE_SRS_MODE 0x1400
853 #define BGE_SRS_STATUS 0x1404
854 #define BGE_SRS_HWDIAG 0x1408
855 #define BGE_SRS_LOC_NIC_CONS0 0x1440
856 #define BGE_SRS_LOC_NIC_CONS1 0x1444
857 #define BGE_SRS_LOC_NIC_CONS2 0x1448
858 #define BGE_SRS_LOC_NIC_CONS3 0x144C
859 #define BGE_SRS_LOC_NIC_CONS4 0x1450
860 #define BGE_SRS_LOC_NIC_CONS5 0x1454
861 #define BGE_SRS_LOC_NIC_CONS6 0x1458
862 #define BGE_SRS_LOC_NIC_CONS7 0x145C
863 #define BGE_SRS_LOC_NIC_CONS8 0x1460
864 #define BGE_SRS_LOC_NIC_CONS9 0x1464
865 #define BGE_SRS_LOC_NIC_CONS10 0x1468
866 #define BGE_SRS_LOC_NIC_CONS11 0x146C
867 #define BGE_SRS_LOC_NIC_CONS12 0x1470
868 #define BGE_SRS_LOC_NIC_CONS13 0x1474
869 #define BGE_SRS_LOC_NIC_CONS14 0x1478
870 #define BGE_SRS_LOC_NIC_CONS15 0x147C
872 /* Send BD Ring Selector Mode register */
873 #define BGE_SRSMODE_RESET 0x00000001
874 #define BGE_SRSMODE_ENABLE 0x00000002
875 #define BGE_SRSMODE_ATTN 0x00000004
877 /* Send BD Ring Selector Status register */
878 #define BGE_SRSSTAT_ERROR 0x00000004
880 /* Send BD Ring Selector HW Diagnostics register */
881 #define BGE_SRSHWDIAG_STATE 0x0000000F
882 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0
883 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00
884 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000
887 * Send BD Initiator Selector Control registers
889 #define BGE_SBDI_MODE 0x1800
890 #define BGE_SBDI_STATUS 0x1804
891 #define BGE_SBDI_LOC_NIC_PROD0 0x1808
892 #define BGE_SBDI_LOC_NIC_PROD1 0x180C
893 #define BGE_SBDI_LOC_NIC_PROD2 0x1810
894 #define BGE_SBDI_LOC_NIC_PROD3 0x1814
895 #define BGE_SBDI_LOC_NIC_PROD4 0x1818
896 #define BGE_SBDI_LOC_NIC_PROD5 0x181C
897 #define BGE_SBDI_LOC_NIC_PROD6 0x1820
898 #define BGE_SBDI_LOC_NIC_PROD7 0x1824
899 #define BGE_SBDI_LOC_NIC_PROD8 0x1828
900 #define BGE_SBDI_LOC_NIC_PROD9 0x182C
901 #define BGE_SBDI_LOC_NIC_PROD10 0x1830
902 #define BGE_SBDI_LOC_NIC_PROD11 0x1834
903 #define BGE_SBDI_LOC_NIC_PROD12 0x1838
904 #define BGE_SBDI_LOC_NIC_PROD13 0x183C
905 #define BGE_SBDI_LOC_NIC_PROD14 0x1840
906 #define BGE_SBDI_LOC_NIC_PROD15 0x1844
908 /* Send BD Initiator Mode register */
909 #define BGE_SBDIMODE_RESET 0x00000001
910 #define BGE_SBDIMODE_ENABLE 0x00000002
911 #define BGE_SBDIMODE_ATTN 0x00000004
913 /* Send BD Initiator Status register */
914 #define BGE_SBDISTAT_ERROR 0x00000004
917 * Send BD Completion Control registers
919 #define BGE_SBDC_MODE 0x1C00
920 #define BGE_SBDC_STATUS 0x1C04
922 /* Send BD Completion Control Mode register */
923 #define BGE_SBDCMODE_RESET 0x00000001
924 #define BGE_SBDCMODE_ENABLE 0x00000002
925 #define BGE_SBDCMODE_ATTN 0x00000004
927 /* Send BD Completion Control Status register */
928 #define BGE_SBDCSTAT_ATTN 0x00000004
931 * Receive List Placement Control registers
933 #define BGE_RXLP_MODE 0x2000
934 #define BGE_RXLP_STATUS 0x2004
935 #define BGE_RXLP_SEL_LIST_LOCK 0x2008
936 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C
937 #define BGE_RXLP_CFG 0x2010
938 #define BGE_RXLP_STATS_CTL 0x2014
939 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018
940 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C
941 #define BGE_RXLP_HEAD0 0x2100
942 #define BGE_RXLP_TAIL0 0x2104
943 #define BGE_RXLP_COUNT0 0x2108
944 #define BGE_RXLP_HEAD1 0x2110
945 #define BGE_RXLP_TAIL1 0x2114
946 #define BGE_RXLP_COUNT1 0x2118
947 #define BGE_RXLP_HEAD2 0x2120
948 #define BGE_RXLP_TAIL2 0x2124
949 #define BGE_RXLP_COUNT2 0x2128
950 #define BGE_RXLP_HEAD3 0x2130
951 #define BGE_RXLP_TAIL3 0x2134
952 #define BGE_RXLP_COUNT3 0x2138
953 #define BGE_RXLP_HEAD4 0x2140
954 #define BGE_RXLP_TAIL4 0x2144
955 #define BGE_RXLP_COUNT4 0x2148
956 #define BGE_RXLP_HEAD5 0x2150
957 #define BGE_RXLP_TAIL5 0x2154
958 #define BGE_RXLP_COUNT5 0x2158
959 #define BGE_RXLP_HEAD6 0x2160
960 #define BGE_RXLP_TAIL6 0x2164
961 #define BGE_RXLP_COUNT6 0x2168
962 #define BGE_RXLP_HEAD7 0x2170
963 #define BGE_RXLP_TAIL7 0x2174
964 #define BGE_RXLP_COUNT7 0x2178
965 #define BGE_RXLP_HEAD8 0x2180
966 #define BGE_RXLP_TAIL8 0x2184
967 #define BGE_RXLP_COUNT8 0x2188
968 #define BGE_RXLP_HEAD9 0x2190
969 #define BGE_RXLP_TAIL9 0x2194
970 #define BGE_RXLP_COUNT9 0x2198
971 #define BGE_RXLP_HEAD10 0x21A0
972 #define BGE_RXLP_TAIL10 0x21A4
973 #define BGE_RXLP_COUNT10 0x21A8
974 #define BGE_RXLP_HEAD11 0x21B0
975 #define BGE_RXLP_TAIL11 0x21B4
976 #define BGE_RXLP_COUNT11 0x21B8
977 #define BGE_RXLP_HEAD12 0x21C0
978 #define BGE_RXLP_TAIL12 0x21C4
979 #define BGE_RXLP_COUNT12 0x21C8
980 #define BGE_RXLP_HEAD13 0x21D0
981 #define BGE_RXLP_TAIL13 0x21D4
982 #define BGE_RXLP_COUNT13 0x21D8
983 #define BGE_RXLP_HEAD14 0x21E0
984 #define BGE_RXLP_TAIL14 0x21E4
985 #define BGE_RXLP_COUNT14 0x21E8
986 #define BGE_RXLP_HEAD15 0x21F0
987 #define BGE_RXLP_TAIL15 0x21F4
988 #define BGE_RXLP_COUNT15 0x21F8
989 #define BGE_RXLP_LOCSTAT_COS0 0x2200
990 #define BGE_RXLP_LOCSTAT_COS1 0x2204
991 #define BGE_RXLP_LOCSTAT_COS2 0x2208
992 #define BGE_RXLP_LOCSTAT_COS3 0x220C
993 #define BGE_RXLP_LOCSTAT_COS4 0x2210
994 #define BGE_RXLP_LOCSTAT_COS5 0x2214
995 #define BGE_RXLP_LOCSTAT_COS6 0x2218
996 #define BGE_RXLP_LOCSTAT_COS7 0x221C
997 #define BGE_RXLP_LOCSTAT_COS8 0x2220
998 #define BGE_RXLP_LOCSTAT_COS9 0x2224
999 #define BGE_RXLP_LOCSTAT_COS10 0x2228
1000 #define BGE_RXLP_LOCSTAT_COS11 0x222C
1001 #define BGE_RXLP_LOCSTAT_COS12 0x2230
1002 #define BGE_RXLP_LOCSTAT_COS13 0x2234
1003 #define BGE_RXLP_LOCSTAT_COS14 0x2238
1004 #define BGE_RXLP_LOCSTAT_COS15 0x223C
1005 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240
1006 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244
1007 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248
1008 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C
1009 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250
1010 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254
1011 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258
1014 /* Receive List Placement mode register */
1015 #define BGE_RXLPMODE_RESET 0x00000001
1016 #define BGE_RXLPMODE_ENABLE 0x00000002
1017 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004
1018 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008
1019 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010
1021 /* Receive List Placement Status register */
1022 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004
1023 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008
1024 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010
1027 * Receive Data and Receive BD Initiator Control Registers
1029 #define BGE_RDBDI_MODE 0x2400
1030 #define BGE_RDBDI_STATUS 0x2404
1031 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440
1032 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444
1033 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448
1034 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C
1035 #define BGE_RX_STD_RCB_HADDR_HI 0x2450
1036 #define BGE_RX_STD_RCB_HADDR_LO 0x2454
1037 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458
1038 #define BGE_RX_STD_RCB_NICADDR 0x245C
1039 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460
1040 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464
1041 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468
1042 #define BGE_RX_MINI_RCB_NICADDR 0x246C
1043 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470
1044 #define BGE_RDBDI_STD_RX_CONS 0x2474
1045 #define BGE_RDBDI_MINI_RX_CONS 0x2478
1046 #define BGE_RDBDI_RETURN_PROD0 0x2480
1047 #define BGE_RDBDI_RETURN_PROD1 0x2484
1048 #define BGE_RDBDI_RETURN_PROD2 0x2488
1049 #define BGE_RDBDI_RETURN_PROD3 0x248C
1050 #define BGE_RDBDI_RETURN_PROD4 0x2490
1051 #define BGE_RDBDI_RETURN_PROD5 0x2494
1052 #define BGE_RDBDI_RETURN_PROD6 0x2498
1053 #define BGE_RDBDI_RETURN_PROD7 0x249C
1054 #define BGE_RDBDI_RETURN_PROD8 0x24A0
1055 #define BGE_RDBDI_RETURN_PROD9 0x24A4
1056 #define BGE_RDBDI_RETURN_PROD10 0x24A8
1057 #define BGE_RDBDI_RETURN_PROD11 0x24AC
1058 #define BGE_RDBDI_RETURN_PROD12 0x24B0
1059 #define BGE_RDBDI_RETURN_PROD13 0x24B4
1060 #define BGE_RDBDI_RETURN_PROD14 0x24B8
1061 #define BGE_RDBDI_RETURN_PROD15 0x24BC
1062 #define BGE_RDBDI_HWDIAG 0x24C0
1065 /* Receive Data and Receive BD Initiator Mode register */
1066 #define BGE_RDBDIMODE_RESET 0x00000001
1067 #define BGE_RDBDIMODE_ENABLE 0x00000002
1068 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004
1069 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008
1070 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010
1072 /* Receive Data and Receive BD Initiator Status register */
1073 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004
1074 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008
1075 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010
1079 * Receive Data Completion Control registers
1081 #define BGE_RDC_MODE 0x2800
1083 /* Receive Data Completion Mode register */
1084 #define BGE_RDCMODE_RESET 0x00000001
1085 #define BGE_RDCMODE_ENABLE 0x00000002
1086 #define BGE_RDCMODE_ATTN 0x00000004
1089 * Receive BD Initiator Control registers
1091 #define BGE_RBDI_MODE 0x2C00
1092 #define BGE_RBDI_STATUS 0x2C04
1093 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08
1094 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C
1095 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10
1096 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14
1097 #define BGE_RBDI_STD_REPL_THRESH 0x2C18
1098 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C
1100 /* Receive BD Initiator Mode register */
1101 #define BGE_RBDIMODE_RESET 0x00000001
1102 #define BGE_RBDIMODE_ENABLE 0x00000002
1103 #define BGE_RBDIMODE_ATTN 0x00000004
1105 /* Receive BD Initiator Status register */
1106 #define BGE_RBDISTAT_ATTN 0x00000004
1109 * Receive BD Completion Control registers
1111 #define BGE_RBDC_MODE 0x3000
1112 #define BGE_RBDC_STATUS 0x3004
1113 #define BGE_RBDC_JUMBO_BD_PROD 0x3008
1114 #define BGE_RBDC_STD_BD_PROD 0x300C
1115 #define BGE_RBDC_MINI_BD_PROD 0x3010
1117 /* Receive BD completion mode register */
1118 #define BGE_RBDCMODE_RESET 0x00000001
1119 #define BGE_RBDCMODE_ENABLE 0x00000002
1120 #define BGE_RBDCMODE_ATTN 0x00000004
1122 /* Receive BD completion status register */
1123 #define BGE_RBDCSTAT_ERROR 0x00000004
1126 * Receive List Selector Control registers
1128 #define BGE_RXLS_MODE 0x3400
1129 #define BGE_RXLS_STATUS 0x3404
1131 /* Receive List Selector Mode register */
1132 #define BGE_RXLSMODE_RESET 0x00000001
1133 #define BGE_RXLSMODE_ENABLE 0x00000002
1134 #define BGE_RXLSMODE_ATTN 0x00000004
1136 /* Receive List Selector Status register */
1137 #define BGE_RXLSSTAT_ERROR 0x00000004
1140 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs)
1142 #define BGE_MBCF_MODE 0x3800
1143 #define BGE_MBCF_STATUS 0x3804
1145 /* Mbuf Cluster Free mode register */
1146 #define BGE_MBCFMODE_RESET 0x00000001
1147 #define BGE_MBCFMODE_ENABLE 0x00000002
1148 #define BGE_MBCFMODE_ATTN 0x00000004
1150 /* Mbuf Cluster Free status register */
1151 #define BGE_MBCFSTAT_ERROR 0x00000004
1154 * Host Coalescing Control registers
1156 #define BGE_HCC_MODE 0x3C00
1157 #define BGE_HCC_STATUS 0x3C04
1158 #define BGE_HCC_RX_COAL_TICKS 0x3C08
1159 #define BGE_HCC_TX_COAL_TICKS 0x3C0C
1160 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10
1161 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14
1162 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */
1163 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */
1164 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */
1165 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */
1166 #define BGE_HCC_STATS_TICKS 0x3C28
1167 #define BGE_HCC_STATS_ADDR_HI 0x3C30
1168 #define BGE_HCC_STATS_ADDR_LO 0x3C34
1169 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38
1170 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C
1171 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */
1172 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */
1173 #define BGE_FLOW_ATTN 0x3C48
1174 #define BGE_HCC_JUMBO_BD_CONS 0x3C50
1175 #define BGE_HCC_STD_BD_CONS 0x3C54
1176 #define BGE_HCC_MINI_BD_CONS 0x3C58
1177 #define BGE_HCC_RX_RETURN_PROD0 0x3C80
1178 #define BGE_HCC_RX_RETURN_PROD1 0x3C84
1179 #define BGE_HCC_RX_RETURN_PROD2 0x3C88
1180 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C
1181 #define BGE_HCC_RX_RETURN_PROD4 0x3C90
1182 #define BGE_HCC_RX_RETURN_PROD5 0x3C94
1183 #define BGE_HCC_RX_RETURN_PROD6 0x3C98
1184 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C
1185 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0
1186 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4
1187 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8
1188 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC
1189 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0
1190 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4
1191 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8
1192 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC
1193 #define BGE_HCC_TX_BD_CONS0 0x3CC0
1194 #define BGE_HCC_TX_BD_CONS1 0x3CC4
1195 #define BGE_HCC_TX_BD_CONS2 0x3CC8
1196 #define BGE_HCC_TX_BD_CONS3 0x3CCC
1197 #define BGE_HCC_TX_BD_CONS4 0x3CD0
1198 #define BGE_HCC_TX_BD_CONS5 0x3CD4
1199 #define BGE_HCC_TX_BD_CONS6 0x3CD8
1200 #define BGE_HCC_TX_BD_CONS7 0x3CDC
1201 #define BGE_HCC_TX_BD_CONS8 0x3CE0
1202 #define BGE_HCC_TX_BD_CONS9 0x3CE4
1203 #define BGE_HCC_TX_BD_CONS10 0x3CE8
1204 #define BGE_HCC_TX_BD_CONS11 0x3CEC
1205 #define BGE_HCC_TX_BD_CONS12 0x3CF0
1206 #define BGE_HCC_TX_BD_CONS13 0x3CF4
1207 #define BGE_HCC_TX_BD_CONS14 0x3CF8
1208 #define BGE_HCC_TX_BD_CONS15 0x3CFC
1211 /* Host coalescing mode register */
1212 #define BGE_HCCMODE_RESET 0x00000001
1213 #define BGE_HCCMODE_ENABLE 0x00000002
1214 #define BGE_HCCMODE_ATTN 0x00000004
1215 #define BGE_HCCMODE_COAL_NOW 0x00000008
1216 #define BGE_HCCMODE_MSI_BITS 0x00000070
1217 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180
1219 #define BGE_STATBLKSZ_FULL 0x00000000
1220 #define BGE_STATBLKSZ_64BYTE 0x00000080
1221 #define BGE_STATBLKSZ_32BYTE 0x00000100
1223 /* Host coalescing status register */
1224 #define BGE_HCCSTAT_ERROR 0x00000004
1226 /* Flow attention register */
1227 #define BGE_FLOWATTN_MB_LOWAT 0x00000040
1228 #define BGE_FLOWATTN_MEMARB 0x00000080
1229 #define BGE_FLOWATTN_HOSTCOAL 0x00008000
1230 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000
1231 #define BGE_FLOWATTN_RCB_INVAL 0x00020000
1232 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000
1233 #define BGE_FLOWATTN_RDBDI 0x00080000
1234 #define BGE_FLOWATTN_RXLS 0x00100000
1235 #define BGE_FLOWATTN_RXLP 0x00200000
1236 #define BGE_FLOWATTN_RBDC 0x00400000
1237 #define BGE_FLOWATTN_RBDI 0x00800000
1238 #define BGE_FLOWATTN_SDC 0x08000000
1239 #define BGE_FLOWATTN_SDI 0x10000000
1240 #define BGE_FLOWATTN_SRS 0x20000000
1241 #define BGE_FLOWATTN_SBDC 0x40000000
1242 #define BGE_FLOWATTN_SBDI 0x80000000
1245 * Memory arbiter registers
1247 #define BGE_MARB_MODE 0x4000
1248 #define BGE_MARB_STATUS 0x4004
1249 #define BGE_MARB_TRAPADDR_HI 0x4008
1250 #define BGE_MARB_TRAPADDR_LO 0x400C
1252 /* Memory arbiter mode register */
1253 #define BGE_MARBMODE_RESET 0x00000001
1254 #define BGE_MARBMODE_ENABLE 0x00000002
1255 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004
1256 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008
1257 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010
1258 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020
1259 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040
1260 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080
1261 #define BGE_MARBMODE_PCI_TRAP 0x00000100
1262 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200
1263 #define BGE_MARBMODE_RXQ_TRAP 0x00000400
1264 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800
1265 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000
1266 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000
1267 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000
1268 #define BGE_MARBMODE_MBUF_TRAP 0x00008000
1269 #define BGE_MARBMODE_TXDI_TRAP 0x00010000
1270 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000
1271 #define BGE_MARBMODE_TXBD_TRAP 0x00040000
1272 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000
1273 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000
1274 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000
1275 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000
1276 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000
1277 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000
1278 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000
1280 /* Memory arbiter status register */
1281 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004
1282 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008
1283 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010
1284 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020
1285 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040
1286 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080
1287 #define BGE_MARBSTAT_PCI_TRAP 0x00000100
1288 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200
1289 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400
1290 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800
1291 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000
1292 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000
1293 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000
1294 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000
1295 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000
1296 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000
1297 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000
1298 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000
1299 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000
1300 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000
1301 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000
1302 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000
1303 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000
1304 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000
1307 * Buffer manager control registers
1309 #define BGE_BMAN_MODE 0x4400
1310 #define BGE_BMAN_STATUS 0x4404
1311 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408
1312 #define BGE_BMAN_MBUFPOOL_LEN 0x440C
1313 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410
1314 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414
1315 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418
1316 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C
1317 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420
1318 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424
1319 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428
1320 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C
1321 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430
1322 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434
1323 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438
1324 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C
1325 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440
1326 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444
1327 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448
1328 #define BGE_BMAN_HWDIAG_1 0x444C
1329 #define BGE_BMAN_HWDIAG_2 0x4450
1330 #define BGE_BMAN_HWDIAG_3 0x4454
1332 /* Buffer manager mode register */
1333 #define BGE_BMANMODE_RESET 0x00000001
1334 #define BGE_BMANMODE_ENABLE 0x00000002
1335 #define BGE_BMANMODE_ATTN 0x00000004
1336 #define BGE_BMANMODE_TESTMODE 0x00000008
1337 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010
1339 /* Buffer manager status register */
1340 #define BGE_BMANSTAT_ERRO 0x00000004
1341 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010
1345 * Read DMA Control registers
1347 #define BGE_RDMA_MODE 0x4800
1348 #define BGE_RDMA_STATUS 0x4804
1350 /* Read DMA mode register */
1351 #define BGE_RDMAMODE_RESET 0x00000001
1352 #define BGE_RDMAMODE_ENABLE 0x00000002
1353 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
1354 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1355 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010
1356 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
1357 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
1358 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
1359 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
1360 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200
1361 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC
1363 /* Read DMA status register */
1364 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
1365 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1366 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010
1367 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
1368 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
1369 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
1370 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
1371 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200
1374 * Write DMA control registers
1376 #define BGE_WDMA_MODE 0x4C00
1377 #define BGE_WDMA_STATUS 0x4C04
1379 /* Write DMA mode register */
1380 #define BGE_WDMAMODE_RESET 0x00000001
1381 #define BGE_WDMAMODE_ENABLE 0x00000002
1382 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
1383 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1384 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010
1385 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
1386 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
1387 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
1388 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
1389 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200
1390 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC
1392 /* Write DMA status register */
1393 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
1394 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1395 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010
1396 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
1397 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
1398 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
1399 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
1400 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200
1406 #define BGE_RXCPU_MODE 0x5000
1407 #define BGE_RXCPU_STATUS 0x5004
1408 #define BGE_RXCPU_PC 0x501C
1410 /* RX CPU mode register */
1411 #define BGE_RXCPUMODE_RESET 0x00000001
1412 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002
1413 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004
1414 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008
1415 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010
1416 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020
1417 #define BGE_RXCPUMODE_ROMFAIL 0x00000040
1418 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080
1419 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100
1420 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200
1421 #define BGE_RXCPUMODE_HALTCPU 0x00000400
1422 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800
1423 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
1424 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000
1426 /* RX CPU status register */
1427 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001
1428 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
1429 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004
1430 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008
1431 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010
1432 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020
1433 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040
1434 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080
1435 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100
1436 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200
1437 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000
1438 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000
1439 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
1440 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
1441 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
1442 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
1443 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000
1448 #define BGE_VCPU_STATUS 0x5100
1449 #define BGE_VCPU_EXT_CTRL 0x6890
1451 #define BGE_VCPU_STATUS_INIT_DONE 0x04000000
1452 #define BGE_VCPU_STATUS_DRV_RESET 0x08000000
1454 #define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000
1455 #define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
1460 #define BGE_TXCPU_MODE 0x5400
1461 #define BGE_TXCPU_STATUS 0x5404
1462 #define BGE_TXCPU_PC 0x541C
1464 /* TX CPU mode register */
1465 #define BGE_TXCPUMODE_RESET 0x00000001
1466 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002
1467 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004
1468 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008
1469 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010
1470 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020
1471 #define BGE_TXCPUMODE_ROMFAIL 0x00000040
1472 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080
1473 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100
1474 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200
1475 #define BGE_TXCPUMODE_HALTCPU 0x00000400
1476 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800
1477 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
1479 /* TX CPU status register */
1480 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001
1481 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
1482 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004
1483 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008
1484 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010
1485 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020
1486 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040
1487 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080
1488 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100
1489 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200
1490 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000
1491 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000
1492 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
1493 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
1494 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
1495 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
1496 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000
1500 * Low priority mailbox registers
1502 #define BGE_LPMBX_IRQ0_HI 0x5800
1503 #define BGE_LPMBX_IRQ0_LO 0x5804
1504 #define BGE_LPMBX_IRQ1_HI 0x5808
1505 #define BGE_LPMBX_IRQ1_LO 0x580C
1506 #define BGE_LPMBX_IRQ2_HI 0x5810
1507 #define BGE_LPMBX_IRQ2_LO 0x5814
1508 #define BGE_LPMBX_IRQ3_HI 0x5818
1509 #define BGE_LPMBX_IRQ3_LO 0x581C
1510 #define BGE_LPMBX_GEN0_HI 0x5820
1511 #define BGE_LPMBX_GEN0_LO 0x5824
1512 #define BGE_LPMBX_GEN1_HI 0x5828
1513 #define BGE_LPMBX_GEN1_LO 0x582C
1514 #define BGE_LPMBX_GEN2_HI 0x5830
1515 #define BGE_LPMBX_GEN2_LO 0x5834
1516 #define BGE_LPMBX_GEN3_HI 0x5828
1517 #define BGE_LPMBX_GEN3_LO 0x582C
1518 #define BGE_LPMBX_GEN4_HI 0x5840
1519 #define BGE_LPMBX_GEN4_LO 0x5844
1520 #define BGE_LPMBX_GEN5_HI 0x5848
1521 #define BGE_LPMBX_GEN5_LO 0x584C
1522 #define BGE_LPMBX_GEN6_HI 0x5850
1523 #define BGE_LPMBX_GEN6_LO 0x5854
1524 #define BGE_LPMBX_GEN7_HI 0x5858
1525 #define BGE_LPMBX_GEN7_LO 0x585C
1526 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860
1527 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864
1528 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868
1529 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C
1530 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870
1531 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874
1532 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878
1533 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C
1534 #define BGE_LPMBX_RX_CONS0_HI 0x5880
1535 #define BGE_LPMBX_RX_CONS0_LO 0x5884
1536 #define BGE_LPMBX_RX_CONS1_HI 0x5888
1537 #define BGE_LPMBX_RX_CONS1_LO 0x588C
1538 #define BGE_LPMBX_RX_CONS2_HI 0x5890
1539 #define BGE_LPMBX_RX_CONS2_LO 0x5894
1540 #define BGE_LPMBX_RX_CONS3_HI 0x5898
1541 #define BGE_LPMBX_RX_CONS3_LO 0x589C
1542 #define BGE_LPMBX_RX_CONS4_HI 0x58A0
1543 #define BGE_LPMBX_RX_CONS4_LO 0x58A4
1544 #define BGE_LPMBX_RX_CONS5_HI 0x58A8
1545 #define BGE_LPMBX_RX_CONS5_LO 0x58AC
1546 #define BGE_LPMBX_RX_CONS6_HI 0x58B0
1547 #define BGE_LPMBX_RX_CONS6_LO 0x58B4
1548 #define BGE_LPMBX_RX_CONS7_HI 0x58B8
1549 #define BGE_LPMBX_RX_CONS7_LO 0x58BC
1550 #define BGE_LPMBX_RX_CONS8_HI 0x58C0
1551 #define BGE_LPMBX_RX_CONS8_LO 0x58C4
1552 #define BGE_LPMBX_RX_CONS9_HI 0x58C8
1553 #define BGE_LPMBX_RX_CONS9_LO 0x58CC
1554 #define BGE_LPMBX_RX_CONS10_HI 0x58D0
1555 #define BGE_LPMBX_RX_CONS10_LO 0x58D4
1556 #define BGE_LPMBX_RX_CONS11_HI 0x58D8
1557 #define BGE_LPMBX_RX_CONS11_LO 0x58DC
1558 #define BGE_LPMBX_RX_CONS12_HI 0x58E0
1559 #define BGE_LPMBX_RX_CONS12_LO 0x58E4
1560 #define BGE_LPMBX_RX_CONS13_HI 0x58E8
1561 #define BGE_LPMBX_RX_CONS13_LO 0x58EC
1562 #define BGE_LPMBX_RX_CONS14_HI 0x58F0
1563 #define BGE_LPMBX_RX_CONS14_LO 0x58F4
1564 #define BGE_LPMBX_RX_CONS15_HI 0x58F8
1565 #define BGE_LPMBX_RX_CONS15_LO 0x58FC
1566 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900
1567 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904
1568 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908
1569 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C
1570 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910
1571 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914
1572 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918
1573 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C
1574 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920
1575 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924
1576 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928
1577 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C
1578 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930
1579 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934
1580 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938
1581 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C
1582 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940
1583 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944
1584 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948
1585 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C
1586 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950
1587 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954
1588 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958
1589 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C
1590 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960
1591 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964
1592 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968
1593 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C
1594 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970
1595 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974
1596 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978
1597 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C
1598 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980
1599 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984
1600 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988
1601 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C
1602 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990
1603 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994
1604 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998
1605 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C
1606 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0
1607 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4
1608 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8
1609 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC
1610 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0
1611 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4
1612 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8
1613 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC
1614 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0
1615 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4
1616 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8
1617 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC
1618 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0
1619 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4
1620 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8
1621 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC
1622 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0
1623 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4
1624 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8
1625 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC
1626 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0
1627 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4
1628 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8
1629 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC
1632 * Flow throw Queue reset register
1634 #define BGE_FTQ_RESET 0x5C00
1636 #define BGE_FTQRESET_DMAREAD 0x00000002
1637 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004
1638 #define BGE_FTQRESET_DMADONE 0x00000010
1639 #define BGE_FTQRESET_SBDC 0x00000020
1640 #define BGE_FTQRESET_SDI 0x00000040
1641 #define BGE_FTQRESET_WDMA 0x00000080
1642 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100
1643 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200
1644 #define BGE_FTQRESET_SDC 0x00000400
1645 #define BGE_FTQRESET_HCC 0x00000800
1646 #define BGE_FTQRESET_TXFIFO 0x00001000
1647 #define BGE_FTQRESET_MBC 0x00002000
1648 #define BGE_FTQRESET_RBDC 0x00004000
1649 #define BGE_FTQRESET_RXLP 0x00008000
1650 #define BGE_FTQRESET_RDBDI 0x00010000
1651 #define BGE_FTQRESET_RDC 0x00020000
1652 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000
1655 * Message Signaled Interrupt registers
1657 #define BGE_MSI_MODE 0x6000
1658 #define BGE_MSI_STATUS 0x6004
1659 #define BGE_MSI_FIFOACCESS 0x6008
1661 /* MSI mode register */
1662 #define BGE_MSIMODE_RESET 0x00000001
1663 #define BGE_MSIMODE_ENABLE 0x00000002
1664 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004
1665 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1666 #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010
1667 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020
1668 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040
1670 /* MSI status register */
1671 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004
1672 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1673 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010
1674 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020
1675 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040
1679 * DMA Completion registers
1681 #define BGE_DMAC_MODE 0x6400
1683 /* DMA Completion mode register */
1684 #define BGE_DMACMODE_RESET 0x00000001
1685 #define BGE_DMACMODE_ENABLE 0x00000002
1689 * General control registers.
1691 #define BGE_MODE_CTL 0x6800
1692 #define BGE_MISC_CFG 0x6804
1693 #define BGE_MISC_LOCAL_CTL 0x6808
1694 #define BGE_CPU_EVENT 0x6810
1695 #define BGE_EE_ADDR 0x6838
1696 #define BGE_EE_DATA 0x683C
1697 #define BGE_EE_CTL 0x6840
1698 #define BGE_MDI_CTL 0x6844
1699 #define BGE_EE_DELAY 0x6848
1700 #define BGE_FASTBOOT_PC 0x6894
1703 * NVRAM Control registers
1705 #define BGE_NVRAM_CMD 0x7000
1706 #define BGE_NVRAM_STAT 0x7004
1707 #define BGE_NVRAM_WRDATA 0x7008
1708 #define BGE_NVRAM_ADDR 0x700c
1709 #define BGE_NVRAM_RDDATA 0x7010
1710 #define BGE_NVRAM_CFG1 0x7014
1711 #define BGE_NVRAM_CFG2 0x7018
1712 #define BGE_NVRAM_CFG3 0x701c
1713 #define BGE_NVRAM_SWARB 0x7020
1714 #define BGE_NVRAM_ACCESS 0x7024
1715 #define BGE_NVRAM_WRITE1 0x7028
1717 #define BGE_NVRAMCMD_RESET 0x00000001
1718 #define BGE_NVRAMCMD_DONE 0x00000008
1719 #define BGE_NVRAMCMD_START 0x00000010
1720 #define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */
1721 #define BGE_NVRAMCMD_ERASE 0x00000040
1722 #define BGE_NVRAMCMD_FIRST 0x00000080
1723 #define BGE_NVRAMCMD_LAST 0x00000100
1725 #define BGE_NVRAM_READCMD \
1726 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \
1727 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE)
1728 #define BGE_NVRAM_WRITECMD \
1729 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \
1730 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR)
1732 #define BGE_NVRAMSWARB_SET0 0x00000001
1733 #define BGE_NVRAMSWARB_SET1 0x00000002
1734 #define BGE_NVRAMSWARB_SET2 0x00000003
1735 #define BGE_NVRAMSWARB_SET3 0x00000004
1736 #define BGE_NVRAMSWARB_CLR0 0x00000010
1737 #define BGE_NVRAMSWARB_CLR1 0x00000020
1738 #define BGE_NVRAMSWARB_CLR2 0x00000040
1739 #define BGE_NVRAMSWARB_CLR3 0x00000080
1740 #define BGE_NVRAMSWARB_GNT0 0x00000100
1741 #define BGE_NVRAMSWARB_GNT1 0x00000200
1742 #define BGE_NVRAMSWARB_GNT2 0x00000400
1743 #define BGE_NVRAMSWARB_GNT3 0x00000800
1744 #define BGE_NVRAMSWARB_REQ0 0x00001000
1745 #define BGE_NVRAMSWARB_REQ1 0x00002000
1746 #define BGE_NVRAMSWARB_REQ2 0x00004000
1747 #define BGE_NVRAMSWARB_REQ3 0x00008000
1749 #define BGE_NVRAMACC_ENABLE 0x00000001
1750 #define BGE_NVRAMACC_WRENABLE 0x00000002
1752 /* Mode control register */
1753 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001
1754 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002
1755 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004
1756 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010
1757 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020
1758 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200
1759 #define BGE_MODECTL_NO_RX_CRC 0x00000400
1760 #define BGE_MODECTL_RX_BADFRAMES 0x00000800
1761 #define BGE_MODECTL_NO_TX_INTR 0x00002000
1762 #define BGE_MODECTL_NO_RX_INTR 0x00004000
1763 #define BGE_MODECTL_FORCE_PCI32 0x00008000
1764 #define BGE_MODECTL_STACKUP 0x00010000
1765 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000
1766 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000
1767 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000
1768 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000
1769 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000
1770 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000
1771 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000
1772 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000
1773 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000
1774 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000
1776 /* Misc. config register */
1777 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001
1778 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE
1779 #define BGE_MISCCFG_BOARD_ID 0x0001E000
1780 #define BGE_MISCCFG_BOARD_ID_5788 0x00010000
1781 #define BGE_MISCCFG_BOARD_ID_5788M 0x00018000
1782 #define BGE_MISCCFG_EPHY_IDDQ 0x00200000
1784 #define BGE_32BITTIME_66MHZ (0x41 << 1)
1786 /* Misc. Local Control */
1787 #define BGE_MLC_INTR_STATE 0x00000001
1788 #define BGE_MLC_INTR_CLR 0x00000002
1789 #define BGE_MLC_INTR_SET 0x00000004
1790 #define BGE_MLC_INTR_ONATTN 0x00000008
1791 #define BGE_MLC_MISCIO_IN0 0x00000100
1792 #define BGE_MLC_MISCIO_IN1 0x00000200
1793 #define BGE_MLC_MISCIO_IN2 0x00000400
1794 #define BGE_MLC_MISCIO_OUTEN0 0x00000800
1795 #define BGE_MLC_MISCIO_OUTEN1 0x00001000
1796 #define BGE_MLC_MISCIO_OUTEN2 0x00002000
1797 #define BGE_MLC_MISCIO_OUT0 0x00004000
1798 #define BGE_MLC_MISCIO_OUT1 0x00008000
1799 #define BGE_MLC_MISCIO_OUT2 0x00010000
1800 #define BGE_MLC_EXTRAM_ENB 0x00020000
1801 #define BGE_MLC_SRAM_SIZE 0x001C0000
1802 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */
1803 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */
1804 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000
1805 #define BGE_MLC_AUTO_EEPROM 0x01000000
1807 #define BGE_SSRAMSIZE_256KB 0x00000000
1808 #define BGE_SSRAMSIZE_512KB 0x00040000
1809 #define BGE_SSRAMSIZE_1MB 0x00080000
1810 #define BGE_SSRAMSIZE_2MB 0x000C0000
1811 #define BGE_SSRAMSIZE_4MB 0x00100000
1812 #define BGE_SSRAMSIZE_8MB 0x00140000
1813 #define BGE_SSRAMSIZE_16M 0x00180000
1815 /* EEPROM address register */
1816 #define BGE_EEADDR_ADDRESS 0x0000FFFC
1817 #define BGE_EEADDR_HALFCLK 0x01FF0000
1818 #define BGE_EEADDR_START 0x02000000
1819 #define BGE_EEADDR_DEVID 0x1C000000
1820 #define BGE_EEADDR_RESET 0x20000000
1821 #define BGE_EEADDR_DONE 0x40000000
1822 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */
1824 #define BGE_EEDEVID(x) ((x & 7) << 26)
1825 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16)
1826 #define BGE_HALFCLK_384SCL 0x60
1827 #define BGE_EE_READCMD \
1828 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
1829 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE)
1830 #define BGE_EE_WRCMD \
1831 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
1832 BGE_EEADDR_START|BGE_EEADDR_DONE)
1834 /* EEPROM Control register */
1835 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001
1836 #define BGE_EECTL_CLKOUT 0x00000002
1837 #define BGE_EECTL_CLKIN 0x00000004
1838 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008
1839 #define BGE_EECTL_DATAOUT 0x00000010
1840 #define BGE_EECTL_DATAIN 0x00000020
1842 /* MDI (MII/GMII) access register */
1843 #define BGE_MDI_DATA 0x00000001
1844 #define BGE_MDI_DIR 0x00000002
1845 #define BGE_MDI_SEL 0x00000004
1846 #define BGE_MDI_CLK 0x00000008
1848 #define BGE_MEMWIN_START 0x00008000
1849 #define BGE_MEMWIN_END 0x0000FFFF
1852 #define BGE_MEMWIN_READ(sc, x, val) \
1854 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
1855 (0xFFFF0000 & x), 4); \
1856 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \
1859 #define BGE_MEMWIN_WRITE(sc, x, val) \
1861 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
1862 (0xFFFF0000 & x), 4); \
1863 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \
1867 * This magic number is written to the firmware mailbox at 0xb50
1868 * before a software reset is issued. After the internal firmware
1869 * has completed its initialization it will write the opposite of
1870 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the
1871 * driver to synchronize with the firmware.
1873 #define BGE_MAGIC_NUMBER 0x4B657654
1876 uint32_t bge_addr_hi;
1877 uint32_t bge_addr_lo;
1880 #define BGE_HOSTADDR(x, y) \
1882 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \
1883 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \
1886 #define BGE_ADDR_LO(y) \
1887 ((uint64_t) (y) & 0xFFFFFFFF)
1888 #define BGE_ADDR_HI(y) \
1889 ((uint64_t) (y) >> 32)
1891 /* Ring control block structure */
1893 bge_hostaddr bge_hostaddr;
1894 uint32_t bge_maxlen_flags;
1895 uint32_t bge_nicaddr;
1898 #define RCB_WRITE_4(sc, rcb, offset, val) \
1899 bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val)
1900 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags))
1902 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001
1903 #define BGE_RCB_FLAG_RING_DISABLED 0x0002
1906 bge_hostaddr bge_addr;
1907 #if BYTE_ORDER == LITTLE_ENDIAN
1910 uint16_t bge_vlan_tag;
1916 uint16_t bge_vlan_tag;
1920 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001
1921 #define BGE_TXBDFLAG_IP_CSUM 0x0002
1922 #define BGE_TXBDFLAG_END 0x0004
1923 #define BGE_TXBDFLAG_IP_FRAG 0x0008
1924 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010
1925 #define BGE_TXBDFLAG_VLAN_TAG 0x0040
1926 #define BGE_TXBDFLAG_COAL_NOW 0x0080
1927 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100
1928 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200
1929 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000
1930 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000
1931 #define BGE_TXBDFLAG_NO_CRC 0x8000
1933 #define BGE_NIC_TXRING_ADDR(ringno, size) \
1934 BGE_SEND_RING_1_TO_4 + \
1935 ((ringno * sizeof(struct bge_tx_bd) * size) / 4)
1938 bge_hostaddr bge_addr;
1939 #if BYTE_ORDER == LITTLE_ENDIAN
1944 uint16_t bge_tcp_udp_csum;
1945 uint16_t bge_ip_csum;
1946 uint16_t bge_vlan_tag;
1947 uint16_t bge_error_flag;
1953 uint16_t bge_ip_csum;
1954 uint16_t bge_tcp_udp_csum;
1955 uint16_t bge_error_flag;
1956 uint16_t bge_vlan_tag;
1959 uint32_t bge_opaque;
1962 struct bge_extrx_bd {
1963 bge_hostaddr bge_addr1;
1964 bge_hostaddr bge_addr2;
1965 bge_hostaddr bge_addr3;
1966 #if BYTE_ORDER == LITTLE_ENDIAN
1977 bge_hostaddr bge_addr0;
1978 #if BYTE_ORDER == LITTLE_ENDIAN
1983 uint16_t bge_tcp_udp_csum;
1984 uint16_t bge_ip_csum;
1985 uint16_t bge_vlan_tag;
1986 uint16_t bge_error_flag;
1992 uint16_t bge_ip_csum;
1993 uint16_t bge_tcp_udp_csum;
1994 uint16_t bge_error_flag;
1995 uint16_t bge_vlan_tag;
1998 uint32_t bge_opaque;
2001 #define BGE_RXBDFLAG_END 0x0004
2002 #define BGE_RXBDFLAG_JUMBO_RING 0x0020
2003 #define BGE_RXBDFLAG_VLAN_TAG 0x0040
2004 #define BGE_RXBDFLAG_ERROR 0x0400
2005 #define BGE_RXBDFLAG_MINI_RING 0x0800
2006 #define BGE_RXBDFLAG_IP_CSUM 0x1000
2007 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000
2008 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000
2010 #define BGE_RXERRFLAG_BAD_CRC 0x0001
2011 #define BGE_RXERRFLAG_COLL_DETECT 0x0002
2012 #define BGE_RXERRFLAG_LINK_LOST 0x0004
2013 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008
2014 #define BGE_RXERRFLAG_MAC_ABORT 0x0010
2015 #define BGE_RXERRFLAG_RUNT 0x0020
2016 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040
2017 #define BGE_RXERRFLAG_GIANT 0x0080
2019 struct bge_sts_idx {
2020 #if BYTE_ORDER == LITTLE_ENDIAN
2021 uint16_t bge_rx_prod_idx;
2022 uint16_t bge_tx_cons_idx;
2024 uint16_t bge_tx_cons_idx;
2025 uint16_t bge_rx_prod_idx;
2029 struct bge_status_block {
2030 uint32_t bge_status;
2032 #if BYTE_ORDER == LITTLE_ENDIAN
2033 uint16_t bge_rx_jumbo_cons_idx;
2034 uint16_t bge_rx_std_cons_idx;
2035 uint16_t bge_rx_mini_cons_idx;
2038 uint16_t bge_rx_std_cons_idx;
2039 uint16_t bge_rx_jumbo_cons_idx;
2041 uint16_t bge_rx_mini_cons_idx;
2043 struct bge_sts_idx bge_idx[16];
2046 #define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx
2047 #define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx
2049 #define BGE_STATFLAG_UPDATED 0x00000001
2050 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002
2051 #define BGE_STATFLAG_ERROR 0x00000004
2055 * Broadcom Vendor ID
2056 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID
2057 * even though they're now manufactured by Broadcom)
2059 #define BCOM_VENDORID 0x14E4
2060 #define BCOM_DEVICEID_BCM5700 0x1644
2061 #define BCOM_DEVICEID_BCM5701 0x1645
2062 #define BCOM_DEVICEID_BCM5702 0x1646
2063 #define BCOM_DEVICEID_BCM5702X 0x16A6
2064 #define BCOM_DEVICEID_BCM5702_ALT 0x16C6
2065 #define BCOM_DEVICEID_BCM5703 0x1647
2066 #define BCOM_DEVICEID_BCM5703X 0x16A7
2067 #define BCOM_DEVICEID_BCM5703_ALT 0x16C7
2068 #define BCOM_DEVICEID_BCM5704C 0x1648
2069 #define BCOM_DEVICEID_BCM5704S 0x16A8
2070 #define BCOM_DEVICEID_BCM5704S_ALT 0x1649
2071 #define BCOM_DEVICEID_BCM5705 0x1653
2072 #define BCOM_DEVICEID_BCM5705K 0x1654
2073 #define BCOM_DEVICEID_BCM5705F 0x166E
2074 #define BCOM_DEVICEID_BCM5705M 0x165D
2075 #define BCOM_DEVICEID_BCM5705M_ALT 0x165E
2076 #define BCOM_DEVICEID_BCM5714C 0x1668
2077 #define BCOM_DEVICEID_BCM5714S 0x1669
2078 #define BCOM_DEVICEID_BCM5715 0x1678
2079 #define BCOM_DEVICEID_BCM5715S 0x1679
2080 #define BCOM_DEVICEID_BCM5720 0x1658
2081 #define BCOM_DEVICEID_BCM5721 0x1659
2082 #define BCOM_DEVICEID_BCM5722 0x165A
2083 #define BCOM_DEVICEID_BCM5750 0x1676
2084 #define BCOM_DEVICEID_BCM5750M 0x167C
2085 #define BCOM_DEVICEID_BCM5751 0x1677
2086 #define BCOM_DEVICEID_BCM5751F 0x167E
2087 #define BCOM_DEVICEID_BCM5751M 0x167D
2088 #define BCOM_DEVICEID_BCM5752 0x1600
2089 #define BCOM_DEVICEID_BCM5752M 0x1601
2090 #define BCOM_DEVICEID_BCM5753 0x16F7
2091 #define BCOM_DEVICEID_BCM5753F 0x16FE
2092 #define BCOM_DEVICEID_BCM5753M 0x16FD
2093 #define BCOM_DEVICEID_BCM5754 0x167A
2094 #define BCOM_DEVICEID_BCM5754M 0x1672
2095 #define BCOM_DEVICEID_BCM5755 0x167B
2096 #define BCOM_DEVICEID_BCM5755M 0x1673
2097 #define BCOM_DEVICEID_BCM5780 0x166A
2098 #define BCOM_DEVICEID_BCM5780S 0x166B
2099 #define BCOM_DEVICEID_BCM5781 0x16DD
2100 #define BCOM_DEVICEID_BCM5782 0x1696
2101 #define BCOM_DEVICEID_BCM5786 0x169A
2102 #define BCOM_DEVICEID_BCM5787 0x169B
2103 #define BCOM_DEVICEID_BCM5787M 0x1693
2104 #define BCOM_DEVICEID_BCM5788 0x169C
2105 #define BCOM_DEVICEID_BCM5789 0x169D
2106 #define BCOM_DEVICEID_BCM5901 0x170D
2107 #define BCOM_DEVICEID_BCM5901A2 0x170E
2108 #define BCOM_DEVICEID_BCM5903M 0x16FF
2109 #define BCOM_DEVICEID_BCM5906 0x1712
2110 #define BCOM_DEVICEID_BCM5906M 0x1713
2113 * Alteon AceNIC PCI vendor/device ID.
2115 #define ALTEON_VENDORID 0x12AE
2116 #define ALTEON_DEVICEID_ACENIC 0x0001
2117 #define ALTEON_DEVICEID_ACENIC_COPPER 0x0002
2118 #define ALTEON_DEVICEID_BCM5700 0x0003
2119 #define ALTEON_DEVICEID_BCM5701 0x0004
2122 * 3Com 3c996 PCI vendor/device ID.
2124 #define TC_VENDORID 0x10B7
2125 #define TC_DEVICEID_3C996 0x0003
2128 * SysKonnect PCI vendor ID
2130 #define SK_VENDORID 0x1148
2131 #define SK_DEVICEID_ALTIMA 0x4400
2132 #define SK_SUBSYSID_9D21 0x4421
2133 #define SK_SUBSYSID_9D41 0x4441
2136 * Altima PCI vendor/device ID.
2138 #define ALTIMA_VENDORID 0x173b
2139 #define ALTIMA_DEVICE_AC1000 0x03e8
2140 #define ALTIMA_DEVICE_AC1002 0x03e9
2141 #define ALTIMA_DEVICE_AC9100 0x03ea
2144 * Dell PCI vendor ID
2147 #define DELL_VENDORID 0x1028
2150 * Apple PCI vendor ID.
2152 #define APPLE_VENDORID 0x106b
2153 #define APPLE_DEVICE_BCM5701 0x1645
2158 #define SUN_VENDORID 0x108e
2161 * Offset of MAC address inside EEPROM.
2163 #define BGE_EE_MAC_OFFSET 0x7C
2164 #define BGE_EE_MAC_OFFSET_5906 0x10
2165 #define BGE_EE_HWCFG_OFFSET 0xC8
2167 #define BGE_HWCFG_VOLTAGE 0x00000003
2168 #define BGE_HWCFG_PHYLED_MODE 0x0000000C
2169 #define BGE_HWCFG_MEDIA 0x00000030
2170 #define BGE_HWCFG_ASF 0x00000080
2172 #define BGE_VOLTAGE_1POINT3 0x00000000
2173 #define BGE_VOLTAGE_1POINT8 0x00000001
2175 #define BGE_PHYLEDMODE_UNSPEC 0x00000000
2176 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004
2177 #define BGE_PHYLEDMODE_SINGLELED 0x00000008
2179 #define BGE_MEDIA_UNSPEC 0x00000000
2180 #define BGE_MEDIA_COPPER 0x00000010
2181 #define BGE_MEDIA_FIBER 0x00000020
2183 #define BGE_TICKS_PER_SEC 1000000
2186 * Ring size constants.
2188 #define BGE_EVENT_RING_CNT 256
2189 #define BGE_CMD_RING_CNT 64
2190 #define BGE_STD_RX_RING_CNT 512
2191 #define BGE_JUMBO_RX_RING_CNT 256
2192 #define BGE_MINI_RX_RING_CNT 1024
2193 #define BGE_RETURN_RING_CNT 1024
2195 /* 5705 has smaller return ring size */
2197 #define BGE_RETURN_RING_CNT_5705 512
2200 * Possible TX ring sizes.
2202 #define BGE_TX_RING_CNT_128 128
2203 #define BGE_TX_RING_BASE_128 0x3800
2205 #define BGE_TX_RING_CNT_256 256
2206 #define BGE_TX_RING_BASE_256 0x3000
2208 #define BGE_TX_RING_CNT_512 512
2209 #define BGE_TX_RING_BASE_512 0x2000
2211 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512
2212 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512
2215 * Tigon III statistics counters.
2217 /* Statistics maintained MAC Receive block. */
2218 struct bge_rx_mac_stats {
2219 bge_hostaddr ifHCInOctets;
2220 bge_hostaddr Reserved1;
2221 bge_hostaddr etherStatsFragments;
2222 bge_hostaddr ifHCInUcastPkts;
2223 bge_hostaddr ifHCInMulticastPkts;
2224 bge_hostaddr ifHCInBroadcastPkts;
2225 bge_hostaddr dot3StatsFCSErrors;
2226 bge_hostaddr dot3StatsAlignmentErrors;
2227 bge_hostaddr xonPauseFramesReceived;
2228 bge_hostaddr xoffPauseFramesReceived;
2229 bge_hostaddr macControlFramesReceived;
2230 bge_hostaddr xoffStateEntered;
2231 bge_hostaddr dot3StatsFramesTooLong;
2232 bge_hostaddr etherStatsJabbers;
2233 bge_hostaddr etherStatsUndersizePkts;
2234 bge_hostaddr inRangeLengthError;
2235 bge_hostaddr outRangeLengthError;
2236 bge_hostaddr etherStatsPkts64Octets;
2237 bge_hostaddr etherStatsPkts65Octetsto127Octets;
2238 bge_hostaddr etherStatsPkts128Octetsto255Octets;
2239 bge_hostaddr etherStatsPkts256Octetsto511Octets;
2240 bge_hostaddr etherStatsPkts512Octetsto1023Octets;
2241 bge_hostaddr etherStatsPkts1024Octetsto1522Octets;
2242 bge_hostaddr etherStatsPkts1523Octetsto2047Octets;
2243 bge_hostaddr etherStatsPkts2048Octetsto4095Octets;
2244 bge_hostaddr etherStatsPkts4096Octetsto8191Octets;
2245 bge_hostaddr etherStatsPkts8192Octetsto9022Octets;
2249 /* Statistics maintained MAC Transmit block. */
2250 struct bge_tx_mac_stats {
2251 bge_hostaddr ifHCOutOctets;
2252 bge_hostaddr Reserved2;
2253 bge_hostaddr etherStatsCollisions;
2254 bge_hostaddr outXonSent;
2255 bge_hostaddr outXoffSent;
2256 bge_hostaddr flowControlDone;
2257 bge_hostaddr dot3StatsInternalMacTransmitErrors;
2258 bge_hostaddr dot3StatsSingleCollisionFrames;
2259 bge_hostaddr dot3StatsMultipleCollisionFrames;
2260 bge_hostaddr dot3StatsDeferredTransmissions;
2261 bge_hostaddr Reserved3;
2262 bge_hostaddr dot3StatsExcessiveCollisions;
2263 bge_hostaddr dot3StatsLateCollisions;
2264 bge_hostaddr dot3Collided2Times;
2265 bge_hostaddr dot3Collided3Times;
2266 bge_hostaddr dot3Collided4Times;
2267 bge_hostaddr dot3Collided5Times;
2268 bge_hostaddr dot3Collided6Times;
2269 bge_hostaddr dot3Collided7Times;
2270 bge_hostaddr dot3Collided8Times;
2271 bge_hostaddr dot3Collided9Times;
2272 bge_hostaddr dot3Collided10Times;
2273 bge_hostaddr dot3Collided11Times;
2274 bge_hostaddr dot3Collided12Times;
2275 bge_hostaddr dot3Collided13Times;
2276 bge_hostaddr dot3Collided14Times;
2277 bge_hostaddr dot3Collided15Times;
2278 bge_hostaddr ifHCOutUcastPkts;
2279 bge_hostaddr ifHCOutMulticastPkts;
2280 bge_hostaddr ifHCOutBroadcastPkts;
2281 bge_hostaddr dot3StatsCarrierSenseErrors;
2282 bge_hostaddr ifOutDiscards;
2283 bge_hostaddr ifOutErrors;
2286 /* Stats counters access through registers */
2287 struct bge_mac_stats_regs {
2288 uint32_t ifHCOutOctets;
2290 uint32_t etherStatsCollisions;
2291 uint32_t outXonSent;
2292 uint32_t outXoffSent;
2294 uint32_t dot3StatsInternalMacTransmitErrors;
2295 uint32_t dot3StatsSingleCollisionFrames;
2296 uint32_t dot3StatsMultipleCollisionFrames;
2297 uint32_t dot3StatsDeferredTransmissions;
2299 uint32_t dot3StatsExcessiveCollisions;
2300 uint32_t dot3StatsLateCollisions;
2301 uint32_t Reserved3[14];
2302 uint32_t ifHCOutUcastPkts;
2303 uint32_t ifHCOutMulticastPkts;
2304 uint32_t ifHCOutBroadcastPkts;
2305 uint32_t Reserved4[2];
2306 uint32_t ifHCInOctets;
2308 uint32_t etherStatsFragments;
2309 uint32_t ifHCInUcastPkts;
2310 uint32_t ifHCInMulticastPkts;
2311 uint32_t ifHCInBroadcastPkts;
2312 uint32_t dot3StatsFCSErrors;
2313 uint32_t dot3StatsAlignmentErrors;
2314 uint32_t xonPauseFramesReceived;
2315 uint32_t xoffPauseFramesReceived;
2316 uint32_t macControlFramesReceived;
2317 uint32_t xoffStateEntered;
2318 uint32_t dot3StatsFramesTooLong;
2319 uint32_t etherStatsJabbers;
2320 uint32_t etherStatsUndersizePkts;
2324 uint8_t Reserved0[256];
2326 /* Statistics maintained by Receive MAC. */
2327 struct bge_rx_mac_stats rxstats;
2329 bge_hostaddr Unused1[37];
2331 /* Statistics maintained by Transmit MAC. */
2332 struct bge_tx_mac_stats txstats;
2334 bge_hostaddr Unused2[31];
2336 /* Statistics maintained by Receive List Placement. */
2337 bge_hostaddr COSIfHCInPkts[16];
2338 bge_hostaddr COSFramesDroppedDueToFilters;
2339 bge_hostaddr nicDmaWriteQueueFull;
2340 bge_hostaddr nicDmaWriteHighPriQueueFull;
2341 bge_hostaddr nicNoMoreRxBDs;
2342 bge_hostaddr ifInDiscards;
2343 bge_hostaddr ifInErrors;
2344 bge_hostaddr nicRecvThresholdHit;
2346 bge_hostaddr Unused3[9];
2348 /* Statistics maintained by Send Data Initiator. */
2349 bge_hostaddr COSIfHCOutPkts[16];
2350 bge_hostaddr nicDmaReadQueueFull;
2351 bge_hostaddr nicDmaReadHighPriQueueFull;
2352 bge_hostaddr nicSendDataCompQueueFull;
2354 /* Statistics maintained by Host Coalescing. */
2355 bge_hostaddr nicRingSetSendProdIndex;
2356 bge_hostaddr nicRingStatusUpdate;
2357 bge_hostaddr nicInterrupts;
2358 bge_hostaddr nicAvoidedInterrupts;
2359 bge_hostaddr nicSendThresholdHit;
2361 uint8_t Reserved4[320];
2365 * Tigon general information block. This resides in host memory
2366 * and contains the status counters, ring control blocks and
2367 * producer pointers.
2371 struct bge_stats bge_stats;
2372 struct bge_rcb bge_tx_rcb[16];
2373 struct bge_rcb bge_std_rx_rcb;
2374 struct bge_rcb bge_jumbo_rx_rcb;
2375 struct bge_rcb bge_mini_rx_rcb;
2376 struct bge_rcb bge_return_rcb;
2379 #define BGE_FRAMELEN 1518
2380 #define BGE_MAX_FRAMELEN 1536
2381 #define BGE_JUMBO_FRAMELEN 9018
2382 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
2383 #define BGE_MIN_FRAMELEN 60
2386 * Other utility macros.
2388 #define BGE_INC(x, y) (x) = (x + 1) % y
2391 * Register access macros. The Tigon always uses memory mapped register
2392 * accesses and all registers must be accessed with 32 bit operations.
2395 #define CSR_WRITE_4(sc, reg, val) \
2396 bus_write_4(sc->bge_res, reg, val)
2398 #define CSR_READ_4(sc, reg) \
2399 bus_read_4(sc->bge_res, reg)
2401 #define BGE_SETBIT(sc, reg, x) \
2402 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
2403 #define BGE_CLRBIT(sc, reg, x) \
2404 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
2406 #define PCI_SETBIT(dev, reg, x, s) \
2407 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
2408 #define PCI_CLRBIT(dev, reg, x, s) \
2409 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
2412 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
2413 * values are tuneable. They control the actual amount of buffers
2414 * allocated for the standard, mini and jumbo receive rings.
2417 #define BGE_SSLOTS 256
2418 #define BGE_MSLOTS 256
2419 #define BGE_JSLOTS 384
2421 #define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN)
2422 #define BGE_JLEN (BGE_JRAWLEN + (sizeof(uint64_t) - \
2423 (BGE_JRAWLEN % sizeof(uint64_t))))
2424 #define BGE_JPAGESZ PAGE_SIZE
2425 #define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ)
2426 #define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID)
2428 #define BGE_NSEG_JUMBO 4
2429 #define BGE_NSEG_NEW 32
2432 * Ring structures. Most of these reside in host memory and we tell
2433 * the NIC where they are via the ring control blocks. The exceptions
2434 * are the tx and command rings, which live in NIC memory and which
2435 * we access via the shared memory window.
2438 struct bge_ring_data {
2439 struct bge_rx_bd *bge_rx_std_ring;
2440 bus_addr_t bge_rx_std_ring_paddr;
2441 struct bge_extrx_bd *bge_rx_jumbo_ring;
2442 bus_addr_t bge_rx_jumbo_ring_paddr;
2443 struct bge_rx_bd *bge_rx_return_ring;
2444 bus_addr_t bge_rx_return_ring_paddr;
2445 struct bge_tx_bd *bge_tx_ring;
2446 bus_addr_t bge_tx_ring_paddr;
2447 struct bge_status_block *bge_status_block;
2448 bus_addr_t bge_status_block_paddr;
2449 struct bge_stats *bge_stats;
2450 bus_addr_t bge_stats_paddr;
2451 struct bge_gib bge_info;
2454 #define BGE_STD_RX_RING_SZ \
2455 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT)
2456 #define BGE_JUMBO_RX_RING_SZ \
2457 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT)
2458 #define BGE_TX_RING_SZ \
2459 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT)
2460 #define BGE_RX_RTN_RING_SZ(x) \
2461 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt)
2463 #define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block)
2465 #define BGE_STATS_SZ sizeof (struct bge_stats)
2468 * Mbuf pointers. We need these to keep track of the virtual addresses
2469 * of our mbuf chains since we can only convert from physical to virtual,
2470 * not the other way around.
2472 struct bge_chain_data {
2473 bus_dma_tag_t bge_parent_tag;
2474 bus_dma_tag_t bge_rx_std_ring_tag;
2475 bus_dma_tag_t bge_rx_jumbo_ring_tag;
2476 bus_dma_tag_t bge_rx_return_ring_tag;
2477 bus_dma_tag_t bge_tx_ring_tag;
2478 bus_dma_tag_t bge_status_tag;
2479 bus_dma_tag_t bge_stats_tag;
2480 bus_dma_tag_t bge_mtag; /* mbuf mapping tag */
2481 bus_dma_tag_t bge_mtag_jumbo; /* mbuf mapping tag */
2482 bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT];
2483 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT];
2484 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT];
2485 bus_dmamap_t bge_rx_std_ring_map;
2486 bus_dmamap_t bge_rx_jumbo_ring_map;
2487 bus_dmamap_t bge_tx_ring_map;
2488 bus_dmamap_t bge_rx_return_ring_map;
2489 bus_dmamap_t bge_status_map;
2490 bus_dmamap_t bge_stats_map;
2491 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT];
2492 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT];
2493 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
2496 struct bge_dmamap_arg {
2497 struct bge_softc *sc;
2498 bus_addr_t bge_busaddr;
2502 struct bge_tx_bd *bge_ring;
2505 #define BGE_HWREV_TIGON 0x01
2506 #define BGE_HWREV_TIGON_II 0x02
2507 #define BGE_TIMEOUT 100000
2508 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */
2510 struct bge_bcom_hack {
2515 #define ASF_ENABLE 1
2516 #define ASF_NEW_HANDSHAKE 2
2517 #define ASF_STACKUP 4
2520 struct ifnet *bge_ifp; /* interface info */
2523 device_t bge_miibus;
2525 struct resource *bge_irq;
2526 struct resource *bge_res;
2527 struct ifmedia bge_ifmedia; /* TBI media info */
2529 #define BGE_FLAG_TBI 0x00000001
2530 #define BGE_FLAG_JUMBO 0x00000002
2531 #define BGE_FLAG_WIRESPEED 0x00000004
2532 #define BGE_FLAG_EADDR 0x00000008
2533 #define BGE_FLAG_MSI 0x00000100
2534 #define BGE_FLAG_PCIX 0x00000200
2535 #define BGE_FLAG_PCIE 0x00000400
2536 #define BGE_FLAG_5700_FAMILY 0x00001000
2537 #define BGE_FLAG_5705_PLUS 0x00002000
2538 #define BGE_FLAG_5714_FAMILY 0x00004000
2539 #define BGE_FLAG_575X_PLUS 0x00008000
2540 #define BGE_FLAG_RX_ALIGNBUG 0x00100000
2541 #define BGE_FLAG_NO_3LED 0x00200000
2542 #define BGE_FLAG_ADC_BUG 0x00400000
2543 #define BGE_FLAG_5704_A0_BUG 0x00800000
2544 #define BGE_FLAG_JITTER_BUG 0x01000000
2545 #define BGE_FLAG_BER_BUG 0x02000000
2546 #define BGE_FLAG_ADJUST_TRIM 0x04000000
2547 #define BGE_FLAG_CRC_BUG 0x08000000
2548 #define BGE_FLAG_5788 0x20000000
2549 uint32_t bge_chipid;
2550 uint8_t bge_asicrev;
2551 uint8_t bge_chiprev;
2552 uint8_t bge_asf_mode;
2553 uint8_t bge_asf_count;
2554 struct bge_ring_data bge_ldata; /* rings */
2555 struct bge_chain_data bge_cdata; /* mbufs */
2556 uint16_t bge_tx_saved_considx;
2557 uint16_t bge_rx_saved_considx;
2558 uint16_t bge_ev_saved_considx;
2559 uint16_t bge_return_ring_cnt;
2560 uint16_t bge_std; /* current std ring head */
2561 uint16_t bge_jumbo; /* current jumo ring head */
2562 uint32_t bge_stat_ticks;
2563 uint32_t bge_rx_coal_ticks;
2564 uint32_t bge_tx_coal_ticks;
2565 uint32_t bge_tx_prodidx;
2566 uint32_t bge_rx_max_coal_bds;
2567 uint32_t bge_tx_max_coal_bds;
2568 uint32_t bge_tx_buf_ratio;
2571 int bge_link; /* link state */
2572 int bge_link_evt; /* pending link event */
2574 struct callout bge_stat_ch;
2575 uint32_t bge_rx_discards;
2576 uint32_t bge_tx_discards;
2577 uint32_t bge_tx_collisions;
2578 #ifdef DEVICE_POLLING
2580 #endif /* DEVICE_POLLING */
2583 #define BGE_LOCK_INIT(_sc, _name) \
2584 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
2585 #define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx)
2586 #define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED)
2587 #define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx)
2588 #define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx)