2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
37 * BCM570x memory map. The internal memory layout varies somewhat
38 * depending on whether or not we have external SSRAM attached.
39 * The BCM5700 can have up to 16MB of external memory. The BCM5701
40 * is apparently not designed to use external SSRAM. The mappings
41 * up to the first 4 send rings are the same for both internal and
42 * external memory configurations. Note that mini RX ring space is
43 * only available with external SSRAM configurations, which means
44 * the mini RX ring is not supported on the BCM5701.
46 * The NIC's memory can be accessed by the host in one of 3 ways:
48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA
49 * registers in PCI config space can be used to read any 32-bit
50 * address within the NIC's memory.
52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config
53 * space can be used in conjunction with the memory window in the
54 * device register space at offset 0x8000 to read any 32K chunk
57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is
58 * set, the device I/O mapping consumes 32MB of host address space,
59 * allowing all of the registers and internal NIC memory to be
60 * accessed directly. NIC memory addresses are offset by 0x01000000.
61 * Flat mode consumes so much host address space that it is not
64 #define BGE_PAGE_ZERO 0x00000000
65 #define BGE_PAGE_ZERO_END 0x000000FF
66 #define BGE_SEND_RING_RCB 0x00000100
67 #define BGE_SEND_RING_RCB_END 0x000001FF
68 #define BGE_RX_RETURN_RING_RCB 0x00000200
69 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF
70 #define BGE_STATS_BLOCK 0x00000300
71 #define BGE_STATS_BLOCK_END 0x00000AFF
72 #define BGE_STATUS_BLOCK 0x00000B00
73 #define BGE_STATUS_BLOCK_END 0x00000B4F
74 #define BGE_SOFTWARE_GENCOMM 0x00000B50
75 #define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54
76 #define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58
77 #define BGE_SOFTWARE_GENCOMM_FW 0x00000B78
78 #define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C
79 #define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80
80 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF
81 #define BGE_UNMAPPED 0x00001000
82 #define BGE_UNMAPPED_END 0x00001FFF
83 #define BGE_DMA_DESCRIPTORS 0x00002000
84 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF
85 #define BGE_SEND_RING_1_TO_4 0x00004000
86 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF
88 /* Firmware interface */
89 #define BGE_FW_DRV_ALIVE 0x00000001
90 #define BGE_FW_PAUSE 0x00000002
92 /* Mappings for internal memory configuration */
93 #define BGE_STD_RX_RINGS 0x00006000
94 #define BGE_STD_RX_RINGS_END 0x00006FFF
95 #define BGE_JUMBO_RX_RINGS 0x00007000
96 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF
97 #define BGE_BUFFPOOL_1 0x00008000
98 #define BGE_BUFFPOOL_1_END 0x0000FFFF
99 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */
100 #define BGE_BUFFPOOL_2_END 0x00017FFF
101 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */
102 #define BGE_BUFFPOOL_3_END 0x0001FFFF
104 /* Mappings for external SSRAM configurations */
105 #define BGE_SEND_RING_5_TO_6 0x00006000
106 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF
107 #define BGE_SEND_RING_7_TO_8 0x00007000
108 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF
109 #define BGE_SEND_RING_9_TO_16 0x00008000
110 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF
111 #define BGE_EXT_STD_RX_RINGS 0x0000C000
112 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF
113 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000
114 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF
115 #define BGE_MINI_RX_RINGS 0x0000E000
116 #define BGE_MINI_RX_RINGS_END 0x0000FFFF
117 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */
118 #define BGE_AVAIL_REGION1_END 0x00017FFF
119 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */
120 #define BGE_AVAIL_REGION2_END 0x0001FFFF
121 #define BGE_EXT_SSRAM 0x00020000
122 #define BGE_EXT_SSRAM_END 0x000FFFFF
126 * BCM570x register offsets. These are memory mapped registers
127 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
128 * Each register must be accessed using 32 bit operations.
130 * All registers are accessed through a 32K shared memory block.
131 * The first group of registers are actually copies of the PCI
132 * configuration space registers.
136 * PCI registers defined in the PCI 2.2 spec.
138 #define BGE_PCI_VID 0x00
139 #define BGE_PCI_DID 0x02
140 #define BGE_PCI_CMD 0x04
141 #define BGE_PCI_STS 0x06
142 #define BGE_PCI_REV 0x08
143 #define BGE_PCI_CLASS 0x09
144 #define BGE_PCI_CACHESZ 0x0C
145 #define BGE_PCI_LATTIMER 0x0D
146 #define BGE_PCI_HDRTYPE 0x0E
147 #define BGE_PCI_BIST 0x0F
148 #define BGE_PCI_BAR0 0x10
149 #define BGE_PCI_BAR1 0x14
150 #define BGE_PCI_SUBSYS 0x2C
151 #define BGE_PCI_SUBVID 0x2E
152 #define BGE_PCI_ROMBASE 0x30
153 #define BGE_PCI_CAPPTR 0x34
154 #define BGE_PCI_INTLINE 0x3C
155 #define BGE_PCI_INTPIN 0x3D
156 #define BGE_PCI_MINGNT 0x3E
157 #define BGE_PCI_MAXLAT 0x3F
158 #define BGE_PCI_PCIXCAP 0x40
159 #define BGE_PCI_NEXTPTR_PM 0x41
160 #define BGE_PCI_PCIX_CMD 0x42
161 #define BGE_PCI_PCIX_STS 0x44
162 #define BGE_PCI_PWRMGMT_CAPID 0x48
163 #define BGE_PCI_NEXTPTR_VPD 0x49
164 #define BGE_PCI_PWRMGMT_CAPS 0x4A
165 #define BGE_PCI_PWRMGMT_CMD 0x4C
166 #define BGE_PCI_PWRMGMT_STS 0x4D
167 #define BGE_PCI_PWRMGMT_DATA 0x4F
168 #define BGE_PCI_VPD_CAPID 0x50
169 #define BGE_PCI_NEXTPTR_MSI 0x51
170 #define BGE_PCI_VPD_ADDR 0x52
171 #define BGE_PCI_VPD_DATA 0x54
172 #define BGE_PCI_MSI_CAPID 0x58
173 #define BGE_PCI_NEXTPTR_NONE 0x59
174 #define BGE_PCI_MSI_CTL 0x5A
175 #define BGE_PCI_MSI_ADDR_HI 0x5C
176 #define BGE_PCI_MSI_ADDR_LO 0x60
177 #define BGE_PCI_MSI_DATA 0x64
180 #define BGE_PCIE_CAPID_REG 0xD0
181 #define BGE_PCIE_CAPID 0x10
184 * PCI registers specific to the BCM570x family.
186 #define BGE_PCI_MISC_CTL 0x68
187 #define BGE_PCI_DMA_RW_CTL 0x6C
188 #define BGE_PCI_PCISTATE 0x70
189 #define BGE_PCI_CLKCTL 0x74
190 #define BGE_PCI_REG_BASEADDR 0x78
191 #define BGE_PCI_MEMWIN_BASEADDR 0x7C
192 #define BGE_PCI_REG_DATA 0x80
193 #define BGE_PCI_MEMWIN_DATA 0x84
194 #define BGE_PCI_MODECTL 0x88
195 #define BGE_PCI_MISC_CFG 0x8C
196 #define BGE_PCI_MISC_LOCALCTL 0x90
197 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98
198 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C
199 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0
200 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4
201 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8
202 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC
203 #define BGE_PCI_ISR_MBX_HI 0xB0
204 #define BGE_PCI_ISR_MBX_LO 0xB4
206 /* PCI Misc. Host control register */
207 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001
208 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002
209 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004
210 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008
211 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010
212 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020
213 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040
214 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080
215 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000
217 #define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP)
218 #if BYTE_ORDER == LITTLE_ENDIAN
219 #define BGE_DMA_SWAP_OPTIONS \
220 BGE_MODECTL_WORDSWAP_NONFRAME| \
221 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA
223 #define BGE_DMA_SWAP_OPTIONS \
224 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \
225 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA
229 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \
230 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS)
232 #define BGE_CHIPID_TIGON_I 0x40000000
233 #define BGE_CHIPID_TIGON_II 0x60000000
234 #define BGE_CHIPID_BCM5700_A0 0x70000000
235 #define BGE_CHIPID_BCM5700_A1 0x70010000
236 #define BGE_CHIPID_BCM5700_B0 0x71000000
237 #define BGE_CHIPID_BCM5700_B1 0x71010000
238 #define BGE_CHIPID_BCM5700_B2 0x71020000
239 #define BGE_CHIPID_BCM5700_B3 0x71030000
240 #define BGE_CHIPID_BCM5700_ALTIMA 0x71040000
241 #define BGE_CHIPID_BCM5700_C0 0x72000000
242 #define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */
243 #define BGE_CHIPID_BCM5701_B0 0x01000000
244 #define BGE_CHIPID_BCM5701_B2 0x01020000
245 #define BGE_CHIPID_BCM5701_B5 0x01050000
246 #define BGE_CHIPID_BCM5703_A0 0x10000000
247 #define BGE_CHIPID_BCM5703_A1 0x10010000
248 #define BGE_CHIPID_BCM5703_A2 0x10020000
249 #define BGE_CHIPID_BCM5703_A3 0x10030000
250 #define BGE_CHIPID_BCM5703_B0 0x11000000
251 #define BGE_CHIPID_BCM5704_A0 0x20000000
252 #define BGE_CHIPID_BCM5704_A1 0x20010000
253 #define BGE_CHIPID_BCM5704_A2 0x20020000
254 #define BGE_CHIPID_BCM5704_A3 0x20030000
255 #define BGE_CHIPID_BCM5704_B0 0x21000000
256 #define BGE_CHIPID_BCM5705_A0 0x30000000
257 #define BGE_CHIPID_BCM5705_A1 0x30010000
258 #define BGE_CHIPID_BCM5705_A2 0x30020000
259 #define BGE_CHIPID_BCM5705_A3 0x30030000
260 #define BGE_CHIPID_BCM5750_A0 0x40000000
261 #define BGE_CHIPID_BCM5750_A1 0x40010000
262 #define BGE_CHIPID_BCM5750_A3 0x40030000
263 #define BGE_CHIPID_BCM5750_B0 0x41000000
264 #define BGE_CHIPID_BCM5750_B1 0x41010000
265 #define BGE_CHIPID_BCM5750_C0 0x42000000
266 #define BGE_CHIPID_BCM5750_C1 0x42010000
267 #define BGE_CHIPID_BCM5750_C2 0x42020000
268 #define BGE_CHIPID_BCM5714_A0 0x50000000
269 #define BGE_CHIPID_BCM5752_A0 0x60000000
270 #define BGE_CHIPID_BCM5752_A1 0x60010000
271 #define BGE_CHIPID_BCM5752_A2 0x60020000
272 #define BGE_CHIPID_BCM5714_B0 0x80000000
273 #define BGE_CHIPID_BCM5714_B3 0x80030000
274 #define BGE_CHIPID_BCM5715_A0 0x90000000
275 #define BGE_CHIPID_BCM5715_A1 0x90010000
276 #define BGE_CHIPID_BCM5715_A3 0x90030000
277 #define BGE_CHIPID_BCM5755_A0 0xa0000000
278 #define BGE_CHIPID_BCM5755_A1 0xa0010000
279 #define BGE_CHIPID_BCM5755_A2 0xa0020000
280 #define BGE_CHIPID_BCM5754_A0 0xb0000000
281 #define BGE_CHIPID_BCM5754_A1 0xb0010000
282 #define BGE_CHIPID_BCM5754_A2 0xb0020000
283 #define BGE_CHIPID_BCM5787_A0 0xb0000000
284 #define BGE_CHIPID_BCM5787_A1 0xb0010000
285 #define BGE_CHIPID_BCM5787_A2 0xb0020000
288 #define BGE_ASICREV(x) ((x) >> 28)
289 #define BGE_ASICREV_BCM5701 0x00
290 #define BGE_ASICREV_BCM5703 0x01
291 #define BGE_ASICREV_BCM5704 0x02
292 #define BGE_ASICREV_BCM5705 0x03
293 #define BGE_ASICREV_BCM5750 0x04
294 #define BGE_ASICREV_BCM5714_A0 0x05
295 #define BGE_ASICREV_BCM5752 0x06
296 #define BGE_ASICREV_BCM5700 0x07
297 #define BGE_ASICREV_BCM5780 0x08
298 #define BGE_ASICREV_BCM5714 0x09
299 #define BGE_ASICREV_BCM5755 0x0a
300 #define BGE_ASICREV_BCM5754 0x0b
301 #define BGE_ASICREV_BCM5787 0x0b
304 #define BGE_CHIPREV(x) ((x) >> 24)
305 #define BGE_CHIPREV_5700_AX 0x70
306 #define BGE_CHIPREV_5700_BX 0x71
307 #define BGE_CHIPREV_5700_CX 0x72
308 #define BGE_CHIPREV_5701_AX 0x00
309 #define BGE_CHIPREV_5703_AX 0x10
310 #define BGE_CHIPREV_5704_AX 0x20
311 #define BGE_CHIPREV_5704_BX 0x21
312 #define BGE_CHIPREV_5750_AX 0x40
313 #define BGE_CHIPREV_5750_BX 0x41
315 /* PCI DMA Read/Write Control register */
316 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF
317 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700
318 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800
319 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000
320 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000
321 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000
322 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000
323 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000
324 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000
325 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000
326 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000
327 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000
329 #define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16)
330 #define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19)
331 #define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24)
332 #define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28)
334 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000
335 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100
336 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200
337 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300
338 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400
339 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500
340 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600
341 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700
343 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000
344 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800
345 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000
346 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800
347 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000
348 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800
349 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000
350 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800
353 * PCI state register -- note, this register is read only
354 * unless the PCISTATE_WR bit of the PCI Misc. Host Control
357 #define BGE_PCISTATE_FORCE_RESET 0x00000001
358 #define BGE_PCISTATE_INTR_STATE 0x00000002
359 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */
360 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */
361 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */
362 #define BGE_PCISTATE_WANT_EXPROM 0x00000020
363 #define BGE_PCISTATE_EXPROM_RETRY 0x00000040
364 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100
365 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00
368 * PCI Clock Control register -- note, this register is read only
369 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control
372 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F
373 #define BGE_PCICLOCKCTL_M66EN 0x00000080
374 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200
375 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400
376 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800
377 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000
378 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000
379 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000
380 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000
381 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000
384 #ifndef PCIM_CMD_MWIEN
385 #define PCIM_CMD_MWIEN 0x0010
389 * High priority mailbox registers
390 * Each mailbox is 64-bits wide, though we only use the
391 * lower 32 bits. To write a 64-bit value, write the upper 32 bits
392 * first. The NIC will load the mailbox after the lower 32 bit word
395 #define BGE_MBX_IRQ0_HI 0x0200
396 #define BGE_MBX_IRQ0_LO 0x0204
397 #define BGE_MBX_IRQ1_HI 0x0208
398 #define BGE_MBX_IRQ1_LO 0x020C
399 #define BGE_MBX_IRQ2_HI 0x0210
400 #define BGE_MBX_IRQ2_LO 0x0214
401 #define BGE_MBX_IRQ3_HI 0x0218
402 #define BGE_MBX_IRQ3_LO 0x021C
403 #define BGE_MBX_GEN0_HI 0x0220
404 #define BGE_MBX_GEN0_LO 0x0224
405 #define BGE_MBX_GEN1_HI 0x0228
406 #define BGE_MBX_GEN1_LO 0x022C
407 #define BGE_MBX_GEN2_HI 0x0230
408 #define BGE_MBX_GEN2_LO 0x0234
409 #define BGE_MBX_GEN3_HI 0x0228
410 #define BGE_MBX_GEN3_LO 0x022C
411 #define BGE_MBX_GEN4_HI 0x0240
412 #define BGE_MBX_GEN4_LO 0x0244
413 #define BGE_MBX_GEN5_HI 0x0248
414 #define BGE_MBX_GEN5_LO 0x024C
415 #define BGE_MBX_GEN6_HI 0x0250
416 #define BGE_MBX_GEN6_LO 0x0254
417 #define BGE_MBX_GEN7_HI 0x0258
418 #define BGE_MBX_GEN7_LO 0x025C
419 #define BGE_MBX_RELOAD_STATS_HI 0x0260
420 #define BGE_MBX_RELOAD_STATS_LO 0x0264
421 #define BGE_MBX_RX_STD_PROD_HI 0x0268
422 #define BGE_MBX_RX_STD_PROD_LO 0x026C
423 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270
424 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274
425 #define BGE_MBX_RX_MINI_PROD_HI 0x0278
426 #define BGE_MBX_RX_MINI_PROD_LO 0x027C
427 #define BGE_MBX_RX_CONS0_HI 0x0280
428 #define BGE_MBX_RX_CONS0_LO 0x0284
429 #define BGE_MBX_RX_CONS1_HI 0x0288
430 #define BGE_MBX_RX_CONS1_LO 0x028C
431 #define BGE_MBX_RX_CONS2_HI 0x0290
432 #define BGE_MBX_RX_CONS2_LO 0x0294
433 #define BGE_MBX_RX_CONS3_HI 0x0298
434 #define BGE_MBX_RX_CONS3_LO 0x029C
435 #define BGE_MBX_RX_CONS4_HI 0x02A0
436 #define BGE_MBX_RX_CONS4_LO 0x02A4
437 #define BGE_MBX_RX_CONS5_HI 0x02A8
438 #define BGE_MBX_RX_CONS5_LO 0x02AC
439 #define BGE_MBX_RX_CONS6_HI 0x02B0
440 #define BGE_MBX_RX_CONS6_LO 0x02B4
441 #define BGE_MBX_RX_CONS7_HI 0x02B8
442 #define BGE_MBX_RX_CONS7_LO 0x02BC
443 #define BGE_MBX_RX_CONS8_HI 0x02C0
444 #define BGE_MBX_RX_CONS8_LO 0x02C4
445 #define BGE_MBX_RX_CONS9_HI 0x02C8
446 #define BGE_MBX_RX_CONS9_LO 0x02CC
447 #define BGE_MBX_RX_CONS10_HI 0x02D0
448 #define BGE_MBX_RX_CONS10_LO 0x02D4
449 #define BGE_MBX_RX_CONS11_HI 0x02D8
450 #define BGE_MBX_RX_CONS11_LO 0x02DC
451 #define BGE_MBX_RX_CONS12_HI 0x02E0
452 #define BGE_MBX_RX_CONS12_LO 0x02E4
453 #define BGE_MBX_RX_CONS13_HI 0x02E8
454 #define BGE_MBX_RX_CONS13_LO 0x02EC
455 #define BGE_MBX_RX_CONS14_HI 0x02F0
456 #define BGE_MBX_RX_CONS14_LO 0x02F4
457 #define BGE_MBX_RX_CONS15_HI 0x02F8
458 #define BGE_MBX_RX_CONS15_LO 0x02FC
459 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300
460 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304
461 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308
462 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C
463 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310
464 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314
465 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318
466 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C
467 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320
468 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324
469 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328
470 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C
471 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330
472 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334
473 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338
474 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C
475 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340
476 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344
477 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348
478 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C
479 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350
480 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354
481 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358
482 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C
483 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360
484 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364
485 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368
486 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C
487 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370
488 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374
489 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378
490 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C
491 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380
492 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384
493 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388
494 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C
495 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390
496 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394
497 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398
498 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C
499 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0
500 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4
501 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8
502 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC
503 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0
504 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4
505 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8
506 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC
507 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0
508 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4
509 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8
510 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC
511 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0
512 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4
513 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8
514 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC
515 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0
516 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4
517 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8
518 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC
519 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0
520 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4
521 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8
522 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC
524 #define BGE_TX_RINGS_MAX 4
525 #define BGE_TX_RINGS_EXTSSRAM_MAX 16
526 #define BGE_RX_RINGS_MAX 16
528 /* Ethernet MAC control registers */
529 #define BGE_MAC_MODE 0x0400
530 #define BGE_MAC_STS 0x0404
531 #define BGE_MAC_EVT_ENB 0x0408
532 #define BGE_MAC_LED_CTL 0x040C
533 #define BGE_MAC_ADDR1_LO 0x0410
534 #define BGE_MAC_ADDR1_HI 0x0414
535 #define BGE_MAC_ADDR2_LO 0x0418
536 #define BGE_MAC_ADDR2_HI 0x041C
537 #define BGE_MAC_ADDR3_LO 0x0420
538 #define BGE_MAC_ADDR3_HI 0x0424
539 #define BGE_MAC_ADDR4_LO 0x0428
540 #define BGE_MAC_ADDR4_HI 0x042C
541 #define BGE_WOL_PATPTR 0x0430
542 #define BGE_WOL_PATCFG 0x0434
543 #define BGE_TX_RANDOM_BACKOFF 0x0438
544 #define BGE_RX_MTU 0x043C
545 #define BGE_GBIT_PCS_TEST 0x0440
546 #define BGE_TX_TBI_AUTONEG 0x0444
547 #define BGE_RX_TBI_AUTONEG 0x0448
548 #define BGE_MI_COMM 0x044C
549 #define BGE_MI_STS 0x0450
550 #define BGE_MI_MODE 0x0454
551 #define BGE_AUTOPOLL_STS 0x0458
552 #define BGE_TX_MODE 0x045C
553 #define BGE_TX_STS 0x0460
554 #define BGE_TX_LENGTHS 0x0464
555 #define BGE_RX_MODE 0x0468
556 #define BGE_RX_STS 0x046C
557 #define BGE_MAR0 0x0470
558 #define BGE_MAR1 0x0474
559 #define BGE_MAR2 0x0478
560 #define BGE_MAR3 0x047C
561 #define BGE_RX_BD_RULES_CTL0 0x0480
562 #define BGE_RX_BD_RULES_MASKVAL0 0x0484
563 #define BGE_RX_BD_RULES_CTL1 0x0488
564 #define BGE_RX_BD_RULES_MASKVAL1 0x048C
565 #define BGE_RX_BD_RULES_CTL2 0x0490
566 #define BGE_RX_BD_RULES_MASKVAL2 0x0494
567 #define BGE_RX_BD_RULES_CTL3 0x0498
568 #define BGE_RX_BD_RULES_MASKVAL3 0x049C
569 #define BGE_RX_BD_RULES_CTL4 0x04A0
570 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4
571 #define BGE_RX_BD_RULES_CTL5 0x04A8
572 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC
573 #define BGE_RX_BD_RULES_CTL6 0x04B0
574 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4
575 #define BGE_RX_BD_RULES_CTL7 0x04B8
576 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC
577 #define BGE_RX_BD_RULES_CTL8 0x04C0
578 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4
579 #define BGE_RX_BD_RULES_CTL9 0x04C8
580 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC
581 #define BGE_RX_BD_RULES_CTL10 0x04D0
582 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4
583 #define BGE_RX_BD_RULES_CTL11 0x04D8
584 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC
585 #define BGE_RX_BD_RULES_CTL12 0x04E0
586 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4
587 #define BGE_RX_BD_RULES_CTL13 0x04E8
588 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC
589 #define BGE_RX_BD_RULES_CTL14 0x04F0
590 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4
591 #define BGE_RX_BD_RULES_CTL15 0x04F8
592 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC
593 #define BGE_RX_RULES_CFG 0x0500
594 #define BGE_SERDES_CFG 0x0590
595 #define BGE_SERDES_STS 0x0594
596 #define BGE_SGDIG_CFG 0x05B0
597 #define BGE_SGDIG_STS 0x05B4
598 #define BGE_MAC_STATS 0x0800
600 /* Ethernet MAC Mode register */
601 #define BGE_MACMODE_RESET 0x00000001
602 #define BGE_MACMODE_HALF_DUPLEX 0x00000002
603 #define BGE_MACMODE_PORTMODE 0x0000000C
604 #define BGE_MACMODE_LOOPBACK 0x00000010
605 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080
606 #define BGE_MACMODE_TX_BURST_ENB 0x00000100
607 #define BGE_MACMODE_MAX_DEFER 0x00000200
608 #define BGE_MACMODE_LINK_POLARITY 0x00000400
609 #define BGE_MACMODE_RX_STATS_ENB 0x00000800
610 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000
611 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000
612 #define BGE_MACMODE_TX_STATS_ENB 0x00004000
613 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000
614 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000
615 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000
616 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000
617 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000
618 #define BGE_MACMODE_MIP_ENB 0x00100000
619 #define BGE_MACMODE_TXDMA_ENB 0x00200000
620 #define BGE_MACMODE_RXDMA_ENB 0x00400000
621 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000
623 #define BGE_PORTMODE_NONE 0x00000000
624 #define BGE_PORTMODE_MII 0x00000004
625 #define BGE_PORTMODE_GMII 0x00000008
626 #define BGE_PORTMODE_TBI 0x0000000C
628 /* MAC Status register */
629 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001
630 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002
631 #define BGE_MACSTAT_RX_CFG 0x00000004
632 #define BGE_MACSTAT_CFG_CHANGED 0x00000008
633 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010
634 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400
635 #define BGE_MACSTAT_LINK_CHANGED 0x00001000
636 #define BGE_MACSTAT_MI_COMPLETE 0x00400000
637 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000
638 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000
639 #define BGE_MACSTAT_ODI_ERROR 0x02000000
640 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000
641 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000
643 /* MAC Event Enable Register */
644 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400
645 #define BGE_EVTENB_LINK_CHANGED 0x00001000
646 #define BGE_EVTENB_MI_COMPLETE 0x00400000
647 #define BGE_EVTENB_MI_INTERRUPT 0x00800000
648 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000
649 #define BGE_EVTENB_ODI_ERROR 0x02000000
650 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000
651 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000
653 /* LED Control Register */
654 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001
655 #define BGE_LEDCTL_1000MBPS_LED 0x00000002
656 #define BGE_LEDCTL_100MBPS_LED 0x00000004
657 #define BGE_LEDCTL_10MBPS_LED 0x00000008
658 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010
659 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020
660 #define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040
661 #define BGE_LEDCTL_1000MBPS_STS 0x00000080
662 #define BGE_LEDCTL_100MBPS_STS 0x00000100
663 #define BGE_LEDCTL_10MBPS_STS 0x00000200
664 #define BGE_LEDCTL_TRADLED_STS 0x00000400
665 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000
666 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000
668 /* TX backoff seed register */
669 #define BGE_TX_BACKOFF_SEED_MASK 0x3F
671 /* Autopoll status register */
672 #define BGE_AUTOPOLLSTS_ERROR 0x00000001
674 /* Transmit MAC mode register */
675 #define BGE_TXMODE_RESET 0x00000001
676 #define BGE_TXMODE_ENABLE 0x00000002
677 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010
678 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020
679 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040
681 /* Transmit MAC status register */
682 #define BGE_TXSTAT_RX_XOFFED 0x00000001
683 #define BGE_TXSTAT_SENT_XOFF 0x00000002
684 #define BGE_TXSTAT_SENT_XON 0x00000004
685 #define BGE_TXSTAT_LINK_UP 0x00000008
686 #define BGE_TXSTAT_ODI_UFLOW 0x00000010
687 #define BGE_TXSTAT_ODI_OFLOW 0x00000020
689 /* Transmit MAC lengths register */
690 #define BGE_TXLEN_SLOTTIME 0x000000FF
691 #define BGE_TXLEN_IPG 0x00000F00
692 #define BGE_TXLEN_CRS 0x00003000
694 /* Receive MAC mode register */
695 #define BGE_RXMODE_RESET 0x00000001
696 #define BGE_RXMODE_ENABLE 0x00000002
697 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004
698 #define BGE_RXMODE_RX_GIANTS 0x00000020
699 #define BGE_RXMODE_RX_RUNTS 0x00000040
700 #define BGE_RXMODE_8022_LENCHECK 0x00000080
701 #define BGE_RXMODE_RX_PROMISC 0x00000100
702 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200
703 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400
705 /* Receive MAC status register */
706 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001
707 #define BGE_RXSTAT_RCVD_XOFF 0x00000002
708 #define BGE_RXSTAT_RCVD_XON 0x00000004
710 /* Receive Rules Control register */
711 #define BGE_RXRULECTL_OFFSET 0x000000FF
712 #define BGE_RXRULECTL_CLASS 0x00001F00
713 #define BGE_RXRULECTL_HDRTYPE 0x0000E000
714 #define BGE_RXRULECTL_COMPARE_OP 0x00030000
715 #define BGE_RXRULECTL_MAP 0x01000000
716 #define BGE_RXRULECTL_DISCARD 0x02000000
717 #define BGE_RXRULECTL_MASK 0x04000000
718 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000
719 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000
720 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000
721 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000
723 /* Receive Rules Mask register */
724 #define BGE_RXRULEMASK_VALUE 0x0000FFFF
725 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000
727 /* SERDES configuration register */
728 #define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */
729 #define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */
730 #define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */
731 #define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */
732 #define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */
733 #define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */
734 #define BGE_SERDESCFG_TXMODE 0x00001000
735 #define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */
736 #define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */
737 #define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */
738 #define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */
739 #define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */
740 #define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */
741 #define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */
742 #define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */
743 #define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */
745 /* SERDES status register */
746 #define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */
747 #define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */
749 /* SGDIG config (not documented) */
750 #define BGE_SGDIGCFG_PAUSE_CAP 0x00000800
751 #define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000
752 #define BGE_SGDIGCFG_SEND 0x40000000
753 #define BGE_SGDIGCFG_AUTO 0x80000000
755 /* SGDIG status (not documented) */
756 #define BGE_SGDIGSTS_PAUSE_CAP 0x00080000
757 #define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000
758 #define BGE_SGDIGSTS_DONE 0x00000002
761 /* MI communication register */
762 #define BGE_MICOMM_DATA 0x0000FFFF
763 #define BGE_MICOMM_REG 0x001F0000
764 #define BGE_MICOMM_PHY 0x03E00000
765 #define BGE_MICOMM_CMD 0x0C000000
766 #define BGE_MICOMM_READFAIL 0x10000000
767 #define BGE_MICOMM_BUSY 0x20000000
769 #define BGE_MIREG(x) ((x & 0x1F) << 16)
770 #define BGE_MIPHY(x) ((x & 0x1F) << 21)
771 #define BGE_MICMD_WRITE 0x04000000
772 #define BGE_MICMD_READ 0x08000000
774 /* MI status register */
775 #define BGE_MISTS_LINK 0x00000001
776 #define BGE_MISTS_10MBPS 0x00000002
778 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002
779 #define BGE_MIMODE_AUTOPOLL 0x00000010
780 #define BGE_MIMODE_CLKCNT 0x001F0000
784 * Send data initiator control registers.
786 #define BGE_SDI_MODE 0x0C00
787 #define BGE_SDI_STATUS 0x0C04
788 #define BGE_SDI_STATS_CTL 0x0C08
789 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C
790 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10
791 #define BGE_LOCSTATS_COS0 0x0C80
792 #define BGE_LOCSTATS_COS1 0x0C84
793 #define BGE_LOCSTATS_COS2 0x0C88
794 #define BGE_LOCSTATS_COS3 0x0C8C
795 #define BGE_LOCSTATS_COS4 0x0C90
796 #define BGE_LOCSTATS_COS5 0x0C84
797 #define BGE_LOCSTATS_COS6 0x0C98
798 #define BGE_LOCSTATS_COS7 0x0C9C
799 #define BGE_LOCSTATS_COS8 0x0CA0
800 #define BGE_LOCSTATS_COS9 0x0CA4
801 #define BGE_LOCSTATS_COS10 0x0CA8
802 #define BGE_LOCSTATS_COS11 0x0CAC
803 #define BGE_LOCSTATS_COS12 0x0CB0
804 #define BGE_LOCSTATS_COS13 0x0CB4
805 #define BGE_LOCSTATS_COS14 0x0CB8
806 #define BGE_LOCSTATS_COS15 0x0CBC
807 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0
808 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4
809 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8
810 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC
811 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0
812 #define BGE_LOCSTATS_IRQS 0x0CD4
813 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8
814 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC
816 /* Send Data Initiator mode register */
817 #define BGE_SDIMODE_RESET 0x00000001
818 #define BGE_SDIMODE_ENABLE 0x00000002
819 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004
821 /* Send Data Initiator stats register */
822 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004
824 /* Send Data Initiator stats control register */
825 #define BGE_SDISTATSCTL_ENABLE 0x00000001
826 #define BGE_SDISTATSCTL_FASTER 0x00000002
827 #define BGE_SDISTATSCTL_CLEAR 0x00000004
828 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008
829 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010
832 * Send Data Completion Control registers
834 #define BGE_SDC_MODE 0x1000
835 #define BGE_SDC_STATUS 0x1004
837 /* Send Data completion mode register */
838 #define BGE_SDCMODE_RESET 0x00000001
839 #define BGE_SDCMODE_ENABLE 0x00000002
840 #define BGE_SDCMODE_ATTN 0x00000004
842 /* Send Data completion status register */
843 #define BGE_SDCSTAT_ATTN 0x00000004
846 * Send BD Ring Selector Control registers
848 #define BGE_SRS_MODE 0x1400
849 #define BGE_SRS_STATUS 0x1404
850 #define BGE_SRS_HWDIAG 0x1408
851 #define BGE_SRS_LOC_NIC_CONS0 0x1440
852 #define BGE_SRS_LOC_NIC_CONS1 0x1444
853 #define BGE_SRS_LOC_NIC_CONS2 0x1448
854 #define BGE_SRS_LOC_NIC_CONS3 0x144C
855 #define BGE_SRS_LOC_NIC_CONS4 0x1450
856 #define BGE_SRS_LOC_NIC_CONS5 0x1454
857 #define BGE_SRS_LOC_NIC_CONS6 0x1458
858 #define BGE_SRS_LOC_NIC_CONS7 0x145C
859 #define BGE_SRS_LOC_NIC_CONS8 0x1460
860 #define BGE_SRS_LOC_NIC_CONS9 0x1464
861 #define BGE_SRS_LOC_NIC_CONS10 0x1468
862 #define BGE_SRS_LOC_NIC_CONS11 0x146C
863 #define BGE_SRS_LOC_NIC_CONS12 0x1470
864 #define BGE_SRS_LOC_NIC_CONS13 0x1474
865 #define BGE_SRS_LOC_NIC_CONS14 0x1478
866 #define BGE_SRS_LOC_NIC_CONS15 0x147C
868 /* Send BD Ring Selector Mode register */
869 #define BGE_SRSMODE_RESET 0x00000001
870 #define BGE_SRSMODE_ENABLE 0x00000002
871 #define BGE_SRSMODE_ATTN 0x00000004
873 /* Send BD Ring Selector Status register */
874 #define BGE_SRSSTAT_ERROR 0x00000004
876 /* Send BD Ring Selector HW Diagnostics register */
877 #define BGE_SRSHWDIAG_STATE 0x0000000F
878 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0
879 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00
880 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000
883 * Send BD Initiator Selector Control registers
885 #define BGE_SBDI_MODE 0x1800
886 #define BGE_SBDI_STATUS 0x1804
887 #define BGE_SBDI_LOC_NIC_PROD0 0x1808
888 #define BGE_SBDI_LOC_NIC_PROD1 0x180C
889 #define BGE_SBDI_LOC_NIC_PROD2 0x1810
890 #define BGE_SBDI_LOC_NIC_PROD3 0x1814
891 #define BGE_SBDI_LOC_NIC_PROD4 0x1818
892 #define BGE_SBDI_LOC_NIC_PROD5 0x181C
893 #define BGE_SBDI_LOC_NIC_PROD6 0x1820
894 #define BGE_SBDI_LOC_NIC_PROD7 0x1824
895 #define BGE_SBDI_LOC_NIC_PROD8 0x1828
896 #define BGE_SBDI_LOC_NIC_PROD9 0x182C
897 #define BGE_SBDI_LOC_NIC_PROD10 0x1830
898 #define BGE_SBDI_LOC_NIC_PROD11 0x1834
899 #define BGE_SBDI_LOC_NIC_PROD12 0x1838
900 #define BGE_SBDI_LOC_NIC_PROD13 0x183C
901 #define BGE_SBDI_LOC_NIC_PROD14 0x1840
902 #define BGE_SBDI_LOC_NIC_PROD15 0x1844
904 /* Send BD Initiator Mode register */
905 #define BGE_SBDIMODE_RESET 0x00000001
906 #define BGE_SBDIMODE_ENABLE 0x00000002
907 #define BGE_SBDIMODE_ATTN 0x00000004
909 /* Send BD Initiator Status register */
910 #define BGE_SBDISTAT_ERROR 0x00000004
913 * Send BD Completion Control registers
915 #define BGE_SBDC_MODE 0x1C00
916 #define BGE_SBDC_STATUS 0x1C04
918 /* Send BD Completion Control Mode register */
919 #define BGE_SBDCMODE_RESET 0x00000001
920 #define BGE_SBDCMODE_ENABLE 0x00000002
921 #define BGE_SBDCMODE_ATTN 0x00000004
923 /* Send BD Completion Control Status register */
924 #define BGE_SBDCSTAT_ATTN 0x00000004
927 * Receive List Placement Control registers
929 #define BGE_RXLP_MODE 0x2000
930 #define BGE_RXLP_STATUS 0x2004
931 #define BGE_RXLP_SEL_LIST_LOCK 0x2008
932 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C
933 #define BGE_RXLP_CFG 0x2010
934 #define BGE_RXLP_STATS_CTL 0x2014
935 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018
936 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C
937 #define BGE_RXLP_HEAD0 0x2100
938 #define BGE_RXLP_TAIL0 0x2104
939 #define BGE_RXLP_COUNT0 0x2108
940 #define BGE_RXLP_HEAD1 0x2110
941 #define BGE_RXLP_TAIL1 0x2114
942 #define BGE_RXLP_COUNT1 0x2118
943 #define BGE_RXLP_HEAD2 0x2120
944 #define BGE_RXLP_TAIL2 0x2124
945 #define BGE_RXLP_COUNT2 0x2128
946 #define BGE_RXLP_HEAD3 0x2130
947 #define BGE_RXLP_TAIL3 0x2134
948 #define BGE_RXLP_COUNT3 0x2138
949 #define BGE_RXLP_HEAD4 0x2140
950 #define BGE_RXLP_TAIL4 0x2144
951 #define BGE_RXLP_COUNT4 0x2148
952 #define BGE_RXLP_HEAD5 0x2150
953 #define BGE_RXLP_TAIL5 0x2154
954 #define BGE_RXLP_COUNT5 0x2158
955 #define BGE_RXLP_HEAD6 0x2160
956 #define BGE_RXLP_TAIL6 0x2164
957 #define BGE_RXLP_COUNT6 0x2168
958 #define BGE_RXLP_HEAD7 0x2170
959 #define BGE_RXLP_TAIL7 0x2174
960 #define BGE_RXLP_COUNT7 0x2178
961 #define BGE_RXLP_HEAD8 0x2180
962 #define BGE_RXLP_TAIL8 0x2184
963 #define BGE_RXLP_COUNT8 0x2188
964 #define BGE_RXLP_HEAD9 0x2190
965 #define BGE_RXLP_TAIL9 0x2194
966 #define BGE_RXLP_COUNT9 0x2198
967 #define BGE_RXLP_HEAD10 0x21A0
968 #define BGE_RXLP_TAIL10 0x21A4
969 #define BGE_RXLP_COUNT10 0x21A8
970 #define BGE_RXLP_HEAD11 0x21B0
971 #define BGE_RXLP_TAIL11 0x21B4
972 #define BGE_RXLP_COUNT11 0x21B8
973 #define BGE_RXLP_HEAD12 0x21C0
974 #define BGE_RXLP_TAIL12 0x21C4
975 #define BGE_RXLP_COUNT12 0x21C8
976 #define BGE_RXLP_HEAD13 0x21D0
977 #define BGE_RXLP_TAIL13 0x21D4
978 #define BGE_RXLP_COUNT13 0x21D8
979 #define BGE_RXLP_HEAD14 0x21E0
980 #define BGE_RXLP_TAIL14 0x21E4
981 #define BGE_RXLP_COUNT14 0x21E8
982 #define BGE_RXLP_HEAD15 0x21F0
983 #define BGE_RXLP_TAIL15 0x21F4
984 #define BGE_RXLP_COUNT15 0x21F8
985 #define BGE_RXLP_LOCSTAT_COS0 0x2200
986 #define BGE_RXLP_LOCSTAT_COS1 0x2204
987 #define BGE_RXLP_LOCSTAT_COS2 0x2208
988 #define BGE_RXLP_LOCSTAT_COS3 0x220C
989 #define BGE_RXLP_LOCSTAT_COS4 0x2210
990 #define BGE_RXLP_LOCSTAT_COS5 0x2214
991 #define BGE_RXLP_LOCSTAT_COS6 0x2218
992 #define BGE_RXLP_LOCSTAT_COS7 0x221C
993 #define BGE_RXLP_LOCSTAT_COS8 0x2220
994 #define BGE_RXLP_LOCSTAT_COS9 0x2224
995 #define BGE_RXLP_LOCSTAT_COS10 0x2228
996 #define BGE_RXLP_LOCSTAT_COS11 0x222C
997 #define BGE_RXLP_LOCSTAT_COS12 0x2230
998 #define BGE_RXLP_LOCSTAT_COS13 0x2234
999 #define BGE_RXLP_LOCSTAT_COS14 0x2238
1000 #define BGE_RXLP_LOCSTAT_COS15 0x223C
1001 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240
1002 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244
1003 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248
1004 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C
1005 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250
1006 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254
1007 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258
1010 /* Receive List Placement mode register */
1011 #define BGE_RXLPMODE_RESET 0x00000001
1012 #define BGE_RXLPMODE_ENABLE 0x00000002
1013 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004
1014 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008
1015 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010
1017 /* Receive List Placement Status register */
1018 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004
1019 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008
1020 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010
1023 * Receive Data and Receive BD Initiator Control Registers
1025 #define BGE_RDBDI_MODE 0x2400
1026 #define BGE_RDBDI_STATUS 0x2404
1027 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440
1028 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444
1029 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448
1030 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C
1031 #define BGE_RX_STD_RCB_HADDR_HI 0x2450
1032 #define BGE_RX_STD_RCB_HADDR_LO 0x2454
1033 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458
1034 #define BGE_RX_STD_RCB_NICADDR 0x245C
1035 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460
1036 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464
1037 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468
1038 #define BGE_RX_MINI_RCB_NICADDR 0x246C
1039 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470
1040 #define BGE_RDBDI_STD_RX_CONS 0x2474
1041 #define BGE_RDBDI_MINI_RX_CONS 0x2478
1042 #define BGE_RDBDI_RETURN_PROD0 0x2480
1043 #define BGE_RDBDI_RETURN_PROD1 0x2484
1044 #define BGE_RDBDI_RETURN_PROD2 0x2488
1045 #define BGE_RDBDI_RETURN_PROD3 0x248C
1046 #define BGE_RDBDI_RETURN_PROD4 0x2490
1047 #define BGE_RDBDI_RETURN_PROD5 0x2494
1048 #define BGE_RDBDI_RETURN_PROD6 0x2498
1049 #define BGE_RDBDI_RETURN_PROD7 0x249C
1050 #define BGE_RDBDI_RETURN_PROD8 0x24A0
1051 #define BGE_RDBDI_RETURN_PROD9 0x24A4
1052 #define BGE_RDBDI_RETURN_PROD10 0x24A8
1053 #define BGE_RDBDI_RETURN_PROD11 0x24AC
1054 #define BGE_RDBDI_RETURN_PROD12 0x24B0
1055 #define BGE_RDBDI_RETURN_PROD13 0x24B4
1056 #define BGE_RDBDI_RETURN_PROD14 0x24B8
1057 #define BGE_RDBDI_RETURN_PROD15 0x24BC
1058 #define BGE_RDBDI_HWDIAG 0x24C0
1061 /* Receive Data and Receive BD Initiator Mode register */
1062 #define BGE_RDBDIMODE_RESET 0x00000001
1063 #define BGE_RDBDIMODE_ENABLE 0x00000002
1064 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004
1065 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008
1066 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010
1068 /* Receive Data and Receive BD Initiator Status register */
1069 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004
1070 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008
1071 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010
1075 * Receive Data Completion Control registers
1077 #define BGE_RDC_MODE 0x2800
1079 /* Receive Data Completion Mode register */
1080 #define BGE_RDCMODE_RESET 0x00000001
1081 #define BGE_RDCMODE_ENABLE 0x00000002
1082 #define BGE_RDCMODE_ATTN 0x00000004
1085 * Receive BD Initiator Control registers
1087 #define BGE_RBDI_MODE 0x2C00
1088 #define BGE_RBDI_STATUS 0x2C04
1089 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08
1090 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C
1091 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10
1092 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14
1093 #define BGE_RBDI_STD_REPL_THRESH 0x2C18
1094 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C
1096 /* Receive BD Initiator Mode register */
1097 #define BGE_RBDIMODE_RESET 0x00000001
1098 #define BGE_RBDIMODE_ENABLE 0x00000002
1099 #define BGE_RBDIMODE_ATTN 0x00000004
1101 /* Receive BD Initiator Status register */
1102 #define BGE_RBDISTAT_ATTN 0x00000004
1105 * Receive BD Completion Control registers
1107 #define BGE_RBDC_MODE 0x3000
1108 #define BGE_RBDC_STATUS 0x3004
1109 #define BGE_RBDC_JUMBO_BD_PROD 0x3008
1110 #define BGE_RBDC_STD_BD_PROD 0x300C
1111 #define BGE_RBDC_MINI_BD_PROD 0x3010
1113 /* Receive BD completion mode register */
1114 #define BGE_RBDCMODE_RESET 0x00000001
1115 #define BGE_RBDCMODE_ENABLE 0x00000002
1116 #define BGE_RBDCMODE_ATTN 0x00000004
1118 /* Receive BD completion status register */
1119 #define BGE_RBDCSTAT_ERROR 0x00000004
1122 * Receive List Selector Control registers
1124 #define BGE_RXLS_MODE 0x3400
1125 #define BGE_RXLS_STATUS 0x3404
1127 /* Receive List Selector Mode register */
1128 #define BGE_RXLSMODE_RESET 0x00000001
1129 #define BGE_RXLSMODE_ENABLE 0x00000002
1130 #define BGE_RXLSMODE_ATTN 0x00000004
1132 /* Receive List Selector Status register */
1133 #define BGE_RXLSSTAT_ERROR 0x00000004
1136 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs)
1138 #define BGE_MBCF_MODE 0x3800
1139 #define BGE_MBCF_STATUS 0x3804
1141 /* Mbuf Cluster Free mode register */
1142 #define BGE_MBCFMODE_RESET 0x00000001
1143 #define BGE_MBCFMODE_ENABLE 0x00000002
1144 #define BGE_MBCFMODE_ATTN 0x00000004
1146 /* Mbuf Cluster Free status register */
1147 #define BGE_MBCFSTAT_ERROR 0x00000004
1150 * Host Coalescing Control registers
1152 #define BGE_HCC_MODE 0x3C00
1153 #define BGE_HCC_STATUS 0x3C04
1154 #define BGE_HCC_RX_COAL_TICKS 0x3C08
1155 #define BGE_HCC_TX_COAL_TICKS 0x3C0C
1156 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10
1157 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14
1158 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */
1159 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */
1160 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */
1161 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */
1162 #define BGE_HCC_STATS_TICKS 0x3C28
1163 #define BGE_HCC_STATS_ADDR_HI 0x3C30
1164 #define BGE_HCC_STATS_ADDR_LO 0x3C34
1165 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38
1166 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C
1167 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */
1168 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */
1169 #define BGE_FLOW_ATTN 0x3C48
1170 #define BGE_HCC_JUMBO_BD_CONS 0x3C50
1171 #define BGE_HCC_STD_BD_CONS 0x3C54
1172 #define BGE_HCC_MINI_BD_CONS 0x3C58
1173 #define BGE_HCC_RX_RETURN_PROD0 0x3C80
1174 #define BGE_HCC_RX_RETURN_PROD1 0x3C84
1175 #define BGE_HCC_RX_RETURN_PROD2 0x3C88
1176 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C
1177 #define BGE_HCC_RX_RETURN_PROD4 0x3C90
1178 #define BGE_HCC_RX_RETURN_PROD5 0x3C94
1179 #define BGE_HCC_RX_RETURN_PROD6 0x3C98
1180 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C
1181 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0
1182 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4
1183 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8
1184 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC
1185 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0
1186 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4
1187 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8
1188 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC
1189 #define BGE_HCC_TX_BD_CONS0 0x3CC0
1190 #define BGE_HCC_TX_BD_CONS1 0x3CC4
1191 #define BGE_HCC_TX_BD_CONS2 0x3CC8
1192 #define BGE_HCC_TX_BD_CONS3 0x3CCC
1193 #define BGE_HCC_TX_BD_CONS4 0x3CD0
1194 #define BGE_HCC_TX_BD_CONS5 0x3CD4
1195 #define BGE_HCC_TX_BD_CONS6 0x3CD8
1196 #define BGE_HCC_TX_BD_CONS7 0x3CDC
1197 #define BGE_HCC_TX_BD_CONS8 0x3CE0
1198 #define BGE_HCC_TX_BD_CONS9 0x3CE4
1199 #define BGE_HCC_TX_BD_CONS10 0x3CE8
1200 #define BGE_HCC_TX_BD_CONS11 0x3CEC
1201 #define BGE_HCC_TX_BD_CONS12 0x3CF0
1202 #define BGE_HCC_TX_BD_CONS13 0x3CF4
1203 #define BGE_HCC_TX_BD_CONS14 0x3CF8
1204 #define BGE_HCC_TX_BD_CONS15 0x3CFC
1207 /* Host coalescing mode register */
1208 #define BGE_HCCMODE_RESET 0x00000001
1209 #define BGE_HCCMODE_ENABLE 0x00000002
1210 #define BGE_HCCMODE_ATTN 0x00000004
1211 #define BGE_HCCMODE_COAL_NOW 0x00000008
1212 #define BGE_HCCMODE_MSI_BITS 0x00000070
1213 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180
1215 #define BGE_STATBLKSZ_FULL 0x00000000
1216 #define BGE_STATBLKSZ_64BYTE 0x00000080
1217 #define BGE_STATBLKSZ_32BYTE 0x00000100
1219 /* Host coalescing status register */
1220 #define BGE_HCCSTAT_ERROR 0x00000004
1222 /* Flow attention register */
1223 #define BGE_FLOWATTN_MB_LOWAT 0x00000040
1224 #define BGE_FLOWATTN_MEMARB 0x00000080
1225 #define BGE_FLOWATTN_HOSTCOAL 0x00008000
1226 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000
1227 #define BGE_FLOWATTN_RCB_INVAL 0x00020000
1228 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000
1229 #define BGE_FLOWATTN_RDBDI 0x00080000
1230 #define BGE_FLOWATTN_RXLS 0x00100000
1231 #define BGE_FLOWATTN_RXLP 0x00200000
1232 #define BGE_FLOWATTN_RBDC 0x00400000
1233 #define BGE_FLOWATTN_RBDI 0x00800000
1234 #define BGE_FLOWATTN_SDC 0x08000000
1235 #define BGE_FLOWATTN_SDI 0x10000000
1236 #define BGE_FLOWATTN_SRS 0x20000000
1237 #define BGE_FLOWATTN_SBDC 0x40000000
1238 #define BGE_FLOWATTN_SBDI 0x80000000
1241 * Memory arbiter registers
1243 #define BGE_MARB_MODE 0x4000
1244 #define BGE_MARB_STATUS 0x4004
1245 #define BGE_MARB_TRAPADDR_HI 0x4008
1246 #define BGE_MARB_TRAPADDR_LO 0x400C
1248 /* Memory arbiter mode register */
1249 #define BGE_MARBMODE_RESET 0x00000001
1250 #define BGE_MARBMODE_ENABLE 0x00000002
1251 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004
1252 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008
1253 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010
1254 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020
1255 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040
1256 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080
1257 #define BGE_MARBMODE_PCI_TRAP 0x00000100
1258 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200
1259 #define BGE_MARBMODE_RXQ_TRAP 0x00000400
1260 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800
1261 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000
1262 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000
1263 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000
1264 #define BGE_MARBMODE_MBUF_TRAP 0x00008000
1265 #define BGE_MARBMODE_TXDI_TRAP 0x00010000
1266 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000
1267 #define BGE_MARBMODE_TXBD_TRAP 0x00040000
1268 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000
1269 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000
1270 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000
1271 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000
1272 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000
1273 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000
1274 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000
1276 /* Memory arbiter status register */
1277 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004
1278 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008
1279 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010
1280 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020
1281 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040
1282 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080
1283 #define BGE_MARBSTAT_PCI_TRAP 0x00000100
1284 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200
1285 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400
1286 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800
1287 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000
1288 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000
1289 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000
1290 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000
1291 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000
1292 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000
1293 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000
1294 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000
1295 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000
1296 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000
1297 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000
1298 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000
1299 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000
1300 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000
1303 * Buffer manager control registers
1305 #define BGE_BMAN_MODE 0x4400
1306 #define BGE_BMAN_STATUS 0x4404
1307 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408
1308 #define BGE_BMAN_MBUFPOOL_LEN 0x440C
1309 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410
1310 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414
1311 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418
1312 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C
1313 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420
1314 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424
1315 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428
1316 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C
1317 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430
1318 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434
1319 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438
1320 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C
1321 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440
1322 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444
1323 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448
1324 #define BGE_BMAN_HWDIAG_1 0x444C
1325 #define BGE_BMAN_HWDIAG_2 0x4450
1326 #define BGE_BMAN_HWDIAG_3 0x4454
1328 /* Buffer manager mode register */
1329 #define BGE_BMANMODE_RESET 0x00000001
1330 #define BGE_BMANMODE_ENABLE 0x00000002
1331 #define BGE_BMANMODE_ATTN 0x00000004
1332 #define BGE_BMANMODE_TESTMODE 0x00000008
1333 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010
1335 /* Buffer manager status register */
1336 #define BGE_BMANSTAT_ERRO 0x00000004
1337 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010
1341 * Read DMA Control registers
1343 #define BGE_RDMA_MODE 0x4800
1344 #define BGE_RDMA_STATUS 0x4804
1346 /* Read DMA mode register */
1347 #define BGE_RDMAMODE_RESET 0x00000001
1348 #define BGE_RDMAMODE_ENABLE 0x00000002
1349 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
1350 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1351 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010
1352 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
1353 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
1354 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
1355 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
1356 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200
1357 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC
1359 /* Read DMA status register */
1360 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
1361 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1362 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010
1363 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
1364 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
1365 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
1366 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
1367 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200
1370 * Write DMA control registers
1372 #define BGE_WDMA_MODE 0x4C00
1373 #define BGE_WDMA_STATUS 0x4C04
1375 /* Write DMA mode register */
1376 #define BGE_WDMAMODE_RESET 0x00000001
1377 #define BGE_WDMAMODE_ENABLE 0x00000002
1378 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
1379 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1380 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010
1381 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
1382 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
1383 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
1384 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
1385 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200
1386 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC
1388 /* Write DMA status register */
1389 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
1390 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1391 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010
1392 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
1393 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
1394 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
1395 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
1396 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200
1402 #define BGE_RXCPU_MODE 0x5000
1403 #define BGE_RXCPU_STATUS 0x5004
1404 #define BGE_RXCPU_PC 0x501C
1406 /* RX CPU mode register */
1407 #define BGE_RXCPUMODE_RESET 0x00000001
1408 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002
1409 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004
1410 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008
1411 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010
1412 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020
1413 #define BGE_RXCPUMODE_ROMFAIL 0x00000040
1414 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080
1415 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100
1416 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200
1417 #define BGE_RXCPUMODE_HALTCPU 0x00000400
1418 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800
1419 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
1420 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000
1422 /* RX CPU status register */
1423 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001
1424 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
1425 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004
1426 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008
1427 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010
1428 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020
1429 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040
1430 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080
1431 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100
1432 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200
1433 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000
1434 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000
1435 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
1436 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
1437 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
1438 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
1439 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000
1445 #define BGE_TXCPU_MODE 0x5400
1446 #define BGE_TXCPU_STATUS 0x5404
1447 #define BGE_TXCPU_PC 0x541C
1449 /* TX CPU mode register */
1450 #define BGE_TXCPUMODE_RESET 0x00000001
1451 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002
1452 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004
1453 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008
1454 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010
1455 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020
1456 #define BGE_TXCPUMODE_ROMFAIL 0x00000040
1457 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080
1458 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100
1459 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200
1460 #define BGE_TXCPUMODE_HALTCPU 0x00000400
1461 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800
1462 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
1464 /* TX CPU status register */
1465 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001
1466 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
1467 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004
1468 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008
1469 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010
1470 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020
1471 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040
1472 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080
1473 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100
1474 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200
1475 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000
1476 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000
1477 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
1478 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
1479 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
1480 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
1481 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000
1485 * Low priority mailbox registers
1487 #define BGE_LPMBX_IRQ0_HI 0x5800
1488 #define BGE_LPMBX_IRQ0_LO 0x5804
1489 #define BGE_LPMBX_IRQ1_HI 0x5808
1490 #define BGE_LPMBX_IRQ1_LO 0x580C
1491 #define BGE_LPMBX_IRQ2_HI 0x5810
1492 #define BGE_LPMBX_IRQ2_LO 0x5814
1493 #define BGE_LPMBX_IRQ3_HI 0x5818
1494 #define BGE_LPMBX_IRQ3_LO 0x581C
1495 #define BGE_LPMBX_GEN0_HI 0x5820
1496 #define BGE_LPMBX_GEN0_LO 0x5824
1497 #define BGE_LPMBX_GEN1_HI 0x5828
1498 #define BGE_LPMBX_GEN1_LO 0x582C
1499 #define BGE_LPMBX_GEN2_HI 0x5830
1500 #define BGE_LPMBX_GEN2_LO 0x5834
1501 #define BGE_LPMBX_GEN3_HI 0x5828
1502 #define BGE_LPMBX_GEN3_LO 0x582C
1503 #define BGE_LPMBX_GEN4_HI 0x5840
1504 #define BGE_LPMBX_GEN4_LO 0x5844
1505 #define BGE_LPMBX_GEN5_HI 0x5848
1506 #define BGE_LPMBX_GEN5_LO 0x584C
1507 #define BGE_LPMBX_GEN6_HI 0x5850
1508 #define BGE_LPMBX_GEN6_LO 0x5854
1509 #define BGE_LPMBX_GEN7_HI 0x5858
1510 #define BGE_LPMBX_GEN7_LO 0x585C
1511 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860
1512 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864
1513 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868
1514 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C
1515 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870
1516 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874
1517 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878
1518 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C
1519 #define BGE_LPMBX_RX_CONS0_HI 0x5880
1520 #define BGE_LPMBX_RX_CONS0_LO 0x5884
1521 #define BGE_LPMBX_RX_CONS1_HI 0x5888
1522 #define BGE_LPMBX_RX_CONS1_LO 0x588C
1523 #define BGE_LPMBX_RX_CONS2_HI 0x5890
1524 #define BGE_LPMBX_RX_CONS2_LO 0x5894
1525 #define BGE_LPMBX_RX_CONS3_HI 0x5898
1526 #define BGE_LPMBX_RX_CONS3_LO 0x589C
1527 #define BGE_LPMBX_RX_CONS4_HI 0x58A0
1528 #define BGE_LPMBX_RX_CONS4_LO 0x58A4
1529 #define BGE_LPMBX_RX_CONS5_HI 0x58A8
1530 #define BGE_LPMBX_RX_CONS5_LO 0x58AC
1531 #define BGE_LPMBX_RX_CONS6_HI 0x58B0
1532 #define BGE_LPMBX_RX_CONS6_LO 0x58B4
1533 #define BGE_LPMBX_RX_CONS7_HI 0x58B8
1534 #define BGE_LPMBX_RX_CONS7_LO 0x58BC
1535 #define BGE_LPMBX_RX_CONS8_HI 0x58C0
1536 #define BGE_LPMBX_RX_CONS8_LO 0x58C4
1537 #define BGE_LPMBX_RX_CONS9_HI 0x58C8
1538 #define BGE_LPMBX_RX_CONS9_LO 0x58CC
1539 #define BGE_LPMBX_RX_CONS10_HI 0x58D0
1540 #define BGE_LPMBX_RX_CONS10_LO 0x58D4
1541 #define BGE_LPMBX_RX_CONS11_HI 0x58D8
1542 #define BGE_LPMBX_RX_CONS11_LO 0x58DC
1543 #define BGE_LPMBX_RX_CONS12_HI 0x58E0
1544 #define BGE_LPMBX_RX_CONS12_LO 0x58E4
1545 #define BGE_LPMBX_RX_CONS13_HI 0x58E8
1546 #define BGE_LPMBX_RX_CONS13_LO 0x58EC
1547 #define BGE_LPMBX_RX_CONS14_HI 0x58F0
1548 #define BGE_LPMBX_RX_CONS14_LO 0x58F4
1549 #define BGE_LPMBX_RX_CONS15_HI 0x58F8
1550 #define BGE_LPMBX_RX_CONS15_LO 0x58FC
1551 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900
1552 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904
1553 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908
1554 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C
1555 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910
1556 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914
1557 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918
1558 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C
1559 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920
1560 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924
1561 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928
1562 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C
1563 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930
1564 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934
1565 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938
1566 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C
1567 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940
1568 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944
1569 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948
1570 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C
1571 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950
1572 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954
1573 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958
1574 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C
1575 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960
1576 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964
1577 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968
1578 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C
1579 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970
1580 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974
1581 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978
1582 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C
1583 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980
1584 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984
1585 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988
1586 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C
1587 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990
1588 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994
1589 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998
1590 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C
1591 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0
1592 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4
1593 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8
1594 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC
1595 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0
1596 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4
1597 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8
1598 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC
1599 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0
1600 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4
1601 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8
1602 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC
1603 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0
1604 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4
1605 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8
1606 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC
1607 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0
1608 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4
1609 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8
1610 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC
1611 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0
1612 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4
1613 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8
1614 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC
1617 * Flow throw Queue reset register
1619 #define BGE_FTQ_RESET 0x5C00
1621 #define BGE_FTQRESET_DMAREAD 0x00000002
1622 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004
1623 #define BGE_FTQRESET_DMADONE 0x00000010
1624 #define BGE_FTQRESET_SBDC 0x00000020
1625 #define BGE_FTQRESET_SDI 0x00000040
1626 #define BGE_FTQRESET_WDMA 0x00000080
1627 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100
1628 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200
1629 #define BGE_FTQRESET_SDC 0x00000400
1630 #define BGE_FTQRESET_HCC 0x00000800
1631 #define BGE_FTQRESET_TXFIFO 0x00001000
1632 #define BGE_FTQRESET_MBC 0x00002000
1633 #define BGE_FTQRESET_RBDC 0x00004000
1634 #define BGE_FTQRESET_RXLP 0x00008000
1635 #define BGE_FTQRESET_RDBDI 0x00010000
1636 #define BGE_FTQRESET_RDC 0x00020000
1637 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000
1640 * Message Signaled Interrupt registers
1642 #define BGE_MSI_MODE 0x6000
1643 #define BGE_MSI_STATUS 0x6004
1644 #define BGE_MSI_FIFOACCESS 0x6008
1646 /* MSI mode register */
1647 #define BGE_MSIMODE_RESET 0x00000001
1648 #define BGE_MSIMODE_ENABLE 0x00000002
1649 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004
1650 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1651 #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010
1652 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020
1653 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040
1655 /* MSI status register */
1656 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004
1657 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1658 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010
1659 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020
1660 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040
1664 * DMA Completion registers
1666 #define BGE_DMAC_MODE 0x6400
1668 /* DMA Completion mode register */
1669 #define BGE_DMACMODE_RESET 0x00000001
1670 #define BGE_DMACMODE_ENABLE 0x00000002
1674 * General control registers.
1676 #define BGE_MODE_CTL 0x6800
1677 #define BGE_MISC_CFG 0x6804
1678 #define BGE_MISC_LOCAL_CTL 0x6808
1679 #define BGE_CPU_EVENT 0x6810
1680 #define BGE_EE_ADDR 0x6838
1681 #define BGE_EE_DATA 0x683C
1682 #define BGE_EE_CTL 0x6840
1683 #define BGE_MDI_CTL 0x6844
1684 #define BGE_EE_DELAY 0x6848
1685 #define BGE_FASTBOOT_PC 0x6894
1687 /* Mode control register */
1688 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001
1689 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002
1690 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004
1691 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010
1692 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020
1693 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200
1694 #define BGE_MODECTL_NO_RX_CRC 0x00000400
1695 #define BGE_MODECTL_RX_BADFRAMES 0x00000800
1696 #define BGE_MODECTL_NO_TX_INTR 0x00002000
1697 #define BGE_MODECTL_NO_RX_INTR 0x00004000
1698 #define BGE_MODECTL_FORCE_PCI32 0x00008000
1699 #define BGE_MODECTL_STACKUP 0x00010000
1700 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000
1701 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000
1702 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000
1703 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000
1704 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000
1705 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000
1706 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000
1707 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000
1708 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000
1709 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000
1711 /* Misc. config register */
1712 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001
1713 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE
1715 #define BGE_32BITTIME_66MHZ (0x41 << 1)
1717 /* Misc. Local Control */
1718 #define BGE_MLC_INTR_STATE 0x00000001
1719 #define BGE_MLC_INTR_CLR 0x00000002
1720 #define BGE_MLC_INTR_SET 0x00000004
1721 #define BGE_MLC_INTR_ONATTN 0x00000008
1722 #define BGE_MLC_MISCIO_IN0 0x00000100
1723 #define BGE_MLC_MISCIO_IN1 0x00000200
1724 #define BGE_MLC_MISCIO_IN2 0x00000400
1725 #define BGE_MLC_MISCIO_OUTEN0 0x00000800
1726 #define BGE_MLC_MISCIO_OUTEN1 0x00001000
1727 #define BGE_MLC_MISCIO_OUTEN2 0x00002000
1728 #define BGE_MLC_MISCIO_OUT0 0x00004000
1729 #define BGE_MLC_MISCIO_OUT1 0x00008000
1730 #define BGE_MLC_MISCIO_OUT2 0x00010000
1731 #define BGE_MLC_EXTRAM_ENB 0x00020000
1732 #define BGE_MLC_SRAM_SIZE 0x001C0000
1733 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */
1734 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */
1735 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000
1736 #define BGE_MLC_AUTO_EEPROM 0x01000000
1738 #define BGE_SSRAMSIZE_256KB 0x00000000
1739 #define BGE_SSRAMSIZE_512KB 0x00040000
1740 #define BGE_SSRAMSIZE_1MB 0x00080000
1741 #define BGE_SSRAMSIZE_2MB 0x000C0000
1742 #define BGE_SSRAMSIZE_4MB 0x00100000
1743 #define BGE_SSRAMSIZE_8MB 0x00140000
1744 #define BGE_SSRAMSIZE_16M 0x00180000
1746 /* EEPROM address register */
1747 #define BGE_EEADDR_ADDRESS 0x0000FFFC
1748 #define BGE_EEADDR_HALFCLK 0x01FF0000
1749 #define BGE_EEADDR_START 0x02000000
1750 #define BGE_EEADDR_DEVID 0x1C000000
1751 #define BGE_EEADDR_RESET 0x20000000
1752 #define BGE_EEADDR_DONE 0x40000000
1753 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */
1755 #define BGE_EEDEVID(x) ((x & 7) << 26)
1756 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16)
1757 #define BGE_HALFCLK_384SCL 0x60
1758 #define BGE_EE_READCMD \
1759 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
1760 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE)
1761 #define BGE_EE_WRCMD \
1762 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
1763 BGE_EEADDR_START|BGE_EEADDR_DONE)
1765 /* EEPROM Control register */
1766 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001
1767 #define BGE_EECTL_CLKOUT 0x00000002
1768 #define BGE_EECTL_CLKIN 0x00000004
1769 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008
1770 #define BGE_EECTL_DATAOUT 0x00000010
1771 #define BGE_EECTL_DATAIN 0x00000020
1773 /* MDI (MII/GMII) access register */
1774 #define BGE_MDI_DATA 0x00000001
1775 #define BGE_MDI_DIR 0x00000002
1776 #define BGE_MDI_SEL 0x00000004
1777 #define BGE_MDI_CLK 0x00000008
1779 #define BGE_MEMWIN_START 0x00008000
1780 #define BGE_MEMWIN_END 0x0000FFFF
1783 #define BGE_MEMWIN_READ(sc, x, val) \
1785 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
1786 (0xFFFF0000 & x), 4); \
1787 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \
1790 #define BGE_MEMWIN_WRITE(sc, x, val) \
1792 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
1793 (0xFFFF0000 & x), 4); \
1794 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \
1798 * This magic number is written to the firmware mailbox at 0xb50
1799 * before a software reset is issued. After the internal firmware
1800 * has completed its initialization it will write the opposite of
1801 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the
1802 * driver to synchronize with the firmware.
1804 #define BGE_MAGIC_NUMBER 0x4B657654
1807 uint32_t bge_addr_hi;
1808 uint32_t bge_addr_lo;
1811 #define BGE_HOSTADDR(x, y) \
1813 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \
1814 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \
1817 #define BGE_ADDR_LO(y) \
1818 ((uint64_t) (y) & 0xFFFFFFFF)
1819 #define BGE_ADDR_HI(y) \
1820 ((uint64_t) (y) >> 32)
1822 /* Ring control block structure */
1824 bge_hostaddr bge_hostaddr;
1825 uint32_t bge_maxlen_flags;
1826 uint32_t bge_nicaddr;
1829 #define RCB_WRITE_4(sc, rcb, offset, val) \
1830 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \
1831 rcb + offsetof(struct bge_rcb, offset), val)
1832 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags))
1834 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001
1835 #define BGE_RCB_FLAG_RING_DISABLED 0x0002
1838 bge_hostaddr bge_addr;
1839 #if BYTE_ORDER == LITTLE_ENDIAN
1842 uint16_t bge_vlan_tag;
1848 uint16_t bge_vlan_tag;
1852 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001
1853 #define BGE_TXBDFLAG_IP_CSUM 0x0002
1854 #define BGE_TXBDFLAG_END 0x0004
1855 #define BGE_TXBDFLAG_IP_FRAG 0x0008
1856 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010
1857 #define BGE_TXBDFLAG_VLAN_TAG 0x0040
1858 #define BGE_TXBDFLAG_COAL_NOW 0x0080
1859 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100
1860 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200
1861 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000
1862 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000
1863 #define BGE_TXBDFLAG_NO_CRC 0x8000
1865 #define BGE_NIC_TXRING_ADDR(ringno, size) \
1866 BGE_SEND_RING_1_TO_4 + \
1867 ((ringno * sizeof(struct bge_tx_bd) * size) / 4)
1870 bge_hostaddr bge_addr;
1871 #if BYTE_ORDER == LITTLE_ENDIAN
1876 uint16_t bge_tcp_udp_csum;
1877 uint16_t bge_ip_csum;
1878 uint16_t bge_vlan_tag;
1879 uint16_t bge_error_flag;
1885 uint16_t bge_ip_csum;
1886 uint16_t bge_tcp_udp_csum;
1887 uint16_t bge_error_flag;
1888 uint16_t bge_vlan_tag;
1891 uint32_t bge_opaque;
1894 struct bge_extrx_bd {
1895 bge_hostaddr bge_addr1;
1896 bge_hostaddr bge_addr2;
1897 bge_hostaddr bge_addr3;
1898 #if BYTE_ORDER == LITTLE_ENDIAN
1909 bge_hostaddr bge_addr0;
1910 #if BYTE_ORDER == LITTLE_ENDIAN
1915 uint16_t bge_tcp_udp_csum;
1916 uint16_t bge_ip_csum;
1917 uint16_t bge_vlan_tag;
1918 uint16_t bge_error_flag;
1924 uint16_t bge_ip_csum;
1925 uint16_t bge_tcp_udp_csum;
1926 uint16_t bge_error_flag;
1927 uint16_t bge_vlan_tag;
1930 uint32_t bge_opaque;
1933 #define BGE_RXBDFLAG_END 0x0004
1934 #define BGE_RXBDFLAG_JUMBO_RING 0x0020
1935 #define BGE_RXBDFLAG_VLAN_TAG 0x0040
1936 #define BGE_RXBDFLAG_ERROR 0x0400
1937 #define BGE_RXBDFLAG_MINI_RING 0x0800
1938 #define BGE_RXBDFLAG_IP_CSUM 0x1000
1939 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000
1940 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000
1942 #define BGE_RXERRFLAG_BAD_CRC 0x0001
1943 #define BGE_RXERRFLAG_COLL_DETECT 0x0002
1944 #define BGE_RXERRFLAG_LINK_LOST 0x0004
1945 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008
1946 #define BGE_RXERRFLAG_MAC_ABORT 0x0010
1947 #define BGE_RXERRFLAG_RUNT 0x0020
1948 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040
1949 #define BGE_RXERRFLAG_GIANT 0x0080
1951 struct bge_sts_idx {
1952 #if BYTE_ORDER == LITTLE_ENDIAN
1953 uint16_t bge_rx_prod_idx;
1954 uint16_t bge_tx_cons_idx;
1956 uint16_t bge_tx_cons_idx;
1957 uint16_t bge_rx_prod_idx;
1961 struct bge_status_block {
1962 uint32_t bge_status;
1964 #if BYTE_ORDER == LITTLE_ENDIAN
1965 uint16_t bge_rx_jumbo_cons_idx;
1966 uint16_t bge_rx_std_cons_idx;
1967 uint16_t bge_rx_mini_cons_idx;
1970 uint16_t bge_rx_std_cons_idx;
1971 uint16_t bge_rx_jumbo_cons_idx;
1973 uint16_t bge_rx_mini_cons_idx;
1975 struct bge_sts_idx bge_idx[16];
1978 #define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx
1979 #define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx
1981 #define BGE_STATFLAG_UPDATED 0x00000001
1982 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002
1983 #define BGE_STATFLAG_ERROR 0x00000004
1987 * Broadcom Vendor ID
1988 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID
1989 * even though they're now manufactured by Broadcom)
1991 #define BCOM_VENDORID 0x14E4
1992 #define BCOM_DEVICEID_BCM5700 0x1644
1993 #define BCOM_DEVICEID_BCM5701 0x1645
1994 #define BCOM_DEVICEID_BCM5702 0x1646
1995 #define BCOM_DEVICEID_BCM5702X 0x16A6
1996 #define BCOM_DEVICEID_BCM5702_ALT 0x16C6
1997 #define BCOM_DEVICEID_BCM5703 0x1647
1998 #define BCOM_DEVICEID_BCM5703X 0x16A7
1999 #define BCOM_DEVICEID_BCM5703_ALT 0x16C7
2000 #define BCOM_DEVICEID_BCM5704C 0x1648
2001 #define BCOM_DEVICEID_BCM5704S 0x16A8
2002 #define BCOM_DEVICEID_BCM5704S_ALT 0x1649
2003 #define BCOM_DEVICEID_BCM5705 0x1653
2004 #define BCOM_DEVICEID_BCM5705K 0x1654
2005 #define BCOM_DEVICEID_BCM5705F 0x166E
2006 #define BCOM_DEVICEID_BCM5705M 0x165D
2007 #define BCOM_DEVICEID_BCM5705M_ALT 0x165E
2008 #define BCOM_DEVICEID_BCM5714C 0x1668
2009 #define BCOM_DEVICEID_BCM5714S 0x1669
2010 #define BCOM_DEVICEID_BCM5715 0x1678
2011 #define BCOM_DEVICEID_BCM5715S 0x1679
2012 #define BCOM_DEVICEID_BCM5720 0x1658
2013 #define BCOM_DEVICEID_BCM5721 0x1659
2014 #define BCOM_DEVICEID_BCM5722 0x165a
2015 #define BCOM_DEVICEID_BCM5750 0x1676
2016 #define BCOM_DEVICEID_BCM5750M 0x167C
2017 #define BCOM_DEVICEID_BCM5751 0x1677
2018 #define BCOM_DEVICEID_BCM5751F 0x167E
2019 #define BCOM_DEVICEID_BCM5751M 0x167D
2020 #define BCOM_DEVICEID_BCM5752 0x1600
2021 #define BCOM_DEVICEID_BCM5752M 0x1601
2022 #define BCOM_DEVICEID_BCM5753 0x16F7
2023 #define BCOM_DEVICEID_BCM5753F 0x16FE
2024 #define BCOM_DEVICEID_BCM5753M 0x16FD
2025 #define BCOM_DEVICEID_BCM5754 0x167A
2026 #define BCOM_DEVICEID_BCM5754M 0x1672
2027 #define BCOM_DEVICEID_BCM5755 0x167B
2028 #define BCOM_DEVICEID_BCM5755M 0x1673
2029 #define BCOM_DEVICEID_BCM5780 0x166A
2030 #define BCOM_DEVICEID_BCM5780S 0x166B
2031 #define BCOM_DEVICEID_BCM5781 0x16DD
2032 #define BCOM_DEVICEID_BCM5782 0x1696
2033 #define BCOM_DEVICEID_BCM5786 0x169A
2034 #define BCOM_DEVICEID_BCM5787 0x169B
2035 #define BCOM_DEVICEID_BCM5787M 0x1693
2036 #define BCOM_DEVICEID_BCM5788 0x169C
2037 #define BCOM_DEVICEID_BCM5789 0x169D
2038 #define BCOM_DEVICEID_BCM5901 0x170D
2039 #define BCOM_DEVICEID_BCM5901A2 0x170E
2040 #define BCOM_DEVICEID_BCM5903M 0x16FF
2043 * Alteon AceNIC PCI vendor/device ID.
2045 #define ALTEON_VENDORID 0x12AE
2046 #define ALTEON_DEVICEID_ACENIC 0x0001
2047 #define ALTEON_DEVICEID_ACENIC_COPPER 0x0002
2048 #define ALTEON_DEVICEID_BCM5700 0x0003
2049 #define ALTEON_DEVICEID_BCM5701 0x0004
2052 * 3Com 3c996 PCI vendor/device ID.
2054 #define TC_VENDORID 0x10B7
2055 #define TC_DEVICEID_3C996 0x0003
2058 * SysKonnect PCI vendor ID
2060 #define SK_VENDORID 0x1148
2061 #define SK_DEVICEID_ALTIMA 0x4400
2062 #define SK_SUBSYSID_9D21 0x4421
2063 #define SK_SUBSYSID_9D41 0x4441
2066 * Altima PCI vendor/device ID.
2068 #define ALTIMA_VENDORID 0x173b
2069 #define ALTIMA_DEVICE_AC1000 0x03e8
2070 #define ALTIMA_DEVICE_AC1002 0x03e9
2071 #define ALTIMA_DEVICE_AC9100 0x03ea
2074 * Dell PCI vendor ID
2077 #define DELL_VENDORID 0x1028
2080 * Apple PCI vendor ID.
2082 #define APPLE_VENDORID 0x106b
2083 #define APPLE_DEVICE_BCM5701 0x1645
2088 #define SUN_VENDORID 0x108e
2091 * Offset of MAC address inside EEPROM.
2093 #define BGE_EE_MAC_OFFSET 0x7C
2094 #define BGE_EE_HWCFG_OFFSET 0xC8
2096 #define BGE_HWCFG_VOLTAGE 0x00000003
2097 #define BGE_HWCFG_PHYLED_MODE 0x0000000C
2098 #define BGE_HWCFG_MEDIA 0x00000030
2099 #define BGE_HWCFG_ASF 0x00000080
2101 #define BGE_VOLTAGE_1POINT3 0x00000000
2102 #define BGE_VOLTAGE_1POINT8 0x00000001
2104 #define BGE_PHYLEDMODE_UNSPEC 0x00000000
2105 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004
2106 #define BGE_PHYLEDMODE_SINGLELED 0x00000008
2108 #define BGE_MEDIA_UNSPEC 0x00000000
2109 #define BGE_MEDIA_COPPER 0x00000010
2110 #define BGE_MEDIA_FIBER 0x00000020
2112 #define BGE_TICKS_PER_SEC 1000000
2115 * Ring size constants.
2117 #define BGE_EVENT_RING_CNT 256
2118 #define BGE_CMD_RING_CNT 64
2119 #define BGE_STD_RX_RING_CNT 512
2120 #define BGE_JUMBO_RX_RING_CNT 256
2121 #define BGE_MINI_RX_RING_CNT 1024
2122 #define BGE_RETURN_RING_CNT 1024
2124 /* 5705 has smaller return ring size */
2126 #define BGE_RETURN_RING_CNT_5705 512
2129 * Possible TX ring sizes.
2131 #define BGE_TX_RING_CNT_128 128
2132 #define BGE_TX_RING_BASE_128 0x3800
2134 #define BGE_TX_RING_CNT_256 256
2135 #define BGE_TX_RING_BASE_256 0x3000
2137 #define BGE_TX_RING_CNT_512 512
2138 #define BGE_TX_RING_BASE_512 0x2000
2140 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512
2141 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512
2144 * Tigon III statistics counters.
2146 /* Statistics maintained MAC Receive block. */
2147 struct bge_rx_mac_stats {
2148 bge_hostaddr ifHCInOctets;
2149 bge_hostaddr Reserved1;
2150 bge_hostaddr etherStatsFragments;
2151 bge_hostaddr ifHCInUcastPkts;
2152 bge_hostaddr ifHCInMulticastPkts;
2153 bge_hostaddr ifHCInBroadcastPkts;
2154 bge_hostaddr dot3StatsFCSErrors;
2155 bge_hostaddr dot3StatsAlignmentErrors;
2156 bge_hostaddr xonPauseFramesReceived;
2157 bge_hostaddr xoffPauseFramesReceived;
2158 bge_hostaddr macControlFramesReceived;
2159 bge_hostaddr xoffStateEntered;
2160 bge_hostaddr dot3StatsFramesTooLong;
2161 bge_hostaddr etherStatsJabbers;
2162 bge_hostaddr etherStatsUndersizePkts;
2163 bge_hostaddr inRangeLengthError;
2164 bge_hostaddr outRangeLengthError;
2165 bge_hostaddr etherStatsPkts64Octets;
2166 bge_hostaddr etherStatsPkts65Octetsto127Octets;
2167 bge_hostaddr etherStatsPkts128Octetsto255Octets;
2168 bge_hostaddr etherStatsPkts256Octetsto511Octets;
2169 bge_hostaddr etherStatsPkts512Octetsto1023Octets;
2170 bge_hostaddr etherStatsPkts1024Octetsto1522Octets;
2171 bge_hostaddr etherStatsPkts1523Octetsto2047Octets;
2172 bge_hostaddr etherStatsPkts2048Octetsto4095Octets;
2173 bge_hostaddr etherStatsPkts4096Octetsto8191Octets;
2174 bge_hostaddr etherStatsPkts8192Octetsto9022Octets;
2178 /* Statistics maintained MAC Transmit block. */
2179 struct bge_tx_mac_stats {
2180 bge_hostaddr ifHCOutOctets;
2181 bge_hostaddr Reserved2;
2182 bge_hostaddr etherStatsCollisions;
2183 bge_hostaddr outXonSent;
2184 bge_hostaddr outXoffSent;
2185 bge_hostaddr flowControlDone;
2186 bge_hostaddr dot3StatsInternalMacTransmitErrors;
2187 bge_hostaddr dot3StatsSingleCollisionFrames;
2188 bge_hostaddr dot3StatsMultipleCollisionFrames;
2189 bge_hostaddr dot3StatsDeferredTransmissions;
2190 bge_hostaddr Reserved3;
2191 bge_hostaddr dot3StatsExcessiveCollisions;
2192 bge_hostaddr dot3StatsLateCollisions;
2193 bge_hostaddr dot3Collided2Times;
2194 bge_hostaddr dot3Collided3Times;
2195 bge_hostaddr dot3Collided4Times;
2196 bge_hostaddr dot3Collided5Times;
2197 bge_hostaddr dot3Collided6Times;
2198 bge_hostaddr dot3Collided7Times;
2199 bge_hostaddr dot3Collided8Times;
2200 bge_hostaddr dot3Collided9Times;
2201 bge_hostaddr dot3Collided10Times;
2202 bge_hostaddr dot3Collided11Times;
2203 bge_hostaddr dot3Collided12Times;
2204 bge_hostaddr dot3Collided13Times;
2205 bge_hostaddr dot3Collided14Times;
2206 bge_hostaddr dot3Collided15Times;
2207 bge_hostaddr ifHCOutUcastPkts;
2208 bge_hostaddr ifHCOutMulticastPkts;
2209 bge_hostaddr ifHCOutBroadcastPkts;
2210 bge_hostaddr dot3StatsCarrierSenseErrors;
2211 bge_hostaddr ifOutDiscards;
2212 bge_hostaddr ifOutErrors;
2215 /* Stats counters access through registers */
2216 struct bge_mac_stats_regs {
2217 uint32_t ifHCOutOctets;
2219 uint32_t etherStatsCollisions;
2220 uint32_t outXonSent;
2221 uint32_t outXoffSent;
2223 uint32_t dot3StatsInternalMacTransmitErrors;
2224 uint32_t dot3StatsSingleCollisionFrames;
2225 uint32_t dot3StatsMultipleCollisionFrames;
2226 uint32_t dot3StatsDeferredTransmissions;
2228 uint32_t dot3StatsExcessiveCollisions;
2229 uint32_t dot3StatsLateCollisions;
2230 uint32_t Reserved3[14];
2231 uint32_t ifHCOutUcastPkts;
2232 uint32_t ifHCOutMulticastPkts;
2233 uint32_t ifHCOutBroadcastPkts;
2234 uint32_t Reserved4[2];
2235 uint32_t ifHCInOctets;
2237 uint32_t etherStatsFragments;
2238 uint32_t ifHCInUcastPkts;
2239 uint32_t ifHCInMulticastPkts;
2240 uint32_t ifHCInBroadcastPkts;
2241 uint32_t dot3StatsFCSErrors;
2242 uint32_t dot3StatsAlignmentErrors;
2243 uint32_t xonPauseFramesReceived;
2244 uint32_t xoffPauseFramesReceived;
2245 uint32_t macControlFramesReceived;
2246 uint32_t xoffStateEntered;
2247 uint32_t dot3StatsFramesTooLong;
2248 uint32_t etherStatsJabbers;
2249 uint32_t etherStatsUndersizePkts;
2253 uint8_t Reserved0[256];
2255 /* Statistics maintained by Receive MAC. */
2256 struct bge_rx_mac_stats rxstats;
2258 bge_hostaddr Unused1[37];
2260 /* Statistics maintained by Transmit MAC. */
2261 struct bge_tx_mac_stats txstats;
2263 bge_hostaddr Unused2[31];
2265 /* Statistics maintained by Receive List Placement. */
2266 bge_hostaddr COSIfHCInPkts[16];
2267 bge_hostaddr COSFramesDroppedDueToFilters;
2268 bge_hostaddr nicDmaWriteQueueFull;
2269 bge_hostaddr nicDmaWriteHighPriQueueFull;
2270 bge_hostaddr nicNoMoreRxBDs;
2271 bge_hostaddr ifInDiscards;
2272 bge_hostaddr ifInErrors;
2273 bge_hostaddr nicRecvThresholdHit;
2275 bge_hostaddr Unused3[9];
2277 /* Statistics maintained by Send Data Initiator. */
2278 bge_hostaddr COSIfHCOutPkts[16];
2279 bge_hostaddr nicDmaReadQueueFull;
2280 bge_hostaddr nicDmaReadHighPriQueueFull;
2281 bge_hostaddr nicSendDataCompQueueFull;
2283 /* Statistics maintained by Host Coalescing. */
2284 bge_hostaddr nicRingSetSendProdIndex;
2285 bge_hostaddr nicRingStatusUpdate;
2286 bge_hostaddr nicInterrupts;
2287 bge_hostaddr nicAvoidedInterrupts;
2288 bge_hostaddr nicSendThresholdHit;
2290 uint8_t Reserved4[320];
2294 * Tigon general information block. This resides in host memory
2295 * and contains the status counters, ring control blocks and
2296 * producer pointers.
2300 struct bge_stats bge_stats;
2301 struct bge_rcb bge_tx_rcb[16];
2302 struct bge_rcb bge_std_rx_rcb;
2303 struct bge_rcb bge_jumbo_rx_rcb;
2304 struct bge_rcb bge_mini_rx_rcb;
2305 struct bge_rcb bge_return_rcb;
2308 #define BGE_FRAMELEN 1518
2309 #define BGE_MAX_FRAMELEN 1536
2310 #define BGE_JUMBO_FRAMELEN 9018
2311 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
2312 #define BGE_MIN_FRAMELEN 60
2315 * Other utility macros.
2317 #define BGE_INC(x, y) (x) = (x + 1) % y
2320 * Register access macros. The Tigon always uses memory mapped register
2321 * accesses and all registers must be accessed with 32 bit operations.
2324 #define CSR_WRITE_4(sc, reg, val) \
2325 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val)
2327 #define CSR_READ_4(sc, reg) \
2328 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg)
2330 #define BGE_SETBIT(sc, reg, x) \
2331 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
2332 #define BGE_CLRBIT(sc, reg, x) \
2333 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
2335 #define PCI_SETBIT(dev, reg, x, s) \
2336 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
2337 #define PCI_CLRBIT(dev, reg, x, s) \
2338 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
2341 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
2342 * values are tuneable. They control the actual amount of buffers
2343 * allocated for the standard, mini and jumbo receive rings.
2346 #define BGE_SSLOTS 256
2347 #define BGE_MSLOTS 256
2348 #define BGE_JSLOTS 384
2350 #define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN)
2351 #define BGE_JLEN (BGE_JRAWLEN + (sizeof(uint64_t) - \
2352 (BGE_JRAWLEN % sizeof(uint64_t))))
2353 #define BGE_JPAGESZ PAGE_SIZE
2354 #define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ)
2355 #define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID)
2357 #define BGE_NSEG_JUMBO 4
2358 #define BGE_NSEG_NEW 32
2361 * Ring structures. Most of these reside in host memory and we tell
2362 * the NIC where they are via the ring control blocks. The exceptions
2363 * are the tx and command rings, which live in NIC memory and which
2364 * we access via the shared memory window.
2367 struct bge_ring_data {
2368 struct bge_rx_bd *bge_rx_std_ring;
2369 bus_addr_t bge_rx_std_ring_paddr;
2370 struct bge_extrx_bd *bge_rx_jumbo_ring;
2371 bus_addr_t bge_rx_jumbo_ring_paddr;
2372 struct bge_rx_bd *bge_rx_return_ring;
2373 bus_addr_t bge_rx_return_ring_paddr;
2374 struct bge_tx_bd *bge_tx_ring;
2375 bus_addr_t bge_tx_ring_paddr;
2376 struct bge_status_block *bge_status_block;
2377 bus_addr_t bge_status_block_paddr;
2378 struct bge_stats *bge_stats;
2379 bus_addr_t bge_stats_paddr;
2380 struct bge_gib bge_info;
2383 #define BGE_STD_RX_RING_SZ \
2384 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT)
2385 #define BGE_JUMBO_RX_RING_SZ \
2386 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT)
2387 #define BGE_TX_RING_SZ \
2388 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT)
2389 #define BGE_RX_RTN_RING_SZ(x) \
2390 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt)
2392 #define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block)
2394 #define BGE_STATS_SZ sizeof (struct bge_stats)
2397 * Mbuf pointers. We need these to keep track of the virtual addresses
2398 * of our mbuf chains since we can only convert from physical to virtual,
2399 * not the other way around.
2401 struct bge_chain_data {
2402 bus_dma_tag_t bge_parent_tag;
2403 bus_dma_tag_t bge_rx_std_ring_tag;
2404 bus_dma_tag_t bge_rx_jumbo_ring_tag;
2405 bus_dma_tag_t bge_rx_return_ring_tag;
2406 bus_dma_tag_t bge_tx_ring_tag;
2407 bus_dma_tag_t bge_status_tag;
2408 bus_dma_tag_t bge_stats_tag;
2409 bus_dma_tag_t bge_mtag; /* mbuf mapping tag */
2410 bus_dma_tag_t bge_mtag_jumbo; /* mbuf mapping tag */
2411 bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT];
2412 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT];
2413 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT];
2414 bus_dmamap_t bge_rx_std_ring_map;
2415 bus_dmamap_t bge_rx_jumbo_ring_map;
2416 bus_dmamap_t bge_tx_ring_map;
2417 bus_dmamap_t bge_rx_return_ring_map;
2418 bus_dmamap_t bge_status_map;
2419 bus_dmamap_t bge_stats_map;
2420 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT];
2421 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT];
2422 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
2425 struct bge_dmamap_arg {
2426 struct bge_softc *sc;
2427 bus_addr_t bge_busaddr;
2431 struct bge_tx_bd *bge_ring;
2434 #define BGE_HWREV_TIGON 0x01
2435 #define BGE_HWREV_TIGON_II 0x02
2436 #define BGE_TIMEOUT 100000
2437 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */
2439 struct bge_bcom_hack {
2444 #define ASF_ENABLE 1
2445 #define ASF_NEW_HANDSHAKE 2
2446 #define ASF_STACKUP 4
2449 struct ifnet *bge_ifp; /* interface info */
2452 device_t bge_miibus;
2453 bus_space_handle_t bge_bhandle;
2454 bus_space_tag_t bge_btag;
2456 struct resource *bge_irq;
2457 struct resource *bge_res;
2458 struct ifmedia bge_ifmedia; /* TBI media info */
2460 #define BGE_FLAG_TBI 0x00000001
2461 #define BGE_FLAG_JUMBO 0x00000002
2462 #define BGE_FLAG_EEPROM 0x00000004
2463 #define BGE_FLAG_MSI 0x00000100
2464 #define BGE_FLAG_PCIX 0x00000200
2465 #define BGE_FLAG_PCIE 0x00000400
2466 #define BGE_FLAG_5700_FAMILY 0x00001000
2467 #define BGE_FLAG_5705_PLUS 0x00002000
2468 #define BGE_FLAG_5714_FAMILY 0x00004000
2469 #define BGE_FLAG_575X_PLUS 0x00008000
2470 #define BGE_FLAG_RX_ALIGNBUG 0x00100000
2471 #define BGE_FLAG_NO_3LED 0x00200000
2472 #define BGE_FLAG_ADC_BUG 0x00400000
2473 #define BGE_FLAG_5704_A0_BUG 0x00800000
2474 #define BGE_FLAG_JITTER_BUG 0x01000000
2475 #define BGE_FLAG_BER_BUG 0x02000000
2476 #define BGE_FLAG_ADJUST_TRIM 0x04000000
2477 #define BGE_FLAG_CRC_BUG 0x08000000
2478 uint32_t bge_chipid;
2479 uint8_t bge_asicrev;
2480 uint8_t bge_chiprev;
2481 uint8_t bge_asf_mode;
2482 uint8_t bge_asf_count;
2483 struct bge_ring_data bge_ldata; /* rings */
2484 struct bge_chain_data bge_cdata; /* mbufs */
2485 uint16_t bge_tx_saved_considx;
2486 uint16_t bge_rx_saved_considx;
2487 uint16_t bge_ev_saved_considx;
2488 uint16_t bge_return_ring_cnt;
2489 uint16_t bge_std; /* current std ring head */
2490 uint16_t bge_jumbo; /* current jumo ring head */
2491 uint32_t bge_stat_ticks;
2492 uint32_t bge_rx_coal_ticks;
2493 uint32_t bge_tx_coal_ticks;
2494 uint32_t bge_tx_prodidx;
2495 uint32_t bge_rx_max_coal_bds;
2496 uint32_t bge_tx_max_coal_bds;
2497 uint32_t bge_tx_buf_ratio;
2500 int bge_link; /* link state */
2501 int bge_link_evt; /* pending link event */
2503 struct callout bge_stat_ch;
2504 uint32_t bge_rx_discards;
2505 uint32_t bge_tx_discards;
2506 uint32_t bge_tx_collisions;
2507 #ifdef DEVICE_POLLING
2509 #endif /* DEVICE_POLLING */
2512 #define BGE_LOCK_INIT(_sc, _name) \
2513 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
2514 #define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx)
2515 #define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED)
2516 #define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx)
2517 #define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx)