sys/dev/bhnd/bhnd_ids.h

   1 /*-
   2  * SPDX-License-Identifier: ISC
   3  *
   4  * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
   5  * Copyright (c) 1999-2015, Broadcom Corporation
   6  *
   7  * This file is derived from the bcmdevs.h header contributed by Broadcom
   8  * to Android's bcmdhd driver module, later revisions of bcmdevs.h distributed
   9  * with the dd-wrt project, and the hndsoc.h header distributed with Broadcom's
  10  * initial brcm80211 Linux driver release as contributed to the Linux staging
  11  * repository.
  12  *
  13  * Permission to use, copy, modify, and/or distribute this software for any
  14  * purpose with or without fee is hereby granted, provided that the above
  15  * copyright notice and this permission notice appear in all copies.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  18  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  19  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  21  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  22  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  23  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #ifndef _BHND_BHND_IDS_H_
  29 #define _BHND_BHND_IDS_H_
  30
  31 /*
  32  * JEDEC JEP-106 Core Vendor IDs
  33  *
  34  * These are the JEDEC JEP-106 manufacturer ID representions (with ARM's
  35  * non-standard 4-bit continutation code), as used in ARM's PrimeCell
  36  * identification registers, bcma(4) EROM core descriptors, etc.
  37  *
  38  * @note
  39  * Bus implementations that predate the adoption of ARM IP
  40  * will need to convert bus-specific vendor IDs to their BHND_MFGID
  41  * JEP-106 equivalents.
  42  *
  43  * @par ARM 4-bit Continuation Code
  44  *
  45  * BHND MFGIDs are encoded using ARM's non-standard 4-bit continuation code
  46  * format:
  47  *
  48  * @code{.unparsed}
  49  * [11:8     ][7:0   ]
  50  * [cont code][mfg id]
  51  * @endcode
  52  *
  53  * The 4-bit continuation code field specifies the number of JEP-106
  54  * continuation codes that prefix the manufacturer's ID code. In the case of
  55  * ARM's JEP-106 ID of `0x7F 0x7F 0x7F 0x7F 0x3B`, the four 0x7F continuations
  56  * are encoded as '4' in the 4-bit continuation code field (i.e. 0x43B).
  57  */
  58 #define BHND_MFGID_ARM          0x043b          /**< arm JEP-106 vendor id */
  59 #define BHND_MFGID_BCM          0x04bf          /**< broadcom JEP-106 vendor id */
  60 #define BHND_MFGID_MIPS         0x04a7          /**< mips JEP-106 vendor id */
  61 #define BHND_MFGID_INVALID      0x0000          /**< invalid JEP-106 vendor id */
  62
  63 /*
  64  * OCP (Open Core Protocol) Vendor IDs.
  65  *
  66  * OCP-IP assigned vendor codes are used by siba(4)
  67  */
  68 #define OCP_VENDOR_BCM          0x4243          /**< Broadcom OCP vendor id */
  69
  70
  71 /* PCI vendor IDs */
  72 #define PCI_VENDOR_ASUSTEK      0x1043
  73 #define PCI_VENDOR_EPIGRAM      0xfeda
  74 #define PCI_VENDOR_BROADCOM     0x14e4
  75 #define PCI_VENDOR_3COM         0x10b7
  76 #define PCI_VENDOR_NETGEAR      0x1385
  77 #define PCI_VENDOR_DIAMOND      0x1092
  78 #define PCI_VENDOR_INTEL        0x8086
  79 #define PCI_VENDOR_DELL         0x1028
  80 #define PCI_VENDOR_HP           0x103c
  81 #define PCI_VENDOR_HP_COMPAQ    0x0e11
  82 #define PCI_VENDOR_LINKSYS      0x1737
  83 #define PCI_VENDOR_MOTOROLA     0x1057
  84 #define PCI_VENDOR_APPLE        0x106b
  85 #define PCI_VENDOR_SI_IMAGE     0x1095          /* Silicon Image, used by Arasan SDIO Host */
  86 #define PCI_VENDOR_BUFFALO      0x1154          /* Buffalo vendor id */
  87 #define PCI_VENDOR_TI           0x104c          /* Texas Instruments */
  88 #define PCI_VENDOR_RICOH        0x1180          /* Ricoh */
  89 #define PCI_VENDOR_JMICRON      0x197b
  90
  91
  92 /* PCMCIA vendor IDs */
  93 #define PCMCIA_VENDOR_BROADCOM  0x02d0
  94
  95
  96 /* SDIO vendor IDs */
  97 #define SDIO_VENDOR_BROADCOM    0x00BF
  98
  99
 100 /* USB dongle VID/PIDs */
 101 #define USB_VID_BROADCOM        0x0a5c
 102 #define USB_PID_BCM4328         0xbd12
 103 #define USB_PID_BCM4322         0xbd13
 104 #define USB_PID_BCM4319         0xbd16
 105 #define USB_PID_BCM43236        0xbd17
 106 #define USB_PID_BCM4332         0xbd18
 107 #define USB_PID_BCM4330         0xbd19
 108 #define USB_PID_BCM4334         0xbd1a
 109 #define USB_PID_BCM43239        0xbd1b
 110 #define USB_PID_BCM4324         0xbd1c
 111 #define USB_PID_BCM4360         0xbd1d
 112 #define USB_PID_BCM43143        0xbd1e
 113 #define USB_PID_BCM43242        0xbd1f
 114 #define USB_PID_BCM43342        0xbd21
 115 #define USB_PID_BCM4335         0xbd20
 116 #define USB_PID_BCM4350         0xbd23
 117 #define USB_PID_BCM43341        0xbd22
 118
 119 #define USB_PID_BCM_DNGL_BDC    0x0bdc          /* BDC USB device controller IP? */
 120 #define USB_PID_BCM_DNGL_JTAG   0x4a44
 121
 122
 123 /* HW USB BLOCK [CPULESS USB] PIDs */
 124 #define USB_PID_CCM_HWUSB_43239 43239
 125
 126
 127 /* PCI Device IDs */
 128 #define PCI_DEVID_BCM4210               0x1072  /* never used */
 129 #define PCI_DEVID_BCM4230               0x1086  /* never used */
 130 #define PCI_DEVID_BCM4401_ENET          0x170c  /* 4401b0 production enet cards */
 131 #define PCI_DEVID_BCM3352               0x3352  /* bcm3352 device id */
 132 #define PCI_DEVID_BCM3360               0x3360  /* bcm3360 device id */
 133 #define PCI_DEVID_BCM4211               0x4211
 134 #define PCI_DEVID_BCM4231               0x4231
 135 #define PCI_DEVID_BCM4301               0x4301  /* 4031 802.11b */
 136 #define PCI_DEVID_BCM4303_D11B          0x4303  /* 4303 802.11b */
 137 #define PCI_DEVID_BCM4306               0x4306  /* 4306 802.11b/g */
 138 #define PCI_DEVID_BCM4307               0x4307  /* 4307 802.11b, 10/100 ethernet, V.92 modem */
 139 #define PCI_DEVID_BCM4311_D11G          0x4311  /* 4311 802.11b/g id */
 140 #define PCI_DEVID_BCM4311_D11DUAL       0x4312  /* 4311 802.11a/b/g id */
 141 #define PCI_DEVID_BCM4311_D11A          0x4313  /* 4311 802.11a id */
 142 #define PCI_DEVID_BCM4328_D11DUAL       0x4314  /* 4328/4312 802.11a/g id */
 143 #define PCI_DEVID_BCM4328_D11G          0x4315  /* 4328/4312 802.11g id */
 144 #define PCI_DEVID_BCM4328_D11A          0x4316  /* 4328/4312 802.11a id */
 145 #define PCI_DEVID_BCM4318_D11G          0x4318  /* 4318 802.11b/g id */
 146 #define PCI_DEVID_BCM4318_D11DUAL       0x4319  /* 4318 802.11a/b/g id */
 147 #define PCI_DEVID_BCM4318_D11A          0x431a  /* 4318 802.11a id */
 148 #define PCI_DEVID_BCM4325_D11DUAL       0x431b  /* 4325 802.11a/g id */
 149 #define PCI_DEVID_BCM4325_D11G          0x431c  /* 4325 802.11g id */
 150 #define PCI_DEVID_BCM4325_D11A          0x431d  /* 4325 802.11a id */
 151 #define PCI_DEVID_BCM4306_D11G          0x4320  /* 4306 802.11g */
 152 #define PCI_DEVID_BCM4306_D11A          0x4321  /* 4306 802.11a */
 153 #define PCI_DEVID_BCM4306_UART          0x4322  /* 4306 uart */
 154 #define PCI_DEVID_BCM4306_V90           0x4323  /* 4306 v90 codec */
 155 #define PCI_DEVID_BCM4306_D11DUAL       0x4324  /* 4306 dual A+B */
 156 #define PCI_DEVID_BCM4306_D11G_ID2      0x4325  /* BCM4306_D11G; INF w/loose binding war */
 157 #define PCI_DEVID_BCM4321_D11N          0x4328  /* 4321 802.11n dualband id */
 158 #define PCI_DEVID_BCM4321_D11N2G        0x4329  /* 4321 802.11n 2.4Ghz band id */
 159 #define PCI_DEVID_BCM4321_D11N5G        0x432a  /* 4321 802.11n 5Ghz band id */
 160 #define PCI_DEVID_BCM4322_D11N          0x432b  /* 4322 802.11n dualband device */
 161 #define PCI_DEVID_BCM4322_D11N2G        0x432c  /* 4322 802.11n 2.4GHz device */
 162 #define PCI_DEVID_BCM4322_D11N5G        0x432d  /* 4322 802.11n 5GHz device */
 163 #define PCI_DEVID_BCM4329_D11N          0x432e  /* 4329 802.11n dualband device */
 164 #define PCI_DEVID_BCM4329_D11N2G        0x432f  /* 4329 802.11n 2.4G device */
 165 #define PCI_DEVID_BCM4329_D11N5G        0x4330  /* 4329 802.11n 5G device */
 166 #define PCI_DEVID_BCM4315_D11DUAL       0x4334  /* 4315 802.11a/g id */
 167 #define PCI_DEVID_BCM4315_D11G          0x4335  /* 4315 802.11g id */
 168 #define PCI_DEVID_BCM4315_D11A          0x4336  /* 4315 802.11a id */
 169 #define PCI_DEVID_BCM4319_D11N          0x4337  /* 4319 802.11n dualband device */
 170 #define PCI_DEVID_BCM4319_D11N2G        0x4338  /* 4319 802.11n 2.4G device */
 171 #define PCI_DEVID_BCM4319_D11N5G        0x4339  /* 4319 802.11n 5G device */
 172 #define PCI_DEVID_BCM43231_D11N2G       0x4340  /* 43231 802.11n 2.4GHz device */
 173 #define PCI_DEVID_BCM43221_D11N2G       0x4341  /* 43221 802.11n 2.4GHz device */
 174 #define PCI_DEVID_BCM43222_D11N         0x4350  /* 43222 802.11n dualband device */
 175 #define PCI_DEVID_BCM43222_D11N2G       0x4351  /* 43222 802.11n 2.4GHz device */
 176 #define PCI_DEVID_BCM43222_D11N5G       0x4352  /* 43222 802.11n 5GHz device */
 177 #define PCI_DEVID_BCM43224_D11N         0x4353  /* 43224 802.11n dualband device */
 178 #define PCI_DEVID_BCM43224_D11N_ID_VEN1 0x0576  /* Vendor specific 43224 802.11n db device */
 179 #define PCI_DEVID_BCM43226_D11N         0x4354  /* 43226 802.11n dualband device */
 180 #define PCI_DEVID_BCM43236_D11N         0x4346  /* 43236 802.11n dualband device */
 181 #define PCI_DEVID_BCM43236_D11N2G       0x4347  /* 43236 802.11n 2.4GHz device */
 182 #define PCI_DEVID_BCM43236_D11N5G       0x4348  /* 43236 802.11n 5GHz device */
 183 #define PCI_DEVID_BCM43225_D11N2G       0x4357  /* 43225 802.11n 2.4GHz device */
 184 #define PCI_DEVID_BCM43421_D11N         0xA99D  /* 43421 802.11n dualband device */
 185 #define PCI_DEVID_BCM4313_D11N2G        0x4727  /* 4313 802.11n 2.4G device */
 186 #define PCI_DEVID_BCM4330_D11N          0x4360  /* 4330 802.11n dualband device */
 187 #define PCI_DEVID_BCM4330_D11N2G        0x4361  /* 4330 802.11n 2.4G device */
 188 #define PCI_DEVID_BCM4330_D11N5G        0x4362  /* 4330 802.11n 5G device */
 189 #define PCI_DEVID_BCM4336_D11N          0x4343  /* 4336 802.11n 2.4GHz device */
 190 #define PCI_DEVID_BCM6362_D11N          0x435f  /* 6362 802.11n dualband device */
 191 #define PCI_DEVID_BCM6362_D11N2G        0x433f  /* 6362 802.11n 2.4Ghz band id */
 192 #define PCI_DEVID_BCM6362_D11N5G        0x434f  /* 6362 802.11n 5Ghz band id */
 193 #define PCI_DEVID_BCM4331_D11N          0x4331  /* 4331 802.11n dualband id */
 194 #define PCI_DEVID_BCM4331_D11N2G        0x4332  /* 4331 802.11n 2.4Ghz band id */
 195 #define PCI_DEVID_BCM4331_D11N5G        0x4333  /* 4331 802.11n 5Ghz band id */
 196 #define PCI_DEVID_BCM43237_D11N         0x4355  /* 43237 802.11n dualband device */
 197 #define PCI_DEVID_BCM43237_D11N5G       0x4356  /* 43237 802.11n 5GHz device */
 198 #define PCI_DEVID_BCM43227_D11N2G       0x4358  /* 43228 802.11n 2.4GHz device */
 199 #define PCI_DEVID_BCM43228_D11N         0x4359  /* 43228 802.11n DualBand device */
 200 #define PCI_DEVID_BCM43228_D11N5G       0x435a  /* 43228 802.11n 5GHz device */
 201 #define PCI_DEVID_BCM43362_D11N         0x4363  /* 43362 802.11n 2.4GHz device */
 202 #define PCI_DEVID_BCM43239_D11N         0x4370  /* 43239 802.11n dualband device */
 203 #define PCI_DEVID_BCM4324_D11N          0x4374  /* 4324 802.11n dualband device */
 204 #define PCI_DEVID_BCM43217_D11N2G       0x43a9  /* 43217 802.11n 2.4GHz device */
 205 #define PCI_DEVID_BCM43131_D11N2G       0x43aa  /* 43131 802.11n 2.4GHz device */
 206 #define PCI_DEVID_BCM4314_D11N2G        0x4364  /* 4314 802.11n 2.4G device */
 207 #define PCI_DEVID_BCM43142_D11N2G       0x4365  /* 43142 802.11n 2.4G device */
 208 #define PCI_DEVID_BCM43143_D11N2G       0x4366  /* 43143 802.11n 2.4G device */
 209 #define PCI_DEVID_BCM4334_D11N          0x4380  /* 4334 802.11n dualband device */
 210 #define PCI_DEVID_BCM4334_D11N2G        0x4381  /* 4334 802.11n 2.4G device */
 211 #define PCI_DEVID_BCM4334_D11N5G        0x4382  /* 4334 802.11n 5G device */
 212 #define PCI_DEVID_BCM43342_D11N         0x4383  /* 43342 802.11n dualband device */
 213 #define PCI_DEVID_BCM43342_D11N2G       0x4384  /* 43342 802.11n 2.4G device */
 214 #define PCI_DEVID_BCM43342_D11N5G       0x4385  /* 43342 802.11n 5G device */
 215 #define PCI_DEVID_BCM43341_D11N         0x4386  /* 43341 802.11n dualband device */
 216 #define PCI_DEVID_BCM43341_D11N2G       0x4387  /* 43341 802.11n 2.4G device */
 217 #define PCI_DEVID_BCM43341_D11N5G       0x4388  /* 43341 802.11n 5G device */
 218 #define PCI_DEVID_BCM4360_D11AC         0x43a0
 219 #define PCI_DEVID_BCM4360_D11AC2G       0x43a1
 220 #define PCI_DEVID_BCM4360_D11AC5G       0x43a2
 221 #define PCI_DEVID_BCM4335_D11AC         0x43ae
 222 #define PCI_DEVID_BCM4335_D11AC2G       0x43af
 223 #define PCI_DEVID_BCM4335_D11AC5G       0x43b0
 224 #define PCI_DEVID_BCM4352_D11AC         0x43b1  /* 4352 802.11ac dualband device */
 225 #define PCI_DEVID_BCM4352_D11AC2G       0x43b2  /* 4352 802.11ac 2.4G device */
 226 #define PCI_DEVID_BCM4352_D11AC5G       0x43b3  /* 4352 802.11ac 5G device */
 227
 228 #define PCI_DEVID_PCIXX21_FLASHMEDIA0   0x8033  /* TI PCI xx21 Standard Host Controller */
 229 #define PCI_DEVID_PCIXX21_SDIOH0        0x8034  /* TI PCI xx21 Standard Host Controller */
 230
 231
 232 /* PCI Subsystem Vendor IDs */
 233 #define PCI_SUBVENDOR_BCM943228HMB      0x0607
 234 #define PCI_SUBVENDOR_BCM94313HMGBL     0x0608
 235 #define PCI_SUBVENDOR_BCM94313HMG       0x0609
 236 #define PCI_SUBVENDOR_BCM943142HM       0x0611
 237
 238
 239 /* PCI Subsystem Device IDs */
 240 #define PCI_SUBDEVID_BCM43143_D11N2G            0x4366  /* 43143 802.11n 2.4G device */
 241
 242 #define PCI_SUBDEVID_BCM43242_D11N              0x4367  /* 43242 802.11n dualband device */
 243 #define PCI_SUBDEVID_BCM43242_D11N2G            0x4368  /* 43242 802.11n 2.4G device */
 244 #define PCI_SUBDEVID_BCM43242_D11N5G            0x4369  /* 43242 802.11n 5G device */
 245
 246 #define PCI_SUBDEVID_BCM4350_D11AC              0x43a3
 247 #define PCI_SUBDEVID_BCM4350_D11AC2G            0x43a4
 248 #define PCI_SUBDEVID_BCM4350_D11AC5G            0x43a5
 249
 250 #define PCI_SUBDEVID_BCMGPRS_UART               0x4333  /* Uart id used by 4306/gprs card */
 251 #define PCI_SUBDEVID_BCMGPRS2_UART              0x4344  /* Uart id used by 4306/gprs card */
 252 #define PCI_SUBDEVID_BCM_FPGA_JTAGM             0x43f0  /* FPGA jtagm device id */
 253 #define PCI_SUBDEVID_BCM_JTAGM                  0x43f1  /* BCM jtagm device id */
 254 #define PCI_SUBDEVID_BCM_SDIOH_FPGA             0x43f2  /* sdio host fpga */
 255 #define PCI_SUBDEVID_BCM_SDIOH                  0x43f3  /* BCM sdio host id */
 256 #define PCI_SUBDEVID_BCM_SDIOD_FPGA             0x43f4  /* sdio device fpga */
 257 #define PCI_SUBDEVID_BCM_SPIH_FPGA              0x43f5  /* PCI SPI Host Controller FPGA */
 258 #define PCI_SUBDEVID_BCM_SPIH                   0x43f6  /* Synopsis SPI Host Controller */
 259 #define PCI_SUBDEVID_BCM_MIMO_FPGA              0x43f8  /* FPGA mimo minimacphy device id */
 260 #define PCI_SUBDEVID_BCM_JTAGM2                 0x43f9  /* PCI_SUBDEVID_BCM alternate jtagm device id */
 261 #define PCI_SUBDEVID_BCM_SDHCI_FPGA             0x43fa  /* Standard SDIO Host Controller FPGA */
 262 #define PCI_SUBDEVID_BCM4402_ENET               0x4402  /* 4402 enet */
 263 #define PCI_SUBDEVID_BCM4402_V90                0x4403  /* 4402 v90 codec */
 264 #define PCI_SUBDEVID_BCM4410                    0x4410  /* bcm44xx family pci iline */
 265 #define PCI_SUBDEVID_BCM4412                    0x4412  /* bcm44xx family pci enet */
 266 #define PCI_SUBDEVID_BCM4430                    0x4430  /* bcm44xx family cardbus iline */
 267 #define PCI_SUBDEVID_BCM4432                    0x4432  /* bcm44xx family cardbus enet */
 268 #define PCI_SUBDEVID_BCM4704_ENET               0x4706  /* 4704 enet (Use 47XX_ENET_ID instead!) */
 269 #define PCI_SUBDEVID_BCM4710                    0x4710  /* 4710 primary function 0 */
 270 #define PCI_SUBDEVID_BCM47XX_AUDIO              0x4711  /* 47xx audio codec */
 271 #define PCI_SUBDEVID_BCM47XX_V90                0x4712  /* 47xx v90 codec */
 272 #define PCI_SUBDEVID_BCM47XX_ENET               0x4713  /* 47xx enet */
 273 #define PCI_SUBDEVID_BCM47XX_EXT                0x4714  /* 47xx external i/f */
 274 #define PCI_SUBDEVID_BCM47XX_GMAC               0x4715  /* 47xx Unimac based GbE */
 275 #define PCI_SUBDEVID_BCM47XX_USBH               0x4716  /* 47xx usb host */
 276 #define PCI_SUBDEVID_BCM47XX_USBD               0x4717  /* 47xx usb device */
 277 #define PCI_SUBDEVID_BCM47XX_IPSEC              0x4718  /* 47xx ipsec */
 278 #define PCI_SUBDEVID_BCM47XX_ROBO               0x4719  /* 47xx/53xx roboswitch core */
 279 #define PCI_SUBDEVID_BCM47XX_USB20H             0x471a  /* 47xx usb 2.0 host */
 280 #define PCI_SUBDEVID_BCM47XX_USB20D             0x471b  /* 47xx usb 2.0 device */
 281 #define PCI_SUBDEVID_BCM47XX_ATA100             0x471d  /* 47xx parallel ATA */
 282 #define PCI_SUBDEVID_BCM47XX_SATAXOR            0x471e  /* 47xx serial ATA & XOR DMA */
 283 #define PCI_SUBDEVID_BCM47XX_GIGETH             0x471f  /* 47xx GbE (5700) */
 284 #define PCI_SUBDEVID_BCM4712_MIPS               0x4720  /* 4712 base devid */
 285 #define PCI_SUBDEVID_BCM4716                    0x4722  /* 4716 base devid */
 286 #define PCI_SUBDEVID_BCM47XX_USB30H             0x472a  /* 47xx usb 3.0 host */
 287 #define PCI_SUBDEVID_BCM47XX_USB30D             0x472b  /* 47xx usb 3.0 device */
 288 #define PCI_SUBDEVID_BCM47XX_SMBUS_EMU          0x47fe  /* 47xx emulated SMBus device */
 289 #define PCI_SUBDEVID_BCM47XX_XOR_EMU            0x47ff  /* 47xx emulated XOR engine */
 290 #define PCI_SUBDEVID_BCM_EPI41210               0xa0fa  /* bcm4210 */
 291 #define PCI_SUBDEVID_BCM_EPI41230               0xa10e  /* bcm4230 */
 292 #define PCI_SUBDEVID_BCM_JINVANI_SDIOH          0x4743  /* Jinvani SDIO Gold Host */
 293 #define PCI_SUBDEVID_BCM27XX_SDIOH              0x2702  /* PCI_SUBDEVID_BCM27xx Standard SDIO Host */
 294 #define PCI_SUBDEVID_BCM_PCIXX21_FLASHMEDIA     0x803b  /* TI PCI xx21 Standard Host Controller */
 295 #define PCI_SUBDEVID_BCM_PCIXX21_SDIOH          0x803c  /* TI PCI xx21 Standard Host Controller */
 296 #define PCI_SUBDEVID_BCM_R5C822_SDIOH           0x0822  /* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host */
 297 #define PCI_SUBDEVID_BCM_JMICRON_SDIOH          0x2381  /* JMicron Standard SDIO Host Controller */
 298
 299
 300 /* Broadcom ChipCommon Chip IDs */
 301 #define BHND_CHIPID_BCM4306             0x4306          /* 4306 chipcommon chipid */
 302 #define BHND_CHIPID_BCM4311             0x4311          /* 4311 PCIe 802.11a/b/g */
 303 #define BHND_CHIPID_BCM43111            43111           /* 43111 chipcommon chipid (OTP chipid) */
 304 #define BHND_CHIPID_BCM43112            43112           /* 43112 chipcommon chipid (OTP chipid) */
 305 #define BHND_CHIPID_BCM4312             0x4312          /* 4312 chipcommon chipid */
 306 #define BHND_CHIPID_BCM4313             0x4313          /* 4313 chip id */
 307 #define BHND_CHIPID_BCM43131            43131           /* 43131 chip id (OTP chipid) */
 308 #define BHND_CHIPID_BCM4315             0x4315          /* 4315 chip id */
 309 #define BHND_CHIPID_BCM4318             0x4318          /* 4318 chipcommon chipid */
 310 #define BHND_CHIPID_BCM4319             0x4319          /* 4319 chip id */
 311 #define BHND_CHIPID_BCM4320             0x4320          /* 4320 chipcommon chipid */
 312 #define BHND_CHIPID_BCM4321             0x4321          /* 4321 chipcommon chipid */
 313 #define BHND_CHIPID_BCM43217            43217           /* 43217 chip id (OTP chipid) */
 314 #define BHND_CHIPID_BCM4322             0x4322          /* 4322 chipcommon chipid */
 315 #define BHND_CHIPID_BCM43221            43221           /* 43221 chipcommon chipid (OTP chipid) */
 316 #define BHND_CHIPID_BCM43222            43222           /* 43222 chipcommon chipid */
 317 #define BHND_CHIPID_BCM43224            43224           /* 43224 chipcommon chipid */
 318 #define BHND_CHIPID_BCM43225            43225           /* 43225 chipcommon chipid */
 319 #define BHND_CHIPID_BCM43227            43227           /* 43227 chipcommon chipid */
 320 #define BHND_CHIPID_BCM43228            43228           /* 43228 chipcommon chipid */
 321 #define BHND_CHIPID_BCM43226            43226           /* 43226 chipcommon chipid */
 322 #define BHND_CHIPID_BCM43231            43231           /* 43231 chipcommon chipid (OTP chipid) */
 323 #define BHND_CHIPID_BCM43234            43234           /* 43234 chipcommon chipid */
 324 #define BHND_CHIPID_BCM43235            43235           /* 43235 chipcommon chipid */
 325 #define BHND_CHIPID_BCM43236            43236           /* 43236 chipcommon chipid */
 326 #define BHND_CHIPID_BCM43237            43237           /* 43237 chipcommon chipid */
 327 #define BHND_CHIPID_BCM43238            43238           /* 43238 chipcommon chipid */
 328 #define BHND_CHIPID_BCM43239            43239           /* 43239 chipcommon chipid */
 329 #define BHND_CHIPID_BCM43420            43420           /* 43222 chipcommon chipid (OTP, RBBU) */
 330 #define BHND_CHIPID_BCM43421            43421           /* 43224 chipcommon chipid (OTP, RBBU) */
 331 #define BHND_CHIPID_BCM43428            43428           /* 43228 chipcommon chipid (OTP, RBBU) */
 332 #define BHND_CHIPID_BCM43431            43431           /* 4331  chipcommon chipid (OTP, RBBU) */
 333 #define BHND_CHIPID_BCM43460            43460           /* 4360  chipcommon chipid (OTP, RBBU) */
 334 #define BHND_CHIPID_BCM43462            0xA9C6          /* 43462 chipcommon chipid */
 335 #define BHND_CHIPID_BCM4325             0x4325          /* 4325 chip id */
 336 #define BHND_CHIPID_BCM4328             0x4328          /* 4328 chip id */
 337 #define BHND_CHIPID_BCM4329             0x4329          /* 4329 chipcommon chipid */
 338 #define BHND_CHIPID_BCM4331             0x4331          /* 4331 chipcommon chipid */
 339 #define BHND_CHIPID_BCM4336             0x4336          /* 4336 chipcommon chipid */
 340 #define BHND_CHIPID_BCM43362            43362           /* 43362 chipcommon chipid */
 341 #define BHND_CHIPID_BCM4330             0x4330          /* 4330 chipcommon chipid */
 342 #define BHND_CHIPID_BCM6362             0x6362          /* 6362 chipcommon chipid */
 343 #define BHND_CHIPID_BCM4314             0x4314          /* 4314 chipcommon chipid */
 344 #define BHND_CHIPID_BCM43142            43142           /* 43142 chipcommon chipid */
 345 #define BHND_CHIPID_BCM43143            43143           /* 43143 chipcommon chipid */
 346 #define BHND_CHIPID_BCM4324             0x4324          /* 4324 chipcommon chipid */
 347 #define BHND_CHIPID_BCM43242            43242           /* 43242 chipcommon chipid */
 348 #define BHND_CHIPID_BCM43243            43243           /* 43243 chipcommon chipid */
 349 #define BHND_CHIPID_BCM4334             0x4334          /* 4334 chipcommon chipid */
 350 #define BHND_CHIPID_BCM4335             0x4335          /* 4335 chipcommon chipid */
 351 #define BHND_CHIPID_BCM4360             0x4360          /* 4360 chipcommon chipid */
 352 #define BHND_CHIPID_BCM43602            0xaa52          /* 43602 chipcommon chipid */
 353 #define BHND_CHIPID_BCM4352             0x4352          /* 4352 chipcommon chipid */
 354 #define BHND_CHIPID_BCM43526            0xAA06
 355 #define BHND_CHIPID_BCM43341            43341           /* 43341 chipcommon chipid */
 356 #define BHND_CHIPID_BCM43342            43342           /* 43342 chipcommon chipid */
 357 #define BHND_CHIPID_BCM4335             0x4335
 358 #define BHND_CHIPID_BCM4350             0x4350          /* 4350 chipcommon chipid */
 359
 360 #define BHND_CHIPID_BCM4342             4342            /* 4342 chipcommon chipid (OTP, RBBU) */
 361 #define BHND_CHIPID_BCM4402             0x4402          /* 4402 chipid */
 362 #define BHND_CHIPID_BCM4704             0x4704          /* 4704 chipcommon chipid */
 363 #define BHND_CHIPID_BCM4706             0x5300          /* 4706 chipcommon chipid */
 364 #define BHND_CHIPID_BCM4707             53010           /* 4707 chipcommon chipid */
 365 #define BHND_CHIPID_BCM53018            53018           /* 53018 chipcommon chipid */
 366 #define BHND_CHIPID_IS_BCM4707(chipid) \
 367         (((chipid) == BHND_CHIPID_BCM4707) || \
 368         ((chipid) == BHND_CHIPID_BCM53018))
 369 #define BHND_CHIPID_BCM4710             0x4710          /* 4710 chipid */
 370 #define BHND_CHIPID_BCM4712             0x4712          /* 4712 chipcommon chipid */
 371 #define BHND_CHIPID_BCM4716             0x4716          /* 4716 chipcommon chipid */
 372 #define BHND_CHIPID_BCM47162            47162           /* 47162 chipcommon chipid */
 373 #define BHND_CHIPID_BCM4748             0x4748          /* 4716 chipcommon chipid (OTP, RBBU) */
 374 #define BHND_CHIPID_BCM4749             0x4749          /* 5357 chipcommon chipid (OTP, RBBU) */
 375 #define BHND_CHIPID_BCM4785             0x4785          /* 4785 chipcommon chipid */
 376 #define BHND_CHIPID_BCM5350             0x5350          /* 5350 chipcommon chipid */
 377 #define BHND_CHIPID_BCM5352             0x5352          /* 5352 chipcommon chipid */
 378 #define BHND_CHIPID_BCM5354             0x5354          /* 5354 chipcommon chipid */
 379 #define BHND_CHIPID_BCM5365             0x5365          /* 5365 chipcommon chipid */
 380 #define BHND_CHIPID_BCM5356             0x5356          /* 5356 chipcommon chipid */
 381 #define BHND_CHIPID_BCM5357             0x5357          /* 5357 chipcommon chipid */
 382 #define BHND_CHIPID_BCM53572            53572           /* 53572 chipcommon chipid */
 383
 384
 385 /* Broadcom ChipCommon Package IDs */
 386 #define BHND_PKGID_BCM4303              2               /* 4303 package id */
 387 #define BHND_PKGID_BCM4309              1               /* 4309 package id */
 388 #define BHND_PKGID_BCM4712LARGE         0               /* 340pin 4712 package id */
 389 #define BHND_PKGID_BCM4712SMALL         1               /* 200pin 4712 package id */
 390 #define BHND_PKGID_BCM4712MID           2               /* 225pin 4712 package id */
 391 #define BHND_PKGID_BCM4328USBD11G       2               /* 4328 802.11g USB package id */
 392 #define BHND_PKGID_BCM4328USBDUAL       3               /* 4328 802.11a/g USB package id */
 393 #define BHND_PKGID_BCM4328SDIOD11G      4               /* 4328 802.11g SDIO package id */
 394 #define BHND_PKGID_BCM4328SDIODUAL      5               /* 4328 802.11a/g SDIO package id */
 395 #define BHND_PKGID_BCM4329_289PIN       0               /* 4329 289-pin package id */
 396 #define BHND_PKGID_BCM4329_182PIN       1               /* 4329N 182-pin package id */
 397 #define BHND_PKGID_BCM5354E             1               /* 5354E package id */
 398 #define BHND_PKGID_BCM4716              8               /* 4716 package id */
 399 #define BHND_PKGID_BCM4717              9               /* 4717 package id */
 400 #define BHND_PKGID_BCM4718              10              /* 4718 package id */
 401 #define BHND_PKGID_BCM5356_NONMODE      1               /* 5356 package without nmode suppport */
 402 #define BHND_PKGID_BCM5358U             8               /* 5358U package id */
 403 #define BHND_PKGID_BCM5358              9               /* 5358 package id */
 404 #define BHND_PKGID_BCM47186             10              /* 47186 package id */
 405 #define BHND_PKGID_BCM5357              11              /* 5357 package id */
 406 #define BHND_PKGID_BCM5356U             12              /* 5356U package id */
 407 #define BHND_PKGID_BCM53572             8               /* 53572 package id */
 408 #define BHND_PKGID_BCM5357C0            8               /* 5357c0 package id (the same as 53572) */
 409 #define BHND_PKGID_BCM47188             9               /* 47188 package id */
 410 #define BHND_PKGID_BCM5358C0            0xa             /* 5358c0 package id */
 411 #define BHND_PKGID_BCM5356C0            0xb             /* 5356c0 package id */
 412 #define BHND_PKGID_BCM4331TT            8               /* 4331 12x12 package id */
 413 #define BHND_PKGID_BCM4331TN            9               /* 4331 12x9 package id */
 414 #define BHND_PKGID_BCM4331TNA0          0xb             /* 4331 12x9 package id */
 415 #define BHND_PKGID_BCM4706L             1               /* 4706L package id */
 416
 417 #define BHND_PKGID_HDLSIM5350           1               /* HDL simulator package id for a 5350 */
 418 #define BHND_PKGID_HDLSIM               14              /* HDL simulator package id */
 419 #define BHND_PKGID_HWSIM                15              /* Hardware simulator package id */
 420 #define BHND_PKGID_BCM43224_FAB_CSM     0x8             /* the chip is manufactured by CSM */
 421 #define BHND_PKGID_BCM43224_FAB_SMIC    0xa             /* the chip is manufactured by SMIC */
 422 #define BHND_PKGID_BCM4336_WLBGA        0x8
 423 #define BHND_PKGID_BCM4330_WLBGA        0x0
 424 #define BHND_PKGID_BCM4314PCIE_ARM      (8 | 0)         /* 4314 QFN PCI package id, bit 3 tie high */
 425 #define BHND_PKGID_BCM4314SDIO          (8 | 1)         /* 4314 QFN SDIO package id */
 426 #define BHND_PKGID_BCM4314PCIE          (8 | 2)         /* 4314 QFN PCI (ARM-less) package id */
 427 #define BHND_PKGID_BCM4314SDIO_ARM      (8 | 3)         /* 4314 QFN SDIO (ARM-less) package id */
 428 #define BHND_PKGID_BCM4314SDIO_FPBGA    (8 | 4)         /* 4314 FpBGA SDIO package id */
 429 #define BHND_PKGID_BCM4314DEV           (8 | 6)         /* 4314 Development package id */
 430
 431 #define BHND_PKGID_BCM4707              1               /* 4707 package id */
 432 #define BHND_PKGID_BCM4708              2               /* 4708 package id */
 433 #define BHND_PKGID_BCM4709              0               /* 4709 package id */
 434
 435 #define BHND_PKGID_BCM4335_WLCSP        (0x0)           /* WLCSP Module/Mobile SDIO/HSIC. */
 436 #define BHND_PKGID_BCM4335_FCBGA        (0x1)           /* FCBGA PC/Embedded/Media PCIE/SDIO */
 437 #define BHND_PKGID_BCM4335_WLBGA        (0x2)           /* WLBGA COB/Mobile SDIO/HSIC. */
 438 #define BHND_PKGID_BCM4335_FCBGAD       (0x3)           /* FCBGA Debug Debug/Dev All if's. */
 439 #define BHND_PKGID_PKG_MASK_BCM4335     (0x3)
 440
 441 /* Broadcom Core IDs */
 442 #define BHND_COREID_INVALID             0x700           /* Invalid coreid */
 443 #define BHND_COREID_CC                  0x800           /* chipcommon core */
 444 #define BHND_COREID_ILINE20             0x801           /* iline20 core */
 445 #define BHND_COREID_SRAM                0x802           /* sram core */
 446 #define BHND_COREID_SDRAM               0x803           /* sdram core */
 447 #define BHND_COREID_PCI                 0x804           /* pci core */
 448 #define BHND_COREID_MIPS                0x805           /* mips core */
 449 #define BHND_COREID_ENET                0x806           /* enet mac core */
 450 #define BHND_COREID_V90_CODEC           0x807           /* v90 codec core */
 451 #define BHND_COREID_USB                 0x808           /* usb 1.1 host/device core */
 452 #define BHND_COREID_ADSL                0x809           /* ADSL core */
 453 #define BHND_COREID_ILINE100            0x80a           /* iline100 core */
 454 #define BHND_COREID_IPSEC               0x80b           /* ipsec core */
 455 #define BHND_COREID_UTOPIA              0x80c           /* utopia core */
 456 #define BHND_COREID_PCMCIA              0x80d           /* pcmcia core */
 457 #define BHND_COREID_SOCRAM              0x80e           /* internal memory core */
 458 #define BHND_COREID_MEMC                0x80f           /* memc sdram core */
 459 #define BHND_COREID_OFDM                0x810           /* OFDM phy core */
 460 #define BHND_COREID_EXTIF               0x811           /* external interface core */
 461 #define BHND_COREID_D11                 0x812           /* 802.11 MAC core */
 462 #define BHND_COREID_APHY                0x813           /* 802.11a phy core */
 463 #define BHND_COREID_BPHY                0x814           /* 802.11b phy core */
 464 #define BHND_COREID_GPHY                0x815           /* 802.11g phy core */
 465 #define BHND_COREID_MIPS33              0x816           /* mips3302 core */
 466 #define BHND_COREID_USB11H              0x817           /* usb 1.1 host core */
 467 #define BHND_COREID_USB11D              0x818           /* usb 1.1 device core */
 468 #define BHND_COREID_USB20H              0x819           /* usb 2.0 host core */
 469 #define BHND_COREID_USB20D              0x81a           /* usb 2.0 device core */
 470 #define BHND_COREID_SDIOH               0x81b           /* sdio host core */
 471 #define BHND_COREID_ROBO                0x81c           /* roboswitch core */
 472 #define BHND_COREID_ATA100              0x81d           /* parallel ATA core */
 473 #define BHND_COREID_SATAXOR             0x81e           /* serial ATA & XOR DMA core */
 474 #define BHND_COREID_GIGETH              0x81f           /* gigabit ethernet core */
 475 #define BHND_COREID_PCIE                0x820           /* pci express core */
 476 #define BHND_COREID_NPHY                0x821           /* 802.11n 2x2 phy core */
 477 #define BHND_COREID_SRAMC               0x822           /* SRAM controller core */
 478 #define BHND_COREID_MINIMAC             0x823           /* MINI MAC/phy core */
 479 #define BHND_COREID_ARM11               0x824           /* ARM 1176 core */
 480 #define BHND_COREID_ARM7S               0x825           /* ARM7tdmi-s core */
 481 #define BHND_COREID_LPPHY               0x826           /* 802.11a/b/g phy core */
 482 #define BHND_COREID_PMU                 0x827           /* PMU core */
 483 #define BHND_COREID_SSNPHY              0x828           /* 802.11n single-stream phy core */
 484 #define BHND_COREID_SDIOD               0x829           /* SDIO device core */
 485 #define BHND_COREID_ARMCM3              0x82a           /* ARM Cortex M3 core */
 486 #define BHND_COREID_HTPHY               0x82b           /* 802.11n 4x4 phy core */
 487 #define BHND_COREID_MIPS74K             0x82c           /* mips 74k core */
 488 #define BHND_COREID_GMAC                0x82d           /* Gigabit MAC core */
 489 #define BHND_COREID_DMEMC               0x82e           /* DDR1/2 memory controller core */
 490 #define BHND_COREID_PCIERC              0x82f           /* PCIE Root Complex core */
 491 #define BHND_COREID_OCP                 0x830           /* OCP2OCP bridge core */
 492 #define BHND_COREID_SC                  0x831           /* shared common core */
 493 #define BHND_COREID_AHB                 0x832           /* OCP2AHB bridge core */
 494 #define BHND_COREID_SPIH                0x833           /* SPI host core */
 495 #define BHND_COREID_I2S                 0x834           /* I2S core */
 496 #define BHND_COREID_DMEMS               0x835           /* SDR/DDR1 memory controller core */
 497 #define BHND_COREID_UBUS_SHIM           0x837           /* SHIM component in ubus/6362 */
 498 #define BHND_COREID_PCIE2               0x83c           /* pci express (gen2) core */
 499 /* ARM/AMBA Core IDs */
 500 #define BHND_COREID_APB_BRIDGE          0x135           /* BP135 AMBA AXI-APB bridge */
 501 #define BHND_COREID_PL301               0x301           /* PL301 AMBA AXI Interconnect */
 502 #define BHND_COREID_EROM                0x366           /* Enumeration ROM */
 503 #define BHND_COREID_OOB_ROUTER          0x367           /* OOB router core ID */
 504 #define BHND_COREID_AXI_UNMAPPED        0xfff           /* AXI "Default Slave"; maps all unused address
 505                                                          * ranges, returning DECERR on read or write. */
 506 /* Northstar Plus and BCM4706 Core IDs */
 507 #define BHND_COREID_4706_CC             0x500           /* chipcommon core */
 508 #define BHND_COREID_NS_PCIE2            0x501           /* pci express (gen2) core */
 509 #define BHND_COREID_NS_DMA              0x502           /* dma core */
 510 #define BHND_COREID_NS_SDIO             0x503           /* sdio host core */
 511 #define BHND_COREID_NS_USB20H           0x504           /* usb 2.0 host core */
 512 #define BHND_COREID_NS_USB30H           0x505           /* usb 3.0 host core */
 513 #define BHND_COREID_NS_A9JTAG           0x506           /* ARM Cortex A9 JTAG core */
 514 #define BHND_COREID_NS_DDR23_MEMC       0x507           /* DDR2/3 cadence/denali memory controller core () */
 515 #define BHND_COREID_NS_ROM              0x508           /* device ROM core */
 516 #define BHND_COREID_NS_NAND             0x509           /* NAND flash controller core */
 517 #define BHND_COREID_NS_QSPI             0x50a           /* QSPI flash controller core */
 518 #define BHND_COREID_NS_CC_B             0x50b           /* chipcommon `b' (auxiliary) core */
 519 #define BHND_COREID_4706_SOCRAM         0x50e           /* internal memory core */
 520 #define BHND_COREID_IHOST_ARMCA9        0x510           /* ARM Cortex A9 core */
 521 #define BHND_COREID_4706_GMAC_CMN       0x5dc           /* Gigabit MAC common core */
 522 #define BHND_COREID_4706_GMAC           0x52d           /* Gigabit MAC core */
 523 #define BHND_COREID_AMEMC               0x52e           /* DDR1/2 cadence/denali memory controller core */
 524
 525
 526
 527 /* ARM PrimeCell Peripherial IDs. These were derived from inspection of the
 528  * PrimeCell-compatible BCM4331 cores, but due to lack of documentation, the
 529  * surmised core name/description may be incorrect. */
 530 #define BHND_PRIMEID_EROM               0x364           /* Enumeration ROM's primecell ID */
 531 #define BHND_PRIMEID_SWRAP              0x368           /* PL368 Device Management Interface (Slave) */
 532 #define BHND_PRIMEID_MWRAP              0x369           /* PL369 Device Management Interface (Master) */
 533
 534 /* Core HW Revision Numbers */
 535 #define BHND_HWREV_INVALID              0xFF            /* Invalid hardware revision ID */
 536
 537 /* Chip Types */
 538 #define BHND_CHIPTYPE_SIBA              0               /**< siba(4) interconnect */
 539 #define BHND_CHIPTYPE_BCMA              1               /**< bcma(4) interconnect */
 540 #define BHND_CHIPTYPE_UBUS              2               /**< ubus interconnect found in bcm63xx devices */
 541 #define BHND_CHIPTYPE_BCMA_ALT          3               /**< bcma(4) interconnect */
 542
 543 /** Evaluates to true if @p _type is a BCMA or BCMA-compatible interconenct */
 544 #define BHND_CHIPTYPE_IS_BCMA_COMPATIBLE(_type) \
 545         ((_type) == BHND_CHIPTYPE_BCMA ||       \
 546          (_type) == BHND_CHIPTYPE_BCMA_ALT ||   \
 547          (_type) == BHND_CHIPTYPE_UBUS)
 548
 549 /** Evaluates to true if @p _type uses a BCMA EROM table */
 550 #define BHND_CHIPTYPE_HAS_EROM(_type)           \
 551         BHND_CHIPTYPE_IS_BCMA_COMPATIBLE(_type)
 552
 553 /* Boardflags */
 554 #define BHND_BFL_BTC2WIRE               0x00000001      /* old 2wire Bluetooth coexistence, OBSOLETE */
 555 #define BHND_BFL_BTCOEX                 0x00000001      /* Board supports BTCOEX */
 556 #define BHND_BFL_PACTRL                 0x00000002      /* Board has gpio 9 controlling the PA */
 557 #define BHND_BFL_AIRLINEMODE            0x00000004      /* Board implements gpio 13 radio disable indication, UNUSED */
 558 #define BHND_BFL_ADCDIV                 0x00000008      /* Board has the rssi ADC divider */
 559 #define BHND_BFL_DIS_256QAM             0x00000008
 560 #define BHND_BFL_ENETROBO               0x00000010      /* Board has robo switch or core */
 561 #define BHND_BFL_NOPLLDOWN              0x00000020      /* Not ok to power down the chip pll and oscillator */
 562 #define BHND_BFL_CCKHIPWR               0x00000040      /* Can do high-power CCK transmission */
 563 #define BHND_BFL_ENETADM                0x00000080      /* Board has ADMtek switch */
 564 #define BHND_BFL_ENETVLAN               0x00000100      /* Board has VLAN capability */
 565 #define BHND_BFL_LTECOEX                0x00000200      /* Board has LTE coex capability */
 566 #define BHND_BFL_NOPCI                  0x00000400      /* Board leaves PCI floating */
 567 #define BHND_BFL_FEM                    0x00000800      /* Board supports the Front End Module */
 568 #define BHND_BFL_EXTLNA                 0x00001000      /* Board has an external LNA in 2.4GHz band */
 569 #define BHND_BFL_HGPA                   0x00002000      /* Board has a high gain PA */
 570 #define BHND_BFL_BTC2WIRE_ALTGPIO       0x00004000
 571 /* Board's BTC 2wire is in the alternate gpios OBSLETE */
 572 #define BHND_BFL_ALTIQ                  0x00008000      /* Alternate I/Q settings */
 573 #define BHND_BFL_NOPA                   0x00010000      /* Board has no PA */
 574 #define BHND_BFL_RSSIINV                0x00020000      /* Board's RSSI uses positive slope(not TSSI) */
 575 #define BHND_BFL_PAREF                  0x00040000      /* Board uses the PARef LDO */
 576 #define BHND_BFL_3TSWITCH               0x00080000      /* Board uses a triple throw switch shared with BT */
 577 #define BHND_BFL_PHASESHIFT             0x00100000      /* Board can support phase shifter */
 578 #define BHND_BFL_BUCKBOOST              0x00200000      /* Power topology uses BUCKBOOST */
 579 #define BHND_BFL_FEM_BT                 0x00400000      /* Board has FEM and switch to share antenna w/ BT */
 580 #define BHND_BFL_RXCHAIN_OFF_BT         0x00400000      /* one rxchain is to be shut off when BT is active */
 581 #define BHND_BFL_NOCBUCK                0x00800000      /* Power topology doesn't use CBUCK */
 582 #define BHND_BFL_CCKFAVOREVM            0x01000000      /* Favor CCK EVM over spectral mask */
 583 #define BHND_BFL_PALDO                  0x02000000      /* Power topology uses PALDO */
 584 #define BHND_BFL_LNLDO2_2P5             0x04000000      /* Select 2.5V as LNLDO2 output voltage */
 585 #define BHND_BFL_FASTPWR                0x08000000
 586 #define BHND_BFL_UCPWRCTL_MININDX       0x08000000      /* Enforce min power index to avoid FEM damage */
 587 #define BHND_BFL_EXTLNA_5GHZ            0x10000000      /* Board has an external LNA in 5GHz band */
 588 #define BHND_BFL_TRSW_1BY2              0x20000000      /* Board has 2 TRSW's in 1by2 designs */
 589 #define BHND_BFL_GAINBOOSTA01           0x20000000      /* 5g Gainboost for core0 and core1 */
 590 #define BHND_BFL_LO_TRSW_R_5GHZ         0x40000000      /* In 5G do not throw TRSW to T for clipLO gain */
 591 #define BHND_BFL_ELNA_GAINDEF           0x80000000      /* Backoff InitGain based on elna_2g/5g field
 592                                                          * when this flag is set
 593                                                          */
 594 #define BHND_BFL_EXTLNA_TX              0x20000000      /* Temp boardflag to indicate to */
 595
 596
 597 /* Boardflags2 */
 598 #define BHND_BFL2_RXBB_INT_REG_DIS      0x00000001      /* Board has an external rxbb regulator */
 599 #define BHND_BFL2_APLL_WAR              0x00000002      /* Flag to implement alternative A-band PLL settings */
 600 #define BHND_BFL2_TXPWRCTRL_EN          0x00000004      /* Board permits enabling TX Power Control */
 601 #define BHND_BFL2_2X4_DIV               0x00000008      /* Board supports the 2X4 diversity switch */
 602 #define BHND_BFL2_5G_PWRGAIN            0x00000010      /* Board supports 5G band power gain */
 603 #define BHND_BFL2_PCIEWAR_OVR           0x00000020      /* Board overrides ASPM and Clkreq settings */
 604 #define BHND_BFL2_CAESERS_BRD           0x00000040      /* Board is Caesers brd (unused by sw) */
 605 #define BHND_BFL2_BTC3WIRE              0x00000080      /* Board support legacy 3 wire or 4 wire */
 606 #define BHND_BFL2_BTCLEGACY             0x00000080      /* Board support legacy 3/4 wire, to replace
 607                                                          * BHND_BFL2_BTC3WIRE
 608                                                          */
 609 #define BHND_BFL2_SKWRKFEM_BRD          0x00000100      /* 4321mcm93 board uses Skyworks FEM */
 610 #define BHND_BFL2_SPUR_WAR              0x00000200      /* Board has a WAR for clock-harmonic spurs */
 611 #define BHND_BFL2_GPLL_WAR              0x00000400      /* Flag to narrow G-band PLL loop b/w */
 612 #define BHND_BFL2_TRISTATE_LED          0x00000800      /* Tri-state the LED */
 613 #define BHND_BFL2_SINGLEANT_CCK         0x00001000      /* Tx CCK pkts on Ant 0 only */
 614 #define BHND_BFL2_2G_SPUR_WAR           0x00002000      /* WAR to reduce and avoid clock-harmonic spurs in 2G */
 615 #define BHND_BFL2_BPHY_ALL_TXCORES      0x00004000      /* Transmit bphy frames using all tx cores */
 616 #define BHND_BFL2_FCC_BANDEDGE_WAR      0x00008000      /* Activates WAR to improve FCC bandedge performance */
 617 #define BHND_BFL2_GPLL_WAR2             0x00010000      /* Flag to widen G-band PLL loop b/w */
 618 #define BHND_BFL2_IPALVLSHIFT_3P3       0x00020000
 619 #define BHND_BFL2_INTERNDET_TXIQCAL     0x00040000      /* Use internal envelope detector for TX IQCAL */
 620 #define BHND_BFL2_XTALBUFOUTEN          0x00080000      /* Keep the buffered Xtal output from radio on */
 621                                                         /* Most drivers will turn it off without this flag */
 622                                                         /* to save power. */
 623
 624 #define BHND_BFL2_ANAPACTRL_2G          0x00100000      /* 2G ext PAs are controlled by analog PA ctrl lines */
 625 #define BHND_BFL2_ANAPACTRL_5G          0x00200000      /* 5G ext PAs are controlled by analog PA ctrl lines */
 626 #define BHND_BFL2_ELNACTRL_TRSW_2G      0x00400000      /* AZW4329: 2G gmode_elna_gain controls TR Switch */
 627 #define BHND_BFL2_BT_SHARE_ANT0         0x00800000      /* WLAN/BT share antenna 0 */
 628 #define BHND_BFL2_BT_SHARE_BM_BIT0      0x00800000      /* bit 0 of WLAN/BT shared core bitmap */
 629 #define BHND_BFL2_TEMPSENSE_HIGHER      0x01000000      /* The tempsense threshold can sustain higher value
 630                                                          * than programmed. The exact delta is decided by
 631                                                          * driver per chip/boardtype. This can be used
 632                                                          * when tempsense qualification happens after shipment
 633                                                          */
 634 #define BHND_BFL2_BTC3WIREONLY          0x02000000      /* standard 3 wire btc only.  4 wire not supported */
 635 #define BHND_BFL2_PWR_NOMINAL           0x04000000      /* 0: power reduction on, 1: no power reduction */
 636 #define BHND_BFL2_EXTLNA_PWRSAVE        0x08000000      /* boardflag to enable ucode to apply power save
 637                                                          * ucode control of eLNA during Tx */
 638 #define BHND_BFL2_4313_RADIOREG         0x10000000
 639                                                         /*  board rework */
 640 #define BHND_BFL2_DYNAMIC_VMID          0x10000000      /* boardflag to enable dynamic Vmid idle TSSI CAL */
 641 #define BHND_BFL2_SDR_EN                0x20000000      /* SDR enabled or disabled */
 642 #define BHND_BFL2_LNA1BYPFORTR2G        0x40000000      /* acphy, enable lna1 bypass for clip gain, 2g */
 643 #define BHND_BFL2_LNA1BYPFORTR5G        0x80000000      /* acphy, enable lna1 bypass for clip gain, 5g */
 644
 645
 646 /* SROM 11 - 11ac boardflag definitions */
 647 #define BHND_BFL_SROM11_BTCOEX          0x00000001      /* Board supports BTCOEX */
 648 #define BHND_BFL_SROM11_WLAN_BT_SH_XTL  0x00000002      /* bluetooth and wlan share same crystal */
 649 #define BHND_BFL_SROM11_EXTLNA          0x00001000      /* Board has an external LNA in 2.4GHz band */
 650 #define BHND_BFL_SROM11_EXTLNA_5GHZ     0x10000000      /* Board has an external LNA in 5GHz band */
 651 #define BHND_BFL_SROM11_GAINBOOSTA01    0x20000000      /* 5g Gainboost for core0 and core1 */
 652 #define BHND_BFL2_SROM11_APLL_WAR       0x00000002      /* Flag to implement alternative A-band PLL settings */
 653 #define BHND_BFL2_SROM11_ANAPACTRL_2G   0x00100000      /* 2G ext PAs are ctrl-ed by analog PA ctrl lines */
 654 #define BHND_BFL2_SROM11_ANAPACTRL_5G   0x00200000      /* 5G ext PAs are ctrl-ed by analog PA ctrl lines */
 655
 656
 657 /* Boardflags3 */
 658 #define BHND_BFL3_FEMCTRL_SUB                   0x00000007      /* acphy, subrevs of femctrl on top of srom_femctrl */
 659 #define BHND_BFL3_RCAL_WAR                      0x00000008      /* acphy, rcal war active on this board (4335a0) */
 660 #define BHND_BFL3_TXGAINTBLID                   0x00000070      /* acphy, txgain table id */
 661 #define BHND_BFL3_TXGAINTBLID_SHIFT             0x4             /* acphy, txgain table id shift bit */
 662 #define BHND_BFL3_TSSI_DIV_WAR                  0x00000080      /* acphy, Separate paparam for 20/40/80 */
 663 #define BHND_BFL3_TSSI_DIV_WAR_SHIFT            0x7             /* acphy, Separate paparam for 20/40/80 shift bit */
 664 #define BHND_BFL3_FEMTBL_FROM_NVRAM             0x00000100      /* acphy, femctrl table is read from nvram */
 665 #define BHND_BFL3_FEMTBL_FROM_NVRAM_SHIFT       0x8             /* acphy, femctrl table is read from nvram */
 666 #define BHND_BFL3_AGC_CFG_2G                    0x00000200      /* acphy, gain control configuration for 2G */
 667 #define BHND_BFL3_AGC_CFG_5G                    0x00000400      /* acphy, gain control configuration for 5G */
 668 #define BHND_BFL3_PPR_BIT_EXT                   0x00000800      /* acphy, bit position for 1bit extension for ppr */
 669 #define BHND_BFL3_PPR_BIT_EXT_SHIFT             11              /* acphy, bit shift for 1bit extension for ppr */
 670 #define BHND_BFL3_BBPLL_SPR_MODE_DIS            0x00001000      /* acphy, disables bbpll spur modes */
 671 #define BHND_BFL3_RCAL_OTP_VAL_EN               0x00002000      /* acphy, to read rcal_trim value from otp */
 672 #define BHND_BFL3_2GTXGAINTBL_BLANK             0x00004000      /* acphy, blank the first X ticks of 2g gaintbl */
 673 #define BHND_BFL3_2GTXGAINTBL_BLANK_SHIFT       14              /* acphy, blank the first X ticks of 2g gaintbl */
 674 #define BHND_BFL3_5GTXGAINTBL_BLANK             0x00008000      /* acphy, blank the first X ticks of 5g gaintbl */
 675 #define BHND_BFL3_5GTXGAINTBL_BLANK_SHIFT       15              /* acphy, blank the first X ticks of 5g gaintbl */
 676 #define BHND_BFL3_BT_SHARE_BM_BIT1              0x40000000      /* bit 1 of WLAN/BT shared core bitmap */
 677 #define BHND_BFL3_PHASETRACK_MAX_ALPHABETA      0x00010000      /* acphy, to max out alpha,beta to 511 */
 678 #define BHND_BFL3_PHASETRACK_MAX_ALPHABETA_SHIFT 16             /* acphy, to max out alpha,beta to 511 */
 679 #define BHND_BFL3_BT_SHARE_BM_BIT1              0x40000000      /* bit 1 of WLAN/BT shared core bitmap */
 680 #define BHND_BFL3_EN_NONBRCM_TXBF               0x10000000      /* acphy, enable non-brcm TXBF */
 681 #define BHND_BFL3_EN_P2PLINK_TXBF               0x20000000      /* acphy, enable TXBF in p2p links */
 682
 683
 684 /* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
 685 #define BHND_GPIO_BOARD_BTC3W_IN        0x850   /* bit 4 is RF_ACTIVE, bit 6 is STATUS, bit 11 is PRI */
 686 #define BHND_GPIO_BOARD_BTC3W_OUT       0x020   /* bit 5 is TX_CONF */
 687 #define BHND_GPIO_BOARD_BTCMOD_IN       0x010   /* bit 4 is the alternate BT Coexistence Input */
 688 #define BHND_GPIO_BOARD_BTCMOD_OUT      0x020   /* bit 5 is the alternate BT Coexistence Out */
 689 #define BHND_GPIO_BOARD_BTC_IN          0x080   /* bit 7 is BT Coexistence Input */
 690 #define BHND_GPIO_BOARD_BTC_OUT         0x100   /* bit 8 is BT Coexistence Out */
 691 #define BHND_GPIO_BOARD_PACTRL          0x200   /* bit 9 controls the PA on new 4306 boards */
 692 #define BHND_GPIO_BOARD_12              0x1000  /* gpio 12 */
 693 #define BHND_GPIO_BOARD_13              0x2000  /* gpio 13 */
 694 #define BHND_GPIO_BOARD_BTC4_IN         0x0800  /* gpio 11, coex4, in */
 695 #define BHND_GPIO_BOARD_BTC4_BT         0x2000  /* gpio 12, coex4, bt active */
 696 #define BHND_GPIO_BOARD_BTC4_STAT       0x4000  /* gpio 14, coex4, status */
 697 #define BHND_GPIO_BOARD_BTC4_WLAN       0x8000  /* gpio 15, coex4, wlan active */
 698 #define BHND_GPIO_BOARD_1_WLAN_PWR      0x02    /* throttle WLAN power on X21 board */
 699 #define BHND_GPIO_BOARD_3_WLAN_PWR      0x08    /* throttle WLAN power on X28 board */
 700 #define BHND_GPIO_BOARD_4_WLAN_PWR      0x10    /* throttle WLAN power on X19 board */
 701
 702 #define BHND_GPIO_BTC4W_OUT_4312        0x010   /* bit 4 is BT_IODISABLE */
 703 #define BHND_GPIO_BTC4W_OUT_43224       0x020   /* bit 5 is BT_IODISABLE */
 704 #define BHND_GPIO_BTC4W_OUT_43224_SHARED 0x0e0  /* bit 5 is BT_IODISABLE */
 705 #define BHND_GPIO_BTC4W_OUT_43225       0x0e0   /* bit 5 BT_IODISABLE, bit 6 SW_BT, bit 7 SW_WL */
 706 #define BHND_GPIO_BTC4W_OUT_43421       0x020   /* bit 5 is BT_IODISABLE */
 707 #define BHND_GPIO_BTC4W_OUT_4313        0x060   /* bit 5 SW_BT, bit 6 SW_WL */
 708 #define BHND_GPIO_BTC4W_OUT_4331_SHARED 0x010   /* GPIO 4  */
 709
 710 /* Board Types */
 711 #define BHND_BOARD_BU4710               0x0400
 712 #define BHND_BOARD_VSIM4710             0x0401
 713 #define BHND_BOARD_QT4710               0x0402
 714
 715 #define BHND_BOARD_BU4309               0x040a
 716 #define BHND_BOARD_BCM94309CB           0x040b
 717 #define BHND_BOARD_BCM94309MP           0x040c
 718 #define BHND_BOARD_BCM4309AP            0x040d
 719
 720 #define BHND_BOARD_BCM94302MP           0x040e
 721
 722 #define BHND_BOARD_BU4306               0x0416
 723 #define BHND_BOARD_BCM94306CB           0x0417
 724 #define BHND_BOARD_BCM94306MP           0x0418
 725
 726 #define BHND_BOARD_BCM94710D            0x041a
 727 #define BHND_BOARD_BCM94710R1           0x041b
 728 #define BHND_BOARD_BCM94710R4           0x041c
 729 #define BHND_BOARD_BCM94710AP           0x041d
 730
 731 #define BHND_BOARD_BU2050               0x041f
 732
 733
 734 #define BHND_BOARD_BCM94309G            0x0421
 735
 736 #define BHND_BOARD_BU4704               0x0423
 737 #define BHND_BOARD_BU4702               0x0424
 738
 739 #define BHND_BOARD_BCM94306PC           0x0425          /* pcmcia 3.3v 4306 card */
 740
 741
 742 #define BHND_BOARD_BCM94702MN           0x0428
 743
 744 /* BCM4702 1U CompactPCI Board */
 745 #define BHND_BOARD_BCM94702CPCI         0x0429
 746
 747 /* BCM4702 with BCM95380 VLAN Router */
 748 #define BHND_BOARD_BCM95380RR           0x042a
 749
 750 /* cb4306 with SiGe PA */
 751 #define BHND_BOARD_BCM94306CBSG         0x042b
 752
 753 /* cb4306 with SiGe PA */
 754 #define BHND_BOARD_PCSG94306            0x042d
 755
 756 /* bu4704 with sdram */
 757 #define BHND_BOARD_BU4704SD             0x042e
 758
 759 /* Dual 11a/11g Router */
 760 #define BHND_BOARD_BCM94704AGR          0x042f
 761
 762 /* 11a-only minipci */
 763 #define BHND_BOARD_BCM94308MP           0x0430
 764
 765
 766
 767 #define BHND_BOARD_BU4712               0x0444
 768 #define BHND_BOARD_BU4712SD             0x045d
 769 #define BHND_BOARD_BU4712L              0x045f
 770
 771 /* BCM4712 boards */
 772 #define BHND_BOARD_BCM94712AP           0x0445
 773 #define BHND_BOARD_BCM94712P            0x0446
 774
 775 /* BCM4318 boards */
 776 #define BHND_BOARD_BU4318               0x0447
 777 #define BHND_BOARD_CB4318               0x0448
 778 #define BHND_BOARD_MPG4318              0x0449
 779 #define BHND_BOARD_MP4318               0x044a
 780 #define BHND_BOARD_SD4318               0x044b
 781
 782 /* BCM4313 boards */
 783 #define BHND_BOARD_BCM94313BU           0x050f
 784 #define BHND_BOARD_BCM94313HM           0x0510
 785 #define BHND_BOARD_BCM94313EPA          0x0511
 786 #define BHND_BOARD_BCM94313HMG          0x051C
 787
 788 /* BCM63XX boards */
 789 #define BHND_BOARD_BCM96338             0x6338
 790 #define BHND_BOARD_BCM96348             0x6348
 791 #define BHND_BOARD_BCM96358             0x6358
 792 #define BHND_BOARD_BCM96368             0x6368
 793
 794 /* Another mp4306 with SiGe */
 795 #define BHND_BOARD_BCM94306P            0x044c
 796
 797 /* mp4303 */
 798 #define BHND_BOARD_BCM94303MP           0x044e
 799
 800 /* mpsgh4306 */
 801 #define BHND_BOARD_BCM94306MPSGH        0x044f
 802
 803 /* BRCM 4306 w/ Front End Modules */
 804 #define BHND_BOARD_BCM94306MPM          0x0450
 805 #define BHND_BOARD_BCM94306MPL          0x0453
 806
 807 /* 4712agr */
 808 #define BHND_BOARD_BCM94712AGR          0x0451
 809
 810 /* pcmcia 4303 */
 811 #define BHND_BOARD_PC4303               0x0454
 812
 813 /* 5350K */
 814 #define BHND_BOARD_BCM95350K            0x0455
 815
 816 /* 5350R */
 817 #define BHND_BOARD_BCM95350R            0x0456
 818
 819 /* 4306mplna */
 820 #define BHND_BOARD_BCM94306MPLNA        0x0457
 821
 822 /* 4320 boards */
 823 #define BHND_BOARD_BU4320               0x0458
 824 #define BHND_BOARD_BU4320S              0x0459
 825 #define BHND_BOARD_BCM94320PH           0x045a
 826
 827 /* 4306mph */
 828 #define BHND_BOARD_BCM94306MPH          0x045b
 829
 830 /* 4306pciv */
 831 #define BHND_BOARD_BCM94306PCIV         0x045c
 832
 833 #define BHND_BOARD_BU4712SD             0x045d
 834
 835 #define BHND_BOARD_BCM94320PFLSH        0x045e
 836
 837 #define BHND_BOARD_BU4712L              0x045f
 838 #define BHND_BOARD_BCM94712LGR          0x0460
 839 #define BHND_BOARD_BCM94320R            0x0461
 840
 841 #define BHND_BOARD_BU5352               0x0462
 842
 843 #define BHND_BOARD_BCM94318MPGH         0x0463
 844
 845 #define BHND_BOARD_BU4311               0x0464
 846 #define BHND_BOARD_BCM94311MC           0x0465
 847 #define BHND_BOARD_BCM94311MCAG         0x0466
 848
 849 #define BHND_BOARD_BCM95352GR           0x0467
 850
 851 /* bcm95351agr */
 852 #define BHND_BOARD_BCM95351AGR          0x0470
 853
 854 /* bcm94704mpcb */
 855 #define BHND_BOARD_BCM94704MPCB         0x0472
 856
 857 /* 4785 boards */
 858 #define BHND_BOARD_BU4785               0x0478
 859
 860 /* 4321 boards */
 861 #define BHND_BOARD_BCM4321BU            0x046b
 862 #define BHND_BOARD_BCM4321BUE           0x047c
 863 #define BHND_BOARD_BCM4321MP            0x046c
 864 #define BHND_BOARD_BCM4321CB2           0x046d
 865 #define BHND_BOARD_BCM4321CB2_AG        0x0066
 866 #define BHND_BOARD_BCM4321MC            0x046e
 867
 868 /* 4328 boards */
 869 #define BHND_BOARD_BU4328               0x0481
 870 #define BHND_BOARD_BCM4328SDG           0x0482
 871 #define BHND_BOARD_BCM4328SDAG          0x0483
 872 #define BHND_BOARD_BCM4328UG            0x0484
 873 #define BHND_BOARD_BCM4328UAG           0x0485
 874 #define BHND_BOARD_BCM4328PC            0x0486
 875 #define BHND_BOARD_BCM4328CF            0x0487
 876
 877 /* 4325 boards */
 878 #define BHND_BOARD_BCM94325DEVBU        0x0490
 879 #define BHND_BOARD_BCM94325BGABU        0x0491
 880
 881 #define BHND_BOARD_BCM94325SDGWB        0x0492
 882
 883 #define BHND_BOARD_BCM94325SDGMDL       0x04aa
 884 #define BHND_BOARD_BCM94325SDGMDL2      0x04c6
 885 #define BHND_BOARD_BCM94325SDGMDL3      0x04c9
 886
 887 #define BHND_BOARD_BCM94325SDABGWBA     0x04e1
 888
 889 /* 4322 boards */
 890 #define BHND_BOARD_BCM94322MC           0x04a4
 891 #define BHND_BOARD_BCM94322USB          0x04a8  /* dualband */
 892 #define BHND_BOARD_BCM94322HM           0x04b0
 893 #define BHND_BOARD_BCM94322USB2D        0x04bf  /* single band discrete front end */
 894
 895 /* 4312 boards */
 896 #define BHND_BOARD_BCM4312MCGSG         0x04b5
 897
 898 /* 4315 boards */
 899 #define BHND_BOARD_BCM94315DEVBU        0x04c2
 900 #define BHND_BOARD_BCM94315USBGP        0x04c7
 901 #define BHND_BOARD_BCM94315BGABU        0x04ca
 902 #define BHND_BOARD_BCM94315USBGP41      0x04cb
 903
 904 /* 4319 boards */
 905 #define BHND_BOARD_BCM94319DEVBU        0X04e5
 906 #define BHND_BOARD_BCM94319USB          0X04e6
 907 #define BHND_BOARD_BCM94319SD           0X04e7
 908
 909 /* 4716 boards */
 910 #define BHND_BOARD_BCM94716NR2          0x04cd
 911
 912 /* 4319 boards */
 913 #define BHND_BOARD_BCM94319DEVBU        0X04e5
 914 #define BHND_BOARD_BCM94319USBNP4L      0X04e6
 915 #define BHND_BOARD_BCM94319WLUSBN4L     0X04e7
 916 #define BHND_BOARD_BCM94319SDG          0X04ea
 917 #define BHND_BOARD_BCM94319LCUSBSDN4L   0X04eb
 918 #define BHND_BOARD_BCM94319USBB         0x04ee
 919 #define BHND_BOARD_BCM94319LCSDN4L      0X0507
 920 #define BHND_BOARD_BCM94319LSUSBN4L     0X0508
 921 #define BHND_BOARD_BCM94319SDNA4L       0X0517
 922 #define BHND_BOARD_BCM94319SDELNA4L     0X0518
 923 #define BHND_BOARD_BCM94319SDELNA6L     0X0539
 924 #define BHND_BOARD_BCM94319ARCADYAN     0X0546
 925 #define BHND_BOARD_BCM94319WINDSOR      0x0561
 926 #define BHND_BOARD_BCM94319MLAP         0x0562
 927 #define BHND_BOARD_BCM94319SDNA         0x058b
 928 #define BHND_BOARD_BCM94319BHEMU3       0x0563
 929 #define BHND_BOARD_BCM94319SDHMB        0x058c
 930 #define BHND_BOARD_BCM94319SDBREF       0x05a1
 931 #define BHND_BOARD_BCM94319USBSDB       0x05a2
 932
 933 /* 4329 boards */
 934 #define BHND_BOARD_BCM94329AGB          0X04b9
 935 #define BHND_BOARD_BCM94329TDKMDL1      0X04ba
 936 #define BHND_BOARD_BCM94329TDKMDL11     0X04fc
 937 #define BHND_BOARD_BCM94329OLYMPICN18   0X04fd
 938 #define BHND_BOARD_BCM94329OLYMPICN90   0X04fe
 939 #define BHND_BOARD_BCM94329OLYMPICN90U  0X050c
 940 #define BHND_BOARD_BCM94329OLYMPICN90M  0X050b
 941 #define BHND_BOARD_BCM94329AGBF         0X04ff
 942 #define BHND_BOARD_BCM94329OLYMPICX17   0X0504
 943 #define BHND_BOARD_BCM94329OLYMPICX17M  0X050a
 944 #define BHND_BOARD_BCM94329OLYMPICX17U  0X0509
 945 #define BHND_BOARD_BCM94329OLYMPICUNO   0X0564
 946 #define BHND_BOARD_BCM94329MOTOROLA     0X0565
 947 #define BHND_BOARD_BCM94329OLYMPICLOCO  0X0568
 948
 949 /* 4336 SDIO board types */
 950 #define BHND_BOARD_BCM94336SD_WLBGABU   0x0511
 951 #define BHND_BOARD_BCM94336SD_WLBGAREF  0x0519
 952 #define BHND_BOARD_BCM94336SDGP         0x0538
 953 #define BHND_BOARD_BCM94336SDG          0x0519
 954 #define BHND_BOARD_BCM94336SDGN         0x0538
 955 #define BHND_BOARD_BCM94336SDGFC        0x056B
 956
 957 /* 4330 SDIO board types */
 958 #define BHND_BOARD_BCM94330SDG          0x0528
 959 #define BHND_BOARD_BCM94330SD_FCBGABU   0x052e
 960 #define BHND_BOARD_BCM94330SD_WLBGABU   0x052f
 961 #define BHND_BOARD_BCM94330SD_FCBGA     0x0530
 962 #define BHND_BOARD_BCM94330FCSDAGB      0x0532
 963 #define BHND_BOARD_BCM94330OLYMPICAMG   0x0549
 964 #define BHND_BOARD_BCM94330OLYMPICAMGEPA        0x054F
 965 #define BHND_BOARD_BCM94330OLYMPICUNO3  0x0551
 966 #define BHND_BOARD_BCM94330WLSDAGB      0x0547
 967 #define BHND_BOARD_BCM94330CSPSDAGBB    0x054A
 968
 969 /* 43224 boards */
 970 #define BHND_BOARD_BCM943224X21         0x056e
 971 #define BHND_BOARD_BCM943224X21_FCC     0x00d1
 972 #define BHND_BOARD_BCM943224X21B        0x00e9
 973 #define BHND_BOARD_BCM943224M93         0x008b
 974 #define BHND_BOARD_BCM943224M93A        0x0090
 975 #define BHND_BOARD_BCM943224X16         0x0093
 976 #define BHND_BOARD_BCM94322X9           0x008d
 977 #define BHND_BOARD_BCM94322M35e         0x008e
 978
 979 /* 43228 Boards */
 980 #define BHND_BOARD_BCM943228BU8         0x0540
 981 #define BHND_BOARD_BCM943228BU9         0x0541
 982 #define BHND_BOARD_BCM943228BU          0x0542
 983 #define BHND_BOARD_BCM943227HM4L        0x0543
 984 #define BHND_BOARD_BCM943227HMB         0x0544
 985 #define BHND_BOARD_BCM943228HM4L        0x0545
 986 #define BHND_BOARD_BCM943228SD          0x0573
 987
 988 /* 43239 Boards */
 989 #define BHND_BOARD_BCM943239MOD         0x05ac
 990 #define BHND_BOARD_BCM943239REF         0x05aa
 991
 992 /* 4331 boards */
 993 #define BHND_BOARD_BCM94331X19          0x00D6  /* X19B */
 994 #define BHND_BOARD_BCM94331X28          0x00E4  /* X28 */
 995 #define BHND_BOARD_BCM94331X28B         0x010E  /* X28B */
 996 #define BHND_BOARD_BCM94331PCIEBT3Ax    BCM94331X28
 997 #define BHND_BOARD_BCM94331X12_2G       0x00EC  /* X12 2G */
 998 #define BHND_BOARD_BCM94331X12_5G       0x00ED  /* X12 5G */
 999 #define BHND_BOARD_BCM94331X29B         0x00EF  /* X29B */
1000 #define BHND_BOARD_BCM94331X29D         0x010F  /* X29D */
1001 #define BHND_BOARD_BCM94331CSAX         BCM94331X29B
1002 #define BHND_BOARD_BCM94331X19C         0x00F5  /* X19C */
1003 #define BHND_BOARD_BCM94331X33          0x00F4  /* X33 */
1004 #define BHND_BOARD_BCM94331BU           0x0523
1005 #define BHND_BOARD_BCM94331S9BU         0x0524
1006 #define BHND_BOARD_BCM94331MC           0x0525
1007 #define BHND_BOARD_BCM94331MCI          0x0526
1008 #define BHND_BOARD_BCM94331PCIEBT4      0x0527
1009 #define BHND_BOARD_BCM94331HM           0x0574
1010 #define BHND_BOARD_BCM94331PCIEDUAL     0x059B
1011 #define BHND_BOARD_BCM94331MCH5         0x05A9
1012 #define BHND_BOARD_BCM94331CS           0x05C6
1013 #define BHND_BOARD_BCM94331CD           0x05DA
1014
1015 /* 4314 Boards */
1016 #define BHND_BOARD_BCM94314BU           0x05b1
1017
1018 /* 53572 Boards */
1019 #define BHND_BOARD_BCM953572BU          0x058D
1020 #define BHND_BOARD_BCM953572NR2         0x058E
1021 #define BHND_BOARD_BCM947188NR2         0x058F
1022 #define BHND_BOARD_BCM953572SDRNR2      0x0590
1023
1024 /* 43236 boards */
1025 #define BHND_BOARD_BCM943236OLYMPICSULLEY       0x594
1026 #define BHND_BOARD_BCM943236PREPROTOBLU2O3      0x5b9
1027 #define BHND_BOARD_BCM943236USBELNA             0x5f8
1028
1029 /* 4314 Boards */
1030 #define BHND_BOARD_BCM94314BUSDIO       0x05c8
1031 #define BHND_BOARD_BCM94314BGABU        0x05c9
1032 #define BHND_BOARD_BCM94314HMEPA        0x05ca
1033 #define BHND_BOARD_BCM94314HMEPABK      0x05cb
1034 #define BHND_BOARD_BCM94314SUHMEPA      0x05cc
1035 #define BHND_BOARD_BCM94314SUHM         0x05cd
1036 #define BHND_BOARD_BCM94314HM           0x05d1
1037
1038 /* 4334 Boards */
1039 #define BHND_BOARD_BCM94334FCAGBI       0x05df
1040 #define BHND_BOARD_BCM94334WLAGBI       0x05dd
1041
1042 /* 4335 Boards */
1043 #define BHND_BOARD_BCM94335X52          0x0114
1044
1045 /* 4345 Boards */
1046 #define BHND_BOARD_BCM94345             0x0687
1047
1048 /* 4360 Boards */
1049 #define BHND_BOARD_BCM94360X52C         0X0117
1050 #define BHND_BOARD_BCM94360X52D         0X0137
1051 #define BHND_BOARD_BCM94360X29C         0X0112
1052 #define BHND_BOARD_BCM94360X29CP2       0X0134
1053 #define BHND_BOARD_BCM94360X51          0x0111
1054 #define BHND_BOARD_BCM94360X51P2        0x0129
1055 #define BHND_BOARD_BCM94360X51A         0x0135
1056 #define BHND_BOARD_BCM94360X51B         0x0136
1057 #define BHND_BOARD_BCM94360CS           0x061B
1058 #define BHND_BOARD_BCM94360J28_D11AC2G  0x0c00
1059 #define BHND_BOARD_BCM94360J28_D11AC5G  0x0c01
1060 #define BHND_BOARD_BCM94360USBH5_D11AC5G        0x06aa
1061
1062 /* 4350 Boards */
1063 #define BHND_BOARD_BCM94350X52B         0X0116
1064 #define BHND_BOARD_BCM94350X14          0X0131
1065
1066 /* 43217 Boards */
1067 #define BHND_BOARD_BCM943217BU          0x05d5
1068 #define BHND_BOARD_BCM943217HM2L        0x05d6
1069 #define BHND_BOARD_BCM943217HMITR2L     0x05d7
1070
1071 /* 43142 Boards */
1072 #define BHND_BOARD_BCM943142HM          0x05e0
1073
1074 /* 43341 Boards */
1075 #define BHND_BOARD_BCM943341WLABGS      0x062d
1076
1077 /* 43342 Boards */
1078 #define BHND_BOARD_BCM943342FCAGBI      0x0641
1079
1080 /* 43602 Boards, unclear yet what boards will be created. */
1081 #define BHND_BOARD_BCM943602RSVD1       0x06a5
1082 #define BHND_BOARD_BCM943602RSVD2       0x06a6
1083 #define BHND_BOARD_BCM943602X87         0X0133
1084 #define BHND_BOARD_BCM943602X238        0X0132
1085
1086 /* 4354 board types */
1087 #define BHND_BOARD_BCM94354WLSAGBI      0x06db
1088 #define BHND_BOARD_BCM94354Z            0x0707
1089
1090 /* # of GPIO pins */
1091 #define BHND_BCM43XX_GPIO_NUMPINS       32
1092
1093 /* These values are used by dhd USB host driver. */
1094 #define BHND_USB_RDL_RAM_BASE_4319      0x60000000
1095 #define BHND_USB_RDL_RAM_BASE_4329      0x60000000
1096 #define BHND_USB_RDL_RAM_SIZE_4319      0x48000
1097 #define BHND_USB_RDL_RAM_SIZE_4329      0x48000
1098 #define BHND_USB_RDL_RAM_SIZE_43236     0x70000
1099 #define BHND_USB_RDL_RAM_BASE_43236     0x60000000
1100 #define BHND_USB_RDL_RAM_SIZE_4328      0x60000
1101 #define BHND_USB_RDL_RAM_BASE_4328      0x80000000
1102 #define BHND_USB_RDL_RAM_SIZE_4322      0x60000
1103 #define BHND_USB_RDL_RAM_BASE_4322      0x60000000
1104 #define BHND_USB_RDL_RAM_SIZE_4360      0xA0000
1105 #define BHND_USB_RDL_RAM_BASE_4360      0x60000000
1106 #define BHND_USB_RDL_RAM_SIZE_43242     0x90000
1107 #define BHND_USB_RDL_RAM_BASE_43242     0x60000000
1108 #define BHND_USB_RDL_RAM_SIZE_43143     0x70000
1109 #define BHND_USB_RDL_RAM_BASE_43143     0x60000000
1110 #define BHND_USB_RDL_RAM_SIZE_4350      0xC0000
1111 #define BHND_USB_RDL_RAM_BASE_4350      0x180800
1112
1113 /* generic defs for nvram "muxenab" bits
1114 * Note: these differ for 4335a0. refer bcmchipc.h for specific mux options.
1115 */
1116 #define BHND_NVRAM_MUXENAB_UART         0x00000001
1117 #define BHND_NVRAM_MUXENAB_GPIO         0x00000002
1118 #define BHND_NVRAM_MUXENAB_ERCX         0x00000004      /* External Radio BT coex */
1119 #define BHND_NVRAM_MUXENAB_JTAG         0x00000008
1120 #define BHND_NVRAM_MUXENAB_HOST_WAKE    0x00000010      /* configure GPIO for SDIO host_wake */
1121 #define BHND_NVRAM_MUXENAB_I2S_EN       0x00000020
1122 #define BHND_NVRAM_MUXENAB_I2S_MASTER   0x00000040
1123 #define BHND_NVRAM_MUXENAB_I2S_FULL     0x00000080
1124 #define BHND_NVRAM_MUXENAB_SFLASH       0x00000100
1125 #define BHND_NVRAM_MUXENAB_RFSWCTRL0    0x00000200
1126 #define BHND_NVRAM_MUXENAB_RFSWCTRL1    0x00000400
1127 #define BHND_NVRAM_MUXENAB_RFSWCTRL2    0x00000800
1128 #define BHND_NVRAM_MUXENAB_SECI         0x00001000
1129 #define BHND_NVRAM_MUXENAB_BT_LEGACY    0x00002000
1130 #define BHND_NVRAM_MUXENAB_HOST_WAKE1   0x00004000      /* configure alternative GPIO for SDIO host_wake */
1131
1132 /* Boot flags */
1133 #define BHND_BOOTFLAG_FLASH_KERNEL_NFLASH       0x00000001
1134 #define BHND_BOOTFLAG_FLASH_BOOT_NFLASH         0x00000002
1135
1136 #endif /* _BHND_BHND_IDS_H_ */