2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/types.h>
35 #include <sys/systm.h>
37 #include <machine/bus.h>
39 #include <machine/resource.h>
41 #include <dev/bhnd/cores/chipc/chipcreg.h>
46 /* BHND core device description table. */
47 static const struct bhnd_core_desc {
50 bhnd_devclass_t class;
52 } bhnd_core_descs[] = {
53 #define BHND_CDESC(_mfg, _cid, _cls, _desc) \
54 { BHND_MFGID_ ## _mfg, BHND_COREID_ ## _cid, \
55 BHND_DEVCLASS_ ## _cls, _desc }
57 BHND_CDESC(BCM, CC, CC, "ChipCommon I/O Controller"),
58 BHND_CDESC(BCM, ILINE20, OTHER, "iLine20 HPNA"),
59 BHND_CDESC(BCM, SRAM, RAM, "SRAM"),
60 BHND_CDESC(BCM, SDRAM, RAM, "SDRAM"),
61 BHND_CDESC(BCM, PCI, PCI, "PCI Bridge"),
62 BHND_CDESC(BCM, MIPS, CPU, "MIPS Core"),
63 BHND_CDESC(BCM, ENET, ENET_MAC, "Fast Ethernet MAC"),
64 BHND_CDESC(BCM, CODEC, OTHER, "V.90 Modem Codec"),
65 BHND_CDESC(BCM, USB, OTHER, "USB 1.1 Device/Host Controller"),
66 BHND_CDESC(BCM, ADSL, OTHER, "ADSL Core"),
67 BHND_CDESC(BCM, ILINE100, OTHER, "iLine100 HPNA"),
68 BHND_CDESC(BCM, IPSEC, OTHER, "IPsec Accelerator"),
69 BHND_CDESC(BCM, UTOPIA, OTHER, "UTOPIA ATM Core"),
70 BHND_CDESC(BCM, PCMCIA, PCCARD, "PCMCIA Bridge"),
71 BHND_CDESC(BCM, SOCRAM, RAM, "Internal Memory"),
72 BHND_CDESC(BCM, MEMC, MEMC, "MEMC SDRAM Controller"),
73 BHND_CDESC(BCM, OFDM, OTHER, "OFDM PHY"),
74 BHND_CDESC(BCM, EXTIF, OTHER, "External Interface"),
75 BHND_CDESC(BCM, D11, WLAN, "802.11 MAC/PHY/Radio"),
76 BHND_CDESC(BCM, APHY, WLAN_PHY, "802.11a PHY"),
77 BHND_CDESC(BCM, BPHY, WLAN_PHY, "802.11b PHY"),
78 BHND_CDESC(BCM, GPHY, WLAN_PHY, "802.11g PHY"),
79 BHND_CDESC(BCM, MIPS33, CPU, "MIPS 3302 Core"),
80 BHND_CDESC(BCM, USB11H, OTHER, "USB 1.1 Host Controller"),
81 BHND_CDESC(BCM, USB11D, OTHER, "USB 1.1 Device Core"),
82 BHND_CDESC(BCM, USB20H, OTHER, "USB 2.0 Host Controller"),
83 BHND_CDESC(BCM, USB20D, OTHER, "USB 2.0 Device Core"),
84 BHND_CDESC(BCM, SDIOH, OTHER, "SDIO Host Controller"),
85 BHND_CDESC(BCM, ROBO, OTHER, "RoboSwitch"),
86 BHND_CDESC(BCM, ATA100, OTHER, "Parallel ATA Controller"),
87 BHND_CDESC(BCM, SATAXOR, OTHER, "SATA DMA/XOR Controller"),
88 BHND_CDESC(BCM, GIGETH, ENET_MAC, "Gigabit Ethernet MAC"),
89 BHND_CDESC(BCM, PCIE, PCIE, "PCIe Bridge"),
90 BHND_CDESC(BCM, NPHY, WLAN_PHY, "802.11n 2x2 PHY"),
91 BHND_CDESC(BCM, SRAMC, MEMC, "SRAM Controller"),
92 BHND_CDESC(BCM, MINIMAC, OTHER, "MINI MAC/PHY"),
93 BHND_CDESC(BCM, ARM11, CPU, "ARM1176 CPU"),
94 BHND_CDESC(BCM, ARM7S, CPU, "ARM7TDMI-S CPU"),
95 BHND_CDESC(BCM, LPPHY, WLAN_PHY, "802.11a/b/g PHY"),
96 BHND_CDESC(BCM, PMU, PMU, "PMU"),
97 BHND_CDESC(BCM, SSNPHY, WLAN_PHY, "802.11n Single-Stream PHY"),
98 BHND_CDESC(BCM, SDIOD, OTHER, "SDIO Device Core"),
99 BHND_CDESC(BCM, ARMCM3, CPU, "ARM Cortex-M3 CPU"),
100 BHND_CDESC(BCM, HTPHY, WLAN_PHY, "802.11n 4x4 PHY"),
101 BHND_CDESC(BCM, MIPS74K, CPU, "MIPS74k CPU"),
102 BHND_CDESC(BCM, GMAC, ENET_MAC, "Gigabit MAC core"),
103 BHND_CDESC(BCM, DMEMC, MEMC, "DDR1/DDR2 Memory Controller"),
104 BHND_CDESC(BCM, PCIERC, OTHER, "PCIe Root Complex"),
105 BHND_CDESC(BCM, OCP, SOC_BRIDGE, "OCP to OCP Bridge"),
106 BHND_CDESC(BCM, SC, OTHER, "Shared Common Core"),
107 BHND_CDESC(BCM, AHB, SOC_BRIDGE, "OCP to AHB Bridge"),
108 BHND_CDESC(BCM, SPIH, OTHER, "SPI Host Controller"),
109 BHND_CDESC(BCM, I2S, OTHER, "I2S Digital Audio Interface"),
110 BHND_CDESC(BCM, DMEMS, MEMC, "SDR/DDR1 Memory Controller"),
111 BHND_CDESC(BCM, UBUS_SHIM, OTHER, "BCM6362/UBUS WLAN SHIM"),
112 BHND_CDESC(BCM, PCIE2, PCIE, "PCIe Bridge (Gen2)"),
114 BHND_CDESC(ARM, APB_BRIDGE, SOC_BRIDGE, "BP135 AMBA3 AXI to APB Bridge"),
115 BHND_CDESC(ARM, PL301, SOC_ROUTER, "PL301 AMBA3 Interconnect"),
116 BHND_CDESC(ARM, EROM, EROM, "PL366 Device Enumeration ROM"),
117 BHND_CDESC(ARM, OOB_ROUTER, OTHER, "PL367 OOB Interrupt Router"),
118 BHND_CDESC(ARM, AXI_UNMAPPED, OTHER, "Unmapped Address Ranges"),
120 BHND_CDESC(BCM, 4706_CC, CC, "ChipCommon I/O Controller"),
121 BHND_CDESC(BCM, NS_PCIE2, PCIE, "PCIe Bridge (Gen2)"),
122 BHND_CDESC(BCM, NS_DMA, OTHER, "DMA engine"),
123 BHND_CDESC(BCM, NS_SDIO, OTHER, "SDIO 3.0 Host Controller"),
124 BHND_CDESC(BCM, NS_USB20H, OTHER, "USB 2.0 Host Controller"),
125 BHND_CDESC(BCM, NS_USB30H, OTHER, "USB 3.0 Host Controller"),
126 BHND_CDESC(BCM, NS_A9JTAG, OTHER, "ARM Cortex A9 JTAG Interface"),
127 BHND_CDESC(BCM, NS_DDR23_MEMC, MEMC, "Denali DDR2/DD3 Memory Controller"),
128 BHND_CDESC(BCM, NS_ROM, NVRAM, "System ROM"),
129 BHND_CDESC(BCM, NS_NAND, NVRAM, "NAND Flash Controller"),
130 BHND_CDESC(BCM, NS_QSPI, NVRAM, "QSPI Flash Controller"),
131 BHND_CDESC(BCM, NS_CC_B, CC_B, "ChipCommon B Auxiliary I/O Controller"),
132 BHND_CDESC(BCM, 4706_SOCRAM, RAM, "Internal Memory"),
133 BHND_CDESC(BCM, IHOST_ARMCA9, CPU, "ARM Cortex A9 CPU"),
134 BHND_CDESC(BCM, 4706_GMAC_CMN, ENET, "Gigabit MAC (Common)"),
135 BHND_CDESC(BCM, 4706_GMAC, ENET_MAC, "Gigabit MAC"),
136 BHND_CDESC(BCM, AMEMC, MEMC, "Denali DDR1/DDR2 Memory Controller"),
139 /* Derived from inspection of the BCM4331 cores that provide PrimeCell
140 * IDs. Due to lack of documentation, the surmised device name/purpose
141 * provided here may be incorrect. */
142 { BHND_MFGID_ARM, BHND_PRIMEID_EROM, BHND_DEVCLASS_OTHER,
143 "PL364 Device Enumeration ROM" },
144 { BHND_MFGID_ARM, BHND_PRIMEID_SWRAP, BHND_DEVCLASS_OTHER,
145 "PL368 Device Management Interface" },
146 { BHND_MFGID_ARM, BHND_PRIMEID_MWRAP, BHND_DEVCLASS_OTHER,
147 "PL369 Device Management Interface" },
153 * Return the name for a given JEP106 manufacturer ID.
155 * @param vendor A JEP106 Manufacturer ID, including the non-standard ARM 4-bit
156 * JEP106 continuation code.
159 bhnd_vendor_name(uint16_t vendor)
166 case BHND_MFGID_MIPS:
174 * Return the name of a port type.
177 bhnd_port_type_name(bhnd_port_type port_type)
180 case BHND_PORT_DEVICE:
182 case BHND_PORT_BRIDGE:
184 case BHND_PORT_AGENT:
190 static const struct bhnd_core_desc *
191 bhnd_find_core_desc(uint16_t vendor, uint16_t device)
193 for (u_int i = 0; bhnd_core_descs[i].desc != NULL; i++) {
194 if (bhnd_core_descs[i].vendor != vendor)
197 if (bhnd_core_descs[i].device != device)
200 return (&bhnd_core_descs[i]);
207 * Return a human-readable name for a BHND core.
209 * @param vendor The core designer's JEDEC-106 Manufacturer ID
210 * @param device The core identifier.
213 bhnd_find_core_name(uint16_t vendor, uint16_t device)
215 const struct bhnd_core_desc *desc;
217 if ((desc = bhnd_find_core_desc(vendor, device)) == NULL)
224 * Return the device class for a BHND core.
226 * @param vendor The core designer's JEDEC-106 Manufacturer ID
227 * @param device The core identifier.
230 bhnd_find_core_class(uint16_t vendor, uint16_t device)
232 const struct bhnd_core_desc *desc;
234 if ((desc = bhnd_find_core_desc(vendor, device)) == NULL)
235 return (BHND_DEVCLASS_OTHER);
241 * Return a human-readable name for a BHND core.
243 * @param ci The core's info record.
246 bhnd_core_name(const struct bhnd_core_info *ci)
248 return bhnd_find_core_name(ci->vendor, ci->device);
252 * Return the device class for a BHND core.
254 * @param ci The core's info record.
257 bhnd_core_class(const struct bhnd_core_info *ci)
259 return bhnd_find_core_class(ci->vendor, ci->device);
263 * Initialize a core info record with data from from a bhnd-attached @p dev.
265 * @param dev A bhnd device.
266 * @param core The record to be initialized.
268 struct bhnd_core_info
269 bhnd_get_core_info(device_t dev) {
270 return (struct bhnd_core_info) {
271 .vendor = bhnd_get_vendor(dev),
272 .device = bhnd_get_device(dev),
273 .hwrev = bhnd_get_hwrev(dev),
274 .core_idx = bhnd_get_core_index(dev),
275 .unit = bhnd_get_core_unit(dev)
280 * Find a @p class child device with @p unit on @p dev.
282 * @param parent The bhnd-compatible bus to be searched.
283 * @param class The device class to match on.
284 * @param unit The device unit number; specify -1 to return the first match
285 * regardless of unit number.
287 * @retval device_t if a matching child device is found.
288 * @retval NULL if no matching child device is found.
291 bhnd_find_child(device_t dev, bhnd_devclass_t class, int unit)
293 struct bhnd_core_match md = {
294 .vendor = BHND_MFGID_INVALID,
295 .device = BHND_COREID_INVALID,
296 .hwrev.start = BHND_HWREV_INVALID,
297 .hwrev.end = BHND_HWREV_INVALID,
302 return bhnd_match_child(dev, &md);
306 * Find the first child device on @p dev that matches @p desc.
308 * @param parent The bhnd-compatible bus to be searched.
309 * @param desc A match descriptor.
311 * @retval device_t if a matching child device is found.
312 * @retval NULL if no matching child device is found.
315 bhnd_match_child(device_t dev, const struct bhnd_core_match *desc)
322 error = device_get_children(dev, &devlistp, &devcnt);
327 for (int i = 0; i < devcnt; i++) {
328 device_t dev = devlistp[i];
329 if (bhnd_device_matches(dev, desc)) {
336 free(devlistp, M_TEMP);
341 * Find the first core in @p cores that matches @p desc.
343 * @param cores The table to search.
344 * @param num_cores The length of @p cores.
345 * @param desc A match descriptor.
347 * @retval bhnd_core_info if a matching core is found.
348 * @retval NULL if no matching core is found.
350 const struct bhnd_core_info *
351 bhnd_match_core(const struct bhnd_core_info *cores, u_int num_cores,
352 const struct bhnd_core_match *desc)
354 for (u_int i = 0; i < num_cores; i++) {
355 if (bhnd_core_matches(&cores[i], desc))
364 * Find the first core in @p cores with the given @p class.
366 * @param cores The table to search.
367 * @param num_cores The length of @p cores.
368 * @param desc A match descriptor.
370 * @retval bhnd_core_info if a matching core is found.
371 * @retval NULL if no matching core is found.
373 const struct bhnd_core_info *
374 bhnd_find_core(const struct bhnd_core_info *cores, u_int num_cores,
375 bhnd_devclass_t class)
377 struct bhnd_core_match md = {
378 .vendor = BHND_MFGID_INVALID,
379 .device = BHND_COREID_INVALID,
380 .hwrev.start = BHND_HWREV_INVALID,
381 .hwrev.end = BHND_HWREV_INVALID,
386 return bhnd_match_core(cores, num_cores, &md);
390 * Return true if the @p core matches @p desc.
392 * @param core A bhnd core descriptor.
393 * @param desc A match descriptor to compare against @p core.
395 * @retval true if @p core matches @p match
396 * @retval false if @p core does not match @p match.
399 bhnd_core_matches(const struct bhnd_core_info *core,
400 const struct bhnd_core_match *desc)
402 if (desc->vendor != BHND_MFGID_INVALID &&
403 desc->vendor != core->vendor)
406 if (desc->device != BHND_COREID_INVALID &&
407 desc->device != core->device)
410 if (desc->unit != -1 && desc->unit != core->unit)
413 if (!bhnd_hwrev_matches(core->hwrev, &desc->hwrev))
416 if (desc->hwrev.end != BHND_HWREV_INVALID &&
417 desc->hwrev.end < core->hwrev)
420 if (desc->class != BHND_DEVCLASS_INVALID &&
421 desc->class != bhnd_core_class(core))
428 * Return true if the @p hwrev matches @p desc.
430 * @param hwrev A bhnd hardware revision.
431 * @param desc A match descriptor to compare against @p core.
433 * @retval true if @p hwrev matches @p match
434 * @retval false if @p hwrev does not match @p match.
437 bhnd_hwrev_matches(uint16_t hwrev, const struct bhnd_hwrev_match *desc)
439 if (desc->start != BHND_HWREV_INVALID &&
443 if (desc->end != BHND_HWREV_INVALID &&
451 * Return true if the @p dev matches @p desc.
453 * @param dev A bhnd device.
454 * @param desc A match descriptor to compare against @p dev.
456 * @retval true if @p dev matches @p match
457 * @retval false if @p dev does not match @p match.
460 bhnd_device_matches(device_t dev, const struct bhnd_core_match *desc)
462 struct bhnd_core_info ci = {
463 .vendor = bhnd_get_vendor(dev),
464 .device = bhnd_get_device(dev),
465 .unit = bhnd_get_core_unit(dev),
466 .hwrev = bhnd_get_hwrev(dev)
469 return bhnd_core_matches(&ci, desc);
473 * Allocate bhnd(4) resources defined in @p rs from a parent bus.
475 * @param dev The device requesting ownership of the resources.
476 * @param rs A standard bus resource specification. This will be updated
477 * with the allocated resource's RIDs.
478 * @param res On success, the allocated bhnd resources.
481 * @retval non-zero if allocation of any non-RF_OPTIONAL resource fails,
482 * all allocated resources will be released and a regular
483 * unix error code will be returned.
486 bhnd_alloc_resources(device_t dev, struct resource_spec *rs,
487 struct bhnd_resource **res)
489 /* Initialize output array */
490 for (u_int i = 0; rs[i].type != -1; i++)
493 for (u_int i = 0; rs[i].type != -1; i++) {
494 res[i] = bhnd_alloc_resource_any(dev, rs[i].type, &rs[i].rid,
497 /* Clean up all allocations on failure */
498 if (res[i] == NULL && !(rs[i].flags & RF_OPTIONAL)) {
499 bhnd_release_resources(dev, rs, res);
508 * Release bhnd(4) resources defined in @p rs from a parent bus.
510 * @param dev The device that owns the resources.
511 * @param rs A standard bus resource specification previously initialized
512 * by @p bhnd_alloc_resources.
513 * @param res The bhnd resources to be released.
516 bhnd_release_resources(device_t dev, const struct resource_spec *rs,
517 struct bhnd_resource **res)
519 for (u_int i = 0; rs[i].type != -1; i++) {
523 bhnd_release_resource(dev, rs[i].type, rs[i].rid, res[i]);
529 * Parse the CHIPC_ID_* fields from the ChipCommon CHIPC_ID
530 * register, returning its bhnd_chipid representation.
532 * @param idreg The CHIPC_ID register value.
533 * @param enum_addr The enumeration address to include in the result.
536 * On early siba(4) devices, the ChipCommon core does not provide
537 * a valid CHIPC_ID_NUMCORE field. On these ChipCommon revisions
538 * (see CHIPC_NCORES_MIN_HWREV()), this function will parse and return
539 * an invalid `ncores` value.
542 bhnd_parse_chipid(uint32_t idreg, bhnd_addr_t enum_addr)
544 struct bhnd_chipid result;
546 /* Fetch the basic chip info */
547 result.chip_id = CHIPC_GET_ATTR(idreg, ID_CHIP);
548 result.chip_pkg = CHIPC_GET_ATTR(idreg, ID_PKG);
549 result.chip_rev = CHIPC_GET_ATTR(idreg, ID_REV);
550 result.chip_type = CHIPC_GET_ATTR(idreg, ID_BUS);
551 result.ncores = CHIPC_GET_ATTR(idreg, ID_NUMCORE);
553 result.enum_addr = enum_addr;
559 * Allocate the resource defined by @p rs via @p dev, use it
560 * to read the ChipCommon ID register relative to @p chipc_offset,
561 * then release the resource.
563 * @param dev The device owning @p rs.
564 * @param rs A resource spec that encompasses the ChipCommon register block.
565 * @param chipc_offset The offset of the ChipCommon registers within @p rs.
566 * @param[out] result the chip identification data.
569 * @retval non-zero if the ChipCommon identification data could not be read.
572 bhnd_read_chipid(device_t dev, struct resource_spec *rs,
573 bus_size_t chipc_offset, struct bhnd_chipid *result)
575 struct resource *res;
577 int error, rid, rtype;
579 /* Allocate the ChipCommon window resource and fetch the chipid data */
582 res = bus_alloc_resource_any(dev, rtype, &rid, RF_ACTIVE);
585 "failed to allocate bhnd chipc resource\n");
589 /* Fetch the basic chip info */
590 reg = bus_read_4(res, chipc_offset + CHIPC_ID);
591 *result = bhnd_parse_chipid(reg, 0x0);
593 /* Fetch the enum base address */
595 switch (result->chip_type) {
596 case BHND_CHIPTYPE_SIBA:
597 result->enum_addr = BHND_DEFAULT_CHIPC_ADDR;
599 case BHND_CHIPTYPE_BCMA:
600 case BHND_CHIPTYPE_BCMA_ALT:
601 result->enum_addr = bus_read_4(res, chipc_offset +
604 case BHND_CHIPTYPE_UBUS:
605 device_printf(dev, "unsupported ubus/bcm63xx chip type");
609 device_printf(dev, "unknown chip type %hhu\n",
617 bus_release_resource(dev, rtype, rid, res);
622 * Using the bhnd(4) bus-level core information, populate @p dev's device
625 * @param dev A bhnd-bus attached device.
628 bhnd_set_generic_core_desc(device_t dev)
630 const char *dev_name;
631 const char *vendor_name;
634 vendor_name = bhnd_get_vendor_name(dev);
635 dev_name = bhnd_get_device_name(dev);
637 asprintf(&desc, M_BHND, "%s %s, rev %hhu",
638 bhnd_get_vendor_name(dev),
639 bhnd_get_device_name(dev),
640 bhnd_get_hwrev(dev));
643 device_set_desc_copy(dev, desc);
646 device_set_desc(dev, dev_name);