2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
5 * Redistribution and use in source and binary forms, with or without
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13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
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32 #ifndef _BHND_BHND_TYPES_H_
33 #define _BHND_BHND_TYPES_H_
35 #include <sys/types.h>
37 #include "nvram/bhnd_nvram.h"
39 /** bhnd(4) device classes. */
41 BHND_DEVCLASS_CC, /**< chipcommon i/o controller */
42 BHND_DEVCLASS_CC_B, /**< chipcommon auxiliary controller */
43 BHND_DEVCLASS_PMU, /**< pmu controller */
44 BHND_DEVCLASS_PCI, /**< pci host/device bridge */
45 BHND_DEVCLASS_PCIE, /**< pcie host/device bridge */
46 BHND_DEVCLASS_PCCARD, /**< pcmcia host/device bridge */
47 BHND_DEVCLASS_RAM, /**< internal RAM/SRAM */
48 BHND_DEVCLASS_MEMC, /**< memory controller */
49 BHND_DEVCLASS_ENET, /**< 802.3 MAC/PHY */
50 BHND_DEVCLASS_ENET_MAC, /**< 802.3 MAC */
51 BHND_DEVCLASS_ENET_PHY, /**< 802.3 PHY */
52 BHND_DEVCLASS_WLAN, /**< 802.11 MAC/PHY/Radio */
53 BHND_DEVCLASS_WLAN_MAC, /**< 802.11 MAC */
54 BHND_DEVCLASS_WLAN_PHY, /**< 802.11 PHY */
55 BHND_DEVCLASS_CPU, /**< cpu core */
56 BHND_DEVCLASS_SOC_ROUTER, /**< interconnect router */
57 BHND_DEVCLASS_SOC_BRIDGE, /**< interconnect host bridge */
58 BHND_DEVCLASS_EROM, /**< bus device enumeration ROM */
59 BHND_DEVCLASS_NVRAM, /**< nvram/flash controller */
60 BHND_DEVCLASS_USB_HOST, /**< USB host controller */
61 BHND_DEVCLASS_USB_DEV, /**< USB device controller */
62 BHND_DEVCLASS_USB_DUAL, /**< USB host/device controller */
64 BHND_DEVCLASS_OTHER = 1000, /**< other / unknown */
65 BHND_DEVCLASS_INVALID /**< no/invalid class */
72 * Only BHND_PORT_DEVICE is guaranteed to be supported by all bhnd(4) bus
76 BHND_PORT_DEVICE = 0, /**< device memory */
77 BHND_PORT_BRIDGE = 1, /**< bridge memory */
78 BHND_PORT_AGENT = 2, /**< interconnect agent/wrapper */
82 * bhnd(4) attachment types.
85 BHND_ATTACH_ADAPTER = 0, /**< A bridged card, such as a PCI WiFi chipset */
86 BHND_ATTACH_NATIVE = 1 /**< A bus resident on the native host, such as
87 * the primary or secondary bus of an embedded
92 * bhnd(4) clock types.
96 * Dynamically select an appropriate clock source based on all
97 * outstanding clock requests.
99 BHND_CLOCK_DYN = (1 << 0),
102 * Idle Low-Power (ILP).
104 * No register access is required, or long request latency is
107 BHND_CLOCK_ILP = (1 << 1),
110 * Active Low-Power (ALP).
112 * Low-latency register access and low-rate DMA.
114 BHND_CLOCK_ALP = (1 << 2),
117 * High Throughput (HT).
119 * High bus throughput and lowest-latency register access.
121 BHND_CLOCK_HT = (1 << 3)
125 * Given two clock types, return the type with the highest precedence.
127 static inline bhnd_clock
128 bhnd_clock_max(bhnd_clock a, bhnd_clock b) {
129 return (a > b ? a : b);
133 * bhnd(4) clock sources.
137 * Clock is provided by the PCI bus clock
141 /** Clock is provided by a crystal. */
142 BHND_CLKSRC_XTAL = 1,
144 /** Clock is provided by a low power oscillator. */
147 /** Clock source is unknown */
148 BHND_CLKSRC_UNKNOWN = 3
151 /** Evaluates to true if @p cls is a device class that can be configured
152 * as a host bridge device. */
153 #define BHND_DEVCLASS_SUPPORTS_HOSTB(cls) \
154 ((cls) == BHND_DEVCLASS_PCI || (cls) == BHND_DEVCLASS_PCIE || \
155 (cls) == BHND_DEVCLASS_PCCARD)
160 * @note While the interconnect may support 64-bit addressing, not
161 * all bridges and SoC CPUs will.
163 typedef uint64_t bhnd_addr_t;
164 #define BHND_ADDR_MAX UINT64_MAX /**< Maximum bhnd_addr_t value */
166 /** BHND bus size. */
167 typedef uint64_t bhnd_size_t;
168 #define BHND_SIZE_MAX UINT64_MAX /**< Maximum bhnd_size_t value */
171 #endif /* _BHND_BHND_TYPES_H_ */