sys/dev/bhnd/bhndb/bhndb_pci_hwdata.c

   1 /*-
   2  * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer,
  10  *    without modification.
  11  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  12  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  13  *    redistribution must be conditioned upon including a substantially
  14  *    similar Disclaimer requirement for further binary redistribution.
  15  *
  16  * NO WARRANTY
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  20  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  22  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  25  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  27  * THE POSSIBILITY OF SUCH DAMAGES.
  28  */
  29
  30 #include <sys/cdefs.h>
  31 __FBSDID("$FreeBSD$");
  32
  33 /*
  34  * Resource specifications and register maps for Broadcom PCI/PCIe cores
  35  * configured as PCI-BHND bridges.
  36  */
  37
  38 #include <sys/param.h>
  39 #include <sys/bus.h>
  40
  41 #include <machine/bus.h>
  42 #include <sys/rman.h>
  43 #include <machine/resource.h>
  44
  45 #include <dev/pci/pcireg.h>
  46 #include <dev/pci/pcivar.h>
  47
  48 #include <dev/bhnd/cores/pci/bhnd_pcireg.h>
  49 #include <dev/bhnd/cores/pcie2/bhnd_pcie2_reg.h>
  50
  51 #include "bhndbvar.h"
  52 #include "bhndb_pcireg.h"
  53
  54 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v0;
  55 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci;
  56 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie;
  57 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v2;
  58 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v3;
  59
  60 /**
  61  * Define a bhndb_hw match entry.
  62  *
  63  * @param _name The entry name.
  64  * @param _vers The configuration version associated with this entry.
  65  */
  66 #define BHNDB_HW_MATCH(_name, _vers, ...) {                             \
  67         .name           = _name,                                        \
  68         .hw_reqs        = _BHNDB_HW_REQ_ARRAY(__VA_ARGS__),             \
  69         .num_hw_reqs    = (sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)) /   \
  70             sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)[0])),               \
  71         .cfg            = &bhndb_pci_hwcfg_ ## _vers                    \
  72 }
  73 #define _BHNDB_HW_REQ_ARRAY(...) (struct bhnd_core_match[]) { __VA_ARGS__ }
  74
  75 /**
  76  * Generic PCI-SIBA bridge configuration usable with all known siba(4)-based
  77  * PCI devices; this configuration is adequate for enumerating a bridged
  78  * siba(4) bus to determine the full hardware configuration.
  79  *
  80  * @par Compatibility
  81  * - Compatible with PCI_V0, PCI_V1, PCI_V2, and PCI_V3 devices.
  82  * - Compatible with siba(4) bus enumeration.
  83  * - Compatible with bcma(4) bus enumeration if the ChipCommon core is mapped
  84  *   at the default enumeration address (0x18000000).
  85  */
  86 const struct bhndb_hwcfg bhndb_pci_siba_generic_hwcfg = {
  87         .resource_specs = (const struct resource_spec[]) {
  88                 { SYS_RES_MEMORY,       PCIR_BAR(0),    RF_ACTIVE },
  89                 { -1,                   0,              0 }
  90         },
  91
  92         .register_windows = (const struct bhndb_regwin[]) {
  93                 /* bar0+0x0000: configurable backplane window */
  94                 {
  95                         .win_type       = BHNDB_REGWIN_T_DYN,
  96                         .win_offset     = BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
  97                         .win_size       = BHNDB_PCI_V1_BAR0_WIN0_SIZE,
  98                         .d.dyn = {
  99                                 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL
 100                         },
 101                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 102                 },
 103                 BHNDB_REGWIN_TABLE_END
 104         },
 105
 106         /* DMA unsupported under generic configuration */
 107         .dma_translations = NULL,
 108 };
 109
 110 /**
 111  * Generic PCI-BCMA bridge configuration usable with all known bcma(4)-based
 112  * PCI devices; this configuration is adequate for enumerating a bridged
 113  * bcma(4) bus to determine the full hardware configuration.
 114  *
 115  * @par Compatibility
 116  * - Compatible with PCI_V1, PCI_V2, and PCI_V3 devices.
 117  * - Compatible with both siba(4) and bcma(4) bus enumeration.
 118  */
 119 const struct bhndb_hwcfg bhndb_pci_bcma_generic_hwcfg = {
 120         .resource_specs         = (const struct resource_spec[]) {
 121                 { SYS_RES_MEMORY,       PCIR_BAR(0),    RF_ACTIVE },
 122                 { -1,                   0,              0 }
 123         },
 124
 125         .register_windows       = (const struct bhndb_regwin[]) {
 126                 /* bar0+0x0000: configurable backplane window */
 127                 {
 128                         .win_type       = BHNDB_REGWIN_T_DYN,
 129                         .win_offset     = BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
 130                         .win_size       = BHNDB_PCI_V1_BAR0_WIN0_SIZE,
 131                         .d.dyn = {
 132                                 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL,
 133                         },
 134                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 135                 },
 136
 137                 /* bar0+0x3000: chipc core registers */
 138                 {
 139                         .win_type       = BHNDB_REGWIN_T_CORE,
 140                         .win_offset     = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET,
 141                         .win_size       = BHNDB_PCI_V1_BAR0_CCREGS_SIZE,
 142                         .d.core = {
 143                                 .class  = BHND_DEVCLASS_CC,
 144                                 .unit   = 0,
 145                                 .port   = 0,
 146                                 .region = 0,
 147                                 .port_type = BHND_PORT_DEVICE
 148                         },
 149                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 150                 },
 151
 152                 BHNDB_REGWIN_TABLE_END
 153         },
 154
 155         /* DMA unsupported under generic configuration */
 156         .dma_translations = NULL,
 157 };
 158
 159 /**
 160  * Hardware configuration tables for Broadcom HND PCI NICs.
 161  */
 162 const struct bhndb_hw bhndb_pci_generic_hw_table[] = {
 163         /* PCI/V0 WLAN */
 164         BHNDB_HW_MATCH("PCI/v0 WLAN", v0,
 165                 /* PCI Core */
 166                 {
 167                         BHND_MATCH_CORE_VENDOR  (BHND_MFGID_BCM),
 168                         BHND_MATCH_CORE_ID      (BHND_COREID_PCI),
 169                         BHND_MATCH_CORE_REV(
 170                             HWREV_LTE           (BHNDB_PCI_V0_MAX_PCI_HWREV)),
 171                         BHND_MATCH_CORE_CLASS   (BHND_DEVCLASS_PCI),
 172                         BHND_MATCH_CORE_UNIT    (0)
 173                 },
 174
 175                 /* 802.11 Core */
 176                 {
 177                         BHND_MATCH_CORE_VENDOR  (BHND_MFGID_BCM),
 178                         BHND_MATCH_CORE_CLASS   (BHND_DEVCLASS_WLAN),
 179                         BHND_MATCH_CORE_UNIT    (0)
 180                 }
 181         ),
 182
 183         /* PCI/V1 WLAN */
 184         BHNDB_HW_MATCH("PCI/v1 WLAN", v1_pci,
 185                 /* PCI Core */
 186                 {
 187                         BHND_MATCH_CORE_VENDOR  (BHND_MFGID_BCM),
 188                         BHND_MATCH_CORE_ID      (BHND_COREID_PCI),
 189                         BHND_MATCH_CORE_REV(
 190                             HWREV_GTE           (BHNDB_PCI_V1_MIN_PCI_HWREV)),
 191                         BHND_MATCH_CORE_CLASS   (BHND_DEVCLASS_PCI),
 192                         BHND_MATCH_CORE_UNIT    (0)
 193                 },
 194
 195                 /* 802.11 Core */
 196                 {
 197                         BHND_MATCH_CORE_VENDOR  (BHND_MFGID_BCM),
 198                         BHND_MATCH_CORE_CLASS   (BHND_DEVCLASS_WLAN),
 199                         BHND_MATCH_CORE_UNIT    (0)
 200                 }
 201         ),
 202
 203         /* PCIE/V1 WLAN */
 204         BHNDB_HW_MATCH("PCIe/v1 WLAN", v1_pcie,
 205                 /* PCIe Core */
 206                 {
 207                         BHND_MATCH_CORE_VENDOR  (BHND_MFGID_BCM),
 208                         BHND_MATCH_CORE_ID      (BHND_COREID_PCIE),
 209                         BHND_MATCH_CORE_CLASS   (BHND_DEVCLASS_PCIE),
 210                         BHND_MATCH_CORE_UNIT    (0)
 211                 },
 212
 213                 /* ChipCommon (revision <= 31) */
 214                 {
 215                         BHND_MATCH_CORE_VENDOR  (BHND_MFGID_BCM),
 216                         BHND_MATCH_CORE_ID      (BHND_COREID_CC),
 217                         BHND_MATCH_CORE_REV(
 218                             HWREV_LTE           (BHNDB_PCI_V1_MAX_CHIPC_HWREV)),
 219                         BHND_MATCH_CORE_CLASS   (BHND_DEVCLASS_CC),
 220                         BHND_MATCH_CORE_UNIT    (0)
 221                 },
 222
 223                 /* 802.11 Core */
 224                 {
 225                         BHND_MATCH_CORE_VENDOR  (BHND_MFGID_BCM),
 226                         BHND_MATCH_CORE_CLASS   (BHND_DEVCLASS_WLAN),
 227                         BHND_MATCH_CORE_UNIT    (0)
 228                 }
 229         ),
 230
 231         /* PCIE/V2 WLAN */
 232         BHNDB_HW_MATCH("PCIe/v2 WLAN", v2,
 233                 /* PCIe Core */
 234                 {
 235                         BHND_MATCH_CORE_VENDOR  (BHND_MFGID_BCM),
 236                         BHND_MATCH_CORE_ID      (BHND_COREID_PCIE),
 237                         BHND_MATCH_CORE_CLASS   (BHND_DEVCLASS_PCIE),
 238                         BHND_MATCH_CORE_UNIT    (0)
 239                 },
 240
 241                 /* ChipCommon (revision >= 32) */
 242                 {
 243                         BHND_MATCH_CORE_VENDOR  (BHND_MFGID_BCM),
 244                         BHND_MATCH_CORE_ID      (BHND_COREID_CC),
 245                         BHND_MATCH_CORE_REV(
 246                             HWREV_GTE           (BHNDB_PCI_V2_MIN_CHIPC_HWREV)),
 247                         BHND_MATCH_CORE_CLASS   (BHND_DEVCLASS_CC),
 248                         BHND_MATCH_CORE_UNIT    (0)
 249                 },
 250
 251                 /* 802.11 Core */
 252                 {
 253                         BHND_MATCH_CORE_VENDOR  (BHND_MFGID_BCM),
 254                         BHND_MATCH_CORE_CLASS   (BHND_DEVCLASS_WLAN),
 255                         BHND_MATCH_CORE_UNIT    (0)
 256                 }
 257         ),
 258
 259         /* PCIE/V3 WLAN */
 260         BHNDB_HW_MATCH("PCIe-Gen2/v3 WLAN", v3,
 261                 /* PCIe Gen2 Core */
 262                 {
 263                         BHND_MATCH_CORE_VENDOR  (BHND_MFGID_BCM),
 264                         BHND_MATCH_CORE_ID      (BHND_COREID_PCIE2),
 265                         BHND_MATCH_CORE_CLASS   (BHND_DEVCLASS_PCIE),
 266                         BHND_MATCH_CORE_UNIT    (0)
 267                 },
 268
 269                 /* 802.11 Core */
 270                 {
 271                         BHND_MATCH_CORE_VENDOR  (BHND_MFGID_BCM),
 272                         BHND_MATCH_CORE_CLASS   (BHND_DEVCLASS_WLAN),
 273                         BHND_MATCH_CORE_UNIT    (0)
 274                 }
 275         ),
 276         { NULL, NULL, 0, NULL }
 277 };
 278
 279 /**
 280  * PCI_V0 hardware configuration.
 281  *
 282  * Applies to:
 283  * - PCI (cid=0x804, revision <= 12)
 284  */
 285 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v0 = {
 286         .resource_specs         = (const struct resource_spec[]) {
 287                 { SYS_RES_MEMORY,       PCIR_BAR(0),    RF_ACTIVE },
 288                 { -1,                   0,              0 }
 289         },
 290
 291         .register_windows       = (const struct bhndb_regwin[]) {
 292                 /* bar0+0x0000: configurable backplane window */
 293                 {
 294                         .win_type       = BHNDB_REGWIN_T_DYN,
 295                         .win_offset     = BHNDB_PCI_V0_BAR0_WIN0_OFFSET,
 296                         .win_size       = BHNDB_PCI_V0_BAR0_WIN0_SIZE,
 297                         .d.dyn = {
 298                                 .cfg_offset = BHNDB_PCI_V0_BAR0_WIN0_CONTROL
 299                         },
 300                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 301                 },
 302
 303                 /* bar0+0x1000: sprom shadow */
 304                 {
 305                         .win_type       = BHNDB_REGWIN_T_SPROM,
 306                         .win_offset     = BHNDB_PCI_V0_BAR0_SPROM_OFFSET,
 307                         .win_size       = BHNDB_PCI_V0_BAR0_SPROM_SIZE,
 308                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 309                 },
 310
 311                 /*
 312                  * bar0+0x1800: pci core registers.
 313                  *
 314                  * Does not include the SSB CFG registers found at the end of
 315                  * the 4K core register block; these are mapped non-contigiously
 316                  * by the next entry.
 317                  */
 318                 {
 319                         .win_type       = BHNDB_REGWIN_T_CORE,
 320                         .win_offset     = BHNDB_PCI_V0_BAR0_PCIREG_OFFSET,
 321                         .win_size       = BHNDB_PCI_V0_BAR0_PCIREG_SIZE,
 322                         .d.core = {
 323                                 .class  = BHND_DEVCLASS_PCI,
 324                                 .unit   = 0,
 325                                 .port   = 0,
 326                                 .region = 0,
 327                                 .port_type = BHND_PORT_DEVICE,
 328                         },
 329                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 330                 },
 331
 332                 /* bar0+0x1E00: pci core (SSB CFG registers) */
 333                 {
 334                         .win_type       = BHNDB_REGWIN_T_CORE,
 335                         .win_offset     = BHNDB_PCI_V0_BAR0_PCISB_OFFSET        ,
 336                         .win_size       = BHNDB_PCI_V0_BAR0_PCISB_SIZE,
 337                         .d.core = {
 338                                 .class  = BHND_DEVCLASS_PCI,
 339                                 .unit   = 0,
 340                                 .port   = 0,
 341                                 .region = 0,
 342                                 .offset = BHNDB_PCI_V0_BAR0_PCISB_COREOFF,
 343                                 .port_type = BHND_PORT_DEVICE
 344                         },
 345                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 346                 },
 347
 348                 BHNDB_REGWIN_TABLE_END
 349         },
 350
 351         .dma_translations = (const struct bhnd_dma_translation[]) {
 352                 {
 353                         .base_addr      = BHND_PCI_DMA32_TRANSLATION,
 354                         .addr_mask      = ~BHND_PCI_DMA32_MASK,
 355                         .addrext_mask   = BHND_PCI_DMA32_MASK
 356                 },
 357                 BHND_DMA_TRANSLATION_TABLE_END
 358         }
 359 };
 360
 361 /**
 362  * PCI_V1 (PCI-only) hardware configuration (PCI version)
 363  *
 364  * Applies to:
 365  * - PCI (cid=0x804, revision >= 13)
 366  */
 367 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci = {
 368         .resource_specs         = (const struct resource_spec[]) {
 369                 { SYS_RES_MEMORY,       PCIR_BAR(0),    RF_ACTIVE },
 370                 { -1,                   0,              0 }
 371         },
 372
 373         .register_windows       = (const struct bhndb_regwin[]) {
 374                 /* bar0+0x0000: configurable backplane window */
 375                 {
 376                         .win_type       = BHNDB_REGWIN_T_DYN,
 377                         .win_offset     = BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
 378                         .win_size       = BHNDB_PCI_V1_BAR0_WIN0_SIZE,
 379                         .d.dyn = {
 380                                 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL
 381                         },
 382                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 383                 },
 384
 385                 /* bar0+0x1000: sprom shadow */
 386                 {
 387                         .win_type       = BHNDB_REGWIN_T_SPROM,
 388                         .win_offset     = BHNDB_PCI_V1_BAR0_SPROM_OFFSET,
 389                         .win_size       = BHNDB_PCI_V1_BAR0_SPROM_SIZE,
 390                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 391                 },
 392
 393                 /* bar0+0x2000: pci core registers */
 394                 {
 395                         .win_type       = BHNDB_REGWIN_T_CORE,
 396                         .win_offset     = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET,
 397                         .win_size       = BHNDB_PCI_V1_BAR0_PCIREG_SIZE,
 398                         .d.core = {
 399                                 .class  = BHND_DEVCLASS_PCI,
 400                                 .unit   = 0,
 401                                 .port   = 0,
 402                                 .region = 0,
 403                                 .port_type = BHND_PORT_DEVICE
 404                         },
 405                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 406                 },
 407
 408                 /* bar0+0x3000: chipc core registers */
 409                 {
 410                         .win_type       = BHNDB_REGWIN_T_CORE,
 411                         .win_offset     = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET,
 412                         .win_size       = BHNDB_PCI_V1_BAR0_CCREGS_SIZE,
 413                         .d.core = {
 414                                 .class  = BHND_DEVCLASS_CC,
 415                                 .unit   = 0,
 416                                 .port   = 0,
 417                                 .region = 0,
 418                                 .port_type = BHND_PORT_DEVICE
 419                         },
 420                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 421                 },
 422
 423                 BHNDB_REGWIN_TABLE_END
 424         },
 425
 426         .dma_translations = (const struct bhnd_dma_translation[]) {
 427                 {
 428                         .base_addr      = BHND_PCI_DMA32_TRANSLATION,
 429                         .addr_mask      = ~BHND_PCI_DMA32_MASK,
 430                         .addrext_mask   = BHND_PCI_DMA32_MASK
 431                 },
 432                 BHND_DMA_TRANSLATION_TABLE_END
 433         }
 434 };
 435
 436 /**
 437  * PCI_V1 hardware configuration (PCIE version).
 438  *
 439  * Applies to:
 440  * - PCIE (cid=0x820) with ChipCommon (revision <= 31)
 441  */
 442 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie = {
 443         .resource_specs         = (const struct resource_spec[]) {
 444                 { SYS_RES_MEMORY,       PCIR_BAR(0),    RF_ACTIVE },
 445                 { -1,                   0,              0 }
 446         },
 447
 448         .register_windows       = (const struct bhndb_regwin[]) {
 449                 /* bar0+0x0000: configurable backplane window */
 450                 {
 451                         .win_type       = BHNDB_REGWIN_T_DYN,
 452                         .win_offset     = BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
 453                         .win_size       = BHNDB_PCI_V1_BAR0_WIN0_SIZE,
 454                         .d.dyn = {
 455                                 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL
 456                         },
 457                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 458                 },
 459
 460                 /* bar0+0x1000: sprom shadow */
 461                 {
 462                         .win_type       = BHNDB_REGWIN_T_SPROM,
 463                         .win_offset     = BHNDB_PCI_V1_BAR0_SPROM_OFFSET,
 464                         .win_size       = BHNDB_PCI_V1_BAR0_SPROM_SIZE,
 465                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 466                 },
 467
 468                 /* bar0+0x2000: pci core registers */
 469                 {
 470                         .win_type       = BHNDB_REGWIN_T_CORE,
 471                         .win_offset     = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET,
 472                         .win_size       = BHNDB_PCI_V1_BAR0_PCIREG_SIZE,
 473                         .d.core = {
 474                                 .class  = BHND_DEVCLASS_PCIE,
 475                                 .unit   = 0,
 476                                 .port   = 0,
 477                                 .region = 0,
 478                                 .port_type = BHND_PORT_DEVICE
 479                         },
 480                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 481                 },
 482
 483                 /* bar0+0x3000: chipc core registers */
 484                 {
 485                         .win_type       = BHNDB_REGWIN_T_CORE,
 486                         .win_offset     = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET,
 487                         .win_size       = BHNDB_PCI_V1_BAR0_CCREGS_SIZE,
 488                         .d.core = {
 489                                 .class  = BHND_DEVCLASS_CC,
 490                                 .unit   = 0,
 491                                 .port   = 0,
 492                                 .region = 0,
 493                                 .port_type = BHND_PORT_DEVICE
 494                         },
 495                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 496                 },
 497
 498                 BHNDB_REGWIN_TABLE_END
 499         },
 500
 501         .dma_translations = (const struct bhnd_dma_translation[]) {
 502                 {
 503                         .base_addr      = BHND_PCIE_DMA32_TRANSLATION,
 504                         .addr_mask      = ~BHND_PCIE_DMA32_MASK,
 505                         .addrext_mask   = BHND_PCIE_DMA32_MASK
 506                 },
 507                 {
 508                         .base_addr      = BHND_PCIE_DMA64_TRANSLATION,
 509                         .addr_mask      = ~BHND_PCIE_DMA64_MASK,
 510                         .addrext_mask   = BHND_PCIE_DMA64_MASK
 511                 },
 512                 BHND_DMA_TRANSLATION_TABLE_END
 513         }
 514 };
 515
 516 /**
 517  * PCI_V2 hardware configuration.
 518  *
 519  * Applies to:
 520  * - PCIE (cid=0x820) with ChipCommon (revision >= 32)
 521  */
 522 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v2 = {
 523         .resource_specs         = (const struct resource_spec[]) {
 524                 { SYS_RES_MEMORY,       PCIR_BAR(0),    RF_ACTIVE },
 525                 { -1,                   0,              0 }
 526         },
 527
 528         .register_windows       = (const struct bhndb_regwin[]) {
 529                 /* bar0+0x0000: configurable backplane window */
 530                 {
 531                         .win_type       = BHNDB_REGWIN_T_DYN,
 532                         .win_offset     = BHNDB_PCI_V2_BAR0_WIN0_OFFSET,
 533                         .win_size       = BHNDB_PCI_V2_BAR0_WIN0_SIZE,
 534                         .d.dyn = {
 535                                 .cfg_offset = BHNDB_PCI_V2_BAR0_WIN0_CONTROL,
 536                         },
 537                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 538                 },
 539
 540                 /* bar0+0x1000: configurable backplane window */
 541                 {
 542                         .win_type       = BHNDB_REGWIN_T_DYN,
 543                         .win_offset     = BHNDB_PCI_V2_BAR0_WIN1_OFFSET,
 544                         .win_size       = BHNDB_PCI_V2_BAR0_WIN1_SIZE,
 545                         .d.dyn = {
 546                                 .cfg_offset = BHNDB_PCI_V2_BAR0_WIN1_CONTROL,
 547                         },
 548                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 549                 },
 550
 551                 /* bar0+0x2000: pcie core registers */
 552                 {
 553                         .win_type       = BHNDB_REGWIN_T_CORE,
 554                         .win_offset     = BHNDB_PCI_V2_BAR0_PCIREG_OFFSET,
 555                         .win_size       = BHNDB_PCI_V2_BAR0_PCIREG_SIZE,
 556                         .d.core = {
 557                                 .class  = BHND_DEVCLASS_PCIE,
 558                                 .unit   = 0,
 559                                 .port   = 0,
 560                                 .region = 0,
 561                                 .port_type = BHND_PORT_DEVICE
 562                         },
 563                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 564                 },
 565
 566                 /* bar0+0x3000: chipc core registers */
 567                 {
 568                         .win_type       = BHNDB_REGWIN_T_CORE,
 569                         .win_offset     = BHNDB_PCI_V2_BAR0_CCREGS_OFFSET,
 570                         .win_size       = BHNDB_PCI_V2_BAR0_CCREGS_SIZE,
 571                         .d.core = {
 572                                 .class  = BHND_DEVCLASS_CC,
 573                                 .unit   = 0,
 574                                 .port   = 0,
 575                                 .region = 0,
 576                                 .port_type = BHND_PORT_DEVICE
 577                         },
 578                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 579                 },
 580
 581                 BHNDB_REGWIN_TABLE_END
 582         },
 583
 584         .dma_translations = (const struct bhnd_dma_translation[]) {
 585                 {
 586                         .base_addr      = BHND_PCIE_DMA32_TRANSLATION,
 587                         .addr_mask      = ~BHND_PCIE_DMA32_MASK,
 588                         .addrext_mask   = BHND_PCIE_DMA32_MASK
 589                 },
 590                 {
 591                         .base_addr      = BHND_PCIE_DMA64_TRANSLATION,
 592                         .addr_mask      = ~BHND_PCIE_DMA64_MASK,
 593                         .addrext_mask   = BHND_PCIE_DMA64_MASK
 594                 },
 595                 BHND_DMA_TRANSLATION_TABLE_END
 596         }
 597 };
 598
 599 /**
 600  * PCI_V3 hardware configuration.
 601  *
 602  * Applies to:
 603  * - PCIE2 (cid=0x83c)
 604  */
 605 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v3 = {
 606         .resource_specs         = (const struct resource_spec[]) {
 607                 { SYS_RES_MEMORY,       PCIR_BAR(0),    RF_ACTIVE },
 608                 { -1,                   0,              0 }
 609         },
 610
 611         .register_windows       = (const struct bhndb_regwin[]) {
 612                 /* bar0+0x0000: configurable backplane window */
 613                 {
 614                         .win_type       = BHNDB_REGWIN_T_DYN,
 615                         .win_offset     = BHNDB_PCI_V3_BAR0_WIN0_OFFSET,
 616                         .win_size       = BHNDB_PCI_V3_BAR0_WIN0_SIZE,
 617                         .d.dyn = {
 618                                 .cfg_offset = BHNDB_PCI_V3_BAR0_WIN0_CONTROL,
 619                         },
 620                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 621                 },
 622
 623                 /* bar0+0x1000: configurable backplane window */
 624                 {
 625                         .win_type       = BHNDB_REGWIN_T_DYN,
 626                         .win_offset     = BHNDB_PCI_V3_BAR0_WIN1_OFFSET,
 627                         .win_size       = BHNDB_PCI_V3_BAR0_WIN1_SIZE,
 628                         .d.dyn = {
 629                                 .cfg_offset = BHNDB_PCI_V3_BAR0_WIN1_CONTROL,
 630                         },
 631                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 632                 },
 633
 634                 /* bar0+0x2000: pcie core registers */
 635                 {
 636                         .win_type       = BHNDB_REGWIN_T_CORE,
 637                         .win_offset     = BHNDB_PCI_V3_BAR0_PCIREG_OFFSET,
 638                         .win_size       = BHNDB_PCI_V3_BAR0_PCIREG_SIZE,
 639                         .d.core = {
 640                                 .class  = BHND_DEVCLASS_PCIE,
 641                                 .unit   = 0,
 642                                 .port   = 0,
 643                                 .region = 0,
 644                                 .port_type = BHND_PORT_DEVICE
 645                         },
 646                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 647                 },
 648
 649                 /* bar0+0x3000: chipc core registers */
 650                 {
 651                         .win_type       = BHNDB_REGWIN_T_CORE,
 652                         .win_offset     = BHNDB_PCI_V3_BAR0_CCREGS_OFFSET,
 653                         .win_size       = BHNDB_PCI_V3_BAR0_CCREGS_SIZE,
 654                         .d.core = {
 655                                 .class  = BHND_DEVCLASS_CC,
 656                                 .unit   = 0,
 657                                 .port   = 0,
 658                                 .region = 0,
 659                                 .port_type = BHND_PORT_DEVICE
 660                         },
 661                         .res            = { SYS_RES_MEMORY, PCIR_BAR(0) }
 662                 },
 663
 664                 BHNDB_REGWIN_TABLE_END
 665         },
 666
 667         .dma_translations = (const struct bhnd_dma_translation[]) {
 668                 {
 669                         .base_addr      = BHND_PCIE2_DMA64_TRANSLATION,
 670                         .addr_mask      = ~BHND_PCIE2_DMA64_MASK,
 671                         .addrext_mask   = BHND_PCIE_DMA64_MASK
 672                 },
 673                 BHND_DMA_TRANSLATION_TABLE_END
 674         }
 675 };