2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Resource specifications and register maps for Broadcom PCI/PCIe cores
35 * configured as PCI-BHND bridges.
38 #include <sys/param.h>
41 #include <machine/bus.h>
43 #include <machine/resource.h>
45 #include <dev/pci/pcireg.h>
46 #include <dev/pci/pcivar.h>
48 #include <dev/bhnd/cores/pci/bhnd_pcireg.h>
49 #include <dev/bhnd/cores/pcie2/bhnd_pcie2_reg.h>
52 #include "bhndb_pcireg.h"
54 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v0;
55 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci;
56 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie;
57 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v2;
58 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v3;
61 * Define a bhndb_hw match entry.
63 * @param _name The entry name.
64 * @param _vers The configuration version associated with this entry.
66 #define BHNDB_HW_MATCH(_name, _vers, ...) { \
68 .hw_reqs = _BHNDB_HW_REQ_ARRAY(__VA_ARGS__), \
69 .num_hw_reqs = (sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)) / \
70 sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)[0])), \
71 .cfg = &bhndb_pci_hwcfg_ ## _vers \
74 #define _BHNDB_HW_REQ_ARRAY(...) (struct bhnd_core_match[]) { __VA_ARGS__ }
77 * Generic PCI-SIBA bridge configuration usable with all known siba(4)-based
78 * PCI devices; this configuration is adequate for enumerating a bridged
79 * siba(4) bus to determine the full hardware configuration.
82 * - Compatible with PCI_V0, PCI_V1, PCI_V2, and PCI_V3 devices.
83 * - Compatible with siba(4) bus enumeration.
84 * - Compatible with bcma(4) bus enumeration if the ChipCommon core is mapped
85 * at the default enumeration address (0x18000000).
87 const struct bhndb_hwcfg bhndb_pci_siba_generic_hwcfg = {
88 .resource_specs = (const struct resource_spec[]) {
89 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
93 .register_windows = (const struct bhndb_regwin[]) {
94 /* bar0+0x0000: configurable backplane window */
96 .win_type = BHNDB_REGWIN_T_DYN,
97 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
98 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE,
100 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL
102 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
104 BHNDB_REGWIN_TABLE_END
107 /* DMA unsupported under generic configuration */
108 .dma_translations = NULL,
113 * Generic PCI-BCMA bridge configuration usable with all known bcma(4)-based
114 * PCI devices; this configuration is adequate for enumerating a bridged
115 * bcma(4) bus to determine the full hardware configuration.
118 * - Compatible with PCI_V1, PCI_V2, and PCI_V3 devices.
119 * - Compatible with both siba(4) and bcma(4) bus enumeration.
121 const struct bhndb_hwcfg bhndb_pci_bcma_generic_hwcfg = {
122 .resource_specs = (const struct resource_spec[]) {
123 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
127 .register_windows = (const struct bhndb_regwin[]) {
128 /* bar0+0x0000: configurable backplane window */
130 .win_type = BHNDB_REGWIN_T_DYN,
131 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
132 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE,
134 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL,
136 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
139 /* bar0+0x3000: chipc core registers */
141 .win_type = BHNDB_REGWIN_T_CORE,
142 .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET,
143 .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE,
145 .class = BHND_DEVCLASS_CC,
149 .port_type = BHND_PORT_DEVICE
151 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
154 BHNDB_REGWIN_TABLE_END
157 /* DMA unsupported under generic configuration */
158 .dma_translations = NULL,
162 * Hardware configuration tables for Broadcom HND PCI NICs.
164 const struct bhndb_hw bhndb_pci_generic_hw_table[] = {
166 BHNDB_HW_MATCH("PCI/v0 WLAN", v0,
169 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
170 BHND_MATCH_CORE_ID (BHND_COREID_PCI),
172 HWREV_LTE (BHNDB_PCI_V0_MAX_PCI_HWREV)),
173 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCI),
174 BHND_MATCH_CORE_UNIT (0)
179 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
180 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN),
181 BHND_MATCH_CORE_UNIT (0)
186 BHNDB_HW_MATCH("PCI/v1 WLAN", v1_pci,
189 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
190 BHND_MATCH_CORE_ID (BHND_COREID_PCI),
192 HWREV_GTE (BHNDB_PCI_V1_MIN_PCI_HWREV)),
193 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCI),
194 BHND_MATCH_CORE_UNIT (0)
199 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
200 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN),
201 BHND_MATCH_CORE_UNIT (0)
206 BHNDB_HW_MATCH("PCIe/v1 WLAN", v1_pcie,
209 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
210 BHND_MATCH_CORE_ID (BHND_COREID_PCIE),
211 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCIE),
212 BHND_MATCH_CORE_UNIT (0)
215 /* ChipCommon (revision <= 31) */
217 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
218 BHND_MATCH_CORE_ID (BHND_COREID_CC),
220 HWREV_LTE (BHNDB_PCI_V1_MAX_CHIPC_HWREV)),
221 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_CC),
222 BHND_MATCH_CORE_UNIT (0)
227 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
228 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN),
229 BHND_MATCH_CORE_UNIT (0)
234 BHNDB_HW_MATCH("PCIe/v2 WLAN", v2,
237 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
238 BHND_MATCH_CORE_ID (BHND_COREID_PCIE),
239 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCIE),
240 BHND_MATCH_CORE_UNIT (0)
243 /* ChipCommon (revision >= 32) */
245 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
246 BHND_MATCH_CORE_ID (BHND_COREID_CC),
248 HWREV_GTE (BHNDB_PCI_V2_MIN_CHIPC_HWREV)),
249 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_CC),
250 BHND_MATCH_CORE_UNIT (0)
255 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
256 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN),
257 BHND_MATCH_CORE_UNIT (0)
263 BHNDB_HW_MATCH("PCIe-Gen2/v3 WLAN", v3,
266 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
267 BHND_MATCH_CORE_ID (BHND_COREID_PCIE2),
268 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCIE),
269 BHND_MATCH_CORE_UNIT (0)
274 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM),
275 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN),
276 BHND_MATCH_CORE_UNIT (0)
280 { NULL, NULL, 0, NULL }
284 * PCI_V0 hardware configuration.
287 * - PCI (cid=0x804, revision <= 12)
289 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v0 = {
290 .resource_specs = (const struct resource_spec[]) {
291 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
295 .register_windows = (const struct bhndb_regwin[]) {
296 /* bar0+0x0000: configurable backplane window */
298 .win_type = BHNDB_REGWIN_T_DYN,
299 .win_offset = BHNDB_PCI_V0_BAR0_WIN0_OFFSET,
300 .win_size = BHNDB_PCI_V0_BAR0_WIN0_SIZE,
302 .cfg_offset = BHNDB_PCI_V0_BAR0_WIN0_CONTROL
304 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
307 /* bar0+0x1000: sprom shadow */
309 .win_type = BHNDB_REGWIN_T_SPROM,
310 .win_offset = BHNDB_PCI_V0_BAR0_SPROM_OFFSET,
311 .win_size = BHNDB_PCI_V0_BAR0_SPROM_SIZE,
312 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
316 * bar0+0x1800: pci core registers.
318 * Does not include the SSB CFG registers found at the end of
319 * the 4K core register block; these are mapped non-contigiously
323 .win_type = BHNDB_REGWIN_T_CORE,
324 .win_offset = BHNDB_PCI_V0_BAR0_PCIREG_OFFSET,
325 .win_size = BHNDB_PCI_V0_BAR0_PCIREG_SIZE,
327 .class = BHND_DEVCLASS_PCI,
331 .port_type = BHND_PORT_DEVICE,
333 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
336 /* bar0+0x1E00: pci core (SSB CFG registers) */
338 .win_type = BHNDB_REGWIN_T_CORE,
339 .win_offset = BHNDB_PCI_V0_BAR0_PCISB_OFFSET ,
340 .win_size = BHNDB_PCI_V0_BAR0_PCISB_SIZE,
342 .class = BHND_DEVCLASS_PCI,
346 .offset = BHNDB_PCI_V0_BAR0_PCISB_COREOFF,
347 .port_type = BHND_PORT_DEVICE
349 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
352 BHNDB_REGWIN_TABLE_END
355 .dma_translations = (const struct bhnd_dma_translation[]) {
357 .base_addr = BHND_PCI_DMA32_TRANSLATION,
358 .addr_mask = ~BHND_PCI_DMA32_MASK,
359 .addrext_mask = BHND_PCI_DMA32_MASK
361 BHND_DMA_TRANSLATION_TABLE_END
366 * PCI_V1 (PCI-only) hardware configuration (PCI version)
369 * - PCI (cid=0x804, revision >= 13)
371 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci = {
372 .resource_specs = (const struct resource_spec[]) {
373 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
377 .register_windows = (const struct bhndb_regwin[]) {
378 /* bar0+0x0000: configurable backplane window */
380 .win_type = BHNDB_REGWIN_T_DYN,
381 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
382 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE,
384 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL
386 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
389 /* bar0+0x1000: sprom shadow */
391 .win_type = BHNDB_REGWIN_T_SPROM,
392 .win_offset = BHNDB_PCI_V1_BAR0_SPROM_OFFSET,
393 .win_size = BHNDB_PCI_V1_BAR0_SPROM_SIZE,
394 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
397 /* bar0+0x2000: pci core registers */
399 .win_type = BHNDB_REGWIN_T_CORE,
400 .win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET,
401 .win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE,
403 .class = BHND_DEVCLASS_PCI,
407 .port_type = BHND_PORT_DEVICE
409 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
412 /* bar0+0x3000: chipc core registers */
414 .win_type = BHNDB_REGWIN_T_CORE,
415 .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET,
416 .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE,
418 .class = BHND_DEVCLASS_CC,
422 .port_type = BHND_PORT_DEVICE
424 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
427 BHNDB_REGWIN_TABLE_END
430 .dma_translations = (const struct bhnd_dma_translation[]) {
432 .base_addr = BHND_PCI_DMA32_TRANSLATION,
433 .addr_mask = ~BHND_PCI_DMA32_MASK,
434 .addrext_mask = BHND_PCI_DMA32_MASK
436 BHND_DMA_TRANSLATION_TABLE_END
441 * PCI_V1 hardware configuration (PCIE version).
444 * - PCIE (cid=0x820) with ChipCommon (revision <= 31)
446 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie = {
447 .resource_specs = (const struct resource_spec[]) {
448 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
452 .register_windows = (const struct bhndb_regwin[]) {
453 /* bar0+0x0000: configurable backplane window */
455 .win_type = BHNDB_REGWIN_T_DYN,
456 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET,
457 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE,
459 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL
461 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
464 /* bar0+0x1000: sprom shadow */
466 .win_type = BHNDB_REGWIN_T_SPROM,
467 .win_offset = BHNDB_PCI_V1_BAR0_SPROM_OFFSET,
468 .win_size = BHNDB_PCI_V1_BAR0_SPROM_SIZE,
469 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
472 /* bar0+0x2000: pci core registers */
474 .win_type = BHNDB_REGWIN_T_CORE,
475 .win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET,
476 .win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE,
478 .class = BHND_DEVCLASS_PCIE,
482 .port_type = BHND_PORT_DEVICE
484 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
487 /* bar0+0x3000: chipc core registers */
489 .win_type = BHNDB_REGWIN_T_CORE,
490 .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET,
491 .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE,
493 .class = BHND_DEVCLASS_CC,
497 .port_type = BHND_PORT_DEVICE
499 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
502 BHNDB_REGWIN_TABLE_END
505 .dma_translations = (const struct bhnd_dma_translation[]) {
507 .base_addr = BHND_PCIE_DMA32_TRANSLATION,
508 .addr_mask = ~BHND_PCIE_DMA32_MASK,
509 .addrext_mask = BHND_PCIE_DMA32_MASK
512 .base_addr = BHND_PCIE_DMA64_TRANSLATION,
513 .addr_mask = ~BHND_PCIE_DMA64_MASK,
514 .addrext_mask = BHND_PCIE_DMA64_MASK
516 BHND_DMA_TRANSLATION_TABLE_END
521 * PCI_V2 hardware configuration.
524 * - PCIE (cid=0x820) with ChipCommon (revision >= 32)
526 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v2 = {
527 .resource_specs = (const struct resource_spec[]) {
528 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
532 .register_windows = (const struct bhndb_regwin[]) {
533 /* bar0+0x0000: configurable backplane window */
535 .win_type = BHNDB_REGWIN_T_DYN,
536 .win_offset = BHNDB_PCI_V2_BAR0_WIN0_OFFSET,
537 .win_size = BHNDB_PCI_V2_BAR0_WIN0_SIZE,
539 .cfg_offset = BHNDB_PCI_V2_BAR0_WIN0_CONTROL,
541 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
544 /* bar0+0x1000: configurable backplane window */
546 .win_type = BHNDB_REGWIN_T_DYN,
547 .win_offset = BHNDB_PCI_V2_BAR0_WIN1_OFFSET,
548 .win_size = BHNDB_PCI_V2_BAR0_WIN1_SIZE,
550 .cfg_offset = BHNDB_PCI_V2_BAR0_WIN1_CONTROL,
552 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
555 /* bar0+0x2000: pcie core registers */
557 .win_type = BHNDB_REGWIN_T_CORE,
558 .win_offset = BHNDB_PCI_V2_BAR0_PCIREG_OFFSET,
559 .win_size = BHNDB_PCI_V2_BAR0_PCIREG_SIZE,
561 .class = BHND_DEVCLASS_PCIE,
565 .port_type = BHND_PORT_DEVICE
567 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
570 /* bar0+0x3000: chipc core registers */
572 .win_type = BHNDB_REGWIN_T_CORE,
573 .win_offset = BHNDB_PCI_V2_BAR0_CCREGS_OFFSET,
574 .win_size = BHNDB_PCI_V2_BAR0_CCREGS_SIZE,
576 .class = BHND_DEVCLASS_CC,
580 .port_type = BHND_PORT_DEVICE
582 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
585 BHNDB_REGWIN_TABLE_END
588 .dma_translations = (const struct bhnd_dma_translation[]) {
590 .base_addr = BHND_PCIE_DMA32_TRANSLATION,
591 .addr_mask = ~BHND_PCIE_DMA32_MASK,
592 .addrext_mask = BHND_PCIE_DMA32_MASK
595 .base_addr = BHND_PCIE_DMA64_TRANSLATION,
596 .addr_mask = ~BHND_PCIE_DMA64_MASK,
597 .addrext_mask = BHND_PCIE_DMA64_MASK
599 BHND_DMA_TRANSLATION_TABLE_END
604 * PCI_V3 hardware configuration.
607 * - PCIE2 (cid=0x83c)
609 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v3 = {
610 .resource_specs = (const struct resource_spec[]) {
611 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
615 .register_windows = (const struct bhndb_regwin[]) {
616 /* bar0+0x0000: configurable backplane window */
618 .win_type = BHNDB_REGWIN_T_DYN,
619 .win_offset = BHNDB_PCI_V3_BAR0_WIN0_OFFSET,
620 .win_size = BHNDB_PCI_V3_BAR0_WIN0_SIZE,
622 .cfg_offset = BHNDB_PCI_V3_BAR0_WIN0_CONTROL,
624 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
627 /* bar0+0x1000: configurable backplane window */
629 .win_type = BHNDB_REGWIN_T_DYN,
630 .win_offset = BHNDB_PCI_V3_BAR0_WIN1_OFFSET,
631 .win_size = BHNDB_PCI_V3_BAR0_WIN1_SIZE,
633 .cfg_offset = BHNDB_PCI_V3_BAR0_WIN1_CONTROL,
635 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
638 /* bar0+0x2000: pcie core registers */
640 .win_type = BHNDB_REGWIN_T_CORE,
641 .win_offset = BHNDB_PCI_V3_BAR0_PCIREG_OFFSET,
642 .win_size = BHNDB_PCI_V3_BAR0_PCIREG_SIZE,
644 .class = BHND_DEVCLASS_PCIE,
648 .port_type = BHND_PORT_DEVICE
650 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
653 /* bar0+0x3000: chipc core registers */
655 .win_type = BHNDB_REGWIN_T_CORE,
656 .win_offset = BHNDB_PCI_V3_BAR0_CCREGS_OFFSET,
657 .win_size = BHNDB_PCI_V3_BAR0_CCREGS_SIZE,
659 .class = BHND_DEVCLASS_CC,
663 .port_type = BHND_PORT_DEVICE
665 .res = { SYS_RES_MEMORY, PCIR_BAR(0) }
668 BHNDB_REGWIN_TABLE_END
671 .dma_translations = (const struct bhnd_dma_translation[]) {
673 .base_addr = BHND_PCIE2_DMA64_TRANSLATION,
674 .addr_mask = ~BHND_PCIE2_DMA64_MASK,
675 .addrext_mask = BHND_PCIE_DMA64_MASK
677 BHND_DMA_TRANSLATION_TABLE_END