2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
3 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
13 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
14 * redistribution must be conditioned upon including a substantially
15 * similar Disclaimer requirement for further binary redistribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
21 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
22 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
23 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
26 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGES.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
35 * Broadcom ChipCommon driver.
37 * With the exception of some very early chipsets, the ChipCommon core
38 * has been included in all HND SoCs and chipsets based on the siba(4)
39 * and bcma(4) interconnects, providing a common interface to chipset
40 * identification, bus enumeration, UARTs, clocks, watchdog interrupts,
44 #include <sys/param.h>
45 #include <sys/kernel.h>
49 #include <sys/malloc.h>
50 #include <sys/module.h>
51 #include <sys/mutex.h>
52 #include <sys/systm.h>
54 #include <machine/bus.h>
55 #include <machine/resource.h>
57 #include <dev/bhnd/bhnd.h>
58 #include <dev/bhnd/bhndvar.h>
63 #include "chipc_private.h"
65 devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */
67 static struct bhnd_device_quirk chipc_quirks[];
69 /* Supported device identifiers */
70 static const struct bhnd_device chipc_devices[] = {
71 BHND_DEVICE(BCM, CC, NULL, chipc_quirks),
72 BHND_DEVICE(BCM, 4706_CC, NULL, chipc_quirks),
77 /* Device quirks table */
78 static struct bhnd_device_quirk chipc_quirks[] = {
79 /* HND OTP controller revisions */
80 BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */
81 BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */
82 BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */
84 /* IPX OTP controller revisions */
85 BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX),
86 BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX),
88 BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM),
89 BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT),
90 BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE),
92 /* 4706 variant quirks */
93 BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */
94 BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH),
97 BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM),
98 BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM),
99 BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM),
100 BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM),
103 BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
104 BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
105 BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
106 BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
108 BHND_DEVICE_QUIRK_END
111 // FIXME: IRQ shouldn't be hard-coded
112 #define CHIPC_MIPS_IRQ 2
114 static int chipc_add_children(struct chipc_softc *sc);
116 static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc,
117 struct chipc_caps *caps);
118 static int chipc_read_caps(struct chipc_softc *sc,
119 struct chipc_caps *caps);
121 static bool chipc_should_enable_muxed_sprom(
122 struct chipc_softc *sc);
123 static int chipc_enable_otp_power(struct chipc_softc *sc);
124 static void chipc_disable_otp_power(struct chipc_softc *sc);
125 static int chipc_enable_sprom_pins(struct chipc_softc *sc);
126 static void chipc_disable_sprom_pins(struct chipc_softc *sc);
128 static int chipc_try_activate_resource(struct chipc_softc *sc,
129 device_t child, int type, int rid,
130 struct resource *r, bool req_direct);
132 static int chipc_init_rman(struct chipc_softc *sc);
133 static void chipc_free_rman(struct chipc_softc *sc);
134 static struct rman *chipc_get_rman(struct chipc_softc *sc, int type);
136 /* quirk and capability flag convenience macros */
137 #define CHIPC_QUIRK(_sc, _name) \
138 ((_sc)->quirks & CHIPC_QUIRK_ ## _name)
140 #define CHIPC_CAP(_sc, _name) \
143 #define CHIPC_ASSERT_QUIRK(_sc, name) \
144 KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set"))
146 #define CHIPC_ASSERT_CAP(_sc, name) \
147 KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set"))
150 chipc_probe(device_t dev)
152 const struct bhnd_device *id;
154 id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0]));
158 bhnd_set_default_core_desc(dev);
159 return (BUS_PROBE_DEFAULT);
163 chipc_attach(device_t dev)
165 struct chipc_softc *sc;
168 sc = device_get_softc(dev);
170 sc->quirks = bhnd_device_quirks(dev, chipc_devices,
171 sizeof(chipc_devices[0]));
172 sc->sprom_refcnt = 0;
175 STAILQ_INIT(&sc->mem_regions);
177 /* Set up resource management */
178 if ((error = chipc_init_rman(sc))) {
179 device_printf(sc->dev,
180 "failed to initialize chipc resource state: %d\n", error);
184 /* Allocate the region containing the chipc register block */
185 if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) {
190 error = chipc_retain_region(sc, sc->core_region,
191 RF_ALLOCATED|RF_ACTIVE);
193 sc->core_region = NULL;
197 /* Save a direct reference to our chipc registers */
198 sc->core = sc->core_region->cr_res;
200 /* Fetch and parse capability register(s) */
201 if ((error = chipc_read_caps(sc, &sc->caps)))
205 chipc_print_caps(sc->dev, &sc->caps);
207 /* Attach all supported child devices */
208 if ((error = chipc_add_children(sc)))
211 if ((error = bus_generic_attach(dev)))
217 device_delete_children(sc->dev);
219 if (sc->core_region != NULL) {
220 chipc_release_region(sc, sc->core_region,
221 RF_ALLOCATED|RF_ACTIVE);
225 CHIPC_LOCK_DESTROY(sc);
230 chipc_detach(device_t dev)
232 struct chipc_softc *sc;
235 sc = device_get_softc(dev);
237 if ((error = bus_generic_detach(dev)))
240 chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE);
243 CHIPC_LOCK_DESTROY(sc);
249 chipc_add_children(struct chipc_softc *sc)
252 const char *flash_bus;
256 if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM ||
257 sc->caps.nvram_src == BHND_NVRAM_SRC_OTP)
259 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", -1);
261 device_printf(sc->dev, "failed to add nvram device\n");
265 /* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */
266 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0,
267 CHIPC_SPROM_OTP, CHIPC_SPROM_OTP_SIZE, 0, 0);
275 * On AOB ("Always on Bus") devices, the PMU core (if it exists) is
276 * attached directly to the bhnd(4) bus -- not chipc.
278 if (sc->caps.pwr_ctrl || (sc->caps.pmu && !sc->caps.aob)) {
279 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", -1);
281 device_printf(sc->dev, "failed to add pmu\n");
286 /* All remaining devices are SoC-only */
287 if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE)
291 for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) {
292 child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1);
294 device_printf(sc->dev, "failed to add uart%u\n", i);
299 error = bus_set_resource(child, SYS_RES_IRQ, 0, CHIPC_MIPS_IRQ,
302 device_printf(sc->dev, "failed to set uart%u irq %u\n",
307 /* UART registers are mapped sequentially */
308 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0,
309 CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0);
315 flash_bus = chipc_flash_bus_name(sc->caps.flash_type);
316 if (flash_bus != NULL) {
317 child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, -1);
319 device_printf(sc->dev, "failed to add %s device\n",
324 /* flash memory mapping */
325 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0,
326 0, RM_MAX_END, 1, 1);
330 /* flashctrl registers */
331 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 1,
332 CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0);
341 * Determine the NVRAM data source for this device.
343 * The SPROM, OTP, and flash capability flags must be fully populated in
346 * @param sc chipc driver state.
347 * @param caps capability flags to be used to derive NVRAM configuration.
349 static bhnd_nvram_src
350 chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps)
352 uint32_t otp_st, srom_ctrl;
355 * We check for hardware presence in order of precedence. For example,
356 * SPROM is is always used in preference to internal OTP if found.
358 if (CHIPC_QUIRK(sc, SUPPORTS_SPROM) && caps->sprom) {
359 srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL);
360 if (srom_ctrl & CHIPC_SRC_PRESENT)
361 return (BHND_NVRAM_SRC_SPROM);
364 /* Check for programmed OTP H/W subregion (contains SROM data) */
365 if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) {
366 /* TODO: need access to HND-OTP device */
367 if (!CHIPC_QUIRK(sc, OTP_HND)) {
368 device_printf(sc->dev,
369 "NVRAM unavailable: unsupported OTP controller.\n");
370 return (BHND_NVRAM_SRC_UNKNOWN);
373 otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST);
374 if (otp_st & CHIPC_OTPS_GUP_HW)
375 return (BHND_NVRAM_SRC_OTP);
378 /* Check for flash */
379 if (caps->flash_type != CHIPC_FLASH_NONE)
380 return (BHND_NVRAM_SRC_FLASH);
382 /* No NVRAM hardware capability declared */
383 return (BHND_NVRAM_SRC_UNKNOWN);
386 /* Read and parse chipc capabilities */
388 chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps)
391 uint32_t cap_ext_reg;
394 /* Fetch cap registers */
395 cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES);
397 if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT))
398 cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT);
401 caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART);
402 caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB);
403 caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO);
404 caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL);
406 caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS);
407 caps->pwr_ctrl = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL);
408 caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP);
410 caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL);
411 caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64);
412 caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM);
413 caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU);
414 caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI);
415 caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM);
416 caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE);
418 caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI);
419 caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO);
420 caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB);
422 /* Fetch OTP size for later IPX controller revisions */
423 if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) {
424 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT);
425 caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE);
428 /* Determine flash type and parameters */
430 switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) {
431 case CHIPC_CAP_SFLASH_ST:
432 caps->flash_type = CHIPC_SFLASH_ST;
434 case CHIPC_CAP_SFLASH_AT:
435 caps->flash_type = CHIPC_SFLASH_AT;
437 case CHIPC_CAP_NFLASH:
439 caps->flash_type = CHIPC_NFLASH;
441 case CHIPC_CAP_PFLASH:
442 caps->flash_type = CHIPC_PFLASH_CFI;
444 /* determine cfi width */
445 regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG);
446 if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS))
452 case CHIPC_CAP_FLASH_NONE:
453 caps->flash_type = CHIPC_FLASH_NONE;
458 /* Handle 4706_NFLASH fallback */
459 if (CHIPC_QUIRK(sc, 4706_NFLASH) &&
460 CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH))
462 caps->flash_type = CHIPC_NFLASH_4706;
466 /* Determine NVRAM source. Must occur after the SPROM/OTP/flash
467 * capability flags have been populated. */
468 caps->nvram_src = chipc_find_nvram_src(sc, caps);
470 /* Determine the SPROM offset within OTP (if any). SPROM-formatted
471 * data is placed within the OTP general use region. */
472 caps->sprom_offset = 0;
473 if (caps->nvram_src == BHND_NVRAM_SRC_OTP) {
474 CHIPC_ASSERT_QUIRK(sc, OTP_IPX);
476 /* Bit offset to GUP HW subregion containing SPROM data */
477 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT);
478 caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP);
480 /* Convert to bytes */
481 caps->sprom_offset /= 8;
488 chipc_suspend(device_t dev)
490 return (bus_generic_suspend(dev));
494 chipc_resume(device_t dev)
496 return (bus_generic_resume(dev));
500 chipc_probe_nomatch(device_t dev, device_t child)
502 struct resource_list *rl;
505 name = device_get_name(child);
507 name = "unknown device";
509 device_printf(dev, "<%s> at", name);
511 rl = BUS_GET_RESOURCE_LIST(dev, child);
513 resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx");
514 resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd");
517 printf(" (no driver attached)\n");
521 chipc_print_child(device_t dev, device_t child)
523 struct resource_list *rl;
526 retval += bus_print_child_header(dev, child);
528 rl = BUS_GET_RESOURCE_LIST(dev, child);
530 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY,
532 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ,
536 retval += bus_print_child_domain(dev, child);
537 retval += bus_print_child_footer(dev, child);
543 chipc_child_pnpinfo_str(device_t dev, device_t child, char *buf,
554 chipc_child_location_str(device_t dev, device_t child, char *buf,
565 chipc_add_child(device_t dev, u_int order, const char *name, int unit)
567 struct chipc_softc *sc;
568 struct chipc_devinfo *dinfo;
571 sc = device_get_softc(dev);
573 child = device_add_child_ordered(dev, order, name, unit);
577 dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT);
579 device_delete_child(dev, child);
583 resource_list_init(&dinfo->resources);
584 device_set_ivars(child, dinfo);
590 chipc_child_deleted(device_t dev, device_t child)
592 struct chipc_devinfo *dinfo = device_get_ivars(child);
595 resource_list_free(&dinfo->resources);
599 device_set_ivars(child, NULL);
602 static struct resource_list *
603 chipc_get_resource_list(device_t dev, device_t child)
605 struct chipc_devinfo *dinfo = device_get_ivars(child);
606 return (&dinfo->resources);
610 /* Allocate region records for the given port, and add the port's memory
611 * range to the mem_rman */
613 chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type,
616 struct chipc_region *cr;
617 rman_res_t start, end;
621 num_regions = bhnd_get_region_count(sc->dev, type, port);
622 for (u_int region = 0; region < num_regions; region++) {
623 /* Allocate new region record */
624 cr = chipc_alloc_region(sc, type, port, region);
628 /* Can't manage regions that cannot be allocated */
629 if (cr->cr_rid < 0) {
630 BHND_DEBUG_DEV(sc->dev, "no rid for chipc region "
631 "%s%u.%u", bhnd_port_type_name(type), port, region);
632 chipc_free_region(sc, cr);
636 /* Add to rman's managed range */
639 if ((error = rman_manage_region(&sc->mem_rman, start, end))) {
640 chipc_free_region(sc, cr);
644 /* Add to region list */
645 STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link);
651 /* Initialize memory state for all chipc port regions */
653 chipc_init_rman(struct chipc_softc *sc)
658 /* Port types for which we'll register chipc_region mappings */
659 bhnd_port_type types[] = {
663 /* Initialize resource manager */
664 sc->mem_rman.rm_start = 0;
665 sc->mem_rman.rm_end = BUS_SPACE_MAXADDR;
666 sc->mem_rman.rm_type = RMAN_ARRAY;
667 sc->mem_rman.rm_descr = "ChipCommon Device Memory";
668 if ((error = rman_init(&sc->mem_rman))) {
669 device_printf(sc->dev, "could not initialize mem_rman: %d\n",
674 /* Populate per-port-region state */
675 for (u_int i = 0; i < nitems(types); i++) {
676 num_ports = bhnd_get_port_count(sc->dev, types[i]);
677 for (u_int port = 0; port < num_ports; port++) {
678 error = chipc_rman_init_regions(sc, types[i], port);
680 device_printf(sc->dev,
681 "region init failed for %s%u: %d\n",
682 bhnd_port_type_name(types[i]), port,
697 /* Free memory management state */
699 chipc_free_rman(struct chipc_softc *sc)
701 struct chipc_region *cr, *cr_next;
703 STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next)
704 chipc_free_region(sc, cr);
706 rman_fini(&sc->mem_rman);
710 * Return the rman instance for a given resource @p type, if any.
712 * @param sc The chipc device state.
713 * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...)
716 chipc_get_rman(struct chipc_softc *sc, int type)
720 return (&sc->mem_rman);
723 /* IRQs can be used with RF_SHAREABLE, so we don't perform
724 * any local proxying of resource requests. */
732 static struct resource *
733 chipc_alloc_resource(device_t dev, device_t child, int type,
734 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
736 struct chipc_softc *sc;
737 struct chipc_region *cr;
738 struct resource_list_entry *rle;
742 bool passthrough, isdefault;
744 sc = device_get_softc(dev);
745 passthrough = (device_get_parent(child) != dev);
746 isdefault = RMAN_IS_DEFAULT_RANGE(start, end);
749 /* Fetch the resource manager, delegate request if necessary */
750 rm = chipc_get_rman(sc, type);
752 /* Requested resource type is delegated to our parent */
753 rv = bus_generic_rl_alloc_resource(dev, child, type, rid,
754 start, end, count, flags);
758 /* Populate defaults */
759 if (!passthrough && isdefault) {
760 /* Fetch the resource list entry. */
761 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child),
765 "default resource %#x type %d for child %s "
766 "not found\n", *rid, type,
767 device_get_nameunit(child));
771 if (rle->res != NULL) {
773 "resource entry %#x type %d for child %s is busy "
775 *rid, type, device_get_nameunit(child),
776 rman_get_flags(rle->res));
783 count = ulmax(count, rle->count);
786 /* Locate a mapping region */
787 if ((cr = chipc_find_region(sc, start, end)) == NULL) {
788 /* Resource requests outside our shared port regions can be
789 * delegated to our parent. */
790 rv = bus_generic_rl_alloc_resource(dev, child, type, rid,
791 start, end, count, flags);
795 /* Try to retain a region reference */
796 if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED)))
799 /* Make our rman reservation */
800 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE,
803 chipc_release_region(sc, cr, RF_ALLOCATED);
807 rman_set_rid(rv, *rid);
810 if (flags & RF_ACTIVE) {
811 error = bus_activate_resource(child, type, *rid, rv);
814 "failed to activate entry %#x type %d for "
816 *rid, type, device_get_nameunit(child), error);
818 chipc_release_region(sc, cr, RF_ALLOCATED);
819 rman_release_resource(rv);
825 /* Update child's resource list entry */
828 rle->start = rman_get_start(rv);
829 rle->end = rman_get_end(rv);
830 rle->count = rman_get_size(rv);
837 chipc_release_resource(device_t dev, device_t child, int type, int rid,
840 struct chipc_softc *sc;
841 struct chipc_region *cr;
843 struct resource_list_entry *rle;
846 sc = device_get_softc(dev);
848 /* Handled by parent bus? */
849 rm = chipc_get_rman(sc, type);
850 if (rm == NULL || !rman_is_region_manager(r, rm)) {
851 return (bus_generic_rl_release_resource(dev, child, type, rid,
855 /* Locate the mapping region */
856 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
860 /* Deactivate resources */
861 if (rman_get_flags(r) & RF_ACTIVE) {
862 error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r);
867 if ((error = rman_release_resource(r)))
870 /* Drop allocation reference */
871 chipc_release_region(sc, cr, RF_ALLOCATED);
873 /* Clear reference from the resource list entry if exists */
874 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid);
882 chipc_adjust_resource(device_t dev, device_t child, int type,
883 struct resource *r, rman_res_t start, rman_res_t end)
885 struct chipc_softc *sc;
886 struct chipc_region *cr;
889 sc = device_get_softc(dev);
891 /* Handled by parent bus? */
892 rm = chipc_get_rman(sc, type);
893 if (rm == NULL || !rman_is_region_manager(r, rm)) {
894 return (bus_generic_adjust_resource(dev, child, type, r, start,
898 /* The range is limited to the existing region mapping */
899 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
906 if (start < cr->cr_addr || end > cr->cr_end)
909 /* Range falls within the existing region */
910 return (rman_adjust_resource(r, start, end));
914 * Retain an RF_ACTIVE reference to the region mapping @p r, and
915 * configure @p r with its subregion values.
917 * @param sc Driver instance state.
918 * @param child Requesting child device.
919 * @param type resource type of @p r.
920 * @param rid resource id of @p r
921 * @param r resource to be activated.
922 * @param req_direct If true, failure to allocate a direct bhnd resource
923 * will be treated as an error. If false, the resource will not be marked
924 * as RF_ACTIVE if bhnd direct resource allocation fails.
927 chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type,
928 int rid, struct resource *r, bool req_direct)
931 struct chipc_region *cr;
932 bhnd_size_t cr_offset;
933 rman_res_t r_start, r_end, r_size;
936 rm = chipc_get_rman(sc, type);
937 if (rm == NULL || !rman_is_region_manager(r, rm))
940 r_start = rman_get_start(r);
941 r_end = rman_get_end(r);
942 r_size = rman_get_size(r);
944 /* Find the corresponding chipc region */
945 cr = chipc_find_region(sc, r_start, r_end);
949 /* Calculate subregion offset within the chipc region */
950 cr_offset = r_start - cr->cr_addr;
952 /* Retain (and activate, if necessary) the chipc region */
953 if ((error = chipc_retain_region(sc, cr, RF_ACTIVE)))
956 /* Configure child resource with its subregion values. */
957 if (cr->cr_res->direct) {
958 error = chipc_init_child_resource(r, cr->cr_res->res,
964 if ((error = rman_activate_resource(r)))
966 } else if (req_direct) {
974 chipc_release_region(sc, cr, RF_ACTIVE);
979 chipc_activate_bhnd_resource(device_t dev, device_t child, int type,
980 int rid, struct bhnd_resource *r)
982 struct chipc_softc *sc;
986 sc = device_get_softc(dev);
988 /* Delegate non-locally managed resources to parent */
989 rm = chipc_get_rman(sc, type);
990 if (rm == NULL || !rman_is_region_manager(r->res, rm)) {
991 return (bhnd_bus_generic_activate_resource(dev, child, type,
995 /* Try activating the chipc region resource */
996 error = chipc_try_activate_resource(sc, child, type, rid, r->res,
1001 /* Mark the child resource as direct according to the returned resource
1003 if (rman_get_flags(r->res) & RF_ACTIVE)
1010 chipc_activate_resource(device_t dev, device_t child, int type, int rid,
1013 struct chipc_softc *sc;
1016 sc = device_get_softc(dev);
1018 /* Delegate non-locally managed resources to parent */
1019 rm = chipc_get_rman(sc, type);
1020 if (rm == NULL || !rman_is_region_manager(r, rm)) {
1021 return (bus_generic_activate_resource(dev, child, type, rid,
1025 /* Try activating the chipc region-based resource */
1026 return (chipc_try_activate_resource(sc, child, type, rid, r, true));
1030 * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE().
1033 chipc_deactivate_resource(device_t dev, device_t child, int type,
1034 int rid, struct resource *r)
1036 struct chipc_softc *sc;
1037 struct chipc_region *cr;
1041 sc = device_get_softc(dev);
1043 /* Handled by parent bus? */
1044 rm = chipc_get_rman(sc, type);
1045 if (rm == NULL || !rman_is_region_manager(r, rm)) {
1046 return (bus_generic_deactivate_resource(dev, child, type, rid,
1050 /* Find the corresponding chipc region */
1051 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
1056 if ((error = rman_deactivate_resource(r)))
1059 /* Drop associated RF_ACTIVE reference */
1060 chipc_release_region(sc, cr, RF_ACTIVE);
1066 * Examine bus state and make a best effort determination of whether it's
1067 * likely safe to enable the muxed SPROM pins.
1069 * On devices that do not use SPROM pin muxing, always returns true.
1071 * @param sc chipc driver state.
1074 chipc_should_enable_muxed_sprom(struct chipc_softc *sc)
1083 /* Nothing to do? */
1084 if (!CHIPC_QUIRK(sc, MUX_SPROM))
1087 mtx_lock(&Giant); /* for newbus */
1089 parent = device_get_parent(sc->dev);
1090 hostb = bhnd_find_hostb_device(parent);
1092 if ((error = device_get_children(parent, &devs, &devcount))) {
1097 /* Reject any active devices other than ChipCommon, or the
1098 * host bridge (if any). */
1100 for (int i = 0; i < devcount; i++) {
1101 if (devs[i] == hostb || devs[i] == sc->dev)
1104 if (!device_is_attached(devs[i]))
1107 if (device_is_suspended(devs[i]))
1110 /* Active device; assume SPROM is busy */
1121 chipc_enable_sprom(device_t dev)
1123 struct chipc_softc *sc;
1126 sc = device_get_softc(dev);
1129 /* Already enabled? */
1130 if (sc->sprom_refcnt >= 1) {
1137 switch (sc->caps.nvram_src) {
1138 case BHND_NVRAM_SRC_SPROM:
1139 error = chipc_enable_sprom_pins(sc);
1141 case BHND_NVRAM_SRC_OTP:
1142 error = chipc_enable_otp_power(sc);
1149 /* Bump the reference count */
1158 chipc_disable_sprom(device_t dev)
1160 struct chipc_softc *sc;
1162 sc = device_get_softc(dev);
1165 /* Check reference count, skip disable if in-use. */
1166 KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease"));
1168 if (sc->sprom_refcnt > 0) {
1173 switch (sc->caps.nvram_src) {
1174 case BHND_NVRAM_SRC_SPROM:
1175 chipc_disable_sprom_pins(sc);
1177 case BHND_NVRAM_SRC_OTP:
1178 chipc_disable_otp_power(sc);
1189 chipc_enable_otp_power(struct chipc_softc *sc)
1191 // TODO: Enable OTP resource via PMU, and wait up to 100 usec for
1192 // OTPS_READY to be set in `optstatus`.
1197 chipc_disable_otp_power(struct chipc_softc *sc)
1199 // TODO: Disable OTP resource via PMU
1203 * If required by this device, enable access to the SPROM.
1205 * @param sc chipc driver state.
1208 chipc_enable_sprom_pins(struct chipc_softc *sc)
1212 CHIPC_LOCK_ASSERT(sc, MA_OWNED);
1213 KASSERT(sc->sprom_refcnt == 0, ("sprom pins already enabled"));
1215 /* Nothing to do? */
1216 if (!CHIPC_QUIRK(sc, MUX_SPROM))
1219 /* Check whether bus is busy */
1220 if (!chipc_should_enable_muxed_sprom(sc))
1223 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
1226 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) {
1227 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN;
1229 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM))
1230 cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5;
1232 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM))
1233 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2;
1235 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
1240 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) {
1244 /* Refuse to proceed on unsupported devices with muxed SPROM pins */
1245 device_printf(sc->dev, "muxed sprom lines on unrecognized device\n");
1250 * If required by this device, revert any GPIO/pin configuration applied
1251 * to allow SPROM access.
1253 * @param sc chipc driver state.
1256 chipc_disable_sprom_pins(struct chipc_softc *sc)
1260 /* Nothing to do? */
1261 if (!CHIPC_QUIRK(sc, MUX_SPROM))
1264 CHIPC_LOCK_ASSERT(sc, MA_OWNED);
1265 KASSERT(sc->sprom_refcnt == 0, ("sprom pins in use"));
1267 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
1270 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) {
1271 cctrl |= CHIPC_CCTRL4331_EXTPA_EN;
1273 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM))
1274 cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5;
1276 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM))
1277 cctrl |= CHIPC_CCTRL4331_EXTPA_EN2;
1279 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
1284 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) {
1290 chipc_read_chipst(device_t dev)
1292 struct chipc_softc *sc = device_get_softc(dev);
1293 return (bhnd_bus_read_4(sc->core, CHIPC_CHIPST));
1297 chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask)
1299 struct chipc_softc *sc;
1302 sc = device_get_softc(dev);
1306 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
1307 cctrl = (cctrl & ~mask) | (value | mask);
1308 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
1313 static struct chipc_caps *
1314 chipc_get_caps(device_t dev)
1316 struct chipc_softc *sc;
1318 sc = device_get_softc(dev);
1322 static device_method_t chipc_methods[] = {
1323 /* Device interface */
1324 DEVMETHOD(device_probe, chipc_probe),
1325 DEVMETHOD(device_attach, chipc_attach),
1326 DEVMETHOD(device_detach, chipc_detach),
1327 DEVMETHOD(device_suspend, chipc_suspend),
1328 DEVMETHOD(device_resume, chipc_resume),
1331 DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch),
1332 DEVMETHOD(bus_print_child, chipc_print_child),
1333 DEVMETHOD(bus_child_pnpinfo_str, chipc_child_pnpinfo_str),
1334 DEVMETHOD(bus_child_location_str, chipc_child_location_str),
1336 DEVMETHOD(bus_add_child, chipc_add_child),
1337 DEVMETHOD(bus_child_deleted, chipc_child_deleted),
1339 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
1340 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
1341 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource),
1342 DEVMETHOD(bus_alloc_resource, chipc_alloc_resource),
1343 DEVMETHOD(bus_release_resource, chipc_release_resource),
1344 DEVMETHOD(bus_adjust_resource, chipc_adjust_resource),
1345 DEVMETHOD(bus_activate_resource, chipc_activate_resource),
1346 DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource),
1347 DEVMETHOD(bus_get_resource_list, chipc_get_resource_list),
1349 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1350 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1351 DEVMETHOD(bus_config_intr, bus_generic_config_intr),
1352 DEVMETHOD(bus_bind_intr, bus_generic_bind_intr),
1353 DEVMETHOD(bus_describe_intr, bus_generic_describe_intr),
1355 /* BHND bus inteface */
1356 DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource),
1358 /* ChipCommon interface */
1359 DEVMETHOD(bhnd_chipc_read_chipst, chipc_read_chipst),
1360 DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl),
1361 DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom),
1362 DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom),
1363 DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps),
1368 DEFINE_CLASS_0(bhnd_chipc, bhnd_chipc_driver, chipc_methods, sizeof(struct chipc_softc));
1369 EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, bhnd_chipc_driver, bhnd_chipc_devclass, 0, 0,
1370 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
1371 MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1);
1372 MODULE_VERSION(bhnd_chipc, 1);