2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
5 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com>
6 * Copyright (c) 2017 The FreeBSD Foundation
9 * Portions of this software were developed by Landon Fuller
10 * under sponsorship from the FreeBSD Foundation.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer,
17 * without modification.
18 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
19 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
20 * redistribution must be conditioned upon including a substantially
21 * similar Disclaimer requirement for further binary redistribution.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
41 * Broadcom ChipCommon driver.
43 * With the exception of some very early chipsets, the ChipCommon core
44 * has been included in all HND SoCs and chipsets based on the siba(4)
45 * and bcma(4) interconnects, providing a common interface to chipset
46 * identification, bus enumeration, UARTs, clocks, watchdog interrupts,
50 #include <sys/param.h>
51 #include <sys/kernel.h>
55 #include <sys/malloc.h>
56 #include <sys/module.h>
57 #include <sys/mutex.h>
58 #include <sys/systm.h>
60 #include <machine/bus.h>
61 #include <machine/resource.h>
63 #include <dev/bhnd/bhnd.h>
64 #include <dev/bhnd/bhndvar.h>
69 #include "chipc_private.h"
71 devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */
73 static struct bhnd_device_quirk chipc_quirks[];
75 /* Supported device identifiers */
76 static const struct bhnd_device chipc_devices[] = {
77 BHND_DEVICE(BCM, CC, NULL, chipc_quirks),
78 BHND_DEVICE(BCM, 4706_CC, NULL, chipc_quirks),
83 /* Device quirks table */
84 static struct bhnd_device_quirk chipc_quirks[] = {
85 /* HND OTP controller revisions */
86 BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */
87 BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */
88 BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */
90 /* IPX OTP controller revisions */
91 BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX),
92 BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX),
94 BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM),
95 BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT),
96 BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE),
98 /* 4706 variant quirks */
99 BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */
100 BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH),
103 BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM),
104 BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM),
105 BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM),
106 BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM),
109 BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
110 BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
111 BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
112 BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
114 BHND_DEVICE_QUIRK_END
117 static int chipc_add_children(struct chipc_softc *sc);
119 static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc,
120 struct chipc_caps *caps);
121 static int chipc_read_caps(struct chipc_softc *sc,
122 struct chipc_caps *caps);
124 static bool chipc_should_enable_muxed_sprom(
125 struct chipc_softc *sc);
126 static int chipc_enable_otp_power(struct chipc_softc *sc);
127 static void chipc_disable_otp_power(struct chipc_softc *sc);
128 static int chipc_enable_sprom_pins(struct chipc_softc *sc);
129 static void chipc_disable_sprom_pins(struct chipc_softc *sc);
131 static int chipc_try_activate_resource(struct chipc_softc *sc,
132 device_t child, int type, int rid,
133 struct resource *r, bool req_direct);
135 static int chipc_init_rman(struct chipc_softc *sc);
136 static void chipc_free_rman(struct chipc_softc *sc);
137 static struct rman *chipc_get_rman(struct chipc_softc *sc, int type);
139 /* quirk and capability flag convenience macros */
140 #define CHIPC_QUIRK(_sc, _name) \
141 ((_sc)->quirks & CHIPC_QUIRK_ ## _name)
143 #define CHIPC_CAP(_sc, _name) \
146 #define CHIPC_ASSERT_QUIRK(_sc, name) \
147 KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set"))
149 #define CHIPC_ASSERT_CAP(_sc, name) \
150 KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set"))
153 chipc_probe(device_t dev)
155 const struct bhnd_device *id;
157 id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0]));
161 bhnd_set_default_core_desc(dev);
162 return (BUS_PROBE_DEFAULT);
166 chipc_attach(device_t dev)
168 struct chipc_softc *sc;
171 sc = device_get_softc(dev);
173 sc->quirks = bhnd_device_quirks(dev, chipc_devices,
174 sizeof(chipc_devices[0]));
175 sc->sprom_refcnt = 0;
178 STAILQ_INIT(&sc->mem_regions);
180 /* Set up resource management */
181 if ((error = chipc_init_rman(sc))) {
182 device_printf(sc->dev,
183 "failed to initialize chipc resource state: %d\n", error);
187 /* Allocate the region containing the chipc register block */
188 if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) {
193 error = chipc_retain_region(sc, sc->core_region,
194 RF_ALLOCATED|RF_ACTIVE);
196 sc->core_region = NULL;
200 /* Save a direct reference to our chipc registers */
201 sc->core = sc->core_region->cr_res;
203 /* Fetch and parse capability register(s) */
204 if ((error = chipc_read_caps(sc, &sc->caps)))
208 chipc_print_caps(sc->dev, &sc->caps);
210 /* Attach all supported child devices */
211 if ((error = chipc_add_children(sc)))
215 * Register ourselves with the bus; we're fully initialized and can
216 * response to ChipCommin API requests.
218 * Since our children may need access to ChipCommon, this must be done
219 * before attaching our children below (via bus_generic_attach).
221 if ((error = bhnd_register_provider(dev, BHND_SERVICE_CHIPC)))
224 if ((error = bus_generic_attach(dev)))
230 device_delete_children(sc->dev);
232 if (sc->core_region != NULL) {
233 chipc_release_region(sc, sc->core_region,
234 RF_ALLOCATED|RF_ACTIVE);
238 CHIPC_LOCK_DESTROY(sc);
243 chipc_detach(device_t dev)
245 struct chipc_softc *sc;
248 sc = device_get_softc(dev);
250 if ((error = bus_generic_detach(dev)))
253 if ((error = device_delete_children(dev)))
256 if ((error = bhnd_deregister_provider(dev, BHND_SERVICE_ANY)))
259 chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE);
262 CHIPC_LOCK_DESTROY(sc);
268 chipc_add_children(struct chipc_softc *sc)
271 const char *flash_bus;
275 if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM ||
276 sc->caps.nvram_src == BHND_NVRAM_SRC_OTP)
278 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", -1);
280 device_printf(sc->dev, "failed to add nvram device\n");
284 /* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */
285 error = chipc_set_mem_resource(sc, child, 0, CHIPC_SPROM_OTP,
286 CHIPC_SPROM_OTP_SIZE, 0, 0);
288 device_printf(sc->dev, "failed to set OTP memory "
289 "resource: %d\n", error);
297 * On AOB ("Always on Bus") devices, the PMU core (if it exists) is
298 * attached directly to the bhnd(4) bus -- not chipc.
300 if (sc->caps.pmu && !sc->caps.aob) {
301 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", -1);
303 device_printf(sc->dev, "failed to add pmu\n");
306 } else if (sc->caps.pwr_ctrl) {
307 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pwrctl", -1);
309 device_printf(sc->dev, "failed to add pwrctl\n");
315 child = BUS_ADD_CHILD(sc->dev, 0, "gpio", -1);
317 device_printf(sc->dev, "failed to add gpio\n");
321 error = chipc_set_mem_resource(sc, child, 0, 0, RM_MAX_END, 0, 0);
323 device_printf(sc->dev, "failed to set gpio memory resource: "
328 /* All remaining devices are SoC-only */
329 if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE)
333 for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) {
334 int irq_rid, mem_rid;
339 child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1);
341 device_printf(sc->dev, "failed to add uart%u\n", i);
346 error = chipc_set_irq_resource(sc, child, irq_rid, 0);
348 device_printf(sc->dev, "failed to set uart%u irq %u\n",
353 /* UART registers are mapped sequentially */
354 error = chipc_set_mem_resource(sc, child, mem_rid,
355 CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0);
357 device_printf(sc->dev, "failed to set uart%u memory "
358 "resource: %d\n", i, error);
364 flash_bus = chipc_flash_bus_name(sc->caps.flash_type);
365 if (flash_bus != NULL) {
368 child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, -1);
370 device_printf(sc->dev, "failed to add %s device\n",
375 /* flash memory mapping */
377 error = chipc_set_mem_resource(sc, child, rid, 0, RM_MAX_END, 1,
380 device_printf(sc->dev, "failed to set flash memory "
381 "resource %d: %d\n", rid, error);
385 /* flashctrl registers */
387 error = chipc_set_mem_resource(sc, child, rid,
388 CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0);
390 device_printf(sc->dev, "failed to set flash memory "
391 "resource %d: %d\n", rid, error);
400 * Determine the NVRAM data source for this device.
402 * The SPROM, OTP, and flash capability flags must be fully populated in
405 * @param sc chipc driver state.
406 * @param caps capability flags to be used to derive NVRAM configuration.
408 static bhnd_nvram_src
409 chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps)
411 uint32_t otp_st, srom_ctrl;
414 * We check for hardware presence in order of precedence. For example,
415 * SPROM is is always used in preference to internal OTP if found.
417 if (CHIPC_QUIRK(sc, SUPPORTS_SPROM) && caps->sprom) {
418 srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL);
419 if (srom_ctrl & CHIPC_SRC_PRESENT)
420 return (BHND_NVRAM_SRC_SPROM);
423 /* Check for programmed OTP H/W subregion (contains SROM data) */
424 if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) {
425 /* TODO: need access to HND-OTP device */
426 if (!CHIPC_QUIRK(sc, OTP_HND)) {
427 device_printf(sc->dev,
428 "NVRAM unavailable: unsupported OTP controller.\n");
429 return (BHND_NVRAM_SRC_UNKNOWN);
432 otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST);
433 if (otp_st & CHIPC_OTPS_GUP_HW)
434 return (BHND_NVRAM_SRC_OTP);
437 /* Check for flash */
438 if (caps->flash_type != CHIPC_FLASH_NONE)
439 return (BHND_NVRAM_SRC_FLASH);
441 /* No NVRAM hardware capability declared */
442 return (BHND_NVRAM_SRC_UNKNOWN);
445 /* Read and parse chipc capabilities */
447 chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps)
450 uint32_t cap_ext_reg;
453 /* Fetch cap registers */
454 cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES);
456 if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT))
457 cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT);
460 caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART);
461 caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB);
462 caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO);
463 caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL);
465 caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS);
466 caps->pwr_ctrl = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL);
467 caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP);
469 caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL);
470 caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64);
471 caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM);
472 caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU);
473 caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI);
474 caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM);
475 caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE);
477 caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI);
478 caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO);
479 caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB);
481 /* Fetch OTP size for later IPX controller revisions */
482 if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) {
483 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT);
484 caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE);
487 /* Determine flash type and parameters */
489 switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) {
490 case CHIPC_CAP_SFLASH_ST:
491 caps->flash_type = CHIPC_SFLASH_ST;
493 case CHIPC_CAP_SFLASH_AT:
494 caps->flash_type = CHIPC_SFLASH_AT;
496 case CHIPC_CAP_NFLASH:
498 caps->flash_type = CHIPC_NFLASH;
500 case CHIPC_CAP_PFLASH:
501 caps->flash_type = CHIPC_PFLASH_CFI;
503 /* determine cfi width */
504 regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG);
505 if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS))
511 case CHIPC_CAP_FLASH_NONE:
512 caps->flash_type = CHIPC_FLASH_NONE;
517 /* Handle 4706_NFLASH fallback */
518 if (CHIPC_QUIRK(sc, 4706_NFLASH) &&
519 CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH))
521 caps->flash_type = CHIPC_NFLASH_4706;
525 /* Determine NVRAM source. Must occur after the SPROM/OTP/flash
526 * capability flags have been populated. */
527 caps->nvram_src = chipc_find_nvram_src(sc, caps);
529 /* Determine the SPROM offset within OTP (if any). SPROM-formatted
530 * data is placed within the OTP general use region. */
531 caps->sprom_offset = 0;
532 if (caps->nvram_src == BHND_NVRAM_SRC_OTP) {
533 CHIPC_ASSERT_QUIRK(sc, OTP_IPX);
535 /* Bit offset to GUP HW subregion containing SPROM data */
536 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT);
537 caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP);
539 /* Convert to bytes */
540 caps->sprom_offset /= 8;
547 chipc_suspend(device_t dev)
549 return (bus_generic_suspend(dev));
553 chipc_resume(device_t dev)
555 return (bus_generic_resume(dev));
559 chipc_probe_nomatch(device_t dev, device_t child)
561 struct resource_list *rl;
564 name = device_get_name(child);
566 name = "unknown device";
568 device_printf(dev, "<%s> at", name);
570 rl = BUS_GET_RESOURCE_LIST(dev, child);
572 resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx");
573 resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd");
576 printf(" (no driver attached)\n");
580 chipc_print_child(device_t dev, device_t child)
582 struct resource_list *rl;
585 retval += bus_print_child_header(dev, child);
587 rl = BUS_GET_RESOURCE_LIST(dev, child);
589 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY,
591 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ,
595 retval += bus_print_child_domain(dev, child);
596 retval += bus_print_child_footer(dev, child);
602 chipc_child_pnpinfo_str(device_t dev, device_t child, char *buf,
613 chipc_child_location_str(device_t dev, device_t child, char *buf,
624 chipc_add_child(device_t dev, u_int order, const char *name, int unit)
626 struct chipc_softc *sc;
627 struct chipc_devinfo *dinfo;
630 sc = device_get_softc(dev);
632 child = device_add_child_ordered(dev, order, name, unit);
636 dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT);
638 device_delete_child(dev, child);
642 resource_list_init(&dinfo->resources);
643 dinfo->irq_mapped = false;
644 device_set_ivars(child, dinfo);
650 chipc_child_deleted(device_t dev, device_t child)
652 struct chipc_devinfo *dinfo = device_get_ivars(child);
655 /* Free the child's resource list */
656 resource_list_free(&dinfo->resources);
658 /* Unmap the child's IRQ */
659 if (dinfo->irq_mapped) {
660 bhnd_unmap_intr(dev, dinfo->irq);
661 dinfo->irq_mapped = false;
667 device_set_ivars(child, NULL);
670 static struct resource_list *
671 chipc_get_resource_list(device_t dev, device_t child)
673 struct chipc_devinfo *dinfo = device_get_ivars(child);
674 return (&dinfo->resources);
678 /* Allocate region records for the given port, and add the port's memory
679 * range to the mem_rman */
681 chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type,
684 struct chipc_region *cr;
685 rman_res_t start, end;
689 num_regions = bhnd_get_region_count(sc->dev, type, port);
690 for (u_int region = 0; region < num_regions; region++) {
691 /* Allocate new region record */
692 cr = chipc_alloc_region(sc, type, port, region);
696 /* Can't manage regions that cannot be allocated */
697 if (cr->cr_rid < 0) {
698 BHND_DEBUG_DEV(sc->dev, "no rid for chipc region "
699 "%s%u.%u", bhnd_port_type_name(type), port, region);
700 chipc_free_region(sc, cr);
704 /* Add to rman's managed range */
707 if ((error = rman_manage_region(&sc->mem_rman, start, end))) {
708 chipc_free_region(sc, cr);
712 /* Add to region list */
713 STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link);
719 /* Initialize memory state for all chipc port regions */
721 chipc_init_rman(struct chipc_softc *sc)
726 /* Port types for which we'll register chipc_region mappings */
727 bhnd_port_type types[] = {
731 /* Initialize resource manager */
732 sc->mem_rman.rm_start = 0;
733 sc->mem_rman.rm_end = BUS_SPACE_MAXADDR;
734 sc->mem_rman.rm_type = RMAN_ARRAY;
735 sc->mem_rman.rm_descr = "ChipCommon Device Memory";
736 if ((error = rman_init(&sc->mem_rman))) {
737 device_printf(sc->dev, "could not initialize mem_rman: %d\n",
742 /* Populate per-port-region state */
743 for (u_int i = 0; i < nitems(types); i++) {
744 num_ports = bhnd_get_port_count(sc->dev, types[i]);
745 for (u_int port = 0; port < num_ports; port++) {
746 error = chipc_rman_init_regions(sc, types[i], port);
748 device_printf(sc->dev,
749 "region init failed for %s%u: %d\n",
750 bhnd_port_type_name(types[i]), port,
765 /* Free memory management state */
767 chipc_free_rman(struct chipc_softc *sc)
769 struct chipc_region *cr, *cr_next;
771 STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next)
772 chipc_free_region(sc, cr);
774 rman_fini(&sc->mem_rman);
778 * Return the rman instance for a given resource @p type, if any.
780 * @param sc The chipc device state.
781 * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...)
784 chipc_get_rman(struct chipc_softc *sc, int type)
788 return (&sc->mem_rman);
791 /* We delegate IRQ resource management to the parent bus */
799 static struct resource *
800 chipc_alloc_resource(device_t dev, device_t child, int type,
801 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
803 struct chipc_softc *sc;
804 struct chipc_region *cr;
805 struct resource_list_entry *rle;
809 bool passthrough, isdefault;
811 sc = device_get_softc(dev);
812 passthrough = (device_get_parent(child) != dev);
813 isdefault = RMAN_IS_DEFAULT_RANGE(start, end);
816 /* Fetch the resource manager, delegate request if necessary */
817 rm = chipc_get_rman(sc, type);
819 /* Requested resource type is delegated to our parent */
820 rv = bus_generic_rl_alloc_resource(dev, child, type, rid,
821 start, end, count, flags);
825 /* Populate defaults */
826 if (!passthrough && isdefault) {
827 /* Fetch the resource list entry. */
828 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child),
832 "default resource %#x type %d for child %s "
833 "not found\n", *rid, type,
834 device_get_nameunit(child));
838 if (rle->res != NULL) {
840 "resource entry %#x type %d for child %s is busy "
842 *rid, type, device_get_nameunit(child),
843 rman_get_flags(rle->res));
850 count = ulmax(count, rle->count);
853 /* Locate a mapping region */
854 if ((cr = chipc_find_region(sc, start, end)) == NULL) {
855 /* Resource requests outside our shared port regions can be
856 * delegated to our parent. */
857 rv = bus_generic_rl_alloc_resource(dev, child, type, rid,
858 start, end, count, flags);
863 * As a special case, children that map the complete ChipCommon register
864 * block are delegated to our parent.
866 * The rman API does not support sharing resources that are not
867 * identical in size; since we allocate subregions to various children,
868 * any children that need to map the entire register block (e.g. because
869 * they require access to discontiguous register ranges) must make the
870 * allocation through our parent, where we hold a compatible
871 * RF_SHAREABLE allocation.
873 if (cr == sc->core_region && cr->cr_addr == start &&
874 cr->cr_end == end && cr->cr_count == count)
876 rv = bus_generic_rl_alloc_resource(dev, child, type, rid,
877 start, end, count, flags);
881 /* Try to retain a region reference */
882 if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED)))
885 /* Make our rman reservation */
886 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE,
889 chipc_release_region(sc, cr, RF_ALLOCATED);
893 rman_set_rid(rv, *rid);
896 if (flags & RF_ACTIVE) {
897 error = bus_activate_resource(child, type, *rid, rv);
900 "failed to activate entry %#x type %d for "
902 *rid, type, device_get_nameunit(child), error);
904 chipc_release_region(sc, cr, RF_ALLOCATED);
905 rman_release_resource(rv);
911 /* Update child's resource list entry */
914 rle->start = rman_get_start(rv);
915 rle->end = rman_get_end(rv);
916 rle->count = rman_get_size(rv);
923 chipc_release_resource(device_t dev, device_t child, int type, int rid,
926 struct chipc_softc *sc;
927 struct chipc_region *cr;
929 struct resource_list_entry *rle;
932 sc = device_get_softc(dev);
934 /* Handled by parent bus? */
935 rm = chipc_get_rman(sc, type);
936 if (rm == NULL || !rman_is_region_manager(r, rm)) {
937 return (bus_generic_rl_release_resource(dev, child, type, rid,
941 /* Locate the mapping region */
942 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
946 /* Deactivate resources */
947 if (rman_get_flags(r) & RF_ACTIVE) {
948 error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r);
953 if ((error = rman_release_resource(r)))
956 /* Drop allocation reference */
957 chipc_release_region(sc, cr, RF_ALLOCATED);
959 /* Clear reference from the resource list entry if exists */
960 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid);
968 chipc_adjust_resource(device_t dev, device_t child, int type,
969 struct resource *r, rman_res_t start, rman_res_t end)
971 struct chipc_softc *sc;
972 struct chipc_region *cr;
975 sc = device_get_softc(dev);
977 /* Handled by parent bus? */
978 rm = chipc_get_rman(sc, type);
979 if (rm == NULL || !rman_is_region_manager(r, rm)) {
980 return (bus_generic_adjust_resource(dev, child, type, r, start,
984 /* The range is limited to the existing region mapping */
985 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
992 if (start < cr->cr_addr || end > cr->cr_end)
995 /* Range falls within the existing region */
996 return (rman_adjust_resource(r, start, end));
1000 * Retain an RF_ACTIVE reference to the region mapping @p r, and
1001 * configure @p r with its subregion values.
1003 * @param sc Driver instance state.
1004 * @param child Requesting child device.
1005 * @param type resource type of @p r.
1006 * @param rid resource id of @p r
1007 * @param r resource to be activated.
1008 * @param req_direct If true, failure to allocate a direct bhnd resource
1009 * will be treated as an error. If false, the resource will not be marked
1010 * as RF_ACTIVE if bhnd direct resource allocation fails.
1013 chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type,
1014 int rid, struct resource *r, bool req_direct)
1017 struct chipc_region *cr;
1018 bhnd_size_t cr_offset;
1019 rman_res_t r_start, r_end, r_size;
1022 rm = chipc_get_rman(sc, type);
1023 if (rm == NULL || !rman_is_region_manager(r, rm))
1026 r_start = rman_get_start(r);
1027 r_end = rman_get_end(r);
1028 r_size = rman_get_size(r);
1030 /* Find the corresponding chipc region */
1031 cr = chipc_find_region(sc, r_start, r_end);
1035 /* Calculate subregion offset within the chipc region */
1036 cr_offset = r_start - cr->cr_addr;
1038 /* Retain (and activate, if necessary) the chipc region */
1039 if ((error = chipc_retain_region(sc, cr, RF_ACTIVE)))
1042 /* Configure child resource with its subregion values. */
1043 if (cr->cr_res->direct) {
1044 error = chipc_init_child_resource(r, cr->cr_res->res,
1050 if ((error = rman_activate_resource(r)))
1052 } else if (req_direct) {
1060 chipc_release_region(sc, cr, RF_ACTIVE);
1065 chipc_activate_bhnd_resource(device_t dev, device_t child, int type,
1066 int rid, struct bhnd_resource *r)
1068 struct chipc_softc *sc;
1072 sc = device_get_softc(dev);
1074 /* Delegate non-locally managed resources to parent */
1075 rm = chipc_get_rman(sc, type);
1076 if (rm == NULL || !rman_is_region_manager(r->res, rm)) {
1077 return (bhnd_bus_generic_activate_resource(dev, child, type,
1081 /* Try activating the chipc region resource */
1082 error = chipc_try_activate_resource(sc, child, type, rid, r->res,
1087 /* Mark the child resource as direct according to the returned resource
1089 if (rman_get_flags(r->res) & RF_ACTIVE)
1096 chipc_activate_resource(device_t dev, device_t child, int type, int rid,
1099 struct chipc_softc *sc;
1102 sc = device_get_softc(dev);
1104 /* Delegate non-locally managed resources to parent */
1105 rm = chipc_get_rman(sc, type);
1106 if (rm == NULL || !rman_is_region_manager(r, rm)) {
1107 return (bus_generic_activate_resource(dev, child, type, rid,
1111 /* Try activating the chipc region-based resource */
1112 return (chipc_try_activate_resource(sc, child, type, rid, r, true));
1116 * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE().
1119 chipc_deactivate_resource(device_t dev, device_t child, int type,
1120 int rid, struct resource *r)
1122 struct chipc_softc *sc;
1123 struct chipc_region *cr;
1127 sc = device_get_softc(dev);
1129 /* Handled by parent bus? */
1130 rm = chipc_get_rman(sc, type);
1131 if (rm == NULL || !rman_is_region_manager(r, rm)) {
1132 return (bus_generic_deactivate_resource(dev, child, type, rid,
1136 /* Find the corresponding chipc region */
1137 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
1142 if ((error = rman_deactivate_resource(r)))
1145 /* Drop associated RF_ACTIVE reference */
1146 chipc_release_region(sc, cr, RF_ACTIVE);
1152 * Examine bus state and make a best effort determination of whether it's
1153 * likely safe to enable the muxed SPROM pins.
1155 * On devices that do not use SPROM pin muxing, always returns true.
1157 * @param sc chipc driver state.
1160 chipc_should_enable_muxed_sprom(struct chipc_softc *sc)
1169 /* Nothing to do? */
1170 if (!CHIPC_QUIRK(sc, MUX_SPROM))
1173 mtx_lock(&Giant); /* for newbus */
1175 parent = device_get_parent(sc->dev);
1176 hostb = bhnd_bus_find_hostb_device(parent);
1178 if ((error = device_get_children(parent, &devs, &devcount))) {
1183 /* Reject any active devices other than ChipCommon, or the
1184 * host bridge (if any). */
1186 for (int i = 0; i < devcount; i++) {
1187 if (devs[i] == hostb || devs[i] == sc->dev)
1190 if (!device_is_attached(devs[i]))
1193 if (device_is_suspended(devs[i]))
1196 /* Active device; assume SPROM is busy */
1207 chipc_enable_sprom(device_t dev)
1209 struct chipc_softc *sc;
1212 sc = device_get_softc(dev);
1215 /* Already enabled? */
1216 if (sc->sprom_refcnt >= 1) {
1223 switch (sc->caps.nvram_src) {
1224 case BHND_NVRAM_SRC_SPROM:
1225 error = chipc_enable_sprom_pins(sc);
1227 case BHND_NVRAM_SRC_OTP:
1228 error = chipc_enable_otp_power(sc);
1235 /* Bump the reference count */
1244 chipc_disable_sprom(device_t dev)
1246 struct chipc_softc *sc;
1248 sc = device_get_softc(dev);
1251 /* Check reference count, skip disable if in-use. */
1252 KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease"));
1254 if (sc->sprom_refcnt > 0) {
1259 switch (sc->caps.nvram_src) {
1260 case BHND_NVRAM_SRC_SPROM:
1261 chipc_disable_sprom_pins(sc);
1263 case BHND_NVRAM_SRC_OTP:
1264 chipc_disable_otp_power(sc);
1275 chipc_enable_otp_power(struct chipc_softc *sc)
1277 // TODO: Enable OTP resource via PMU, and wait up to 100 usec for
1278 // OTPS_READY to be set in `optstatus`.
1283 chipc_disable_otp_power(struct chipc_softc *sc)
1285 // TODO: Disable OTP resource via PMU
1289 * If required by this device, enable access to the SPROM.
1291 * @param sc chipc driver state.
1294 chipc_enable_sprom_pins(struct chipc_softc *sc)
1298 CHIPC_LOCK_ASSERT(sc, MA_OWNED);
1299 KASSERT(sc->sprom_refcnt == 0, ("sprom pins already enabled"));
1301 /* Nothing to do? */
1302 if (!CHIPC_QUIRK(sc, MUX_SPROM))
1305 /* Check whether bus is busy */
1306 if (!chipc_should_enable_muxed_sprom(sc))
1309 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
1312 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) {
1313 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN;
1315 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM))
1316 cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5;
1318 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM))
1319 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2;
1321 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
1326 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) {
1330 /* Refuse to proceed on unsupported devices with muxed SPROM pins */
1331 device_printf(sc->dev, "muxed sprom lines on unrecognized device\n");
1336 * If required by this device, revert any GPIO/pin configuration applied
1337 * to allow SPROM access.
1339 * @param sc chipc driver state.
1342 chipc_disable_sprom_pins(struct chipc_softc *sc)
1346 /* Nothing to do? */
1347 if (!CHIPC_QUIRK(sc, MUX_SPROM))
1350 CHIPC_LOCK_ASSERT(sc, MA_OWNED);
1351 KASSERT(sc->sprom_refcnt == 0, ("sprom pins in use"));
1353 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
1356 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) {
1357 cctrl |= CHIPC_CCTRL4331_EXTPA_EN;
1359 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM))
1360 cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5;
1362 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM))
1363 cctrl |= CHIPC_CCTRL4331_EXTPA_EN2;
1365 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
1370 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) {
1376 chipc_read_chipst(device_t dev)
1378 struct chipc_softc *sc = device_get_softc(dev);
1379 return (bhnd_bus_read_4(sc->core, CHIPC_CHIPST));
1383 chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask)
1385 struct chipc_softc *sc;
1388 sc = device_get_softc(dev);
1392 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
1393 cctrl = (cctrl & ~mask) | (value | mask);
1394 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
1399 static struct chipc_caps *
1400 chipc_get_caps(device_t dev)
1402 struct chipc_softc *sc;
1404 sc = device_get_softc(dev);
1408 static device_method_t chipc_methods[] = {
1409 /* Device interface */
1410 DEVMETHOD(device_probe, chipc_probe),
1411 DEVMETHOD(device_attach, chipc_attach),
1412 DEVMETHOD(device_detach, chipc_detach),
1413 DEVMETHOD(device_suspend, chipc_suspend),
1414 DEVMETHOD(device_resume, chipc_resume),
1417 DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch),
1418 DEVMETHOD(bus_print_child, chipc_print_child),
1419 DEVMETHOD(bus_child_pnpinfo_str, chipc_child_pnpinfo_str),
1420 DEVMETHOD(bus_child_location_str, chipc_child_location_str),
1422 DEVMETHOD(bus_add_child, chipc_add_child),
1423 DEVMETHOD(bus_child_deleted, chipc_child_deleted),
1425 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
1426 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
1427 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource),
1428 DEVMETHOD(bus_alloc_resource, chipc_alloc_resource),
1429 DEVMETHOD(bus_release_resource, chipc_release_resource),
1430 DEVMETHOD(bus_adjust_resource, chipc_adjust_resource),
1431 DEVMETHOD(bus_activate_resource, chipc_activate_resource),
1432 DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource),
1433 DEVMETHOD(bus_get_resource_list, chipc_get_resource_list),
1435 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1436 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1437 DEVMETHOD(bus_config_intr, bus_generic_config_intr),
1438 DEVMETHOD(bus_bind_intr, bus_generic_bind_intr),
1439 DEVMETHOD(bus_describe_intr, bus_generic_describe_intr),
1441 /* BHND bus inteface */
1442 DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource),
1444 /* ChipCommon interface */
1445 DEVMETHOD(bhnd_chipc_read_chipst, chipc_read_chipst),
1446 DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl),
1447 DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom),
1448 DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom),
1449 DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps),
1454 DEFINE_CLASS_0(bhnd_chipc, bhnd_chipc_driver, chipc_methods, sizeof(struct chipc_softc));
1455 EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, bhnd_chipc_driver, bhnd_chipc_devclass, 0, 0,
1456 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
1457 MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1);
1458 MODULE_VERSION(bhnd_chipc, 1);