2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
3 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com>
4 * Copyright (c) 2017 The FreeBSD Foundation
7 * Portions of this software were developed by Landon Fuller
8 * under sponsorship from the FreeBSD Foundation.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
25 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
26 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
27 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
30 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGES.
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
39 * Broadcom ChipCommon driver.
41 * With the exception of some very early chipsets, the ChipCommon core
42 * has been included in all HND SoCs and chipsets based on the siba(4)
43 * and bcma(4) interconnects, providing a common interface to chipset
44 * identification, bus enumeration, UARTs, clocks, watchdog interrupts,
48 #include <sys/param.h>
49 #include <sys/kernel.h>
53 #include <sys/malloc.h>
54 #include <sys/module.h>
55 #include <sys/mutex.h>
56 #include <sys/systm.h>
58 #include <machine/bus.h>
59 #include <machine/resource.h>
61 #include <dev/bhnd/bhnd.h>
62 #include <dev/bhnd/bhndvar.h>
67 #include "chipc_private.h"
69 devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */
71 static struct bhnd_device_quirk chipc_quirks[];
73 /* Supported device identifiers */
74 static const struct bhnd_device chipc_devices[] = {
75 BHND_DEVICE(BCM, CC, NULL, chipc_quirks),
76 BHND_DEVICE(BCM, 4706_CC, NULL, chipc_quirks),
81 /* Device quirks table */
82 static struct bhnd_device_quirk chipc_quirks[] = {
83 /* HND OTP controller revisions */
84 BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */
85 BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */
86 BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */
88 /* IPX OTP controller revisions */
89 BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX),
90 BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX),
92 BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM),
93 BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT),
94 BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE),
96 /* 4706 variant quirks */
97 BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */
98 BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH),
101 BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM),
102 BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM),
103 BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM),
104 BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM),
107 BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
108 BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
109 BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
110 BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
112 BHND_DEVICE_QUIRK_END
115 static int chipc_add_children(struct chipc_softc *sc);
117 static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc,
118 struct chipc_caps *caps);
119 static int chipc_read_caps(struct chipc_softc *sc,
120 struct chipc_caps *caps);
122 static bool chipc_should_enable_muxed_sprom(
123 struct chipc_softc *sc);
124 static int chipc_enable_otp_power(struct chipc_softc *sc);
125 static void chipc_disable_otp_power(struct chipc_softc *sc);
126 static int chipc_enable_sprom_pins(struct chipc_softc *sc);
127 static void chipc_disable_sprom_pins(struct chipc_softc *sc);
129 static int chipc_try_activate_resource(struct chipc_softc *sc,
130 device_t child, int type, int rid,
131 struct resource *r, bool req_direct);
133 static int chipc_init_rman(struct chipc_softc *sc);
134 static void chipc_free_rman(struct chipc_softc *sc);
135 static struct rman *chipc_get_rman(struct chipc_softc *sc, int type);
137 /* quirk and capability flag convenience macros */
138 #define CHIPC_QUIRK(_sc, _name) \
139 ((_sc)->quirks & CHIPC_QUIRK_ ## _name)
141 #define CHIPC_CAP(_sc, _name) \
144 #define CHIPC_ASSERT_QUIRK(_sc, name) \
145 KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set"))
147 #define CHIPC_ASSERT_CAP(_sc, name) \
148 KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set"))
151 chipc_probe(device_t dev)
153 const struct bhnd_device *id;
155 id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0]));
159 bhnd_set_default_core_desc(dev);
160 return (BUS_PROBE_DEFAULT);
164 chipc_attach(device_t dev)
166 struct chipc_softc *sc;
169 sc = device_get_softc(dev);
171 sc->quirks = bhnd_device_quirks(dev, chipc_devices,
172 sizeof(chipc_devices[0]));
173 sc->sprom_refcnt = 0;
176 STAILQ_INIT(&sc->mem_regions);
178 /* Set up resource management */
179 if ((error = chipc_init_rman(sc))) {
180 device_printf(sc->dev,
181 "failed to initialize chipc resource state: %d\n", error);
185 /* Allocate the region containing the chipc register block */
186 if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) {
191 error = chipc_retain_region(sc, sc->core_region,
192 RF_ALLOCATED|RF_ACTIVE);
194 sc->core_region = NULL;
198 /* Save a direct reference to our chipc registers */
199 sc->core = sc->core_region->cr_res;
201 /* Fetch and parse capability register(s) */
202 if ((error = chipc_read_caps(sc, &sc->caps)))
206 chipc_print_caps(sc->dev, &sc->caps);
208 /* Attach all supported child devices */
209 if ((error = chipc_add_children(sc)))
213 * Register ourselves with the bus; we're fully initialized and can
214 * response to ChipCommin API requests.
216 * Since our children may need access to ChipCommon, this must be done
217 * before attaching our children below (via bus_generic_attach).
219 if ((error = bhnd_register_provider(dev, BHND_SERVICE_CHIPC)))
222 if ((error = bus_generic_attach(dev)))
228 device_delete_children(sc->dev);
230 if (sc->core_region != NULL) {
231 chipc_release_region(sc, sc->core_region,
232 RF_ALLOCATED|RF_ACTIVE);
236 CHIPC_LOCK_DESTROY(sc);
241 chipc_detach(device_t dev)
243 struct chipc_softc *sc;
246 sc = device_get_softc(dev);
248 if ((error = bhnd_deregister_provider(dev, BHND_SERVICE_ANY)))
251 if ((error = bus_generic_detach(dev)))
254 chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE);
257 CHIPC_LOCK_DESTROY(sc);
263 chipc_add_children(struct chipc_softc *sc)
266 const char *flash_bus;
270 if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM ||
271 sc->caps.nvram_src == BHND_NVRAM_SRC_OTP)
273 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", -1);
275 device_printf(sc->dev, "failed to add nvram device\n");
279 /* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */
280 error = chipc_set_mem_resource(sc, child, 0, CHIPC_SPROM_OTP,
281 CHIPC_SPROM_OTP_SIZE, 0, 0);
283 device_printf(sc->dev, "failed to set OTP memory "
284 "resource: %d\n", error);
292 * On AOB ("Always on Bus") devices, the PMU core (if it exists) is
293 * attached directly to the bhnd(4) bus -- not chipc.
295 if (sc->caps.pmu && !sc->caps.aob) {
296 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", 0);
298 device_printf(sc->dev, "failed to add pmu\n");
301 } else if (sc->caps.pwr_ctrl) {
302 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pwrctl", 0);
304 device_printf(sc->dev, "failed to add pwrctl\n");
309 /* All remaining devices are SoC-only */
310 if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE)
314 for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) {
315 int irq_rid, mem_rid;
320 child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1);
322 device_printf(sc->dev, "failed to add uart%u\n", i);
327 error = chipc_set_irq_resource(sc, child, irq_rid, 0);
329 device_printf(sc->dev, "failed to set uart%u irq %u\n",
334 /* UART registers are mapped sequentially */
335 error = chipc_set_mem_resource(sc, child, mem_rid,
336 CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0);
338 device_printf(sc->dev, "failed to set uart%u memory "
339 "resource: %d\n", i, error);
345 flash_bus = chipc_flash_bus_name(sc->caps.flash_type);
346 if (flash_bus != NULL) {
349 child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, -1);
351 device_printf(sc->dev, "failed to add %s device\n",
356 /* flash memory mapping */
358 error = chipc_set_mem_resource(sc, child, rid, 0, RM_MAX_END, 1,
361 device_printf(sc->dev, "failed to set flash memory "
362 "resource %d: %d\n", rid, error);
366 /* flashctrl registers */
368 error = chipc_set_mem_resource(sc, child, rid,
369 CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0);
371 device_printf(sc->dev, "failed to set flash memory "
372 "resource %d: %d\n", rid, error);
381 * Determine the NVRAM data source for this device.
383 * The SPROM, OTP, and flash capability flags must be fully populated in
386 * @param sc chipc driver state.
387 * @param caps capability flags to be used to derive NVRAM configuration.
389 static bhnd_nvram_src
390 chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps)
392 uint32_t otp_st, srom_ctrl;
395 * We check for hardware presence in order of precedence. For example,
396 * SPROM is is always used in preference to internal OTP if found.
398 if (CHIPC_QUIRK(sc, SUPPORTS_SPROM) && caps->sprom) {
399 srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL);
400 if (srom_ctrl & CHIPC_SRC_PRESENT)
401 return (BHND_NVRAM_SRC_SPROM);
404 /* Check for programmed OTP H/W subregion (contains SROM data) */
405 if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) {
406 /* TODO: need access to HND-OTP device */
407 if (!CHIPC_QUIRK(sc, OTP_HND)) {
408 device_printf(sc->dev,
409 "NVRAM unavailable: unsupported OTP controller.\n");
410 return (BHND_NVRAM_SRC_UNKNOWN);
413 otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST);
414 if (otp_st & CHIPC_OTPS_GUP_HW)
415 return (BHND_NVRAM_SRC_OTP);
418 /* Check for flash */
419 if (caps->flash_type != CHIPC_FLASH_NONE)
420 return (BHND_NVRAM_SRC_FLASH);
422 /* No NVRAM hardware capability declared */
423 return (BHND_NVRAM_SRC_UNKNOWN);
426 /* Read and parse chipc capabilities */
428 chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps)
431 uint32_t cap_ext_reg;
434 /* Fetch cap registers */
435 cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES);
437 if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT))
438 cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT);
441 caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART);
442 caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB);
443 caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO);
444 caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL);
446 caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS);
447 caps->pwr_ctrl = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL);
448 caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP);
450 caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL);
451 caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64);
452 caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM);
453 caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU);
454 caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI);
455 caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM);
456 caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE);
458 caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI);
459 caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO);
460 caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB);
462 /* Fetch OTP size for later IPX controller revisions */
463 if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) {
464 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT);
465 caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE);
468 /* Determine flash type and parameters */
470 switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) {
471 case CHIPC_CAP_SFLASH_ST:
472 caps->flash_type = CHIPC_SFLASH_ST;
474 case CHIPC_CAP_SFLASH_AT:
475 caps->flash_type = CHIPC_SFLASH_AT;
477 case CHIPC_CAP_NFLASH:
479 caps->flash_type = CHIPC_NFLASH;
481 case CHIPC_CAP_PFLASH:
482 caps->flash_type = CHIPC_PFLASH_CFI;
484 /* determine cfi width */
485 regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG);
486 if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS))
492 case CHIPC_CAP_FLASH_NONE:
493 caps->flash_type = CHIPC_FLASH_NONE;
498 /* Handle 4706_NFLASH fallback */
499 if (CHIPC_QUIRK(sc, 4706_NFLASH) &&
500 CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH))
502 caps->flash_type = CHIPC_NFLASH_4706;
506 /* Determine NVRAM source. Must occur after the SPROM/OTP/flash
507 * capability flags have been populated. */
508 caps->nvram_src = chipc_find_nvram_src(sc, caps);
510 /* Determine the SPROM offset within OTP (if any). SPROM-formatted
511 * data is placed within the OTP general use region. */
512 caps->sprom_offset = 0;
513 if (caps->nvram_src == BHND_NVRAM_SRC_OTP) {
514 CHIPC_ASSERT_QUIRK(sc, OTP_IPX);
516 /* Bit offset to GUP HW subregion containing SPROM data */
517 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT);
518 caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP);
520 /* Convert to bytes */
521 caps->sprom_offset /= 8;
528 chipc_suspend(device_t dev)
530 return (bus_generic_suspend(dev));
534 chipc_resume(device_t dev)
536 return (bus_generic_resume(dev));
540 chipc_probe_nomatch(device_t dev, device_t child)
542 struct resource_list *rl;
545 name = device_get_name(child);
547 name = "unknown device";
549 device_printf(dev, "<%s> at", name);
551 rl = BUS_GET_RESOURCE_LIST(dev, child);
553 resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx");
554 resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd");
557 printf(" (no driver attached)\n");
561 chipc_print_child(device_t dev, device_t child)
563 struct resource_list *rl;
566 retval += bus_print_child_header(dev, child);
568 rl = BUS_GET_RESOURCE_LIST(dev, child);
570 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY,
572 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ,
576 retval += bus_print_child_domain(dev, child);
577 retval += bus_print_child_footer(dev, child);
583 chipc_child_pnpinfo_str(device_t dev, device_t child, char *buf,
594 chipc_child_location_str(device_t dev, device_t child, char *buf,
605 chipc_add_child(device_t dev, u_int order, const char *name, int unit)
607 struct chipc_softc *sc;
608 struct chipc_devinfo *dinfo;
611 sc = device_get_softc(dev);
613 child = device_add_child_ordered(dev, order, name, unit);
617 dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT);
619 device_delete_child(dev, child);
623 resource_list_init(&dinfo->resources);
624 dinfo->irq_mapped = false;
625 device_set_ivars(child, dinfo);
631 chipc_child_deleted(device_t dev, device_t child)
633 struct chipc_devinfo *dinfo = device_get_ivars(child);
636 /* Free the child's resource list */
637 resource_list_free(&dinfo->resources);
639 /* Unmap the child's IRQ */
640 if (dinfo->irq_mapped) {
641 bhnd_unmap_intr(dev, dinfo->irq);
642 dinfo->irq_mapped = false;
648 device_set_ivars(child, NULL);
651 static struct resource_list *
652 chipc_get_resource_list(device_t dev, device_t child)
654 struct chipc_devinfo *dinfo = device_get_ivars(child);
655 return (&dinfo->resources);
659 /* Allocate region records for the given port, and add the port's memory
660 * range to the mem_rman */
662 chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type,
665 struct chipc_region *cr;
666 rman_res_t start, end;
670 num_regions = bhnd_get_region_count(sc->dev, type, port);
671 for (u_int region = 0; region < num_regions; region++) {
672 /* Allocate new region record */
673 cr = chipc_alloc_region(sc, type, port, region);
677 /* Can't manage regions that cannot be allocated */
678 if (cr->cr_rid < 0) {
679 BHND_DEBUG_DEV(sc->dev, "no rid for chipc region "
680 "%s%u.%u", bhnd_port_type_name(type), port, region);
681 chipc_free_region(sc, cr);
685 /* Add to rman's managed range */
688 if ((error = rman_manage_region(&sc->mem_rman, start, end))) {
689 chipc_free_region(sc, cr);
693 /* Add to region list */
694 STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link);
700 /* Initialize memory state for all chipc port regions */
702 chipc_init_rman(struct chipc_softc *sc)
707 /* Port types for which we'll register chipc_region mappings */
708 bhnd_port_type types[] = {
712 /* Initialize resource manager */
713 sc->mem_rman.rm_start = 0;
714 sc->mem_rman.rm_end = BUS_SPACE_MAXADDR;
715 sc->mem_rman.rm_type = RMAN_ARRAY;
716 sc->mem_rman.rm_descr = "ChipCommon Device Memory";
717 if ((error = rman_init(&sc->mem_rman))) {
718 device_printf(sc->dev, "could not initialize mem_rman: %d\n",
723 /* Populate per-port-region state */
724 for (u_int i = 0; i < nitems(types); i++) {
725 num_ports = bhnd_get_port_count(sc->dev, types[i]);
726 for (u_int port = 0; port < num_ports; port++) {
727 error = chipc_rman_init_regions(sc, types[i], port);
729 device_printf(sc->dev,
730 "region init failed for %s%u: %d\n",
731 bhnd_port_type_name(types[i]), port,
746 /* Free memory management state */
748 chipc_free_rman(struct chipc_softc *sc)
750 struct chipc_region *cr, *cr_next;
752 STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next)
753 chipc_free_region(sc, cr);
755 rman_fini(&sc->mem_rman);
759 * Return the rman instance for a given resource @p type, if any.
761 * @param sc The chipc device state.
762 * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...)
765 chipc_get_rman(struct chipc_softc *sc, int type)
769 return (&sc->mem_rman);
772 /* We delegate IRQ resource management to the parent bus */
780 static struct resource *
781 chipc_alloc_resource(device_t dev, device_t child, int type,
782 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
784 struct chipc_softc *sc;
785 struct chipc_region *cr;
786 struct resource_list_entry *rle;
790 bool passthrough, isdefault;
792 sc = device_get_softc(dev);
793 passthrough = (device_get_parent(child) != dev);
794 isdefault = RMAN_IS_DEFAULT_RANGE(start, end);
797 /* Fetch the resource manager, delegate request if necessary */
798 rm = chipc_get_rman(sc, type);
800 /* Requested resource type is delegated to our parent */
801 rv = bus_generic_rl_alloc_resource(dev, child, type, rid,
802 start, end, count, flags);
806 /* Populate defaults */
807 if (!passthrough && isdefault) {
808 /* Fetch the resource list entry. */
809 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child),
813 "default resource %#x type %d for child %s "
814 "not found\n", *rid, type,
815 device_get_nameunit(child));
819 if (rle->res != NULL) {
821 "resource entry %#x type %d for child %s is busy "
823 *rid, type, device_get_nameunit(child),
824 rman_get_flags(rle->res));
831 count = ulmax(count, rle->count);
834 /* Locate a mapping region */
835 if ((cr = chipc_find_region(sc, start, end)) == NULL) {
836 /* Resource requests outside our shared port regions can be
837 * delegated to our parent. */
838 rv = bus_generic_rl_alloc_resource(dev, child, type, rid,
839 start, end, count, flags);
843 /* Try to retain a region reference */
844 if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED)))
847 /* Make our rman reservation */
848 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE,
851 chipc_release_region(sc, cr, RF_ALLOCATED);
855 rman_set_rid(rv, *rid);
858 if (flags & RF_ACTIVE) {
859 error = bus_activate_resource(child, type, *rid, rv);
862 "failed to activate entry %#x type %d for "
864 *rid, type, device_get_nameunit(child), error);
866 chipc_release_region(sc, cr, RF_ALLOCATED);
867 rman_release_resource(rv);
873 /* Update child's resource list entry */
876 rle->start = rman_get_start(rv);
877 rle->end = rman_get_end(rv);
878 rle->count = rman_get_size(rv);
885 chipc_release_resource(device_t dev, device_t child, int type, int rid,
888 struct chipc_softc *sc;
889 struct chipc_region *cr;
891 struct resource_list_entry *rle;
894 sc = device_get_softc(dev);
896 /* Handled by parent bus? */
897 rm = chipc_get_rman(sc, type);
898 if (rm == NULL || !rman_is_region_manager(r, rm)) {
899 return (bus_generic_rl_release_resource(dev, child, type, rid,
903 /* Locate the mapping region */
904 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
908 /* Deactivate resources */
909 if (rman_get_flags(r) & RF_ACTIVE) {
910 error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r);
915 if ((error = rman_release_resource(r)))
918 /* Drop allocation reference */
919 chipc_release_region(sc, cr, RF_ALLOCATED);
921 /* Clear reference from the resource list entry if exists */
922 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid);
930 chipc_adjust_resource(device_t dev, device_t child, int type,
931 struct resource *r, rman_res_t start, rman_res_t end)
933 struct chipc_softc *sc;
934 struct chipc_region *cr;
937 sc = device_get_softc(dev);
939 /* Handled by parent bus? */
940 rm = chipc_get_rman(sc, type);
941 if (rm == NULL || !rman_is_region_manager(r, rm)) {
942 return (bus_generic_adjust_resource(dev, child, type, r, start,
946 /* The range is limited to the existing region mapping */
947 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
954 if (start < cr->cr_addr || end > cr->cr_end)
957 /* Range falls within the existing region */
958 return (rman_adjust_resource(r, start, end));
962 * Retain an RF_ACTIVE reference to the region mapping @p r, and
963 * configure @p r with its subregion values.
965 * @param sc Driver instance state.
966 * @param child Requesting child device.
967 * @param type resource type of @p r.
968 * @param rid resource id of @p r
969 * @param r resource to be activated.
970 * @param req_direct If true, failure to allocate a direct bhnd resource
971 * will be treated as an error. If false, the resource will not be marked
972 * as RF_ACTIVE if bhnd direct resource allocation fails.
975 chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type,
976 int rid, struct resource *r, bool req_direct)
979 struct chipc_region *cr;
980 bhnd_size_t cr_offset;
981 rman_res_t r_start, r_end, r_size;
984 rm = chipc_get_rman(sc, type);
985 if (rm == NULL || !rman_is_region_manager(r, rm))
988 r_start = rman_get_start(r);
989 r_end = rman_get_end(r);
990 r_size = rman_get_size(r);
992 /* Find the corresponding chipc region */
993 cr = chipc_find_region(sc, r_start, r_end);
997 /* Calculate subregion offset within the chipc region */
998 cr_offset = r_start - cr->cr_addr;
1000 /* Retain (and activate, if necessary) the chipc region */
1001 if ((error = chipc_retain_region(sc, cr, RF_ACTIVE)))
1004 /* Configure child resource with its subregion values. */
1005 if (cr->cr_res->direct) {
1006 error = chipc_init_child_resource(r, cr->cr_res->res,
1012 if ((error = rman_activate_resource(r)))
1014 } else if (req_direct) {
1022 chipc_release_region(sc, cr, RF_ACTIVE);
1027 chipc_activate_bhnd_resource(device_t dev, device_t child, int type,
1028 int rid, struct bhnd_resource *r)
1030 struct chipc_softc *sc;
1034 sc = device_get_softc(dev);
1036 /* Delegate non-locally managed resources to parent */
1037 rm = chipc_get_rman(sc, type);
1038 if (rm == NULL || !rman_is_region_manager(r->res, rm)) {
1039 return (bhnd_bus_generic_activate_resource(dev, child, type,
1043 /* Try activating the chipc region resource */
1044 error = chipc_try_activate_resource(sc, child, type, rid, r->res,
1049 /* Mark the child resource as direct according to the returned resource
1051 if (rman_get_flags(r->res) & RF_ACTIVE)
1058 chipc_activate_resource(device_t dev, device_t child, int type, int rid,
1061 struct chipc_softc *sc;
1064 sc = device_get_softc(dev);
1066 /* Delegate non-locally managed resources to parent */
1067 rm = chipc_get_rman(sc, type);
1068 if (rm == NULL || !rman_is_region_manager(r, rm)) {
1069 return (bus_generic_activate_resource(dev, child, type, rid,
1073 /* Try activating the chipc region-based resource */
1074 return (chipc_try_activate_resource(sc, child, type, rid, r, true));
1078 * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE().
1081 chipc_deactivate_resource(device_t dev, device_t child, int type,
1082 int rid, struct resource *r)
1084 struct chipc_softc *sc;
1085 struct chipc_region *cr;
1089 sc = device_get_softc(dev);
1091 /* Handled by parent bus? */
1092 rm = chipc_get_rman(sc, type);
1093 if (rm == NULL || !rman_is_region_manager(r, rm)) {
1094 return (bus_generic_deactivate_resource(dev, child, type, rid,
1098 /* Find the corresponding chipc region */
1099 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
1104 if ((error = rman_deactivate_resource(r)))
1107 /* Drop associated RF_ACTIVE reference */
1108 chipc_release_region(sc, cr, RF_ACTIVE);
1114 * Examine bus state and make a best effort determination of whether it's
1115 * likely safe to enable the muxed SPROM pins.
1117 * On devices that do not use SPROM pin muxing, always returns true.
1119 * @param sc chipc driver state.
1122 chipc_should_enable_muxed_sprom(struct chipc_softc *sc)
1131 /* Nothing to do? */
1132 if (!CHIPC_QUIRK(sc, MUX_SPROM))
1135 mtx_lock(&Giant); /* for newbus */
1137 parent = device_get_parent(sc->dev);
1138 hostb = bhnd_bus_find_hostb_device(parent);
1140 if ((error = device_get_children(parent, &devs, &devcount))) {
1145 /* Reject any active devices other than ChipCommon, or the
1146 * host bridge (if any). */
1148 for (int i = 0; i < devcount; i++) {
1149 if (devs[i] == hostb || devs[i] == sc->dev)
1152 if (!device_is_attached(devs[i]))
1155 if (device_is_suspended(devs[i]))
1158 /* Active device; assume SPROM is busy */
1169 chipc_enable_sprom(device_t dev)
1171 struct chipc_softc *sc;
1174 sc = device_get_softc(dev);
1177 /* Already enabled? */
1178 if (sc->sprom_refcnt >= 1) {
1185 switch (sc->caps.nvram_src) {
1186 case BHND_NVRAM_SRC_SPROM:
1187 error = chipc_enable_sprom_pins(sc);
1189 case BHND_NVRAM_SRC_OTP:
1190 error = chipc_enable_otp_power(sc);
1197 /* Bump the reference count */
1206 chipc_disable_sprom(device_t dev)
1208 struct chipc_softc *sc;
1210 sc = device_get_softc(dev);
1213 /* Check reference count, skip disable if in-use. */
1214 KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease"));
1216 if (sc->sprom_refcnt > 0) {
1221 switch (sc->caps.nvram_src) {
1222 case BHND_NVRAM_SRC_SPROM:
1223 chipc_disable_sprom_pins(sc);
1225 case BHND_NVRAM_SRC_OTP:
1226 chipc_disable_otp_power(sc);
1237 chipc_enable_otp_power(struct chipc_softc *sc)
1239 // TODO: Enable OTP resource via PMU, and wait up to 100 usec for
1240 // OTPS_READY to be set in `optstatus`.
1245 chipc_disable_otp_power(struct chipc_softc *sc)
1247 // TODO: Disable OTP resource via PMU
1251 * If required by this device, enable access to the SPROM.
1253 * @param sc chipc driver state.
1256 chipc_enable_sprom_pins(struct chipc_softc *sc)
1260 CHIPC_LOCK_ASSERT(sc, MA_OWNED);
1261 KASSERT(sc->sprom_refcnt == 0, ("sprom pins already enabled"));
1263 /* Nothing to do? */
1264 if (!CHIPC_QUIRK(sc, MUX_SPROM))
1267 /* Check whether bus is busy */
1268 if (!chipc_should_enable_muxed_sprom(sc))
1271 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
1274 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) {
1275 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN;
1277 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM))
1278 cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5;
1280 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM))
1281 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2;
1283 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
1288 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) {
1292 /* Refuse to proceed on unsupported devices with muxed SPROM pins */
1293 device_printf(sc->dev, "muxed sprom lines on unrecognized device\n");
1298 * If required by this device, revert any GPIO/pin configuration applied
1299 * to allow SPROM access.
1301 * @param sc chipc driver state.
1304 chipc_disable_sprom_pins(struct chipc_softc *sc)
1308 /* Nothing to do? */
1309 if (!CHIPC_QUIRK(sc, MUX_SPROM))
1312 CHIPC_LOCK_ASSERT(sc, MA_OWNED);
1313 KASSERT(sc->sprom_refcnt == 0, ("sprom pins in use"));
1315 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
1318 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) {
1319 cctrl |= CHIPC_CCTRL4331_EXTPA_EN;
1321 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM))
1322 cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5;
1324 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM))
1325 cctrl |= CHIPC_CCTRL4331_EXTPA_EN2;
1327 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
1332 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) {
1338 chipc_read_chipst(device_t dev)
1340 struct chipc_softc *sc = device_get_softc(dev);
1341 return (bhnd_bus_read_4(sc->core, CHIPC_CHIPST));
1345 chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask)
1347 struct chipc_softc *sc;
1350 sc = device_get_softc(dev);
1354 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
1355 cctrl = (cctrl & ~mask) | (value | mask);
1356 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
1361 static struct chipc_caps *
1362 chipc_get_caps(device_t dev)
1364 struct chipc_softc *sc;
1366 sc = device_get_softc(dev);
1370 static device_method_t chipc_methods[] = {
1371 /* Device interface */
1372 DEVMETHOD(device_probe, chipc_probe),
1373 DEVMETHOD(device_attach, chipc_attach),
1374 DEVMETHOD(device_detach, chipc_detach),
1375 DEVMETHOD(device_suspend, chipc_suspend),
1376 DEVMETHOD(device_resume, chipc_resume),
1379 DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch),
1380 DEVMETHOD(bus_print_child, chipc_print_child),
1381 DEVMETHOD(bus_child_pnpinfo_str, chipc_child_pnpinfo_str),
1382 DEVMETHOD(bus_child_location_str, chipc_child_location_str),
1384 DEVMETHOD(bus_add_child, chipc_add_child),
1385 DEVMETHOD(bus_child_deleted, chipc_child_deleted),
1387 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
1388 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
1389 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource),
1390 DEVMETHOD(bus_alloc_resource, chipc_alloc_resource),
1391 DEVMETHOD(bus_release_resource, chipc_release_resource),
1392 DEVMETHOD(bus_adjust_resource, chipc_adjust_resource),
1393 DEVMETHOD(bus_activate_resource, chipc_activate_resource),
1394 DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource),
1395 DEVMETHOD(bus_get_resource_list, chipc_get_resource_list),
1397 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1398 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1399 DEVMETHOD(bus_config_intr, bus_generic_config_intr),
1400 DEVMETHOD(bus_bind_intr, bus_generic_bind_intr),
1401 DEVMETHOD(bus_describe_intr, bus_generic_describe_intr),
1403 /* BHND bus inteface */
1404 DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource),
1406 /* ChipCommon interface */
1407 DEVMETHOD(bhnd_chipc_read_chipst, chipc_read_chipst),
1408 DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl),
1409 DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom),
1410 DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom),
1411 DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps),
1416 DEFINE_CLASS_0(bhnd_chipc, bhnd_chipc_driver, chipc_methods, sizeof(struct chipc_softc));
1417 EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, bhnd_chipc_driver, bhnd_chipc_devclass, 0, 0,
1418 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
1419 MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1);
1420 MODULE_VERSION(bhnd_chipc, 1);