2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
3 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com>
4 * Copyright (c) 2017 The FreeBSD Foundation
7 * This software was developed by Landon Fuller under sponsorship from
8 * the FreeBSD Foundation.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
25 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
26 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
27 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
30 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGES.
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
39 * Broadcom ChipCommon driver.
41 * With the exception of some very early chipsets, the ChipCommon core
42 * has been included in all HND SoCs and chipsets based on the siba(4)
43 * and bcma(4) interconnects, providing a common interface to chipset
44 * identification, bus enumeration, UARTs, clocks, watchdog interrupts,
48 #include <sys/param.h>
49 #include <sys/kernel.h>
53 #include <sys/malloc.h>
54 #include <sys/module.h>
55 #include <sys/mutex.h>
56 #include <sys/systm.h>
58 #include <machine/bus.h>
59 #include <machine/resource.h>
61 #include <dev/bhnd/bhnd.h>
62 #include <dev/bhnd/bhndvar.h>
67 #include "chipc_private.h"
69 devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */
71 static struct bhnd_device_quirk chipc_quirks[];
73 /* Supported device identifiers */
74 static const struct bhnd_device chipc_devices[] = {
75 BHND_DEVICE(BCM, CC, NULL, chipc_quirks),
76 BHND_DEVICE(BCM, 4706_CC, NULL, chipc_quirks),
81 /* Device quirks table */
82 static struct bhnd_device_quirk chipc_quirks[] = {
83 /* HND OTP controller revisions */
84 BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */
85 BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */
86 BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */
88 /* IPX OTP controller revisions */
89 BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX),
90 BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX),
92 BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM),
93 BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT),
94 BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE),
96 /* 4706 variant quirks */
97 BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */
98 BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH),
101 BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM),
102 BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM),
103 BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM),
104 BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM),
107 BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
108 BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
109 BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
110 BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM),
112 BHND_DEVICE_QUIRK_END
115 // FIXME: IRQ shouldn't be hard-coded
116 #define CHIPC_MIPS_IRQ 2
118 static int chipc_add_children(struct chipc_softc *sc);
120 static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc,
121 struct chipc_caps *caps);
122 static int chipc_read_caps(struct chipc_softc *sc,
123 struct chipc_caps *caps);
125 static bool chipc_should_enable_muxed_sprom(
126 struct chipc_softc *sc);
127 static int chipc_enable_otp_power(struct chipc_softc *sc);
128 static void chipc_disable_otp_power(struct chipc_softc *sc);
129 static int chipc_enable_sprom_pins(struct chipc_softc *sc);
130 static void chipc_disable_sprom_pins(struct chipc_softc *sc);
132 static int chipc_try_activate_resource(struct chipc_softc *sc,
133 device_t child, int type, int rid,
134 struct resource *r, bool req_direct);
136 static int chipc_init_rman(struct chipc_softc *sc);
137 static void chipc_free_rman(struct chipc_softc *sc);
138 static struct rman *chipc_get_rman(struct chipc_softc *sc, int type);
140 /* quirk and capability flag convenience macros */
141 #define CHIPC_QUIRK(_sc, _name) \
142 ((_sc)->quirks & CHIPC_QUIRK_ ## _name)
144 #define CHIPC_CAP(_sc, _name) \
147 #define CHIPC_ASSERT_QUIRK(_sc, name) \
148 KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set"))
150 #define CHIPC_ASSERT_CAP(_sc, name) \
151 KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set"))
154 chipc_probe(device_t dev)
156 const struct bhnd_device *id;
158 id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0]));
162 bhnd_set_default_core_desc(dev);
163 return (BUS_PROBE_DEFAULT);
167 chipc_attach(device_t dev)
169 struct chipc_softc *sc;
172 sc = device_get_softc(dev);
174 sc->quirks = bhnd_device_quirks(dev, chipc_devices,
175 sizeof(chipc_devices[0]));
176 sc->sprom_refcnt = 0;
179 STAILQ_INIT(&sc->mem_regions);
181 /* Set up resource management */
182 if ((error = chipc_init_rman(sc))) {
183 device_printf(sc->dev,
184 "failed to initialize chipc resource state: %d\n", error);
188 /* Allocate the region containing the chipc register block */
189 if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) {
194 error = chipc_retain_region(sc, sc->core_region,
195 RF_ALLOCATED|RF_ACTIVE);
197 sc->core_region = NULL;
201 /* Save a direct reference to our chipc registers */
202 sc->core = sc->core_region->cr_res;
204 /* Fetch and parse capability register(s) */
205 if ((error = chipc_read_caps(sc, &sc->caps)))
209 chipc_print_caps(sc->dev, &sc->caps);
211 /* Attach all supported child devices */
212 if ((error = chipc_add_children(sc)))
215 if ((error = bus_generic_attach(dev)))
218 /* Register ourselves with the bus */
219 if ((error = bhnd_register_provider(dev, BHND_SERVICE_CHIPC)))
225 device_delete_children(sc->dev);
227 if (sc->core_region != NULL) {
228 chipc_release_region(sc, sc->core_region,
229 RF_ALLOCATED|RF_ACTIVE);
233 CHIPC_LOCK_DESTROY(sc);
238 chipc_detach(device_t dev)
240 struct chipc_softc *sc;
243 sc = device_get_softc(dev);
245 if ((error = bhnd_deregister_provider(dev, BHND_SERVICE_ANY)))
248 if ((error = bus_generic_detach(dev)))
251 chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE);
254 CHIPC_LOCK_DESTROY(sc);
260 chipc_add_children(struct chipc_softc *sc)
263 const char *flash_bus;
267 if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM ||
268 sc->caps.nvram_src == BHND_NVRAM_SRC_OTP)
270 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", -1);
272 device_printf(sc->dev, "failed to add nvram device\n");
276 /* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */
277 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0,
278 CHIPC_SPROM_OTP, CHIPC_SPROM_OTP_SIZE, 0, 0);
286 * On AOB ("Always on Bus") devices, the PMU core (if it exists) is
287 * attached directly to the bhnd(4) bus -- not chipc.
289 if (sc->caps.pwr_ctrl || (sc->caps.pmu && !sc->caps.aob)) {
290 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", -1);
292 device_printf(sc->dev, "failed to add pmu\n");
297 /* All remaining devices are SoC-only */
298 if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE)
302 for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) {
303 child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1);
305 device_printf(sc->dev, "failed to add uart%u\n", i);
310 error = bus_set_resource(child, SYS_RES_IRQ, 0, CHIPC_MIPS_IRQ,
313 device_printf(sc->dev, "failed to set uart%u irq %u\n",
318 /* UART registers are mapped sequentially */
319 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0,
320 CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0);
326 flash_bus = chipc_flash_bus_name(sc->caps.flash_type);
327 if (flash_bus != NULL) {
328 child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, -1);
330 device_printf(sc->dev, "failed to add %s device\n",
335 /* flash memory mapping */
336 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 0,
337 0, RM_MAX_END, 1, 1);
341 /* flashctrl registers */
342 error = chipc_set_resource(sc, child, SYS_RES_MEMORY, 1,
343 CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0);
352 * Determine the NVRAM data source for this device.
354 * The SPROM, OTP, and flash capability flags must be fully populated in
357 * @param sc chipc driver state.
358 * @param caps capability flags to be used to derive NVRAM configuration.
360 static bhnd_nvram_src
361 chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps)
363 uint32_t otp_st, srom_ctrl;
366 * We check for hardware presence in order of precedence. For example,
367 * SPROM is is always used in preference to internal OTP if found.
369 if (CHIPC_QUIRK(sc, SUPPORTS_SPROM) && caps->sprom) {
370 srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL);
371 if (srom_ctrl & CHIPC_SRC_PRESENT)
372 return (BHND_NVRAM_SRC_SPROM);
375 /* Check for programmed OTP H/W subregion (contains SROM data) */
376 if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) {
377 /* TODO: need access to HND-OTP device */
378 if (!CHIPC_QUIRK(sc, OTP_HND)) {
379 device_printf(sc->dev,
380 "NVRAM unavailable: unsupported OTP controller.\n");
381 return (BHND_NVRAM_SRC_UNKNOWN);
384 otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST);
385 if (otp_st & CHIPC_OTPS_GUP_HW)
386 return (BHND_NVRAM_SRC_OTP);
389 /* Check for flash */
390 if (caps->flash_type != CHIPC_FLASH_NONE)
391 return (BHND_NVRAM_SRC_FLASH);
393 /* No NVRAM hardware capability declared */
394 return (BHND_NVRAM_SRC_UNKNOWN);
397 /* Read and parse chipc capabilities */
399 chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps)
402 uint32_t cap_ext_reg;
405 /* Fetch cap registers */
406 cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES);
408 if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT))
409 cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT);
412 caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART);
413 caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB);
414 caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO);
415 caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL);
417 caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS);
418 caps->pwr_ctrl = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL);
419 caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP);
421 caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL);
422 caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64);
423 caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM);
424 caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU);
425 caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI);
426 caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM);
427 caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE);
429 caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI);
430 caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO);
431 caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB);
433 /* Fetch OTP size for later IPX controller revisions */
434 if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) {
435 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT);
436 caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE);
439 /* Determine flash type and parameters */
441 switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) {
442 case CHIPC_CAP_SFLASH_ST:
443 caps->flash_type = CHIPC_SFLASH_ST;
445 case CHIPC_CAP_SFLASH_AT:
446 caps->flash_type = CHIPC_SFLASH_AT;
448 case CHIPC_CAP_NFLASH:
450 caps->flash_type = CHIPC_NFLASH;
452 case CHIPC_CAP_PFLASH:
453 caps->flash_type = CHIPC_PFLASH_CFI;
455 /* determine cfi width */
456 regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG);
457 if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS))
463 case CHIPC_CAP_FLASH_NONE:
464 caps->flash_type = CHIPC_FLASH_NONE;
469 /* Handle 4706_NFLASH fallback */
470 if (CHIPC_QUIRK(sc, 4706_NFLASH) &&
471 CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH))
473 caps->flash_type = CHIPC_NFLASH_4706;
477 /* Determine NVRAM source. Must occur after the SPROM/OTP/flash
478 * capability flags have been populated. */
479 caps->nvram_src = chipc_find_nvram_src(sc, caps);
481 /* Determine the SPROM offset within OTP (if any). SPROM-formatted
482 * data is placed within the OTP general use region. */
483 caps->sprom_offset = 0;
484 if (caps->nvram_src == BHND_NVRAM_SRC_OTP) {
485 CHIPC_ASSERT_QUIRK(sc, OTP_IPX);
487 /* Bit offset to GUP HW subregion containing SPROM data */
488 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT);
489 caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP);
491 /* Convert to bytes */
492 caps->sprom_offset /= 8;
499 chipc_suspend(device_t dev)
501 return (bus_generic_suspend(dev));
505 chipc_resume(device_t dev)
507 return (bus_generic_resume(dev));
511 chipc_probe_nomatch(device_t dev, device_t child)
513 struct resource_list *rl;
516 name = device_get_name(child);
518 name = "unknown device";
520 device_printf(dev, "<%s> at", name);
522 rl = BUS_GET_RESOURCE_LIST(dev, child);
524 resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx");
525 resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd");
528 printf(" (no driver attached)\n");
532 chipc_print_child(device_t dev, device_t child)
534 struct resource_list *rl;
537 retval += bus_print_child_header(dev, child);
539 rl = BUS_GET_RESOURCE_LIST(dev, child);
541 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY,
543 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ,
547 retval += bus_print_child_domain(dev, child);
548 retval += bus_print_child_footer(dev, child);
554 chipc_child_pnpinfo_str(device_t dev, device_t child, char *buf,
565 chipc_child_location_str(device_t dev, device_t child, char *buf,
576 chipc_add_child(device_t dev, u_int order, const char *name, int unit)
578 struct chipc_softc *sc;
579 struct chipc_devinfo *dinfo;
582 sc = device_get_softc(dev);
584 child = device_add_child_ordered(dev, order, name, unit);
588 dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT);
590 device_delete_child(dev, child);
594 resource_list_init(&dinfo->resources);
595 device_set_ivars(child, dinfo);
601 chipc_child_deleted(device_t dev, device_t child)
603 struct chipc_devinfo *dinfo = device_get_ivars(child);
606 resource_list_free(&dinfo->resources);
610 device_set_ivars(child, NULL);
613 static struct resource_list *
614 chipc_get_resource_list(device_t dev, device_t child)
616 struct chipc_devinfo *dinfo = device_get_ivars(child);
617 return (&dinfo->resources);
621 /* Allocate region records for the given port, and add the port's memory
622 * range to the mem_rman */
624 chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type,
627 struct chipc_region *cr;
628 rman_res_t start, end;
632 num_regions = bhnd_get_region_count(sc->dev, type, port);
633 for (u_int region = 0; region < num_regions; region++) {
634 /* Allocate new region record */
635 cr = chipc_alloc_region(sc, type, port, region);
639 /* Can't manage regions that cannot be allocated */
640 if (cr->cr_rid < 0) {
641 BHND_DEBUG_DEV(sc->dev, "no rid for chipc region "
642 "%s%u.%u", bhnd_port_type_name(type), port, region);
643 chipc_free_region(sc, cr);
647 /* Add to rman's managed range */
650 if ((error = rman_manage_region(&sc->mem_rman, start, end))) {
651 chipc_free_region(sc, cr);
655 /* Add to region list */
656 STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link);
662 /* Initialize memory state for all chipc port regions */
664 chipc_init_rman(struct chipc_softc *sc)
669 /* Port types for which we'll register chipc_region mappings */
670 bhnd_port_type types[] = {
674 /* Initialize resource manager */
675 sc->mem_rman.rm_start = 0;
676 sc->mem_rman.rm_end = BUS_SPACE_MAXADDR;
677 sc->mem_rman.rm_type = RMAN_ARRAY;
678 sc->mem_rman.rm_descr = "ChipCommon Device Memory";
679 if ((error = rman_init(&sc->mem_rman))) {
680 device_printf(sc->dev, "could not initialize mem_rman: %d\n",
685 /* Populate per-port-region state */
686 for (u_int i = 0; i < nitems(types); i++) {
687 num_ports = bhnd_get_port_count(sc->dev, types[i]);
688 for (u_int port = 0; port < num_ports; port++) {
689 error = chipc_rman_init_regions(sc, types[i], port);
691 device_printf(sc->dev,
692 "region init failed for %s%u: %d\n",
693 bhnd_port_type_name(types[i]), port,
708 /* Free memory management state */
710 chipc_free_rman(struct chipc_softc *sc)
712 struct chipc_region *cr, *cr_next;
714 STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next)
715 chipc_free_region(sc, cr);
717 rman_fini(&sc->mem_rman);
721 * Return the rman instance for a given resource @p type, if any.
723 * @param sc The chipc device state.
724 * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...)
727 chipc_get_rman(struct chipc_softc *sc, int type)
731 return (&sc->mem_rman);
734 /* IRQs can be used with RF_SHAREABLE, so we don't perform
735 * any local proxying of resource requests. */
743 static struct resource *
744 chipc_alloc_resource(device_t dev, device_t child, int type,
745 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
747 struct chipc_softc *sc;
748 struct chipc_region *cr;
749 struct resource_list_entry *rle;
753 bool passthrough, isdefault;
755 sc = device_get_softc(dev);
756 passthrough = (device_get_parent(child) != dev);
757 isdefault = RMAN_IS_DEFAULT_RANGE(start, end);
760 /* Fetch the resource manager, delegate request if necessary */
761 rm = chipc_get_rman(sc, type);
763 /* Requested resource type is delegated to our parent */
764 rv = bus_generic_rl_alloc_resource(dev, child, type, rid,
765 start, end, count, flags);
769 /* Populate defaults */
770 if (!passthrough && isdefault) {
771 /* Fetch the resource list entry. */
772 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child),
776 "default resource %#x type %d for child %s "
777 "not found\n", *rid, type,
778 device_get_nameunit(child));
782 if (rle->res != NULL) {
784 "resource entry %#x type %d for child %s is busy "
786 *rid, type, device_get_nameunit(child),
787 rman_get_flags(rle->res));
794 count = ulmax(count, rle->count);
797 /* Locate a mapping region */
798 if ((cr = chipc_find_region(sc, start, end)) == NULL) {
799 /* Resource requests outside our shared port regions can be
800 * delegated to our parent. */
801 rv = bus_generic_rl_alloc_resource(dev, child, type, rid,
802 start, end, count, flags);
806 /* Try to retain a region reference */
807 if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED)))
810 /* Make our rman reservation */
811 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE,
814 chipc_release_region(sc, cr, RF_ALLOCATED);
818 rman_set_rid(rv, *rid);
821 if (flags & RF_ACTIVE) {
822 error = bus_activate_resource(child, type, *rid, rv);
825 "failed to activate entry %#x type %d for "
827 *rid, type, device_get_nameunit(child), error);
829 chipc_release_region(sc, cr, RF_ALLOCATED);
830 rman_release_resource(rv);
836 /* Update child's resource list entry */
839 rle->start = rman_get_start(rv);
840 rle->end = rman_get_end(rv);
841 rle->count = rman_get_size(rv);
848 chipc_release_resource(device_t dev, device_t child, int type, int rid,
851 struct chipc_softc *sc;
852 struct chipc_region *cr;
854 struct resource_list_entry *rle;
857 sc = device_get_softc(dev);
859 /* Handled by parent bus? */
860 rm = chipc_get_rman(sc, type);
861 if (rm == NULL || !rman_is_region_manager(r, rm)) {
862 return (bus_generic_rl_release_resource(dev, child, type, rid,
866 /* Locate the mapping region */
867 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
871 /* Deactivate resources */
872 if (rman_get_flags(r) & RF_ACTIVE) {
873 error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r);
878 if ((error = rman_release_resource(r)))
881 /* Drop allocation reference */
882 chipc_release_region(sc, cr, RF_ALLOCATED);
884 /* Clear reference from the resource list entry if exists */
885 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid);
893 chipc_adjust_resource(device_t dev, device_t child, int type,
894 struct resource *r, rman_res_t start, rman_res_t end)
896 struct chipc_softc *sc;
897 struct chipc_region *cr;
900 sc = device_get_softc(dev);
902 /* Handled by parent bus? */
903 rm = chipc_get_rman(sc, type);
904 if (rm == NULL || !rman_is_region_manager(r, rm)) {
905 return (bus_generic_adjust_resource(dev, child, type, r, start,
909 /* The range is limited to the existing region mapping */
910 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
917 if (start < cr->cr_addr || end > cr->cr_end)
920 /* Range falls within the existing region */
921 return (rman_adjust_resource(r, start, end));
925 * Retain an RF_ACTIVE reference to the region mapping @p r, and
926 * configure @p r with its subregion values.
928 * @param sc Driver instance state.
929 * @param child Requesting child device.
930 * @param type resource type of @p r.
931 * @param rid resource id of @p r
932 * @param r resource to be activated.
933 * @param req_direct If true, failure to allocate a direct bhnd resource
934 * will be treated as an error. If false, the resource will not be marked
935 * as RF_ACTIVE if bhnd direct resource allocation fails.
938 chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type,
939 int rid, struct resource *r, bool req_direct)
942 struct chipc_region *cr;
943 bhnd_size_t cr_offset;
944 rman_res_t r_start, r_end, r_size;
947 rm = chipc_get_rman(sc, type);
948 if (rm == NULL || !rman_is_region_manager(r, rm))
951 r_start = rman_get_start(r);
952 r_end = rman_get_end(r);
953 r_size = rman_get_size(r);
955 /* Find the corresponding chipc region */
956 cr = chipc_find_region(sc, r_start, r_end);
960 /* Calculate subregion offset within the chipc region */
961 cr_offset = r_start - cr->cr_addr;
963 /* Retain (and activate, if necessary) the chipc region */
964 if ((error = chipc_retain_region(sc, cr, RF_ACTIVE)))
967 /* Configure child resource with its subregion values. */
968 if (cr->cr_res->direct) {
969 error = chipc_init_child_resource(r, cr->cr_res->res,
975 if ((error = rman_activate_resource(r)))
977 } else if (req_direct) {
985 chipc_release_region(sc, cr, RF_ACTIVE);
990 chipc_activate_bhnd_resource(device_t dev, device_t child, int type,
991 int rid, struct bhnd_resource *r)
993 struct chipc_softc *sc;
997 sc = device_get_softc(dev);
999 /* Delegate non-locally managed resources to parent */
1000 rm = chipc_get_rman(sc, type);
1001 if (rm == NULL || !rman_is_region_manager(r->res, rm)) {
1002 return (bhnd_bus_generic_activate_resource(dev, child, type,
1006 /* Try activating the chipc region resource */
1007 error = chipc_try_activate_resource(sc, child, type, rid, r->res,
1012 /* Mark the child resource as direct according to the returned resource
1014 if (rman_get_flags(r->res) & RF_ACTIVE)
1021 chipc_activate_resource(device_t dev, device_t child, int type, int rid,
1024 struct chipc_softc *sc;
1027 sc = device_get_softc(dev);
1029 /* Delegate non-locally managed resources to parent */
1030 rm = chipc_get_rman(sc, type);
1031 if (rm == NULL || !rman_is_region_manager(r, rm)) {
1032 return (bus_generic_activate_resource(dev, child, type, rid,
1036 /* Try activating the chipc region-based resource */
1037 return (chipc_try_activate_resource(sc, child, type, rid, r, true));
1041 * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE().
1044 chipc_deactivate_resource(device_t dev, device_t child, int type,
1045 int rid, struct resource *r)
1047 struct chipc_softc *sc;
1048 struct chipc_region *cr;
1052 sc = device_get_softc(dev);
1054 /* Handled by parent bus? */
1055 rm = chipc_get_rman(sc, type);
1056 if (rm == NULL || !rman_is_region_manager(r, rm)) {
1057 return (bus_generic_deactivate_resource(dev, child, type, rid,
1061 /* Find the corresponding chipc region */
1062 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
1067 if ((error = rman_deactivate_resource(r)))
1070 /* Drop associated RF_ACTIVE reference */
1071 chipc_release_region(sc, cr, RF_ACTIVE);
1077 * Examine bus state and make a best effort determination of whether it's
1078 * likely safe to enable the muxed SPROM pins.
1080 * On devices that do not use SPROM pin muxing, always returns true.
1082 * @param sc chipc driver state.
1085 chipc_should_enable_muxed_sprom(struct chipc_softc *sc)
1094 /* Nothing to do? */
1095 if (!CHIPC_QUIRK(sc, MUX_SPROM))
1098 mtx_lock(&Giant); /* for newbus */
1100 parent = device_get_parent(sc->dev);
1101 hostb = bhnd_bus_find_hostb_device(parent);
1103 if ((error = device_get_children(parent, &devs, &devcount))) {
1108 /* Reject any active devices other than ChipCommon, or the
1109 * host bridge (if any). */
1111 for (int i = 0; i < devcount; i++) {
1112 if (devs[i] == hostb || devs[i] == sc->dev)
1115 if (!device_is_attached(devs[i]))
1118 if (device_is_suspended(devs[i]))
1121 /* Active device; assume SPROM is busy */
1132 chipc_enable_sprom(device_t dev)
1134 struct chipc_softc *sc;
1137 sc = device_get_softc(dev);
1140 /* Already enabled? */
1141 if (sc->sprom_refcnt >= 1) {
1148 switch (sc->caps.nvram_src) {
1149 case BHND_NVRAM_SRC_SPROM:
1150 error = chipc_enable_sprom_pins(sc);
1152 case BHND_NVRAM_SRC_OTP:
1153 error = chipc_enable_otp_power(sc);
1160 /* Bump the reference count */
1169 chipc_disable_sprom(device_t dev)
1171 struct chipc_softc *sc;
1173 sc = device_get_softc(dev);
1176 /* Check reference count, skip disable if in-use. */
1177 KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease"));
1179 if (sc->sprom_refcnt > 0) {
1184 switch (sc->caps.nvram_src) {
1185 case BHND_NVRAM_SRC_SPROM:
1186 chipc_disable_sprom_pins(sc);
1188 case BHND_NVRAM_SRC_OTP:
1189 chipc_disable_otp_power(sc);
1200 chipc_enable_otp_power(struct chipc_softc *sc)
1202 // TODO: Enable OTP resource via PMU, and wait up to 100 usec for
1203 // OTPS_READY to be set in `optstatus`.
1208 chipc_disable_otp_power(struct chipc_softc *sc)
1210 // TODO: Disable OTP resource via PMU
1214 * If required by this device, enable access to the SPROM.
1216 * @param sc chipc driver state.
1219 chipc_enable_sprom_pins(struct chipc_softc *sc)
1223 CHIPC_LOCK_ASSERT(sc, MA_OWNED);
1224 KASSERT(sc->sprom_refcnt == 0, ("sprom pins already enabled"));
1226 /* Nothing to do? */
1227 if (!CHIPC_QUIRK(sc, MUX_SPROM))
1230 /* Check whether bus is busy */
1231 if (!chipc_should_enable_muxed_sprom(sc))
1234 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
1237 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) {
1238 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN;
1240 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM))
1241 cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5;
1243 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM))
1244 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2;
1246 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
1251 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) {
1255 /* Refuse to proceed on unsupported devices with muxed SPROM pins */
1256 device_printf(sc->dev, "muxed sprom lines on unrecognized device\n");
1261 * If required by this device, revert any GPIO/pin configuration applied
1262 * to allow SPROM access.
1264 * @param sc chipc driver state.
1267 chipc_disable_sprom_pins(struct chipc_softc *sc)
1271 /* Nothing to do? */
1272 if (!CHIPC_QUIRK(sc, MUX_SPROM))
1275 CHIPC_LOCK_ASSERT(sc, MA_OWNED);
1276 KASSERT(sc->sprom_refcnt == 0, ("sprom pins in use"));
1278 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
1281 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) {
1282 cctrl |= CHIPC_CCTRL4331_EXTPA_EN;
1284 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM))
1285 cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5;
1287 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM))
1288 cctrl |= CHIPC_CCTRL4331_EXTPA_EN2;
1290 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
1295 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) {
1301 chipc_read_chipst(device_t dev)
1303 struct chipc_softc *sc = device_get_softc(dev);
1304 return (bhnd_bus_read_4(sc->core, CHIPC_CHIPST));
1308 chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask)
1310 struct chipc_softc *sc;
1313 sc = device_get_softc(dev);
1317 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
1318 cctrl = (cctrl & ~mask) | (value | mask);
1319 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
1324 static struct chipc_caps *
1325 chipc_get_caps(device_t dev)
1327 struct chipc_softc *sc;
1329 sc = device_get_softc(dev);
1333 static device_method_t chipc_methods[] = {
1334 /* Device interface */
1335 DEVMETHOD(device_probe, chipc_probe),
1336 DEVMETHOD(device_attach, chipc_attach),
1337 DEVMETHOD(device_detach, chipc_detach),
1338 DEVMETHOD(device_suspend, chipc_suspend),
1339 DEVMETHOD(device_resume, chipc_resume),
1342 DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch),
1343 DEVMETHOD(bus_print_child, chipc_print_child),
1344 DEVMETHOD(bus_child_pnpinfo_str, chipc_child_pnpinfo_str),
1345 DEVMETHOD(bus_child_location_str, chipc_child_location_str),
1347 DEVMETHOD(bus_add_child, chipc_add_child),
1348 DEVMETHOD(bus_child_deleted, chipc_child_deleted),
1350 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
1351 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
1352 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource),
1353 DEVMETHOD(bus_alloc_resource, chipc_alloc_resource),
1354 DEVMETHOD(bus_release_resource, chipc_release_resource),
1355 DEVMETHOD(bus_adjust_resource, chipc_adjust_resource),
1356 DEVMETHOD(bus_activate_resource, chipc_activate_resource),
1357 DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource),
1358 DEVMETHOD(bus_get_resource_list, chipc_get_resource_list),
1360 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1361 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1362 DEVMETHOD(bus_config_intr, bus_generic_config_intr),
1363 DEVMETHOD(bus_bind_intr, bus_generic_bind_intr),
1364 DEVMETHOD(bus_describe_intr, bus_generic_describe_intr),
1366 /* BHND bus inteface */
1367 DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource),
1369 /* ChipCommon interface */
1370 DEVMETHOD(bhnd_chipc_read_chipst, chipc_read_chipst),
1371 DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl),
1372 DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom),
1373 DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom),
1374 DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps),
1379 DEFINE_CLASS_0(bhnd_chipc, bhnd_chipc_driver, chipc_methods, sizeof(struct chipc_softc));
1380 EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, bhnd_chipc_driver, bhnd_chipc_devclass, 0, 0,
1381 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
1382 MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1);
1383 MODULE_VERSION(bhnd_chipc, 1);