2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
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34 #ifndef _BHND_CORES_CHIPC_CHIPC_H_
35 #define _BHND_CORES_CHIPC_CHIPC_H_
37 #include <dev/bhnd/bhnd.h>
38 #include <dev/bhnd/nvram/bhnd_nvram.h>
40 #include "bhnd_chipc_if.h"
43 * Supported ChipCommon flash types.
46 CHIPC_FLASH_NONE = 0, /**< No flash, or a type unrecognized
47 by the ChipCommon driver */
48 CHIPC_PFLASH_CFI = 1, /**< CFI-compatible parallel flash */
49 CHIPC_SFLASH_ST = 2, /**< ST serial flash */
50 CHIPC_SFLASH_AT = 3, /**< Atmel serial flash */
51 CHIPC_QSFLASH_ST = 4, /**< ST quad-SPI flash */
52 CHIPC_QSFLASH_AT = 5, /**< Atmel quad-SPI flash */
53 CHIPC_NFLASH = 6, /**< NAND flash */
54 CHIPC_NFLASH_4706 = 7 /**< BCM4706 NAND flash */
58 * ChipCommon capability flags;
61 uint8_t num_uarts; /**< Number of attached UARTS (1-3) */
62 bool mipseb; /**< MIPS is big-endian */
63 uint8_t uart_clock; /**< UART clock source (see CHIPC_CAP_UCLKSEL_*) */
64 uint8_t uart_gpio; /**< UARTs own GPIO pins 12-15 */
66 uint8_t extbus_type; /**< ExtBus type (CHIPC_CAP_EXTBUS_*) */
68 chipc_flash flash_type; /**< flash type */
69 uint8_t cfi_width; /**< CFI bus width, 0 if unknown or CFI
72 bhnd_nvram_src nvram_src; /**< identified NVRAM source */
73 bus_size_t sprom_offset; /**< Offset to SPROM data within
74 SPROM/OTP, 0 if unknown or not
76 uint8_t otp_size; /**< OTP (row?) size, 0 if not present */
78 uint8_t pll_type; /**< PLL type */
79 bool pwr_ctrl; /**< Power/clock control available */
80 bool jtag_master; /**< JTAG Master present */
81 bool boot_rom; /**< Internal boot ROM is active */
82 uint8_t backplane_64; /**< Backplane supports 64-bit addressing.
83 Note that this does not gaurantee
84 the CPU itself supports 64-bit
86 bool pmu; /**< PMU is present. */
87 bool eci; /**< ECI (enhanced coexistence inteface) is present. */
88 bool seci; /**< SECI (serial ECI) is present */
89 bool sprom; /**< SPROM is present */
90 bool gsio; /**< GSIO (SPI/I2C) present */
91 bool aob; /**< AOB (always on bus) present.
92 If set, PMU and GCI registers are
93 not accessible via ChipCommon,
94 and are instead accessible via
95 dedicated cores on the bhnd bus */
98 #endif /* _BHND_CORES_CHIPC_CHIPC_H_ */