2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2017 The FreeBSD Foundation
7 * This software was developed by Landon Fuller under sponsorship from
8 * the FreeBSD Foundation.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 #ifndef _BHND_CORES_CHIPC_CHIPC_GPIOVAR_H_
35 #define _BHND_CORES_CHIPC_CHIPC_GPIOVAR_H_
37 #include <sys/param.h>
41 #include <sys/mutex.h>
43 #include <dev/bhnd/bhnd.h>
46 * ChipCommon GPIO device quirks.
50 * No GPIO event support.
52 * The CHIPC_GPIOEVENT, CHIPC_GPIOEVENT_INTM, and
53 * CHIPC_GPIOEVENT_INTPOLARITY registers are not available.
55 CC_GPIO_QUIRK_NO_EVENTS = (1<<0),
58 * No GPIO duty-cycle timer support.
60 * The CHIPC_GPIOTIMERVAL and CHIPC_GPIOTIMEROUTMASK registers are not
63 CC_GPIO_QUIRK_NO_DCTIMER = (1<<1),
66 * No GPIO pull-up/pull-down configuration support.
68 * The CHIPC_GPIOPU and CHIPC_GPIOPD registers are not available.
70 CC_GPIO_QUIRK_NO_PULLUPDOWN = (1<<2),
73 * Do not attach a child gpioc(4) device.
75 * This is primarily intended for use on bridged Wi-Fi adapters, where
76 * userspace modification of GPIO pin configuration could introduce
77 * significant undesirable behavior.
79 CC_GPIO_QUIRK_NO_GPIOC = (1<<3),
82 /** ChipCommon GPIO pin modes */
87 } chipc_gpio_pin_mode;
90 * A single GPIO update register.
92 struct chipc_gpio_reg {
93 uint32_t value; /**< register update value */
94 uint32_t mask; /**< register update mask */
98 * A GPIO register update descriptor.
100 struct chipc_gpio_update {
101 struct chipc_gpio_reg pullup; /**< CHIPC_GPIOPU changes */
102 struct chipc_gpio_reg pulldown; /**< CHIPC_GPIOPD changes */
103 struct chipc_gpio_reg out; /**< CHIPC_GPIOOUT changes */
104 struct chipc_gpio_reg outen; /**< CHIPC_GPIOOUTEN changes */
105 struct chipc_gpio_reg timeroutmask; /**< CHIPC_GPIOTIMEROUTMASK changes */
106 struct chipc_gpio_reg ctrl; /**< CHIPC_GPIOCTRL changes */
109 #define CC_GPIO_UPDATE(_upd, _pin, _reg, _val) do { \
110 (_upd)->_reg.mask |= (1 << (_pin)); \
112 (_upd)->_reg.value |= (1 << (_pin)); \
114 (_upd)->_reg.value &= ~(1 << (_pin)); \
118 * ChipCommon GPIO driver instance state.
120 struct chipc_gpio_softc {
122 device_t gpiobus; /**< attached gpiobus child */
123 struct bhnd_resource *mem_res; /**< chipcommon register block */
124 int mem_rid; /**< resource ID of mem_res */
125 uint32_t quirks; /**< device quirks (see CC_GPIO_QUIRK_*) */
126 struct mtx mtx; /**< lock protecting RMW register access */
129 #define CC_GPIO_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \
130 device_get_nameunit((sc)->dev), NULL, MTX_DEF)
131 #define CC_GPIO_LOCK(sc) mtx_lock(&(sc)->mtx)
132 #define CC_GPIO_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
133 #define CC_GPIO_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what)
134 #define CC_GPIO_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx)
136 #define CC_GPIO_WR4(sc, off, val) \
137 bhnd_bus_write_4((sc)->mem_res, (off), (val))
138 #define CC_GPIO_WRFLAG(sc, pin_num, flag, val) \
139 CC_GPIO_WR4(sc, CHIPC_ ## flag, \
140 (CC_GPIO_RD4(sc, CHIPC_ ## flag) & ~(1 << pin_num)) | \
141 (val ? (1 << pin_num) : 0))
143 #define CC_GPIO_RD4(sc, off) \
144 bhnd_bus_read_4((sc)->mem_res, (off))
145 #define CC_GPIO_RDFLAG(sc, pin_num, flag) \
146 ((CC_GPIO_RD4(sc, CHIPC_ ## flag) & (1 << pin_num)) != 0)
148 #define CC_GPIO_NPINS 32
149 #define CC_GPIO_VALID_PIN(_pin) \
150 ((_pin) >= 0 && (_pin) < CC_GPIO_NPINS)
151 #define CC_GPIO_VALID_PINS(_first, _num) \
152 ((_num) <= CC_GPIO_NPINS && CC_GPIO_NPINS - (_num) >= _first)
154 #define CC_GPIO_ASSERT_VALID_PIN(sc, pin_num) \
155 KASSERT(CC_GPIO_VALID_PIN(pin_num), ("invalid pin# %" PRIu32, pin_num));
157 #define CC_GPIO_QUIRK(_sc, _name) \
158 ((_sc)->quirks & CC_GPIO_QUIRK_ ## _name)
160 #define CC_GPIO_ASSERT_QUIRK(_sc, name) \
161 KASSERT(CC_GPIO_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set"))
163 #endif /* _BHND_PWRCTL_BHND_PWRCTLVAR_H_ */