2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
5 * Redistribution and use in source and binary forms, with or without
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11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
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32 #ifndef _BHND_CORES_CHIPC_CHIPCVAR_H_
33 #define _BHND_CORES_CHIPC_CHIPCVAR_H_
35 #include <sys/types.h>
38 #include <dev/bhnd/nvram/bhnd_spromvar.h>
42 DECLARE_CLASS(bhnd_chipc_driver);
43 extern devclass_t bhnd_chipc_devclass;
47 const char *chipc_flash_name(chipc_flash type);
48 const char *chipc_flash_bus_name(chipc_flash type);
49 const char *chipc_sflash_device_name(chipc_flash type);
52 * ChipCommon device quirks / features
59 * ChipCommon-controlled SPROM/OTP is supported, along with the
60 * CHIPC_CAP_SPROM capability flag.
62 CHIPC_QUIRK_SUPPORTS_SPROM = (1<<1),
65 * The BCM4706 NAND flash interface is supported, along with the
66 * CHIPC_CAP_4706_NFLASH capability flag.
68 CHIPC_QUIRK_4706_NFLASH = (1<<2),
71 * The SPROM is attached via muxed pins. The pins must be switched
72 * to allow reading/writing.
74 CHIPC_QUIRK_MUX_SPROM = (1<<3),
77 * Access to the SPROM uses pins shared with the 802.11a external PA.
79 * On modules using these 4331 packages, the CCTRL4331_EXTPA_EN flag
80 * must be cleared to allow SPROM access.
82 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM = (1<<4) |
83 CHIPC_QUIRK_MUX_SPROM,
86 * Access to the SPROM uses pins shared with the 802.11a external PA.
88 * On modules using these 4331 chip packages, the external PA is
89 * attached via GPIO 2, 5, and sprom_dout pins.
91 * When enabling and disabling EXTPA to allow SPROM access, the
92 * CCTRL4331_EXTPA_ON_GPIO2_5 flag must also be set or cleared,
95 CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM = (1<<5) |
96 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM,
99 * Access to the SPROM uses pins shared with two 802.11a external PAs.
101 * When enabling and disabling EXTPA, the CCTRL4331_EXTPA_EN2 must also
102 * be cleared to allow SPROM access.
104 CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM = (1<<6) |
105 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM,
109 * SPROM pins are muxed with the FEM control lines on this 4360-family
110 * device. The muxed pins must be switched to allow reading/writing
113 CHIPC_QUIRK_4360_FEM_MUX_SPROM = (1<<5) |
114 CHIPC_QUIRK_MUX_SPROM,
116 /** Supports CHIPC_CAPABILITIES_EXT register */
117 CHIPC_QUIRK_SUPPORTS_CAP_EXT = (1<<6),
119 /** Supports HND or IPX OTP registers (CHIPC_OTPST, CHIPC_OTPCTRL,
121 CHIPC_QUIRK_SUPPORTS_OTP = (1<<7),
123 /** Supports HND OTP registers. */
124 CHIPC_QUIRK_OTP_HND = (1<<8) |
125 CHIPC_QUIRK_SUPPORTS_OTP,
127 /** Supports IPX OTP registers. */
128 CHIPC_QUIRK_OTP_IPX = (1<<9) |
129 CHIPC_QUIRK_SUPPORTS_OTP,
131 /** OTP size is defined via CHIPC_OTPLAYOUT register in later
132 * ChipCommon revisions using the 'IPX' OTP controller. */
133 CHIPC_QUIRK_IPX_OTPL_SIZE = (1<<10)
137 * chipc child device info.
139 struct chipc_devinfo {
140 struct resource_list resources; /**< child resources */
144 * chipc driver instance state.
149 struct bhnd_resource *core; /**< core registers. */
150 struct chipc_region *core_region; /**< region containing core registers */
152 uint32_t quirks; /**< chipc quirk flags */
153 struct chipc_caps caps; /**< chipc capabilities */
155 struct mtx mtx; /**< state mutex. */
156 size_t sprom_refcnt; /**< SPROM pin enable refcount */
157 struct rman mem_rman; /**< port memory manager */
158 STAILQ_HEAD(, chipc_region) mem_regions;/**< memory allocation records */
161 #define CHIPC_LOCK_INIT(sc) \
162 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \
163 "BHND chipc driver lock", MTX_DEF)
164 #define CHIPC_LOCK(sc) mtx_lock(&(sc)->mtx)
165 #define CHIPC_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
166 #define CHIPC_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what)
167 #define CHIPC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx)
169 #endif /* _BHND_CORES_CHIPC_CHIPCVAR_H_ */