2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
5 * Copyright (c) 2017 The FreeBSD Foundation
8 * Portions of this software were developed by Landon Fuller
9 * under sponsorship from the FreeBSD Foundation.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer,
16 * without modification.
17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
18 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
19 * redistribution must be conditioned upon including a substantially
20 * similar Disclaimer requirement for further binary redistribution.
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
26 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
27 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
28 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
31 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGES.
38 #ifndef _BHND_CORES_CHIPC_CHIPCVAR_H_
39 #define _BHND_CORES_CHIPC_CHIPCVAR_H_
41 #include <sys/types.h>
44 #include <dev/bhnd/nvram/bhnd_spromvar.h>
48 DECLARE_CLASS(bhnd_chipc_driver);
49 extern devclass_t bhnd_chipc_devclass;
53 const char *chipc_flash_name(chipc_flash type);
54 const char *chipc_flash_bus_name(chipc_flash type);
55 const char *chipc_sflash_device_name(chipc_flash type);
58 * ChipCommon device quirks / features
65 * ChipCommon-controlled SPROM/OTP is supported, along with the
66 * CHIPC_CAP_SPROM capability flag.
68 CHIPC_QUIRK_SUPPORTS_SPROM = (1<<1),
71 * The BCM4706 NAND flash interface is supported, along with the
72 * CHIPC_CAP_4706_NFLASH capability flag.
74 CHIPC_QUIRK_4706_NFLASH = (1<<2),
77 * The SPROM is attached via muxed pins. The pins must be switched
78 * to allow reading/writing.
80 CHIPC_QUIRK_MUX_SPROM = (1<<3),
83 * Access to the SPROM uses pins shared with the 802.11a external PA.
85 * On modules using these 4331 packages, the CCTRL4331_EXTPA_EN flag
86 * must be cleared to allow SPROM access.
88 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM = (1<<4) |
89 CHIPC_QUIRK_MUX_SPROM,
92 * Access to the SPROM uses pins shared with the 802.11a external PA.
94 * On modules using these 4331 chip packages, the external PA is
95 * attached via GPIO 2, 5, and sprom_dout pins.
97 * When enabling and disabling EXTPA to allow SPROM access, the
98 * CCTRL4331_EXTPA_ON_GPIO2_5 flag must also be set or cleared,
101 CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM = (1<<5) |
102 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM,
105 * Access to the SPROM uses pins shared with two 802.11a external PAs.
107 * When enabling and disabling EXTPA, the CCTRL4331_EXTPA_EN2 must also
108 * be cleared to allow SPROM access.
110 CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM = (1<<6) |
111 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM,
115 * SPROM pins are muxed with the FEM control lines on this 4360-family
116 * device. The muxed pins must be switched to allow reading/writing
119 CHIPC_QUIRK_4360_FEM_MUX_SPROM = (1<<5) |
120 CHIPC_QUIRK_MUX_SPROM,
122 /** Supports CHIPC_CAPABILITIES_EXT register */
123 CHIPC_QUIRK_SUPPORTS_CAP_EXT = (1<<6),
125 /** Supports HND or IPX OTP registers (CHIPC_OTPST, CHIPC_OTPCTRL,
127 CHIPC_QUIRK_SUPPORTS_OTP = (1<<7),
129 /** Supports HND OTP registers. */
130 CHIPC_QUIRK_OTP_HND = (1<<8) |
131 CHIPC_QUIRK_SUPPORTS_OTP,
133 /** Supports IPX OTP registers. */
134 CHIPC_QUIRK_OTP_IPX = (1<<9) |
135 CHIPC_QUIRK_SUPPORTS_OTP,
137 /** OTP size is defined via CHIPC_OTPLAYOUT register in later
138 * ChipCommon revisions using the 'IPX' OTP controller. */
139 CHIPC_QUIRK_IPX_OTPL_SIZE = (1<<10)
143 * chipc child device info.
145 struct chipc_devinfo {
146 struct resource_list resources; /**< child resources */
147 rman_res_t irq; /**< child IRQ, if mapped */
148 bool irq_mapped; /**< true if IRQ mapped, false otherwise */
152 * chipc driver instance state.
157 struct bhnd_resource *core; /**< core registers. */
158 struct chipc_region *core_region; /**< region containing core registers */
160 uint32_t quirks; /**< chipc quirk flags */
161 struct chipc_caps caps; /**< chipc capabilities */
163 struct mtx mtx; /**< state mutex. */
164 size_t sprom_refcnt; /**< SPROM pin enable refcount */
165 struct rman mem_rman; /**< port memory manager */
166 STAILQ_HEAD(, chipc_region) mem_regions;/**< memory allocation records */
169 #define CHIPC_LOCK_INIT(sc) \
170 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \
171 "BHND chipc driver lock", MTX_DEF)
172 #define CHIPC_LOCK(sc) mtx_lock(&(sc)->mtx)
173 #define CHIPC_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
174 #define CHIPC_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what)
175 #define CHIPC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx)
177 #endif /* _BHND_CORES_CHIPC_CHIPCVAR_H_ */