2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Broadcom Common PCI/PCIe Support.
36 * This base driver implementation is shared by the bhnd_pcib (root complex)
37 * and bhnd_pci_hostb (host bridge) drivers.
40 #include <sys/param.h>
41 #include <sys/malloc.h>
42 #include <sys/kernel.h>
44 #include <sys/module.h>
45 #include <sys/systm.h>
47 #include <machine/bus.h>
49 #include <machine/resource.h>
51 #include <dev/bhnd/bhnd.h>
52 #include <dev/mdio/mdio.h>
54 #include "bhnd_pcireg.h"
55 #include "bhnd_pcivar.h"
57 static int bhnd_pcie_mdio_wait_idle(struct bhnd_pci_softc *sc);
58 static int bhnd_pcie_mdio_ioctl(struct bhnd_pci_softc *sc, uint32_t cmd);
59 static int bhnd_pcie_mdio_enable(struct bhnd_pci_softc *sc);
60 static void bhnd_pcie_mdio_disable(struct bhnd_pci_softc *sc);
61 static int bhnd_pcie_mdio_cmd_write(struct bhnd_pci_softc *sc,
63 static int bhnd_pcie_mdio_cmd_read(struct bhnd_pci_softc *sc, uint32_t cmd,
66 static struct bhnd_device_quirk bhnd_pci_quirks[];
67 static struct bhnd_device_quirk bhnd_pcie_quirks[];
69 #define BHND_PCI_QUIRKS bhnd_pci_quirks
70 #define BHND_PCIE_QUIRKS bhnd_pcie_quirks
71 #define BHND_PCI_DEV(_core, _desc, ...) \
72 { BHND_DEVICE(BCM, _core, _desc, BHND_ ## _core ## _QUIRKS, \
73 ## __VA_ARGS__), BHND_PCI_REGFMT_ ## _core }
75 static const struct bhnd_pci_device {
76 struct bhnd_device device;
77 bhnd_pci_regfmt_t regfmt; /**< register format */
79 BHND_PCI_DEV(PCI, "Host-PCI bridge", BHND_DF_HOSTB),
80 BHND_PCI_DEV(PCI, "PCI-BHND bridge", BHND_DF_SOC),
81 BHND_PCI_DEV(PCIE, "PCIe-G1 Host-PCI bridge", BHND_DF_HOSTB),
82 BHND_PCI_DEV(PCIE, "PCIe-G1 PCI-BHND bridge", BHND_DF_SOC),
84 { BHND_DEVICE_END, 0 }
87 /* Device quirks tables */
88 static struct bhnd_device_quirk bhnd_pci_quirks[] = { BHND_DEVICE_QUIRK_END };
89 static struct bhnd_device_quirk bhnd_pcie_quirks[] = {
90 BHND_CORE_QUIRK(HWREV_GTE(10), BHND_PCI_QUIRK_SD_C22_EXTADDR),
95 #define BHND_PCIE_MDIO_CTL_DELAY 10 /**< usec delay required between
96 * MDIO_CTL/MDIO_DATA accesses. */
97 #define BHND_PCIE_MDIO_RETRY_DELAY 2000 /**< usec delay before retrying
98 * BHND_PCIE_MDIOCTL_DONE. */
99 #define BHND_PCIE_MDIO_RETRY_COUNT 200 /**< number of times to loop waiting
100 * for BHND_PCIE_MDIOCTL_DONE. */
102 #define BHND_PCI_READ_4(_sc, _reg) \
103 bhnd_bus_read_4((_sc)->mem_res, (_reg))
104 #define BHND_PCI_WRITE_4(_sc, _reg, _val) \
105 bhnd_bus_write_4((_sc)->mem_res, (_reg), (_val))
107 #define BHND_PCIE_ASSERT(sc) \
108 KASSERT(bhnd_get_class(sc->dev) == BHND_DEVCLASS_PCIE, \
109 ("not a pcie device!"));
112 bhnd_pci_generic_probe(device_t dev)
114 const struct bhnd_device *id;
116 id = bhnd_device_lookup(dev, &bhnd_pci_devs[0].device,
117 sizeof(bhnd_pci_devs[0]));
121 bhnd_set_custom_core_desc(dev, id->desc);
122 return (BUS_PROBE_DEFAULT);
126 bhnd_pci_generic_attach(device_t dev)
128 struct bhnd_pci_softc *sc;
131 sc = device_get_softc(dev);
133 sc->quirks = bhnd_device_quirks(dev, &bhnd_pci_devs[0].device,
134 sizeof(bhnd_pci_devs[0]));
136 /* Allocate bus resources */
137 sc->mem_res = bhnd_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
139 if (sc->mem_res == NULL)
142 BHND_PCI_LOCK_INIT(sc);
144 /* Probe and attach children */
145 if ((error = bus_generic_attach(dev)))
151 bhnd_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res);
152 BHND_PCI_LOCK_DESTROY(sc);
158 bhnd_pci_generic_detach(device_t dev)
160 struct bhnd_pci_softc *sc;
163 sc = device_get_softc(dev);
165 if ((error = bus_generic_detach(dev)))
168 bhnd_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res);
170 BHND_PCI_LOCK_DESTROY(sc);
175 static struct resource_list *
176 bhnd_pci_get_resource_list(device_t dev, device_t child)
178 struct bhnd_pci_devinfo *dinfo;
180 if (device_get_parent(child) != dev)
183 dinfo = device_get_ivars(child);
184 return (&dinfo->resources);
188 bhnd_pci_add_child(device_t dev, u_int order, const char *name, int unit)
190 struct bhnd_pci_devinfo *dinfo;
193 child = device_add_child_ordered(dev, order, name, unit);
197 dinfo = malloc(sizeof(struct bhnd_pci_devinfo), M_DEVBUF, M_NOWAIT);
199 device_delete_child(dev, child);
203 resource_list_init(&dinfo->resources);
205 device_set_ivars(child, dinfo);
210 bhnd_pci_child_deleted(device_t dev, device_t child)
212 struct bhnd_pci_devinfo *dinfo;
214 if (device_get_parent(child) != dev)
217 dinfo = device_get_ivars(child);
219 resource_list_free(&dinfo->resources);
220 free(dinfo, M_DEVBUF);
223 device_set_ivars(child, NULL);
227 bhnd_pci_generic_suspend(device_t dev)
229 return (bus_generic_suspend(dev));
233 bhnd_pci_generic_resume(device_t dev)
235 return (bus_generic_resume(dev));
239 * Read a 32-bit PCIe TLP/DLLP/PLP protocol register.
241 * @param sc The bhndb_pci driver state.
242 * @param addr The protocol register offset.
245 bhnd_pcie_read_proto_reg(struct bhnd_pci_softc *sc, uint32_t addr)
249 BHND_PCIE_ASSERT(sc);
252 BHND_PCI_WRITE_4(sc, BHND_PCIE_IND_ADDR, addr);
253 val = BHND_PCI_READ_4(sc, BHND_PCIE_IND_DATA);
260 * Write a 32-bit PCIe TLP/DLLP/PLP protocol register value.
262 * @param sc The bhndb_pci driver state.
263 * @param addr The protocol register offset.
264 * @param val The value to write to @p addr.
267 bhnd_pcie_write_proto_reg(struct bhnd_pci_softc *sc, uint32_t addr,
270 BHND_PCIE_ASSERT(sc);
273 BHND_PCI_WRITE_4(sc, BHND_PCIE_IND_ADDR, addr);
274 BHND_PCI_WRITE_4(sc, BHND_PCIE_IND_DATA, val);
278 /* Spin until the MDIO device reports itself as idle, or timeout is reached. */
280 bhnd_pcie_mdio_wait_idle(struct bhnd_pci_softc *sc)
284 /* Spin waiting for the BUSY flag to clear */
285 for (int i = 0; i < BHND_PCIE_MDIO_RETRY_COUNT; i++) {
286 ctl = BHND_PCI_READ_4(sc, BHND_PCIE_MDIO_CTL);
287 if ((ctl & BHND_PCIE_MDIOCTL_DONE))
290 DELAY(BHND_PCIE_MDIO_RETRY_DELAY);
298 * Write an MDIO IOCTL and wait for completion.
301 bhnd_pcie_mdio_ioctl(struct bhnd_pci_softc *sc, uint32_t cmd)
303 BHND_PCI_LOCK_ASSERT(sc, MA_OWNED);
305 BHND_PCI_WRITE_4(sc, BHND_PCIE_MDIO_CTL, cmd);
306 DELAY(BHND_PCIE_MDIO_CTL_DELAY);
314 bhnd_pcie_mdio_enable(struct bhnd_pci_softc *sc)
318 BHND_PCIE_ASSERT(sc);
320 /* Enable MDIO clock and preamble mode */
321 ctl = BHND_PCIE_MDIOCTL_PREAM_EN|BHND_PCIE_MDIOCTL_DIVISOR_VAL;
322 return (bhnd_pcie_mdio_ioctl(sc, ctl));
326 * Disable MDIO device.
329 bhnd_pcie_mdio_disable(struct bhnd_pci_softc *sc)
331 if (bhnd_pcie_mdio_ioctl(sc, 0))
332 device_printf(sc->dev, "failed to disable MDIO clock\n");
337 * Issue a write command and wait for completion
340 bhnd_pcie_mdio_cmd_write(struct bhnd_pci_softc *sc, uint32_t cmd)
344 BHND_PCI_LOCK_ASSERT(sc, MA_OWNED);
346 cmd |= BHND_PCIE_MDIODATA_START|BHND_PCIE_MDIODATA_TA|BHND_PCIE_MDIODATA_CMD_WRITE;
348 BHND_PCI_WRITE_4(sc, BHND_PCIE_MDIO_DATA, cmd);
349 DELAY(BHND_PCIE_MDIO_CTL_DELAY);
351 if ((error = bhnd_pcie_mdio_wait_idle(sc)))
358 * Issue an an MDIO read command, wait for completion, and return
359 * the result in @p data_read.
362 bhnd_pcie_mdio_cmd_read(struct bhnd_pci_softc *sc, uint32_t cmd,
367 BHND_PCI_LOCK_ASSERT(sc, MA_OWNED);
369 cmd |= BHND_PCIE_MDIODATA_START|BHND_PCIE_MDIODATA_TA|BHND_PCIE_MDIODATA_CMD_READ;
370 BHND_PCI_WRITE_4(sc, BHND_PCIE_MDIO_DATA, cmd);
371 DELAY(BHND_PCIE_MDIO_CTL_DELAY);
373 if ((error = bhnd_pcie_mdio_wait_idle(sc)))
376 *data_read = (BHND_PCI_READ_4(sc, BHND_PCIE_MDIO_DATA) &
377 BHND_PCIE_MDIODATA_DATA_MASK);
383 bhnd_pcie_mdio_read(struct bhnd_pci_softc *sc, int phy, int reg)
389 /* Enable MDIO access */
391 bhnd_pcie_mdio_enable(sc);
394 cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg);
395 error = bhnd_pcie_mdio_cmd_read(sc, cmd, &val);
397 /* Disable MDIO access */
398 bhnd_pcie_mdio_disable(sc);
408 bhnd_pcie_mdio_write(struct bhnd_pci_softc *sc, int phy, int reg, int val)
413 /* Enable MDIO access */
415 bhnd_pcie_mdio_enable(sc);
417 /* Issue the write */
418 cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg) | (val & BHND_PCIE_MDIODATA_DATA_MASK);
419 error = bhnd_pcie_mdio_cmd_write(sc, cmd);
421 /* Disable MDIO access */
422 bhnd_pcie_mdio_disable(sc);
429 bhnd_pcie_mdio_read_ext(struct bhnd_pci_softc *sc, int phy, int devaddr,
436 if (devaddr == MDIO_DEVADDR_NONE)
437 return (bhnd_pcie_mdio_read(sc, phy, reg));
439 /* Extended register access is only supported for the SerDes device,
440 * using the non-standard C22 extended address mechanism */
441 if (!(sc->quirks & BHND_PCI_QUIRK_SD_C22_EXTADDR) ||
442 phy != BHND_PCIE_PHYADDR_SD)
447 /* Enable MDIO access */
449 bhnd_pcie_mdio_enable(sc);
451 /* Write the block address to the address extension register */
452 cmd = BHND_PCIE_MDIODATA_ADDR(phy, BHND_PCIE_SD_ADDREXT) | devaddr;
453 if ((error = bhnd_pcie_mdio_cmd_write(sc, cmd)))
457 cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg);
458 error = bhnd_pcie_mdio_cmd_read(sc, cmd, &val);
461 bhnd_pcie_mdio_disable(sc);
471 bhnd_pcie_mdio_write_ext(struct bhnd_pci_softc *sc, int phy, int devaddr,
477 if (devaddr == MDIO_DEVADDR_NONE)
478 return (bhnd_pcie_mdio_write(sc, phy, reg, val));
480 /* Extended register access is only supported for the SerDes device,
481 * using the non-standard C22 extended address mechanism */
482 if (!(sc->quirks & BHND_PCI_QUIRK_SD_C22_EXTADDR) ||
483 phy != BHND_PCIE_PHYADDR_SD)
488 /* Enable MDIO access */
490 bhnd_pcie_mdio_enable(sc);
492 /* Write the block address to the address extension register */
493 cmd = BHND_PCIE_MDIODATA_ADDR(phy, BHND_PCIE_SD_ADDREXT) | devaddr;
494 if ((error = bhnd_pcie_mdio_cmd_write(sc, cmd)))
497 /* Issue the write */
498 cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg) |
499 (val & BHND_PCIE_MDIODATA_DATA_MASK);
500 error = bhnd_pcie_mdio_cmd_write(sc, cmd);
503 bhnd_pcie_mdio_disable(sc);
509 static device_method_t bhnd_pci_methods[] = {
510 /* Device interface */
511 DEVMETHOD(device_probe, bhnd_pci_generic_probe),
512 DEVMETHOD(device_attach, bhnd_pci_generic_attach),
513 DEVMETHOD(device_detach, bhnd_pci_generic_detach),
514 DEVMETHOD(device_suspend, bhnd_pci_generic_suspend),
515 DEVMETHOD(device_resume, bhnd_pci_generic_resume),
518 DEVMETHOD(bus_add_child, bhnd_pci_add_child),
519 DEVMETHOD(bus_child_deleted, bhnd_pci_child_deleted),
520 DEVMETHOD(bus_print_child, bus_generic_print_child),
521 DEVMETHOD(bus_get_resource_list, bhnd_pci_get_resource_list),
522 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
523 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
524 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource),
526 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource),
527 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
528 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
529 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
530 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
535 DEFINE_CLASS_0(bhnd_pci, bhnd_pci_driver, bhnd_pci_methods, sizeof(struct bhnd_pci_softc));
536 MODULE_DEPEND(bhnd_pci, bhnd, 1, 1, 1);
537 MODULE_DEPEND(bhnd_pci, pci, 1, 1, 1);
538 MODULE_VERSION(bhnd_pci, 1);