2 # Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
3 # Copyright (C) 2008-2015, Broadcom Corporation.
6 # The contents of this file (variable names, descriptions, and offsets) were
7 # extracted or derived from Broadcom's ISC-licensed sources.
9 # Permission to use, copy, modify, and/or distribute this software for any
10 # purpose with or without fee is hereby granted, provided that the above
11 # copyright notice and this permission notice appear in all copies.
13 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
16 # SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
18 # OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
19 # CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
24 # NVRAM variable definitions and revision-specific SPROM offsets.
26 # Processed by nvram_map_gen.awk to produce bhnd_nvram_map.h
28 # NOTE: file was originally generated automatically by using libclang
29 # to analyze and extract format information and descriptions from Broadcom's
30 # available ISC-licensed CIS and SROM code and associated headers.
36 u16 boardvendor {} # PCI vendor ID (SoC NVRAM-only)
37 u16 subvid { srom >= 2 0x6 } # PCI subvendor ID
38 u16 devid { srom >= 8 0x60 } # PCI device ID
42 srom 2 u16 0x72 | u16 0x38 (<<16)
43 srom 3 u16 0x72 | u16 0x7A (<<16)
57 # Board serial number, independent of mac addr
91 # PMU min resource mask (embedded-only).
96 # PMU min resource max (embedded-only).
104 srom 1-3 0x5C (&0x30, >>4)
110 srom 1-3 0x5C (&0xC0, >>6)
116 # ACPHY PA trimming parameters: 40
121 # ACPHY PA trimming parameters: 80
126 # ACPHY PA trimming parameters: 40/80
127 u16[12] pa5gbw4080a0 {
130 u16[12] pa5gbw4080a1 {
131 srom >= 11 u16 0xB6, u16 0xBC, u16 0xCE, u16 0xD4, u16[8] 0x128
134 # ACPHY PA trimming parameters: CCK
139 # ACPHY Power-per-rate 2gpo
140 u16 dot11agofdmhrbw202gpo {
147 # ACPHY Power-per-rate 5gpo
158 srom >= 11 0x190 (&0xFFF)
167 # ACPHY Power-per-rate sbpo
171 u16 sb20in80and160hr5glpo {
174 u16 sb40and80hr5glpo {
177 u16 sb20in80and160hr5gmpo {
180 u16 sb40and80hr5gmpo {
183 u16 sb20in80and160hr5ghpo {
186 u16 sb40and80hr5ghpo {
192 u16 sb20in80and160lr5glpo {
195 u16 sb40and80lr5glpo {
198 u16 sb20in80and160lr5gmpo {
201 u16 sb40and80lr5gmpo {
204 u16 sb20in80and160lr5ghpo {
207 u16 sb40and80lr5ghpo {
256 # Default country code (sromrev == 1)
262 # CCK Power offsets for 20 MHz rates (11, 5.5, 2, 1Mbps)
263 # cckbw202gpo cckbw20ul2gpo
274 # Country code (2 bytes ascii + 1 byte cctl)
286 # 2 byte; txchain, rxchain
290 srom 8-10 0xA3 (&0xF)
291 srom >= 11 0xA9 (&0xF)
295 srom 4-7 0x7B (&0xF0, >>4)
296 srom 8-10 0xA3 (&0xF0, >>4)
297 srom >= 11 0xA9 (&0xF0, >>4)
314 # 11n front-end specification
316 srom 8-10 0xAE (&0xF8, >>3)
319 srom 8-10 0xAE (&0x7)
322 srom 8-10 0xAF (&0xF8, >>3)
325 srom 8-10 0xAF (&0x6, >>1)
328 srom 8-10 0xAF (&0x1)
331 srom 8-10 0xB0 (&0xF8, >>3)
334 srom 8-10 0xB0 (&0x7)
337 srom 8-10 0xB1 (&0xF8, >>3)
340 srom 8-10 0xB1 (&0x6, >>1)
343 srom 8-10 0xB1 (&0x1)
349 srom >= 11 0xAA (&0xF8, >>3)
353 srom >= 11 0xAA (&0x4, >>2)
357 srom >= 11 0xAA (&0x2, >>1)
361 srom >= 11 u16 0xAA (&0x1F0, >>4)
365 srom >= 11 0xAB (&0xE, >>1)
369 srom >= 11 0xAB (&0x1)
373 srom >= 11 0xAC (&0xF8, >>3)
377 srom >= 11 0xAC (&0x4, >>2)
381 srom >= 11 0xAC (&0x2, >>1)
385 srom >= 11 u16 0xAC (&0x1F0, >>4)
389 srom >= 11 0xAD (&0xE, >>1)
393 srom >= 11 0xAD (&0x1)
442 # Additional power offset for Legacy Dup40 transmissions.
443 # Applied in addition to legofdmbw20ulXpo, X=2g, 5gl, 5gm, or 5gh.
444 # LSB nibble: 2G band, MSB nibble: 5G band high subband.
445 # leg40dup5ghpo, leg40dup5gmpo, leg40dup5glpo, leg40dup2gpo
452 # OFDM power offsets for 20 MHz Legacy rates
453 # (54, 48, 36, 24, 18, 12, 9, 6 Mbps)
454 # legofdmbw202gpo legofdmbw20ul2gpo
456 u32 legofdmbw202gpo {
459 u32 legofdmbw20ul2gpo {
464 # 5G band: OFDM power offsets for 20 MHz Legacy rates
465 # (54, 48, 36, 24, 18, 12, 9, 6 Mbps)
466 # low subband : legofdmbw205glpo legofdmbw20ul2glpo
467 # mid subband :legofdmbw205gmpo legofdmbw20ul2gmpo
468 # high subband :legofdmbw205ghpo legofdmbw20ul2ghpo
470 u32 legofdmbw205glpo {
473 u32 legofdmbw20ul5glpo {
476 u32 legofdmbw205gmpo {
479 u32 legofdmbw20ul5gmpo {
482 u32 legofdmbw205ghpo {
485 u32 legofdmbw20ul5ghpo {
489 # mac addr override for the standard CIS LAN_NID
492 srom 3 u8 0x4B, u8 0x4A, u8 0x4D, u8 0x4C, u8 0x4F, u8 0x4E
493 srom 4 u8 0x4D, u8 0x4C, u8 0x4F, u8 0x4E, u8 0x51, u8 0x50
494 srom 5-7 u8 0x53, u8 0x52, u8 0x55, u8 0x54, u8 0x57, u8 0x56
495 srom 8-10 u8 0x8D, u8 0x8C, u8 0x8F, u8 0x8E, u8 0x91, u8 0x90
496 srom >= 11 u8 0x91, u8 0x90, u8 0x93, u8 0x92, u8 0x95, u8 0x94
500 # mcs 0-7 power-offset. LSB nibble: m0, MSB nibble: m7
501 # mcsbw202gpo mcsbw20ul2gpo mcsbw402gpo
516 # 5G high subband mcs 0-7 power-offset.
517 # LSB nibble: m0, MSB nibble: m7
518 # mcsbw205ghpo mcsbw20ul5ghpo mcsbw405ghpo
533 # 5G low subband mcs 0-7 power-offset.
534 # LSB nibble: m0, MSB nibble: m7
535 # mcsbw205glpo mcsbw20ul5glpo mcsbw405glpo
550 # 5G mid subband mcs 0-7 power-offset.
551 # LSB nibble: m0, MSB nibble: m7
552 # mcsbw205gmpo mcsbw20ul5gmpo mcsbw405gmpo
567 # mcs-32 power offset for each band/subband.
568 # LSB nibble: 2G band, MSB nibble:
569 # mcs322ghpo, mcs325gmpo, mcs325glpo, mcs322gpo
576 srom 8-10 0xB4 (&0xFE, >>1)
577 srom >= 11 0xB0 (&0xFE, >>1)
580 srom 8-10 0xBF (&0x7F)
581 srom >= 11 0xBB (&0x7F)
584 srom 8-10 u16 0xBE (&0x3F80, >>7)
585 srom >= 11 u16 0xBA (&0x3F80, >>7)
588 srom 8-10 0xB4 (&0x1FF)
589 srom >= 11 0xB0 (&0x1FF)
594 srom 8-10 0x1AB (&0x1F)
595 srom >= 11 0x1BD (&0x1F)
599 srom 8-10 u16 0x1AA (&0x3E0, >>5)
600 srom >= 11 u16 0x1BC (&0x3E0, >>5)
604 srom 8-10 0x1AA (&0x7C, >>2)
605 srom >= 11 0x1BC (&0x7C, >>2)
609 srom >= 11 u8 0x1BF (&0x1F), u8 0x1C1 (&0x1F), u8 0x1C3 (&0x1F), u8 0x1C5 (&0x1F)
613 srom >= 11 u16[4] 0x1BE (&0x3E0, >>5)
617 srom >= 11 u8 0x1BE (&0x7C, >>2), u8 0x1C0 (&0x7C, >>2), u8 0x1C2 (&0x7C, >>2), u8 0x1C4 (&0x7C, >>2)
623 srom >= 11 0x190 (&0xF0, >>4)
626 # PA parameters: 8 (sromrev == 1)
627 # or 9 (sromrev > 1) bytes
746 srom >= 11 0xC9 (&0xF)
749 srom >= 11 0xC9 (&0xF0, >>4)
752 srom >= 11 0xC8 (&0xF)
754 u8 pdoffset2g40mvalid {
755 srom >= 11 0xC8 (&0x80, >>7)
758 # 40Mhz channel 2g/5g power offset
764 # 40Mhz channel dup 2g/5g power offset
770 # cck2g/ofdm2g/ofdm5g power offset
792 # cdd2g/5g power offset
832 # mcs5g low-high band power offset
898 # mcs5g mid band power offset
932 # stbc2g/5g power offset
946 # 4328 2G RSSI mid pt sel & board switch arch,
951 srom 8-10 0xA5 (&0xF)
954 srom 3 0x51 (&0xF0, >>4)
955 srom 8-10 0xA5 (&0xF0, >>4)
959 srom 8-10 0xA4 (&0x7)
962 srom 3 0x50 (&0x18, >>3)
963 srom 8-10 0xA4 (&0x18, >>3)
966 # 4328 5G RSSI mid pt sel & board switch arch,
971 srom 8-10 0xA7 (&0xF)
974 srom 3 0x53 (&0xF0, >>4)
975 srom 8-10 0xA7 (&0xF0, >>4)
979 srom 8-10 0xA6 (&0x7)
982 srom 3 0x52 (&0x18, >>3)
983 srom 8-10 0xA6 (&0x18, >>3)
987 srom 8-10 0x19B (&0x3F)
988 srom >= 11 0x1C7 (&0x3F)
991 srom 8-10 u16 0x19A (&0x7C0, >>6)
992 srom >= 11 u16 0x1C6 (&0x7C0, >>6)
995 srom 8-10 0x19A (&0xF8, >>3)
996 srom >= 11 0x1C6 (&0xF8, >>3)
998 u8[4] rxgainerr5ga0 {
999 srom >= 11 u8 0x1C9 (&0x3F), u8 0x1CB (&0x3F), u8 0x1CD (&0x3F), u8 0x1CF (&0x3F)
1001 u8[4] rxgainerr5ga1 {
1002 srom >= 11 u16[4] 0x1C8 (&0x7C0, >>6)
1004 u8[4] rxgainerr5ga2 {
1005 srom >= 11 u8 0x1C8 (&0xF8, >>3), u8 0x1CA (&0xF8, >>3), u8 0x1CC (&0xF8, >>3), u8 0x1CE (&0xF8, >>3)
1008 srom 8-10 0x1A1 (&0x3F)
1011 srom 8-10 u16 0x1A0 (&0x7C0, >>6)
1014 srom 8-10 0x1A0 (&0xF8, >>3)
1017 srom 8-10 0x19D (&0x3F)
1020 srom 8-10 u16 0x19C (&0x7C0, >>6)
1023 srom 8-10 0x19C (&0xF8, >>3)
1026 srom 8-10 0x19F (&0x3F)
1029 srom 8-10 u16 0x19E (&0x7C0, >>6)
1032 srom 8-10 0x19E (&0xF8, >>3)
1035 srom 8-10 0x1A3 (&0x3F)
1038 srom 8-10 u16 0x1A2 (&0x7C0, >>6)
1041 srom 8-10 0x1A2 (&0xF8, >>3)
1044 # 4328 2G RX power offset
1051 # 4328 5G RX power offset
1059 srom 8-10 u8 0x1A5 (&0x7)
1065 # byte2 period(msb 4 bits) | hysterisis(lsb 4 bits)
1073 srom 8-10 0xBC (&0xF)
1074 srom >= 11 0xB8 (&0xF)
1076 u8 temps_hysteresis {
1078 srom 8-10 0xBC (&0xF0, >>4)
1079 srom >= 11 0xB8 (&0xF0, >>4)
1086 u8 tempsense_slope {
1091 srom 8-10 0xB6 (&0xFC, >>2)
1092 srom >= 11 0xB2 (&0xFC, >>2)
1094 u8 tempsense_option {
1095 srom 8-10 0xB6 (&0x3)
1096 srom >= 11 0xB2 (&0x3)
1098 u8 phycal_tempdelta {
1104 # 4328 2G TR isolation, 1 byte
1110 # 4328 5G TR isolation, 3 bytes
1124 # phy txbf rpcalvars
1141 # Crystal frequency in kilohertz
1147 # N-PHY tx power workaround
1202 srom 0-2 u8 0x55, u8 0x54, u8 0x57, u8 0x56, u8 0x59, u8 0x58
1216 u8 freqoffset_corr {
1217 srom 8-10 0xB9 (&0xF)
1220 srom 8-10 0xB9 (&0x20, >>5)
1224 srom 0-2 u8 0x49, u8 0x48, u8 0x51, u8 0x50, u8 0x53, u8 0x52
1227 srom 8-10 0xB9 (&0x10, >>4)
1233 u8 noisecaloffset5g {
1237 srom 8-10 0x1B1 (&0x1F)
1240 srom 8-10 u16 0x1B0 (&0x3E0, >>5)
1243 srom 8-10 0x1B0 (&0x7C, >>2)
1246 srom 8-10 0x1AD (&0x1F)
1249 srom 8-10 u16 0x1AC (&0x3E0, >>5)
1252 srom 8-10 0x1AC (&0x7C, >>2)
1255 srom 8-10 0x1AF (&0x1F)
1258 srom 8-10 u16 0x1AE (&0x3E0, >>5)
1261 srom 8-10 0x1AE (&0x7C, >>2)
1264 srom 8-10 0x1B3 (&0x1F)
1267 srom 8-10 u16 0x1B2 (&0x3E0, >>5)
1270 srom 8-10 0x1B2 (&0x7C, >>2)
1273 u8 pcieingress_war {
1274 srom 8-10 0x1A7 (&0xF)
1278 srom >= 11 0x18F (&0xF)
1281 srom >= 11 0x18F (&0xF0, >>4)
1284 srom >= 11 0x18E (&0xF)
1296 u32[5] swctrlmap_2g {
1297 srom 10 u32[4] 0x1B8, u16 0x1C8
1301 srom >= 11 0xBE (&0x3FF)
1303 u16[4] tssifloor5g {
1304 srom >= 11 0xC0 (&0x3FF)
1308 srom >= 11 u16 0x1A8 (&0xFF0, >>4)
1311 srom >= 11 u16 0x1AC (&0xFF0, >>4)
1315 # Any variables defined within a `struct` block will be interpreted relative to
1316 # the provided array of SPROM base addresses; this is used to define
1317 # a common layout defined at the given base addresses.
1319 # To produce SPROM variable names matching those used in the Broadcom HND
1320 # ASCII 'key=value\0' NVRAM, the index number of the variable's
1321 # struct instance will be appended (e.g., given a variable of noiselvl5ga, the
1322 # generated variable instances will be named noiselvl5ga0, noiselvl5ga1,
1323 # noiselvl5ga2, noiselvl5ga3 ...)
1326 # PHY chain[0-4] parameters
1327 struct phy_chains[] {
1328 srom 4-7 [0x080, 0x0AE, 0x0DC, 0x10A]
1329 srom 8-10 [0x0C0, 0x0E0, 0x100, 0x120]
1330 srom >= 11 [0x0D8, 0x100, 0x128]
1332 # AC-PHY PA parameters
1336 srom >= 11 u8 0xD, u8 0xC, u8 0xF, u8 0xE
1351 u8 rxgains5ghtrelnabypa {
1352 srom >= 11 0x8 (&0x80, >>7)
1354 u8 rxgains5ghelnagaina {
1355 srom >= 11 0x8 (&0x7)
1357 u8 rxgains5gelnagaina {
1358 srom >= 11 0xA (&0x7)
1360 u8 rxgains5gmtrelnabypa {
1361 srom >= 11 0x9 (&0x80, >>7)
1363 u8 rxgains2gtrelnabypa {
1364 srom >= 11 0xB (&0x80, >>7)
1366 u8 rxgains5gmtrisoa {
1367 srom >= 11 0x9 (&0x78, >>3)
1369 u8 rxgains5gmelnagaina {
1370 srom >= 11 0x9 (&0x7)
1372 u8 rxgains2gelnagaina {
1373 srom >= 11 0xB (&0x7)
1375 u8 rxgains5gtrisoa {
1376 srom >= 11 0xA (&0x78, >>3)
1378 u8 rxgains5gtrelnabypa {
1379 srom >= 11 0xA (&0x80, >>7)
1381 u8 rxgains2gtrisoa {
1382 srom >= 11 0xB (&0x78, >>3)
1384 u8 rxgains5ghtrisoa {
1385 srom >= 11 0x8 (&0x78, >>3)