2 # Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
3 # Copyright (C) 2008-2015, Broadcom Corporation.
6 # The contents of this file (variable names, descriptions, and offsets) were
7 # extracted or derived from Broadcom's ISC-licensed sources.
9 # Permission to use, copy, modify, and/or distribute this software for any
10 # purpose with or without fee is hereby granted, provided that the above
11 # copyright notice and this permission notice appear in all copies.
13 # THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 # WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 # MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
16 # SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
18 # OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
19 # CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
24 # NVRAM variable definitions and revision-specific SPROM offsets.
26 # Processed by nvram_map_gen.awk to produce bhnd_nvram_map.h
28 # NOTE: file was originally generated automatically by using libclang
29 # to analyze and extract format information and descriptions from Broadcom's
30 # available ISC-licensed CIS and SROM code and associated headers.
36 u16 boardvendor {} # PCI vendor ID (SoC NVRAM-only)
37 u16 subvid { srom >= 2 0x6 } # PCI subvendor ID
38 u16 devid { srom >= 8 0x60 } # PCI device ID
42 srom 2 u16 0x72 | u16 0x38 (<<16)
43 srom 3 u16 0x72 | u16 0x7A (<<16)
57 # Board serial number, independent of mac addr
89 srom 1-3 0x5C (&0x30, >>4)
95 srom 1-3 0x5C (&0xC0, >>6)
101 # ACPHY PA trimming parameters: 40
106 # ACPHY PA trimming parameters: 80
111 # ACPHY PA trimming parameters: 40/80
112 u16[12] pa5gbw4080a0 {
115 u16[12] pa5gbw4080a1 {
116 srom >= 11 u16 0xB6, u16 0xBC, u16 0xCE, u16 0xD4, u16[8] 0x128
119 # ACPHY PA trimming parameters: CCK
124 # ACPHY Power-per-rate 2gpo
125 u16 dot11agofdmhrbw202gpo {
132 # ACPHY Power-per-rate 5gpo
143 srom >= 11 0x190 (&0xFFF)
152 # ACPHY Power-per-rate sbpo
156 u16 sb20in80and160hr5glpo {
159 u16 sb40and80hr5glpo {
162 u16 sb20in80and160hr5gmpo {
165 u16 sb40and80hr5gmpo {
168 u16 sb20in80and160hr5ghpo {
171 u16 sb40and80hr5ghpo {
177 u16 sb20in80and160lr5glpo {
180 u16 sb40and80lr5glpo {
183 u16 sb20in80and160lr5gmpo {
186 u16 sb40and80lr5gmpo {
189 u16 sb20in80and160lr5ghpo {
192 u16 sb40and80lr5ghpo {
241 # Default country code (sromrev == 1)
247 # CCK Power offsets for 20 MHz rates (11, 5.5, 2, 1Mbps)
248 # cckbw202gpo cckbw20ul2gpo
259 # Country code (2 bytes ascii + 1 byte cctl)
271 # 2 byte; txchain, rxchain
275 srom 8-10 0xA3 (&0xF)
276 srom >= 11 0xA9 (&0xF)
280 srom 4-7 0x7B (&0xF0, >>4)
281 srom 8-10 0xA3 (&0xF0, >>4)
282 srom >= 11 0xA9 (&0xF0, >>4)
299 # 11n front-end specification
301 srom 8-10 0xAE (&0xF8, >>3)
304 srom 8-10 0xAE (&0x7)
307 srom 8-10 0xAF (&0xF8, >>3)
310 srom 8-10 0xAF (&0x6, >>1)
313 srom 8-10 0xAF (&0x1)
316 srom 8-10 0xB0 (&0xF8, >>3)
319 srom 8-10 0xB0 (&0x7)
322 srom 8-10 0xB1 (&0xF8, >>3)
325 srom 8-10 0xB1 (&0x6, >>1)
328 srom 8-10 0xB1 (&0x1)
334 srom >= 11 0xAA (&0xF8, >>3)
338 srom >= 11 0xAA (&0x4, >>2)
342 srom >= 11 0xAA (&0x2, >>1)
346 srom >= 11 u16 0xAA (&0x1F0, >>4)
350 srom >= 11 0xAB (&0xE, >>1)
354 srom >= 11 0xAB (&0x1)
358 srom >= 11 0xAC (&0xF8, >>3)
362 srom >= 11 0xAC (&0x4, >>2)
366 srom >= 11 0xAC (&0x2, >>1)
370 srom >= 11 u16 0xAC (&0x1F0, >>4)
374 srom >= 11 0xAD (&0xE, >>1)
378 srom >= 11 0xAD (&0x1)
427 # Additional power offset for Legacy Dup40 transmissions.
428 # Applied in addition to legofdmbw20ulXpo, X=2g, 5gl, 5gm, or 5gh.
429 # LSB nibble: 2G band, MSB nibble: 5G band high subband.
430 # leg40dup5ghpo, leg40dup5gmpo, leg40dup5glpo, leg40dup2gpo
437 # OFDM power offsets for 20 MHz Legacy rates
438 # (54, 48, 36, 24, 18, 12, 9, 6 Mbps)
439 # legofdmbw202gpo legofdmbw20ul2gpo
441 u32 legofdmbw202gpo {
444 u32 legofdmbw20ul2gpo {
449 # 5G band: OFDM power offsets for 20 MHz Legacy rates
450 # (54, 48, 36, 24, 18, 12, 9, 6 Mbps)
451 # low subband : legofdmbw205glpo legofdmbw20ul2glpo
452 # mid subband :legofdmbw205gmpo legofdmbw20ul2gmpo
453 # high subband :legofdmbw205ghpo legofdmbw20ul2ghpo
455 u32 legofdmbw205glpo {
458 u32 legofdmbw20ul5glpo {
461 u32 legofdmbw205gmpo {
464 u32 legofdmbw20ul5gmpo {
467 u32 legofdmbw205ghpo {
470 u32 legofdmbw20ul5ghpo {
474 # mac addr override for the standard CIS LAN_NID
477 srom 3 u8 0x4B, u8 0x4A, u8 0x4D, u8 0x4C, u8 0x4F, u8 0x4E
478 srom 4 u8 0x4D, u8 0x4C, u8 0x4F, u8 0x4E, u8 0x51, u8 0x50
479 srom 5-7 u8 0x53, u8 0x52, u8 0x55, u8 0x54, u8 0x57, u8 0x56
480 srom 8-10 u8 0x8D, u8 0x8C, u8 0x8F, u8 0x8E, u8 0x91, u8 0x90
481 srom >= 11 u8 0x91, u8 0x90, u8 0x93, u8 0x92, u8 0x95, u8 0x94
485 # mcs 0-7 power-offset. LSB nibble: m0, MSB nibble: m7
486 # mcsbw202gpo mcsbw20ul2gpo mcsbw402gpo
501 # 5G high subband mcs 0-7 power-offset.
502 # LSB nibble: m0, MSB nibble: m7
503 # mcsbw205ghpo mcsbw20ul5ghpo mcsbw405ghpo
518 # 5G low subband mcs 0-7 power-offset.
519 # LSB nibble: m0, MSB nibble: m7
520 # mcsbw205glpo mcsbw20ul5glpo mcsbw405glpo
535 # 5G mid subband mcs 0-7 power-offset.
536 # LSB nibble: m0, MSB nibble: m7
537 # mcsbw205gmpo mcsbw20ul5gmpo mcsbw405gmpo
552 # mcs-32 power offset for each band/subband.
553 # LSB nibble: 2G band, MSB nibble:
554 # mcs322ghpo, mcs325gmpo, mcs325glpo, mcs322gpo
561 srom 8-10 0xB4 (&0xFE, >>1)
562 srom >= 11 0xB0 (&0xFE, >>1)
565 srom 8-10 0xBF (&0x7F)
566 srom >= 11 0xBB (&0x7F)
569 srom 8-10 u16 0xBE (&0x3F80, >>7)
570 srom >= 11 u16 0xBA (&0x3F80, >>7)
573 srom 8-10 0xB4 (&0x1FF)
574 srom >= 11 0xB0 (&0x1FF)
579 srom 8-10 0x1AB (&0x1F)
580 srom >= 11 0x1BD (&0x1F)
584 srom 8-10 u16 0x1AA (&0x3E0, >>5)
585 srom >= 11 u16 0x1BC (&0x3E0, >>5)
589 srom 8-10 0x1AA (&0x7C, >>2)
590 srom >= 11 0x1BC (&0x7C, >>2)
594 srom >= 11 u8 0x1BF (&0x1F), u8 0x1C1 (&0x1F), u8 0x1C3 (&0x1F), u8 0x1C5 (&0x1F)
598 srom >= 11 u16[4] 0x1BE (&0x3E0, >>5)
602 srom >= 11 u8 0x1BE (&0x7C, >>2), u8 0x1C0 (&0x7C, >>2), u8 0x1C2 (&0x7C, >>2), u8 0x1C4 (&0x7C, >>2)
608 srom >= 11 0x190 (&0xF0, >>4)
611 # PA parameters: 8 (sromrev == 1)
612 # or 9 (sromrev > 1) bytes
731 srom >= 11 0xC9 (&0xF)
734 srom >= 11 0xC9 (&0xF0, >>4)
737 srom >= 11 0xC8 (&0xF)
739 u8 pdoffset2g40mvalid {
740 srom >= 11 0xC8 (&0x80, >>7)
743 # 40Mhz channel 2g/5g power offset
749 # 40Mhz channel dup 2g/5g power offset
755 # cck2g/ofdm2g/ofdm5g power offset
777 # cdd2g/5g power offset
817 # mcs5g low-high band power offset
883 # mcs5g mid band power offset
917 # stbc2g/5g power offset
931 # 4328 2G RSSI mid pt sel & board switch arch,
936 srom 8-10 0xA5 (&0xF)
939 srom 3 0x51 (&0xF0, >>4)
940 srom 8-10 0xA5 (&0xF0, >>4)
944 srom 8-10 0xA4 (&0x7)
947 srom 3 0x50 (&0x18, >>3)
948 srom 8-10 0xA4 (&0x18, >>3)
951 # 4328 5G RSSI mid pt sel & board switch arch,
956 srom 8-10 0xA7 (&0xF)
959 srom 3 0x53 (&0xF0, >>4)
960 srom 8-10 0xA7 (&0xF0, >>4)
964 srom 8-10 0xA6 (&0x7)
967 srom 3 0x52 (&0x18, >>3)
968 srom 8-10 0xA6 (&0x18, >>3)
972 srom 8-10 0x19B (&0x3F)
973 srom >= 11 0x1C7 (&0x3F)
976 srom 8-10 u16 0x19A (&0x7C0, >>6)
977 srom >= 11 u16 0x1C6 (&0x7C0, >>6)
980 srom 8-10 0x19A (&0xF8, >>3)
981 srom >= 11 0x1C6 (&0xF8, >>3)
983 u8[4] rxgainerr5ga0 {
984 srom >= 11 u8 0x1C9 (&0x3F), u8 0x1CB (&0x3F), u8 0x1CD (&0x3F), u8 0x1CF (&0x3F)
986 u8[4] rxgainerr5ga1 {
987 srom >= 11 u16[4] 0x1C8 (&0x7C0, >>6)
989 u8[4] rxgainerr5ga2 {
990 srom >= 11 u8 0x1C8 (&0xF8, >>3), u8 0x1CA (&0xF8, >>3), u8 0x1CC (&0xF8, >>3), u8 0x1CE (&0xF8, >>3)
993 srom 8-10 0x1A1 (&0x3F)
996 srom 8-10 u16 0x1A0 (&0x7C0, >>6)
999 srom 8-10 0x1A0 (&0xF8, >>3)
1002 srom 8-10 0x19D (&0x3F)
1005 srom 8-10 u16 0x19C (&0x7C0, >>6)
1008 srom 8-10 0x19C (&0xF8, >>3)
1011 srom 8-10 0x19F (&0x3F)
1014 srom 8-10 u16 0x19E (&0x7C0, >>6)
1017 srom 8-10 0x19E (&0xF8, >>3)
1020 srom 8-10 0x1A3 (&0x3F)
1023 srom 8-10 u16 0x1A2 (&0x7C0, >>6)
1026 srom 8-10 0x1A2 (&0xF8, >>3)
1029 # 4328 2G RX power offset
1036 # 4328 5G RX power offset
1044 srom 8-10 u8 0x1A5 (&0x7)
1050 # byte2 period(msb 4 bits) | hysterisis(lsb 4 bits)
1058 srom 8-10 0xBC (&0xF)
1059 srom >= 11 0xB8 (&0xF)
1061 u8 temps_hysteresis {
1063 srom 8-10 0xBC (&0xF0, >>4)
1064 srom >= 11 0xB8 (&0xF0, >>4)
1071 u8 tempsense_slope {
1076 srom 8-10 0xB6 (&0xFC, >>2)
1077 srom >= 11 0xB2 (&0xFC, >>2)
1079 u8 tempsense_option {
1080 srom 8-10 0xB6 (&0x3)
1081 srom >= 11 0xB2 (&0x3)
1083 u8 phycal_tempdelta {
1089 # 4328 2G TR isolation, 1 byte
1095 # 4328 5G TR isolation, 3 bytes
1109 # phy txbf rpcalvars
1126 # Crystal frequency in kilohertz
1132 # N-PHY tx power workaround
1187 srom 0-2 u8 0x55, u8 0x54, u8 0x57, u8 0x56, u8 0x59, u8 0x58
1201 u8 freqoffset_corr {
1202 srom 8-10 0xB9 (&0xF)
1205 srom 8-10 0xB9 (&0x20, >>5)
1209 srom 0-2 u8 0x49, u8 0x48, u8 0x51, u8 0x50, u8 0x53, u8 0x52
1212 srom 8-10 0xB9 (&0x10, >>4)
1218 u8 noisecaloffset5g {
1222 srom 8-10 0x1B1 (&0x1F)
1225 srom 8-10 u16 0x1B0 (&0x3E0, >>5)
1228 srom 8-10 0x1B0 (&0x7C, >>2)
1231 srom 8-10 0x1AD (&0x1F)
1234 srom 8-10 u16 0x1AC (&0x3E0, >>5)
1237 srom 8-10 0x1AC (&0x7C, >>2)
1240 srom 8-10 0x1AF (&0x1F)
1243 srom 8-10 u16 0x1AE (&0x3E0, >>5)
1246 srom 8-10 0x1AE (&0x7C, >>2)
1249 srom 8-10 0x1B3 (&0x1F)
1252 srom 8-10 u16 0x1B2 (&0x3E0, >>5)
1255 srom 8-10 0x1B2 (&0x7C, >>2)
1258 u8 pcieingress_war {
1259 srom 8-10 0x1A7 (&0xF)
1263 srom >= 11 0x18F (&0xF)
1266 srom >= 11 0x18F (&0xF0, >>4)
1269 srom >= 11 0x18E (&0xF)
1281 u32[5] swctrlmap_2g {
1282 srom 10 u32[4] 0x1B8, u16 0x1C8
1286 srom >= 11 0xBE (&0x3FF)
1288 u16[4] tssifloor5g {
1289 srom >= 11 0xC0 (&0x3FF)
1293 srom >= 11 u16 0x1A8 (&0xFF0, >>4)
1296 srom >= 11 u16 0x1AC (&0xFF0, >>4)
1300 # Any variables defined within a `struct` block will be interpreted relative to
1301 # the provided array of SPROM base addresses; this is used to define
1302 # a common layout defined at the given base addresses.
1304 # To produce SPROM variable names matching those used in the Broadcom HND
1305 # ASCII 'key=value\0' NVRAM, the index number of the variable's
1306 # struct instance will be appended (e.g., given a variable of noiselvl5ga, the
1307 # generated variable instances will be named noiselvl5ga0, noiselvl5ga1,
1308 # noiselvl5ga2, noiselvl5ga3 ...)
1311 # PHY chain[0-4] parameters
1312 struct phy_chains[] {
1313 srom 4-7 [0x080, 0x0AE, 0x0DC, 0x10A]
1314 srom 8-10 [0x0C0, 0x0E0, 0x100, 0x120]
1315 srom >= 11 [0x0D8, 0x100, 0x128]
1317 # AC-PHY PA parameters
1321 srom >= 11 u8 0xD, u8 0xC, u8 0xF, u8 0xE
1336 u8 rxgains5ghtrelnabypa {
1337 srom >= 11 0x8 (&0x80, >>7)
1339 u8 rxgains5ghelnagaina {
1340 srom >= 11 0x8 (&0x7)
1342 u8 rxgains5gelnagaina {
1343 srom >= 11 0xA (&0x7)
1345 u8 rxgains5gmtrelnabypa {
1346 srom >= 11 0x9 (&0x80, >>7)
1348 u8 rxgains2gtrelnabypa {
1349 srom >= 11 0xB (&0x80, >>7)
1351 u8 rxgains5gmtrisoa {
1352 srom >= 11 0x9 (&0x78, >>3)
1354 u8 rxgains5gmelnagaina {
1355 srom >= 11 0x9 (&0x7)
1357 u8 rxgains2gelnagaina {
1358 srom >= 11 0xB (&0x7)
1360 u8 rxgains5gtrisoa {
1361 srom >= 11 0xA (&0x78, >>3)
1363 u8 rxgains5gtrelnabypa {
1364 srom >= 11 0xA (&0x80, >>7)
1366 u8 rxgains2gtrisoa {
1367 srom >= 11 0xB (&0x78, >>3)
1369 u8 rxgains5ghtrisoa {
1370 srom >= 11 0x8 (&0x78, >>3)