2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
3 * Copyright (c) 2017 The FreeBSD Foundation
6 * Portions of this software were developed by Landon Fuller
7 * under sponsorship from the FreeBSD Foundation.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
16 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
17 * redistribution must be conditioned upon including a substantially
18 * similar Disclaimer requirement for further binary redistribution.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
24 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
25 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
26 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
29 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGES.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
39 #include <sys/kernel.h>
40 #include <sys/malloc.h>
41 #include <sys/module.h>
42 #include <sys/refcount.h>
43 #include <sys/systm.h>
45 #include <machine/bus.h>
47 #include <dev/bhnd/cores/chipc/chipc.h>
48 #include <dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl.h>
50 #include "siba_eromvar.h"
55 /* RID used when allocating EROM resources */
56 #define SIBA_EROM_RID 0
58 static bhnd_erom_class_t *
59 siba_get_erom_class(driver_t *driver)
61 return (&siba_erom_parser);
65 siba_probe(device_t dev)
67 device_set_desc(dev, "SIBA BHND bus");
68 return (BUS_PROBE_DEFAULT);
72 * Default siba(4) bus driver implementation of DEVICE_ATTACH().
74 * This implementation initializes internal siba(4) state and performs
75 * bus enumeration, and must be called by subclassing drivers in
76 * DEVICE_ATTACH() before any other bus methods.
79 siba_attach(device_t dev)
81 struct siba_softc *sc;
84 sc = device_get_softc(dev);
89 /* Enumerate children */
90 if ((error = siba_add_children(dev))) {
91 device_delete_children(dev);
92 SIBA_LOCK_DESTROY(sc);
100 siba_detach(device_t dev)
102 struct siba_softc *sc;
105 sc = device_get_softc(dev);
107 if ((error = bhnd_generic_detach(dev)))
110 SIBA_LOCK_DESTROY(sc);
116 siba_resume(device_t dev)
118 return (bhnd_generic_resume(dev));
122 siba_suspend(device_t dev)
124 return (bhnd_generic_suspend(dev));
128 siba_read_ivar(device_t dev, device_t child, int index, uintptr_t *result)
130 struct siba_softc *sc;
131 const struct siba_devinfo *dinfo;
132 const struct bhnd_core_info *cfg;
134 sc = device_get_softc(dev);
135 dinfo = device_get_ivars(child);
136 cfg = &dinfo->core_id.core_info;
139 case BHND_IVAR_VENDOR:
140 *result = cfg->vendor;
142 case BHND_IVAR_DEVICE:
143 *result = cfg->device;
145 case BHND_IVAR_HWREV:
146 *result = cfg->hwrev;
148 case BHND_IVAR_DEVICE_CLASS:
149 *result = bhnd_core_class(cfg);
151 case BHND_IVAR_VENDOR_NAME:
152 *result = (uintptr_t) bhnd_vendor_name(cfg->vendor);
154 case BHND_IVAR_DEVICE_NAME:
155 *result = (uintptr_t) bhnd_core_name(cfg);
157 case BHND_IVAR_CORE_INDEX:
158 *result = cfg->core_idx;
160 case BHND_IVAR_CORE_UNIT:
163 case BHND_IVAR_PMU_INFO:
165 switch (dinfo->pmu_state) {
167 *result = (uintptr_t)NULL;
172 *result = (uintptr_t)dinfo->pmu.bhnd_info;
176 case SIBA_PMU_PWRCTL:
178 *result = (uintptr_t)NULL;
183 panic("invalid PMU state: %d", dinfo->pmu_state);
192 siba_write_ivar(device_t dev, device_t child, int index, uintptr_t value)
194 struct siba_softc *sc;
195 struct siba_devinfo *dinfo;
197 sc = device_get_softc(dev);
198 dinfo = device_get_ivars(child);
201 case BHND_IVAR_VENDOR:
202 case BHND_IVAR_DEVICE:
203 case BHND_IVAR_HWREV:
204 case BHND_IVAR_DEVICE_CLASS:
205 case BHND_IVAR_VENDOR_NAME:
206 case BHND_IVAR_DEVICE_NAME:
207 case BHND_IVAR_CORE_INDEX:
208 case BHND_IVAR_CORE_UNIT:
210 case BHND_IVAR_PMU_INFO:
212 switch (dinfo->pmu_state) {
215 dinfo->pmu.bhnd_info = (void *)value;
216 dinfo->pmu_state = SIBA_PMU_BHND;
220 case SIBA_PMU_PWRCTL:
222 panic("bhnd_set_pmu_info() called with siba PMU state "
223 "%d", dinfo->pmu_state);
227 panic("invalid PMU state: %d", dinfo->pmu_state);
235 static struct resource_list *
236 siba_get_resource_list(device_t dev, device_t child)
238 struct siba_devinfo *dinfo = device_get_ivars(child);
239 return (&dinfo->resources);
242 /* BHND_BUS_ALLOC_PMU() */
244 siba_alloc_pmu(device_t dev, device_t child)
246 struct siba_softc *sc;
247 struct siba_devinfo *dinfo;
250 struct chipc_caps ccaps;
251 siba_pmu_state pmu_state;
254 if (device_get_parent(child) != dev)
257 sc = device_get_softc(dev);
258 dinfo = device_get_ivars(child);
261 /* Fetch ChipCommon capability flags */
262 chipc = bhnd_retain_provider(child, BHND_SERVICE_CHIPC);
264 ccaps = *BHND_CHIPC_GET_CAPS(chipc);
265 bhnd_release_provider(child, chipc, BHND_SERVICE_CHIPC);
267 memset(&ccaps, 0, sizeof(ccaps));
270 /* Defer to bhnd(4)'s PMU implementation if ChipCommon exists and
271 * advertises PMU support */
273 if ((error = bhnd_generic_alloc_pmu(dev, child)))
276 KASSERT(dinfo->pmu_state == SIBA_PMU_BHND,
277 ("unexpected PMU state: %d", dinfo->pmu_state));
283 * This is either a legacy PWRCTL chipset, or the device does not
284 * support dynamic clock control.
286 * We need to map all bhnd(4) bus PMU to PWRCTL or no-op operations.
288 if (ccaps.pwr_ctrl) {
289 pmu_state = SIBA_PMU_PWRCTL;
290 pwrctl = bhnd_retain_provider(child, BHND_SERVICE_PWRCTL);
291 if (pwrctl == NULL) {
292 device_printf(dev, "PWRCTL not found\n");
296 pmu_state = SIBA_PMU_FIXED;
302 /* Per-core PMU state already allocated? */
303 if (dinfo->pmu_state != SIBA_PMU_NONE) {
304 panic("duplicate PMU allocation for %s",
305 device_get_nameunit(child));
308 /* Update the child's PMU allocation state, and transfer ownership of
309 * the PWRCTL provider reference (if any) */
310 dinfo->pmu_state = pmu_state;
311 dinfo->pmu.pwrctl = pwrctl;
318 /* BHND_BUS_RELEASE_PMU() */
320 siba_release_pmu(device_t dev, device_t child)
322 struct siba_softc *sc;
323 struct siba_devinfo *dinfo;
327 if (device_get_parent(child) != dev)
330 sc = device_get_softc(dev);
331 dinfo = device_get_ivars(child);
334 switch(dinfo->pmu_state) {
336 panic("pmu over-release for %s", device_get_nameunit(child));
342 return (bhnd_generic_release_pmu(dev, child));
344 case SIBA_PMU_PWRCTL:
345 /* Requesting BHND_CLOCK_DYN releases any outstanding clock
347 pwrctl = dinfo->pmu.pwrctl;
348 error = bhnd_pwrctl_request_clock(pwrctl, child,
355 /* Clean up the child's PMU state */
356 dinfo->pmu_state = SIBA_PMU_NONE;
357 dinfo->pmu.pwrctl = NULL;
360 /* Release the provider reference */
361 bhnd_release_provider(child, pwrctl, BHND_SERVICE_PWRCTL);
365 /* Clean up the child's PMU state */
366 KASSERT(dinfo->pmu.pwrctl == NULL,
367 ("PWRCTL reference with FIXED state"));
369 dinfo->pmu_state = SIBA_PMU_NONE;
370 dinfo->pmu.pwrctl = NULL;
374 panic("invalid PMU state: %d", dinfo->pmu_state);
377 /* BHND_BUS_GET_CLOCK_LATENCY() */
379 siba_get_clock_latency(device_t dev, device_t child, bhnd_clock clock,
382 struct siba_softc *sc;
383 struct siba_devinfo *dinfo;
386 if (device_get_parent(child) != dev)
389 sc = device_get_softc(dev);
390 dinfo = device_get_ivars(child);
393 switch(dinfo->pmu_state) {
395 panic("no active PMU request state");
402 return (bhnd_generic_get_clock_latency(dev, child, clock,
405 case SIBA_PMU_PWRCTL:
406 error = bhnd_pwrctl_get_clock_latency(dinfo->pmu.pwrctl, clock,
415 /* HT clock is always available, and incurs no transition
429 panic("invalid PMU state: %d", dinfo->pmu_state);
432 /* BHND_BUS_GET_CLOCK_FREQ() */
434 siba_get_clock_freq(device_t dev, device_t child, bhnd_clock clock,
437 struct siba_softc *sc;
438 struct siba_devinfo *dinfo;
441 if (device_get_parent(child) != dev)
444 sc = device_get_softc(dev);
445 dinfo = device_get_ivars(child);
448 switch(dinfo->pmu_state) {
450 panic("no active PMU request state");
457 return (bhnd_generic_get_clock_freq(dev, child, clock, freq));
459 case SIBA_PMU_PWRCTL:
460 error = bhnd_pwrctl_get_clock_freq(dinfo->pmu.pwrctl, clock,
472 panic("invalid PMU state: %d", dinfo->pmu_state);
475 /* BHND_BUS_REQUEST_EXT_RSRC() */
477 siba_request_ext_rsrc(device_t dev, device_t child, u_int rsrc)
479 struct siba_softc *sc;
480 struct siba_devinfo *dinfo;
482 if (device_get_parent(child) != dev)
485 sc = device_get_softc(dev);
486 dinfo = device_get_ivars(child);
489 switch(dinfo->pmu_state) {
491 panic("no active PMU request state");
498 return (bhnd_generic_request_ext_rsrc(dev, child, rsrc));
500 case SIBA_PMU_PWRCTL:
502 /* HW does not support per-core external resources */
507 panic("invalid PMU state: %d", dinfo->pmu_state);
510 /* BHND_BUS_RELEASE_EXT_RSRC() */
512 siba_release_ext_rsrc(device_t dev, device_t child, u_int rsrc)
514 struct siba_softc *sc;
515 struct siba_devinfo *dinfo;
517 if (device_get_parent(child) != dev)
520 sc = device_get_softc(dev);
521 dinfo = device_get_ivars(child);
524 switch(dinfo->pmu_state) {
526 panic("no active PMU request state");
533 return (bhnd_generic_release_ext_rsrc(dev, child, rsrc));
535 case SIBA_PMU_PWRCTL:
537 /* HW does not support per-core external resources */
542 panic("invalid PMU state: %d", dinfo->pmu_state);
545 /* BHND_BUS_REQUEST_CLOCK() */
547 siba_request_clock(device_t dev, device_t child, bhnd_clock clock)
549 struct siba_softc *sc;
550 struct siba_devinfo *dinfo;
553 if (device_get_parent(child) != dev)
556 sc = device_get_softc(dev);
557 dinfo = device_get_ivars(child);
560 switch(dinfo->pmu_state) {
562 panic("no active PMU request state");
569 return (bhnd_generic_request_clock(dev, child, clock));
571 case SIBA_PMU_PWRCTL:
572 error = bhnd_pwrctl_request_clock(dinfo->pmu.pwrctl, child,
581 /* HT clock is always available, and fulfills any of the
582 * following clock requests */
595 panic("invalid PMU state: %d", dinfo->pmu_state);
598 /* BHND_BUS_ENABLE_CLOCKS() */
600 siba_enable_clocks(device_t dev, device_t child, uint32_t clocks)
602 struct siba_softc *sc;
603 struct siba_devinfo *dinfo;
605 if (device_get_parent(child) != dev)
608 sc = device_get_softc(dev);
609 dinfo = device_get_ivars(child);
612 switch(dinfo->pmu_state) {
614 panic("no active PMU request state");
621 return (bhnd_generic_enable_clocks(dev, child, clocks));
623 case SIBA_PMU_PWRCTL:
627 /* All (supported) clocks are already enabled by default */
628 clocks &= ~(BHND_CLOCK_DYN |
634 device_printf(dev, "%s requested unknown clocks: %#x\n",
635 device_get_nameunit(child), clocks);
642 panic("invalid PMU state: %d", dinfo->pmu_state);
646 siba_read_iost(device_t dev, device_t child, uint16_t *iost)
651 error = bhnd_read_config(child, SIBA_CFG0_TMSTATEHIGH, &tmhigh, 4);
655 *iost = (SIBA_REG_GET(tmhigh, TMH_SISF));
660 siba_read_ioctl(device_t dev, device_t child, uint16_t *ioctl)
665 if ((error = bhnd_read_config(child, SIBA_CFG0_TMSTATELOW, &ts_low, 4)))
668 *ioctl = (SIBA_REG_GET(ts_low, TML_SICF));
673 siba_write_ioctl(device_t dev, device_t child, uint16_t value, uint16_t mask)
675 struct siba_devinfo *dinfo;
676 struct bhnd_resource *r;
677 uint32_t ts_low, ts_mask;
679 if (device_get_parent(child) != dev)
682 /* Fetch CFG0 mapping */
683 dinfo = device_get_ivars(child);
684 if ((r = dinfo->cfg_res[0]) == NULL)
687 /* Mask and set TMSTATELOW core flag bits */
688 ts_mask = (mask << SIBA_TML_SICF_SHIFT) & SIBA_TML_SICF_MASK;
689 ts_low = (value << SIBA_TML_SICF_SHIFT) & ts_mask;
691 siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATELOW,
697 siba_is_hw_suspended(device_t dev, device_t child)
703 /* Fetch target state */
704 error = bhnd_read_config(child, SIBA_CFG0_TMSTATELOW, &ts_low, 4);
706 device_printf(child, "error reading HW reset state: %d\n",
711 /* Is core held in RESET? */
712 if (ts_low & SIBA_TML_RESET)
715 /* Is target reject enabled? */
716 if (ts_low & SIBA_TML_REJ_MASK)
719 /* Is core clocked? */
720 ioctl = SIBA_REG_GET(ts_low, TML_SICF);
721 if (!(ioctl & BHND_IOCTL_CLK_EN))
728 siba_reset_hw(device_t dev, device_t child, uint16_t ioctl,
729 uint16_t reset_ioctl)
731 struct siba_devinfo *dinfo;
732 struct bhnd_resource *r;
733 uint32_t ts_low, imstate;
737 if (device_get_parent(child) != dev)
740 dinfo = device_get_ivars(child);
742 /* Can't suspend the core without access to the CFG0 registers */
743 if ((r = dinfo->cfg_res[0]) == NULL)
746 /* We require exclusive control over BHND_IOCTL_CLK_(EN|FORCE) */
747 clkflags = BHND_IOCTL_CLK_EN | BHND_IOCTL_CLK_FORCE;
748 if (ioctl & clkflags)
751 /* Place core into known RESET state */
752 if ((error = bhnd_suspend_hw(child, reset_ioctl)))
755 /* Set RESET, clear REJ, set the caller's IOCTL flags, and
756 * force clocks to ensure the signal propagates throughout the
758 ts_low = SIBA_TML_RESET |
759 (ioctl << SIBA_TML_SICF_SHIFT) |
760 (BHND_IOCTL_CLK_EN << SIBA_TML_SICF_SHIFT) |
761 (BHND_IOCTL_CLK_FORCE << SIBA_TML_SICF_SHIFT);
763 siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATELOW,
766 /* Clear any target errors */
767 if (bhnd_bus_read_4(r, SIBA_CFG0_TMSTATEHIGH) & SIBA_TMH_SERR) {
768 siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATEHIGH,
772 /* Clear any initiator errors */
773 imstate = bhnd_bus_read_4(r, SIBA_CFG0_IMSTATE);
774 if (imstate & (SIBA_IM_IBE|SIBA_IM_TO)) {
775 siba_write_target_state(child, dinfo, SIBA_CFG0_IMSTATE, 0x0,
776 SIBA_IM_IBE|SIBA_IM_TO);
779 /* Release from RESET while leaving clocks forced, ensuring the
780 * signal propagates throughout the core */
781 siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATELOW, 0x0,
784 /* The core should now be active; we can clear the BHND_IOCTL_CLK_FORCE
785 * bit and allow the core to manage clock gating. */
786 siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATELOW, 0x0,
787 (BHND_IOCTL_CLK_FORCE << SIBA_TML_SICF_SHIFT));
793 siba_suspend_hw(device_t dev, device_t child, uint16_t ioctl)
795 struct siba_softc *sc;
796 struct siba_devinfo *dinfo;
797 struct bhnd_resource *r;
798 uint32_t idl, ts_low, ts_mask;
799 uint16_t cflags, clkflags;
802 if (device_get_parent(child) != dev)
805 sc = device_get_softc(dev);
806 dinfo = device_get_ivars(child);
808 /* Can't suspend the core without access to the CFG0 registers */
809 if ((r = dinfo->cfg_res[0]) == NULL)
812 /* We require exclusive control over BHND_IOCTL_CLK_(EN|FORCE) */
813 clkflags = BHND_IOCTL_CLK_EN | BHND_IOCTL_CLK_FORCE;
814 if (ioctl & clkflags)
817 /* Already in RESET? */
818 ts_low = bhnd_bus_read_4(r, SIBA_CFG0_TMSTATELOW);
819 if (ts_low & SIBA_TML_RESET)
822 /* If clocks are already disabled, we can place the core directly
823 * into RESET|REJ while setting the caller's IOCTL flags. */
824 cflags = SIBA_REG_GET(ts_low, TML_SICF);
825 if (!(cflags & BHND_IOCTL_CLK_EN)) {
826 ts_low = SIBA_TML_RESET | SIBA_TML_REJ |
827 (ioctl << SIBA_TML_SICF_SHIFT);
828 ts_mask = SIBA_TML_RESET | SIBA_TML_REJ | SIBA_TML_SICF_MASK;
830 siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATELOW,
835 /* Reject further transactions reaching this core */
836 siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATELOW,
837 SIBA_TML_REJ, SIBA_TML_REJ);
839 /* Wait for transaction busy flag to clear for all transactions
840 * initiated by this core */
841 error = siba_wait_target_state(child, dinfo, SIBA_CFG0_TMSTATEHIGH,
842 0x0, SIBA_TMH_BUSY, 100000);
846 /* If this is an initiator core, we need to reject initiator
847 * transactions too. */
848 idl = bhnd_bus_read_4(r, SIBA_CFG0_IDLOW);
849 if (idl & SIBA_IDL_INIT) {
850 /* Reject further initiator transactions */
851 siba_write_target_state(child, dinfo, SIBA_CFG0_IMSTATE,
852 SIBA_IM_RJ, SIBA_IM_RJ);
854 /* Wait for initiator busy flag to clear */
855 error = siba_wait_target_state(child, dinfo, SIBA_CFG0_IMSTATE,
856 0x0, SIBA_IM_BY, 100000);
861 /* Put the core into RESET, set the caller's IOCTL flags, and
862 * force clocks to ensure the RESET signal propagates throughout the
864 ts_low = SIBA_TML_RESET |
865 (ioctl << SIBA_TML_SICF_SHIFT) |
866 (BHND_IOCTL_CLK_EN << SIBA_TML_SICF_SHIFT) |
867 (BHND_IOCTL_CLK_FORCE << SIBA_TML_SICF_SHIFT);
868 ts_mask = SIBA_TML_RESET |
871 siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATELOW, ts_low,
874 /* Give RESET ample time */
877 /* Clear previously asserted initiator reject */
878 if (idl & SIBA_IDL_INIT) {
879 siba_write_target_state(child, dinfo, SIBA_CFG0_IMSTATE, 0x0,
883 /* Disable all clocks, leaving RESET and REJ asserted */
884 siba_write_target_state(child, dinfo, SIBA_CFG0_TMSTATELOW, 0x0,
885 (BHND_IOCTL_CLK_EN | BHND_IOCTL_CLK_FORCE) << SIBA_TML_SICF_SHIFT);
888 * Core is now in RESET.
890 * If the core holds any PWRCTL clock reservations, we need to release
891 * those now. This emulates the standard bhnd(4) PMU behavior of RESET
892 * automatically clearing clkctl
895 if (dinfo->pmu_state == SIBA_PMU_PWRCTL) {
896 error = bhnd_pwrctl_request_clock(dinfo->pmu.pwrctl, child,
901 device_printf(child, "failed to release clock request: "
914 siba_read_config(device_t dev, device_t child, bus_size_t offset, void *value,
917 struct siba_devinfo *dinfo;
920 /* Must be directly attached */
921 if (device_get_parent(child) != dev)
924 /* CFG0 registers must be available */
925 dinfo = device_get_ivars(child);
926 if (dinfo->cfg_res[0] == NULL)
929 /* Offset must fall within CFG0 */
930 r_size = rman_get_size(dinfo->cfg_res[0]->res);
931 if (r_size < offset || r_size - offset < width)
936 *((uint8_t *)value) = bhnd_bus_read_1(dinfo->cfg_res[0],
940 *((uint16_t *)value) = bhnd_bus_read_2(dinfo->cfg_res[0],
944 *((uint32_t *)value) = bhnd_bus_read_4(dinfo->cfg_res[0],
953 siba_write_config(device_t dev, device_t child, bus_size_t offset,
954 const void *value, u_int width)
956 struct siba_devinfo *dinfo;
957 struct bhnd_resource *r;
960 /* Must be directly attached */
961 if (device_get_parent(child) != dev)
964 /* CFG0 registers must be available */
965 dinfo = device_get_ivars(child);
966 if ((r = dinfo->cfg_res[0]) == NULL)
969 /* Offset must fall within CFG0 */
970 r_size = rman_get_size(r->res);
971 if (r_size < offset || r_size - offset < width)
976 bhnd_bus_write_1(r, offset, *(const uint8_t *)value);
979 bhnd_bus_write_2(r, offset, *(const uint8_t *)value);
982 bhnd_bus_write_4(r, offset, *(const uint8_t *)value);
990 siba_get_port_count(device_t dev, device_t child, bhnd_port_type type)
992 struct siba_devinfo *dinfo;
994 /* delegate non-bus-attached devices to our parent */
995 if (device_get_parent(child) != dev)
996 return (BHND_BUS_GET_PORT_COUNT(device_get_parent(dev), child,
999 dinfo = device_get_ivars(child);
1000 return (siba_port_count(&dinfo->core_id, type));
1004 siba_get_region_count(device_t dev, device_t child, bhnd_port_type type,
1007 struct siba_devinfo *dinfo;
1009 /* delegate non-bus-attached devices to our parent */
1010 if (device_get_parent(child) != dev)
1011 return (BHND_BUS_GET_REGION_COUNT(device_get_parent(dev), child,
1014 dinfo = device_get_ivars(child);
1015 return (siba_port_region_count(&dinfo->core_id, type, port));
1019 siba_get_port_rid(device_t dev, device_t child, bhnd_port_type port_type,
1020 u_int port_num, u_int region_num)
1022 struct siba_devinfo *dinfo;
1023 struct siba_addrspace *addrspace;
1024 struct siba_cfg_block *cfg;
1026 /* delegate non-bus-attached devices to our parent */
1027 if (device_get_parent(child) != dev)
1028 return (BHND_BUS_GET_PORT_RID(device_get_parent(dev), child,
1029 port_type, port_num, region_num));
1031 dinfo = device_get_ivars(child);
1033 /* Look for a matching addrspace entry */
1034 addrspace = siba_find_addrspace(dinfo, port_type, port_num, region_num);
1035 if (addrspace != NULL)
1036 return (addrspace->sa_rid);
1038 /* Try the config blocks */
1039 cfg = siba_find_cfg_block(dinfo, port_type, port_num, region_num);
1041 return (cfg->cb_rid);
1048 siba_decode_port_rid(device_t dev, device_t child, int type, int rid,
1049 bhnd_port_type *port_type, u_int *port_num, u_int *region_num)
1051 struct siba_devinfo *dinfo;
1053 /* delegate non-bus-attached devices to our parent */
1054 if (device_get_parent(child) != dev)
1055 return (BHND_BUS_DECODE_PORT_RID(device_get_parent(dev), child,
1056 type, rid, port_type, port_num, region_num));
1058 dinfo = device_get_ivars(child);
1060 /* Ports are always memory mapped */
1061 if (type != SYS_RES_MEMORY)
1064 /* Look for a matching addrspace entry */
1065 for (u_int i = 0; i < dinfo->core_id.num_admatch; i++) {
1066 if (dinfo->addrspace[i].sa_rid != rid)
1069 *port_type = BHND_PORT_DEVICE;
1070 *port_num = siba_addrspace_device_port(i);
1071 *region_num = siba_addrspace_device_region(i);
1075 /* Try the config blocks */
1076 for (u_int i = 0; i < dinfo->core_id.num_cfg_blocks; i++) {
1077 if (dinfo->cfg[i].cb_rid != rid)
1080 *port_type = BHND_PORT_AGENT;
1081 *port_num = siba_cfg_agent_port(i);
1082 *region_num = siba_cfg_agent_region(i);
1091 siba_get_region_addr(device_t dev, device_t child, bhnd_port_type port_type,
1092 u_int port_num, u_int region_num, bhnd_addr_t *addr, bhnd_size_t *size)
1094 struct siba_devinfo *dinfo;
1095 struct siba_addrspace *addrspace;
1096 struct siba_cfg_block *cfg;
1098 /* delegate non-bus-attached devices to our parent */
1099 if (device_get_parent(child) != dev) {
1100 return (BHND_BUS_GET_REGION_ADDR(device_get_parent(dev), child,
1101 port_type, port_num, region_num, addr, size));
1104 dinfo = device_get_ivars(child);
1106 /* Look for a matching addrspace */
1107 addrspace = siba_find_addrspace(dinfo, port_type, port_num, region_num);
1108 if (addrspace != NULL) {
1109 *addr = addrspace->sa_base;
1110 *size = addrspace->sa_size - addrspace->sa_bus_reserved;
1114 /* Look for a matching cfg block */
1115 cfg = siba_find_cfg_block(dinfo, port_type, port_num, region_num);
1117 *addr = cfg->cb_base;
1118 *size = cfg->cb_size;
1127 * Default siba(4) bus driver implementation of BHND_BUS_GET_INTR_COUNT().
1130 siba_get_intr_count(device_t dev, device_t child)
1132 struct siba_devinfo *dinfo;
1134 /* delegate non-bus-attached devices to our parent */
1135 if (device_get_parent(child) != dev)
1136 return (BHND_BUS_GET_INTR_COUNT(device_get_parent(dev), child));
1138 dinfo = device_get_ivars(child);
1139 if (!dinfo->core_id.intr_en) {
1143 /* One assigned interrupt */
1149 * Default siba(4) bus driver implementation of BHND_BUS_GET_INTR_IVEC().
1152 siba_get_intr_ivec(device_t dev, device_t child, u_int intr, u_int *ivec)
1154 struct siba_devinfo *dinfo;
1156 /* delegate non-bus-attached devices to our parent */
1157 if (device_get_parent(child) != dev)
1158 return (BHND_BUS_GET_INTR_IVEC(device_get_parent(dev), child,
1161 /* Must be a valid interrupt ID */
1162 if (intr >= siba_get_intr_count(dev, child))
1165 KASSERT(intr == 0, ("invalid ivec %u", intr));
1167 dinfo = device_get_ivars(child);
1169 KASSERT(dinfo->core_id.intr_en,
1170 ("core does not have an interrupt assigned"));
1172 *ivec = dinfo->core_id.intr_flag;
1177 * Map per-core configuration blocks for @p dinfo.
1179 * @param dev The siba bus device.
1180 * @param dinfo The device info instance on which to map all per-core
1181 * configuration blocks.
1184 siba_map_cfg_resources(device_t dev, struct siba_devinfo *dinfo)
1186 struct siba_addrspace *addrspace;
1187 rman_res_t r_start, r_count, r_end;
1191 num_cfg = dinfo->core_id.num_cfg_blocks;
1192 if (num_cfg > SIBA_MAX_CFG) {
1193 device_printf(dev, "config block count %hhu out of range\n",
1198 /* Fetch the core register address space */
1199 addrspace = siba_find_addrspace(dinfo, BHND_PORT_DEVICE, 0, 0);
1200 if (addrspace == NULL) {
1201 device_printf(dev, "missing device registers\n");
1206 * Map the per-core configuration blocks
1208 for (uint8_t i = 0; i < num_cfg; i++) {
1209 /* Add to child's resource list */
1210 r_start = addrspace->sa_base + SIBA_CFG_OFFSET(i);
1211 r_count = SIBA_CFG_SIZE;
1212 r_end = r_start + r_count - 1;
1214 rid = resource_list_add_next(&dinfo->resources, SYS_RES_MEMORY,
1215 r_start, r_end, r_count);
1217 /* Initialize config block descriptor */
1218 dinfo->cfg[i] = ((struct siba_cfg_block) {
1220 .cb_size = SIBA_CFG_SIZE,
1224 /* Map the config resource for bus-level access */
1225 dinfo->cfg_rid[i] = SIBA_CFG_RID(dinfo, i);
1226 dinfo->cfg_res[i] = BHND_BUS_ALLOC_RESOURCE(dev, dev,
1227 SYS_RES_MEMORY, &dinfo->cfg_rid[i], r_start, r_end,
1228 r_count, RF_ACTIVE|RF_SHAREABLE);
1230 if (dinfo->cfg_res[i] == NULL) {
1231 device_printf(dev, "failed to allocate SIBA_CFG%hhu\n",
1241 siba_add_child(device_t dev, u_int order, const char *name, int unit)
1243 struct siba_devinfo *dinfo;
1246 child = device_add_child_ordered(dev, order, name, unit);
1250 if ((dinfo = siba_alloc_dinfo(dev)) == NULL) {
1251 device_delete_child(dev, child);
1255 device_set_ivars(child, dinfo);
1261 siba_child_deleted(device_t dev, device_t child)
1263 struct bhnd_softc *sc;
1264 struct siba_devinfo *dinfo;
1266 sc = device_get_softc(dev);
1268 /* Call required bhnd(4) implementation */
1269 bhnd_generic_child_deleted(dev, child);
1271 /* Free siba device info */
1272 if ((dinfo = device_get_ivars(child)) != NULL)
1273 siba_free_dinfo(dev, child, dinfo);
1275 device_set_ivars(child, NULL);
1279 * Scan the core table and add all valid discovered cores to
1282 * @param dev The siba bus device.
1285 siba_add_children(device_t dev)
1288 struct siba_erom *siba_erom;
1289 struct bhnd_erom_io *eio;
1290 const struct bhnd_chipid *cid;
1291 struct siba_core_id *cores;
1295 cid = BHND_BUS_GET_CHIPID(dev, dev);
1297 /* Allocate our EROM parser */
1298 eio = bhnd_erom_iores_new(dev, SIBA_EROM_RID);
1299 erom = bhnd_erom_alloc(&siba_erom_parser, cid, eio);
1301 bhnd_erom_io_fini(eio);
1305 /* Allocate our temporary core and device table */
1306 cores = malloc(sizeof(*cores) * cid->ncores, M_BHND, M_WAITOK);
1307 children = malloc(sizeof(*children) * cid->ncores, M_BHND,
1311 * Add child devices for all discovered cores.
1313 * On bridged devices, we'll exhaust our available register windows if
1314 * we map config blocks on unpopulated/disabled cores. To avoid this, we
1315 * defer mapping of the per-core siba(4) config blocks until all cores
1316 * have been enumerated and otherwise configured.
1318 siba_erom = (struct siba_erom *)erom;
1319 for (u_int i = 0; i < cid->ncores; i++) {
1320 struct siba_devinfo *dinfo;
1323 if ((error = siba_erom_get_core_id(siba_erom, i, &cores[i])))
1326 /* Add the child device */
1327 child = BUS_ADD_CHILD(dev, 0, NULL, -1);
1328 if (child == NULL) {
1333 children[i] = child;
1335 /* Initialize per-device bus info */
1336 if ((dinfo = device_get_ivars(child)) == NULL) {
1341 if ((error = siba_init_dinfo(dev, child, dinfo, &cores[i])))
1344 /* If pins are floating or the hardware is otherwise
1345 * unpopulated, the device shouldn't be used. */
1346 if (bhnd_is_hw_disabled(child))
1347 device_disable(child);
1350 /* Free EROM (and any bridge register windows it might hold) */
1351 bhnd_erom_free(erom);
1354 /* Map all valid core's config register blocks and perform interrupt
1356 for (u_int i = 0; i < cid->ncores; i++) {
1357 struct siba_devinfo *dinfo;
1360 child = children[i];
1362 /* Skip if core is disabled */
1363 if (bhnd_is_hw_disabled(child))
1366 dinfo = device_get_ivars(child);
1368 /* Map the core's config blocks */
1369 if ((error = siba_map_cfg_resources(dev, dinfo)))
1372 /* Issue bus callback for fully initialized child. */
1373 BHND_BUS_CHILD_ADDED(dev, child);
1376 free(cores, M_BHND);
1377 free(children, M_BHND);
1382 for (u_int i = 0; i < cid->ncores; i++) {
1383 if (children[i] == NULL)
1386 device_delete_child(dev, children[i]);
1389 free(cores, M_BHND);
1390 free(children, M_BHND);
1392 bhnd_erom_free(erom);
1397 static device_method_t siba_methods[] = {
1398 /* Device interface */
1399 DEVMETHOD(device_probe, siba_probe),
1400 DEVMETHOD(device_attach, siba_attach),
1401 DEVMETHOD(device_detach, siba_detach),
1402 DEVMETHOD(device_resume, siba_resume),
1403 DEVMETHOD(device_suspend, siba_suspend),
1406 DEVMETHOD(bus_add_child, siba_add_child),
1407 DEVMETHOD(bus_child_deleted, siba_child_deleted),
1408 DEVMETHOD(bus_read_ivar, siba_read_ivar),
1409 DEVMETHOD(bus_write_ivar, siba_write_ivar),
1410 DEVMETHOD(bus_get_resource_list, siba_get_resource_list),
1412 /* BHND interface */
1413 DEVMETHOD(bhnd_bus_get_erom_class, siba_get_erom_class),
1414 DEVMETHOD(bhnd_bus_alloc_pmu, siba_alloc_pmu),
1415 DEVMETHOD(bhnd_bus_release_pmu, siba_release_pmu),
1416 DEVMETHOD(bhnd_bus_request_clock, siba_request_clock),
1417 DEVMETHOD(bhnd_bus_enable_clocks, siba_enable_clocks),
1418 DEVMETHOD(bhnd_bus_request_ext_rsrc, siba_request_ext_rsrc),
1419 DEVMETHOD(bhnd_bus_release_ext_rsrc, siba_release_ext_rsrc),
1420 DEVMETHOD(bhnd_bus_get_clock_freq, siba_get_clock_freq),
1421 DEVMETHOD(bhnd_bus_get_clock_latency, siba_get_clock_latency),
1422 DEVMETHOD(bhnd_bus_read_ioctl, siba_read_ioctl),
1423 DEVMETHOD(bhnd_bus_write_ioctl, siba_write_ioctl),
1424 DEVMETHOD(bhnd_bus_read_iost, siba_read_iost),
1425 DEVMETHOD(bhnd_bus_is_hw_suspended, siba_is_hw_suspended),
1426 DEVMETHOD(bhnd_bus_reset_hw, siba_reset_hw),
1427 DEVMETHOD(bhnd_bus_suspend_hw, siba_suspend_hw),
1428 DEVMETHOD(bhnd_bus_read_config, siba_read_config),
1429 DEVMETHOD(bhnd_bus_write_config, siba_write_config),
1430 DEVMETHOD(bhnd_bus_get_port_count, siba_get_port_count),
1431 DEVMETHOD(bhnd_bus_get_region_count, siba_get_region_count),
1432 DEVMETHOD(bhnd_bus_get_port_rid, siba_get_port_rid),
1433 DEVMETHOD(bhnd_bus_decode_port_rid, siba_decode_port_rid),
1434 DEVMETHOD(bhnd_bus_get_region_addr, siba_get_region_addr),
1435 DEVMETHOD(bhnd_bus_get_intr_count, siba_get_intr_count),
1436 DEVMETHOD(bhnd_bus_get_intr_ivec, siba_get_intr_ivec),
1441 DEFINE_CLASS_1(bhnd, siba_driver, siba_methods, sizeof(struct siba_softc), bhnd_driver);
1443 MODULE_VERSION(siba, 1);
1444 MODULE_DEPEND(siba, bhnd, 1, 1, 1);