2 * Copyright 2008 Nathan Whitehorn. All rights reserved.
3 * Copyright 2003 by Peter Grehan. All rights reserved.
4 * Copyright (C) 1998, 1999, 2000 Tsubai Masanari. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * NetBSD: if_bm.c,v 1.9.2.1 2000/11/01 15:02:49 tv Exp
34 * BMAC/BMAC+ Macio cell 10/100 ethernet driver
35 * The low-cost, low-feature Apple variant of the Sun HME
38 #include <sys/cdefs.h>
39 __FBSDID("$FreeBSD$");
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/sockio.h>
44 #include <sys/endian.h>
46 #include <sys/module.h>
47 #include <sys/malloc.h>
48 #include <sys/kernel.h>
49 #include <sys/socket.h>
53 #include <net/if_arp.h>
54 #include <net/ethernet.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/if_types.h>
59 #include <machine/pio.h>
60 #include <machine/bus.h>
61 #include <machine/resource.h>
65 #include <dev/mii/mii.h>
66 #include <dev/mii/miivar.h>
68 #include <dev/ofw/ofw_bus.h>
69 #include <dev/ofw/openfirm.h>
70 #include <machine/dbdma.h>
72 MODULE_DEPEND(bm, ether, 1, 1, 1);
73 MODULE_DEPEND(bm, miibus, 1, 1, 1);
75 /* "controller miibus0" required. See GENERIC if you get errors here. */
76 #include "miibus_if.h"
81 static int bm_probe (device_t);
82 static int bm_attach (device_t);
83 static int bm_detach (device_t);
84 static int bm_shutdown (device_t);
86 static void bm_start (struct ifnet *);
87 static void bm_start_locked (struct ifnet *);
88 static int bm_encap (struct bm_softc *sc, struct mbuf **m_head);
89 static int bm_ioctl (struct ifnet *, u_long, caddr_t);
90 static void bm_init (void *);
91 static void bm_init_locked (struct bm_softc *sc);
92 static void bm_chip_setup (struct bm_softc *sc);
93 static void bm_stop (struct bm_softc *sc);
94 static void bm_setladrf (struct bm_softc *sc);
95 static void bm_dummypacket (struct bm_softc *sc);
96 static void bm_txintr (void *xsc);
97 static void bm_rxintr (void *xsc);
99 static int bm_add_rxbuf (struct bm_softc *sc, int i);
100 static int bm_add_rxbuf_dma (struct bm_softc *sc, int i);
101 static void bm_enable_interrupts (struct bm_softc *sc);
102 static void bm_disable_interrupts (struct bm_softc *sc);
103 static void bm_tick (void *xsc);
105 static int bm_ifmedia_upd (struct ifnet *);
106 static void bm_ifmedia_sts (struct ifnet *, struct ifmediareq *);
108 static void bm_miicsr_dwrite (struct bm_softc *, u_int16_t);
109 static void bm_mii_writebit (struct bm_softc *, int);
110 static int bm_mii_readbit (struct bm_softc *);
111 static void bm_mii_sync (struct bm_softc *);
112 static void bm_mii_send (struct bm_softc *, u_int32_t, int);
113 static int bm_mii_readreg (struct bm_softc *, struct bm_mii_frame *);
114 static int bm_mii_writereg (struct bm_softc *, struct bm_mii_frame *);
115 static int bm_miibus_readreg (device_t, int, int);
116 static int bm_miibus_writereg (device_t, int, int, int);
117 static void bm_miibus_statchg (device_t);
119 static device_method_t bm_methods[] = {
120 /* Device interface */
121 DEVMETHOD(device_probe, bm_probe),
122 DEVMETHOD(device_attach, bm_attach),
123 DEVMETHOD(device_detach, bm_detach),
124 DEVMETHOD(device_shutdown, bm_shutdown),
126 /* bus interface, for miibus */
127 DEVMETHOD(bus_print_child, bus_generic_print_child),
128 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
131 DEVMETHOD(miibus_readreg, bm_miibus_readreg),
132 DEVMETHOD(miibus_writereg, bm_miibus_writereg),
133 DEVMETHOD(miibus_statchg, bm_miibus_statchg),
137 static driver_t bm_macio_driver = {
140 sizeof(struct bm_softc)
143 static devclass_t bm_devclass;
145 DRIVER_MODULE(bm, macio, bm_macio_driver, bm_devclass, 0, 0);
146 DRIVER_MODULE(miibus, bm, miibus_driver, miibus_devclass, 0, 0);
149 * MII internal routines
153 * Write to the MII csr, introducing a delay to allow valid
154 * MII clock pulses to be formed
157 bm_miicsr_dwrite(struct bm_softc *sc, u_int16_t val)
159 CSR_WRITE_2(sc, BM_MII_CSR, val);
161 * Assume this is a clock toggle and generate a 1us delay
162 * to cover both MII's 160ns high/low minimum and 400ns
169 * Write a bit to the MII bus.
172 bm_mii_writebit(struct bm_softc *sc, int bit)
176 regval = BM_MII_OENABLE;
178 regval |= BM_MII_DATAOUT;
180 bm_miicsr_dwrite(sc, regval);
181 bm_miicsr_dwrite(sc, regval | BM_MII_CLK);
182 bm_miicsr_dwrite(sc, regval);
186 * Read a bit from the MII bus.
189 bm_mii_readbit(struct bm_softc *sc)
191 u_int16_t regval, bitin;
193 /* ~BM_MII_OENABLE */
196 bm_miicsr_dwrite(sc, regval);
197 bm_miicsr_dwrite(sc, regval | BM_MII_CLK);
198 bm_miicsr_dwrite(sc, regval);
199 bitin = CSR_READ_2(sc, BM_MII_CSR) & BM_MII_DATAIN;
201 return (bitin == BM_MII_DATAIN);
205 * Sync the PHYs by setting data bit and strobing the clock 32 times.
208 bm_mii_sync(struct bm_softc *sc)
213 regval = BM_MII_OENABLE | BM_MII_DATAOUT;
215 bm_miicsr_dwrite(sc, regval);
216 for (i = 0; i < 32; i++) {
217 bm_miicsr_dwrite(sc, regval | BM_MII_CLK);
218 bm_miicsr_dwrite(sc, regval);
223 * Clock a series of bits through the MII.
226 bm_mii_send(struct bm_softc *sc, u_int32_t bits, int cnt)
230 for (i = (0x1 << (cnt - 1)); i; i >>= 1)
231 bm_mii_writebit(sc, bits & i);
235 * Read a PHY register through the MII.
238 bm_mii_readreg(struct bm_softc *sc, struct bm_mii_frame *frame)
243 * Set up frame for RX.
245 frame->mii_stdelim = BM_MII_STARTDELIM;
246 frame->mii_opcode = BM_MII_READOP;
247 frame->mii_turnaround = 0;
256 * Send command/address info
258 bm_mii_send(sc, frame->mii_stdelim, 2);
259 bm_mii_send(sc, frame->mii_opcode, 2);
260 bm_mii_send(sc, frame->mii_phyaddr, 5);
261 bm_mii_send(sc, frame->mii_regaddr, 5);
266 ack = bm_mii_readbit(sc);
269 * Now try reading data bits. If the ack failed, we still
270 * need to clock through 16 cycles to keep the PHY(s) in sync.
272 for (i = 0x8000; i; i >>= 1) {
273 bit = bm_mii_readbit(sc);
275 frame->mii_data |= i;
279 * Skip through idle bit-times
281 bm_mii_writebit(sc, 0);
282 bm_mii_writebit(sc, 0);
284 return ((ack) ? 1 : 0);
288 * Write to a PHY register through the MII.
291 bm_mii_writereg(struct bm_softc *sc, struct bm_mii_frame *frame)
294 * Set up frame for tx
296 frame->mii_stdelim = BM_MII_STARTDELIM;
297 frame->mii_opcode = BM_MII_WRITEOP;
298 frame->mii_turnaround = BM_MII_TURNAROUND;
301 * Sync the phy and start the bitbang write sequence
305 bm_mii_send(sc, frame->mii_stdelim, 2);
306 bm_mii_send(sc, frame->mii_opcode, 2);
307 bm_mii_send(sc, frame->mii_phyaddr, 5);
308 bm_mii_send(sc, frame->mii_regaddr, 5);
309 bm_mii_send(sc, frame->mii_turnaround, 2);
310 bm_mii_send(sc, frame->mii_data, 16);
315 bm_mii_writebit(sc, 0);
324 bm_miibus_readreg(device_t dev, int phy, int reg)
327 struct bm_mii_frame frame;
329 sc = device_get_softc(dev);
330 bzero(&frame, sizeof(frame));
332 frame.mii_phyaddr = phy;
333 frame.mii_regaddr = reg;
335 bm_mii_readreg(sc, &frame);
337 return (frame.mii_data);
341 bm_miibus_writereg(device_t dev, int phy, int reg, int data)
344 struct bm_mii_frame frame;
346 sc = device_get_softc(dev);
347 bzero(&frame, sizeof(frame));
349 frame.mii_phyaddr = phy;
350 frame.mii_regaddr = reg;
351 frame.mii_data = data;
353 bm_mii_writereg(sc, &frame);
359 bm_miibus_statchg(device_t dev)
361 struct bm_softc *sc = device_get_softc(dev);
365 reg = CSR_READ_2(sc, BM_TX_CONFIG);
366 new_duplex = IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX;
368 if (new_duplex != sc->sc_duplex) {
369 /* Turn off TX MAC while we fiddle its settings */
372 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
373 while (CSR_READ_2(sc, BM_TX_CONFIG) & BM_ENABLE)
377 if (new_duplex && !sc->sc_duplex)
378 reg |= BM_TX_IGNORECOLL | BM_TX_FULLDPX;
379 else if (!new_duplex && sc->sc_duplex)
380 reg &= ~(BM_TX_IGNORECOLL | BM_TX_FULLDPX);
382 if (new_duplex != sc->sc_duplex) {
383 /* Turn TX MAC back on */
386 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
387 sc->sc_duplex = new_duplex;
392 * ifmedia/mii callbacks
395 bm_ifmedia_upd(struct ifnet *ifp)
397 struct bm_softc *sc = ifp->if_softc;
401 error = mii_mediachg(sc->sc_mii);
407 bm_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifm)
409 struct bm_softc *sc = ifp->if_softc;
412 mii_pollstat(sc->sc_mii);
413 ifm->ifm_active = sc->sc_mii->mii_media_active;
414 ifm->ifm_status = sc->sc_mii->mii_media_status;
422 bm_probe(device_t dev)
424 const char *dname = ofw_bus_get_name(dev);
425 const char *dcompat = ofw_bus_get_compat(dev);
428 * BMAC+ cells have a name of "ethernet" and
429 * a compatible property of "bmac+"
431 if (strcmp(dname, "bmac") == 0) {
432 device_set_desc(dev, "Apple BMAC Ethernet Adaptor");
433 } else if (strcmp(dcompat, "bmac+") == 0) {
434 device_set_desc(dev, "Apple BMAC+ Ethernet Adaptor");
442 bm_attach(device_t dev)
447 int error, cellid, i;
448 struct bm_txsoft *txs;
449 struct bm_softc *sc = device_get_softc(dev);
451 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
454 sc->sc_duplex = ~IFM_FDX;
457 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
459 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
461 /* Check for an improved version of Paddington */
462 sc->sc_streaming = 0;
464 node = ofw_bus_get_node(dev);
466 OF_getprop(node, "cell-id", &cellid, sizeof(cellid));
468 sc->sc_streaming = 1;
471 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
472 &sc->sc_memrid, RF_ACTIVE);
473 if (sc->sc_memr == NULL) {
474 device_printf(dev, "Could not alloc chip registers!\n");
478 sc->sc_txdmarid = BM_TXDMA_REGISTERS;
479 sc->sc_rxdmarid = BM_RXDMA_REGISTERS;
481 sc->sc_txdmar = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
482 &sc->sc_txdmarid, RF_ACTIVE);
483 sc->sc_rxdmar = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
484 &sc->sc_rxdmarid, RF_ACTIVE);
486 if (sc->sc_txdmar == NULL || sc->sc_rxdmar == NULL) {
487 device_printf(dev, "Could not map DBDMA registers!\n");
491 error = dbdma_allocate_channel(sc->sc_txdmar, 0, bus_get_dma_tag(dev),
492 BM_MAX_DMA_COMMANDS, &sc->sc_txdma);
493 error += dbdma_allocate_channel(sc->sc_rxdmar, 0, bus_get_dma_tag(dev),
494 BM_MAX_DMA_COMMANDS, &sc->sc_rxdma);
497 device_printf(dev,"Could not allocate DBDMA channel!\n");
501 /* alloc DMA tags and buffers */
502 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
503 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
504 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,
505 NULL, &sc->sc_pdma_tag);
508 device_printf(dev,"Could not allocate DMA tag!\n");
512 error = bus_dma_tag_create(sc->sc_pdma_tag, 1, 0, BUS_SPACE_MAXADDR,
513 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES,
514 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdma_tag);
517 device_printf(dev,"Could not allocate RX DMA channel!\n");
521 error = bus_dma_tag_create(sc->sc_pdma_tag, 1, 0, BUS_SPACE_MAXADDR,
522 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * BM_NTXSEGS, BM_NTXSEGS,
523 MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdma_tag);
526 device_printf(dev,"Could not allocate TX DMA tag!\n");
530 /* init transmit descriptors */
531 STAILQ_INIT(&sc->sc_txfreeq);
532 STAILQ_INIT(&sc->sc_txdirtyq);
534 /* create TX DMA maps */
536 for (i = 0; i < BM_MAX_TX_PACKETS; i++) {
537 txs = &sc->sc_txsoft[i];
538 txs->txs_mbuf = NULL;
539 error = bus_dmamap_create(sc->sc_tdma_tag, 0, &txs->txs_dmamap);
541 device_printf(sc->sc_dev,
542 "unable to create TX DMA map %d, error = %d\n",
545 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
548 /* Create the receive buffer DMA maps. */
549 for (i = 0; i < BM_MAX_RX_PACKETS; i++) {
550 error = bus_dmamap_create(sc->sc_rdma_tag, 0,
551 &sc->sc_rxsoft[i].rxs_dmamap);
553 device_printf(sc->sc_dev,
554 "unable to create RX DMA map %d, error = %d\n",
557 sc->sc_rxsoft[i].rxs_mbuf = NULL;
560 /* alloc interrupt */
562 sc->sc_txdmairqid = BM_TXDMA_INTERRUPT;
563 sc->sc_txdmairq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
564 &sc->sc_txdmairqid, RF_ACTIVE);
567 device_printf(dev,"Could not allocate TX interrupt!\n");
571 bus_setup_intr(dev,sc->sc_txdmairq,
572 INTR_TYPE_MISC | INTR_MPSAFE | INTR_ENTROPY, NULL, bm_txintr, sc,
575 sc->sc_rxdmairqid = BM_RXDMA_INTERRUPT;
576 sc->sc_rxdmairq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
577 &sc->sc_rxdmairqid, RF_ACTIVE);
580 device_printf(dev,"Could not allocate RX interrupt!\n");
584 bus_setup_intr(dev,sc->sc_rxdmairq,
585 INTR_TYPE_MISC | INTR_MPSAFE | INTR_ENTROPY, NULL, bm_rxintr, sc,
589 * Get the ethernet address from OpenFirmware
591 eaddr = sc->sc_enaddr;
592 OF_getprop(node, "local-mac-address", eaddr, ETHER_ADDR_LEN);
594 /* reset the adapter */
599 * On Apple BMAC controllers, we end up in a weird state of
600 * partially-completed autonegotiation on boot. So we force
601 * autonegotation to try again.
603 error = mii_attach(dev, &sc->sc_miibus, ifp, bm_ifmedia_upd,
604 bm_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
607 device_printf(dev, "attaching PHYs failed\n");
611 sc->sc_mii = device_get_softc(sc->sc_miibus);
613 if_initname(ifp, device_get_name(sc->sc_dev),
614 device_get_unit(sc->sc_dev));
615 ifp->if_mtu = ETHERMTU;
616 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
617 ifp->if_start = bm_start;
618 ifp->if_ioctl = bm_ioctl;
619 ifp->if_init = bm_init;
620 IFQ_SET_MAXLEN(&ifp->if_snd, BM_MAX_TX_PACKETS);
621 ifp->if_snd.ifq_drv_maxlen = BM_MAX_TX_PACKETS;
622 IFQ_SET_READY(&ifp->if_snd);
624 /* Attach the interface. */
625 ether_ifattach(ifp, sc->sc_enaddr);
626 ifp->if_hwassist = 0;
632 bm_detach(device_t dev)
634 struct bm_softc *sc = device_get_softc(dev);
640 callout_drain(&sc->sc_tick_ch);
641 ether_ifdetach(sc->sc_ifp);
642 bus_teardown_intr(dev, sc->sc_txdmairq, sc->sc_txihtx);
643 bus_teardown_intr(dev, sc->sc_rxdmairq, sc->sc_rxih);
645 dbdma_free_channel(sc->sc_txdma);
646 dbdma_free_channel(sc->sc_rxdma);
648 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid, sc->sc_memr);
649 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_txdmarid,
651 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rxdmarid,
654 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_txdmairqid,
656 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_rxdmairqid,
659 mtx_destroy(&sc->sc_mtx);
666 bm_shutdown(device_t dev)
670 sc = device_get_softc(dev);
680 bm_dummypacket(struct bm_softc *sc)
687 MGETHDR(m, M_DONTWAIT, MT_DATA);
693 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
695 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
696 mtod(m, struct ether_header *)->ether_type = htons(3);
697 mtod(m, unsigned char *)[14] = 0;
698 mtod(m, unsigned char *)[15] = 0;
699 mtod(m, unsigned char *)[16] = 0xE3;
700 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
701 IF_ENQUEUE(&ifp->if_snd, m);
702 bm_start_locked(ifp);
708 struct bm_softc *sc = xsc;
709 struct ifnet *ifp = sc->sc_ifp;
711 int i, prev_stop, new_stop;
716 status = dbdma_get_chan_status(sc->sc_rxdma);
717 if (status & DBDMA_STATUS_DEAD) {
718 dbdma_reset(sc->sc_rxdma);
722 if (!(status & DBDMA_STATUS_RUN)) {
723 device_printf(sc->sc_dev,"Bad RX Interrupt!\n");
728 prev_stop = sc->next_rxdma_slot - 1;
730 prev_stop = sc->rxdma_loop_slot - 1;
738 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_POSTREAD);
740 for (i = sc->next_rxdma_slot; i < BM_MAX_RX_PACKETS; i++) {
741 if (i == sc->rxdma_loop_slot)
747 status = dbdma_get_cmd_status(sc->sc_rxdma, i);
752 m = sc->sc_rxsoft[i].rxs_mbuf;
754 if (bm_add_rxbuf(sc, i)) {
764 m->m_pkthdr.rcvif = ifp;
765 m->m_len -= (dbdma_get_residuals(sc->sc_rxdma, i) + 2);
766 m->m_pkthdr.len = m->m_len;
768 /* Send up the stack */
770 (*ifp->if_input)(ifp, m);
773 /* Clear all fields on this command */
774 bm_add_rxbuf_dma(sc, i);
779 /* Change the last packet we processed to the ring buffer terminator,
780 * and restore a receive buffer to the old terminator */
782 dbdma_insert_stop(sc->sc_rxdma, new_stop);
783 bm_add_rxbuf_dma(sc, prev_stop);
784 if (i < sc->rxdma_loop_slot)
785 sc->next_rxdma_slot = i;
787 sc->next_rxdma_slot = 0;
789 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_PREWRITE);
791 dbdma_wake(sc->sc_rxdma);
799 struct bm_softc *sc = xsc;
800 struct ifnet *ifp = sc->sc_ifp;
801 struct bm_txsoft *txs;
806 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
807 if (!dbdma_get_cmd_status(sc->sc_txdma, txs->txs_lastdesc))
810 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
811 bus_dmamap_unload(sc->sc_tdma_tag, txs->txs_dmamap);
813 if (txs->txs_mbuf != NULL) {
814 m_freem(txs->txs_mbuf);
815 txs->txs_mbuf = NULL;
818 /* Set the first used TXDMA slot to the location of the
819 * STOP/NOP command associated with this packet. */
821 sc->first_used_txdma_slot = txs->txs_stopdesc;
823 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
831 * We freed some descriptors, so reset IFF_DRV_OACTIVE
834 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
835 sc->sc_wdog_timer = STAILQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5;
837 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) &&
838 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
839 bm_start_locked(ifp);
846 bm_start(struct ifnet *ifp)
848 struct bm_softc *sc = ifp->if_softc;
851 bm_start_locked(ifp);
856 bm_start_locked(struct ifnet *ifp)
858 struct bm_softc *sc = ifp->if_softc;
859 struct mbuf *mb_head;
864 * We lay out our DBDMA program in the following manner:
867 * OUTPUT_LAST (+ Interrupt)
870 * To extend the channel, we append a new program,
871 * then replace STOP with NOP and wake the channel.
872 * If we stalled on the STOP already, the program proceeds,
873 * if not it will sail through the NOP.
876 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
877 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head);
882 prev_stop = sc->next_txdma_slot - 1;
884 if (bm_encap(sc, &mb_head)) {
885 /* Put the packet back and stop */
886 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
887 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head);
891 dbdma_insert_nop(sc->sc_txdma, prev_stop);
895 BPF_MTAP(ifp, mb_head);
898 dbdma_sync_commands(sc->sc_txdma, BUS_DMASYNC_PREWRITE);
901 dbdma_wake(sc->sc_txdma);
902 sc->sc_wdog_timer = 5;
907 bm_encap(struct bm_softc *sc, struct mbuf **m_head)
909 bus_dma_segment_t segs[BM_NTXSEGS];
910 struct bm_txsoft *txs;
912 int nsegs = BM_NTXSEGS;
917 /* Limit the command size to the number of free DBDMA slots */
919 if (sc->next_txdma_slot >= sc->first_used_txdma_slot)
920 nsegs = BM_MAX_DMA_COMMANDS - 2 - sc->next_txdma_slot +
921 sc->first_used_txdma_slot; /* -2 for branch and indexing */
923 nsegs = sc->first_used_txdma_slot - sc->next_txdma_slot;
925 /* Remove one slot for the STOP/NOP terminator */
928 if (nsegs > BM_NTXSEGS)
931 /* Get a work queue entry. */
932 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) {
933 /* Ran out of descriptors. */
937 error = bus_dmamap_load_mbuf_sg(sc->sc_tdma_tag, txs->txs_dmamap,
938 *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
940 if (error == EFBIG) {
941 m = m_collapse(*m_head, M_DONTWAIT, nsegs);
949 error = bus_dmamap_load_mbuf_sg(sc->sc_tdma_tag,
950 txs->txs_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
956 } else if (error != 0)
965 txs->txs_ndescs = nsegs;
966 txs->txs_firstdesc = sc->next_txdma_slot;
968 for (i = 0; i < nsegs; i++) {
969 /* Loop back to the beginning if this is our last slot */
970 if (sc->next_txdma_slot == (BM_MAX_DMA_COMMANDS - 1))
971 branch_type = DBDMA_ALWAYS;
973 branch_type = DBDMA_NEVER;
976 txs->txs_lastdesc = sc->next_txdma_slot;
978 dbdma_insert_command(sc->sc_txdma, sc->next_txdma_slot++,
979 (i + 1 < nsegs) ? DBDMA_OUTPUT_MORE : DBDMA_OUTPUT_LAST,
980 0, segs[i].ds_addr, segs[i].ds_len,
981 (i + 1 < nsegs) ? DBDMA_NEVER : DBDMA_ALWAYS,
982 branch_type, DBDMA_NEVER, 0);
984 if (branch_type == DBDMA_ALWAYS)
985 sc->next_txdma_slot = 0;
988 /* We have a corner case where the STOP command is the last slot,
989 * but you can't branch in STOP commands. So add a NOP branch here
990 * and the STOP in slot 0. */
992 if (sc->next_txdma_slot == (BM_MAX_DMA_COMMANDS - 1)) {
993 dbdma_insert_branch(sc->sc_txdma, sc->next_txdma_slot, 0);
994 sc->next_txdma_slot = 0;
997 txs->txs_stopdesc = sc->next_txdma_slot;
998 dbdma_insert_stop(sc->sc_txdma, sc->next_txdma_slot++);
1000 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
1001 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
1002 txs->txs_mbuf = *m_head;
1008 bm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1010 struct bm_softc *sc = ifp->if_softc;
1011 struct ifreq *ifr = (struct ifreq *)data;
1019 if ((ifp->if_flags & IFF_UP) != 0) {
1020 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
1021 ((ifp->if_flags ^ sc->sc_ifpflags) &
1022 (IFF_ALLMULTI | IFF_PROMISC)) != 0)
1026 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1028 sc->sc_ifpflags = ifp->if_flags;
1038 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd);
1041 error = ether_ioctl(ifp, cmd, data);
1049 bm_setladrf(struct bm_softc *sc)
1051 struct ifnet *ifp = sc->sc_ifp;
1052 struct ifmultiaddr *inm;
1057 reg = BM_CRC_ENABLE | BM_REJECT_OWN_PKTS;
1059 /* Turn off RX MAC while we fiddle its settings */
1060 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
1061 while (CSR_READ_2(sc, BM_RX_CONFIG) & BM_ENABLE)
1064 if ((ifp->if_flags & IFF_PROMISC) != 0) {
1067 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
1071 reg = CSR_READ_2(sc, BM_RX_CONFIG);
1073 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
1077 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
1078 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
1080 /* Clear the hash table. */
1081 memset(hash, 0, sizeof(hash));
1083 if_maddr_rlock(ifp);
1084 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) {
1085 if (inm->ifma_addr->sa_family != AF_LINK)
1087 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1088 inm->ifma_addr), ETHER_ADDR_LEN);
1090 /* We just want the 6 most significant bits */
1093 /* Set the corresponding bit in the filter. */
1094 hash[crc >> 4] |= 1 << (crc & 0xf);
1096 if_maddr_runlock(ifp);
1099 /* Write out new hash table */
1100 CSR_WRITE_2(sc, BM_HASHTAB0, hash[0]);
1101 CSR_WRITE_2(sc, BM_HASHTAB1, hash[1]);
1102 CSR_WRITE_2(sc, BM_HASHTAB2, hash[2]);
1103 CSR_WRITE_2(sc, BM_HASHTAB3, hash[3]);
1105 /* And turn the RX MAC back on, this time with the hash bit set */
1106 reg |= BM_HASH_FILTER_ENABLE;
1107 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
1109 while (!(CSR_READ_2(sc, BM_RX_CONFIG) & BM_HASH_FILTER_ENABLE))
1112 reg = CSR_READ_2(sc, BM_RX_CONFIG);
1114 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
1120 struct bm_softc *sc = xsc;
1128 bm_chip_setup(struct bm_softc *sc)
1131 uint16_t *eaddr_sect;
1135 eaddr_sect = (uint16_t *)(sc->sc_enaddr);
1138 * Enable BMAC cell by opening and closing its OF node. This enables
1139 * the cell in macio as a side effect. We should probably directly
1140 * twiddle the FCR bits, but we lack a good interface for this at the
1144 OF_package_to_path(ofw_bus_get_node(sc->sc_dev), path, sizeof(path));
1145 bmac_ih = OF_open(path);
1146 if (bmac_ih == -1) {
1147 device_printf(sc->sc_dev,
1148 "Enabling BMAC cell failed! Hoping it's already active.\n");
1154 CSR_WRITE_2(sc, BM_RX_RESET, 0x0000);
1155 CSR_WRITE_2(sc, BM_TX_RESET, 0x0001);
1157 reg = CSR_READ_2(sc, BM_TX_RESET);
1158 } while (reg & 0x0001);
1160 /* Some random junk. OS X uses the system time. We use
1161 * the low 16 bits of the MAC address. */
1162 CSR_WRITE_2(sc, BM_TX_RANDSEED, eaddr_sect[2]);
1164 /* Enable transmit */
1165 reg = CSR_READ_2(sc, BM_TX_IFC);
1167 CSR_WRITE_2(sc, BM_TX_IFC, reg);
1169 CSR_READ_2(sc, BM_TX_PEAKCNT);
1173 bm_stop(struct bm_softc *sc)
1175 struct bm_txsoft *txs;
1178 /* Disable TX and RX MACs */
1179 reg = CSR_READ_2(sc, BM_TX_CONFIG);
1181 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
1183 reg = CSR_READ_2(sc, BM_RX_CONFIG);
1185 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
1189 /* Stop DMA engine */
1190 dbdma_stop(sc->sc_rxdma);
1191 dbdma_stop(sc->sc_txdma);
1192 sc->next_rxdma_slot = 0;
1193 sc->rxdma_loop_slot = 0;
1195 /* Disable interrupts */
1196 bm_disable_interrupts(sc);
1198 /* Don't worry about pending transmits anymore */
1199 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1200 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
1201 if (txs->txs_ndescs != 0) {
1202 bus_dmamap_sync(sc->sc_tdma_tag, txs->txs_dmamap,
1203 BUS_DMASYNC_POSTWRITE);
1204 bus_dmamap_unload(sc->sc_tdma_tag, txs->txs_dmamap);
1205 if (txs->txs_mbuf != NULL) {
1206 m_freem(txs->txs_mbuf);
1207 txs->txs_mbuf = NULL;
1210 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
1213 /* And we're down */
1214 sc->sc_ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1215 sc->sc_wdog_timer = 0;
1216 callout_stop(&sc->sc_tick_ch);
1220 bm_init_locked(struct bm_softc *sc)
1223 uint16_t *eaddr_sect;
1224 struct bm_rxsoft *rxs;
1227 eaddr_sect = (uint16_t *)(sc->sc_enaddr);
1229 /* Zero RX slot info and stop DMA */
1230 dbdma_stop(sc->sc_rxdma);
1231 dbdma_stop(sc->sc_txdma);
1232 sc->next_rxdma_slot = 0;
1233 sc->rxdma_loop_slot = 0;
1235 /* Initialize TX/RX DBDMA programs */
1236 dbdma_insert_stop(sc->sc_rxdma, 0);
1237 dbdma_insert_stop(sc->sc_txdma, 0);
1238 dbdma_set_current_cmd(sc->sc_rxdma, 0);
1239 dbdma_set_current_cmd(sc->sc_txdma, 0);
1241 sc->next_rxdma_slot = 0;
1242 sc->next_txdma_slot = 1;
1243 sc->first_used_txdma_slot = 0;
1245 for (i = 0; i < BM_MAX_RX_PACKETS; i++) {
1246 rxs = &sc->sc_rxsoft[i];
1247 rxs->dbdma_slot = i;
1249 if (rxs->rxs_mbuf == NULL) {
1250 bm_add_rxbuf(sc, i);
1252 if (rxs->rxs_mbuf == NULL) {
1253 /* If we can't add anymore, mark the problem */
1254 rxs->dbdma_slot = -1;
1260 bm_add_rxbuf_dma(sc, i);
1264 * Now terminate the RX ring buffer, and follow with the loop to
1267 dbdma_insert_stop(sc->sc_rxdma, i - 1);
1268 dbdma_insert_branch(sc->sc_rxdma, i, 0);
1269 sc->rxdma_loop_slot = i;
1271 /* Now add in the first element of the RX DMA chain */
1272 bm_add_rxbuf_dma(sc, 0);
1274 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_PREWRITE);
1275 dbdma_sync_commands(sc->sc_txdma, BUS_DMASYNC_PREWRITE);
1277 /* Zero collision counters */
1278 CSR_WRITE_2(sc, BM_TX_NCCNT, 0);
1279 CSR_WRITE_2(sc, BM_TX_FCCNT, 0);
1280 CSR_WRITE_2(sc, BM_TX_EXCNT, 0);
1281 CSR_WRITE_2(sc, BM_TX_LTCNT, 0);
1283 /* Zero receive counters */
1284 CSR_WRITE_2(sc, BM_RX_FRCNT, 0);
1285 CSR_WRITE_2(sc, BM_RX_LECNT, 0);
1286 CSR_WRITE_2(sc, BM_RX_AECNT, 0);
1287 CSR_WRITE_2(sc, BM_RX_FECNT, 0);
1288 CSR_WRITE_2(sc, BM_RXCV, 0);
1290 /* Prime transmit */
1291 CSR_WRITE_2(sc, BM_TX_THRESH, 0xff);
1293 CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0);
1294 CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0x0001);
1297 CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0);
1298 CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0x0001);
1300 /* Clear status reg */
1301 CSR_READ_2(sc, BM_STATUS);
1303 /* Zero hash filters */
1304 CSR_WRITE_2(sc, BM_HASHTAB0, 0);
1305 CSR_WRITE_2(sc, BM_HASHTAB1, 0);
1306 CSR_WRITE_2(sc, BM_HASHTAB2, 0);
1307 CSR_WRITE_2(sc, BM_HASHTAB3, 0);
1309 /* Write MAC address to chip */
1310 CSR_WRITE_2(sc, BM_MACADDR0, eaddr_sect[0]);
1311 CSR_WRITE_2(sc, BM_MACADDR1, eaddr_sect[1]);
1312 CSR_WRITE_2(sc, BM_MACADDR2, eaddr_sect[2]);
1314 /* Final receive engine setup */
1315 reg = BM_CRC_ENABLE | BM_REJECT_OWN_PKTS | BM_HASH_FILTER_ENABLE;
1316 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
1318 /* Now turn it all on! */
1319 dbdma_reset(sc->sc_rxdma);
1320 dbdma_reset(sc->sc_txdma);
1322 /* Enable RX and TX MACs. Setting the address filter has
1323 * the side effect of enabling the RX MAC. */
1326 reg = CSR_READ_2(sc, BM_TX_CONFIG);
1328 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
1331 * Enable interrupts, unwedge the controller with a dummy packet,
1332 * and nudge the DMA queue.
1334 bm_enable_interrupts(sc);
1336 dbdma_wake(sc->sc_rxdma); /* Nudge RXDMA */
1338 sc->sc_ifp->if_drv_flags |= IFF_DRV_RUNNING;
1339 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1340 sc->sc_ifpflags = sc->sc_ifp->if_flags;
1342 /* Resync PHY and MAC states */
1343 sc->sc_mii = device_get_softc(sc->sc_miibus);
1344 sc->sc_duplex = ~IFM_FDX;
1345 mii_mediachg(sc->sc_mii);
1347 /* Start the one second timer. */
1348 sc->sc_wdog_timer = 0;
1349 callout_reset(&sc->sc_tick_ch, hz, bm_tick, sc);
1355 struct bm_softc *sc = arg;
1357 /* Read error counters */
1358 sc->sc_ifp->if_collisions += CSR_READ_2(sc, BM_TX_NCCNT) +
1359 CSR_READ_2(sc, BM_TX_FCCNT) + CSR_READ_2(sc, BM_TX_EXCNT) +
1360 CSR_READ_2(sc, BM_TX_LTCNT);
1362 sc->sc_ifp->if_ierrors += CSR_READ_2(sc, BM_RX_LECNT) +
1363 CSR_READ_2(sc, BM_RX_AECNT) + CSR_READ_2(sc, BM_RX_FECNT);
1365 /* Zero collision counters */
1366 CSR_WRITE_2(sc, BM_TX_NCCNT, 0);
1367 CSR_WRITE_2(sc, BM_TX_FCCNT, 0);
1368 CSR_WRITE_2(sc, BM_TX_EXCNT, 0);
1369 CSR_WRITE_2(sc, BM_TX_LTCNT, 0);
1371 /* Zero receive counters */
1372 CSR_WRITE_2(sc, BM_RX_FRCNT, 0);
1373 CSR_WRITE_2(sc, BM_RX_LECNT, 0);
1374 CSR_WRITE_2(sc, BM_RX_AECNT, 0);
1375 CSR_WRITE_2(sc, BM_RX_FECNT, 0);
1376 CSR_WRITE_2(sc, BM_RXCV, 0);
1378 /* Check for link changes and run watchdog */
1379 mii_tick(sc->sc_mii);
1380 bm_miibus_statchg(sc->sc_dev);
1382 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) {
1383 callout_reset(&sc->sc_tick_ch, hz, bm_tick, sc);
1388 device_printf(sc->sc_dev, "device timeout\n");
1394 bm_add_rxbuf(struct bm_softc *sc, int idx)
1396 struct bm_rxsoft *rxs = &sc->sc_rxsoft[idx];
1398 bus_dma_segment_t segs[1];
1401 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1404 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
1406 if (rxs->rxs_mbuf != NULL) {
1407 bus_dmamap_sync(sc->sc_rdma_tag, rxs->rxs_dmamap,
1408 BUS_DMASYNC_POSTREAD);
1409 bus_dmamap_unload(sc->sc_rdma_tag, rxs->rxs_dmamap);
1412 error = bus_dmamap_load_mbuf_sg(sc->sc_rdma_tag, rxs->rxs_dmamap, m,
1413 segs, &nsegs, BUS_DMA_NOWAIT);
1415 device_printf(sc->sc_dev,
1416 "cannot load RS DMA map %d, error = %d\n", idx, error);
1420 /* If nsegs is wrong then the stack is corrupt. */
1422 ("%s: too many DMA segments (%d)", __func__, nsegs));
1424 rxs->segment = segs[0];
1426 bus_dmamap_sync(sc->sc_rdma_tag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD);
1432 bm_add_rxbuf_dma(struct bm_softc *sc, int idx)
1434 struct bm_rxsoft *rxs = &sc->sc_rxsoft[idx];
1436 dbdma_insert_command(sc->sc_rxdma, idx, DBDMA_INPUT_LAST, 0,
1437 rxs->segment.ds_addr, rxs->segment.ds_len, DBDMA_ALWAYS,
1438 DBDMA_NEVER, DBDMA_NEVER, 0);
1444 bm_enable_interrupts(struct bm_softc *sc)
1446 CSR_WRITE_2(sc, BM_INTR_DISABLE,
1447 (sc->sc_streaming) ? BM_INTR_NONE : BM_INTR_NORMAL);
1451 bm_disable_interrupts(struct bm_softc *sc)
1453 CSR_WRITE_2(sc, BM_INTR_DISABLE, BM_INTR_NONE);