2 * Broadcom NetXtreme-C/E network driver.
4 * Copyright (c) 2016 Broadcom, All Rights Reserved.
5 * The term Broadcom refers to Broadcom Limited and/or its subsidiaries
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
33 #include <sys/param.h>
34 #include <sys/socket.h>
35 #include <sys/sysctl.h>
36 #include <sys/taskqueue.h>
37 #include <sys/bitstring.h>
39 #include <machine/bus.h>
41 #include <net/ethernet.h>
43 #include <net/if_var.h>
44 #include <net/iflib.h>
46 #include "hsi_struct_def.h"
49 #define BROADCOM_VENDOR_ID 0x14E4
51 #define BCM57301 0x16c8
52 #define BCM57302 0x16c9
53 #define BCM57304 0x16ca
54 #define BCM57311 0x16ce
55 #define BCM57312 0x16cf
56 #define BCM57314 0x16df
57 #define BCM57402 0x16d0
58 #define BCM57402_NPAR 0x16d4
59 #define BCM57404 0x16d1
60 #define BCM57404_NPAR 0x16e7
61 #define BCM57406 0x16d2
62 #define BCM57406_NPAR 0x16e8
63 #define BCM57407 0x16d5
64 #define BCM57407_NPAR 0x16ea
65 #define BCM57407_SFP 0x16e9
66 #define BCM57412 0x16d6
67 #define BCM57412_NPAR1 0x16de
68 #define BCM57412_NPAR2 0x16eb
69 #define BCM57414 0x16d7
70 #define BCM57414_NPAR1 0x16ec
71 #define BCM57414_NPAR2 0x16ed
72 #define BCM57416 0x16d8
73 #define BCM57416_NPAR1 0x16ee
74 #define BCM57416_NPAR2 0x16ef
75 #define BCM57416_SFP 0x16e3
76 #define BCM57417 0x16d9
77 #define BCM57417_NPAR1 0x16c0
78 #define BCM57417_NPAR2 0x16cc
79 #define BCM57417_SFP 0x16e2
80 #define BCM57454 0x1614
81 #define BCM58700 0x16cd
82 #define BCM57508 0x1750
83 #define BCM57504 0x1751
84 #define BCM57502 0x1752
85 #define NETXTREME_C_VF1 0x16cb
86 #define NETXTREME_C_VF2 0x16e1
87 #define NETXTREME_C_VF3 0x16e5
88 #define NETXTREME_E_VF1 0x16c1
89 #define NETXTREME_E_VF2 0x16d3
90 #define NETXTREME_E_VF3 0x16dc
92 /* Maximum numbers of RX and TX descriptors. iflib requires this to be a power
93 * of two. The hardware has no particular limitation. */
94 #define BNXT_MAX_RXD ((INT32_MAX >> 1) + 1)
95 #define BNXT_MAX_TXD ((INT32_MAX >> 1) + 1)
97 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
98 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
99 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
101 #define BNXT_MAX_MTU 9000
103 #define BNXT_RSS_HASH_TYPE_TCPV4 0
104 #define BNXT_RSS_HASH_TYPE_UDPV4 1
105 #define BNXT_RSS_HASH_TYPE_IPV4 2
106 #define BNXT_RSS_HASH_TYPE_TCPV6 3
107 #define BNXT_RSS_HASH_TYPE_UDPV6 4
108 #define BNXT_RSS_HASH_TYPE_IPV6 5
109 #define BNXT_GET_RSS_PROFILE_ID(rss_hash_type) ((rss_hash_type >> 1) & 0x1F)
111 #define BNXT_NO_MORE_WOL_FILTERS 0xFFFF
112 #define bnxt_wol_supported(softc) (!((softc)->flags & BNXT_FLAG_VF) && \
113 ((softc)->flags & BNXT_FLAG_WOL_CAP ))
115 /* 64-bit doorbell */
116 #define DBR_INDEX_MASK 0x0000000000ffffffULL
117 #define DBR_PI_LO_MASK 0xff000000UL
118 #define DBR_PI_LO_SFT 24
119 #define DBR_XID_MASK 0x000fffff00000000ULL
120 #define DBR_XID_SFT 32
121 #define DBR_PI_HI_MASK 0xf0000000000000ULL
122 #define DBR_PI_HI_SFT 52
123 #define DBR_PATH_L2 (0x1ULL << 56)
124 #define DBR_VALID (0x1ULL << 58)
125 #define DBR_TYPE_SQ (0x0ULL << 60)
126 #define DBR_TYPE_RQ (0x1ULL << 60)
127 #define DBR_TYPE_SRQ (0x2ULL << 60)
128 #define DBR_TYPE_SRQ_ARM (0x3ULL << 60)
129 #define DBR_TYPE_CQ (0x4ULL << 60)
130 #define DBR_TYPE_CQ_ARMSE (0x5ULL << 60)
131 #define DBR_TYPE_CQ_ARMALL (0x6ULL << 60)
132 #define DBR_TYPE_CQ_ARMENA (0x7ULL << 60)
133 #define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60)
134 #define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60)
135 #define DBR_TYPE_NQ (0xaULL << 60)
136 #define DBR_TYPE_NQ_ARM (0xbULL << 60)
137 #define DBR_TYPE_PUSH_START (0xcULL << 60)
138 #define DBR_TYPE_PUSH_END (0xdULL << 60)
139 #define DBR_TYPE_NULL (0xfULL << 60)
141 #define BNXT_MAX_NUM_QUEUES 32
143 /* Completion related defines */
144 #define CMP_VALID(cmp, v_bit) \
145 ((!!(((struct cmpl_base *)(cmp))->info3_v & htole32(CMPL_BASE_V))) == !!(v_bit) )
147 /* Chip class phase 5 */
148 #define BNXT_CHIP_P5(sc) ((softc->flags & BNXT_FLAG_CHIP_P5))
150 #define DB_PF_OFFSET_P5 0x10000
151 #define NQ_VALID(cmp, v_bit) \
152 ((!!(((nq_cn_t *)(cmp))->v & htole32(NQ_CN_V))) == !!(v_bit) )
155 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
158 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
161 #define NEXT_CP_CONS_V(ring, cons, v_bit) do { \
162 if (__predict_false(++(cons) == (ring)->ring_size)) \
163 ((cons) = 0, (v_bit) = !v_bit); \
166 #define RING_NEXT(ring, idx) (__predict_false(idx + 1 == (ring)->ring_size) ? \
169 #define CMPL_PREFETCH_NEXT(cpr, idx) \
170 __builtin_prefetch(&((struct cmpl_base *)(cpr)->ring.vaddr)[((idx) +\
171 (CACHE_LINE_SIZE / sizeof(struct cmpl_base))) & \
172 ((cpr)->ring.ring_size - 1)])
175 #define BNXT_HWRM_LOCK_INIT(_softc, _name) \
176 mtx_init(&(_softc)->hwrm_lock, _name, "BNXT HWRM Lock", MTX_DEF)
177 #define BNXT_HWRM_LOCK(_softc) mtx_lock(&(_softc)->hwrm_lock)
178 #define BNXT_HWRM_UNLOCK(_softc) mtx_unlock(&(_softc)->hwrm_lock)
179 #define BNXT_HWRM_LOCK_DESTROY(_softc) mtx_destroy(&(_softc)->hwrm_lock)
180 #define BNXT_HWRM_LOCK_ASSERT(_softc) mtx_assert(&(_softc)->hwrm_lock, \
182 #define BNXT_IS_FLOW_CTRL_CHANGED(link_info) \
183 ((link_info->last_flow_ctrl.tx != link_info->flow_ctrl.tx) || \
184 (link_info->last_flow_ctrl.rx != link_info->flow_ctrl.rx) || \
185 (link_info->last_flow_ctrl.autoneg != link_info->flow_ctrl.autoneg))
188 #define BNXT_TSO_SIZE UINT16_MAX
190 #define min_t(type, x, y) ({ \
193 __min1 < __min2 ? __min1 : __min2; })
195 #define max_t(type, x, y) ({ \
198 __max1 > __max2 ? __max1 : __max2; })
200 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
202 #define BNXT_IFMEDIA_ADD(supported, fw_speed, ifm_speed) do { \
203 if ((supported) & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_ ## fw_speed) \
204 ifmedia_add(softc->media, IFM_ETHER | (ifm_speed), 0, NULL); \
207 #define BNXT_MIN_FRAME_SIZE 52 /* Frames must be padded to this size for some A0 chips */
209 extern const char bnxt_driver_version[];
210 typedef void (*bnxt_doorbell_tx)(void *, uint16_t idx);
211 typedef void (*bnxt_doorbell_rx)(void *, uint16_t idx);
212 typedef void (*bnxt_doorbell_rx_cq)(void *, bool);
213 typedef void (*bnxt_doorbell_tx_cq)(void *, bool);
214 typedef void (*bnxt_doorbell_nq)(void *, bool);
216 typedef struct bnxt_doorbell_ops {
217 bnxt_doorbell_tx bnxt_db_tx;
218 bnxt_doorbell_rx bnxt_db_rx;
219 bnxt_doorbell_rx_cq bnxt_db_rx_cq;
220 bnxt_doorbell_tx_cq bnxt_db_tx_cq;
221 bnxt_doorbell_nq bnxt_db_nq;
222 } bnxt_dooorbell_ops_t;
224 enum bnxt_nvm_directory_type {
225 BNX_DIR_TYPE_UNUSED = 0,
226 BNX_DIR_TYPE_PKG_LOG = 1,
227 BNX_DIR_TYPE_UPDATE = 2,
228 BNX_DIR_TYPE_CHIMP_PATCH = 3,
229 BNX_DIR_TYPE_BOOTCODE = 4,
230 BNX_DIR_TYPE_VPD = 5,
231 BNX_DIR_TYPE_EXP_ROM_MBA = 6,
232 BNX_DIR_TYPE_AVS = 7,
233 BNX_DIR_TYPE_PCIE = 8,
234 BNX_DIR_TYPE_PORT_MACRO = 9,
235 BNX_DIR_TYPE_APE_FW = 10,
236 BNX_DIR_TYPE_APE_PATCH = 11,
237 BNX_DIR_TYPE_KONG_FW = 12,
238 BNX_DIR_TYPE_KONG_PATCH = 13,
239 BNX_DIR_TYPE_BONO_FW = 14,
240 BNX_DIR_TYPE_BONO_PATCH = 15,
241 BNX_DIR_TYPE_TANG_FW = 16,
242 BNX_DIR_TYPE_TANG_PATCH = 17,
243 BNX_DIR_TYPE_BOOTCODE_2 = 18,
244 BNX_DIR_TYPE_CCM = 19,
245 BNX_DIR_TYPE_PCI_CFG = 20,
246 BNX_DIR_TYPE_TSCF_UCODE = 21,
247 BNX_DIR_TYPE_ISCSI_BOOT = 22,
248 BNX_DIR_TYPE_ISCSI_BOOT_IPV6 = 24,
249 BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6 = 25,
250 BNX_DIR_TYPE_ISCSI_BOOT_CFG6 = 26,
251 BNX_DIR_TYPE_EXT_PHY = 27,
252 BNX_DIR_TYPE_SHARED_CFG = 40,
253 BNX_DIR_TYPE_PORT_CFG = 41,
254 BNX_DIR_TYPE_FUNC_CFG = 42,
255 BNX_DIR_TYPE_MGMT_CFG = 48,
256 BNX_DIR_TYPE_MGMT_DATA = 49,
257 BNX_DIR_TYPE_MGMT_WEB_DATA = 50,
258 BNX_DIR_TYPE_MGMT_WEB_META = 51,
259 BNX_DIR_TYPE_MGMT_EVENT_LOG = 52,
260 BNX_DIR_TYPE_MGMT_AUDIT_LOG = 53
263 enum bnxnvm_pkglog_field_index {
264 BNX_PKG_LOG_FIELD_IDX_INSTALLED_TIMESTAMP = 0,
265 BNX_PKG_LOG_FIELD_IDX_PKG_DESCRIPTION = 1,
266 BNX_PKG_LOG_FIELD_IDX_PKG_VERSION = 2,
267 BNX_PKG_LOG_FIELD_IDX_PKG_TIMESTAMP = 3,
268 BNX_PKG_LOG_FIELD_IDX_PKG_CHECKSUM = 4,
269 BNX_PKG_LOG_FIELD_IDX_INSTALLED_ITEMS = 5,
270 BNX_PKG_LOG_FIELD_IDX_INSTALLED_MASK = 6
273 #define BNX_DIR_ORDINAL_FIRST 0
274 #define BNX_DIR_EXT_NONE 0
276 struct bnxt_bar_info {
277 struct resource *res;
279 bus_space_handle_t handle;
284 struct bnxt_flow_ctrl {
290 struct bnxt_link_info {
294 uint8_t phy_link_status;
298 uint8_t last_link_up;
301 struct bnxt_flow_ctrl flow_ctrl;
302 struct bnxt_flow_ctrl last_flow_ctrl;
303 uint8_t duplex_setting;
305 #define PHY_VER_LEN 3
306 uint8_t phy_ver[PHY_VER_LEN];
309 uint16_t support_speeds;
310 uint16_t auto_link_speeds;
311 uint16_t auto_link_speed;
312 uint16_t force_link_speed;
313 uint32_t preemphasis;
315 /* copy of requested setting */
317 #define BNXT_AUTONEG_SPEED 1
318 #define BNXT_AUTONEG_FLOW_CTRL 2
320 uint16_t req_link_speed;
330 struct bnxt_cos_queue {
335 struct bnxt_func_info {
337 uint8_t mac_addr[ETHER_ADDR_LEN];
338 uint16_t max_rsscos_ctxs;
339 uint16_t max_cp_rings;
340 uint16_t max_tx_rings;
341 uint16_t max_rx_rings;
342 uint16_t max_hw_ring_grps;
344 uint16_t max_l2_ctxs;
346 uint16_t max_stat_ctxs;
349 struct bnxt_pf_info {
350 #define BNXT_FIRST_PF_FID 1
351 #define BNXT_FIRST_VF_FID 128
353 uint32_t first_vf_id;
356 uint32_t max_encap_records;
357 uint32_t max_decap_records;
358 uint32_t max_tx_em_flows;
359 uint32_t max_tx_wm_flows;
360 uint32_t max_rx_em_flows;
361 uint32_t max_rx_wm_flows;
362 unsigned long *vf_event_bmap;
363 uint16_t hwrm_cmd_req_pages;
364 void *hwrm_cmd_req_addr[4];
365 bus_addr_t hwrm_cmd_req_dma_addr[4];
368 struct bnxt_vf_info {
370 uint8_t mac_addr[ETHER_ADDR_LEN];
371 uint16_t max_rsscos_ctxs;
372 uint16_t max_cp_rings;
373 uint16_t max_tx_rings;
374 uint16_t max_rx_rings;
375 uint16_t max_hw_ring_grps;
376 uint16_t max_l2_ctxs;
379 uint16_t max_stat_ctxs;
381 #define BNXT_VF_QOS 0x1
382 #define BNXT_VF_SPOOFCHK 0x2
383 #define BNXT_VF_LINK_FORCED 0x4
384 #define BNXT_VF_LINK_UP 0x8
386 uint32_t func_flags; /* func cfg flags */
387 uint32_t min_tx_rate;
388 uint32_t max_tx_rate;
389 void *hwrm_cmd_req_addr;
390 bus_addr_t hwrm_cmd_req_dma_addr;
393 #define BNXT_PF(softc) (!((softc)->flags & BNXT_FLAG_VF))
394 #define BNXT_VF(softc) ((softc)->flags & BNXT_FLAG_VF)
396 struct bnxt_vlan_tag {
397 SLIST_ENTRY(bnxt_vlan_tag) next;
402 struct bnxt_vnic_info {
404 uint16_t def_ring_grp;
410 struct iflib_dma_info mc_list;
412 #define BNXT_MAX_MC_ADDRS 16
415 #define BNXT_VNIC_FLAG_DEFAULT 0x01
416 #define BNXT_VNIC_FLAG_BD_STALL 0x02
417 #define BNXT_VNIC_FLAG_VLAN_STRIP 0x04
422 uint32_t rss_hash_type;
423 uint8_t rss_hash_key[HW_HASH_KEY_SIZE];
424 struct iflib_dma_info rss_hash_key_tbl;
425 struct iflib_dma_info rss_grp_tbl;
426 SLIST_HEAD(vlan_head, bnxt_vlan_tag) vlan_tags;
427 struct iflib_dma_info vlan_tag_list;
430 struct bnxt_grp_info {
440 vm_offset_t doorbell;
442 struct bnxt_softc *softc;
443 uint32_t ring_size; /* Must be a power of two */
444 uint16_t id; /* Logical ID */
447 struct bnxt_full_tpa_start *tpa_start;
450 struct bnxt_cp_ring {
451 struct bnxt_ring ring;
454 bool v_bit; /* Value of valid bit */
455 struct ctx_hw_stats *stats;
456 uint32_t stats_ctx_id;
457 uint32_t last_idx; /* Used by RX rings only
458 * set to the last read pidx
463 struct bnxt_full_tpa_start {
464 struct rx_tpa_start_cmpl low;
465 struct rx_tpa_start_cmpl_hi high;
468 /* All the version information for the part */
469 #define BNXT_VERSTR_SIZE (3*3+2+1) /* ie: "255.255.255\0" */
470 #define BNXT_NAME_SIZE 17
471 #define FW_VER_STR_LEN 32
472 #define BC_HWRM_STR_LEN 21
473 struct bnxt_ver_info {
474 uint8_t hwrm_if_major;
475 uint8_t hwrm_if_minor;
476 uint8_t hwrm_if_update;
477 char hwrm_if_ver[BNXT_VERSTR_SIZE];
478 char driver_hwrm_if_ver[BNXT_VERSTR_SIZE];
479 char hwrm_fw_ver[BNXT_VERSTR_SIZE];
480 char mgmt_fw_ver[BNXT_VERSTR_SIZE];
481 char netctrl_fw_ver[BNXT_VERSTR_SIZE];
482 char roce_fw_ver[BNXT_VERSTR_SIZE];
483 char fw_ver_str[FW_VER_STR_LEN];
484 char phy_ver[BNXT_VERSTR_SIZE];
487 char hwrm_fw_name[BNXT_NAME_SIZE];
488 char mgmt_fw_name[BNXT_NAME_SIZE];
489 char netctrl_fw_name[BNXT_NAME_SIZE];
490 char roce_fw_name[BNXT_NAME_SIZE];
491 char phy_vendor[BNXT_NAME_SIZE];
492 char phy_partnumber[BNXT_NAME_SIZE];
497 uint8_t chip_bond_id;
500 uint8_t hwrm_min_major;
501 uint8_t hwrm_min_minor;
502 uint8_t hwrm_min_update;
504 struct sysctl_ctx_list ver_ctx;
505 struct sysctl_oid *ver_oid;
508 struct bnxt_nvram_info {
511 uint32_t sector_size;
513 uint32_t reserved_size;
514 uint32_t available_size;
516 struct sysctl_ctx_list nvm_ctx;
517 struct sysctl_oid *nvm_oid;
520 struct bnxt_func_qcfg {
521 uint16_t alloc_completion_rings;
522 uint16_t alloc_tx_rings;
523 uint16_t alloc_rx_rings;
524 uint16_t alloc_vnics;
529 uint16_t is_mode_gro;
530 uint16_t max_agg_segs;
532 uint32_t min_agg_len;
535 /* The hardware supports certain page sizes. Use the supported page sizes
536 * to allocate the rings.
538 #if (PAGE_SHIFT < 12)
539 #define BNXT_PAGE_SHIFT 12
540 #elif (PAGE_SHIFT <= 13)
541 #define BNXT_PAGE_SHIFT PAGE_SHIFT
542 #elif (PAGE_SHIFT < 16)
543 #define BNXT_PAGE_SHIFT 13
545 #define BNXT_PAGE_SHIFT 16
548 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
550 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
551 #define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES)
552 struct bnxt_ring_mem_info {
556 #define BNXT_RMEM_VALID_PTE_FLAG 1
557 #define BNXT_RMEM_RING_PTE_FLAG 2
558 #define BNXT_RMEM_USE_FULL_PAGE_FLAG 4
561 struct iflib_dma_info *pg_arr;
562 struct iflib_dma_info pg_tbl;
567 struct bnxt_ctx_pg_info {
570 struct iflib_dma_info ctx_arr[MAX_CTX_PAGES];
571 struct bnxt_ring_mem_info ring_mem;
572 struct bnxt_ctx_pg_info **ctx_pg_tbl;
575 struct bnxt_ctx_mem_info {
576 uint32_t qp_max_entries;
577 uint16_t qp_min_qp1_entries;
578 uint16_t qp_max_l2_entries;
579 uint16_t qp_entry_size;
580 uint16_t srq_max_l2_entries;
581 uint32_t srq_max_entries;
582 uint16_t srq_entry_size;
583 uint16_t cq_max_l2_entries;
584 uint32_t cq_max_entries;
585 uint16_t cq_entry_size;
586 uint16_t vnic_max_vnic_entries;
587 uint16_t vnic_max_ring_table_entries;
588 uint16_t vnic_entry_size;
589 uint32_t stat_max_entries;
590 uint16_t stat_entry_size;
591 uint16_t tqm_entry_size;
592 uint32_t tqm_min_entries_per_ring;
593 uint32_t tqm_max_entries_per_ring;
594 uint32_t mrav_max_entries;
595 uint16_t mrav_entry_size;
596 uint16_t tim_entry_size;
597 uint32_t tim_max_entries;
598 uint8_t tqm_entries_multiple;
599 uint8_t ctx_kind_initializer;
602 #define BNXT_CTX_FLAG_INITED 0x01
604 struct bnxt_ctx_pg_info qp_mem;
605 struct bnxt_ctx_pg_info srq_mem;
606 struct bnxt_ctx_pg_info cq_mem;
607 struct bnxt_ctx_pg_info vnic_mem;
608 struct bnxt_ctx_pg_info stat_mem;
609 struct bnxt_ctx_pg_info mrav_mem;
610 struct bnxt_ctx_pg_info tim_mem;
611 struct bnxt_ctx_pg_info *tqm_mem[9];
614 struct bnxt_hw_resc {
615 uint16_t min_rsscos_ctxs;
616 uint16_t max_rsscos_ctxs;
617 uint16_t min_cp_rings;
618 uint16_t max_cp_rings;
619 uint16_t resv_cp_rings;
620 uint16_t min_tx_rings;
621 uint16_t max_tx_rings;
622 uint16_t resv_tx_rings;
623 uint16_t max_tx_sch_inputs;
624 uint16_t min_rx_rings;
625 uint16_t max_rx_rings;
626 uint16_t resv_rx_rings;
627 uint16_t min_hw_ring_grps;
628 uint16_t max_hw_ring_grps;
629 uint16_t resv_hw_ring_grps;
630 uint16_t min_l2_ctxs;
631 uint16_t max_l2_ctxs;
635 uint16_t min_stat_ctxs;
636 uint16_t max_stat_ctxs;
637 uint16_t resv_stat_ctxs;
643 #define BNXT_LLQ(q_profile) \
644 ((q_profile) == HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE)
645 #define BNXT_CNPQ(q_profile) \
646 ((q_profile) == HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP)
648 #define BNXT_HWRM_MAX_REQ_LEN (softc->hwrm_max_req_len)
650 struct bnxt_softc_list {
651 SLIST_ENTRY(bnxt_softc_list) next;
652 struct bnxt_softc *softc;
658 if_softc_ctx_t scctx;
659 if_shared_ctx_t sctx;
665 struct ifmedia *media;
666 struct bnxt_ctx_mem_info *ctx_mem;
667 struct bnxt_hw_resc hw_resc;
668 struct bnxt_softc_list list;
670 struct bnxt_bar_info hwrm_bar;
671 struct bnxt_bar_info doorbell_bar;
672 struct bnxt_link_info link_info;
673 #define BNXT_FLAG_VF 0x0001
674 #define BNXT_FLAG_NPAR 0x0002
675 #define BNXT_FLAG_WOL_CAP 0x0004
676 #define BNXT_FLAG_SHORT_CMD 0x0008
677 #define BNXT_FLAG_FW_CAP_NEW_RM 0x0010
678 #define BNXT_FLAG_CHIP_P5 0x0020
679 #define BNXT_FLAG_TPA 0x0040
681 #define BNXT_STATE_LINK_CHANGE (0)
682 #define BNXT_STATE_MAX (BNXT_STATE_LINK_CHANGE + 1)
686 struct bnxt_func_info func;
687 struct bnxt_func_qcfg fn_qcfg;
688 struct bnxt_pf_info pf;
689 struct bnxt_vf_info vf;
691 uint16_t hwrm_cmd_seq;
692 uint32_t hwrm_cmd_timeo; /* milliseconds */
693 struct iflib_dma_info hwrm_cmd_resp;
694 struct iflib_dma_info hwrm_short_cmd_req_addr;
695 /* Interrupt info for HWRM */
697 struct mtx hwrm_lock;
698 uint16_t hwrm_max_req_len;
699 uint16_t hwrm_max_ext_req_len;
700 uint32_t hwrm_spec_code;
702 #define BNXT_MAX_COS_QUEUE 8
704 uint8_t max_lltc; /* lossless TCs */
705 struct bnxt_cos_queue q_info[BNXT_MAX_COS_QUEUE];
706 uint8_t tc_to_qidx[BNXT_MAX_COS_QUEUE];
707 uint8_t q_ids[BNXT_MAX_COS_QUEUE];
710 uint64_t admin_ticks;
711 struct iflib_dma_info hw_rx_port_stats;
712 struct iflib_dma_info hw_tx_port_stats;
713 struct rx_port_stats *rx_port_stats;
714 struct tx_port_stats *tx_port_stats;
718 struct bnxt_cp_ring *nq_rings;
720 struct bnxt_ring *tx_rings;
721 struct bnxt_cp_ring *tx_cp_rings;
722 struct iflib_dma_info tx_stats[BNXT_MAX_NUM_QUEUES];
725 struct bnxt_vnic_info vnic_info;
726 struct bnxt_ring *ag_rings;
727 struct bnxt_ring *rx_rings;
728 struct bnxt_cp_ring *rx_cp_rings;
729 struct bnxt_grp_info *grp_info;
730 struct iflib_dma_info rx_stats[BNXT_MAX_NUM_QUEUES];
732 uint16_t rx_buf_size;
734 struct bnxt_cp_ring def_cp_ring;
735 struct bnxt_cp_ring def_nq_ring;
736 struct iflib_dma_info def_cp_ring_mem;
737 struct iflib_dma_info def_nq_ring_mem;
738 struct grouptask def_cp_task;
739 struct bnxt_doorbell_ops db_ops;
741 struct sysctl_ctx_list hw_stats;
742 struct sysctl_oid *hw_stats_oid;
743 struct sysctl_ctx_list hw_lro_ctx;
744 struct sysctl_oid *hw_lro_oid;
745 struct sysctl_ctx_list flow_ctrl_ctx;
746 struct sysctl_oid *flow_ctrl_oid;
748 struct bnxt_ver_info *ver_info;
749 struct bnxt_nvram_info *nvm_info;
752 struct bnxt_hw_lro hw_lro;
753 uint8_t wol_filter_id;
754 uint16_t rx_coal_usecs;
755 uint16_t rx_coal_usecs_irq;
756 uint16_t rx_coal_frames;
757 uint16_t rx_coal_frames_irq;
758 uint16_t tx_coal_usecs;
759 uint16_t tx_coal_usecs_irq;
760 uint16_t tx_coal_frames;
761 uint16_t tx_coal_frames_irq;
763 #define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2)
764 #define BNXT_DEF_STATS_COAL_TICKS 1000000
765 #define BNXT_MIN_STATS_COAL_TICKS 250000
766 #define BNXT_MAX_STATS_COAL_TICKS 1000000
770 struct bnxt_filter_info {
771 STAILQ_ENTRY(bnxt_filter_info) next;
772 uint64_t fw_l2_filter_id;
773 #define INVALID_MAC_INDEX ((uint16_t)-1)
776 /* Filter Characteristics */
779 uint8_t l2_addr[ETHER_ADDR_LEN];
780 uint8_t l2_addr_mask[ETHER_ADDR_LEN];
782 uint16_t l2_ovlan_mask;
784 uint16_t l2_ivlan_mask;
785 uint8_t t_l2_addr[ETHER_ADDR_LEN];
786 uint8_t t_l2_addr_mask[ETHER_ADDR_LEN];
788 uint16_t t_l2_ovlan_mask;
790 uint16_t t_l2_ivlan_mask;
792 uint16_t mirror_vnic_id;
795 uint64_t l2_filter_id_hint;
798 /* Function declarations */
799 void bnxt_report_link(struct bnxt_softc *softc);
800 bool bnxt_check_hwrm_version(struct bnxt_softc *softc);
801 struct bnxt_softc *bnxt_find_dev(uint32_t domain, uint32_t bus, uint32_t dev_fn, char *name);