4 * Copyright (c) 2016 Broadcom, All Rights Reserved.
5 * The term Broadcom refers to Broadcom Limited and/or its subsidiaries
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 /****************************************************************************
35 * Description: Definition of HSI data structures
37 * Date: 08/31/17 17:55:46
39 * Note: This file is scripted generated by hsi_decode.py.
40 * DO NOT modify this file manually !!!!
42 ****************************************************************************/
43 #ifndef _HSI_STRUCT_DEF_EXTERNAL_H_
44 #define _HSI_STRUCT_DEF_EXTERNAL_H_
45 /* HSI and HWRM Specification 1.8.1 */
46 #define HWRM_VERSION_MAJOR 1
47 #define HWRM_VERSION_MINOR 8
48 #define HWRM_VERSION_UPDATE 1
50 #define HWRM_VERSION_RSVD 7
52 #define HWRM_VERSION_STR "1.8.1.7"
54 * Following is the signature for HWRM message field that indicates not
55 * applicable (All F's). Need to cast it the size of the field if needed.
57 #define HWRM_NA_SIGNATURE ((uint32_t)(-1))
58 #define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */
59 #define HWRM_MAX_RESP_LEN (272) /* hwrm_selftest_qlist */
60 #define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */
61 #define HW_HASH_KEY_SIZE 40
62 #define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */
63 #define ROCE_SP_HSI_VERSION_MAJOR 1
64 #define ROCE_SP_HSI_VERSION_MINOR 8
65 #define ROCE_SP_HSI_VERSION_UPDATE 1
67 #define ROCE_SP_HSI_VERSION_STR "1.8.1"
69 * Following is the signature for ROCE_SP_HSI message field that indicates not
70 * applicable (All F's). Need to cast it the size of the field if needed.
72 #define ROCE_SP_HSI_NA_SIGNATURE ((uint32_t)(-1))
74 * Note: The Host Software Interface (HSI) and Hardware Resource Manager (HWRM)
75 * specification describes the data structures used in Ethernet packet or RDMA
76 * message data transfers as well as an abstract interface for managing Ethernet
77 * NIC hardware resources.
79 /* Ethernet Data path Host Structures */
81 * Description: The following three sections document the host structures used
82 * between device and software drivers for communicating Ethernet packets.
84 /* BD Ring Structures */
86 * Description: This structure is used to inform the NIC of a location for and
87 * an aggregation buffer that will be used for packet data that is received. An
88 * aggregation buffer creates a different kind of completion operation for a
89 * packet where a variable number of BDs may be used to place the packet in the
90 * host. RX Rings that have aggregation buffers are known as aggregation rings
91 * and must contain only aggregation buffers.
94 * Note: BD Ring structures are written by the driver to TX Rings and RX Rings
95 * to indicate to the chip there is more buffer space in the host that needs to
96 * be transmitted or is available for receive data.
98 /* BD Base (8 bytes) */
102 /* This value identifies the type of buffer descriptor. */
103 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
104 #define BD_BASE_TYPE_SFT 0
106 * Indicates that this BD is 16B long and is used for normal L2
107 * packet transmission.
109 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
111 * Indicates that this BD is 1BB long and is an empty TX BD. Not
112 * valid for use by the driver.
114 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
116 * Indicates that this BD is 16B long and is an RX Producer (ie.
117 * empty) buffer descriptor.
119 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
121 * Indicates that this BD is 16B long and is an RX Producer
124 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
126 * Indicates that this BD is 16B long and is an RX Producer
127 * Assembly Buffer Descriptor.
129 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
131 * Indicates that this BD is 32B long and is used for normal L2
132 * packet transmission.
134 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
136 } __attribute__((packed));
138 /* Short TX BD (16 bytes) */
143 * All bits in this field must be valid on the first BD of a packet.
144 * Only the packet_end bit must be valid for the remaining BDs of a
147 /* This value identifies the type of buffer descriptor. */
148 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
149 #define TX_BD_SHORT_TYPE_SFT 0
151 * Indicates that this BD is 16B long and is used for normal L2
152 * packet transmission.
154 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
156 * If set to 1, the packet ends with the data in the buffer pointed to
157 * by this descriptor. This flag must be valid on every BD.
159 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
161 * If set to 1, the device will not generate a completion for this
162 * transmit packet unless there is an error in it's processing. If this
163 * bit is set to 0, then the packet will be completed normally. This bit
164 * must be valid only on the first BD of a packet.
166 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
168 * This value indicates how many 16B BD locations are consumed in the
169 * ring by this packet. A value of 1 indicates that this BD is the only
170 * BD (and that the it is a short BD). A value of 3 indicates either 3
171 * short BDs or 1 long BD and one short BD in the packet. A value of 0
172 * indicates that there are 32 BD locations in the packet (the maximum).
173 * This field is valid only on the first BD of a packet.
175 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
176 #define TX_BD_SHORT_FLAGS_BD_CNT_SFT 8
178 * This value is a hint for the length of the entire packet. It is used
179 * by the chip to optimize internal processing. The packet will be
180 * dropped if the hint is too short. This field is valid only on the
181 * first BD of a packet.
183 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
184 #define TX_BD_SHORT_FLAGS_LHINT_SFT 13
185 /* indicates packet length < 512B */
186 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
187 /* indicates 512 <= packet length < 1KB */
188 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
189 /* indicates 1KB <= packet length < 2KB */
190 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
191 /* indicates packet length >= 2KB */
192 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
193 #define TX_BD_SHORT_FLAGS_LHINT_LAST TX_BD_SHORT_FLAGS_LHINT_GTE2K
195 * If set to 1, the device immediately updates the Send Consumer Index
196 * after the buffer associated with this descriptor has been transferred
197 * via DMA to NIC memory from host memory. An interrupt may or may not
198 * be generated according to the state of the interrupt avoidance
199 * mechanisms. If this bit is set to 0, then the Consumer Index is only
200 * updated as soon as one of the host interrupt coalescing conditions
201 * has been met. This bit must be valid on the first BD of a packet.
203 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
205 * All bits in this field must be valid on the first BD of a packet.
206 * Only the packet_end bit must be valid for the remaining BDs of a
209 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
210 #define TX_BD_SHORT_FLAGS_SFT 6
213 * This is the length of the host physical buffer this BD describes in
214 * bytes. This field must be valid on all BDs of a packet.
218 * The opaque data field is pass through to the completion and can be
219 * used for any data that the driver wants to associate with the
220 * transmit BD. This field must be valid on the first BD of a packet.
224 * This is the host physical address for the portion of the packet
225 * described by this TX BD. This value must be valid on all BDs of a
228 } __attribute__((packed));
230 /* Long TX BD (32 bytes split to 2 16-byte struct) */
235 * All bits in this field must be valid on the first BD of a packet.
236 * Only the packet_end bit must be valid for the remaining BDs of a
239 /* This value identifies the type of buffer descriptor. */
240 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
241 #define TX_BD_LONG_TYPE_SFT 0
243 * Indicates that this BD is 32B long and is used for normal L2
244 * packet transmission.
246 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
248 * If set to 1, the packet ends with the data in the buffer pointed to
249 * by this descriptor. This flag must be valid on every BD.
251 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
253 * If set to 1, the device will not generate a completion for this
254 * transmit packet unless there is an error in it's processing. If this
255 * bit is set to 0, then the packet will be completed normally. This bit
256 * must be valid only on the first BD of a packet.
258 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
260 * This value indicates how many 16B BD locations are consumed in the
261 * ring by this packet. A value of 1 indicates that this BD is the only
262 * BD (and that the it is a short BD). A value of 3 indicates either 3
263 * short BDs or 1 long BD and one short BD in the packet. A value of 0
264 * indicates that there are 32 BD locations in the packet (the maximum).
265 * This field is valid only on the first BD of a packet.
267 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
268 #define TX_BD_LONG_FLAGS_BD_CNT_SFT 8
270 * This value is a hint for the length of the entire packet. It is used
271 * by the chip to optimize internal processing. The packet will be
272 * dropped if the hint is too short. This field is valid only on the
273 * first BD of a packet.
275 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
276 #define TX_BD_LONG_FLAGS_LHINT_SFT 13
277 /* indicates packet length < 512B */
278 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
279 /* indicates 512 <= packet length < 1KB */
280 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
281 /* indicates 1KB <= packet length < 2KB */
282 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
283 /* indicates packet length >= 2KB */
284 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
285 #define TX_BD_LONG_FLAGS_LHINT_LAST TX_BD_LONG_FLAGS_LHINT_GTE2K
287 * If set to 1, the device immediately updates the Send Consumer Index
288 * after the buffer associated with this descriptor has been transferred
289 * via DMA to NIC memory from host memory. An interrupt may or may not
290 * be generated according to the state of the interrupt avoidance
291 * mechanisms. If this bit is set to 0, then the Consumer Index is only
292 * updated as soon as one of the host interrupt coalescing conditions
293 * has been met. This bit must be valid on the first BD of a packet.
295 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
297 * All bits in this field must be valid on the first BD of a packet.
298 * Only the packet_end bit must be valid for the remaining BDs of a
301 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
302 #define TX_BD_LONG_FLAGS_SFT 6
305 * This is the length of the host physical buffer this BD describes in
306 * bytes. This field must be valid on all BDs of a packet.
310 * The opaque data field is pass through to the completion and can be
311 * used for any data that the driver wants to associate with the
312 * transmit BD. This field must be valid on the first BD of a packet.
316 * This is the host physical address for the portion of the packet
317 * described by this TX BD. This value must be valid on all BDs of a
320 } __attribute__((packed));
322 /* last 16 bytes of Long TX BD */
324 struct tx_bd_long_hi {
327 * All bits in this field must be valid on the first BD of a packet.
328 * Their value on other BDs of the packet will be ignored.
331 * If set to 1, the controller replaces the TCP/UPD checksum fields of
332 * normal TCP/UPD checksum, or the inner TCP/UDP checksum field of the
333 * encapsulated TCP/UDP packets with the hardware calculated TCP/UDP
334 * checksum for the packet associated with this descriptor. The flag is
335 * ignored if the LSO flag is set. This bit must be valid on the first
338 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
340 * If set to 1, the controller replaces the IP checksum of the normal
341 * packets, or the inner IP checksum of the encapsulated packets with
342 * the hardware calculated IP checksum for the packet associated with
343 * this descriptor. This bit must be valid on the first BD of a packet.
345 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
347 * If set to 1, the controller will not append an Ethernet CRC to the
348 * end of the frame. This bit must be valid on the first BD of a packet.
349 * Packet must be 64B or longer when this flag is set. It is not useful
350 * to use this bit with any form of TX offload such as CSO or LSO. The
351 * intent is that the packet from the host already has a valid Ethernet
354 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
356 * If set to 1, the device will record the time at which the packet was
357 * actually transmitted at the TX MAC. This bit must be valid on the
358 * first BD of a packet.
360 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
362 * If set to 1, The controller replaces the tunnel IP checksum field
363 * with hardware calculated IP checksum for the IP header of the packet
364 * associated with this descriptor. For outer UDP checksum, global outer
365 * UDP checksum TE_NIC register needs to be enabled. If the global outer
366 * UDP checksum TE_NIC register bit is set, outer UDP checksum will be
367 * calculated for the following cases: 1. Packets with tcp_udp_chksum
368 * flag set to offload checksum for inner packet AND the inner packet is
369 * TCP/UDP. If the inner packet is ICMP for example (non-TCP/UDP), even
370 * if the tcp_udp_chksum is set, the outer UDP checksum will not be
371 * calculated. 2. Packets with lso flag set which implies inner TCP
372 * checksum calculation as part of LSO operation.
374 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
376 * If set to 1, the device will treat this packet with LSO(Large Send
377 * Offload) processing for both normal or encapsulated packets, which is
378 * a form of TCP segmentation. When this bit is 1, the hdr_size and mss
379 * fields must be valid. The driver doesn't need to set t_ip_chksum,
380 * ip_chksum, and tcp_udp_chksum flags since the controller will replace
381 * the appropriate checksum fields for segmented packets. When this bit
382 * is 1, the hdr_size and mss fields must be valid.
384 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
386 * If set to zero when LSO is '1', then the IPID will be treated as a
387 * 16b number and will be wrapped if it exceeds a value of 0xffff. If
388 * set to one when LSO is '1', then the IPID will be treated as a 15b
389 * number and will be wrapped if it exceeds a value 0f 0x7fff.
391 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
393 * If set to zero when LSO is '1', then the IPID of the tunnel IP header
394 * will not be modified during LSO operations. If set to one when LSO is
395 * '1', then the IPID of the tunnel IP header will be incremented for
396 * each subsequent segment of an LSO operation. The flag is ignored if
397 * the LSO packet is a normal (non-tunneled) TCP packet.
399 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
401 * If set to '1', then the RoCE ICRC will be appended to the packet.
402 * Packet must be a valid RoCE format packet.
404 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
406 * If set to '1', then the FCoE CRC will be appended to the packet.
407 * Packet must be a valid FCoE format packet.
409 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
412 * When LSO is '1', this field must contain the offset of the TCP
413 * payload from the beginning of the packet in as 16b words. In case of
414 * encapsulated/tunneling packet, this field contains the offset of the
415 * inner TCP payload from beginning of the packet as 16-bit words. This
416 * value must be valid on the first BD of a packet.
418 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
419 #define TX_BD_LONG_HDR_SIZE_SFT 0
422 * This is the MSS value that will be used to do the LSO processing. The
423 * value is the length in bytes of the TCP payload for each segment
424 * generated by the LSO operation. This value must be valid on the first
427 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
428 #define TX_BD_LONG_MSS_SFT 0
432 * This value selects a CFA action to perform on the packet. Set this
433 * value to zero if no CFA action is desired. This value must be valid
434 * on the first BD of a packet.
438 * This value is action meta-data that defines CFA edit operations that
439 * are done in addition to any action editing.
441 /* When key=1, This is the VLAN tag VID value. */
442 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
443 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
444 /* When key=1, This is the VLAN tag DE value. */
445 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
446 /* When key=1, This is the VLAN tag PRI value. */
447 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
448 #define TX_BD_LONG_CFA_META_VLAN_PRI_SFT 13
449 /* When key=1, This is the VLAN tag TPID select value. */
450 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
451 #define TX_BD_LONG_CFA_META_VLAN_TPID_SFT 16
453 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
455 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
457 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
459 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
461 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
462 /* Value programmed in CFA VLANTPID register. */
463 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
464 #define TX_BD_LONG_CFA_META_VLAN_TPID_LAST TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG
465 /* When key=1, This is the VLAN tag TPID select value. */
466 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
467 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19
469 * This field identifies the type of edit to be performed on the packet.
470 * This value must be valid on the first BD of a packet.
472 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
473 #define TX_BD_LONG_CFA_META_KEY_SFT 28
475 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
477 * - meta[17:16] - TPID select value (0 = 0x8100). - meta[15:12]
478 * - PRI/DE value. - meta[11:0] - VID value.
480 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
481 #define TX_BD_LONG_CFA_META_KEY_LAST TX_BD_LONG_CFA_META_KEY_VLAN_TAG
482 } __attribute__((packed));
484 /* Empty TX BD (16 bytes) */
488 /* This value identifies the type of buffer descriptor. */
489 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
490 #define TX_BD_EMPTY_TYPE_SFT 0
492 * Indicates that this BD is 1BB long and is an empty TX BD. Not
493 * valid for use by the driver.
495 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
500 } __attribute__((packed));
502 /* RX Producer Packet BD (16 bytes) */
504 struct rx_prod_pkt_bd {
506 /* This value identifies the type of buffer descriptor. */
507 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
508 #define RX_PROD_PKT_BD_TYPE_SFT 0
510 * Indicates that this BD is 16B long and is an RX Producer (ie.
511 * empty) buffer descriptor.
513 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
515 * If set to 1, the packet will be placed at the address plus 2B. The 2
516 * Bytes of padding will be written as zero.
519 * This is intended to be used when the host buffer is cache-line
520 * aligned to produce packets that are easy to parse in host memory
521 * while still allowing writes to be cache line aligned.
523 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
525 * If set to 1, the packet write will be padded out to the nearest
526 * cache-line with zero value padding.
529 * If receive buffers start/end on cache-line boundaries, this feature
530 * will ensure that all data writes on the PCI bus start/end on cache
533 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
535 * This value is the number of additional buffers in the ring that
536 * describe the buffer space to be consumed for the this packet. If the
537 * value is zero, then the packet must fit within the space described by
538 * this BD. If this value is 1 or more, it indicates how many additional
539 * "buffer" BDs are in the ring immediately following this BD to be used
540 * for the same network packet. Even if the packet to be placed does not
541 * need all the additional buffers, they will be consumed anyway.
543 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
544 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_SFT 8
545 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
546 #define RX_PROD_PKT_BD_FLAGS_SFT 6
549 * This is the length in Bytes of the host physical buffer where data
550 * for the packet may be placed in host memory.
553 * While this is a Byte resolution value, it is often advantageous to
554 * ensure that the buffers provided end on a host cache line.
558 * The opaque data field is pass through to the completion and can be
559 * used for any data that the driver wants to associate with this
560 * receive buffer set.
564 * This is the host physical address where data for the packet may by
565 * placed in host memory.
568 * While this is a Byte resolution value, it is often advantageous to
569 * ensure that the buffers provide start on a host cache line.
571 } __attribute__((packed));
573 /* RX Producer Buffer BD (16 bytes) */
575 struct rx_prod_bfr_bd {
577 /* This value identifies the type of buffer descriptor. */
578 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
579 #define RX_PROD_BFR_BD_TYPE_SFT 0
581 * Indicates that this BD is 16B long and is an RX Producer
584 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
585 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
586 #define RX_PROD_BFR_BD_FLAGS_SFT 6
589 * This is the length in Bytes of the host physical buffer where data
590 * for the packet may be placed in host memory.
593 * While this is a Byte resolution value, it is often advantageous to
594 * ensure that the buffers provided end on a host cache line.
597 /* This field is not used. */
600 * This is the host physical address where data for the packet may by
601 * placed in host memory.
604 * While this is a Byte resolution value, it is often advantageous to
605 * ensure that the buffers provide start on a host cache line.
607 } __attribute__((packed));
609 /* RX Producer Aggregation BD (16 bytes) */
611 struct rx_prod_agg_bd {
613 /* This value identifies the type of buffer descriptor. */
614 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
615 #define RX_PROD_AGG_BD_TYPE_SFT 0
617 * Indicates that this BD is 16B long and is an RX Producer
618 * Assembly Buffer Descriptor.
620 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
622 * If set to 1, the packet write will be padded out to the nearest
623 * cache-line with zero value padding.
626 * If receive buffers start/end on cache-line boundaries, this feature
627 * will ensure that all data writes on the PCI bus end on cache line
630 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
631 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
632 #define RX_PROD_AGG_BD_FLAGS_SFT 6
635 * This is the length in Bytes of the host physical buffer where data
636 * for the packet may be placed in host memory.
639 * While this is a Byte resolution value, it is often advantageous to
640 * ensure that the buffers provided end on a host cache line.
644 * The opaque data field is pass through to the completion and can be
645 * used for any data that the driver wants to associate with this
646 * receive assembly buffer.
650 * This is the host physical address where data for the packet may by
651 * placed in host memory.
654 * While this is a Byte resolution value, it is often advantageous to
655 * ensure that the buffers provide start on a host cache line.
657 } __attribute__((packed));
659 /* Completion Ring Structures */
660 /* Note: This structure is used by the HWRM to communicate HWRM Error. */
661 /* Base Completion Record (16 bytes) */
667 * This field indicates the exact type of the completion. By convention,
668 * the LSB identifies the length of the record in 16B units. Even values
669 * indicate 16B records. Odd values indicate 32B records.
671 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
672 #define CMPL_BASE_TYPE_SFT 0
673 /* TX L2 completion: Completion of TX packet. Length = 16B */
674 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
675 /* RX L2 completion: Completion of and L2 RX packet. Length = 32B */
676 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
678 * RX Aggregation Buffer completion : Completion of an L2
679 * aggregation buffer in support of TPA, HDS, or Jumbo packet
680 * completion. Length = 16B
682 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
684 * RX L2 TPA Start Completion: Completion at the beginning of a
685 * TPA operation. Length = 32B
687 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
689 * RX L2 TPA End Completion: Completion at the end of a TPA
690 * operation. Length = 32B
692 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
694 * Statistics Ejection Completion: Completion of statistics data
695 * ejection buffer. Length = 16B
697 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
698 /* HWRM Command Completion: Completion of an HWRM command. */
699 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
700 /* Forwarded HWRM Request */
701 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
702 /* Forwarded HWRM Response */
703 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
704 /* HWRM Asynchronous Event Information */
705 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
706 /* CQ Notification */
707 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
708 /* SRQ Threshold Event */
709 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
710 /* DBQ Threshold Event */
711 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
712 /* QP Async Notification */
713 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
714 /* Function Async Notification */
715 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
724 * This value is written by the NIC such that it will be different for
725 * each pass through the completion queue. The even passes will write 1.
726 * The odd passes will write 0.
728 #define CMPL_BASE_V UINT32_C(0x1)
730 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
731 #define CMPL_BASE_INFO3_SFT 1
734 } __attribute__((packed));
736 /* TX Completion Record (16 bytes) */
741 * This field indicates the exact type of the completion. By convention,
742 * the LSB identifies the length of the record in 16B units. Even values
743 * indicate 16B records. Odd values indicate 32B records.
745 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
746 #define TX_CMPL_TYPE_SFT 0
747 /* TX L2 completion: Completion of TX packet. Length = 16B */
748 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
750 * When this bit is '1', it indicates a packet that has an error of some
751 * type. Type of error is indicated in error_flags.
753 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
755 * When this bit is '1', it indicates that the packet completed was
756 * transmitted using the push acceleration data provided by the driver.
757 * When this bit is '0', it indicates that the packet had not push
758 * acceleration data written or was executed as a normal packet even
759 * though push data was provided.
761 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
762 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
763 #define TX_CMPL_FLAGS_SFT 6
765 /* unused1 is 16 b */
768 * This is a copy of the opaque field from the first TX BD of this
769 * transmitted packet.
773 * This value is written by the NIC such that it will be different for
774 * each pass through the completion queue. The even passes will write 1.
775 * The odd passes will write 0.
777 #define TX_CMPL_V UINT32_C(0x1)
779 * This error indicates that there was some sort of problem with the BDs
782 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
783 #define TX_CMPL_ERRORS_BUFFER_ERROR_SFT 1
785 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
786 /* Bad Format: BDs were not formatted correctly. */
787 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
788 #define TX_CMPL_ERRORS_BUFFER_ERROR_LAST TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT
790 * When this bit is '1', it indicates that the length of the packet was
791 * zero. No packet was transmitted.
793 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
795 * When this bit is '1', it indicates that the packet was longer than
796 * the programmed limit in TDI. No packet was transmitted.
798 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
800 * When this bit is '1', it indicates that one or more of the BDs
801 * associated with this packet generated a PCI error. This probably
802 * means the address was not valid.
804 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
806 * When this bit is '1', it indicates that the packet was longer than
807 * indicated by the hint. No packet was transmitted.
809 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
811 * When this bit is '1', it indicates that the packet was dropped due to
812 * Poison TLP error on one or more of the TLPs in the PXP completion.
814 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
815 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
816 #define TX_CMPL_ERRORS_SFT 1
818 /* unused2 is 16 b */
820 /* unused3 is 32 b */
821 } __attribute__((packed));
823 /* RX Packet Completion Record (32 bytes split to 2 16-byte struct) */
828 * This field indicates the exact type of the completion. By convention,
829 * the LSB identifies the length of the record in 16B units. Even values
830 * indicate 16B records. Odd values indicate 32B records.
832 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
833 #define RX_PKT_CMPL_TYPE_SFT 0
834 /* RX L2 completion: Completion of and L2 RX packet. Length = 32B */
835 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
837 * When this bit is '1', it indicates a packet that has an error of some
838 * type. Type of error is indicated in error_flags.
840 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
841 /* This field indicates how the packet was placed in the buffer. */
842 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
843 #define RX_PKT_CMPL_FLAGS_PLACEMENT_SFT 7
844 /* Normal: Packet was placed using normal algorithm. */
845 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
846 /* Jumbo: Packet was placed using jumbo algorithm. */
847 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
849 * Header/Data Separation: Packet was placed using Header/Data
850 * separation algorithm. The separation location is indicated by
853 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
854 #define RX_PKT_CMPL_FLAGS_PLACEMENT_LAST RX_PKT_CMPL_FLAGS_PLACEMENT_HDS
855 /* This bit is '1' if the RSS field in this completion is valid. */
856 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
858 #define RX_PKT_CMPL_FLAGS_UNUSED UINT32_C(0x800)
860 * This value indicates what the inner packet determined for the packet
863 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
864 #define RX_PKT_CMPL_FLAGS_ITYPE_SFT 12
865 /* Not Known: Indicates that the packet type was not known. */
866 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 12)
868 * IP Packet: Indicates that the packet was an IP packet, but
869 * further classification was not possible.
871 #define RX_PKT_CMPL_FLAGS_ITYPE_IP (UINT32_C(0x1) << 12)
873 * TCP Packet: Indicates that the packet was IP and TCP. This
874 * indicates that the payload_offset field is valid.
876 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
878 * UDP Packet: Indicates that the packet was IP and UDP. This
879 * indicates that the payload_offset field is valid.
881 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 12)
883 * FCoE Packet: Indicates that the packet was recognized as a
884 * FCoE. This also indicates that the payload_offset field is
887 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 12)
889 * RoCE Packet: Indicates that the packet was recognized as a
890 * RoCE. This also indicates that the payload_offset field is
893 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 12)
895 * ICMP Packet: Indicates that the packet was recognized as
896 * ICMP. This indicates that the payload_offset field is valid.
898 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 12)
900 * PtP packet wo/timestamp: Indicates that the packet was
901 * recognized as a PtP packet.
903 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 12)
905 * PtP packet w/timestamp: Indicates that the packet was
906 * recognized as a PtP packet and that a timestamp was taken for
909 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 12)
910 #define RX_PKT_CMPL_FLAGS_ITYPE_LAST RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP
911 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
912 #define RX_PKT_CMPL_FLAGS_SFT 6
915 * This is the length of the data for the packet stored in the buffer(s)
916 * identified by the opaque value. This includes the packet BD and any
917 * associated buffer BDs. This does not include the the length of any
918 * data places in aggregation BDs.
922 * This is a copy of the opaque field from the RX BD this completion
928 * This value is written by the NIC such that it will be different for
929 * each pass through the completion queue. The even passes will write 1.
930 * The odd passes will write 0.
932 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
934 * This value is the number of aggregation buffers that follow this
935 * entry in the completion ring that are a part of this packet. If the
936 * value is zero, then the packet is completely contained in the buffer
937 * space provided for the packet in the RX ring.
939 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
940 #define RX_PKT_CMPL_AGG_BUFS_SFT 1
942 uint8_t rss_hash_type;
944 * This is the RSS hash type for the packet. The value is packed
945 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. The
946 * value of tuple_extrac_op provides the information about what fields
947 * the hash was computed on. * 0: The RSS hash was computed over source
948 * IP address, destination IP address, source port, and destination port
949 * of inner IP and TCP or UDP headers. Note: For non-tunneled packets,
950 * the packet headers are considered inner packet headers for the RSS
951 * hash computation purpose. * 1: The RSS hash was computed over source
952 * IP address and destination IP address of inner IP header. Note: For
953 * non-tunneled packets, the packet headers are considered inner packet
954 * headers for the RSS hash computation purpose. * 2: The RSS hash was
955 * computed over source IP address, destination IP address, source port,
956 * and destination port of IP and TCP or UDP headers of outer tunnel
957 * headers. Note: For non-tunneled packets, this value is not
958 * applicable. * 3: The RSS hash was computed over source IP address and
959 * destination IP address of IP header of outer tunnel headers. Note:
960 * For non-tunneled packets, this value is not applicable. Note that
961 * 4-tuples values listed above are applicable for layer 4 protocols
962 * supported and enabled for RSS in the hardware, HWRM firmware, and
963 * drivers. For example, if RSS hash is supported and enabled for TCP
964 * traffic only, then the values of tuple_extract_op corresponding to
965 * 4-tuples are only valid for TCP traffic.
967 uint8_t payload_offset;
969 * This value indicates the offset in bytes from the beginning of the
970 * packet where the inner payload starts. This value is valid for TCP,
971 * UDP, FCoE, and RoCE packets. A value of zero indicates that header is
972 * 256B into the packet.
978 * This value is the RSS hash value calculated for the packet based on
979 * the mode bits and key value in the VNIC.
981 } __attribute__((packed));
983 /* last 16 bytes of RX Packet Completion Record */
985 struct rx_pkt_cmpl_hi {
988 * This indicates that the ip checksum was calculated for the inner
989 * packet and that the ip_cs_error field indicates if there was an
992 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
994 * This indicates that the TCP, UDP or ICMP checksum was calculated for
995 * the inner packet and that the l4_cs_error field indicates if there
998 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
1000 * This indicates that the ip checksum was calculated for the tunnel
1001 * header and that the t_ip_cs_error field indicates if there was an
1004 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
1006 * This indicates that the UDP checksum was calculated for the tunnel
1007 * packet and that the t_l4_cs_error field indicates if there was an
1010 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
1011 /* This value indicates what format the metadata field is. */
1012 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
1013 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
1014 /* No metadata informtaion. Value is zero. */
1015 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
1017 * The metadata field contains the VLAN tag and TPID value. -
1018 * metadata[11:0] contains the vlan VID value. - metadata[12]
1019 * contains the vlan DE value. - metadata[15:13] contains the
1020 * vlan PRI value. - metadata[31:16] contains the vlan TPID
1023 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
1024 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN
1026 * This field indicates the IP type for the inner-most IP header. A
1027 * value of '0' indicates IPv4. A value of '1' indicates IPv6. This
1028 * value is only valid if itype indicates a packet with an IP header.
1030 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
1033 * This is data from the CFA block as indicated by the meta_format
1036 /* When meta_format=1, this value is the VLAN VID. */
1037 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
1038 #define RX_PKT_CMPL_METADATA_VID_SFT 0
1039 /* When meta_format=1, this value is the VLAN DE. */
1040 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
1041 /* When meta_format=1, this value is the VLAN PRI. */
1042 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
1043 #define RX_PKT_CMPL_METADATA_PRI_SFT 13
1044 /* When meta_format=1, this value is the VLAN TPID. */
1045 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
1046 #define RX_PKT_CMPL_METADATA_TPID_SFT 16
1049 * This value is written by the NIC such that it will be different for
1050 * each pass through the completion queue. The even passes will write 1.
1051 * The odd passes will write 0.
1053 #define RX_PKT_CMPL_V2 UINT32_C(0x1)
1055 * This error indicates that there was some sort of problem with the BDs
1056 * for the packet that was found after part of the packet was already
1057 * placed. The packet should be treated as invalid.
1059 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
1060 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
1061 /* No buffer error */
1062 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (UINT32_C(0x0) << 1)
1064 * Did Not Fit: Packet did not fit into packet buffer provided.
1065 * For regular placement, this means the packet did not fit in
1066 * the buffer provided. For HDS and jumbo placement, this means
1067 * that the packet could not be placed into 7 physical buffers
1070 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (UINT32_C(0x1) << 1)
1072 * Not On Chip: All BDs needed for the packet were not on-chip
1073 * when the packet arrived.
1075 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (UINT32_C(0x2) << 1)
1076 /* Bad Format: BDs were not formatted correctly. */
1077 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (UINT32_C(0x3) << 1)
1078 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT
1079 /* This indicates that there was an error in the IP header checksum. */
1080 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR UINT32_C(0x10)
1082 * This indicates that there was an error in the TCP, UDP or ICMP
1085 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR UINT32_C(0x20)
1087 * This indicates that there was an error in the tunnel IP header
1090 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR UINT32_C(0x40)
1091 /* This indicates that there was an error in the tunnel UDP checksum. */
1092 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR UINT32_C(0x80)
1094 * This indicates that there was a CRC error on either an FCoE or RoCE
1095 * packet. The itype indicates the packet type.
1097 #define RX_PKT_CMPL_ERRORS_CRC_ERROR UINT32_C(0x100)
1099 * This indicates that there was an error in the tunnel portion of the
1100 * packet when this field is non-zero.
1102 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00)
1103 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
1105 * No additional error occurred on the tunnel portion of the
1106 * packet of the packet does not have a tunnel.
1108 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9)
1110 * Indicates that IP header version does not match expectation
1111 * from L2 Ethertype for IPv4 and IPv6 in the tunnel header.
1113 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9)
1115 * Indicates that header length is out of range in the tunnel
1116 * header. Valid for IPv4.
1118 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9)
1120 * Indicates that the physical packet is shorter than that
1121 * claimed by the PPPoE header length for a tunnel PPPoE packet.
1123 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (UINT32_C(0x3) << 9)
1125 * Indicates that physical packet is shorter than that claimed
1126 * by the tunnel l3 header length. Valid for IPv4, or IPv6
1127 * tunnel packet packets.
1129 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x4) << 9)
1131 * Indicates that the physical packet is shorter than that
1132 * claimed by the tunnel UDP header length for a tunnel UDP
1133 * packet that is not fragmented.
1135 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x5) << 9)
1137 * indicates that the IPv4 TTL or IPv6 hop limit check have
1138 * failed (e.g. TTL = 0) in the tunnel header. Valid for IPv4,
1141 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x6) << 9)
1142 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_LAST RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
1144 * This indicates that there was an error in the inner portion of the
1145 * packet when this field is non-zero.
1147 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000)
1148 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
1150 * No additional error occurred on the tunnel portion of the
1151 * packet of the packet does not have a tunnel.
1153 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12)
1155 * Indicates that IP header version does not match expectation
1156 * from L2 Ethertype for IPv4 and IPv6 or that option other than
1157 * VFT was parsed on FCoE packet.
1159 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12)
1161 * indicates that header length is out of range. Valid for IPv4
1164 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12)
1166 * indicates that the IPv4 TTL or IPv6 hop limit check have
1167 * failed (e.g. TTL = 0). Valid for IPv4, and IPv6
1169 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12)
1171 * Indicates that physical packet is shorter than that claimed
1172 * by the l3 header length. Valid for IPv4, IPv6 packet or RoCE
1175 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12)
1177 * Indicates that the physical packet is shorter than that
1178 * claimed by the UDP header length for a UDP packet that is not
1181 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12)
1183 * Indicates that TCP header length > IP payload. Valid for TCP
1186 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12)
1187 /* Indicates that TCP header length < 5. Valid for TCP. */
1188 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) << 12)
1190 * Indicates that TCP option headers result in a TCP header size
1191 * that does not match data offset in TCP header. Valid for TCP.
1193 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12)
1194 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_LAST RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
1195 #define RX_PKT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
1196 #define RX_PKT_CMPL_ERRORS_SFT 1
1199 * This field identifies the CFA action rule that was used for this
1204 * This value holds the reordering sequence number for the packet. If
1205 * the reordering sequence is not valid, then this value is zero. The
1206 * reordering domain for the packet is in the bottom 8 to 10b of the
1207 * rss_hash value. The bottom 20b of this value contain the ordering
1208 * domain value for the packet.
1210 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
1211 #define RX_PKT_CMPL_REORDER_SFT 0
1212 } __attribute__((packed));
1214 /* RX L2 TPA Start Completion Record (32 bytes split to 2 16-byte struct) */
1216 struct rx_tpa_start_cmpl {
1217 uint16_t flags_type;
1219 * This field indicates the exact type of the completion. By convention,
1220 * the LSB identifies the length of the record in 16B units. Even values
1221 * indicate 16B records. Odd values indicate 32B records.
1223 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
1224 #define RX_TPA_START_CMPL_TYPE_SFT 0
1226 * RX L2 TPA Start Completion: Completion at the beginning of a
1227 * TPA operation. Length = 32B
1229 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
1230 /* This bit will always be '0' for TPA start completions. */
1231 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
1232 /* This field indicates how the packet was placed in the buffer. */
1233 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
1234 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_SFT 7
1236 * Jumbo: TPA Packet was placed using jumbo algorithm. This
1237 * means that the first buffer will be filled with data before
1238 * moving to aggregation buffers. Each aggregation buffer will
1239 * be filled before moving to the next aggregation buffer.
1241 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
1243 * Header/Data Separation: Packet was placed using Header/Data
1244 * separation algorithm. The separation location is indicated by
1247 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
1249 * GRO/Jumbo: Packet will be placed using GRO/Jumbo where the
1250 * first packet is filled with data. Subsequent packets will be
1251 * placed such that any one packet does not span two aggregation
1252 * buffers unless it starts at the beginning of an aggregation
1255 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO (UINT32_C(0x5) << 7)
1257 * GRO/Header-Data Separation: Packet will be placed using
1258 * GRO/HDS where the header is in the first packet. Payload of
1259 * each packet will be placed such that any one packet does not
1260 * span two aggregation buffers unless it starts at the
1261 * beginning of an aggregation buffer.
1263 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS (UINT32_C(0x6) << 7)
1264 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_LAST RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS
1265 /* This bit is '1' if the RSS field in this completion is valid. */
1266 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
1268 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
1270 * This value indicates what the inner packet determined for the packet
1273 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
1274 #define RX_TPA_START_CMPL_FLAGS_ITYPE_SFT 12
1275 /* TCP Packet: Indicates that the packet was IP and TCP. */
1276 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
1277 #define RX_TPA_START_CMPL_FLAGS_ITYPE_LAST RX_TPA_START_CMPL_FLAGS_ITYPE_TCP
1278 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
1279 #define RX_TPA_START_CMPL_FLAGS_SFT 6
1282 * This value indicates the amount of packet data written to the buffer
1283 * the opaque field in this completion corresponds to.
1287 * This is a copy of the opaque field from the RX BD this completion
1291 /* unused1 is 7 b */
1293 * This value is written by the NIC such that it will be different for
1294 * each pass through the completion queue. The even passes will write 1.
1295 * The odd passes will write 0.
1297 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
1298 /* unused1 is 7 b */
1299 uint8_t rss_hash_type;
1301 * This is the RSS hash type for the packet. The value is packed
1302 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}. The
1303 * value of tuple_extrac_op provides the information about what fields
1304 * the hash was computed on. * 0: The RSS hash was computed over source
1305 * IP address, destination IP address, source port, and destination port
1306 * of inner IP and TCP or UDP headers. Note: For non-tunneled packets,
1307 * the packet headers are considered inner packet headers for the RSS
1308 * hash computation purpose. * 1: The RSS hash was computed over source
1309 * IP address and destination IP address of inner IP header. Note: For
1310 * non-tunneled packets, the packet headers are considered inner packet
1311 * headers for the RSS hash computation purpose. * 2: The RSS hash was
1312 * computed over source IP address, destination IP address, source port,
1313 * and destination port of IP and TCP or UDP headers of outer tunnel
1314 * headers. Note: For non-tunneled packets, this value is not
1315 * applicable. * 3: The RSS hash was computed over source IP address and
1316 * destination IP address of IP header of outer tunnel headers. Note:
1317 * For non-tunneled packets, this value is not applicable. Note that
1318 * 4-tuples values listed above are applicable for layer 4 protocols
1319 * supported and enabled for RSS in the hardware, HWRM firmware, and
1320 * drivers. For example, if RSS hash is supported and enabled for TCP
1321 * traffic only, then the values of tuple_extract_op corresponding to
1322 * 4-tuples are only valid for TCP traffic.
1326 * This is the aggregation ID that the completion is associated with.
1327 * Use this number to correlate the TPA start completion with the TPA
1330 /* unused2 is 9 b */
1332 * This is the aggregation ID that the completion is associated with.
1333 * Use this number to correlate the TPA start completion with the TPA
1336 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
1337 #define RX_TPA_START_CMPL_AGG_ID_SFT 9
1340 * This value is the RSS hash value calculated for the packet based on
1341 * the mode bits and key value in the VNIC.
1343 } __attribute__((packed));
1345 /* last 16 bytes of RX L2 TPA Start Completion Record */
1347 struct rx_tpa_start_cmpl_hi {
1350 * This indicates that the ip checksum was calculated for the inner
1351 * packet and that the sum passed for all segments included in the
1354 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
1356 * This indicates that the TCP, UDP or ICMP checksum was calculated for
1357 * the inner packet and that the sum passed for all segments included in
1360 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
1362 * This indicates that the ip checksum was calculated for the tunnel
1363 * header and that the sum passed for all segments included in the
1366 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
1368 * This indicates that the UDP checksum was calculated for the tunnel
1369 * packet and that the sum passed for all segments included in the
1372 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
1373 /* This value indicates what format the metadata field is. */
1374 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
1375 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
1376 /* No metadata informtaion. Value is zero. */
1377 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
1379 * The metadata field contains the VLAN tag and TPID value. -
1380 * metadata[11:0] contains the vlan VID value. - metadata[12]
1381 * contains the vlan DE value. - metadata[15:13] contains the
1382 * vlan PRI value. - metadata[31:16] contains the vlan TPID
1385 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
1386 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
1388 * This field indicates the IP type for the inner-most IP header. A
1389 * value of '0' indicates IPv4. A value of '1' indicates IPv6.
1391 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
1394 * This is data from the CFA block as indicated by the meta_format
1397 /* When meta_format=1, this value is the VLAN VID. */
1398 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
1399 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
1400 /* When meta_format=1, this value is the VLAN DE. */
1401 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
1402 /* When meta_format=1, this value is the VLAN PRI. */
1403 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
1404 #define RX_TPA_START_CMPL_METADATA_PRI_SFT 13
1405 /* When meta_format=1, this value is the VLAN TPID. */
1406 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
1407 #define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
1409 /* unused4 is 15 b */
1411 * This value is written by the NIC such that it will be different for
1412 * each pass through the completion queue. The even passes will write 1.
1413 * The odd passes will write 0.
1415 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
1416 /* unused4 is 15 b */
1419 * This field identifies the CFA action rule that was used for this
1422 uint32_t inner_l4_size_inner_l3_offset_inner_l2_offset_outer_l3_offset;
1424 * This is the size in bytes of the inner most L4 header. This can be
1425 * subtracted from the payload_offset to determine the start of the
1426 * inner most L4 header.
1429 * This is the offset from the beginning of the packet in bytes for the
1430 * outer L3 header. If there is no outer L3 header, then this value is
1433 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
1434 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
1436 * This is the offset from the beginning of the packet in bytes for the
1437 * inner most L2 header.
1439 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
1440 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_SFT 9
1442 * This is the offset from the beginning of the packet in bytes for the
1443 * inner most L3 header.
1445 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
1446 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_SFT 18
1448 * This is the size in bytes of the inner most L4 header. This can be
1449 * subtracted from the payload_offset to determine the start of the
1450 * inner most L4 header.
1452 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
1453 #define RX_TPA_START_CMPL_INNER_L4_SIZE_SFT 27
1454 } __attribute__((packed));
1456 /* RX TPA End Completion Record (32 bytes split to 2 16-byte struct) */
1458 struct rx_tpa_end_cmpl {
1459 uint16_t flags_type;
1461 * This field indicates the exact type of the completion. By convention,
1462 * the LSB identifies the length of the record in 16B units. Even values
1463 * indicate 16B records. Odd values indicate 32B records.
1465 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
1466 #define RX_TPA_END_CMPL_TYPE_SFT 0
1468 * RX L2 TPA End Completion: Completion at the end of a TPA
1469 * operation. Length = 32B
1471 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
1473 * When this bit is '1', it indicates a packet that has an error of some
1474 * type. Type of error is indicated in error_flags.
1476 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
1477 /* This field indicates how the packet was placed in the buffer. */
1478 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
1479 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_SFT 7
1481 * Jumbo: TPA Packet was placed using jumbo algorithm. This
1482 * means that the first buffer will be filled with data before
1483 * moving to aggregation buffers. Each aggregation buffer will
1484 * be filled before moving to the next aggregation buffer.
1486 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
1488 * Header/Data Separation: Packet was placed using Header/Data
1489 * separation algorithm. The separation location is indicated by
1492 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
1494 * GRO/Jumbo: Packet will be placed using GRO/Jumbo where the
1495 * first packet is filled with data. Subsequent packets will be
1496 * placed such that any one packet does not span two aggregation
1497 * buffers unless it starts at the beginning of an aggregation
1500 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO (UINT32_C(0x5) << 7)
1502 * GRO/Header-Data Separation: Packet will be placed using
1503 * GRO/HDS where the header is in the first packet. Payload of
1504 * each packet will be placed such that any one packet does not
1505 * span two aggregation buffers unless it starts at the
1506 * beginning of an aggregation buffer.
1508 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS (UINT32_C(0x6) << 7)
1509 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_LAST RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS
1511 #define RX_TPA_END_CMPL_FLAGS_UNUSED_MASK UINT32_C(0xc00)
1512 #define RX_TPA_END_CMPL_FLAGS_UNUSED_SFT 10
1514 * This value indicates what the inner packet determined for the packet
1515 * was. - 2 TCP Packet Indicates that the packet was IP and TCP. This
1516 * indicates that the ip_cs field is valid and that the tcp_udp_cs field
1517 * is valid and contains the TCP checksum. This also indicates that the
1518 * payload_offset field is valid.
1520 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
1521 #define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
1522 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
1523 #define RX_TPA_END_CMPL_FLAGS_SFT 6
1526 * This value is zero for TPA End completions. There is no data in the
1527 * buffer that corresponds to the opaque value in this completion.
1531 * This is a copy of the opaque field from the RX BD this completion
1534 uint8_t agg_bufs_v1;
1535 /* unused1 is 1 b */
1537 * This value is written by the NIC such that it will be different for
1538 * each pass through the completion queue. The even passes will write 1.
1539 * The odd passes will write 0.
1541 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
1543 * This value is the number of aggregation buffers that follow this
1544 * entry in the completion ring that are a part of this aggregation
1545 * packet. If the value is zero, then the packet is completely contained
1546 * in the buffer space provided in the aggregation start completion.
1548 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
1549 #define RX_TPA_END_CMPL_AGG_BUFS_SFT 1
1550 /* unused1 is 1 b */
1552 /* This value is the number of segments in the TPA operation. */
1553 uint8_t payload_offset;
1555 * This value indicates the offset in bytes from the beginning of the
1556 * packet where the inner payload starts. This value is valid for TCP,
1557 * UDP, FCoE, and RoCE packets. A value of zero indicates an offset of
1562 * This is the aggregation ID that the completion is associated with.
1563 * Use this number to correlate the TPA start completion with the TPA
1566 /* unused2 is 1 b */
1568 * This is the aggregation ID that the completion is associated with.
1569 * Use this number to correlate the TPA start completion with the TPA
1572 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
1573 #define RX_TPA_END_CMPL_AGG_ID_SFT 1
1576 * For non-GRO packets, this value is the timestamp delta between
1577 * earliest and latest timestamp values for TPA packet. If packets were
1578 * not time stamped, then delta will be zero. For GRO packets, this
1579 * field is zero except for the following sub-fields. - tsdelta[31]
1580 * Timestamp present indication. When '0', no Timestamp option is in the
1581 * packet. When '1', then a Timestamp option is present in the packet.
1583 } __attribute__((packed));
1585 /* last 16 bytes of RX TPA End Completion Record */
1587 struct rx_tpa_end_cmpl_hi {
1588 uint32_t tpa_dup_acks;
1589 /* unused3 is 28 b */
1591 * This value is the number of duplicate ACKs that have been received as
1592 * part of the TPA operation.
1594 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
1595 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
1596 /* unused3 is 28 b */
1597 uint16_t tpa_seg_len;
1599 * This value is the valid when TPA completion is active. It indicates
1600 * the length of the longest segment of the TPA operation for LRO mode
1601 * and the length of the first segment in GRO mode. This value may be
1602 * used by GRO software to re-construct the original packet stream from
1603 * the TPA packet. This is the length of all but the last segment for
1604 * GRO. In LRO mode this value may be used to indicate MSS size to the
1608 /* unused4 is 16 b */
1611 * This value is written by the NIC such that it will be different for
1612 * each pass through the completion queue. The even passes will write 1.
1613 * The odd passes will write 0.
1615 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
1617 * This error indicates that there was some sort of problem with the BDs
1618 * for the packet that was found after part of the packet was already
1619 * placed. The packet should be treated as invalid.
1621 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
1622 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
1624 * This error occurs when there is a fatal HW problem in the
1625 * chip only. It indicates that there were not BDs on chip but
1626 * that there was adequate reservation. provided by the TPA
1629 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (UINT32_C(0x2) << 1)
1631 * This error occurs when TPA block was not configured to
1632 * reserve adequate BDs for TPA operations on this RX ring. All
1633 * data for the TPA operation was not placed. This error can
1634 * also be generated when the number of segments is not
1635 * programmed correctly in TPA and the 33 total aggregation
1636 * buffers allowed for the TPA operation has been exceeded.
1638 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR (UINT32_C(0x4) << 1)
1639 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
1640 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
1641 #define RX_TPA_END_CMPL_ERRORS_SFT 1
1643 /* unused5 is 16 b */
1644 uint32_t start_opaque;
1646 * This is the opaque value that was completed for the TPA start
1647 * completion that corresponds to this TPA end completion.
1649 } __attribute__((packed));
1651 /* RX Aggregation Buffer Completion Record (16 bytes) */
1653 struct rx_abuf_cmpl {
1655 /* unused is 10 b */
1657 * This field indicates the exact type of the completion. By convention,
1658 * the LSB identifies the length of the record in 16B units. Even values
1659 * indicate 16B records. Odd values indicate 32B records.
1661 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
1662 #define RX_ABUF_CMPL_TYPE_SFT 0
1664 * RX Aggregation Buffer completion : Completion of an L2
1665 * aggregation buffer in support of TPA, HDS, or Jumbo packet
1666 * completion. Length = 16B
1668 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
1669 /* unused is 10 b */
1672 * This is the length of the data for the packet stored in this
1673 * aggregation buffer identified by the opaque value. This does not
1674 * include the length of any data placed in other aggregation BDs or in
1675 * the packet or buffer BDs. This length does not include any space
1676 * added due to hdr_offset register during HDS placement mode.
1680 * This is a copy of the opaque field from the RX BD this aggregation
1681 * buffer corresponds to.
1684 /* unused2 is 31 b */
1686 * This value is written by the NIC such that it will be different for
1687 * each pass through the completion queue. The even passes will write 1.
1688 * The odd passes will write 0.
1690 #define RX_ABUF_CMPL_V UINT32_C(0x1)
1691 /* unused2 is 31 b */
1693 /* unused3 is 32 b */
1694 } __attribute__((packed));
1696 /* Statistics Ejection Buffer Completion Record (16 bytes) */
1700 /* unused is 10 b */
1702 * This field indicates the exact type of the completion. By convention,
1703 * the LSB identifies the length of the record in 16B units. Even values
1704 * indicate 16B records. Odd values indicate 32B records.
1706 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
1707 #define EJECT_CMPL_TYPE_SFT 0
1709 * Statistics Ejection Completion: Completion of statistics data
1710 * ejection buffer. Length = 16B
1712 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
1713 /* unused is 10 b */
1715 /* This is the length of the statistics data stored in this buffer. */
1718 * This is a copy of the opaque field from the RX BD this ejection
1719 * buffer corresponds to.
1722 /* unused2 is 31 b */
1724 * This value is written by the NIC such that it will be different for
1725 * each pass through the completion queue. The even passes will write 1.
1726 * The odd passes will write 0.
1728 #define EJECT_CMPL_V UINT32_C(0x1)
1729 /* unused2 is 31 b */
1731 /* unused3 is 32 b */
1732 } __attribute__((packed));
1734 /* HWRM Completion Record (16 bytes) */
1738 /* unused is 10 b */
1740 * This field indicates the exact type of the completion. By convention,
1741 * the LSB identifies the length of the record in 16B units. Even values
1742 * indicate 16B records. Odd values indicate 32B records.
1744 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
1745 #define HWRM_CMPL_TYPE_SFT 0
1746 /* HWRM Command Completion: Completion of an HWRM command. */
1747 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
1748 /* unused is 10 b */
1749 uint16_t sequence_id;
1750 /* This is the sequence_id of the HWRM command that has completed. */
1752 /* unused2 is 32 b */
1754 /* unused3 is 31 b */
1756 * This value is written by the NIC such that it will be different for
1757 * each pass through the completion queue. The even passes will write 1.
1758 * The odd passes will write 0.
1760 #define HWRM_CMPL_V UINT32_C(0x1)
1761 /* unused3 is 31 b */
1763 /* unused4 is 32 b */
1764 } __attribute__((packed));
1766 /* HWRM Forwarded Request (16 bytes) */
1768 struct hwrm_fwd_req_cmpl {
1769 uint16_t req_len_type;
1770 /* Length of forwarded request in bytes. */
1772 * This field indicates the exact type of the completion. By convention,
1773 * the LSB identifies the length of the record in 16B units. Even values
1774 * indicate 16B records. Odd values indicate 32B records.
1776 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
1777 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
1778 /* Forwarded HWRM Request */
1779 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
1780 /* Length of forwarded request in bytes. */
1781 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
1782 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
1785 * Source ID of this request. Typically used in forwarding requests and
1786 * responses. 0x0 - 0xFFF8 - Used for function ids 0xFFF8 - 0xFFFE -
1787 * Reserved for internal processors 0xFFFF - HWRM
1790 /* unused1 is 32 b */
1791 uint64_t req_buf_addr_v;
1792 /* Address of forwarded request. */
1794 * This value is written by the NIC such that it will be different for
1795 * each pass through the completion queue. The even passes will write 1.
1796 * The odd passes will write 0.
1798 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
1799 /* Address of forwarded request. */
1800 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
1801 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
1802 } __attribute__((packed));
1804 /* HWRM Forwarded Response (16 bytes) */
1806 struct hwrm_fwd_resp_cmpl {
1808 /* unused1 is 10 b */
1810 * This field indicates the exact type of the completion. By convention,
1811 * the LSB identifies the length of the record in 16B units. Even values
1812 * indicate 16B records. Odd values indicate 32B records.
1814 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
1815 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
1816 /* Forwarded HWRM Response */
1817 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
1818 /* unused1 is 10 b */
1821 * Source ID of this response. Typically used in forwarding requests and
1822 * responses. 0x0 - 0xFFF8 - Used for function ids 0xFFF8 - 0xFFFE -
1823 * Reserved for internal processors 0xFFFF - HWRM
1826 /* Length of forwarded response in bytes. */
1828 /* unused2 is 16 b */
1829 uint64_t resp_buf_addr_v;
1830 /* Address of forwarded response. */
1832 * This value is written by the NIC such that it will be different for
1833 * each pass through the completion queue. The even passes will write 1.
1834 * The odd passes will write 0.
1836 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
1837 /* Address of forwarded response. */
1838 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
1839 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
1840 } __attribute__((packed));
1842 #define GET_EVENT_ID(x) \
1843 ((x) == 0x30 ? "VF_FLR": \
1844 ((x) == 0x20 ? "PF_DRVR_UNLOAD": \
1845 ((x) == 0x10 ? "FUNC_DRVR_UNLOAD": \
1846 ((x) == 0xff ? "HWRM_ERROR": \
1847 ((x) == 0x32 ? "PF_VF_COMM_STATUS_CHANGE": \
1848 ((x) == 0x33 ? "VF_CFG_CHANGE": \
1849 ((x) == 0x11 ? "FUNC_DRVR_LOAD": \
1850 ((x) == 0x31 ? "VF_MAC_ADDR_CHANGE": \
1851 ((x) == 0x34 ? "LLFC_PFC_CHANGE": \
1852 ((x) == 0x4 ? "PORT_CONN_NOT_ALLOWED": \
1853 ((x) == 0x5 ? "LINK_SPEED_CFG_NOT_ALLOWED": \
1854 ((x) == 0x6 ? "LINK_SPEED_CFG_CHANGE": \
1855 ((x) == 0x7 ? "PORT_PHY_CFG_CHANGE": \
1856 ((x) == 0x0 ? "LINK_STATUS_CHANGE": \
1857 ((x) == 0x1 ? "LINK_MTU_CHANGE": \
1858 ((x) == 0x2 ? "LINK_SPEED_CHANGE": \
1859 ((x) == 0x3 ? "DCB_CONFIG_CHANGE": \
1860 ((x) == 0x12 ? "FUNC_FLR_PROC_CMPLT": \
1861 ((x) == 0x21 ? "PF_DRVR_LOAD": \
1862 "Unknown event_id")))))))))))))))))))
1864 /* HWRM Asynchronous Event Completion Record (16 bytes) */
1866 struct hwrm_async_event_cmpl {
1868 /* unused1 is 10 b */
1870 * This field indicates the exact type of the completion. By convention,
1871 * the LSB identifies the length of the record in 16B units. Even values
1872 * indicate 16B records. Odd values indicate 32B records.
1874 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
1875 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
1876 /* HWRM Asynchronous Event Information */
1877 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
1878 /* unused1 is 10 b */
1880 /* Identifiers of events. */
1881 /* Link status changed */
1882 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE UINT32_C(0x0)
1883 /* Link MTU changed */
1884 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE UINT32_C(0x1)
1885 /* Link speed changed */
1886 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE UINT32_C(0x2)
1887 /* DCB Configuration changed */
1888 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE UINT32_C(0x3)
1889 /* Port connection not allowed */
1890 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED UINT32_C(0x4)
1891 /* Link speed configuration was not allowed */
1892 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED UINT32_C(0x5)
1893 /* Link speed configuration change */
1894 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE UINT32_C(0x6)
1895 /* Port PHY configuration change */
1896 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE UINT32_C(0x7)
1897 /* Function driver unloaded */
1898 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD UINT32_C(0x10)
1899 /* Function driver loaded */
1900 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD UINT32_C(0x11)
1901 /* Function FLR related processing has completed */
1902 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT UINT32_C(0x12)
1903 /* PF driver unloaded */
1904 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD UINT32_C(0x20)
1905 /* PF driver loaded */
1906 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD UINT32_C(0x21)
1907 /* VF Function Level Reset (FLR) */
1908 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR UINT32_C(0x30)
1909 /* VF MAC Address Change */
1910 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE UINT32_C(0x31)
1911 /* PF-VF communication channel status change. */
1912 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE UINT32_C(0x32)
1913 /* VF Configuration Change */
1914 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE UINT32_C(0x33)
1915 /* LLFC/PFC Configuration Change */
1916 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE UINT32_C(0x34)
1918 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR UINT32_C(0xff)
1919 uint32_t event_data2;
1920 /* Event specific data */
1924 * This value is written by the NIC such that it will be different for
1925 * each pass through the completion queue. The even passes will write 1.
1926 * The odd passes will write 0.
1928 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
1930 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
1931 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
1932 uint8_t timestamp_lo;
1933 /* 8-lsb timestamp from POR (100-msec resolution) */
1934 uint16_t timestamp_hi;
1935 /* 16-lsb timestamp from POR (100-msec resolution) */
1936 uint32_t event_data1;
1937 /* Event specific data */
1938 } __attribute__((packed));
1940 /* HWRM Asynchronous Event Completion Record for link status change (16 bytes) */
1942 struct hwrm_async_event_cmpl_link_status_change {
1944 /* unused1 is 10 b */
1946 * This field indicates the exact type of the completion. By convention,
1947 * the LSB identifies the length of the record in 16B units. Even values
1948 * indicate 16B records. Odd values indicate 32B records.
1950 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK UINT32_C(0x3f)
1951 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
1952 /* HWRM Asynchronous Event Information */
1953 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
1954 /* unused1 is 10 b */
1956 /* Identifiers of events. */
1957 /* Link status changed */
1958 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE UINT32_C(0x0)
1959 uint32_t event_data2;
1960 /* Event specific data */
1964 * This value is written by the NIC such that it will be different for
1965 * each pass through the completion queue. The even passes will write 1.
1966 * The odd passes will write 0.
1968 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V UINT32_C(0x1)
1970 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
1971 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
1972 uint8_t timestamp_lo;
1973 /* 8-lsb timestamp from POR (100-msec resolution) */
1974 uint16_t timestamp_hi;
1975 /* 16-lsb timestamp from POR (100-msec resolution) */
1976 uint32_t event_data1;
1977 /* Event specific data */
1978 /* Indicates link status change */
1979 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE UINT32_C(0x1)
1981 * If this bit set to 0, then it indicates that the link was up
1984 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN (UINT32_C(0x0) << 0)
1986 * If this bit is set to 1, then it indicates that the link was
1987 * down and it went up.
1989 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP (UINT32_C(0x1) << 0)
1990 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
1991 /* Indicates the physical port this link status change occur */
1992 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK UINT32_C(0xe)
1993 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1
1995 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff0)
1996 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4
1997 } __attribute__((packed));
1999 /* HWRM Asynchronous Event Completion Record for link MTU change (16 bytes) */
2001 struct hwrm_async_event_cmpl_link_mtu_change {
2003 /* unused1 is 10 b */
2005 * This field indicates the exact type of the completion. By convention,
2006 * the LSB identifies the length of the record in 16B units. Even values
2007 * indicate 16B records. Odd values indicate 32B records.
2009 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK UINT32_C(0x3f)
2010 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
2011 /* HWRM Asynchronous Event Information */
2012 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2013 /* unused1 is 10 b */
2015 /* Identifiers of events. */
2016 /* Link MTU changed */
2017 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE UINT32_C(0x1)
2018 uint32_t event_data2;
2019 /* Event specific data */
2023 * This value is written by the NIC such that it will be different for
2024 * each pass through the completion queue. The even passes will write 1.
2025 * The odd passes will write 0.
2027 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
2029 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
2030 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
2031 uint8_t timestamp_lo;
2032 /* 8-lsb timestamp from POR (100-msec resolution) */
2033 uint16_t timestamp_hi;
2034 /* 16-lsb timestamp from POR (100-msec resolution) */
2035 uint32_t event_data1;
2036 /* Event specific data */
2037 /* The new MTU of the link in bytes. */
2038 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK UINT32_C(0xffff)
2039 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
2040 } __attribute__((packed));
2042 /* HWRM Asynchronous Event Completion Record for link speed change (16 bytes) */
2044 struct hwrm_async_event_cmpl_link_speed_change {
2046 /* unused1 is 10 b */
2048 * This field indicates the exact type of the completion. By convention,
2049 * the LSB identifies the length of the record in 16B units. Even values
2050 * indicate 16B records. Odd values indicate 32B records.
2052 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK UINT32_C(0x3f)
2053 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
2054 /* HWRM Asynchronous Event Information */
2055 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2056 /* unused1 is 10 b */
2058 /* Identifiers of events. */
2059 /* Link speed changed */
2060 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE UINT32_C(0x2)
2061 uint32_t event_data2;
2062 /* Event specific data */
2066 * This value is written by the NIC such that it will be different for
2067 * each pass through the completion queue. The even passes will write 1.
2068 * The odd passes will write 0.
2070 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V UINT32_C(0x1)
2072 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
2073 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
2074 uint8_t timestamp_lo;
2075 /* 8-lsb timestamp from POR (100-msec resolution) */
2076 uint16_t timestamp_hi;
2077 /* 16-lsb timestamp from POR (100-msec resolution) */
2078 uint32_t event_data1;
2079 /* Event specific data */
2081 * When this bit is '1', the link was forced to the force_link_speed
2084 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE UINT32_C(0x1)
2085 /* The new link speed in 100 Mbps units. */
2086 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK UINT32_C(0xfffe)
2087 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT 1
2088 /* 100Mb link speed */
2089 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (UINT32_C(0x1) << 1)
2090 /* 1Gb link speed */
2091 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (UINT32_C(0xa) << 1)
2092 /* 2Gb link speed */
2093 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (UINT32_C(0x14) << 1)
2094 /* 2.5Gb link speed */
2095 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (UINT32_C(0x19) << 1)
2096 /* 10Gb link speed */
2097 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (UINT32_C(0x64) << 1)
2098 /* 20Mb link speed */
2099 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (UINT32_C(0xc8) << 1)
2100 /* 25Gb link speed */
2101 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (UINT32_C(0xfa) << 1)
2102 /* 40Gb link speed */
2103 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (UINT32_C(0x190) << 1)
2104 /* 50Gb link speed */
2105 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (UINT32_C(0x1f4) << 1)
2106 /* 100Gb link speed */
2107 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB (UINT32_C(0x3e8) << 1)
2108 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB
2110 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff0000)
2111 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT 16
2112 } __attribute__((packed));
2114 /* HWRM Asynchronous Event Completion Record for DCB Config change (16 bytes) */
2116 struct hwrm_async_event_cmpl_dcb_config_change {
2118 /* unused1 is 10 b */
2120 * This field indicates the exact type of the completion. By convention,
2121 * the LSB identifies the length of the record in 16B units. Even values
2122 * indicate 16B records. Odd values indicate 32B records.
2124 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK UINT32_C(0x3f)
2125 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
2126 /* HWRM Asynchronous Event Information */
2127 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2128 /* unused1 is 10 b */
2130 /* Identifiers of events. */
2131 /* DCB Configuration changed */
2132 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE UINT32_C(0x3)
2133 uint32_t event_data2;
2134 /* Event specific data */
2135 /* ETS configuration change */
2136 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS UINT32_C(0x1)
2137 /* PFC configuration change */
2138 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC UINT32_C(0x2)
2139 /* APP configuration change */
2140 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP UINT32_C(0x4)
2144 * This value is written by the NIC such that it will be different for
2145 * each pass through the completion queue. The even passes will write 1.
2146 * The odd passes will write 0.
2148 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V UINT32_C(0x1)
2150 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
2151 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
2152 uint8_t timestamp_lo;
2153 /* 8-lsb timestamp from POR (100-msec resolution) */
2154 uint16_t timestamp_hi;
2155 /* 16-lsb timestamp from POR (100-msec resolution) */
2156 uint32_t event_data1;
2157 /* Event specific data */
2159 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff)
2160 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
2161 /* Priority recommended for RoCE traffic */
2162 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK UINT32_C(0xff0000)
2163 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT 16
2165 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE (UINT32_C(0xff) << 16)
2166 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE
2167 /* Priority recommended for L2 traffic */
2168 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK UINT32_C(0xff000000)
2169 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT 24
2171 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE (UINT32_C(0xff) << 24)
2172 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE
2173 } __attribute__((packed));
2175 /* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */
2177 struct hwrm_async_event_cmpl_port_conn_not_allowed {
2179 /* unused1 is 10 b */
2181 * This field indicates the exact type of the completion. By convention,
2182 * the LSB identifies the length of the record in 16B units. Even values
2183 * indicate 16B records. Odd values indicate 32B records.
2185 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK UINT32_C(0x3f)
2186 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0
2187 /* HWRM Asynchronous Event Information */
2188 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2189 /* unused1 is 10 b */
2191 /* Identifiers of events. */
2192 /* Port connection not allowed */
2193 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED UINT32_C(0x4)
2194 uint32_t event_data2;
2195 /* Event specific data */
2199 * This value is written by the NIC such that it will be different for
2200 * each pass through the completion queue. The even passes will write 1.
2201 * The odd passes will write 0.
2203 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V UINT32_C(0x1)
2205 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK UINT32_C(0xfe)
2206 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
2207 uint8_t timestamp_lo;
2208 /* 8-lsb timestamp from POR (100-msec resolution) */
2209 uint16_t timestamp_hi;
2210 /* 16-lsb timestamp from POR (100-msec resolution) */
2211 uint32_t event_data1;
2212 /* Event specific data */
2214 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff)
2215 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
2217 * This value indicates the current port level enforcement policy for
2218 * the optics module when there is an optical module mismatch and port
2221 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK UINT32_C(0xff0000)
2222 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16
2223 /* No enforcement */
2224 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (UINT32_C(0x0) << 16)
2225 /* Disable Transmit side Laser. */
2226 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (UINT32_C(0x1) << 16)
2227 /* Raise a warning message. */
2228 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (UINT32_C(0x2) << 16)
2229 /* Power down the module. */
2230 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (UINT32_C(0x3) << 16)
2231 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
2232 } __attribute__((packed));
2234 /* HWRM Asynchronous Event Completion Record for link speed config not allowed (16 bytes) */
2236 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed {
2238 /* unused1 is 10 b */
2240 * This field indicates the exact type of the completion. By convention,
2241 * the LSB identifies the length of the record in 16B units. Even values
2242 * indicate 16B records. Odd values indicate 32B records.
2244 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK UINT32_C(0x3f)
2245 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT 0
2246 /* HWRM Asynchronous Event Information */
2247 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2248 /* unused1 is 10 b */
2250 /* Identifiers of events. */
2251 /* Link speed configuration was not allowed */
2252 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED UINT32_C(0x5)
2253 uint32_t event_data2;
2254 /* Event specific data */
2258 * This value is written by the NIC such that it will be different for
2259 * each pass through the completion queue. The even passes will write 1.
2260 * The odd passes will write 0.
2262 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V UINT32_C(0x1)
2264 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK UINT32_C(0xfe)
2265 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1
2266 uint8_t timestamp_lo;
2267 /* 8-lsb timestamp from POR (100-msec resolution) */
2268 uint16_t timestamp_hi;
2269 /* 16-lsb timestamp from POR (100-msec resolution) */
2270 uint32_t event_data1;
2271 /* Event specific data */
2273 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff)
2274 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
2275 } __attribute__((packed));
2277 /* HWRM Asynchronous Event Completion Record for link speed configuration change (16 bytes) */
2279 struct hwrm_async_event_cmpl_link_speed_cfg_change {
2281 /* unused1 is 10 b */
2283 * This field indicates the exact type of the completion. By convention,
2284 * the LSB identifies the length of the record in 16B units. Even values
2285 * indicate 16B records. Odd values indicate 32B records.
2287 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK UINT32_C(0x3f)
2288 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0
2289 /* HWRM Asynchronous Event Information */
2290 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2291 /* unused1 is 10 b */
2293 /* Identifiers of events. */
2294 /* Link speed configuration change */
2295 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE UINT32_C(0x6)
2296 uint32_t event_data2;
2297 /* Event specific data */
2301 * This value is written by the NIC such that it will be different for
2302 * each pass through the completion queue. The even passes will write 1.
2303 * The odd passes will write 0.
2305 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V UINT32_C(0x1)
2307 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
2308 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
2309 uint8_t timestamp_lo;
2310 /* 8-lsb timestamp from POR (100-msec resolution) */
2311 uint16_t timestamp_hi;
2312 /* 16-lsb timestamp from POR (100-msec resolution) */
2313 uint32_t event_data1;
2314 /* Event specific data */
2316 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff)
2317 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
2319 * If set to 1, it indicates that the supported link speeds
2320 * configuration on the port has changed. If set to 0, then there is no
2321 * change in supported link speeds configuration.
2323 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE UINT32_C(0x10000)
2325 * If set to 1, it indicates that the link speed configuration on the
2326 * port has become illegal or invalid. If set to 0, then the link speed
2327 * configuration on the port is legal or valid.
2329 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG UINT32_C(0x20000)
2330 } __attribute__((packed));
2332 /* HWRM Asynchronous Event Completion Record for port PHY configuration change (16 bytes) */
2334 struct hwrm_async_event_cmpl_port_phy_cfg_change {
2336 /* unused1 is 10 b */
2338 * This field indicates the exact type of the completion. By convention,
2339 * the LSB identifies the length of the record in 16B units. Even values
2340 * indicate 16B records. Odd values indicate 32B records.
2342 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK UINT32_C(0x3f)
2343 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT 0
2344 /* HWRM Asynchronous Event Information */
2345 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2346 /* unused1 is 10 b */
2348 /* Identifiers of events. */
2349 /* Port PHY configuration change */
2350 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE UINT32_C(0x7)
2351 uint32_t event_data2;
2352 /* Event specific data */
2356 * This value is written by the NIC such that it will be different for
2357 * each pass through the completion queue. The even passes will write 1.
2358 * The odd passes will write 0.
2360 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V UINT32_C(0x1)
2362 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
2363 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_SFT 1
2364 uint8_t timestamp_lo;
2365 /* 8-lsb timestamp from POR (100-msec resolution) */
2366 uint16_t timestamp_hi;
2367 /* 16-lsb timestamp from POR (100-msec resolution) */
2368 uint32_t event_data1;
2369 /* Event specific data */
2371 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff)
2372 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
2374 * If set to 1, it indicates that the FEC configuration on the port has
2375 * changed. If set to 0, then there is no change in FEC configuration.
2377 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE UINT32_C(0x10000)
2379 * If set to 1, it indicates that the EEE configuration on the port has
2380 * changed. If set to 0, then there is no change in EEE configuration on
2383 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE UINT32_C(0x20000)
2385 * If set to 1, it indicates that the pause configuration on the PHY has
2386 * changed. If set to 0, then there is no change in the pause
2387 * configuration on the PHY.
2389 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE UINT32_C(0x40000)
2390 } __attribute__((packed));
2392 /* HWRM Asynchronous Event Completion Record for Function Driver Unload (16 bytes) */
2394 struct hwrm_async_event_cmpl_func_drvr_unload {
2396 /* unused1 is 10 b */
2398 * This field indicates the exact type of the completion. By convention,
2399 * the LSB identifies the length of the record in 16B units. Even values
2400 * indicate 16B records. Odd values indicate 32B records.
2402 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK UINT32_C(0x3f)
2403 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
2404 /* HWRM Asynchronous Event Information */
2405 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2406 /* unused1 is 10 b */
2408 /* Identifiers of events. */
2409 /* Function driver unloaded */
2410 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD UINT32_C(0x10)
2411 uint32_t event_data2;
2412 /* Event specific data */
2416 * This value is written by the NIC such that it will be different for
2417 * each pass through the completion queue. The even passes will write 1.
2418 * The odd passes will write 0.
2420 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
2422 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
2423 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
2424 uint8_t timestamp_lo;
2425 /* 8-lsb timestamp from POR (100-msec resolution) */
2426 uint16_t timestamp_hi;
2427 /* 16-lsb timestamp from POR (100-msec resolution) */
2428 uint32_t event_data1;
2429 /* Event specific data */
2431 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff)
2432 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
2433 } __attribute__((packed));
2435 /* HWRM Asynchronous Event Completion Record for Function Driver load (16 bytes) */
2437 struct hwrm_async_event_cmpl_func_drvr_load {
2439 /* unused1 is 10 b */
2441 * This field indicates the exact type of the completion. By convention,
2442 * the LSB identifies the length of the record in 16B units. Even values
2443 * indicate 16B records. Odd values indicate 32B records.
2445 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK UINT32_C(0x3f)
2446 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
2447 /* HWRM Asynchronous Event Information */
2448 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2449 /* unused1 is 10 b */
2451 /* Identifiers of events. */
2452 /* Function driver loaded */
2453 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD UINT32_C(0x11)
2454 uint32_t event_data2;
2455 /* Event specific data */
2459 * This value is written by the NIC such that it will be different for
2460 * each pass through the completion queue. The even passes will write 1.
2461 * The odd passes will write 0.
2463 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
2465 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
2466 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
2467 uint8_t timestamp_lo;
2468 /* 8-lsb timestamp from POR (100-msec resolution) */
2469 uint16_t timestamp_hi;
2470 /* 16-lsb timestamp from POR (100-msec resolution) */
2471 uint32_t event_data1;
2472 /* Event specific data */
2474 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff)
2475 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
2476 } __attribute__((packed));
2478 /* HWRM Asynchronous Event Completion Record to indicate completion of FLR related processing (16 bytes) */
2480 struct hwrm_async_event_cmpl_func_flr_proc_cmplt {
2482 /* unused1 is 10 b */
2484 * This field indicates the exact type of the completion. By convention,
2485 * the LSB identifies the length of the record in 16B units. Even values
2486 * indicate 16B records. Odd values indicate 32B records.
2488 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK UINT32_C(0x3f)
2489 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT 0
2490 /* HWRM Asynchronous Event Information */
2491 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2492 /* unused1 is 10 b */
2494 /* Identifiers of events. */
2495 /* Function FLR related processing has completed */
2496 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT UINT32_C(0x12)
2497 uint32_t event_data2;
2498 /* Event specific data */
2502 * This value is written by the NIC such that it will be different for
2503 * each pass through the completion queue. The even passes will write 1.
2504 * The odd passes will write 0.
2506 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V UINT32_C(0x1)
2508 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK UINT32_C(0xfe)
2509 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1
2510 uint8_t timestamp_lo;
2511 /* 8-lsb timestamp from POR (100-msec resolution) */
2512 uint16_t timestamp_hi;
2513 /* 16-lsb timestamp from POR (100-msec resolution) */
2514 uint32_t event_data1;
2515 /* Event specific data */
2517 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff)
2518 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT 0
2519 } __attribute__((packed));
2521 /* HWRM Asynchronous Event Completion Record for PF Driver Unload (16 bytes) */
2523 struct hwrm_async_event_cmpl_pf_drvr_unload {
2525 /* unused1 is 10 b */
2527 * This field indicates the exact type of the completion. By convention,
2528 * the LSB identifies the length of the record in 16B units. Even values
2529 * indicate 16B records. Odd values indicate 32B records.
2531 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK UINT32_C(0x3f)
2532 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
2533 /* HWRM Asynchronous Event Information */
2534 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2535 /* unused1 is 10 b */
2537 /* Identifiers of events. */
2538 /* PF driver unloaded */
2539 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD UINT32_C(0x20)
2540 uint32_t event_data2;
2541 /* Event specific data */
2545 * This value is written by the NIC such that it will be different for
2546 * each pass through the completion queue. The even passes will write 1.
2547 * The odd passes will write 0.
2549 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
2551 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
2552 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
2553 uint8_t timestamp_lo;
2554 /* 8-lsb timestamp from POR (100-msec resolution) */
2555 uint16_t timestamp_hi;
2556 /* 16-lsb timestamp from POR (100-msec resolution) */
2557 uint32_t event_data1;
2558 /* Event specific data */
2560 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff)
2561 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
2562 /* Indicates the physical port this pf belongs to */
2563 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK UINT32_C(0x70000)
2564 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
2565 } __attribute__((packed));
2567 /* HWRM Asynchronous Event Completion Record for PF Driver load (16 bytes) */
2569 struct hwrm_async_event_cmpl_pf_drvr_load {
2571 /* unused1 is 10 b */
2573 * This field indicates the exact type of the completion. By convention,
2574 * the LSB identifies the length of the record in 16B units. Even values
2575 * indicate 16B records. Odd values indicate 32B records.
2577 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK UINT32_C(0x3f)
2578 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
2579 /* HWRM Asynchronous Event Information */
2580 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2581 /* unused1 is 10 b */
2583 /* Identifiers of events. */
2584 /* PF driver loaded */
2585 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD UINT32_C(0x21)
2586 uint32_t event_data2;
2587 /* Event specific data */
2591 * This value is written by the NIC such that it will be different for
2592 * each pass through the completion queue. The even passes will write 1.
2593 * The odd passes will write 0.
2595 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
2597 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
2598 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
2599 uint8_t timestamp_lo;
2600 /* 8-lsb timestamp from POR (100-msec resolution) */
2601 uint16_t timestamp_hi;
2602 /* 16-lsb timestamp from POR (100-msec resolution) */
2603 uint32_t event_data1;
2604 /* Event specific data */
2606 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff)
2607 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
2608 /* Indicates the physical port this pf belongs to */
2609 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK UINT32_C(0x70000)
2610 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
2611 } __attribute__((packed));
2613 /* HWRM Asynchronous Event Completion Record for VF FLR (16 bytes) */
2615 struct hwrm_async_event_cmpl_vf_flr {
2617 /* unused1 is 10 b */
2619 * This field indicates the exact type of the completion. By convention,
2620 * the LSB identifies the length of the record in 16B units. Even values
2621 * indicate 16B records. Odd values indicate 32B records.
2623 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK UINT32_C(0x3f)
2624 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
2625 /* HWRM Asynchronous Event Information */
2626 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2627 /* unused1 is 10 b */
2629 /* Identifiers of events. */
2630 /* VF Function Level Reset (FLR) */
2631 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
2632 uint32_t event_data2;
2633 /* Event specific data */
2637 * This value is written by the NIC such that it will be different for
2638 * each pass through the completion queue. The even passes will write 1.
2639 * The odd passes will write 0.
2641 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
2643 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
2644 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
2645 uint8_t timestamp_lo;
2646 /* 8-lsb timestamp from POR (100-msec resolution) */
2647 uint16_t timestamp_hi;
2648 /* 16-lsb timestamp from POR (100-msec resolution) */
2649 uint32_t event_data1;
2650 /* Event specific data */
2652 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK UINT32_C(0xffff)
2653 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
2654 } __attribute__((packed));
2656 /* HWRM Asynchronous Event Completion Record for VF MAC Addr change (16 bytes) */
2658 struct hwrm_async_event_cmpl_vf_mac_addr_change {
2660 /* unused1 is 10 b */
2662 * This field indicates the exact type of the completion. By convention,
2663 * the LSB identifies the length of the record in 16B units. Even values
2664 * indicate 16B records. Odd values indicate 32B records.
2666 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK UINT32_C(0x3f)
2667 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
2668 /* HWRM Asynchronous Event Information */
2669 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2670 /* unused1 is 10 b */
2672 /* Identifiers of events. */
2673 /* VF MAC Address Change */
2674 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE UINT32_C(0x31)
2675 uint32_t event_data2;
2676 /* Event specific data */
2680 * This value is written by the NIC such that it will be different for
2681 * each pass through the completion queue. The even passes will write 1.
2682 * The odd passes will write 0.
2684 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V UINT32_C(0x1)
2686 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
2687 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
2688 uint8_t timestamp_lo;
2689 /* 8-lsb timestamp from POR (100-msec resolution) */
2690 uint16_t timestamp_hi;
2691 /* 16-lsb timestamp from POR (100-msec resolution) */
2692 uint32_t event_data1;
2693 /* Event specific data */
2695 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK UINT32_C(0xffff)
2696 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0
2697 } __attribute__((packed));
2699 /* HWRM Asynchronous Event Completion Record for PF-VF communication status change (16 bytes) */
2701 struct hwrm_async_event_cmpl_pf_vf_comm_status_change {
2703 /* unused1 is 10 b */
2705 * This field indicates the exact type of the completion. By convention,
2706 * the LSB identifies the length of the record in 16B units. Even values
2707 * indicate 16B records. Odd values indicate 32B records.
2709 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK UINT32_C(0x3f)
2710 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT 0
2711 /* HWRM Asynchronous Event Information */
2712 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2713 /* unused1 is 10 b */
2715 /* Identifiers of events. */
2716 /* PF-VF communication channel status change. */
2717 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE UINT32_C(0x32)
2718 uint32_t event_data2;
2719 /* Event specific data */
2723 * This value is written by the NIC such that it will be different for
2724 * each pass through the completion queue. The even passes will write 1.
2725 * The odd passes will write 0.
2727 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V UINT32_C(0x1)
2729 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
2730 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1
2731 uint8_t timestamp_lo;
2732 /* 8-lsb timestamp from POR (100-msec resolution) */
2733 uint16_t timestamp_hi;
2734 /* 16-lsb timestamp from POR (100-msec resolution) */
2735 uint32_t event_data1;
2736 /* Event specific data */
2738 * If this bit is set to 1, then it indicates that the PF-VF
2739 * communication was lost and it is established. If this bit set to 0,
2740 * then it indicates that the PF-VF communication was established and it
2743 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED UINT32_C(0x1)
2744 } __attribute__((packed));
2746 /* HWRM Asynchronous Event Completion Record for VF configuration change (16 bytes) */
2748 struct hwrm_async_event_cmpl_vf_cfg_change {
2750 /* unused1 is 10 b */
2752 * This field indicates the exact type of the completion. By convention,
2753 * the LSB identifies the length of the record in 16B units. Even values
2754 * indicate 16B records. Odd values indicate 32B records.
2756 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK UINT32_C(0x3f)
2757 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
2758 /* HWRM Asynchronous Event Information */
2759 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2760 /* unused1 is 10 b */
2762 /* Identifiers of events. */
2763 /* VF Configuration Change */
2764 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE UINT32_C(0x33)
2765 uint32_t event_data2;
2766 /* Event specific data */
2770 * This value is written by the NIC such that it will be different for
2771 * each pass through the completion queue. The even passes will write 1.
2772 * The odd passes will write 0.
2774 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
2776 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
2777 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
2778 uint8_t timestamp_lo;
2779 /* 8-lsb timestamp from POR (100-msec resolution) */
2780 uint16_t timestamp_hi;
2781 /* 16-lsb timestamp from POR (100-msec resolution) */
2782 uint32_t event_data1;
2784 * Each flag provided in this field indicates a specific VF
2785 * configuration change. At least one of these flags shall be set to 1
2786 * when an asynchronous event completion of this type is provided by the
2790 * If this bit is set to 1, then the value of MTU was changed on this
2791 * VF. If set to 0, then this bit should be ignored.
2793 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE UINT32_C(0x1)
2795 * If this bit is set to 1, then the value of MRU was changed on this
2796 * VF. If set to 0, then this bit should be ignored.
2798 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE UINT32_C(0x2)
2800 * If this bit is set to 1, then the value of default MAC address was
2801 * changed on this VF. If set to 0, then this bit should be ignored.
2803 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE UINT32_C(0x4)
2805 * If this bit is set to 1, then the value of default VLAN was changed
2806 * on this VF. If set to 0, then this bit should be ignored.
2808 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE UINT32_C(0x8)
2809 } __attribute__((packed));
2811 /* HWRM Asynchronous Event Completion Record for llfc pfc status change (16 bytes) */
2813 struct hwrm_async_event_cmpl_llfc_pfc_change {
2815 /* unused1 is 10 b */
2817 * This field indicates the exact type of the completion. By convention,
2818 * the LSB identifies the length of the record in 16B units. Even values
2819 * indicate 16B records. Odd values indicate 32B records.
2821 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK UINT32_C(0x3f)
2822 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
2823 /* HWRM Asynchronous Event Information */
2824 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2825 /* unused1 is 10 b */
2827 /* Identifiers of events. */
2828 /* LLFC/PFC Configuration Change */
2829 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE UINT32_C(0x34)
2830 uint32_t event_data2;
2831 /* Event specific data */
2835 * This value is written by the NIC such that it will be different for
2836 * each pass through the completion queue. The even passes will write 1.
2837 * The odd passes will write 0.
2839 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
2841 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
2842 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_SFT 1
2843 uint8_t timestamp_lo;
2844 /* 8-lsb timestamp from POR (100-msec resolution) */
2845 uint16_t timestamp_hi;
2846 /* 16-lsb timestamp from POR (100-msec resolution) */
2847 uint32_t event_data1;
2848 /* Event specific data */
2849 /* Indicates llfc pfc status change */
2850 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK UINT32_C(0x3)
2851 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT 0
2852 /* If this field set to 1, then it indicates that llfc is enabled. */
2853 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC (UINT32_C(0x1) << 0)
2854 /* If this field is set to 2, then it indicates that pfc is enabled. */
2855 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC (UINT32_C(0x2) << 0)
2856 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LAST HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC
2857 /* Indicates the physical port this llfc pfc change occur */
2858 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK UINT32_C(0x1c)
2859 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_SFT 2
2861 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0x1fffe0)
2862 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_SFT 5
2863 } __attribute__((packed));
2865 /* HWRM Asynchronous Event Completion Record for HWRM Error (16 bytes) */
2867 struct hwrm_async_event_cmpl_hwrm_error {
2869 /* unused1 is 10 b */
2871 * This field indicates the exact type of the completion. By convention,
2872 * the LSB identifies the length of the record in 16B units. Even values
2873 * indicate 16B records. Odd values indicate 32B records.
2875 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK UINT32_C(0x3f)
2876 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
2877 /* HWRM Asynchronous Event Information */
2878 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
2879 /* unused1 is 10 b */
2881 /* Identifiers of events. */
2883 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR UINT32_C(0xff)
2884 uint32_t event_data2;
2885 /* Event specific data */
2886 /* Severity of HWRM Error */
2887 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK UINT32_C(0xff)
2888 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
2890 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING UINT32_C(0x0)
2891 /* Non-fatal Error */
2892 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL UINT32_C(0x1)
2894 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL UINT32_C(0x2)
2895 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
2899 * This value is written by the NIC such that it will be different for
2900 * each pass through the completion queue. The even passes will write 1.
2901 * The odd passes will write 0.
2903 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
2905 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
2906 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
2907 uint8_t timestamp_lo;
2908 /* 8-lsb timestamp from POR (100-msec resolution) */
2909 uint16_t timestamp_hi;
2910 /* 16-lsb timestamp from POR (100-msec resolution) */
2911 uint32_t event_data1;
2912 /* Event specific data */
2913 /* Time stamp for error event */
2914 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP UINT32_C(0x1)
2915 } __attribute__((packed));
2917 /* Door Bell Formats */
2919 * Description: The backup version of the packet must be valid in the TX ring
2920 * before the push doorbell is written to the chip. The first 32b and the BD
2921 * portion of the push doorbell must be written in multiples of 32b units on the
2922 * PCI interface. The data portion of the push doorbell may be written in
2923 * multiples of 8b units on the PCI interface. A push update must contain
2924 * exactly one push packet. The backup version of the packet must start with a
2925 * long (32B) BD and the BDs must be less than or equal to 16x16B units long.
2928 * Note: This door bell format is used by the driver when it wants to push a
2929 * packet into the chip for super-fast transmission. This pushes a partial BD
2930 * and the packet data into the chip. If the chip has room, it will transmit the
2931 * packet. If the chip dosn't have room, it will read the BD and packet data
2932 * from host memory as a normal packet.
2934 /* TX Door Bell Format (4 bytes) */
2936 struct tx_doorbell {
2939 * This value indicates the type of door bell operation that is begin
2940 * requested. This value is '0' for TX door bell operations.
2943 * BD Index of next BD that will be used to transmit data on the TX ring
2944 * mapped to this door bell. NIC may read and process all BDs up to, but
2945 * not including this index.
2947 #define TX_DOORBELL_IDX_MASK UINT32_C(0xffffff)
2948 #define TX_DOORBELL_IDX_SFT 0
2949 /* reserved is 4 b */
2950 #define TX_DOORBELL_RESERVED_MASK UINT32_C(0xf000000)
2951 #define TX_DOORBELL_RESERVED_SFT 24
2953 * This value indicates the type of door bell operation that is begin
2954 * requested. This value is '0' for TX door bell operations.
2956 #define TX_DOORBELL_KEY_MASK UINT32_C(0xf0000000)
2957 #define TX_DOORBELL_KEY_SFT 28
2959 #define TX_DOORBELL_KEY_TX (UINT32_C(0x0) << 28)
2960 } __attribute__((packed));
2962 /* RX Door Bell Format (4 bytes) */
2964 struct rx_doorbell {
2967 * This value indicates the type of door bell operation that is begin
2968 * requested. This value is '1' for RX door bell operations.
2971 * BD Index of next BD that will be used for an empty receive buffer on
2972 * the RX ring mapped to this door bell. NIC may read and process all
2973 * BDs up to, but not including this index.
2975 #define RX_DOORBELL_IDX_MASK UINT32_C(0xffffff)
2976 #define RX_DOORBELL_IDX_SFT 0
2977 /* reserved is 4 b */
2978 #define RX_DOORBELL_RESERVED_MASK UINT32_C(0xf000000)
2979 #define RX_DOORBELL_RESERVED_SFT 24
2981 * This value indicates the type of door bell operation that is begin
2982 * requested. This value is '1' for RX door bell operations.
2984 #define RX_DOORBELL_KEY_MASK UINT32_C(0xf0000000)
2985 #define RX_DOORBELL_KEY_SFT 28
2987 #define RX_DOORBELL_KEY_RX (UINT32_C(0x1) << 28)
2988 } __attribute__((packed));
2990 /* CMP Door Bell Format (4 bytes) */
2992 struct cmpl_doorbell {
2993 uint32_t key_mask_valid_idx;
2995 * This value indicates the type of door bell operation that is begin
2996 * requested. This value is '2' for CMP door bell operations.
2999 * BD Index of the most recently handed completion record on the
3000 * completion ring mapped to this door bell. NIC may write this location
3001 * again with a new completion.
3003 #define CMPL_DOORBELL_IDX_MASK UINT32_C(0xffffff)
3004 #define CMPL_DOORBELL_IDX_SFT 0
3005 /* reserved is 2 b */
3006 #define CMPL_DOORBELL_RESERVED_MASK UINT32_C(0x3000000)
3007 #define CMPL_DOORBELL_RESERVED_SFT 24
3009 * This indicates if the BDIDX value is valid for this update when it is
3010 * '1'. When it is '0', the BDIDX value should be ignored.
3012 #define CMPL_DOORBELL_IDX_VALID UINT32_C(0x4000000)
3014 * This bit indicates the new interrupt mask state for the interrupt
3015 * associated with the BDIDX. A '1', means the interrupt is to be
3016 * masked. A '0' indicates the interrupt is to be unmasked.
3018 #define CMPL_DOORBELL_MASK UINT32_C(0x8000000)
3020 * This value indicates the type of door bell operation that is begin
3021 * requested. This value is '2' for CMP door bell operations.
3023 #define CMPL_DOORBELL_KEY_MASK UINT32_C(0xf0000000)
3024 #define CMPL_DOORBELL_KEY_SFT 28
3025 /* Completion Operation */
3026 #define CMPL_DOORBELL_KEY_CMPL (UINT32_C(0x2) << 28)
3027 } __attribute__((packed));
3029 /* Status Door Bell Format (4 bytes) */
3031 struct status_doorbell {
3034 * This value indicates the type of door bell operation that is begin
3035 * requested. This value is '3' for Status door bell operations.
3038 * BD Index of the status record for which space is now available to the
3042 * While there is no actual BD associated with the index, the similar
3043 * scheme is being used to communicate to the NIC that space is
3044 * available for status completions.
3046 #define STATUS_DOORBELL_IDX_MASK UINT32_C(0xffffff)
3047 #define STATUS_DOORBELL_IDX_SFT 0
3048 /* reserved is 4 b */
3049 #define STATUS_DOORBELL_RESERVED_MASK UINT32_C(0xf000000)
3050 #define STATUS_DOORBELL_RESERVED_SFT 24
3052 * This value indicates the type of door bell operation that is begin
3053 * requested. This value is '3' for Status door bell operations.
3055 #define STATUS_DOORBELL_KEY_MASK UINT32_C(0xf0000000)
3056 #define STATUS_DOORBELL_KEY_SFT 28
3057 /* Status Operation */
3058 #define STATUS_DOORBELL_KEY_STAT (UINT32_C(0x3) << 28)
3059 } __attribute__((packed));
3061 /* Push w/32B BD Door Bell Format (32 bytes) */
3063 struct push32_doorbell {
3064 uint32_t key_sz_idx;
3066 * This value indicates the type of door bell operation that is begin
3067 * requested. This value is 4 for push door bell operations.
3070 * This is the BD Index of last BD of the push packet that will be used
3071 * to transmit data on the TX ring mapped to this door bell.
3073 #define PUSH32_DOORBELL_IDX_MASK UINT32_C(0xffffff)
3074 #define PUSH32_DOORBELL_IDX_SFT 0
3076 * This is the number of 16B BDs spaces consumed in the TX Ring by the
3077 * "backup" version of the packet being pushed. A value of 1 is invalid
3078 * since backup must start with a long 32B BE. A value of 2 indicates
3079 * just the first 32B BE. A value of 3 indicates 32B+16B BD. etc. A
3080 * value of 0 indicates 16x16B BD spaces are consumed.
3082 #define PUSH32_DOORBELL_SZ_MASK UINT32_C(0xf000000)
3083 #define PUSH32_DOORBELL_SZ_SFT 24
3085 * This value indicates the type of door bell operation that is begin
3086 * requested. This value is 4 for push door bell operations.
3088 #define PUSH32_DOORBELL_KEY_MASK UINT32_C(0xf0000000)
3089 #define PUSH32_DOORBELL_KEY_SFT 28
3090 /* Push Operation */
3091 #define PUSH32_DOORBELL_KEY_PUSH (UINT32_C(0x4) << 28)
3092 uint16_t flags_type;
3094 * All bits in this field must be valid on the first BD of a packet.
3095 * Only the packet_end bit must be valid for the remaining BDs of a
3098 /* This value identifies the type of buffer descriptor. */
3099 #define PUSH32_DOORBELL_TYPE_MASK UINT32_C(0x3f)
3100 #define PUSH32_DOORBELL_TYPE_SFT 0
3102 * Indicates that this BD is 32B long and is used for normal L2
3103 * packet transmission.
3105 #define PUSH32_DOORBELL_TYPE_TX_BD_LONG UINT32_C(0x10)
3107 * If set to 1, the packet ends with the data in the buffer pointed to
3108 * by this descriptor. This flag must be valid on every BD. This bit
3109 * must be set on all push doorbells.
3111 #define PUSH32_DOORBELL_FLAGS_PACKET_END UINT32_C(0x40)
3113 * If set to 1, the device will not generate a completion for this
3114 * transmit packet unless there is an error in it's processing. If this
3115 * bit is set to 0, then the packet will be completed normally. This bit
3116 * must be valid only on the first BD of a packet.
3118 #define PUSH32_DOORBELL_FLAGS_NO_CMPL UINT32_C(0x80)
3120 * This value must match the sz field in the first 32b of the push
3121 * operation except that if 16x16B BD locations are consumed in the ring
3122 * by this packet, then this value must be 16 (not zero).
3124 #define PUSH32_DOORBELL_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
3125 #define PUSH32_DOORBELL_FLAGS_BD_CNT_SFT 8
3127 * This value is a hint for the length of the entire packet. It is used
3128 * by the chip to optimize internal processing. The packet will be
3129 * dropped if the hint is too short. This field is valid only on the
3130 * first BD of a packet.
3132 #define PUSH32_DOORBELL_FLAGS_LHINT_MASK UINT32_C(0x6000)
3133 #define PUSH32_DOORBELL_FLAGS_LHINT_SFT 13
3134 /* indicates packet length < 512B */
3135 #define PUSH32_DOORBELL_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
3136 /* indicates 512 <= packet length < 1KB */
3137 #define PUSH32_DOORBELL_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
3138 /* indicates 1KB <= packet length < 2KB */
3139 #define PUSH32_DOORBELL_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
3140 /* indicates packet length >= 2KB */
3141 #define PUSH32_DOORBELL_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
3142 #define PUSH32_DOORBELL_FLAGS_LHINT_LAST PUSH32_DOORBELL_FLAGS_LHINT_GTE2K
3144 * If set to 1, the device immediately updates the Send Consumer Index
3145 * after the buffer associated with this descriptor has been transferred
3146 * via DMA to NIC memory from host memory. An interrupt may or may not
3147 * be generated according to the state of the interrupt avoidance
3148 * mechanisms. If this bit is set to 0, then the Consumer Index is only
3149 * updated as soon as one of the host interrupt coalescing conditions
3150 * has been met. This bit must be valid on the first BD of a packet.
3152 #define PUSH32_DOORBELL_FLAGS_COAL_NOW UINT32_C(0x8000)
3154 * All bits in this field must be valid on the first BD of a packet.
3155 * Only the packet_end bit must be valid for the remaining BDs of a
3158 #define PUSH32_DOORBELL_FLAGS_MASK UINT32_C(0xffc0)
3159 #define PUSH32_DOORBELL_FLAGS_SFT 6
3162 * This is the length of the host physical buffer this BD describes in
3163 * bytes. This field must be valid on all BDs of a packet.
3167 * The opaque data field is pass through to the completion and can be
3168 * used for any data that the driver wants to associate with the
3169 * transmit BD. This field must be valid on the first BD of a packet.
3173 * All bits in this field must be valid on the first BD of a packet.
3174 * Their value on other BDs of the packet will be ignored.
3177 * If set to 1, the controller replaces the TCP/UPD checksum fields of
3178 * normal TCP/UPD checksum, or the inner TCP/UDP checksum field of the
3179 * encapsulated TCP/UDP packets with the hardware calculated TCP/UDP
3180 * checksum for the packet associated with this descriptor. The flag is
3181 * ignored if the LSO flag is set. This bit must be valid on the first
3184 #define PUSH32_DOORBELL_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
3186 * If set to 1, the controller replaces the IP checksum of the normal
3187 * packets, or the inner IP checksum of the encapsulated packets with
3188 * the hardware calculated IP checksum for the packet associated with
3189 * this descriptor. This bit must be valid on the first BD of a packet.
3191 #define PUSH32_DOORBELL_LFLAGS_IP_CHKSUM UINT32_C(0x2)
3193 * If set to 1, the controller will not append an Ethernet CRC to the
3194 * end of the frame. This bit must be valid on the first BD of a packet.
3195 * Packet must be 64B or longer when this flag is set. It is not useful
3196 * to use this bit with any form of TX offload such as CSO or LSO. The
3197 * intent is that the packet from the host already has a valid Ethernet
3198 * CRC on the packet.
3200 #define PUSH32_DOORBELL_LFLAGS_NOCRC UINT32_C(0x4)
3202 * If set to 1, the device will record the time at which the packet was
3203 * actually transmitted at the TX MAC. This bit must be valid on the
3204 * first BD of a packet.
3206 #define PUSH32_DOORBELL_LFLAGS_STAMP UINT32_C(0x8)
3208 * If set to 1, The controller replaces the tunnel IP checksum field
3209 * with hardware calculated IP checksum for the IP header of the packet
3210 * associated with this descriptor. For outer UDP checksum, global outer
3211 * UDP checksum TE_NIC register needs to be enabled. If the global outer
3212 * UDP checksum TE_NIC register bit is set, outer UDP checksum will be
3213 * calculated for the following cases: 1. Packets with tcp_udp_chksum
3214 * flag set to offload checksum for inner packet AND the inner packet is
3215 * TCP/UDP. If the inner packet is ICMP for example (non-TCP/UDP), even
3216 * if the tcp_udp_chksum is set, the outer UDP checksum will not be
3217 * calculated. 2. Packets with lso flag set which implies inner TCP
3218 * checksum calculation as part of LSO operation.
3220 #define PUSH32_DOORBELL_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
3222 * If set to 1, the device will treat this packet with LSO(Large Send
3223 * Offload) processing for both normal or encapsulated packets, which is
3224 * a form of TCP segmentation. When this bit is 1, the hdr_size and mss
3225 * fields must be valid. The driver doesn't need to set t_ip_chksum,
3226 * ip_chksum, and tcp_udp_chksum flags since the controller will replace
3227 * the appropriate checksum fields for segmented packets. When this bit
3228 * is 1, the hdr_size and mss fields must be valid.
3230 #define PUSH32_DOORBELL_LFLAGS_LSO UINT32_C(0x20)
3232 * If set to zero when LSO is '1', then the IPID will be treated as a
3233 * 16b number and will be wrapped if it exceeds a value of 0xffff. If
3234 * set to one when LSO is '1', then the IPID will be treated as a 15b
3235 * number and will be wrapped if it exceeds a value 0f 0x7fff.
3237 #define PUSH32_DOORBELL_LFLAGS_IPID_FMT UINT32_C(0x40)
3239 * If set to zero when LSO is '1', then the IPID of the tunnel IP header
3240 * will not be modified during LSO operations. If set to one when LSO is
3241 * '1', then the IPID of the tunnel IP header will be incremented for
3242 * each subsequent segment of an LSO operation. The flag is ignored if
3243 * the LSO packet is a normal (non-tunneled) TCP packet.
3245 #define PUSH32_DOORBELL_LFLAGS_T_IPID UINT32_C(0x80)
3247 * If set to '1', then the RoCE ICRC will be appended to the packet.
3248 * Packet must be a valid RoCE format packet.
3250 #define PUSH32_DOORBELL_LFLAGS_ROCE_CRC UINT32_C(0x100)
3252 * If set to '1', then the FCoE CRC will be appended to the packet.
3253 * Packet must be a valid FCoE format packet.
3255 #define PUSH32_DOORBELL_LFLAGS_FCOE_CRC UINT32_C(0x200)
3258 * When LSO is '1', this field must contain the offset of the TCP
3259 * payload from the beginning of the packet in as 16b words. In case of
3260 * encapsulated/tunneling packet, this field contains the offset of the
3261 * inner TCP payload from beginning of the packet as 16-bit words. This
3262 * value must be valid on the first BD of a packet.
3264 #define PUSH32_DOORBELL_HDR_SIZE_MASK UINT32_C(0x1ff)
3265 #define PUSH32_DOORBELL_HDR_SIZE_SFT 0
3268 * This is the MSS value that will be used to do the LSO processing. The
3269 * value is the length in bytes of the TCP payload for each segment
3270 * generated by the LSO operation. This value must be valid on the first
3273 #define PUSH32_DOORBELL_MSS_MASK UINT32_C(0x7fff)
3274 #define PUSH32_DOORBELL_MSS_SFT 0
3276 uint16_t cfa_action;
3278 * This value selects a CFA action to perform on the packet. Set this
3279 * value to zero if no CFA action is desired. This value must be valid
3280 * on the first BD of a packet.
3284 * This value is action meta-data that defines CFA edit operations that
3285 * are done in addition to any action editing.
3287 /* When key=1, This is the VLAN tag VID value. */
3288 #define PUSH32_DOORBELL_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
3289 #define PUSH32_DOORBELL_CFA_META_VLAN_VID_SFT 0
3290 /* When key=1, This is the VLAN tag DE value. */
3291 #define PUSH32_DOORBELL_CFA_META_VLAN_DE UINT32_C(0x1000)
3292 /* When key=1, This is the VLAN tag PRI value. */
3293 #define PUSH32_DOORBELL_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
3294 #define PUSH32_DOORBELL_CFA_META_VLAN_PRI_SFT 13
3295 /* When key=1, This is the VLAN tag TPID select value. */
3296 #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
3297 #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_SFT 16
3299 #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
3301 #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
3303 #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
3305 #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
3307 #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
3308 /* Value programmed in CFA VLANTPID register. */
3309 #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
3310 #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_LAST PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPIDCFG
3311 /* When key=1, This is the VLAN tag TPID select value. */
3312 #define PUSH32_DOORBELL_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
3313 #define PUSH32_DOORBELL_CFA_META_VLAN_RESERVED_SFT 19
3315 * This field identifies the type of edit to be performed on the packet.
3316 * This value must be valid on the first BD of a packet.
3318 #define PUSH32_DOORBELL_CFA_META_KEY_MASK UINT32_C(0xf0000000)
3319 #define PUSH32_DOORBELL_CFA_META_KEY_SFT 28
3321 #define PUSH32_DOORBELL_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
3323 * - meta[17:16] - TPID select value (0 = 0x8100). - meta[15:12]
3324 * - PRI/DE value. - meta[11:0] - VID value.
3326 #define PUSH32_DOORBELL_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
3327 #define PUSH32_DOORBELL_CFA_META_KEY_LAST PUSH32_DOORBELL_CFA_META_KEY_VLAN_TAG
3330 * This is the data for the push packet. If the packet data does not fit
3331 * in the first pass, data writing can continue at offset 4 of the
3332 * doorbell for up to 4 additional passes for a total data size of 512B
3335 } __attribute__((packed));
3337 /* Doorbell Structures */
3339 * Description: This is the RoCE 32b Doorbell format. The host writes this
3340 * message format directly to byte offset 8 of the appropriate doorbell page.
3342 /* 64b Doorbell Format (8 bytes) */
3347 * This value is the index being written. For SQ, RQ, SRQ, this is the
3348 * producer index and should be the queue index of the last WQE written
3349 * plus 1. For CQ, this is the consumer index and should be the index of
3350 * the last CQE processed plus 1.
3352 #define DBR_DBR_INDEX_MASK UINT32_C(0xfffff)
3353 #define DBR_DBR_INDEX_SFT 0
3354 #define DBR_DBR_RESERVED12_MASK UINT32_C(0xfff00000)
3355 #define DBR_DBR_RESERVED12_SFT 20
3357 /* This value identifies the type of doorbell being written. */
3359 * This value identifies the resource that the doorbell is intended to
3360 * notify. For SQ and RQ, this is the QPID. For SRQ, this is the SID.
3361 * For CQ, this is the CID. Bits [19:16] of this values must be zero for
3364 #define DBR_DBR_XID_MASK UINT32_C(0xfffff)
3365 #define DBR_DBR_XID_SFT 0
3366 #define DBR_DBR_RESERVED8_MASK UINT32_C(0xff00000)
3367 #define DBR_DBR_RESERVED8_SFT 20
3368 /* This value identifies the type of doorbell being written. */
3369 #define DBR_DBR_TYPE_MASK UINT32_C(0xf0000000)
3370 #define DBR_DBR_TYPE_SFT 28
3372 * This is a SQ producer index update. It indicates one or more
3373 * new entries have been written to the SQ for the QPID
3374 * indicated on the xID field.
3376 #define DBR_DBR_TYPE_SQ (UINT32_C(0x0) << 28)
3378 * This is a RQ producer index update. It indicates one or more
3379 * new entries have been written to the RQ for the QPID
3380 * indicated on the xID field.
3382 #define DBR_DBR_TYPE_RQ (UINT32_C(0x1) << 28)
3384 * This is a SRQ producer index update. It indicates one or more
3385 * new entries have been written to the SRQ for the SID
3386 * indicated on the xID field.
3388 #define DBR_DBR_TYPE_SRQ (UINT32_C(0x2) << 28)
3390 * This doorbell command arms the SRQ async event. The xID field
3391 * must identify the SID that is begin armed. The index field is
3392 * will set the arm threshold such that a notification will be
3393 * generated if less than that number or SRQ entries are posted.
3395 #define DBR_DBR_TYPE_SRQ_ARM (UINT32_C(0x3) << 28)
3397 * This is a CQ consumer index update. It indicates one or more
3398 * entries have been processed off the CQ indicated on the xID
3401 #define DBR_DBR_TYPE_CQ (UINT32_C(0x4) << 28)
3403 * this is a CQ consumer index update that also arms the CQ for
3406 #define DBR_DBR_TYPE_CQ_ARMSE (UINT32_C(0x5) << 28)
3408 * This is a CQ consumer index update that also arms the CQ for
3411 #define DBR_DBR_TYPE_CQ_ARMALL (UINT32_C(0x6) << 28)
3413 * This is a CQ arm enable message. This message must be sent
3414 * from the privileged driver before a new CQ_ARMSE or CQ_ARMALL
3415 * message will be accepted. This doorbell can only be sent from
3416 * the privileged (first) doorbell page of a function.
3418 #define DBR_DBR_TYPE_CQ_ARMENA (UINT32_C(0x7) << 28)
3420 * This doorbell command enables the SRQ async event to be
3421 * armed. This message must be setn from the privileged driver
3422 * before a new SRQ_ARM message will be accepted. The xID field
3423 * must identify the SID that is begin enabled for arm. This
3424 * doorbell can only be sent from the privileged (first)
3425 * doorbell page of a function.
3427 #define DBR_DBR_TYPE_SRQ_ARMENA (UINT32_C(0x8) << 28)
3429 * This doorbell command indicates that the cutoff CQE has been
3430 * processed and the driver is now processing completions from
3431 * the new CQ. The index field for this doorbell type must be
3434 #define DBR_DBR_TYPE_CQ_CUTOFF_ACK (UINT32_C(0x9) << 28)
3436 * This doorbell command is used during doorbell moderation to
3437 * consume system BW and help prevent doorbell FIFO overflow.
3438 * All other fields should be zero for NULL doorbell.
3440 #define DBR_DBR_TYPE_NULL (UINT32_C(0xf) << 28)
3441 } __attribute__((packed));
3443 /* 32b Doorbell Format (4 bytes) */
3446 uint32_t type_abs_incr_xid;
3447 /* This value identifies the type of doorbell being written. */
3449 * This value identifies the resource that the doorbell is intended to
3450 * notify. For SQ and RQ, this is the QPID. For SRQ, this is the SID.
3451 * For CQ, this is the CID. Bits [19:16] of this values must be zero for
3454 #define DBR_DBR32_XID_MASK UINT32_C(0xfffff)
3455 #define DBR_DBR32_XID_SFT 0
3456 #define DBR_DBR32_RESERVED4_MASK UINT32_C(0xf00000)
3457 #define DBR_DBR32_RESERVED4_SFT 20
3459 * When abs=0, this value is the value to add to the appropriate index
3460 * value. When abs=1, this value is the new value for the index.
3461 * Absolute value is used when the queue is being wrapped. When abs=1,
3462 * the incr value follows the same rules as the index value in the 64b
3465 #define DBR_DBR32_INCR_MASK UINT32_C(0xf000000)
3466 #define DBR_DBR32_INCR_SFT 24
3467 /* This value defines how the incr value will be interpreted. */
3468 #define DBR_DBR32_ABS UINT32_C(0x10000000)
3469 /* This value identifies the type of doorbell being written. */
3470 #define DBR_DBR32_TYPE_MASK UINT32_C(0xe0000000)
3471 #define DBR_DBR32_TYPE_SFT 29
3473 * This is a SQ producer index update. It indicates one or more
3474 * new entries have been written to the SQ for the QPID
3475 * indicated on the xID field.
3477 #define DBR_DBR32_TYPE_SQ (UINT32_C(0x0) << 29)
3478 } __attribute__((packed));
3480 /* SQ WQE Structures */
3482 * Description: This is the Bind WQE structure. This WQE can perform either: *
3483 * type1 "bind memory window", if mw_type==Type1 * type2 "post send bind memory
3484 * window", if mw_type==Type2
3486 /* Base SQ WQE (8 bytes) */
3490 /* This field defines the type of SQ WQE. */
3492 #define SQ_BASE_WQE_TYPE_SEND UINT32_C(0x0)
3494 * Send with Immediate Allowed only on reliable connection (RC)
3495 * and unreliable datagram (UD) SQ's.
3497 #define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD UINT32_C(0x1)
3499 * Send with Invalidate. Allowed only on reliable connection
3502 #define SQ_BASE_WQE_TYPE_SEND_W_INVALID UINT32_C(0x2)
3503 /* RDMA Write. Allowed only on reliable connection (RC) SQ's. */
3504 #define SQ_BASE_WQE_TYPE_WRITE_WQE UINT32_C(0x4)
3506 * RDMA Write with Immediate. Allowed only on reliable
3507 * connection (RC) SQ's.
3509 #define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD UINT32_C(0x5)
3510 /* RDMA Read. Allowed only on reliable connection (RC) SQ's. */
3511 #define SQ_BASE_WQE_TYPE_READ_WQE UINT32_C(0x6)
3513 * Atomic Compare/Swap. Allowed only on reliable connection (RC)
3516 #define SQ_BASE_WQE_TYPE_ATOMIC_CS UINT32_C(0x8)
3517 /* Atomic Fetch/Add. Allowed only on reliable connection (RC) SQ's. */
3518 #define SQ_BASE_WQE_TYPE_ATOMIC_FA UINT32_C(0xb)
3519 /* Local Invalidate. Allowed only on reliable connection (RC) SQ's. */
3520 #define SQ_BASE_WQE_TYPE_LOCAL_INVALID UINT32_C(0xc)
3522 * FR-PMR (Fast Register Physical Memory Region) Allowed only on
3523 * reliable connection (RC) SQ's.
3525 #define SQ_BASE_WQE_TYPE_FR_PMR UINT32_C(0xd)
3526 /* Memory Bind Allowed only on reliable connection (RC) SQ's. */
3527 #define SQ_BASE_WQE_TYPE_BIND UINT32_C(0xe)
3528 uint8_t unused_0[7];
3529 } __attribute__((packed));
3531 /* WQE SGE (16 bytes) */
3536 * The virtual address in local memory or a physical address when l_key
3537 * value is a reserved value of a physical address. Driver configures
3538 * this value in the chip and the chip compares l_key in SGEs with that
3539 * reserved value, if equal it access the physical address specified.
3540 * The chip however MUST verify that the QP allows the use reserved key.
3544 * Local Key associated with this registered MR; The 24 msb of the key
3545 * used to index the MRW Table and the 8 lsb are compared with the 8
3546 * bits key part stored in the MRWC. The PBL in the MRW Context is used
3547 * to translate the above VA to physical address.
3551 * Size of SGE in bytes; Based on page size of the system the chip knows
3552 * how many entries are in the PBL
3554 } __attribute__((packed));
3556 /* PSN Search Structure (8 bytes) */
3558 struct sq_psn_search {
3559 uint32_t opcode_start_psn;
3560 /* The opcodes are software defined. */
3562 #define SQ_PSN_SEARCH_START_PSN_MASK UINT32_C(0xffffff)
3563 #define SQ_PSN_SEARCH_START_PSN_SFT 0
3564 /* The opcodes are software defined. */
3565 #define SQ_PSN_SEARCH_OPCODE_MASK UINT32_C(0xff000000)
3566 #define SQ_PSN_SEARCH_OPCODE_SFT 24
3567 uint32_t flags_next_psn;
3568 /* Opcode specific flags. */
3569 /* Next PSN. Equal to the start PSN of the next WQE. */
3570 #define SQ_PSN_SEARCH_NEXT_PSN_MASK UINT32_C(0xffffff)
3571 #define SQ_PSN_SEARCH_NEXT_PSN_SFT 0
3572 /* Opcode specific flags. */
3573 #define SQ_PSN_SEARCH_FLAGS_MASK UINT32_C(0xff000000)
3574 #define SQ_PSN_SEARCH_FLAGS_SFT 24
3575 } __attribute__((packed));
3577 /* Send SQ WQE (40 bytes) */
3581 /* This field defines the type of SQ WQE. */
3583 #define SQ_SEND_WQE_TYPE_SEND UINT32_C(0x0)
3585 * Send with Immediate Allowed only on reliable connection (RC)
3586 * and unreliable datagram (UD) SQ's.
3588 #define SQ_SEND_WQE_TYPE_SEND_W_IMMEAD UINT32_C(0x1)
3590 * Send with Invalidate. Allowed only on reliable connection
3593 #define SQ_SEND_WQE_TYPE_SEND_W_INVALID UINT32_C(0x2)
3596 * Set if completion signaling is requested. If this bit is 0, and the
3597 * SQ is configured to support Unsignaled completion the controller
3598 * should not generate a CQE unless there was an error. This refers to
3599 * the CQE on the sender side. (The se flag refers to the receiver
3602 #define SQ_SEND_FLAGS_SIGNAL_COMP UINT32_C(0x1)
3604 * Indication to complete all previous RDMA Read or Atomic WQEs on the
3605 * SQ before executing this WQE. This flag must be zero for a UD send.
3607 #define SQ_SEND_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
3609 * For local invalidate request. Indicate to complete all previous SQ's
3610 * WQEs before executing this WQE. This flag must be zero for a UD send.
3612 #define SQ_SEND_FLAGS_UC_FENCE UINT32_C(0x4)
3614 * Solicit event flag. Indication sent in BTH header to the receiver to
3615 * generate a Completion Event Notification, i.e. CNQE. This bit should
3616 * be set only in the last (or only) packet of the message.
3618 #define SQ_SEND_FLAGS_SE UINT32_C(0x8)
3620 * Indicate that inline data is posted to the SQ in the data area of
3623 #define SQ_SEND_FLAGS_INLINE UINT32_C(0x10)
3626 * The number of 16 bytes chunks of data including this first word of
3627 * the request that are a valid part of the request. The valid 16 bytes
3628 * units other than the WQE structure can be SGEs (Scatter Gather
3629 * Elements) OR inline data. While this field defines the valid WQE
3630 * size. The actual total WQE size is always 128B.
3632 uint8_t reserved8_1;
3633 uint32_t inv_key_or_imm_data;
3635 * Either invalidate key (R_Key of the remote host) that will be send
3636 * with IETH (Invalidate ETH) if wqe_type is of Send with Invalidate, or
3637 * immediate value that will be sent with ImmDt header if wqe_type is
3638 * Send with Immediate.
3641 /* This field represents a 32-bit total data length, in bytes. */
3644 * When in the SQ of a UD QP, indicates the q_key to be used in the
3645 * transmitted packet. However, if the most significant bit of this
3646 * field is set, then the q_key will be taken from QP context, rather
3647 * than from this field. When in the SQ of a non-UD QP, this field is
3648 * reserved and should be filled with zeros.
3652 * When in the SQ of a UD QP, indicates the destination QP to be used in
3653 * the transmitted packet. When in the SQ of a non-UD QP, this field is
3654 * reserved and should be filled with zeros.
3656 #define SQ_SEND_DST_QP_MASK UINT32_C(0xffffff)
3657 #define SQ_SEND_DST_QP_SFT 0
3658 #define SQ_SEND_RESERVED8_2_MASK UINT32_C(0xff000000)
3659 #define SQ_SEND_RESERVED8_2_SFT 24
3661 /* This field is reserved for future expansion of the AVID. */
3663 * If the serv_type is 'UD', then this field supplies the AVID (Address
3666 #define SQ_SEND_AVID_MASK UINT32_C(0xfffff)
3667 #define SQ_SEND_AVID_SFT 0
3668 /* This field is reserved for future expansion of the AVID. */
3669 #define SQ_SEND_RESERVED_AVID_MASK UINT32_C(0xfff00000)
3670 #define SQ_SEND_RESERVED_AVID_SFT 20
3671 uint64_t reserved64;
3674 * When inline=0, then this area is filled with from 1 to 6 SGEs based
3675 * on the wqe_size field. When inline=1, this area is filled with
3676 * payload data for the send based on the length_or_AVID field. Bits
3677 * [7:0] of word 0 hold the first byte to go out on the wire.
3679 } __attribute__((packed));
3681 /* Send Raw Ethernet and QP1 SQ WQE (40 bytes) */
3683 struct sq_send_raweth_qp1 {
3685 /* This field defines the type of SQ WQE. */
3687 #define SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND UINT32_C(0x0)
3690 * Set if completion signaling is requested. If this bit is 0, and the
3691 * SQ is configured to support Unsignaled completion the controller
3692 * should not generate a CQE unless there was an error. This refers to
3693 * the CQE on the sender side. (The se flag refers to the receiver
3696 #define SQ_SEND_RAWETH_QP1_FLAGS_SIGNAL_COMP UINT32_C(0x1)
3697 /* This flag must be zero for a Raweth or QP1 send. */
3698 #define SQ_SEND_RAWETH_QP1_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
3699 /* This flag must be zero for a Raweth or QP1 send. */
3700 #define SQ_SEND_RAWETH_QP1_FLAGS_UC_FENCE UINT32_C(0x4)
3701 /* This flag must be zero for a Raweth or QP1 send. */
3702 #define SQ_SEND_RAWETH_QP1_FLAGS_SE UINT32_C(0x8)
3704 * Indicate that inline data is posted to the SQ in the data area of
3707 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE UINT32_C(0x10)
3710 * The number of 16 bytes chunks of data including this first word of
3711 * the request that are a valid part of the request. The valid 16 bytes
3712 * units other than the WQE structure can be SGEs (Scatter Gather
3713 * Elements) OR inline data. While this field defines the valid WQE
3714 * size. The actual total WQE size is always 128B.
3719 * All bits in this field must be valid on the first BD of a packet.
3720 * Their value on other BDs of the packet will be ignored.
3723 * If set to 1, the controller replaces the TCP/UPD checksum fields of
3724 * normal TCP/UPD checksum, or the inner TCP/UDP checksum field of the
3725 * encapsulated TCP/UDP packets with the hardware calculated TCP/UDP
3726 * checksum for the packet associated with this descriptor. This bit
3727 * must be valid on the first BD of a packet.
3729 #define SQ_SEND_RAWETH_QP1_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
3731 * If set to 1, the controller replaces the IP checksum of the normal
3732 * packets, or the inner IP checksum of the encapsulated packets with
3733 * the hardware calculated IP checksum for the packet associated with
3734 * this descriptor. This bit must be valid on the first BD of a packet.
3736 #define SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM UINT32_C(0x2)
3738 * If set to 1, the controller will not append an Ethernet CRC to the
3739 * end of the frame. This bit must be valid on the first BD of a packet.
3740 * Packet must be 64B or longer when this flag is set. It is not usefull
3741 * to use this bit with any form of TX offload such as CSO or LSO. The
3742 * intent is that the packet from the host already has a valid Ethernet
3743 * CRC on the packet.
3745 #define SQ_SEND_RAWETH_QP1_LFLAGS_NOCRC UINT32_C(0x4)
3747 * If set to 1, the device will record the time at which the packet was
3748 * actually transmitted at the TX MAC. This bit must be valid on the
3749 * first BD of a packet.
3751 #define SQ_SEND_RAWETH_QP1_LFLAGS_STAMP UINT32_C(0x8)
3753 * If set to 1, The controller replaces the tunnel IP checksum field
3754 * with hardware calculated IP checksum for the IP header of the packet
3755 * associated with this descriptor. In case of VXLAN, the controller
3756 * also replaces the outer header UDP checksum with hardware calculated
3757 * UDP checksum for the packet associated with this descriptor.
3759 #define SQ_SEND_RAWETH_QP1_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
3760 /* This bit is reserved and should be zero. */
3761 #define SQ_SEND_RAWETH_QP1_LFLAGS_RESERVED1_1 UINT32_C(0x20)
3762 /* This bit is reserved and should be zero. */
3763 #define SQ_SEND_RAWETH_QP1_LFLAGS_RESERVED1_2 UINT32_C(0x40)
3764 /* This bit is reserved and should be zero. */
3765 #define SQ_SEND_RAWETH_QP1_LFLAGS_RESERVED1_3 UINT32_C(0x80)
3767 * If set to '1', then the RoCE ICRC will be appended to the packet.
3768 * Packet must be a valid RoCE format packet.
3770 #define SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC UINT32_C(0x100)
3772 * If set to '1', then the FCoE CRC will be appended to the packet.
3773 * Packet must be a valid FCoE format packet.
3775 #define SQ_SEND_RAWETH_QP1_LFLAGS_FCOE_CRC UINT32_C(0x200)
3776 uint16_t cfa_action;
3778 * This value selects a CFA action to perform on the packet. Set this
3779 * value to zero if no CFA action is desired. This value must be valid
3780 * on the first BD of a packet.
3784 * This field represents a 32-bit total data length, in bytes. Note,
3785 * however, that the length cannot exceed the MTU.
3787 uint32_t reserved32_1;
3790 * This value is action meta-data that defines CFA edit operations that
3791 * are done in addition to any action editing.
3793 /* When key=1, This is the VLAN tag VID value. */
3794 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
3795 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_SFT 0
3796 /* When key=1, This is the VLAN tag DE value. */
3797 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_DE UINT32_C(0x1000)
3798 /* When key=1, This is the VLAN tag PRI value. */
3799 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
3800 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_SFT 13
3801 /* When key=1, This is the VLAN tag TPID select value. */
3802 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
3803 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_SFT 16
3805 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
3807 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
3809 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
3811 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
3813 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
3814 /* Value programmed in CFA VLANTPID register. */
3815 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
3816 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_LAST SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG
3817 /* When key=1, This is the VLAN tag TPID select value. */
3818 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
3819 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_SFT 19
3821 * This field identifies the type of edit to be performed on the packet.
3822 * This value must be valid on the first BD of a packet.
3824 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_MASK UINT32_C(0xf0000000)
3825 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_SFT 28
3827 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
3829 * - meta[17:16] - TPID select value (0 = 0x8100). - meta[15:12]
3830 * - PRI/DE value. - meta[11:0] - VID value.
3832 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
3833 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_LAST SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG
3834 uint32_t reserved32_2;
3835 uint64_t reserved64;
3838 * When inline=0, then this area is filled with from 1 to 6 SGEs based
3839 * on the wqe_size field. When inline=1, this area is filled with
3840 * payload data for the send based on the length_or_AVID field. Bits
3841 * [7:0] of word 0 hold the first byte to go out on the wire.
3843 } __attribute__((packed));
3845 /* RDMA SQ WQE (40 bytes) */
3849 /* This field defines the type of SQ WQE. */
3850 /* RDMA Write. Allowed only on reliable connection (RC) SQ's. */
3851 #define SQ_RDMA_WQE_TYPE_WRITE_WQE UINT32_C(0x4)
3853 * RDMA Write with Immediate. Allowed only on reliable
3854 * connection (RC) SQ's.
3856 #define SQ_RDMA_WQE_TYPE_WRITE_W_IMMEAD UINT32_C(0x5)
3857 /* RDMA Read. Allowed only on reliable connection (RC) SQ's. */
3858 #define SQ_RDMA_WQE_TYPE_READ_WQE UINT32_C(0x6)
3861 * Set if completion signaling is requested. If this bit is 0, and the
3862 * SQ is configured to support Unsignaled completion the controller
3863 * should not generate a CQE unless there was an error. This refer to
3864 * CQE on the sender side (se_flag refer to the receiver side)
3866 #define SQ_RDMA_FLAGS_SIGNAL_COMP UINT32_C(0x1)
3868 * Indication to complete all previous RDMA Read or Atomic WQEs on the
3869 * SQ before executing this WQE
3871 #define SQ_RDMA_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
3873 * Unconditional fence. Indicate to complete all previous SQ's WQEs
3874 * before executing this WQE.
3876 #define SQ_RDMA_FLAGS_UC_FENCE UINT32_C(0x4)
3878 * Solicit event. Indication sent in BTH header to the receiver to
3879 * generate a Completion Event Notification, i.e. CNQE. This bit should
3880 * be set only in the last (or only) packet of the message.
3882 #define SQ_RDMA_FLAGS_SE UINT32_C(0x8)
3884 * Indicate that inline data is posted to the SQ following this WQE.
3885 * This bit may be 1 only for write operations.
3887 #define SQ_RDMA_FLAGS_INLINE UINT32_C(0x10)
3890 * The number of 16 bytes chunks of data including this first wqe of the
3891 * request that are a valid part of the request. The valid 16 bytes
3892 * units other than the WQE structure can be SGEs (Scatter Gather
3893 * Elements) OR inline data. While this field defines the valid WQE
3894 * size. The actual total WQE size is always 128B.
3899 * Immediate data - valid for RDMA Write with immediate and causes the
3900 * controller to add immDt header with this value
3903 /* Total data length in bytes */
3904 uint32_t reserved32_1;
3906 /* Remote VA sent to the destination QP */
3907 uint32_t remote_key;
3909 * R_Key provided by remote node when the connection was established and
3910 * placed in the RETH header. It identify the MRW on the remote host
3912 uint32_t reserved32_2;
3915 * When inline=0, then this area is filled with from 1 to 6 SGEs based
3916 * on the wqe_size field. When inline=1, this area is filled with
3917 * payload data for the write based on the length field. Bits [7:0] of
3918 * word 0 hold the first byte to go out on the wire.
3920 } __attribute__((packed));
3922 /* Atomic SQ WQE (40 bytes) */
3926 /* This field defines the type of SQ WQE. */
3928 * Atomic Compare/Swap. Allowed only on reliable connection (RC)
3931 #define SQ_ATOMIC_WQE_TYPE_ATOMIC_CS UINT32_C(0x8)
3932 /* Atomic Fetch/Add. Allowed only on reliable connection (RC) SQ's. */
3933 #define SQ_ATOMIC_WQE_TYPE_ATOMIC_FA UINT32_C(0xb)
3936 * Set if completion signaling is requested. If this bit is 0, and the
3937 * SQ is configured to support Unsignaled completion the controller
3938 * should not generate a CQE unless there was an error. This refer to
3939 * CQE on the sender side (se_flag refer to the receiver side)
3941 #define SQ_ATOMIC_FLAGS_SIGNAL_COMP UINT32_C(0x1)
3943 * Indication to complete all previous RDMA Read or Atomic WQEs on the
3944 * SQ before executing this WQE
3946 #define SQ_ATOMIC_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
3948 * Unconditional fence. Indicate to complete all previous SQ's WQEs
3949 * before executing this WQE.
3951 #define SQ_ATOMIC_FLAGS_UC_FENCE UINT32_C(0x4)
3953 * Solicit event. Indication sent in BTH header to the receiver to
3954 * generate a Completion Event Notification, i.e. CNQE. This bit should
3955 * be set only in the last (or only) packet of the message.
3957 #define SQ_ATOMIC_FLAGS_SE UINT32_C(0x8)
3958 /* NA for this WQE. */
3959 #define SQ_ATOMIC_FLAGS_INLINE UINT32_C(0x10)
3960 uint16_t reserved16;
3961 uint32_t remote_key;
3963 * R_Key provided by remote node when the connection was established and
3964 * placed in the AETH header. It identify the MRW on the remote host
3967 /* Remote VA sent to the destination QP */
3969 /* Data value to be placed in remote host specified address */
3972 * Data value to be compared with the value in the remote host specified
3977 * The first 16B of the data field must be filled with a single SGE.
3978 * This will be used to store the return value from the Atomic Ack
3979 * response. The size of the single SGE must be 8B.
3981 } __attribute__((packed));
3983 /* Local Invalidate SQ WQE (40 bytes) */
3985 struct sq_localinvalidate {
3987 /* This field defines the type of SQ WQE. */
3988 /* Local Invalidate. Allowed only on reliable connection (RC) SQ's. */
3989 #define SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID UINT32_C(0xc)
3992 * Set if completion signaling is requested. If this bit is 0, and the
3993 * SQ is configured to support Unsignaled completion the controller
3994 * should not generate a CQE unless there was an error. This refer to
3995 * CQE on the sender side (se_flag refer to the receiver side)
3997 #define SQ_LOCALINVALIDATE_FLAGS_SIGNAL_COMP UINT32_C(0x1)
3999 * Indication to complete all previous RDMA Read or Atomic WQEs on the
4000 * SQ before executing this WQE
4002 #define SQ_LOCALINVALIDATE_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
4004 * Unconditional fence. Indicate to complete all previous SQ's WQEs
4005 * before executing this WQE.
4007 #define SQ_LOCALINVALIDATE_FLAGS_UC_FENCE UINT32_C(0x4)
4009 * Solicit event. Indication sent in BTH header to the receiver to
4010 * generate a Completion Event Notification, i.e. CNQE. This bit should
4011 * be set only in the last (or only) packet of the message.
4013 #define SQ_LOCALINVALIDATE_FLAGS_SE UINT32_C(0x8)
4014 /* NA for this WQE */
4015 #define SQ_LOCALINVALIDATE_FLAGS_INLINE UINT32_C(0x10)
4016 uint16_t reserved16;
4019 * The local key for the MR/W to invalidate; 24 msb of the key are used
4020 * to index the MRW table, 8 lsb are compared with the 8 bit key in the
4023 uint64_t reserved64;
4024 uint32_t reserved128[4];
4026 /* The data field for local invalidate is not used. */
4027 } __attribute__((packed));
4029 /* FR-PMR SQ WQE (40 bytes) */
4033 /* This field defines the type of SQ WQE. */
4035 * FR-PMR (Fast Register Physical Memory Region) Allowed only on
4036 * reliable connection (RC) SQ's.
4038 #define SQ_FR_PMR_WQE_TYPE_FR_PMR UINT32_C(0xd)
4041 * Set if completion signaling is requested. If this bit is 0, and the
4042 * SQ is configured to support Unsignaled completion the controller
4043 * should not generate a CQE unless there was an error. This refer to
4044 * CQE on the sender side (se_flag refer to the receiver side)
4046 #define SQ_FR_PMR_FLAGS_SIGNAL_COMP UINT32_C(0x1)
4048 * Indication to complete all previous RDMA Read or Atomic WQEs on the
4049 * SQ before executing this WQE
4051 #define SQ_FR_PMR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
4053 * Unconditional fence. Indicate to complete all previous SQ's WQEs
4054 * before executing this WQE.
4056 #define SQ_FR_PMR_FLAGS_UC_FENCE UINT32_C(0x4)
4057 /* Not Applicable for FR_PMR. Nothing is sent */
4058 #define SQ_FR_PMR_FLAGS_SE UINT32_C(0x8)
4060 #define SQ_FR_PMR_FLAGS_INLINE UINT32_C(0x10)
4061 uint8_t access_cntl;
4063 * This is the new access control for the MR. '1' means the operation is
4064 * allowed. '0' means operation is not allowed.
4066 /* Local Write Access */
4067 #define SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
4068 /* Remote Read Access */
4069 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
4070 /* Remote Write Access */
4071 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
4072 /* Remote Atomic Access */
4073 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
4074 /* Window Binding Allowed */
4075 #define SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
4076 uint8_t zero_based_page_size_log;
4077 /* 0 for 4KB page size, ... to 8GB */
4078 #define SQ_FR_PMR_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
4079 #define SQ_FR_PMR_PAGE_SIZE_LOG_SFT 0
4080 /* Page size is 4KB. */
4081 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
4082 /* Page size is 8KB. */
4083 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
4084 /* Page size is 64KB. */
4085 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
4086 /* Page size is 256KB. */
4087 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
4088 /* Page size is 1MB. */
4089 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
4090 /* Page size is 2MB. */
4091 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
4092 /* Page size is 4MB. */
4093 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
4094 /* Page size is 1GB. */
4095 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
4096 /* Indicate the MR is ZBVA (Zero Base VA) */
4097 #define SQ_FR_PMR_ZERO_BASED UINT32_C(0x20)
4098 #define SQ_FR_PMR_RESERVED2_MASK UINT32_C(0xc0)
4099 #define SQ_FR_PMR_RESERVED2_SFT 6
4102 * Local Key; 24 msb of the key are used to index the MRW table, 8 lsb
4103 * are assigned to the 8 bit key_lsb field in the MRWC.
4106 /* Length in bytes of registered MR */
4107 uint8_t reserved8_1;
4108 uint8_t reserved8_2;
4109 uint8_t numlevels_pbl_page_size_log;
4110 /* Number of levels of PBL for translation */
4111 /* PBL page size. 0 for 4KB page size. */
4112 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
4113 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_SFT 0
4114 /* Page size is 4KB. */
4115 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
4116 /* Page size is 8KB. */
4117 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
4118 /* Page size is 64KB. */
4119 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
4120 /* Page size is 256KB. */
4121 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
4122 /* Page size is 1MB. */
4123 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
4124 /* Page size is 2MB. */
4125 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
4126 /* Page size is 4MB. */
4127 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
4128 /* Page size is 1GB. */
4129 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
4130 #define SQ_FR_PMR_RESERVED1 UINT32_C(0x20)
4131 /* Number of levels of PBL for translation */
4132 #define SQ_FR_PMR_NUMLEVELS_MASK UINT32_C(0xc0)
4133 #define SQ_FR_PMR_NUMLEVELS_SFT 6
4135 * A zero level PBL means that the VA is the physical address
4136 * used for the operation. No translation is done by the PTU.
4138 #define SQ_FR_PMR_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 6)
4140 * A one layer translation is provided between the logical and
4141 * physical address. The PBL points to a physical page that
4142 * contains PBE values that point to actual pg_size physical
4145 #define SQ_FR_PMR_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 6)
4147 * A two layer translation is provided between the logical and
4148 * physical address. The PBL points to a physical page that
4149 * contains PDE values that in turn point to pbl_pg_size
4150 * physical pages that contain PBE values that point to actual
4153 #define SQ_FR_PMR_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 6)
4155 /* Pointer to the PBL, or PDL depending on number of levels */
4157 /* Local Virtual Address */
4159 /* The data field for FR-PRM is not used. */
4160 } __attribute__((packed));
4162 /* Bind SQ WQE (40 bytes) */
4166 /* This field defines the type of SQ WQE. */
4167 /* Memory Bind Allowed only on reliable connection (RC) SQ's. */
4168 #define SQ_BIND_WQE_TYPE_BIND UINT32_C(0xe)
4171 * Set if completion signaling is requested. If this bit is 0, and the
4172 * SQ is configured to support Unsignaled completion the controller
4173 * should not generate a CQE unless there was an error. This refer to
4174 * CQE on the sender side (se_flag refer to the receiver side)
4176 #define SQ_BIND_FLAGS_SIGNAL_COMP UINT32_C(0x1)
4178 * Indication to complete all previous RDMA Read or Atomic WQEs on the
4179 * SQ before executing this WQE
4181 #define SQ_BIND_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
4183 * Unconditional fence. Indicate to complete all previous SQ's WQEs
4184 * before executing this WQE.
4186 #define SQ_BIND_FLAGS_UC_FENCE UINT32_C(0x4)
4187 /* NA, nothing is sent. */
4188 #define SQ_BIND_FLAGS_SE UINT32_C(0x8)
4190 #define SQ_BIND_FLAGS_INLINE UINT32_C(0x10)
4191 uint8_t access_cntl;
4193 * This is the new access control for the MR. '1' means the operation is
4194 * allowed. '0' means operation is not allowed.
4197 * Local Write Access. Local accesses are never allowed for memory
4198 * windows, so this bit must always be zero in a bind WQE. If this bit
4199 * is ever set, the bind will fail with an errored completion.
4201 #define SQ_BIND_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
4202 /* Remote Read Access */
4203 #define SQ_BIND_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
4205 * Remote Write Access. Note that, if this bit is set, then the parent
4206 * region to which the window is being bound must allow local writes. If
4207 * this is not the case, then the bind will fail with an errored
4210 #define SQ_BIND_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
4212 * Remote Atomic Access. Note that, if this bit is set, then the parent
4213 * region to which the window is being bound must allow local writes. If
4214 * this is not the case, then the bind will fail with an errored
4217 #define SQ_BIND_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
4219 * Window Binding Allowed. It is never allowed to bind windows to
4220 * windows, so this bit must always be zero in a bind WQE. If this bit
4221 * is ever set, the bind will fail with an errored completion.
4223 #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
4224 uint8_t reserved8_1;
4225 /* reserved8_1 is 8 b */
4226 uint8_t mw_type_zero_based;
4228 * If this bit is set, then the newly-bound memory window will be zero-
4229 * based. If clear, then the newly-bound memory window will be non-zero-
4232 #define SQ_BIND_ZERO_BASED UINT32_C(0x1)
4234 * If type1 is specified, then this WQE performs a "bind memory window"
4235 * operation on a type1 window. If type2 is specified, then this WQE
4236 * performs a "post send bind memory window" operation on a type2
4237 * window. Note that the bind WQE cannot change the type of the memory
4238 * window. If a "bind memory window" operation is attempted on a memory
4239 * window that was allocated as type2, then the bind will fail with an
4240 * errored completion, as "bind memory window" is allowed only on type1
4241 * memory windows. Similarly, if a "post send bind memory window"
4242 * operation is attempted on a memory window that was allocated as
4243 * type1, then the bind will fail with an errored completions, as "post
4244 * send bind memory window" is allowed only on type2 memory windows.
4246 #define SQ_BIND_MW_TYPE UINT32_C(0x2)
4247 /* Type 1 Bind Memory Window */
4248 #define SQ_BIND_MW_TYPE_TYPE1 (UINT32_C(0x0) << 1)
4249 /* Type 2 Post Send Bind Memory Window */
4250 #define SQ_BIND_MW_TYPE_TYPE2 (UINT32_C(0x1) << 1)
4251 #define SQ_BIND_RESERVED6_MASK UINT32_C(0xfc)
4252 #define SQ_BIND_RESERVED6_SFT 2
4253 uint8_t reserved8_2;
4254 uint16_t reserved16;
4255 uint32_t parent_l_key;
4257 * The L_Key of the parent MR; 24 msb of the key are used to index the
4258 * MRW table, 8 lsb are compared with the 8 bit key in the MRWC.
4262 * Local Key; 24 msb of the key are used to index the memory window
4263 * being bound in the MRW table, 8 lsb are assign to the 8 bit key_lsb
4264 * field in the MRWC.
4267 /* Local Virtual Address */
4270 * Length in bytes of registered MW; 40 bits as this is the max size of
4273 uint8_t data_reserved24[99];
4274 /* The data field for Bind is not used. */
4275 #define SQ_BIND_RESERVED24_MASK UINT32_C(0xffffff00)
4276 #define SQ_BIND_RESERVED24_SFT 8
4277 /* The data field for Bind is not used. */
4278 #define SQ_BIND_DATA_MASK UINT32_C(0xffffffff)
4279 #define SQ_BIND_DATA_SFT 0
4280 } __attribute__((packed));
4282 /* RQ/SRQ WQE Structures */
4283 /* Description: This is the RQ/SRQ WQE structure. */
4284 /* RQ/SRQ WQE (40 bytes) */
4288 /* wqe_type is 8 b */
4289 /* RQ/SRQ WQE. This WQE is used for posting buffers on an RQ or SRQ. */
4290 #define RQ_WQE_WQE_TYPE_RCV UINT32_C(0x80)
4292 /* No flags supported for this WQE type. */
4295 * Specify the total number 16B chunks that make up the valid portion of
4296 * the WQE. This includes the first chunk that is the WQE structure and
4297 * up to 6 SGE structures. While the valid area is defined by the
4298 * wqe_size field, the actual WQE size is fixed at 128B.
4301 uint32_t reserved32;
4304 * Opaque value used by upper layer SW to identify the id of the WR
4305 * which generated the WQE. Used in CQE. Valid in the first SGE of an
4308 #define RQ_WQE_WR_ID_MASK UINT32_C(0xfffff)
4309 #define RQ_WQE_WR_ID_SFT 0
4310 #define RQ_WQE_RESERVED44_MASK UINT32_C(0xfff00000)
4311 #define RQ_WQE_RESERVED44_SFT 20
4312 uint32_t reserved128[4];
4315 * The data field for RQ WQE is filled with from 1 to 6 SGE structures
4316 * as defined by the wqe_size field.
4318 } __attribute__((packed));
4320 /* CQ CQE Structures */
4321 /* Description: This is the Cutoff CQE structure. */
4322 /* Base CQE (32 bytes) */
4325 uint64_t reserved64_1;
4326 uint64_t reserved64_2;
4327 uint64_t reserved64_3;
4328 uint8_t cqe_type_toggle;
4330 * Indicate valid completion - written by the chip. Cumulus toggle this
4331 * bit each time it finished consuming all PBL entries
4333 #define CQ_BASE_TOGGLE UINT32_C(0x1)
4334 /* This field defines the type of SQ WQE. */
4335 #define CQ_BASE_CQE_TYPE_MASK UINT32_C(0x1e)
4336 #define CQ_BASE_CQE_TYPE_SFT 1
4338 * Requester completion - This is used for both RC and UD SQ
4341 #define CQ_BASE_CQE_TYPE_REQ (UINT32_C(0x0) << 1)
4343 * Responder RC Completion - This is used for both RQ and SRQ
4344 * completions for RC service QPs.
4346 #define CQ_BASE_CQE_TYPE_RES_RC (UINT32_C(0x1) << 1)
4348 * Responder UD Completion - This is used for both RQ and SRQ
4349 * completion for UD service QPs.
4351 #define CQ_BASE_CQE_TYPE_RES_UD (UINT32_C(0x2) << 1)
4353 * Responder RawEth and QP1 Completion - This is used for RQ
4354 * completion for RawEth service and QP1 service QPs.
4356 #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1 (UINT32_C(0x3) << 1)
4358 * Terminal completion - This is used to indicate that no
4359 * further completions will be made for this QP on this CQ.
4361 #define CQ_BASE_CQE_TYPE_TERMINAL (UINT32_C(0xe) << 1)
4362 /* Cut off CQE; for CQ resize see CQ and SRQ Resize */
4363 #define CQ_BASE_CQE_TYPE_CUT_OFF (UINT32_C(0xf) << 1)
4364 #define CQ_BASE_RESERVED3_MASK UINT32_C(0xe0)
4365 #define CQ_BASE_RESERVED3_SFT 5
4367 /* This field indicates the status for the CQE. */
4368 uint16_t reserved16;
4369 uint32_t reserved32;
4370 } __attribute__((packed));
4372 /* Requester CQ CQE (32 bytes) */
4377 * This is an application level ID used to identify the QP and its SQ
4380 uint16_t sq_cons_idx;
4382 * SQ Consumer Index - points to the entry just past the last WQE that
4383 * has been completed by the chip. Wraps around at QPC.sq_size (i.e. the
4384 * valid range of the SQ Consumer Index is 0 to (QPC.sq_size - 1)).
4386 uint16_t reserved16_1;
4387 uint32_t reserved32_2;
4388 uint64_t reserved64;
4389 uint8_t cqe_type_toggle;
4391 * Indicate valid completion - written by the chip. Cumulus toggle this
4392 * bit each time it finished consuming all PBL entries
4394 #define CQ_REQ_TOGGLE UINT32_C(0x1)
4395 /* This field defines the type of SQ WQE. */
4396 #define CQ_REQ_CQE_TYPE_MASK UINT32_C(0x1e)
4397 #define CQ_REQ_CQE_TYPE_SFT 1
4399 * Requester completion - This is used for both RC and UD SQ
4402 #define CQ_REQ_CQE_TYPE_REQ (UINT32_C(0x0) << 1)
4403 #define CQ_REQ_RESERVED3_MASK UINT32_C(0xe0)
4404 #define CQ_REQ_RESERVED3_SFT 5
4406 /* This field indicates the status for the CQE. */
4408 #define CQ_REQ_STATUS_OK UINT32_C(0x0)
4409 /* BAD_RESPONSE_ERR is 1 */
4410 #define CQ_REQ_STATUS_BAD_RESPONSE_ERR UINT32_C(0x1)
4411 /* LOCAL_LENGTH_ERR is 2 */
4412 #define CQ_REQ_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2)
4413 /* LOCAL_QP_OPERATION_ERR is 3 */
4414 #define CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x3)
4415 /* LOCAL_PROTECTION_ERR is 4 */
4416 #define CQ_REQ_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x4)
4417 /* MEMORY_MGT_OPERATION_ERR is 5 */
4418 #define CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
4419 /* REMOTE_INVALID_REQUEST_ERR is 6 */
4420 #define CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x6)
4421 /* REMOTE_ACCESS_ERR is 7 */
4422 #define CQ_REQ_STATUS_REMOTE_ACCESS_ERR UINT32_C(0x7)
4423 /* REMOTE_OPERATION_ERR is 8 */
4424 #define CQ_REQ_STATUS_REMOTE_OPERATION_ERR UINT32_C(0x8)
4425 /* RNR_NAK_RETRY_CNT_ERR is 9 */
4426 #define CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR UINT32_C(0x9)
4427 /* TRANSPORT_RETRY_CNT_ERR is 10 */
4428 #define CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR UINT32_C(0xa)
4429 /* WORK_REQUEST_FLUSHED_ERR is 11 */
4430 #define CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xb)
4431 uint16_t reserved16_2;
4432 uint32_t reserved32_1;
4433 } __attribute__((packed));
4435 /* Responder RC CQE (32 bytes) */
4439 /* The length of the message's payload in bytes, stored in the SGEs */
4440 uint32_t imm_data_or_inv_r_key;
4442 * Immediate data in case the imm_flag set, R_Key to be invalidated in
4443 * case inv_flag is set.
4447 * This is an application level ID used to identify the QP and its SQ
4452 * Opaque value - valid when inv_flag is set. Used by driver to
4453 * reference the buffer used to store PBL when the MR was fast
4454 * registered. The driver can reclaim this buffer after an MR was
4455 * remotely invalidated. The controller take that value from the MR
4456 * referenced by R_Key
4458 uint8_t cqe_type_toggle;
4460 * Indicate valid completion - written by the chip. Cumulus toggle this
4461 * bit each time it finished consuming all PBL entries
4463 #define CQ_RES_RC_TOGGLE UINT32_C(0x1)
4464 /* This field defines the type of SQ WQE. */
4465 #define CQ_RES_RC_CQE_TYPE_MASK UINT32_C(0x1e)
4466 #define CQ_RES_RC_CQE_TYPE_SFT 1
4468 * Responder RC Completion - This is used for both RQ and SRQ
4469 * completions for RC service QPs.
4471 #define CQ_RES_RC_CQE_TYPE_RES_RC (UINT32_C(0x1) << 1)
4472 #define CQ_RES_RC_RESERVED3_MASK UINT32_C(0xe0)
4473 #define CQ_RES_RC_RESERVED3_SFT 5
4475 /* This field indicates the status for the CQE. */
4477 #define CQ_RES_RC_STATUS_OK UINT32_C(0x0)
4478 /* LOCAL_ACCESS_ERROR is 1 */
4479 #define CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1)
4480 /* LOCAL_LENGTH_ERR is 2 */
4481 #define CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2)
4482 /* LOCAL_PROTECTION_ERR is 3 */
4483 #define CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3)
4484 /* LOCAL_QP_OPERATION_ERR is 4 */
4485 #define CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
4486 /* MEMORY_MGT_OPERATION_ERR is 5 */
4487 #define CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
4488 /* REMOTE_INVALID_REQUEST_ERR is 6 */
4489 #define CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x6)
4490 /* WORK_REQUEST_FLUSHED_ERR is 7 */
4491 #define CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
4492 /* HW_FLUSH_ERR is 8 */
4493 #define CQ_RES_RC_STATUS_HW_FLUSH_ERR UINT32_C(0x8)
4496 * This flag indicates that the completion is for a SRQ entry rather
4497 * than for an RQ entry.
4499 #define CQ_RES_RC_FLAGS_SRQ UINT32_C(0x1)
4500 /* CQE relates to RQ WQE. */
4501 #define CQ_RES_RC_FLAGS_SRQ_RQ (UINT32_C(0x0) << 0)
4502 /* CQE relates to SRQ WQE. */
4503 #define CQ_RES_RC_FLAGS_SRQ_SRQ (UINT32_C(0x1) << 0)
4504 #define CQ_RES_RC_FLAGS_SRQ_LAST CQ_RES_RC_FLAGS_SRQ_SRQ
4505 /* Immediate data indicator */
4506 #define CQ_RES_RC_FLAGS_IMM UINT32_C(0x2)
4507 /* R_Key invalidate indicator */
4508 #define CQ_RES_RC_FLAGS_INV UINT32_C(0x4)
4509 #define CQ_RES_RC_FLAGS_RDMA UINT32_C(0x8)
4510 /* CQE relates to an incoming Send request */
4511 #define CQ_RES_RC_FLAGS_RDMA_SEND (UINT32_C(0x0) << 3)
4512 /* CQE relates to incoming RDMA Write request */
4513 #define CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE (UINT32_C(0x1) << 3)
4514 #define CQ_RES_RC_FLAGS_RDMA_LAST CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE
4515 uint32_t srq_or_rq_wr_id;
4517 * Opaque value from RQ or SRQ WQE. Used by driver/lib to reference the
4518 * WQE in order to claim the received data and reuse the WQE space
4520 #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
4521 #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_SFT 0
4522 #define CQ_RES_RC_RESERVED12_MASK UINT32_C(0xfff00000)
4523 #define CQ_RES_RC_RESERVED12_SFT 20
4524 } __attribute__((packed));
4526 /* Responder UD CQE (32 bytes) */
4530 /* The length of the message's payload in bytes, stored in the SGEs */
4531 #define CQ_RES_UD_LENGTH_MASK UINT32_C(0x3fff)
4532 #define CQ_RES_UD_LENGTH_SFT 0
4533 #define CQ_RES_UD_RESERVED18_MASK UINT32_C(0xffffc000)
4534 #define CQ_RES_UD_RESERVED18_SFT 14
4536 /* Immediate data in case the imm_flag set. */
4539 * This is an application level ID used to identify the QP and its SQ
4542 uint16_t src_mac[3];
4544 * Source MAC address for the UD message placed in the WQE that is
4545 * completed by this CQE.
4547 uint16_t src_qp_low;
4548 /* Lower 16b of the Source QP value from the DETH header. */
4549 uint8_t cqe_type_toggle;
4551 * Indicate valid completion - written by the chip. Cumulus toggle this
4552 * bit each time it finished consuming all PBL entries
4554 #define CQ_RES_UD_TOGGLE UINT32_C(0x1)
4555 /* This field defines the type of SQ WQE. */
4556 #define CQ_RES_UD_CQE_TYPE_MASK UINT32_C(0x1e)
4557 #define CQ_RES_UD_CQE_TYPE_SFT 1
4559 * Responder UD Completion - This is used for both RQ and SRQ
4560 * completion for UD service QPs.
4562 #define CQ_RES_UD_CQE_TYPE_RES_UD (UINT32_C(0x2) << 1)
4563 #define CQ_RES_UD_RESERVED3_MASK UINT32_C(0xe0)
4564 #define CQ_RES_UD_RESERVED3_SFT 5
4566 /* This field indicates the status for the CQE. */
4568 * This indicates that the completion is without error. All
4571 #define CQ_RES_UD_STATUS_OK UINT32_C(0x0)
4573 * This indicates that write access was not allowed for at least
4574 * one of the SGEs in the WQE. This is a fatal error. Only the
4575 * srq_or_rq_wr_id is field is valid.
4577 #define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1)
4579 * This indicates that the packet was too long for the WQE
4580 * provided on the SRQ/RQ. This is not a fatal error. All the
4583 #define CQ_RES_UD_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2)
4584 /* LOCAL_PROTECTION_ERR is 3 */
4585 #define CQ_RES_UD_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3)
4586 /* LOCAL_QP_OPERATION_ERR is 4 */
4587 #define CQ_RES_UD_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
4588 /* MEMORY_MGT_OPERATION_ERR is 5 */
4589 #define CQ_RES_UD_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
4590 /* WORK_REQUEST_FLUSHED_ERR is 7 */
4591 #define CQ_RES_UD_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
4592 /* HW_FLUSH_ERR is 8 */
4593 #define CQ_RES_UD_STATUS_HW_FLUSH_ERR UINT32_C(0x8)
4596 * This flag indicates that the completion is for a SRQ entry rather
4597 * than for an RQ entry.
4599 #define CQ_RES_UD_FLAGS_SRQ UINT32_C(0x1)
4600 /* CQE relates to RQ WQE. */
4601 #define CQ_RES_UD_FLAGS_SRQ_RQ (UINT32_C(0x0) << 0)
4602 /* CQE relates to SRQ WQE. */
4603 #define CQ_RES_UD_FLAGS_SRQ_SRQ (UINT32_C(0x1) << 0)
4604 #define CQ_RES_UD_FLAGS_SRQ_LAST CQ_RES_UD_FLAGS_SRQ_SRQ
4605 /* Immediate data indicator */
4606 #define CQ_RES_UD_FLAGS_IMM UINT32_C(0x2)
4607 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK UINT32_C(0xc)
4608 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT 2
4609 /* RoCEv1 Message */
4610 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 2)
4611 /* RoCEv2 IPv4 Message */
4612 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 2)
4613 /* RoCEv2 IPv6 Message */
4614 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 2)
4615 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6
4616 uint32_t src_qp_high_srq_or_rq_wr_id;
4617 /* Upper 8b of the Source QP value from the DETH header. */
4619 * Opaque value from RQ or SRQ WQE. Used by driver/lib to reference the
4620 * WQE in order to claim the received data and reuse the WQE space
4622 #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
4623 #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_SFT 0
4624 #define CQ_RES_UD_RESERVED4_MASK UINT32_C(0xf00000)
4625 #define CQ_RES_UD_RESERVED4_SFT 20
4626 /* Upper 8b of the Source QP value from the DETH header. */
4627 #define CQ_RES_UD_SRC_QP_HIGH_MASK UINT32_C(0xff000000)
4628 #define CQ_RES_UD_SRC_QP_HIGH_SFT 24
4629 } __attribute__((packed));
4631 /* Responder RawEth and QP1 CQE (32 bytes) */
4633 struct cq_res_raweth_qp1 {
4635 /* The length of the message's payload in bytes, stored in the SGEs */
4636 #define CQ_RES_RAWETH_QP1_LENGTH_MASK UINT32_C(0x3fff)
4637 #define CQ_RES_RAWETH_QP1_LENGTH_SFT 0
4638 #define CQ_RES_RAWETH_QP1_RESERVED2_MASK UINT32_C(0xc000)
4639 #define CQ_RES_RAWETH_QP1_RESERVED2_SFT 14
4640 uint16_t raweth_qp1_flags;
4642 * When this bit is '1', it indicates a packet that has an error of some
4643 * type. Type of error is indicated in raweth_qp1_errors.
4645 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ERROR UINT32_C(0x1)
4646 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_RESERVED5_1_MASK UINT32_C(0x3e)
4647 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_RESERVED5_1_SFT 1
4649 * This value indicates what the inner packet determined for the packet
4652 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_MASK UINT32_C(0x3c0)
4653 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_SFT 6
4654 /* Not Known: Indicates that the packet type was not known. */
4655 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 6)
4657 * IP Packet: Indicates that the packet was an IP packet, but
4658 * further classification was not possible.
4660 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_IP (UINT32_C(0x1) << 6)
4662 * TCP Packet: Indicates that the packet was IP and TCP. This
4663 * indicates that the raweth_qp1_payload_offset field is valid.
4665 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 6)
4667 * UDP Packet: Indicates that the packet was IP and UDP. This
4668 * indicates that the raweth_qp1_payload_offset field is valid.
4670 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 6)
4672 * FCoE Packet: Indicates that the packet was recognized as a
4673 * FCoE. This also indicates that the raweth_qp1_payload_offset
4676 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 6)
4678 * RoCE Packet: Indicates that the packet was recognized as a
4679 * RoCE. This also indicates that the raweth_qp1_payload_offset
4682 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 6)
4684 * ICMP Packet: Indicates that the packet was recognized as
4685 * ICMP. This indicates that the raweth_qp1_payload_offset field
4688 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 6)
4690 * PtP packet wo/timestamp: Indicates that the packet was
4691 * recognized as a PtP packet.
4693 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 6)
4695 * PtP packet w/timestamp: Indicates that the packet was
4696 * recognized as a PtP packet and that a timestamp was taken for
4699 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 6)
4700 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP
4701 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_MASK UINT32_C(0x3ff)
4702 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_SFT 0
4703 #define CQ_RES_RAWETH_QP1_RESERVED6_MASK UINT32_C(0xfc00)
4704 #define CQ_RES_RAWETH_QP1_RESERVED6_SFT 10
4705 uint16_t raweth_qp1_errors;
4706 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_RESERVED4_MASK UINT32_C(0xf)
4707 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_RESERVED4_SFT 0
4708 /* This indicates that there was an error in the IP header checksum. */
4709 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_IP_CS_ERROR UINT32_C(0x10)
4711 * This indicates that there was an error in the TCP, UDP or ICMP
4714 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_L4_CS_ERROR UINT32_C(0x20)
4716 * This indicates that there was an error in the tunnel IP header
4719 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_IP_CS_ERROR UINT32_C(0x40)
4720 /* This indicates that there was an error in the tunnel UDP checksum. */
4721 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_L4_CS_ERROR UINT32_C(0x80)
4723 * This indicates that there was a CRC error on either an FCoE or RoCE
4724 * packet. The itype indicates the packet type.
4726 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_CRC_ERROR UINT32_C(0x100)
4728 * This indicates that there was an error in the tunnel portion of the
4729 * packet when this field is non-zero.
4731 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00)
4732 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9
4734 * No additional error occurred on the tunnel portion of the
4735 * packet of the packet does not have a tunnel.
4737 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9)
4739 * Indicates that IP header version does not match expectation
4740 * from L2 Ethertype for IPv4 and IPv6 in the tunnel header.
4742 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9)
4744 * Indicates that header length is out of range in the tunnel
4745 * header. Valid for IPv4.
4747 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9)
4749 * Indicates that the physical packet is shorter than that
4750 * claimed by the PPPoE header length for a tunnel PPPoE packet.
4752 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (UINT32_C(0x3) << 9)
4754 * Indicates that physical packet is shorter than that claimed
4755 * by the tunnel l3 header length. Valid for IPv4, or IPv6
4756 * tunnel packet packets.
4758 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x4) << 9)
4760 * Indicates that the physical packet is shorter than that
4761 * claimed by the tunnel UDP header length for a tunnel UDP
4762 * packet that is not fragmented.
4764 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x5) << 9)
4766 * indicates that the IPv4 TTL or IPv6 hop limit check have
4767 * failed (e.g. TTL = 0) in the tunnel header. Valid for IPv4,
4770 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x6) << 9)
4771 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
4773 * This indicates that there was an error in the inner portion of the
4774 * packet when this field is non-zero.
4776 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000)
4777 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12
4779 * No additional error occurred on the tunnel portion of the
4780 * packet of the packet does not have a tunnel.
4782 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12)
4784 * Indicates that IP header version does not match expectation
4785 * from L2 Ethertype for IPv4 and IPv6 or that option other than
4786 * VFT was parsed on FCoE packet.
4788 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12)
4790 * indicates that header length is out of range. Valid for IPv4
4793 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12)
4795 * indicates that the IPv4 TTL or IPv6 hop limit check have
4796 * failed (e.g. TTL = 0). Valid for IPv4, and IPv6
4798 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12)
4800 * Indicates that physical packet is shorter than that claimed
4801 * by the l3 header length. Valid for IPv4, IPv6 packet or RoCE
4804 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12)
4806 * Indicates that the physical packet is shorter than that
4807 * claimed by the UDP header length for a UDP packet that is not
4810 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12)
4812 * Indicates that TCP header length > IP payload. Valid for TCP
4815 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12)
4816 /* Indicates that TCP header length < 5. Valid for TCP. */
4817 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) << 12)
4819 * Indicates that TCP option headers result in a TCP header size
4820 * that does not match data offset in TCP header. Valid for TCP.
4822 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12)
4823 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
4824 uint16_t raweth_qp1_cfa_code;
4826 * This field identifies the CFA action rule that was used for this
4831 * This is an application level ID used to identify the QP and its SQ
4834 uint32_t raweth_qp1_flags2;
4836 * This indicates that the ip checksum was calculated for the inner
4837 * packet and that the ip_cs_error field indicates if there was an
4840 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC UINT32_C(0x1)
4842 * This indicates that the TCP, UDP or ICMP checksum was calculated for
4843 * the inner packet and that the l4_cs_error field indicates if there
4846 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC UINT32_C(0x2)
4848 * This indicates that the ip checksum was calculated for the tunnel
4849 * header and that the t_ip_cs_error field indicates if there was an
4852 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
4854 * This indicates that the UDP checksum was calculated for the tunnel
4855 * packet and that the t_l4_cs_error field indicates if there was an
4858 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
4859 /* This value indicates what format the raweth_qp1_metadata field is. */
4860 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
4861 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4
4862 /* No metadata information. Value is zero. */
4863 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
4865 * The raweth_qp1_metadata field contains the VLAN tag and TPID
4866 * value. - raweth_qp1_metadata[11:0] contains the vlan VID
4867 * value. - raweth_qp1_metadata[12] contains the vlan DE value.
4868 * - raweth_qp1_metadata[15:13] contains the vlan PRI value. -
4869 * raweth_qp1_metadata[31:16] contains the vlan TPID value.
4871 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
4872 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_LAST CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN
4874 * This field indicates the IP type for the inner-most IP header. A
4875 * value of '0' indicates IPv4. A value of '1' indicates IPv6. This
4876 * value is only valid if itype indicates a packet with an IP header.
4878 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE UINT32_C(0x100)
4879 uint32_t raweth_qp1_metadata;
4881 * This is data from the CFA block as indicated by the meta_format
4884 /* When meta_format=1, this value is the VLAN VID. */
4885 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK UINT32_C(0xfff)
4886 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_SFT 0
4887 /* When meta_format=1, this value is the VLAN DE. */
4888 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_DE UINT32_C(0x1000)
4889 /* When meta_format=1, this value is the VLAN PRI. */
4890 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK UINT32_C(0xe000)
4891 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT 13
4892 /* When meta_format=1, this value is the VLAN TPID. */
4893 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK UINT32_C(0xffff0000)
4894 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT 16
4895 uint8_t cqe_type_toggle;
4897 * Indicate valid completion - written by the chip. Cumulus toggle this
4898 * bit each time it finished consuming all PBL entries
4900 #define CQ_RES_RAWETH_QP1_TOGGLE UINT32_C(0x1)
4901 /* This field defines the type of SQ WQE. */
4902 #define CQ_RES_RAWETH_QP1_CQE_TYPE_MASK UINT32_C(0x1e)
4903 #define CQ_RES_RAWETH_QP1_CQE_TYPE_SFT 1
4905 * Responder RawEth and QP1 Completion - This is used for RQ
4906 * completion for RawEth service and QP1 service QPs.
4908 #define CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 (UINT32_C(0x3) << 1)
4909 #define CQ_RES_RAWETH_QP1_RESERVED3_MASK UINT32_C(0xe0)
4910 #define CQ_RES_RAWETH_QP1_RESERVED3_SFT 5
4912 /* This field indicates the status for the CQE. */
4914 * This indicates that the completion is without error. All
4917 #define CQ_RES_RAWETH_QP1_STATUS_OK UINT32_C(0x0)
4919 * This indicates that write access was not allowed for at least
4920 * one of the SGEs in the WQE. This is a fatal error. Only the
4921 * srq_or_rq_wr_id is field is valid.
4923 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1)
4925 * This indicates that the packet was too long for the WQE
4926 * provided on the RQ. This is not a fatal error. All the fields
4929 #define CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2)
4930 /* LOCAL_PROTECTION_ERR is 3 */
4931 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3)
4932 /* LOCAL_QP_OPERATION_ERR is 4 */
4933 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
4934 /* MEMORY_MGT_OPERATION_ERR is 5 */
4935 #define CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
4936 /* WORK_REQUEST_FLUSHED_ERR is 7 */
4937 #define CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
4938 /* HW_FLUSH_ERR is 8 */
4939 #define CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR UINT32_C(0x8)
4942 * This flag indicates that the completion is for a SRQ entry rather
4943 * than for an RQ entry.
4945 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ UINT32_C(0x1)
4946 /* CQE relates to RQ WQE. */
4947 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_RQ UINT32_C(0x0)
4948 /* CQE relates to SRQ WQE. */
4949 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ UINT32_C(0x1)
4950 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ
4951 uint32_t raweth_qp1_payload_offset_srq_or_rq_wr_id;
4953 * This value indicates the offset in bytes from the beginning of the
4954 * packet where the inner payload starts. This value is valid for TCP,
4955 * UDP, FCoE, and RoCE packets. A value of zero indicates an offset of
4959 * Opaque value from RQ or SRQ WQE. Used by driver/lib to reference the
4960 * WQE in order to claim the received data and reuse the WQE space
4962 #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
4963 #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_SFT 0
4964 #define CQ_RES_RAWETH_QP1_RESERVED4_MASK UINT32_C(0xf00000)
4965 #define CQ_RES_RAWETH_QP1_RESERVED4_SFT 20
4967 * This value indicates the offset in bytes from the beginning of the
4968 * packet where the inner payload starts. This value is valid for TCP,
4969 * UDP, FCoE, and RoCE packets. A value of zero indicates an offset of
4972 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_MASK UINT32_C(0xff000000)
4973 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24
4974 } __attribute__((packed));
4976 /* Terminal CQE (32 bytes) */
4978 struct cq_terminal {
4981 * This is an application level ID used to identify the QP and its SQ
4984 uint16_t sq_cons_idx;
4986 * Final SQ Consumer Index value. Any additional SQ WQEs will have to be
4987 * completed by the user provider.
4989 uint16_t rq_cons_idx;
4991 * Final RQ Consumer Index value. Any additional RQ WQEs will have to be
4992 * completed by the user provider.
4994 uint32_t reserved32_1;
4995 uint64_t reserved64_3;
4996 uint8_t cqe_type_toggle;
4998 * Indicate valid completion - written by the chip. Cumulus toggle this
4999 * bit each time it finished consuming all PBL entries
5001 #define CQ_TERMINAL_TOGGLE UINT32_C(0x1)
5002 /* This field defines the type of SQ WQE. */
5003 #define CQ_TERMINAL_CQE_TYPE_MASK UINT32_C(0x1e)
5004 #define CQ_TERMINAL_CQE_TYPE_SFT 1
5006 * Terminal completion - This is used to indicate that no
5007 * further completions will be made for this QP on this CQ.
5009 #define CQ_TERMINAL_CQE_TYPE_TERMINAL (UINT32_C(0xe) << 1)
5010 #define CQ_TERMINAL_RESERVED3_MASK UINT32_C(0xe0)
5011 #define CQ_TERMINAL_RESERVED3_SFT 5
5013 /* This field indicates the status for the CQE. */
5015 #define CQ_TERMINAL_STATUS_OK UINT32_C(0x0)
5016 uint16_t reserved16;
5017 uint32_t reserved32_2;
5018 } __attribute__((packed));
5020 /* Cutoff CQE (32 bytes) */
5023 uint64_t reserved64_1;
5024 uint64_t reserved64_2;
5025 uint64_t reserved64_3;
5026 uint8_t cqe_type_toggle;
5028 * Indicate valid completion - written by the chip. Cumulus toggle this
5029 * bit each time it finished consuming all PBL entries
5031 #define CQ_CUTOFF_TOGGLE UINT32_C(0x1)
5032 /* This field defines the type of SQ WQE. */
5033 #define CQ_CUTOFF_CQE_TYPE_MASK UINT32_C(0x1e)
5034 #define CQ_CUTOFF_CQE_TYPE_SFT 1
5035 /* Cut off CQE; for CQ resize see CQ and SRQ Resize */
5036 #define CQ_CUTOFF_CQE_TYPE_CUT_OFF (UINT32_C(0xf) << 1)
5037 #define CQ_CUTOFF_RESERVED3_MASK UINT32_C(0xe0)
5038 #define CQ_CUTOFF_RESERVED3_SFT 5
5040 /* This field indicates the status for the CQE. */
5042 #define CQ_CUTOFF_STATUS_OK UINT32_C(0x0)
5043 uint16_t reserved16;
5044 uint32_t reserved32;
5045 } __attribute__((packed));
5047 /* Notification Queue (NQ) Structures */
5049 * Description: This completion indicates that the DBQ has reached the
5050 * programmed threshold value.
5052 /* Base NQ Record (16 bytes) */
5055 uint16_t info10_type;
5056 /* info10 is 10 b */
5058 * This field indicates the exact type of the completion. By convention,
5059 * the LSB identifies the length of the record in 16B units. Even values
5060 * indicate 16B records. Odd values indicate 32B records.
5062 #define NQ_BASE_TYPE_MASK UINT32_C(0x3f)
5063 #define NQ_BASE_TYPE_SFT 0
5064 /* CQ Notification */
5065 #define NQ_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
5066 /* SRQ Threshold Event */
5067 #define NQ_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
5068 /* DBQ Threshold Event */
5069 #define NQ_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
5070 /* QP Async Notification */
5071 #define NQ_BASE_TYPE_QP_EVENT UINT32_C(0x38)
5072 /* Function Async Notification */
5073 #define NQ_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
5074 /* info10 is 10 b */
5075 #define NQ_BASE_INFO10_MASK UINT32_C(0xffc0)
5076 #define NQ_BASE_INFO10_SFT 6
5078 /* info16 is 16 b */
5080 /* info32 is 32 b */
5082 /* info63 is 63 b */
5084 * This value is written by the NIC such that it will be different for
5085 * each pass through the completion queue. The even passes will write 1.
5086 * The odd passes will write 0.
5088 #define NQ_BASE_V UINT32_C(0x1)
5089 /* info63 is 63 b */
5090 #define NQ_BASE_INFO63_MASK UINT32_C(0xfffffffe)
5091 #define NQ_BASE_INFO63_SFT 1
5092 } __attribute__((packed));
5094 /* Completion Queue Notification (16 bytes) */
5099 * This field indicates the exact type of the completion. By convention,
5100 * the LSB identifies the length of the record in 16B units. Even values
5101 * indicate 16B records. Odd values indicate 32B records.
5103 #define NQ_CN_TYPE_MASK UINT32_C(0x3f)
5104 #define NQ_CN_TYPE_SFT 0
5105 /* CQ Notification */
5106 #define NQ_CN_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
5107 #define NQ_CN_RESERVED9_MASK UINT32_C(0xffc0)
5108 #define NQ_CN_RESERVED9_SFT 6
5109 uint16_t reserved16;
5110 uint32_t cq_handle_low;
5112 * This is an application level ID used to identify the CQ. This field
5113 * carries the lower 32b of the value.
5117 * This value is written by the NIC such that it will be different for
5118 * each pass through the completion queue. The even passes will write 1.
5119 * The odd passes will write 0.
5121 #define NQ_CN_V UINT32_C(0x1)
5122 #define NQ_CN_RESERVED31_MASK UINT32_C(0xfffffffe)
5123 #define NQ_CN_RESERVED31_SFT 1
5124 uint32_t cq_handle_high;
5126 * This is an application level ID used to identify the CQ. This field
5127 * carries the upper 32b of the value.
5129 } __attribute__((packed));
5131 /* SRQ Event Notification (16 bytes) */
5133 struct nq_srq_event {
5136 * This field indicates the exact type of the completion. By convention,
5137 * the LSB identifies the length of the record in 16B units. Even values
5138 * indicate 16B records. Odd values indicate 32B records.
5140 #define NQ_SRQ_EVENT_TYPE_MASK UINT32_C(0x3f)
5141 #define NQ_SRQ_EVENT_TYPE_SFT 0
5142 /* SRQ Threshold Event */
5143 #define NQ_SRQ_EVENT_TYPE_SRQ_EVENT UINT32_C(0x32)
5144 #define NQ_SRQ_EVENT_RESERVED1_MASK UINT32_C(0xc0)
5145 #define NQ_SRQ_EVENT_RESERVED1_SFT 6
5147 /* This value define what type of async event has occurred on the SRQ. */
5148 /* The threshold event has occurred on the specified SRQ. */
5149 #define NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT UINT32_C(0x1)
5150 uint16_t reserved16;
5151 uint32_t srq_handle_low;
5153 * This is the SRQ handle value for the queue that has reached it's
5154 * event threshold. This field carries the lower 32b of the value.
5158 * This value is written by the NIC such that it will be different for
5159 * each pass through the completion queue. The even passes will write 1.
5160 * The odd passes will write 0.
5162 #define NQ_SRQ_EVENT_V UINT32_C(0x1)
5163 #define NQ_SRQ_EVENT_RESERVED31_MASK UINT32_C(0xfffffffe)
5164 #define NQ_SRQ_EVENT_RESERVED31_SFT 1
5165 uint32_t srq_handle_high;
5167 * This is the SRQ handle value for the queue that has reached it's
5168 * event threshold. This field carries the upper 32b of the value.
5170 } __attribute__((packed));
5172 /* DBQ Async Event Notification (16 bytes) */
5174 struct nq_dbq_event {
5177 * This field indicates the exact type of the completion. By convention,
5178 * the LSB identifies the length of the record in 16B units. Even values
5179 * indicate 16B records. Odd values indicate 32B records.
5181 #define NQ_DBQ_EVENT_TYPE_MASK UINT32_C(0x3f)
5182 #define NQ_DBQ_EVENT_TYPE_SFT 0
5183 /* DBQ Threshold Event */
5184 #define NQ_DBQ_EVENT_TYPE_DBQ_EVENT UINT32_C(0x34)
5185 #define NQ_DBQ_EVENT_RESERVED1_MASK UINT32_C(0xc0)
5186 #define NQ_DBQ_EVENT_RESERVED1_SFT 6
5188 /* This value define what type of action the driver should take. */
5190 * The driver should start writing dummy values to the the
5191 * doorbell in an attempt to consume all the PCIE posted write
5192 * resources and prevent doorbell overflow.
5194 #define NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT UINT32_C(0x1)
5197 * This is the PFID of function that wrote the doorbell that crossed the
5198 * async event threshold.
5200 #define NQ_DBQ_EVENT_DB_PFID_MASK UINT32_C(0xf)
5201 #define NQ_DBQ_EVENT_DB_PFID_SFT 0
5202 #define NQ_DBQ_EVENT_RESERVED12_MASK UINT32_C(0xfff0)
5203 #define NQ_DBQ_EVENT_RESERVED12_SFT 4
5206 * This is the DPI of the doorbell write that crossed the async event
5209 #define NQ_DBQ_EVENT_DB_DPI_MASK UINT32_C(0xfffff)
5210 #define NQ_DBQ_EVENT_DB_DPI_SFT 0
5211 #define NQ_DBQ_EVENT_RESERVED12_2_MASK UINT32_C(0xfff00000)
5212 #define NQ_DBQ_EVENT_RESERVED12_2_SFT 20
5215 * This value is written by the NIC such that it will be different for
5216 * each pass through the completion queue. The even passes will write 1.
5217 * The odd passes will write 0.
5219 #define NQ_DBQ_EVENT_V UINT32_C(0x1)
5220 #define NQ_DBQ_EVENT_RESERVED32_MASK UINT32_C(0xfffffffe)
5221 #define NQ_DBQ_EVENT_RESERVED32_SFT 1
5222 uint32_t db_type_db_xid;
5223 /* DB 'type' field from doorbell that crossed the async event threshold. */
5225 * DB 'XID' field from doorbell that crossed the async event threshold.
5226 * This is a QPID, SID, or CID, depending on the db_type field.
5228 #define NQ_DBQ_EVENT_DB_XID_MASK UINT32_C(0xfffff)
5229 #define NQ_DBQ_EVENT_DB_XID_SFT 0
5230 #define NQ_DBQ_EVENT_RESERVED8_MASK UINT32_C(0xff00000)
5231 #define NQ_DBQ_EVENT_RESERVED8_SFT 20
5232 /* DB 'type' field from doorbell that crossed the async event threshold. */
5233 #define NQ_DBQ_EVENT_DB_TYPE_MASK UINT32_C(0xf0000000)
5234 #define NQ_DBQ_EVENT_DB_TYPE_SFT 28
5235 } __attribute__((packed));
5237 /* Read Request/Response Queue Structures */
5239 * Description: This queue messages is used on the ORRQ to indicate output read
5240 * requests to the RX side of the chip.
5242 /* Input Read Request Queue (IRRQ) Message (32 bytes) */
5245 uint16_t credits_type;
5247 * The credit code calculated by Rx path when receiving the request. It
5248 * will be placed in the syndrome credit code with the acks on first and
5251 /* Type indication */
5252 #define XRRQ_IRRQ_TYPE UINT32_C(0x1)
5254 #define XRRQ_IRRQ_TYPE_READ_REQ UINT32_C(0x0)
5256 #define XRRQ_IRRQ_TYPE_ATOMIC_REQ UINT32_C(0x1)
5257 #define XRRQ_IRRQ_RESERVED10_MASK UINT32_C(0x7fe)
5258 #define XRRQ_IRRQ_RESERVED10_SFT 1
5260 * The credit code calculated by Rx path when receiving the request. It
5261 * will be placed in the syndrome credit code with the acks on first and
5264 #define XRRQ_IRRQ_CREDITS_MASK UINT32_C(0xf800)
5265 #define XRRQ_IRRQ_CREDITS_SFT 11
5266 uint16_t reserved16;
5267 uint32_t reserved32;
5269 /* The PSN of the outstanding incoming request */
5270 #define XRRQ_IRRQ_PSN_MASK UINT32_C(0xffffff)
5271 #define XRRQ_IRRQ_PSN_SFT 0
5272 #define XRRQ_IRRQ_RESERVED8_1_MASK UINT32_C(0xff000000)
5273 #define XRRQ_IRRQ_RESERVED8_1_SFT 24
5276 * The value of QPC.pending_ack_msn after it is incremented as a result
5277 * of receiving the read/atomic request. IRRQ.msn-1 will be placed in
5278 * the MSN field of the first response and IRRQ.msn will placed in the
5279 * MSN field of the last or only response.
5281 #define XRRQ_IRRQ_MSN_MASK UINT32_C(0xffffff)
5282 #define XRRQ_IRRQ_MSN_SFT 0
5283 #define XRRQ_IRRQ_RESERVED8_2_MASK UINT32_C(0xff000000)
5284 #define XRRQ_IRRQ_RESERVED8_2_SFT 24
5285 uint64_t va_or_atomic_result;
5287 * Virtual address on local host for RDMA READ In case of duplicate
5288 * Atomic, the VA is not required to be validated, only the PSN is, thus
5289 * this field is used to store the value returned in the Ack to the
5290 * atomic request, and if duplicate arrives, this value is used again
5291 * for resending the ack.
5293 uint32_t rdma_r_key;
5294 /* The key to the MR/W in the request */
5297 * Length in bytes of the data requested. Length must be 8 if type is
5300 } __attribute__((packed));
5302 /* Output Read Request Queue (ORRQ) Message (32 bytes) */
5305 uint16_t num_sges_type;
5307 * Up to 6 SGEs. This value is 1 if type is atomic as one SGE is
5308 * required to store Atomic response result field. 2 more bits allocated
5309 * for future growth. Note that, if num_sges is 1 for an RDMA Read
5310 * request, then the first_sge_phy_or_sing_sge_va, single_sge_l_key, and
5311 * single_sge_size fields will be populated from the single SGE. If
5312 * num_sges is 2 or more for an RDMA Read request, then the
5313 * first_sge_phy_or_sing_sge_va field carries the physical address in
5314 * host memory where the first sge is stored. The single_sge_l_key and
5315 * single_sge_size fields are unused in this case. A special case is a
5316 * zero-length, zero-sge RDMA read request WQE. In this situation,
5317 * num_sges will be 1. However, first_sge_phy_or_sing_sge_va,
5318 * single_sge_l_key, and single_sge_size will all be populated with
5321 /* Type indication */
5322 #define XRRQ_ORRQ_TYPE UINT32_C(0x1)
5324 #define XRRQ_ORRQ_TYPE_READ_REQ UINT32_C(0x0)
5326 #define XRRQ_ORRQ_TYPE_ATOMIC_REQ UINT32_C(0x1)
5327 #define XRRQ_ORRQ_RESERVED10_MASK UINT32_C(0x7fe)
5328 #define XRRQ_ORRQ_RESERVED10_SFT 1
5330 * Up to 6 SGEs. This value is 1 if type is atomic as one SGE is
5331 * required to store Atomic response result field. 2 more bits allocated
5332 * for future growth. Note that, if num_sges is 1 for an RDMA Read
5333 * request, then the first_sge_phy_or_sing_sge_va, single_sge_l_key, and
5334 * single_sge_size fields will be populated from the single SGE. If
5335 * num_sges is 2 or more for an RDMA Read request, then the
5336 * first_sge_phy_or_sing_sge_va field carries the physical address in
5337 * host memory where the first sge is stored. The single_sge_l_key and
5338 * single_sge_size fields are unused in this case. A special case is a
5339 * zero-length, zero-sge RDMA read request WQE. In this situation,
5340 * num_sges will be 1. However, first_sge_phy_or_sing_sge_va,
5341 * single_sge_l_key, and single_sge_size will all be populated with
5344 #define XRRQ_ORRQ_NUM_SGES_MASK UINT32_C(0xf800)
5345 #define XRRQ_ORRQ_NUM_SGES_SFT 11
5346 uint16_t reserved16;
5349 * Length in bytes of the data requested. Length must be 8 if type is
5353 /* The PSN of the outstanding outgoing request */
5354 #define XRRQ_ORRQ_PSN_MASK UINT32_C(0xffffff)
5355 #define XRRQ_ORRQ_PSN_SFT 0
5356 #define XRRQ_ORRQ_RESERVED8_1_MASK UINT32_C(0xff000000)
5357 #define XRRQ_ORRQ_RESERVED8_1_SFT 24
5360 * The expected last PSN on a response to this request where an ack with
5361 * response, rather than just response, should arrive. If ack arrive
5362 * with smaller PSN than end_psn then it is considered a NAK.
5364 #define XRRQ_ORRQ_END_PSN_MASK UINT32_C(0xffffff)
5365 #define XRRQ_ORRQ_END_PSN_SFT 0
5366 #define XRRQ_ORRQ_RESERVED8_2_MASK UINT32_C(0xff000000)
5367 #define XRRQ_ORRQ_RESERVED8_2_SFT 24
5368 uint64_t first_sge_phy_or_sing_sge_va;
5370 * If num_sges == 1 this is the va of that SGE. Otherwise, physical
5371 * address to the first SGE specified by the WQE. Points to the first
5372 * SGE in the Request's WQE in the SQ. It is assumed that WQE does not
5373 * cross page boundaries! Driver is responsible to enforce that. SGEs
5374 * are 16B aligned 0b0000 lsb added to get 64 bit address.
5376 uint32_t single_sge_l_key;
5377 /* The L_Key of a single SGE if used */
5378 uint32_t single_sge_size;
5379 /* The size in bytes of the single SGE if used */
5380 } __attribute__((packed));
5382 /* Page Buffer List Memory Structures (PBL) */
5384 * Description: Page directory entries point to a page directories made up of
5387 /* Page Table Entry (PTE) (8 bytes) */
5390 uint64_t page_next_to_last_last_valid;
5392 * This is the upper bits of the physical page controlled by this PTE.
5393 * If the page is larger than 4KB, then the unused lower bits of the
5394 * page address should be zero.
5397 * This field indicates if the PTE is valid. A value of '0' indicates
5398 * that the page is not valid. A value of '1' indicates that the page is
5399 * valid. A reference to an invalid page will return a PTU error.
5401 #define PTU_PTE_VALID UINT32_C(0x1)
5403 * This field is used only for "ring" PBLs that are used for SQ, RQ,
5404 * SRQ, or CQ structures. For all other PBL structures, this bit should
5405 * be zero. When this bit is '1', it indicates that the page pointed to
5406 * by this PTE is the last page in the ring. A prefetch for the ring
5407 * should use the first PTE in the PBL.
5409 #define PTU_PTE_LAST UINT32_C(0x2)
5411 * This field is used only for "ring" PBLs that are used for SQ, RQ,
5412 * SRQ, or CQ structures. For all other PBL structures, this bit should
5413 * be zero. When this bit is '1', it indicates that this is the next-to-
5414 * last page of the PBL.
5416 #define PTU_PTE_NEXT_TO_LAST UINT32_C(0x4)
5417 /* These bits should be programmed to zero. */
5419 * This is the upper bits of the physical page controlled by this PTE.
5420 * If the page is larger than 4KB, then the unused lower bits of the
5421 * page address should be zero.
5423 #define PTU_PTE_PAGE_MASK UINT32_C(0xfffff000)
5424 #define PTU_PTE_PAGE_SFT 12
5425 } __attribute__((packed));
5427 /* Page Directory Entry (PDE) (8 bytes) */
5430 uint64_t page_valid;
5432 * This is the upper bits of the physical page controlled by this PTE.
5433 * If the page is larger than 4KB, then the unused lower bits of the
5434 * page address should be zero.
5437 * This field indicates if the PTE is valid. A value of '0' indicates
5438 * that the page is not valid. A value of '1' indicates that the page is
5439 * valid. A reference to an invalid page will return a PTU error.
5441 #define PTU_PDE_VALID UINT32_C(0x1)
5442 /* These bits should be programmed to zero. */
5444 * This is the upper bits of the physical page controlled by this PTE.
5445 * If the page is larger than 4KB, then the unused lower bits of the
5446 * page address should be zero.
5448 #define PTU_PDE_PAGE_MASK UINT32_C(0xfffff000)
5449 #define PTU_PDE_PAGE_SFT 12
5450 } __attribute__((packed));
5452 /* RoCE Fastpath Host Structures */
5454 * Note: This section documents the host structures used between RoCE state
5455 * machines and RoCE drivers/libraries.
5459 * Description: This function is called by a driver to determine the HWRM
5460 * interface version supported by the HWRM firmware, the version of HWRM
5461 * firmware implementation, the name of HWRM firmware, the versions of other
5462 * embedded firmwares, and the names of other embedded firmwares, etc. Any
5463 * interface or firmware version with major = 0, minor = 0, and update = 0 shall
5464 * be considered an invalid version.
5466 /* Input (24 bytes) */
5468 struct hwrm_ver_get_input {
5471 * This value indicates what type of request this is. The format for the
5472 * rest of the command is determined by this field.
5476 * This value indicates the what completion ring the request will be
5477 * optionally completed on. If the value is -1, then no CR completion
5478 * will be generated. Any other value must be a valid CR ring_id value
5479 * for this function.
5482 /* This value indicates the command sequence number. */
5485 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
5486 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
5490 * This is the host address where the response will be written when the
5491 * request is complete. This area must be 16B aligned and must be
5492 * cleared to zero before the request is made.
5494 uint8_t hwrm_intf_maj;
5496 * This field represents the major version of HWRM interface
5497 * specification supported by the driver HWRM implementation. The
5498 * interface major version is intended to change only when non backward
5499 * compatible changes are made to the HWRM interface specification.
5501 uint8_t hwrm_intf_min;
5503 * This field represents the minor version of HWRM interface
5504 * specification supported by the driver HWRM implementation. A change
5505 * in interface minor version is used to reflect significant backward
5506 * compatible modification to HWRM interface specification. This can be
5507 * due to addition or removal of functionality. HWRM interface
5508 * specifications with the same major version but different minor
5509 * versions are compatible.
5511 uint8_t hwrm_intf_upd;
5513 * This field represents the update version of HWRM interface
5514 * specification supported by the driver HWRM implementation. The
5515 * interface update version is used to reflect minor changes or bug
5516 * fixes to a released HWRM interface specification.
5518 uint8_t unused_0[5];
5519 } __attribute__((packed));
5521 /* Output (128 bytes) */
5523 struct hwrm_ver_get_output {
5524 uint16_t error_code;
5526 * Pass/Fail or error type Note: receiver to verify the in parameters,
5527 * and fail the call with an error when appropriate
5530 /* This field returns the type of original request. */
5532 /* This field provides original sequence number of the command. */
5535 * This field is the length of the response in bytes. The last byte of
5536 * the response is a valid flag that will read as '1' when the command
5537 * has been completely written to memory.
5539 uint8_t hwrm_intf_maj;
5541 * This field represents the major version of HWRM interface
5542 * specification supported by the HWRM implementation. The interface
5543 * major version is intended to change only when non backward compatible
5544 * changes are made to the HWRM interface specification. A HWRM
5545 * implementation that is compliant with this specification shall
5546 * provide value of 1 in this field.
5548 uint8_t hwrm_intf_min;
5550 * This field represents the minor version of HWRM interface
5551 * specification supported by the HWRM implementation. A change in
5552 * interface minor version is used to reflect significant backward
5553 * compatible modification to HWRM interface specification. This can be
5554 * due to addition or removal of functionality. HWRM interface
5555 * specifications with the same major version but different minor
5556 * versions are compatible. A HWRM implementation that is compliant with
5557 * this specification shall provide value of 2 in this field.
5559 uint8_t hwrm_intf_upd;
5561 * This field represents the update version of HWRM interface
5562 * specification supported by the HWRM implementation. The interface
5563 * update version is used to reflect minor changes or bug fixes to a
5564 * released HWRM interface specification. A HWRM implementation that is
5565 * compliant with this specification shall provide value of 2 in this
5568 uint8_t hwrm_intf_rsvd;
5569 uint8_t hwrm_fw_maj;
5571 * This field represents the major version of HWRM firmware. A change in
5572 * firmware major version represents a major firmware release.
5574 uint8_t hwrm_fw_min;
5576 * This field represents the minor version of HWRM firmware. A change in
5577 * firmware minor version represents significant firmware functionality
5580 uint8_t hwrm_fw_bld;
5582 * This field represents the build version of HWRM firmware. A change in
5583 * firmware build version represents bug fixes to a released firmware.
5585 uint8_t hwrm_fw_rsvd;
5587 * This field is a reserved field. This field can be used to represent
5588 * firmware branches or customer specific releases tied to a specific
5589 * (major,minor,update) version of the HWRM firmware.
5591 uint8_t mgmt_fw_maj;
5593 * This field represents the major version of mgmt firmware. A change in
5594 * major version represents a major release.
5596 uint8_t mgmt_fw_min;
5598 * This field represents the minor version of mgmt firmware. A change in
5599 * minor version represents significant functionality changes.
5601 uint8_t mgmt_fw_bld;
5603 * This field represents the build version of mgmt firmware. A change in
5604 * update version represents bug fixes.
5606 uint8_t mgmt_fw_rsvd;
5608 * This field is a reserved field. This field can be used to represent
5609 * firmware branches or customer specific releases tied to a specific
5610 * (major,minor,update) version
5612 uint8_t netctrl_fw_maj;
5614 * This field represents the major version of network control firmware.
5615 * A change in major version represents a major release.
5617 uint8_t netctrl_fw_min;
5619 * This field represents the minor version of network control firmware.
5620 * A change in minor version represents significant functionality
5623 uint8_t netctrl_fw_bld;
5625 * This field represents the build version of network control firmware.
5626 * A change in update version represents bug fixes.
5628 uint8_t netctrl_fw_rsvd;
5630 * This field is a reserved field. This field can be used to represent
5631 * firmware branches or customer specific releases tied to a specific
5632 * (major,minor,update) version
5634 uint32_t dev_caps_cfg;
5636 * This field is used to indicate device's capabilities and
5640 * If set to 1, then secure firmware update behavior is supported. If
5641 * set to 0, then secure firmware update behavior is not supported.
5643 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED UINT32_C(0x1)
5645 * If set to 1, then firmware based DCBX agent is supported. If set to
5646 * 0, then firmware based DCBX agent capability is not supported on this
5649 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED UINT32_C(0x2)
5651 * If set to 1, then HWRM short command format is supported. If set to
5652 * 0, then HWRM short command format is not supported.
5654 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED UINT32_C(0x4)
5656 * If set to 1, then HWRM short command format is required. If set to 0,
5657 * then HWRM short command format is not required.
5659 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED UINT32_C(0x8)
5660 uint8_t roce_fw_maj;
5662 * This field represents the major version of RoCE firmware. A change in
5663 * major version represents a major release.
5665 uint8_t roce_fw_min;
5667 * This field represents the minor version of RoCE firmware. A change in
5668 * minor version represents significant functionality changes.
5670 uint8_t roce_fw_bld;
5672 * This field represents the build version of RoCE firmware. A change in
5673 * update version represents bug fixes.
5675 uint8_t roce_fw_rsvd;
5677 * This field is a reserved field. This field can be used to represent
5678 * firmware branches or customer specific releases tied to a specific
5679 * (major,minor,update) version
5681 char hwrm_fw_name[16];
5683 * This field represents the name of HWRM FW (ASCII chars with NULL at
5686 char mgmt_fw_name[16];
5688 * This field represents the name of mgmt FW (ASCII chars with NULL at
5691 char netctrl_fw_name[16];
5693 * This field represents the name of network control firmware (ASCII
5694 * chars with NULL at the end).
5696 uint32_t reserved2[4];
5698 * This field is reserved for future use. The responder should set it to
5699 * 0. The requester should ignore this field.
5701 char roce_fw_name[16];
5703 * This field represents the name of RoCE FW (ASCII chars with NULL at
5707 /* This field returns the chip number. */
5709 /* This field returns the revision of chip. */
5711 /* This field returns the chip metal number. */
5712 uint8_t chip_bond_id;
5713 /* This field returns the bond id of the chip. */
5714 uint8_t chip_platform_type;
5716 * This value indicates the type of platform used for chip
5720 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
5721 /* FPGA platform of the chip. */
5722 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
5723 /* Palladium platform of the chip. */
5724 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
5725 uint16_t max_req_win_len;
5727 * This field returns the maximum value of request window that is
5728 * supported by the HWRM. The request window is mapped into device
5729 * address space using MMIO.
5731 uint16_t max_resp_len;
5732 /* This field returns the maximum value of response buffer in bytes. */
5733 uint16_t def_req_timeout;
5734 /* This field returns the default request timeout value in milliseconds. */
5735 uint8_t init_pending;
5736 /* This field will indicate if any subsystems is not fully initialized. */
5738 * If set to 1, device is not ready. If set to 0, device is ready to
5739 * accept all HWRM commands.
5741 #define HWRM_VER_GET_OUTPUT_INIT_PENDING_DEV_NOT_RDY UINT32_C(0x1)
5746 * This field is used in Output records to indicate that the output is
5747 * completely written to RAM. This field should be read as '1' to
5748 * indicate that the output has been completely written. When writing a
5749 * command completion or response to an internal processor, the order of
5750 * writes has to be such that this field is written last.
5752 } __attribute__((packed));
5754 /* hwrm_func_reset */
5756 * Description: This command resets a hardware function (PCIe function) and
5757 * frees any resources used by the function. This command shall be initiated by
5758 * the driver after an FLR has occurred to prepare the function for re-use. This
5759 * command may also be initiated by a driver prior to doing it's own
5760 * configuration. This command puts the function into the reset state. In the
5761 * reset state, global and port related features of the chip are not available.
5764 * Note: This command will reset a function that has already been disabled or
5765 * idled. The command returns all the resources owned by the function so a new
5766 * driver may allocate and configure resources normally.
5768 /* Input (24 bytes) */
5770 struct hwrm_func_reset_input {
5773 * This value indicates what type of request this is. The format for the
5774 * rest of the command is determined by this field.
5778 * This value indicates the what completion ring the request will be
5779 * optionally completed on. If the value is -1, then no CR completion
5780 * will be generated. Any other value must be a valid CR ring_id value
5781 * for this function.
5784 /* This value indicates the command sequence number. */
5787 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
5788 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
5792 * This is the host address where the response will be written when the
5793 * request is complete. This area must be 16B aligned and must be
5794 * cleared to zero before the request is made.
5797 /* This bit must be '1' for the vf_id_valid field to be configured. */
5798 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
5801 * The ID of the VF that this PF is trying to reset. Only the parent PF
5802 * shall be allowed to reset a child VF. A parent PF driver shall use
5803 * this field only when a specific child VF is requested to be reset.
5805 uint8_t func_reset_level;
5806 /* This value indicates the level of a function reset. */
5808 * Reset the caller function and its children VFs (if any). If
5809 * no children functions exist, then reset the caller function
5812 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL UINT32_C(0x0)
5813 /* Reset the caller function only */
5814 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME UINT32_C(0x1)
5816 * Reset all children VFs of the caller function driver if the
5817 * caller is a PF driver. It is an error to specify this level
5818 * by a VF driver. It is an error to specify this level by a PF
5819 * driver with no children VFs.
5821 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN UINT32_C(0x2)
5823 * Reset a specific VF of the caller function driver if the
5824 * caller is the parent PF driver. It is an error to specify
5825 * this level by a VF driver. It is an error to specify this
5826 * level by a PF driver that is not the parent of the VF that is
5827 * being requested to reset.
5829 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF UINT32_C(0x3)
5831 } __attribute__((packed));
5833 /* Output (16 bytes) */
5835 struct hwrm_func_reset_output {
5836 uint16_t error_code;
5838 * Pass/Fail or error type Note: receiver to verify the in parameters,
5839 * and fail the call with an error when appropriate
5842 /* This field returns the type of original request. */
5844 /* This field provides original sequence number of the command. */
5847 * This field is the length of the response in bytes. The last byte of
5848 * the response is a valid flag that will read as '1' when the command
5849 * has been completely written to memory.
5857 * This field is used in Output records to indicate that the output is
5858 * completely written to RAM. This field should be read as '1' to
5859 * indicate that the output has been completely written. When writing a
5860 * command completion or response to an internal processor, the order of
5861 * writes has to be such that this field is written last.
5863 } __attribute__((packed));
5865 /* hwrm_func_getfid */
5867 * Description: This command returns the FID value for the function. If a valid
5868 * pci_id is provided, then this function returns fid for that PCI function.
5869 * Otherwise, it returns FID of the requesting function. This value is needed to
5870 * configure Rings and MSI-X vectors so their DMA operations appear correctly on
5871 * the PCI bus. For PF-HWRM commands, there is no need for FID. Similarly there
5872 * is no need for FID for VF-HWRM commands. In the PF-VF communication, only PF
5873 * needs to know FIDs.
5875 /* Input (24 bytes) */
5877 struct hwrm_func_getfid_input {
5880 * This value indicates what type of request this is. The format for the
5881 * rest of the command is determined by this field.
5885 * This value indicates the what completion ring the request will be
5886 * optionally completed on. If the value is -1, then no CR completion
5887 * will be generated. Any other value must be a valid CR ring_id value
5888 * for this function.
5891 /* This value indicates the command sequence number. */
5894 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
5895 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
5899 * This is the host address where the response will be written when the
5900 * request is complete. This area must be 16B aligned and must be
5901 * cleared to zero before the request is made.
5904 /* This bit must be '1' for the pci_id field to be configured. */
5905 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
5908 * This value is the PCI ID of the queried function. If ARI is enabled,
5909 * then it is Bus Number (8b):Function Number(8b). Otherwise, it is Bus
5910 * Number (8b):Device Number (5b):Function Number(3b).
5913 } __attribute__((packed));
5915 /* Output (16 bytes) */
5917 struct hwrm_func_getfid_output {
5918 uint16_t error_code;
5920 * Pass/Fail or error type Note: receiver to verify the in parameters,
5921 * and fail the call with an error when appropriate
5924 /* This field returns the type of original request. */
5926 /* This field provides original sequence number of the command. */
5929 * This field is the length of the response in bytes. The last byte of
5930 * the response is a valid flag that will read as '1' when the command
5931 * has been completely written to memory.
5935 * FID value. This value is used to identify operations on the PCI bus
5936 * as belonging to a particular PCI function.
5945 * This field is used in Output records to indicate that the output is
5946 * completely written to RAM. This field should be read as '1' to
5947 * indicate that the output has been completely written. When writing a
5948 * command completion or response to an internal processor, the order of
5949 * writes has to be such that this field is written last.
5951 } __attribute__((packed));
5953 /* hwrm_func_vf_alloc */
5955 * Description: This command is used to allocate requested number of virtual
5956 * functions on a physical function. It will return the FID value of the first
5957 * virtual function. The FIDs of the remaining virtual functions can be derived
5958 * by sequentially incrementing the FID value of the first VF. This command
5959 * supports the following models for VF allocation: # Allocation of one or more
5960 * VFs from a PF without specifying the first VF ID # Allocation of multiple VFs
5961 * from a PF starting with a specific VF # Allocation of a specific VF from a PF
5962 * If this command is called on a virtual function or a physical function that
5963 * is not enabled for SR-IOV, the HWRM shall return an error. The VF IDs
5964 * returned by this function remain valid after the VF is disabled or reset.
5966 /* Input (24 bytes) */
5968 struct hwrm_func_vf_alloc_input {
5971 * This value indicates what type of request this is. The format for the
5972 * rest of the command is determined by this field.
5976 * This value indicates the what completion ring the request will be
5977 * optionally completed on. If the value is -1, then no CR completion
5978 * will be generated. Any other value must be a valid CR ring_id value
5979 * for this function.
5982 /* This value indicates the command sequence number. */
5985 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
5986 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
5990 * This is the host address where the response will be written when the
5991 * request is complete. This area must be 16B aligned and must be
5992 * cleared to zero before the request is made.
5995 /* This bit must be '1' for the first_vf_id field to be configured. */
5996 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
5997 uint16_t first_vf_id;
5999 * This value is used to identify a Virtual Function (VF). The scope of
6000 * VF ID is local within a PF.
6003 /* The number of virtual functions requested. */
6004 } __attribute__((packed));
6006 /* Output (16 bytes) */
6008 struct hwrm_func_vf_alloc_output {
6009 uint16_t error_code;
6011 * Pass/Fail or error type Note: receiver to verify the in parameters,
6012 * and fail the call with an error when appropriate
6015 /* This field returns the type of original request. */
6017 /* This field provides original sequence number of the command. */
6020 * This field is the length of the response in bytes. The last byte of
6021 * the response is a valid flag that will read as '1' when the command
6022 * has been completely written to memory.
6024 uint16_t first_vf_id;
6025 /* The ID of the first VF allocated. */
6033 * This field is used in Output records to indicate that the output is
6034 * completely written to RAM. This field should be read as '1' to
6035 * indicate that the output has been completely written. When writing a
6036 * command completion or response to an internal processor, the order of
6037 * writes has to be such that this field is written last.
6039 } __attribute__((packed));
6041 /* hwrm_func_vf_free */
6043 * Description: This command will free allocated virtual functions on a physical
6044 * function. If this command is called on a virtual function or a physical
6045 * function that is not enabled for SR-IOV, the HWRM shall return an error.
6046 * After the successful completion of this command, the VF IDs of the VFs that
6047 * are freed on the PF are invalid.
6049 /* Input (24 bytes) */
6051 struct hwrm_func_vf_free_input {
6054 * This value indicates what type of request this is. The format for the
6055 * rest of the command is determined by this field.
6059 * This value indicates the what completion ring the request will be
6060 * optionally completed on. If the value is -1, then no CR completion
6061 * will be generated. Any other value must be a valid CR ring_id value
6062 * for this function.
6065 /* This value indicates the command sequence number. */
6068 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
6069 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
6073 * This is the host address where the response will be written when the
6074 * request is complete. This area must be 16B aligned and must be
6075 * cleared to zero before the request is made.
6078 /* This bit must be '1' for the first_vf_id field to be configured. */
6079 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
6080 uint16_t first_vf_id;
6082 * This value is used to identify a Virtual Function (VF). The scope of
6083 * VF ID is local within a PF.
6087 * The number of virtual functions requested. 0xFFFF - Cleanup all
6088 * children of this PF.
6090 } __attribute__((packed));
6092 /* Output (16 bytes) */
6094 struct hwrm_func_vf_free_output {
6095 uint16_t error_code;
6097 * Pass/Fail or error type Note: receiver to verify the in parameters,
6098 * and fail the call with an error when appropriate
6101 /* This field returns the type of original request. */
6103 /* This field provides original sequence number of the command. */
6106 * This field is the length of the response in bytes. The last byte of
6107 * the response is a valid flag that will read as '1' when the command
6108 * has been completely written to memory.
6116 * This field is used in Output records to indicate that the output is
6117 * completely written to RAM. This field should be read as '1' to
6118 * indicate that the output has been completely written. When writing a
6119 * command completion or response to an internal processor, the order of
6120 * writes has to be such that this field is written last.
6122 } __attribute__((packed));
6124 /* hwrm_func_vf_cfg */
6126 * Description: This command allows configuration of a VF by its driver. If this
6127 * function is called by a PF driver, then the HWRM shall fail this command. If
6128 * guest VLAN and/or MAC address are provided in this command, then the HWRM
6129 * shall set up appropriate MAC/VLAN filters for the VF that is being
6130 * configured. A VF driver should set VF MTU/MRU using this command prior to
6131 * allocating RX VNICs or TX rings for the corresponding VF.
6133 /* Input (32 bytes) */
6135 struct hwrm_func_vf_cfg_input {
6138 * This value indicates what type of request this is. The format for the
6139 * rest of the command is determined by this field.
6143 * This value indicates the what completion ring the request will be
6144 * optionally completed on. If the value is -1, then no CR completion
6145 * will be generated. Any other value must be a valid CR ring_id value
6146 * for this function.
6149 /* This value indicates the command sequence number. */
6152 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
6153 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
6157 * This is the host address where the response will be written when the
6158 * request is complete. This area must be 16B aligned and must be
6159 * cleared to zero before the request is made.
6162 /* This bit must be '1' for the mtu field to be configured. */
6163 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU UINT32_C(0x1)
6164 /* This bit must be '1' for the guest_vlan field to be configured. */
6165 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN UINT32_C(0x2)
6166 /* This bit must be '1' for the async_event_cr field to be configured. */
6167 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR UINT32_C(0x4)
6168 /* This bit must be '1' for the dflt_mac_addr field to be configured. */
6169 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR UINT32_C(0x8)
6172 * The maximum transmission unit requested on the function. The HWRM
6173 * should make sure that the mtu of the function does not exceed the mtu
6174 * of the physical port that this function is associated with. In
6175 * addition to requesting mtu per function, it is possible to configure
6176 * mtu per transmit ring. By default, the mtu of each transmit ring
6177 * associated with a function is equal to the mtu of the function. The
6178 * HWRM should make sure that the mtu of each transmit ring that is
6179 * assigned to a function has a valid mtu.
6181 uint16_t guest_vlan;
6183 * The guest VLAN for the function being configured. This field's format
6184 * is same as 802.1Q Tag's Tag Control Information (TCI) format that
6185 * includes both Priority Code Point (PCP) and VLAN Identifier (VID).
6187 uint16_t async_event_cr;
6189 * ID of the target completion ring for receiving asynchronous event
6190 * completions. If this field is not valid, then the HWRM shall use the
6191 * default completion ring of the function that is being configured as
6192 * the target completion ring for providing any asynchronous event
6193 * completions for that function. If this field is valid, then the HWRM
6194 * shall use the completion ring identified by this ID as the target
6195 * completion ring for providing any asynchronous event completions for
6196 * the function that is being configured.
6198 uint8_t dflt_mac_addr[6];
6200 * This value is the current MAC address requested by the VF driver to
6201 * be configured on this VF. A value of 00-00-00-00-00-00 indicates no
6202 * MAC address configuration is requested by the VF driver. The parent
6203 * PF driver may reject or overwrite this MAC address.
6205 } __attribute__((packed));
6207 /* Output (16 bytes) */
6209 struct hwrm_func_vf_cfg_output {
6210 uint16_t error_code;
6212 * Pass/Fail or error type Note: receiver to verify the in parameters,
6213 * and fail the call with an error when appropriate
6216 /* This field returns the type of original request. */
6218 /* This field provides original sequence number of the command. */
6221 * This field is the length of the response in bytes. The last byte of
6222 * the response is a valid flag that will read as '1' when the command
6223 * has been completely written to memory.
6231 * This field is used in Output records to indicate that the output is
6232 * completely written to RAM. This field should be read as '1' to
6233 * indicate that the output has been completely written. When writing a
6234 * command completion or response to an internal processor, the order of
6235 * writes has to be such that this field is written last.
6237 } __attribute__((packed));
6239 /* hwrm_func_qcaps */
6241 * Description: This command returns capabilities of a function. The input FID
6242 * value is used to indicate what function is being queried. This allows a
6243 * physical function driver to query virtual functions that are children of the
6244 * physical function. The output FID value is needed to configure Rings and
6245 * MSI-X vectors so their DMA operations appear correctly on the PCI bus.
6247 /* Input (24 bytes) */
6249 struct hwrm_func_qcaps_input {
6252 * This value indicates what type of request this is. The format for the
6253 * rest of the command is determined by this field.
6257 * This value indicates the what completion ring the request will be
6258 * optionally completed on. If the value is -1, then no CR completion
6259 * will be generated. Any other value must be a valid CR ring_id value
6260 * for this function.
6263 /* This value indicates the command sequence number. */
6266 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
6267 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
6271 * This is the host address where the response will be written when the
6272 * request is complete. This area must be 16B aligned and must be
6273 * cleared to zero before the request is made.
6277 * Function ID of the function that is being queried. 0xFF... (All Fs)
6278 * if the query is for the requesting function.
6280 uint16_t unused_0[3];
6281 } __attribute__((packed));
6283 /* Output (80 bytes) */
6285 struct hwrm_func_qcaps_output {
6286 uint16_t error_code;
6288 * Pass/Fail or error type Note: receiver to verify the in parameters,
6289 * and fail the call with an error when appropriate
6292 /* This field returns the type of original request. */
6294 /* This field provides original sequence number of the command. */
6297 * This field is the length of the response in bytes. The last byte of
6298 * the response is a valid flag that will read as '1' when the command
6299 * has been completely written to memory.
6303 * FID value. This value is used to identify operations on the PCI bus
6304 * as belonging to a particular PCI function.
6308 * Port ID of port that this function is associated with. Valid only for
6309 * the PF. 0xFF... (All Fs) if this function is not associated with any
6310 * port. 0xFF... (All Fs) if this function is called from a VF.
6313 /* If 1, then Push mode is supported on this function. */
6314 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED UINT32_C(0x1)
6315 /* If 1, then the global MSI-X auto-masking is enabled for the device. */
6316 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING UINT32_C(0x2)
6318 * If 1, then the Precision Time Protocol (PTP) processing is supported
6319 * on this function. The HWRM should enable PTP on only a single
6320 * Physical Function (PF) per port.
6322 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED UINT32_C(0x4)
6324 * If 1, then RDMA over Converged Ethernet (RoCE) v1 is supported on
6327 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED UINT32_C(0x8)
6329 * If 1, then RDMA over Converged Ethernet (RoCE) v2 is supported on
6332 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED UINT32_C(0x10)
6334 * If 1, then control and configuration of WoL magic packet are
6335 * supported on this function.
6337 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED UINT32_C(0x20)
6339 * If 1, then control and configuration of bitmap pattern packet are
6340 * supported on this function.
6342 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED UINT32_C(0x40)
6344 * If set to 1, then the control and configuration of rate limit of an
6345 * allocated TX ring on the queried function is supported.
6347 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED UINT32_C(0x80)
6349 * If 1, then control and configuration of minimum and maximum
6350 * bandwidths are supported on the queried function.
6352 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED UINT32_C(0x100)
6354 * If the query is for a VF, then this flag shall be ignored. If this
6355 * query is for a PF and this flag is set to 1, then the PF has the
6356 * capability to set the rate limits on the TX rings of its children
6357 * VFs. If this query is for a PF and this flag is set to 0, then the PF
6358 * does not have the capability to set the rate limits on the TX rings
6359 * of its children VFs.
6361 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED UINT32_C(0x200)
6363 * If the query is for a VF, then this flag shall be ignored. If this
6364 * query is for a PF and this flag is set to 1, then the PF has the
6365 * capability to set the minimum and/or maximum bandwidths for its
6366 * children VFs. If this query is for a PF and this flag is set to 0,
6367 * then the PF does not have the capability to set the minimum or
6368 * maximum bandwidths for its children VFs.
6370 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED UINT32_C(0x400)
6372 * Standard TX Ring mode is used for the allocation of TX ring and
6373 * underlying scheduling resources that allow bandwidth reservation and
6374 * limit settings on the queried function. If set to 1, then standard TX
6375 * ring mode is supported on the queried function. If set to 0, then
6376 * standard TX ring mode is not available on the queried function.
6378 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED UINT32_C(0x800)
6379 uint8_t mac_address[6];
6381 * This value is current MAC address configured for this function. A
6382 * value of 00-00-00-00-00-00 indicates no MAC address is currently
6385 uint16_t max_rsscos_ctx;
6387 * The maximum number of RSS/COS contexts that can be allocated to the
6390 uint16_t max_cmpl_rings;
6392 * The maximum number of completion rings that can be allocated to the
6395 uint16_t max_tx_rings;
6397 * The maximum number of transmit rings that can be allocated to the
6400 uint16_t max_rx_rings;
6402 * The maximum number of receive rings that can be allocated to the
6405 uint16_t max_l2_ctxs;
6407 * The maximum number of L2 contexts that can be allocated to the
6411 /* The maximum number of VNICs that can be allocated to the function. */
6412 uint16_t first_vf_id;
6414 * The identifier for the first VF enabled on a PF. This is valid only
6415 * on the PF with SR-IOV enabled. 0xFF... (All Fs) if this command is
6416 * called on a PF with SR-IOV disabled or on a VF.
6420 * The maximum number of VFs that can be allocated to the function. This
6421 * is valid only on the PF with SR-IOV enabled. 0xFF... (All Fs) if this
6422 * command is called on a PF with SR-IOV disabled or on a VF.
6424 uint16_t max_stat_ctx;
6426 * The maximum number of statistic contexts that can be allocated to the
6429 uint32_t max_encap_records;
6431 * The maximum number of Encapsulation records that can be offloaded by
6434 uint32_t max_decap_records;
6436 * The maximum number of decapsulation records that can be offloaded by
6439 uint32_t max_tx_em_flows;
6441 * The maximum number of Exact Match (EM) flows that can be offloaded by
6442 * this function on the TX side.
6444 uint32_t max_tx_wm_flows;
6446 * The maximum number of Wildcard Match (WM) flows that can be offloaded
6447 * by this function on the TX side.
6449 uint32_t max_rx_em_flows;
6451 * The maximum number of Exact Match (EM) flows that can be offloaded by
6452 * this function on the RX side.
6454 uint32_t max_rx_wm_flows;
6456 * The maximum number of Wildcard Match (WM) flows that can be offloaded
6457 * by this function on the RX side.
6459 uint32_t max_mcast_filters;
6461 * The maximum number of multicast filters that can be supported by this
6462 * function on the RX side.
6464 uint32_t max_flow_id;
6466 * The maximum value of flow_id that can be supported in completion
6469 uint32_t max_hw_ring_grps;
6471 * The maximum number of HW ring groups that can be supported on this
6474 uint16_t max_sp_tx_rings;
6476 * The maximum number of strict priority transmit rings that can be
6477 * allocated to the function. This number indicates the maximum number
6478 * of TX rings that can be assigned strict priorities out of the maximum
6479 * number of TX rings that can be allocated (max_tx_rings) to the
6485 * This field is used in Output records to indicate that the output is
6486 * completely written to RAM. This field should be read as '1' to
6487 * indicate that the output has been completely written. When writing a
6488 * command completion or response to an internal processor, the order of
6489 * writes has to be such that this field is written last.
6491 } __attribute__((packed));
6493 /* hwrm_func_qcfg */
6495 * Description: This command returns the current configuration of a function.
6496 * The input FID value is used to indicate what function is being queried. This
6497 * allows a physical function driver to query virtual functions that are
6498 * children of the physical function. The output FID value is needed to
6499 * configure Rings and MSI-X vectors so their DMA operations appear correctly on
6500 * the PCI bus. This command should be called by every driver after
6501 * 'hwrm_func_cfg' to get the actual number of resources allocated by the HWRM.
6502 * The values returned by hwrm_func_qcfg are the values the driver shall use.
6503 * These values may be different than what was originally requested in the
6504 * 'hwrm_func_cfg' command.
6506 /* Input (24 bytes) */
6508 struct hwrm_func_qcfg_input {
6511 * This value indicates what type of request this is. The format for the
6512 * rest of the command is determined by this field.
6516 * This value indicates the what completion ring the request will be
6517 * optionally completed on. If the value is -1, then no CR completion
6518 * will be generated. Any other value must be a valid CR ring_id value
6519 * for this function.
6522 /* This value indicates the command sequence number. */
6525 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
6526 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
6530 * This is the host address where the response will be written when the
6531 * request is complete. This area must be 16B aligned and must be
6532 * cleared to zero before the request is made.
6536 * Function ID of the function that is being queried. 0xFF... (All Fs)
6537 * if the query is for the requesting function.
6539 uint16_t unused_0[3];
6540 } __attribute__((packed));
6542 /* Output (72 bytes) */
6544 struct hwrm_func_qcfg_output {
6545 uint16_t error_code;
6547 * Pass/Fail or error type Note: receiver to verify the in parameters,
6548 * and fail the call with an error when appropriate
6551 /* This field returns the type of original request. */
6553 /* This field provides original sequence number of the command. */
6556 * This field is the length of the response in bytes. The last byte of
6557 * the response is a valid flag that will read as '1' when the command
6558 * has been completely written to memory.
6562 * FID value. This value is used to identify operations on the PCI bus
6563 * as belonging to a particular PCI function.
6567 * Port ID of port that this function is associated with. 0xFF... (All
6568 * Fs) if this function is not associated with any port.
6572 * This value is the current VLAN setting for this function. The value
6573 * of 0 for this field indicates no priority tagging or VLAN is used.
6574 * This field's format is same as 802.1Q Tag's Tag Control Information
6575 * (TCI) format that includes both Priority Code Point (PCP) and VLAN
6580 * If 1, then magic packet based Out-Of-Box WoL is enabled on the port
6581 * associated with this function.
6583 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED UINT32_C(0x1)
6585 * If 1, then bitmap pattern based Out-Of-Box WoL packet is enabled on
6586 * the port associated with this function.
6588 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED UINT32_C(0x2)
6590 * If set to 1, then FW based DCBX agent is enabled and running on the
6591 * port associated with this function. If set to 0, then DCBX agent is
6592 * not running in the firmware.
6594 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED UINT32_C(0x4)
6596 * Standard TX Ring mode is used for the allocation of TX ring and
6597 * underlying scheduling resources that allow bandwidth reservation and
6598 * limit settings on the queried function. If set to 1, then standard TX
6599 * ring mode is enabled on the queried function. If set to 0, then the
6600 * standard TX ring mode is disabled on the queried function. In this
6601 * extended TX ring resource mode, the minimum and maximum bandwidth
6602 * settings are not supported to allow the allocation of TX rings to
6603 * span multiple scheduler nodes.
6605 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED UINT32_C(0x8)
6607 * If set to 1 then FW based LLDP agent is enabled and running on the
6608 * port associated with this function. If set to 0 then the LLDP agent
6609 * is not running in the firmware.
6611 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED UINT32_C(0x10)
6613 * If set to 1, then multi-host mode is active for this function. If set
6614 * to 0, then multi-host mode is inactive for this function or not
6615 * applicable for this device.
6617 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST UINT32_C(0x20)
6618 uint8_t mac_address[6];
6620 * This value is current MAC address configured for this function. A
6621 * value of 00-00-00-00-00-00 indicates no MAC address is currently
6626 * This value is current PCI ID of this function. If ARI is enabled,
6627 * then it is Bus Number (8b):Function Number(8b). Otherwise, it is Bus
6628 * Number (8b):Device Number (4b):Function Number(4b). If multi-host
6629 * mode is active, the 4 lsb will indicate the PF index for this
6632 uint16_t alloc_rsscos_ctx;
6633 /* The number of RSS/COS contexts currently allocated to the function. */
6634 uint16_t alloc_cmpl_rings;
6636 * The number of completion rings currently allocated to the function.
6637 * This does not include the rings allocated to any children functions
6640 uint16_t alloc_tx_rings;
6642 * The number of transmit rings currently allocated to the function.
6643 * This does not include the rings allocated to any children functions
6646 uint16_t alloc_rx_rings;
6648 * The number of receive rings currently allocated to the function. This
6649 * does not include the rings allocated to any children functions if
6652 uint16_t alloc_l2_ctx;
6653 /* The allocated number of L2 contexts to the function. */
6654 uint16_t alloc_vnics;
6655 /* The allocated number of vnics to the function. */
6658 * The maximum transmission unit of the function. For rings allocated on
6659 * this function, this default value is used if ring MTU is not
6664 * The maximum receive unit of the function. For vnics allocated on this
6665 * function, this default value is used if vnic MRU is not specified.
6667 uint16_t stat_ctx_id;
6668 /* The statistics context assigned to a function. */
6669 uint8_t port_partition_type;
6671 * The HWRM shall return Unknown value for this field when this command
6672 * is used to query VF's configuration.
6674 /* Single physical function */
6675 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
6676 /* Multiple physical functions */
6677 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
6678 /* Network Partitioning 1.0 */
6679 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
6680 /* Network Partitioning 1.5 */
6681 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
6682 /* Network Partitioning 2.0 */
6683 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
6685 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN UINT32_C(0xff)
6686 uint8_t port_pf_cnt;
6688 * This field will indicate number of physical functions on this
6689 * port_partition. HWRM shall return unavail (i.e. value of 0) for this
6690 * field when this command is used to query VF's configuration or from
6691 * older firmware that doesn't support this field.
6693 /* number of PFs is not available */
6694 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
6695 uint16_t dflt_vnic_id;
6696 /* The default VNIC ID assigned to a function that is being queried. */
6701 * Minimum BW allocated for this function. The HWRM will translate this
6702 * value into byte counter and time interval used for the scheduler
6703 * inside the device. A value of 0 indicates the minimum bandwidth is
6706 /* The bandwidth value. */
6707 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
6708 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
6709 /* The granularity of the value (bits or bytes). */
6710 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE UINT32_C(0x10000000)
6711 /* Value is in bits. */
6712 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
6713 /* Value is in bytes. */
6714 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
6715 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_LAST HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES
6716 /* bw_value_unit is 3 b */
6717 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
6718 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
6719 /* Value is in Mb or MB (base 10). */
6720 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
6721 /* Value is in Kb or KB (base 10). */
6722 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
6723 /* Value is in bits or bytes. */
6724 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
6725 /* Value is in Gb or GB (base 10). */
6726 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
6727 /* Value is in 1/100th of a percentage of total bandwidth. */
6728 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
6730 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
6731 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_LAST HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID
6734 * Maximum BW allocated for this function. The HWRM will translate this
6735 * value into byte counter and time interval used for the scheduler
6736 * inside the device. A value of 0 indicates that the maximum bandwidth
6737 * is not configured.
6739 /* The bandwidth value. */
6740 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
6741 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
6742 /* The granularity of the value (bits or bytes). */
6743 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE UINT32_C(0x10000000)
6744 /* Value is in bits. */
6745 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
6746 /* Value is in bytes. */
6747 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
6748 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_LAST HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES
6749 /* bw_value_unit is 3 b */
6750 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
6751 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
6752 /* Value is in Mb or MB (base 10). */
6753 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
6754 /* Value is in Kb or KB (base 10). */
6755 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
6756 /* Value is in bits or bytes. */
6757 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
6758 /* Value is in Gb or GB (base 10). */
6759 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
6760 /* Value is in 1/100th of a percentage of total bandwidth. */
6761 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
6763 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
6764 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_LAST HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID
6767 * This value indicates the Edge virtual bridge mode for the domain that
6768 * this function belongs to.
6770 /* No Edge Virtual Bridging (EVB) */
6771 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
6772 /* Virtual Ethernet Bridge (VEB) */
6773 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
6774 /* Virtual Ethernet Port Aggregator (VEPA) */
6775 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
6779 * The number of VFs that are allocated to the function. This is valid
6780 * only on the PF with SR-IOV enabled. 0xFF... (All Fs) if this command
6781 * is called on a PF with SR-IOV disabled or on a VF.
6783 uint32_t alloc_mcast_filters;
6785 * The number of allocated multicast filters for this function on the RX
6788 uint32_t alloc_hw_ring_grps;
6789 /* The number of allocated HW ring groups for this function. */
6790 uint16_t alloc_sp_tx_rings;
6792 * The number of strict priority transmit rings out of currently
6793 * allocated TX rings to the function (alloc_tx_rings).
6798 * This field is used in Output records to indicate that the output is
6799 * completely written to RAM. This field should be read as '1' to
6800 * indicate that the output has been completely written. When writing a
6801 * command completion or response to an internal processor, the order of
6802 * writes has to be such that this field is written last.
6804 } __attribute__((packed));
6806 /* hwrm_func_vlan_qcfg */
6808 * Description: This command should be called by PF driver to get the current
6809 * C-TAG, S-TAG and correcponsing PCP and TPID values configured for the
6812 /* Input (24 bytes) */
6814 struct hwrm_func_vlan_qcfg_input {
6817 * This value indicates what type of request this is. The format for the
6818 * rest of the command is determined by this field.
6822 * This value indicates the what completion ring the request will be
6823 * optionally completed on. If the value is -1, then no CR completion
6824 * will be generated. Any other value must be a valid CR ring_id value
6825 * for this function.
6828 /* This value indicates the command sequence number. */
6831 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
6832 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
6836 * This is the host address where the response will be written when the
6837 * request is complete. This area must be 16B aligned and must be
6838 * cleared to zero before the request is made.
6842 * Function ID of the function that is being configured. If set to
6843 * 0xFF... (All Fs), then the configuration is for the requesting
6846 uint16_t unused_0[3];
6847 } __attribute__((packed));
6849 /* Output (40 bytes) */
6851 struct hwrm_func_vlan_qcfg_output {
6852 uint16_t error_code;
6854 * Pass/Fail or error type Note: receiver to verify the in parameters,
6855 * and fail the call with an error when appropriate
6858 /* This field returns the type of original request. */
6860 /* This field provides original sequence number of the command. */
6863 * This field is the length of the response in bytes. The last byte of
6864 * the response is a valid flag that will read as '1' when the command
6865 * has been completely written to memory.
6873 * This field is used in Output records to indicate that the output is
6874 * completely written to RAM. This field should be read as '1' to
6875 * indicate that the output has been completely written. When writing a
6876 * command completion or response to an internal processor, the order of
6877 * writes has to be such that this field is written last.
6880 /* S-TAG VLAN identifier configured for the function. */
6882 /* S-TAG PCP value configured for the function. */
6884 uint16_t stag_tpid; /* big endian */
6886 * S-TAG TPID value configured for the function. This field is specified
6887 * in network byte order.
6890 /* C-TAG VLAN identifier configured for the function. */
6892 /* C-TAG PCP value configured for the function. */
6894 uint16_t ctag_tpid; /* big endian */
6896 * C-TAG TPID value configured for the function. This field is specified
6897 * in network byte order.
6904 } __attribute__((packed));
6906 /* hwrm_func_vlan_cfg */
6908 * Description: This command allows PF driver to configure C-TAG, S-TAG and
6909 * corresponding PCP and TPID values for a function.
6911 /* Input (48 bytes) */
6913 struct hwrm_func_vlan_cfg_input {
6916 * This value indicates what type of request this is. The format for the
6917 * rest of the command is determined by this field.
6921 * This value indicates the what completion ring the request will be
6922 * optionally completed on. If the value is -1, then no CR completion
6923 * will be generated. Any other value must be a valid CR ring_id value
6924 * for this function.
6927 /* This value indicates the command sequence number. */
6930 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
6931 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
6935 * This is the host address where the response will be written when the
6936 * request is complete. This area must be 16B aligned and must be
6937 * cleared to zero before the request is made.
6941 * Function ID of the function that is being configured. If set to
6942 * 0xFF... (All Fs), then the configuration is for the requesting
6948 /* This bit must be '1' for the stag_vid field to be configured. */
6949 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
6950 /* This bit must be '1' for the ctag_vid field to be configured. */
6951 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
6952 /* This bit must be '1' for the stag_pcp field to be configured. */
6953 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
6954 /* This bit must be '1' for the ctag_pcp field to be configured. */
6955 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
6956 /* This bit must be '1' for the stag_tpid field to be configured. */
6957 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
6958 /* This bit must be '1' for the ctag_tpid field to be configured. */
6959 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
6961 /* S-TAG VLAN identifier configured for the function. */
6963 /* S-TAG PCP value configured for the function. */
6965 uint16_t stag_tpid; /* big endian */
6967 * S-TAG TPID value configured for the function. This field is specified
6968 * in network byte order.
6971 /* C-TAG VLAN identifier configured for the function. */
6973 /* C-TAG PCP value configured for the function. */
6975 uint16_t ctag_tpid; /* big endian */
6977 * C-TAG TPID value configured for the function. This field is specified
6978 * in network byte order.
6985 } __attribute__((packed));
6987 /* Output (16 bytes) */
6989 struct hwrm_func_vlan_cfg_output {
6990 uint16_t error_code;
6992 * Pass/Fail or error type Note: receiver to verify the in parameters,
6993 * and fail the call with an error when appropriate
6996 /* This field returns the type of original request. */
6998 /* This field provides original sequence number of the command. */
7001 * This field is the length of the response in bytes. The last byte of
7002 * the response is a valid flag that will read as '1' when the command
7003 * has been completely written to memory.
7011 * This field is used in Output records to indicate that the output is
7012 * completely written to RAM. This field should be read as '1' to
7013 * indicate that the output has been completely written. When writing a
7014 * command completion or response to an internal processor, the order of
7015 * writes has to be such that this field is written last.
7017 } __attribute__((packed));
7021 * Description: This command allows configuration of a PF by the corresponding
7022 * PF driver. This command also allows configuration of a child VF by its parent
7023 * PF driver. The input FID value is used to indicate what function is being
7024 * configured. This allows a PF driver to configure the PF owned by itself or a
7025 * virtual function that is a child of the PF. This command allows to reserve
7026 * resources for a VF by its parent PF. To reverse the process, the command
7027 * should be called with all enables flags cleared for resources. This will free
7028 * allocated resources for the VF and return them to the resource pool. If this
7029 * command is requested by a VF driver to configure or reserve resources, then
7030 * the HWRM shall fail this command. If default MAC address and/or VLAN are
7031 * provided in this command, then the HWRM shall set up appropriate MAC/VLAN
7032 * filters for the function that is being configured. If source properties
7033 * checks are enabled and default MAC address and/or IP address are provided in
7034 * this command, then the HWRM shall set appropriate source property checks
7035 * based on provided MAC and/or IP addresses. The parent PF driver should not
7036 * set MTU/MRU for a VF using this command. This is to allow MTU/MRU setting by
7037 * the VF driver. If the MTU or MRU for a VF is set by the PF driver, then the
7038 * HWRM should ignore it. A function's MTU/MRU should be set prior to allocating
7039 * RX VNICs or TX rings. A PF driver calls hwrm_func_cfg to allocate resources
7040 * for itself or its children VFs. All function drivers shall call hwrm_func_cfg
7041 * to reserve resources. A request to hwrm_func_cfg may not be fully granted;
7042 * that is, a request for resources may be larger than what can be supported by
7043 * the device and the HWRM will allocate the best set of resources available,
7044 * but that may be less than requested. If all the amounts requested could not
7045 * be fulfilled, the HWRM shall allocate what it could and return a status code
7046 * of success. A function driver should call hwrm_func_qcfg immediately after
7047 * hwrm_func_cfg to determine what resources were assigned to the configured
7048 * function. A call by a PF driver to hwrm_func_cfg to allocate resources for
7049 * itself shall only allocate resources for the PF driver to use, not for its
7050 * children VFs. Likewise, a call to hwrm_func_qcfg shall return the resources
7051 * available for the PF driver to use, not what is available to its children
7054 /* Input (88 bytes) */
7056 struct hwrm_func_cfg_input {
7059 * This value indicates what type of request this is. The format for the
7060 * rest of the command is determined by this field.
7064 * This value indicates the what completion ring the request will be
7065 * optionally completed on. If the value is -1, then no CR completion
7066 * will be generated. Any other value must be a valid CR ring_id value
7067 * for this function.
7070 /* This value indicates the command sequence number. */
7073 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
7074 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
7078 * This is the host address where the response will be written when the
7079 * request is complete. This area must be 16B aligned and must be
7080 * cleared to zero before the request is made.
7084 * Function ID of the function that is being configured. If set to
7085 * 0xFF... (All Fs), then the the configuration is for the requesting
7092 * When this bit is '1', the function is disabled with source MAC
7093 * address check. This is an anti-spoofing check. If this flag is set,
7094 * then the function shall be configured to disallow transmission of
7095 * frames with the source MAC address that is configured for this
7098 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE UINT32_C(0x1)
7100 * When this bit is '1', the function is enabled with source MAC address
7101 * check. This is an anti-spoofing check. If this flag is set, then the
7102 * function shall be configured to allow transmission of frames with the
7103 * source MAC address that is configured for this function.
7105 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE UINT32_C(0x2)
7107 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK UINT32_C(0x1fc)
7108 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_SFT 2
7110 * Standard TX Ring mode is used for the allocation of TX ring and
7111 * underlying scheduling resources that allow bandwidth reservation and
7112 * limit settings on the queried function. If set to 1, then standard TX
7113 * ring mode is requested to be enabled on the function being
7116 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE UINT32_C(0x200)
7118 * Standard TX Ring mode is used for the allocation of TX ring and
7119 * underlying scheduling resources that allow bandwidth reservation and
7120 * limit settings on the queried function. If set to 1, then the
7121 * standard TX ring mode is requested to be disabled on the function
7122 * being configured. In this extended TX ring resource mode, the minimum
7123 * and maximum bandwidth settings are not supported to allow the
7124 * allocation of TX rings to span multiple scheduler nodes.
7126 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE UINT32_C(0x400)
7128 * If this bit is set, virtual mac address configured in this command
7129 * will be persistent over warm boot.
7131 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST UINT32_C(0x800)
7133 * This bit only applies to the VF. If this bit is set, the statistic
7134 * context counters will not be cleared when the statistic context is
7135 * freed or a function reset is called on VF. This bit will be cleared
7136 * when the PF is unloaded or a function reset is called on the PF.
7138 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC UINT32_C(0x1000)
7140 * This bit requests that the firmware test to see if all the assets
7141 * requested in this command (i.e. number of TX rings) are available.
7142 * The firmware will return an error if the requested assets are not
7143 * available. The firwmare will NOT reserve the assets if they are
7146 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST UINT32_C(0x2000)
7148 /* This bit must be '1' for the mtu field to be configured. */
7149 #define HWRM_FUNC_CFG_INPUT_ENABLES_MTU UINT32_C(0x1)
7150 /* This bit must be '1' for the mru field to be configured. */
7151 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU UINT32_C(0x2)
7152 /* This bit must be '1' for the num_rsscos_ctxs field to be configured. */
7153 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS UINT32_C(0x4)
7154 /* This bit must be '1' for the num_cmpl_rings field to be configured. */
7155 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS UINT32_C(0x8)
7156 /* This bit must be '1' for the num_tx_rings field to be configured. */
7157 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS UINT32_C(0x10)
7158 /* This bit must be '1' for the num_rx_rings field to be configured. */
7159 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS UINT32_C(0x20)
7160 /* This bit must be '1' for the num_l2_ctxs field to be configured. */
7161 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS UINT32_C(0x40)
7162 /* This bit must be '1' for the num_vnics field to be configured. */
7163 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS UINT32_C(0x80)
7164 /* This bit must be '1' for the num_stat_ctxs field to be configured. */
7165 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS UINT32_C(0x100)
7166 /* This bit must be '1' for the dflt_mac_addr field to be configured. */
7167 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR UINT32_C(0x200)
7168 /* This bit must be '1' for the dflt_vlan field to be configured. */
7169 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN UINT32_C(0x400)
7170 /* This bit must be '1' for the dflt_ip_addr field to be configured. */
7171 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR UINT32_C(0x800)
7172 /* This bit must be '1' for the min_bw field to be configured. */
7173 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW UINT32_C(0x1000)
7174 /* This bit must be '1' for the max_bw field to be configured. */
7175 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW UINT32_C(0x2000)
7176 /* This bit must be '1' for the async_event_cr field to be configured. */
7177 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR UINT32_C(0x4000)
7179 * This bit must be '1' for the vlan_antispoof_mode field to be
7182 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE UINT32_C(0x8000)
7184 * This bit must be '1' for the allowed_vlan_pris field to be
7187 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS UINT32_C(0x10000)
7188 /* This bit must be '1' for the evb_mode field to be configured. */
7189 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE UINT32_C(0x20000)
7191 * This bit must be '1' for the num_mcast_filters field to be
7194 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS UINT32_C(0x40000)
7195 /* This bit must be '1' for the num_hw_ring_grps field to be configured. */
7196 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS UINT32_C(0x80000)
7199 * The maximum transmission unit of the function. The HWRM should make
7200 * sure that the mtu of the function does not exceed the mtu of the
7201 * physical port that this function is associated with. In addition to
7202 * configuring mtu per function, it is possible to configure mtu per
7203 * transmit ring. By default, the mtu of each transmit ring associated
7204 * with a function is equal to the mtu of the function. The HWRM should
7205 * make sure that the mtu of each transmit ring that is assigned to a
7206 * function has a valid mtu.
7210 * The maximum receive unit of the function. The HWRM should make sure
7211 * that the mru of the function does not exceed the mru of the physical
7212 * port that this function is associated with. In addition to
7213 * configuring mru per function, it is possible to configure mru per
7214 * vnic. By default, the mru of each vnic associated with a function is
7215 * equal to the mru of the function. The HWRM should make sure that the
7216 * mru of each vnic that is assigned to a function has a valid mru.
7218 uint16_t num_rsscos_ctxs;
7219 /* The number of RSS/COS contexts requested for the function. */
7220 uint16_t num_cmpl_rings;
7222 * The number of completion rings requested for the function. This does
7223 * not include the rings allocated to any children functions if any.
7225 uint16_t num_tx_rings;
7227 * The number of transmit rings requested for the function. This does
7228 * not include the rings allocated to any children functions if any.
7230 uint16_t num_rx_rings;
7232 * The number of receive rings requested for the function. This does not
7233 * include the rings allocated to any children functions if any.
7235 uint16_t num_l2_ctxs;
7236 /* The requested number of L2 contexts for the function. */
7238 /* The requested number of vnics for the function. */
7239 uint16_t num_stat_ctxs;
7240 /* The requested number of statistic contexts for the function. */
7241 uint16_t num_hw_ring_grps;
7243 * The number of HW ring groups that should be reserved for this
7246 uint8_t dflt_mac_addr[6];
7247 /* The default MAC address for the function being configured. */
7250 * The default VLAN for the function being configured. This field's
7251 * format is same as 802.1Q Tag's Tag Control Information (TCI) format
7252 * that includes both Priority Code Point (PCP) and VLAN Identifier
7255 uint32_t dflt_ip_addr[4]; /* big endian */
7257 * The default IP address for the function being configured. This
7258 * address is only used in enabling source property check.
7262 * Minimum BW allocated for this function. The HWRM will translate this
7263 * value into byte counter and time interval used for the scheduler
7264 * inside the device.
7266 /* The bandwidth value. */
7267 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
7268 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
7269 /* The granularity of the value (bits or bytes). */
7270 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE UINT32_C(0x10000000)
7271 /* Value is in bits. */
7272 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
7273 /* Value is in bytes. */
7274 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
7275 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_LAST HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES
7276 /* bw_value_unit is 3 b */
7277 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
7278 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_SFT 29
7279 /* Value is in Mb or MB (base 10). */
7280 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
7281 /* Value is in Kb or KB (base 10). */
7282 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
7283 /* Value is in bits or bytes. */
7284 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
7285 /* Value is in Gb or GB (base 10). */
7286 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
7287 /* Value is in 1/100th of a percentage of total bandwidth. */
7288 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
7290 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
7291 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_LAST HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID
7294 * Maximum BW allocated for this function. The HWRM will translate this
7295 * value into byte counter and time interval used for the scheduler
7296 * inside the device.
7298 /* The bandwidth value. */
7299 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
7300 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
7301 /* The granularity of the value (bits or bytes). */
7302 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE UINT32_C(0x10000000)
7303 /* Value is in bits. */
7304 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
7305 /* Value is in bytes. */
7306 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
7307 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_LAST HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES
7308 /* bw_value_unit is 3 b */
7309 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
7310 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
7311 /* Value is in Mb or MB (base 10). */
7312 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
7313 /* Value is in Kb or KB (base 10). */
7314 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
7315 /* Value is in bits or bytes. */
7316 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
7317 /* Value is in Gb or GB (base 10). */
7318 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
7319 /* Value is in 1/100th of a percentage of total bandwidth. */
7320 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
7322 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
7323 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_LAST HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
7324 uint16_t async_event_cr;
7326 * ID of the target completion ring for receiving asynchronous event
7327 * completions. If this field is not valid, then the HWRM shall use the
7328 * default completion ring of the function that is being configured as
7329 * the target completion ring for providing any asynchronous event
7330 * completions for that function. If this field is valid, then the HWRM
7331 * shall use the completion ring identified by this ID as the target
7332 * completion ring for providing any asynchronous event completions for
7333 * the function that is being configured.
7335 uint8_t vlan_antispoof_mode;
7336 /* VLAN Anti-spoofing mode. */
7337 /* No VLAN anti-spoofing checks are enabled */
7338 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK UINT32_C(0x0)
7339 /* Validate VLAN against the configured VLAN(s) */
7340 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN UINT32_C(0x1)
7341 /* Insert VLAN if it does not exist, otherwise discard */
7342 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE UINT32_C(0x2)
7343 /* Insert VLAN if it does not exist, override VLAN if it exists */
7344 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN UINT32_C(0x3)
7345 uint8_t allowed_vlan_pris;
7347 * This bit field defines VLAN PRIs that are allowed on this function.
7348 * If nth bit is set, then VLAN PRI n is allowed on this function.
7352 * The HWRM shall allow a PF driver to change EVB mode for the partition
7353 * it belongs to. The HWRM shall not allow a VF driver to change the EVB
7354 * mode. The HWRM shall take into account the switching of EVB mode from
7355 * one to another and reconfigure hardware resources as appropriately.
7356 * The switching from VEB to VEPA mode requires the disabling of the
7357 * loopback traffic. Additionally, source knock outs are handled
7358 * differently in VEB and VEPA modes.
7360 /* No Edge Virtual Bridging (EVB) */
7361 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
7362 /* Virtual Ethernet Bridge (VEB) */
7363 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
7364 /* Virtual Ethernet Port Aggregator (VEPA) */
7365 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
7367 uint16_t num_mcast_filters;
7369 * The number of multicast filters that should be reserved for this
7370 * function on the RX side.
7372 } __attribute__((packed));
7374 /* Output (16 bytes) */
7376 struct hwrm_func_cfg_output {
7377 uint16_t error_code;
7379 * Pass/Fail or error type Note: receiver to verify the in parameters,
7380 * and fail the call with an error when appropriate
7383 /* This field returns the type of original request. */
7385 /* This field provides original sequence number of the command. */
7388 * This field is the length of the response in bytes. The last byte of
7389 * the response is a valid flag that will read as '1' when the command
7390 * has been completely written to memory.
7398 * This field is used in Output records to indicate that the output is
7399 * completely written to RAM. This field should be read as '1' to
7400 * indicate that the output has been completely written. When writing a
7401 * command completion or response to an internal processor, the order of
7402 * writes has to be such that this field is written last.
7404 } __attribute__((packed));
7406 /* hwrm_func_qstats */
7408 * Description: This command returns statistics of a function. The input FID
7409 * value is used to indicate what function is being queried. This allows a
7410 * physical function driver to query virtual functions that are children of the
7411 * physical function. The HWRM shall return any unsupported counter with a value
7412 * of 0xFFFFFFFF for 32-bit counters and 0xFFFFFFFFFFFFFFFF for 64-bit counters.
7414 /* Input (24 bytes) */
7416 struct hwrm_func_qstats_input {
7419 * This value indicates what type of request this is. The format for the
7420 * rest of the command is determined by this field.
7424 * This value indicates the what completion ring the request will be
7425 * optionally completed on. If the value is -1, then no CR completion
7426 * will be generated. Any other value must be a valid CR ring_id value
7427 * for this function.
7430 /* This value indicates the command sequence number. */
7433 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
7434 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
7438 * This is the host address where the response will be written when the
7439 * request is complete. This area must be 16B aligned and must be
7440 * cleared to zero before the request is made.
7444 * Function ID of the function that is being queried. 0xFF... (All Fs)
7445 * if the query is for the requesting function.
7447 uint16_t unused_0[3];
7448 } __attribute__((packed));
7450 /* Output (176 bytes) */
7452 struct hwrm_func_qstats_output {
7453 uint16_t error_code;
7455 * Pass/Fail or error type Note: receiver to verify the in parameters,
7456 * and fail the call with an error when appropriate
7459 /* This field returns the type of original request. */
7461 /* This field provides original sequence number of the command. */
7464 * This field is the length of the response in bytes. The last byte of
7465 * the response is a valid flag that will read as '1' when the command
7466 * has been completely written to memory.
7468 uint64_t tx_ucast_pkts;
7469 /* Number of transmitted unicast packets on the function. */
7470 uint64_t tx_mcast_pkts;
7471 /* Number of transmitted multicast packets on the function. */
7472 uint64_t tx_bcast_pkts;
7473 /* Number of transmitted broadcast packets on the function. */
7474 uint64_t tx_discard_pkts;
7476 * Number of transmitted packets that were discarded due to internal NIC
7477 * resource problems. For transmit, this can only happen if TMP is
7478 * configured to allow dropping in HOL blocking conditions, which is not
7479 * a normal configuration.
7481 uint64_t tx_drop_pkts;
7483 * Number of dropped packets on transmit path on the function. These are
7484 * packets that have been marked for drop by the TE CFA block or are
7485 * packets that exceeded the transmit MTU limit for the function.
7487 uint64_t tx_ucast_bytes;
7488 /* Number of transmitted bytes for unicast traffic on the function. */
7489 uint64_t tx_mcast_bytes;
7490 /* Number of transmitted bytes for multicast traffic on the function. */
7491 uint64_t tx_bcast_bytes;
7492 /* Number of transmitted bytes for broadcast traffic on the function. */
7493 uint64_t rx_ucast_pkts;
7494 /* Number of received unicast packets on the function. */
7495 uint64_t rx_mcast_pkts;
7496 /* Number of received multicast packets on the function. */
7497 uint64_t rx_bcast_pkts;
7498 /* Number of received broadcast packets on the function. */
7499 uint64_t rx_discard_pkts;
7501 * Number of received packets that were discarded on the function due to
7502 * resource limitations. This can happen for 3 reasons. # The BD used
7503 * for the packet has a bad format. # There were no BDs available in the
7504 * ring for the packet. # There were no BDs available on-chip for the
7507 uint64_t rx_drop_pkts;
7509 * Number of dropped packets on received path on the function. These are
7510 * packets that have been marked for drop by the RE CFA.
7512 uint64_t rx_ucast_bytes;
7513 /* Number of received bytes for unicast traffic on the function. */
7514 uint64_t rx_mcast_bytes;
7515 /* Number of received bytes for multicast traffic on the function. */
7516 uint64_t rx_bcast_bytes;
7517 /* Number of received bytes for broadcast traffic on the function. */
7518 uint64_t rx_agg_pkts;
7519 /* Number of aggregated unicast packets on the function. */
7520 uint64_t rx_agg_bytes;
7521 /* Number of aggregated unicast bytes on the function. */
7522 uint64_t rx_agg_events;
7523 /* Number of aggregation events on the function. */
7524 uint64_t rx_agg_aborts;
7525 /* Number of aborted aggregations on the function. */
7532 * This field is used in Output records to indicate that the output is
7533 * completely written to RAM. This field should be read as '1' to
7534 * indicate that the output has been completely written. When writing a
7535 * command completion or response to an internal processor, the order of
7536 * writes has to be such that this field is written last.
7538 } __attribute__((packed));
7540 /* hwrm_func_clr_stats */
7542 * Description: This command clears statistics of a function. The input FID
7543 * value is used to indicate what function's statistics is being cleared. This
7544 * allows a physical function driver to clear statistics of virtual functions
7545 * that are children of the physical function.
7547 /* Input (24 bytes) */
7549 struct hwrm_func_clr_stats_input {
7552 * This value indicates what type of request this is. The format for the
7553 * rest of the command is determined by this field.
7557 * This value indicates the what completion ring the request will be
7558 * optionally completed on. If the value is -1, then no CR completion
7559 * will be generated. Any other value must be a valid CR ring_id value
7560 * for this function.
7563 /* This value indicates the command sequence number. */
7566 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
7567 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
7571 * This is the host address where the response will be written when the
7572 * request is complete. This area must be 16B aligned and must be
7573 * cleared to zero before the request is made.
7577 * Function ID of the function. 0xFF... (All Fs) if the query is for the
7578 * requesting function.
7580 uint16_t unused_0[3];
7581 } __attribute__((packed));
7583 /* Output (16 bytes) */
7585 struct hwrm_func_clr_stats_output {
7586 uint16_t error_code;
7588 * Pass/Fail or error type Note: receiver to verify the in parameters,
7589 * and fail the call with an error when appropriate
7592 /* This field returns the type of original request. */
7594 /* This field provides original sequence number of the command. */
7597 * This field is the length of the response in bytes. The last byte of
7598 * the response is a valid flag that will read as '1' when the command
7599 * has been completely written to memory.
7607 * This field is used in Output records to indicate that the output is
7608 * completely written to RAM. This field should be read as '1' to
7609 * indicate that the output has been completely written. When writing a
7610 * command completion or response to an internal processor, the order of
7611 * writes has to be such that this field is written last.
7613 } __attribute__((packed));
7615 /* hwrm_func_vf_resc_free */
7616 /* Description: This command frees resources of a vf. */
7617 /* Input (24 bytes) */
7619 struct hwrm_func_vf_resc_free_input {
7622 * This value indicates what type of request this is. The format for the
7623 * rest of the command is determined by this field.
7627 * This value indicates the what completion ring the request will be
7628 * optionally completed on. If the value is -1, then no CR completion
7629 * will be generated. Any other value must be a valid CR ring_id value
7630 * for this function.
7633 /* This value indicates the command sequence number. */
7636 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
7637 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
7641 * This is the host address where the response will be written when the
7642 * request is complete. This area must be 16B aligned and must be
7643 * cleared to zero before the request is made.
7647 * This value is used to identify a Virtual Function (VF). The scope of
7648 * VF ID is local within a PF.
7650 uint16_t unused_0[3];
7651 } __attribute__((packed));
7653 /* Output (16 bytes) */
7655 struct hwrm_func_vf_resc_free_output {
7656 uint16_t error_code;
7658 * Pass/Fail or error type Note: receiver to verify the in parameters,
7659 * and fail the call with an error when appropriate
7662 /* This field returns the type of original request. */
7664 /* This field provides original sequence number of the command. */
7667 * This field is the length of the response in bytes. The last byte of
7668 * the response is a valid flag that will read as '1' when the command
7669 * has been completely written to memory.
7677 * This field is used in Output records to indicate that the output is
7678 * completely written to RAM. This field should be read as '1' to
7679 * indicate that the output has been completely written. When writing a
7680 * command completion or response to an internal processor, the order of
7681 * writes has to be such that this field is written last.
7683 } __attribute__((packed));
7685 /* hwrm_func_vf_vnic_ids_query */
7686 /* Description: This command is used to query vf vnic ids. */
7687 /* Input (32 bytes) */
7689 struct hwrm_func_vf_vnic_ids_query_input {
7692 * This value indicates what type of request this is. The format for the
7693 * rest of the command is determined by this field.
7697 * This value indicates the what completion ring the request will be
7698 * optionally completed on. If the value is -1, then no CR completion
7699 * will be generated. Any other value must be a valid CR ring_id value
7700 * for this function.
7703 /* This value indicates the command sequence number. */
7706 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
7707 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
7711 * This is the host address where the response will be written when the
7712 * request is complete. This area must be 16B aligned and must be
7713 * cleared to zero before the request is made.
7717 * This value is used to identify a Virtual Function (VF). The scope of
7718 * VF ID is local within a PF.
7722 uint32_t max_vnic_id_cnt;
7723 /* Max number of vnic ids in vnic id table */
7724 uint64_t vnic_id_tbl_addr;
7725 /* This is the address for VF VNIC ID table */
7726 } __attribute__((packed));
7728 /* Output (16 bytes) */
7730 struct hwrm_func_vf_vnic_ids_query_output {
7731 uint16_t error_code;
7733 * Pass/Fail or error type Note: receiver to verify the in parameters,
7734 * and fail the call with an error when appropriate
7737 /* This field returns the type of original request. */
7739 /* This field provides original sequence number of the command. */
7742 * This field is the length of the response in bytes. The last byte of
7743 * the response is a valid flag that will read as '1' when the command
7744 * has been completely written to memory.
7746 uint32_t vnic_id_cnt;
7747 /* Actual number of vnic ids Each VNIC ID is written as a 32-bit number. */
7753 * This field is used in Output records to indicate that the output is
7754 * completely written to RAM. This field should be read as '1' to
7755 * indicate that the output has been completely written. When writing a
7756 * command completion or response to an internal processor, the order of
7757 * writes has to be such that this field is written last.
7759 } __attribute__((packed));
7761 /* hwrm_func_drv_rgtr */
7763 * Description: This command is used by the function driver to register its
7764 * information with the HWRM. A function driver shall implement this command. A
7765 * function driver shall use this command during the driver initialization right
7766 * after the HWRM version discovery and default ring resources allocation.
7768 /* Input (80 bytes) */
7770 struct hwrm_func_drv_rgtr_input {
7773 * This value indicates what type of request this is. The format for the
7774 * rest of the command is determined by this field.
7778 * This value indicates the what completion ring the request will be
7779 * optionally completed on. If the value is -1, then no CR completion
7780 * will be generated. Any other value must be a valid CR ring_id value
7781 * for this function.
7784 /* This value indicates the command sequence number. */
7787 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
7788 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
7792 * This is the host address where the response will be written when the
7793 * request is complete. This area must be 16B aligned and must be
7794 * cleared to zero before the request is made.
7798 * When this bit is '1', the function driver is requesting all requests
7799 * from its children VF drivers to be forwarded to itself. This flag can
7800 * only be set by the PF driver. If a VF driver sets this flag, it
7801 * should be ignored by the HWRM.
7803 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE UINT32_C(0x1)
7805 * When this bit is '1', the function is requesting none of the requests
7806 * from its children VF drivers to be forwarded to itself. This flag can
7807 * only be set by the PF driver. If a VF driver sets this flag, it
7808 * should be ignored by the HWRM.
7810 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE UINT32_C(0x2)
7812 /* This bit must be '1' for the os_type field to be configured. */
7813 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE UINT32_C(0x1)
7814 /* This bit must be '1' for the ver field to be configured. */
7815 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER UINT32_C(0x2)
7816 /* This bit must be '1' for the timestamp field to be configured. */
7817 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP UINT32_C(0x4)
7818 /* This bit must be '1' for the vf_req_fwd field to be configured. */
7819 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD UINT32_C(0x8)
7820 /* This bit must be '1' for the async_event_fwd field to be configured. */
7821 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD UINT32_C(0x10)
7824 * This value indicates the type of OS. The values are based on
7825 * CIM_OperatingSystem.mof file as published by the DMTF.
7828 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
7829 /* Other OS not listed below. */
7830 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
7832 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
7834 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
7836 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
7838 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
7840 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
7841 /* VMware ESXi OS. */
7842 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
7843 /* Microsoft Windows 8 64-bit OS. */
7844 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
7845 /* Microsoft Windows Server 2012 R2 OS. */
7846 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
7848 /* This is the major version of the driver. */
7850 /* This is the minor version of the driver. */
7852 /* This is the update version of the driver. */
7857 * This is a 32-bit timestamp provided by the driver for keep alive. The
7858 * timestamp is in multiples of 1ms.
7861 uint32_t vf_req_fwd[8];
7863 * This is a 256-bit bit mask provided by the PF driver for letting the
7864 * HWRM know what commands issued by the VF driver to the HWRM should be
7865 * forwarded to the PF driver. Nth bit refers to the Nth req_type.
7866 * Setting Nth bit to 1 indicates that requests from the VF driver with
7867 * req_type equal to N shall be forwarded to the parent PF driver. This
7868 * field is not valid for the VF driver.
7870 uint32_t async_event_fwd[8];
7872 * This is a 256-bit bit mask provided by the function driver (PF or VF
7873 * driver) to indicate the list of asynchronous event completions to be
7874 * forwarded. Nth bit refers to the Nth event_id. Setting Nth bit to 1
7875 * by the function driver shall result in the HWRM forwarding
7876 * asynchronous event completion with event_id equal to N. If all bits
7877 * are set to 0 (value of 0), then the HWRM shall not forward any
7878 * asynchronous event completion to this function driver.
7880 } __attribute__((packed));
7882 /* Output (16 bytes) */
7884 struct hwrm_func_drv_rgtr_output {
7885 uint16_t error_code;
7887 * Pass/Fail or error type Note: receiver to verify the in parameters,
7888 * and fail the call with an error when appropriate
7891 /* This field returns the type of original request. */
7893 /* This field provides original sequence number of the command. */
7896 * This field is the length of the response in bytes. The last byte of
7897 * the response is a valid flag that will read as '1' when the command
7898 * has been completely written to memory.
7906 * This field is used in Output records to indicate that the output is
7907 * completely written to RAM. This field should be read as '1' to
7908 * indicate that the output has been completely written. When writing a
7909 * command completion or response to an internal processor, the order of
7910 * writes has to be such that this field is written last.
7912 } __attribute__((packed));
7914 /* hwrm_func_drv_unrgtr */
7916 * Description: This command is used by the function driver to un register with
7917 * the HWRM. A function driver shall implement this command. A function driver
7918 * shall use this command during the driver unloading.
7920 /* Input (24 bytes) */
7922 struct hwrm_func_drv_unrgtr_input {
7925 * This value indicates what type of request this is. The format for the
7926 * rest of the command is determined by this field.
7930 * This value indicates the what completion ring the request will be
7931 * optionally completed on. If the value is -1, then no CR completion
7932 * will be generated. Any other value must be a valid CR ring_id value
7933 * for this function.
7936 /* This value indicates the command sequence number. */
7939 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
7940 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
7944 * This is the host address where the response will be written when the
7945 * request is complete. This area must be 16B aligned and must be
7946 * cleared to zero before the request is made.
7950 * When this bit is '1', the function driver is notifying the HWRM to
7951 * prepare for the shutdown.
7953 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN UINT32_C(0x1)
7955 } __attribute__((packed));
7957 /* Output (16 bytes) */
7959 struct hwrm_func_drv_unrgtr_output {
7960 uint16_t error_code;
7962 * Pass/Fail or error type Note: receiver to verify the in parameters,
7963 * and fail the call with an error when appropriate
7966 /* This field returns the type of original request. */
7968 /* This field provides original sequence number of the command. */
7971 * This field is the length of the response in bytes. The last byte of
7972 * the response is a valid flag that will read as '1' when the command
7973 * has been completely written to memory.
7981 * This field is used in Output records to indicate that the output is
7982 * completely written to RAM. This field should be read as '1' to
7983 * indicate that the output has been completely written. When writing a
7984 * command completion or response to an internal processor, the order of
7985 * writes has to be such that this field is written last.
7987 } __attribute__((packed));
7989 /* hwrm_func_buf_rgtr */
7991 * Description: This command is used by the PF driver to register buffers used
7992 * in the PF-VF communication with the HWRM. The PF driver uses this command to
7993 * register buffers for each PF-VF channel. A parent PF may issue this command
7994 * per child VF. If VF ID is not valid, then this command is used to register
7995 * buffers for all children VFs of the PF.
7997 /* Input (128 bytes) */
7999 struct hwrm_func_buf_rgtr_input {
8002 * This value indicates what type of request this is. The format for the
8003 * rest of the command is determined by this field.
8007 * This value indicates the what completion ring the request will be
8008 * optionally completed on. If the value is -1, then no CR completion
8009 * will be generated. Any other value must be a valid CR ring_id value
8010 * for this function.
8013 /* This value indicates the command sequence number. */
8016 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
8017 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
8021 * This is the host address where the response will be written when the
8022 * request is complete. This area must be 16B aligned and must be
8023 * cleared to zero before the request is made.
8026 /* This bit must be '1' for the vf_id field to be configured. */
8027 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
8028 /* This bit must be '1' for the err_buf_addr field to be configured. */
8029 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
8032 * This value is used to identify a Virtual Function (VF). The scope of
8033 * VF ID is local within a PF.
8035 uint16_t req_buf_num_pages;
8036 /* This field represents the number of pages used for request buffer(s). */
8037 uint16_t req_buf_page_size;
8038 /* This field represents the page size used for request buffer(s). */
8040 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
8042 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
8044 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
8046 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
8048 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
8050 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
8052 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
8053 uint16_t req_buf_len;
8054 /* The length of the request buffer per VF in bytes. */
8055 uint16_t resp_buf_len;
8056 /* The length of the response buffer in bytes. */
8059 uint64_t req_buf_page_addr0;
8060 /* This field represents the page address of page #0. */
8061 uint64_t req_buf_page_addr1;
8062 /* This field represents the page address of page #1. */
8063 uint64_t req_buf_page_addr2;
8064 /* This field represents the page address of page #2. */
8065 uint64_t req_buf_page_addr3;
8066 /* This field represents the page address of page #3. */
8067 uint64_t req_buf_page_addr4;
8068 /* This field represents the page address of page #4. */
8069 uint64_t req_buf_page_addr5;
8070 /* This field represents the page address of page #5. */
8071 uint64_t req_buf_page_addr6;
8072 /* This field represents the page address of page #6. */
8073 uint64_t req_buf_page_addr7;
8074 /* This field represents the page address of page #7. */
8075 uint64_t req_buf_page_addr8;
8076 /* This field represents the page address of page #8. */
8077 uint64_t req_buf_page_addr9;
8078 /* This field represents the page address of page #9. */
8079 uint64_t error_buf_addr;
8081 * This field is used to receive the error reporting from the chipset.
8082 * Only applicable for PFs.
8084 uint64_t resp_buf_addr;
8085 /* This field is used to receive the response forwarded by the HWRM. */
8086 } __attribute__((packed));
8088 /* Output (16 bytes) */
8090 struct hwrm_func_buf_rgtr_output {
8091 uint16_t error_code;
8093 * Pass/Fail or error type Note: receiver to verify the in parameters,
8094 * and fail the call with an error when appropriate
8097 /* This field returns the type of original request. */
8099 /* This field provides original sequence number of the command. */
8102 * This field is the length of the response in bytes. The last byte of
8103 * the response is a valid flag that will read as '1' when the command
8104 * has been completely written to memory.
8112 * This field is used in Output records to indicate that the output is
8113 * completely written to RAM. This field should be read as '1' to
8114 * indicate that the output has been completely written. When writing a
8115 * command completion or response to an internal processor, the order of
8116 * writes has to be such that this field is written last.
8118 } __attribute__((packed));
8120 /* hwrm_func_buf_unrgtr */
8122 * Description: This command is used by the PF driver to unregister buffers used
8123 * in the PF-VF communication with the HWRM. The PF driver uses this command to
8124 * unregister buffers for PF-VF communication. A parent PF may issue this
8125 * command to unregister buffers for communication between the PF and a specific
8126 * VF. If the VF ID is not valid, then this command is used to unregister
8127 * buffers used for communications with all children VFs of the PF.
8129 /* Input (24 bytes) */
8131 struct hwrm_func_buf_unrgtr_input {
8134 * This value indicates what type of request this is. The format for the
8135 * rest of the command is determined by this field.
8139 * This value indicates the what completion ring the request will be
8140 * optionally completed on. If the value is -1, then no CR completion
8141 * will be generated. Any other value must be a valid CR ring_id value
8142 * for this function.
8145 /* This value indicates the command sequence number. */
8148 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
8149 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
8153 * This is the host address where the response will be written when the
8154 * request is complete. This area must be 16B aligned and must be
8155 * cleared to zero before the request is made.
8158 /* This bit must be '1' for the vf_id field to be configured. */
8159 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
8162 * This value is used to identify a Virtual Function (VF). The scope of
8163 * VF ID is local within a PF.
8166 } __attribute__((packed));
8168 /* Output (16 bytes) */
8170 struct hwrm_func_buf_unrgtr_output {
8171 uint16_t error_code;
8173 * Pass/Fail or error type Note: receiver to verify the in parameters,
8174 * and fail the call with an error when appropriate
8177 /* This field returns the type of original request. */
8179 /* This field provides original sequence number of the command. */
8182 * This field is the length of the response in bytes. The last byte of
8183 * the response is a valid flag that will read as '1' when the command
8184 * has been completely written to memory.
8192 * This field is used in Output records to indicate that the output is
8193 * completely written to RAM. This field should be read as '1' to
8194 * indicate that the output has been completely written. When writing a
8195 * command completion or response to an internal processor, the order of
8196 * writes has to be such that this field is written last.
8198 } __attribute__((packed));
8200 /* hwrm_func_drv_qver */
8202 * Description: This command is used to query the version of the driver. Any
8203 * driver version with major = 0, minor = 0, and update = 0 shall be considered
8204 * an invalid or unknown version.
8206 /* Input (24 bytes) */
8208 struct hwrm_func_drv_qver_input {
8211 * This value indicates what type of request this is. The format for the
8212 * rest of the command is determined by this field.
8216 * This value indicates the what completion ring the request will be
8217 * optionally completed on. If the value is -1, then no CR completion
8218 * will be generated. Any other value must be a valid CR ring_id value
8219 * for this function.
8222 /* This value indicates the command sequence number. */
8225 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
8226 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
8230 * This is the host address where the response will be written when the
8231 * request is complete. This area must be 16B aligned and must be
8232 * cleared to zero before the request is made.
8235 /* Reserved for future use */
8238 * Function ID of the function that is being queried. 0xFF... (All Fs)
8239 * if the query is for the requesting function.
8242 } __attribute__((packed));
8244 /* Output (16 bytes) */
8246 struct hwrm_func_drv_qver_output {
8247 uint16_t error_code;
8249 * Pass/Fail or error type Note: receiver to verify the in parameters,
8250 * and fail the call with an error when appropriate
8253 /* This field returns the type of original request. */
8255 /* This field provides original sequence number of the command. */
8258 * This field is the length of the response in bytes. The last byte of
8259 * the response is a valid flag that will read as '1' when the command
8260 * has been completely written to memory.
8264 * This value indicates the type of OS. The values are based on
8265 * CIM_OperatingSystem.mof file as published by the DMTF.
8268 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
8269 /* Other OS not listed below. */
8270 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
8272 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
8274 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
8276 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
8278 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
8280 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
8281 /* VMware ESXi OS. */
8282 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
8283 /* Microsoft Windows 8 64-bit OS. */
8284 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
8285 /* Microsoft Windows Server 2012 R2 OS. */
8286 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
8288 /* This is the major version of the driver. */
8290 /* This is the minor version of the driver. */
8292 /* This is the update version of the driver. */
8297 * This field is used in Output records to indicate that the output is
8298 * completely written to RAM. This field should be read as '1' to
8299 * indicate that the output has been completely written. When writing a
8300 * command completion or response to an internal processor, the order of
8301 * writes has to be such that this field is written last.
8303 } __attribute__((packed));
8305 /* hwrm_port_phy_cfg */
8307 * Description: This command configures the PHY device for the port. It allows
8308 * setting of the most generic settings for the PHY. The HWRM shall complete
8309 * this command as soon as PHY settings are configured. They may not be applied
8310 * when the command response is provided. A VF driver shall not be allowed to
8311 * configure PHY using this command. In a network partition mode, a PF driver
8312 * shall not be allowed to configure PHY using this command.
8314 /* Input (56 bytes) */
8316 struct hwrm_port_phy_cfg_input {
8319 * This value indicates what type of request this is. The format for the
8320 * rest of the command is determined by this field.
8324 * This value indicates the what completion ring the request will be
8325 * optionally completed on. If the value is -1, then no CR completion
8326 * will be generated. Any other value must be a valid CR ring_id value
8327 * for this function.
8330 /* This value indicates the command sequence number. */
8333 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
8334 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
8338 * This is the host address where the response will be written when the
8339 * request is complete. This area must be 16B aligned and must be
8340 * cleared to zero before the request is made.
8344 * When this bit is set to '1', the PHY for the port shall be reset. #
8345 * If this bit is set to 1, then the HWRM shall reset the PHY after
8346 * applying PHY configuration changes specified in this command. # In
8347 * order to guarantee that PHY configuration changes specified in this
8348 * command take effect, the HWRM client should set this flag to 1. # If
8349 * this bit is not set to 1, then the HWRM may reset the PHY depending
8350 * on the current PHY configuration and settings specified in this
8353 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY UINT32_C(0x1)
8354 /* deprecated bit. Do not use!!! */
8355 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED UINT32_C(0x2)
8357 * When this bit is set to '1', the link shall be forced to the
8358 * force_link_speed value. When this bit is set to '1', the HWRM client
8359 * should not enable any of the auto negotiation related fields
8360 * represented by auto_XXX fields in this command. When this bit is set
8361 * to '1' and the HWRM client has enabled a auto_XXX field in this
8362 * command, then the HWRM shall ignore the enabled auto_XXX field. When
8363 * this bit is set to zero, the link shall be allowed to autoneg.
8365 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE UINT32_C(0x4)
8367 * When this bit is set to '1', the auto-negotiation process shall be
8368 * restarted on the link.
8370 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG UINT32_C(0x8)
8372 * When this bit is set to '1', Energy Efficient Ethernet (EEE) is
8373 * requested to be enabled on this link. If EEE is not supported on this
8374 * port, then this flag shall be ignored by the HWRM.
8376 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE UINT32_C(0x10)
8378 * When this bit is set to '1', Energy Efficient Ethernet (EEE) is
8379 * requested to be disabled on this link. If EEE is not supported on
8380 * this port, then this flag shall be ignored by the HWRM.
8382 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE UINT32_C(0x20)
8384 * When this bit is set to '1' and EEE is enabled on this link, then TX
8385 * LPI is requested to be enabled on the link. If EEE is not supported
8386 * on this port, then this flag shall be ignored by the HWRM. If EEE is
8387 * disabled on this port, then this flag shall be ignored by the HWRM.
8389 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE UINT32_C(0x40)
8391 * When this bit is set to '1' and EEE is enabled on this link, then TX
8392 * LPI is requested to be disabled on the link. If EEE is not supported
8393 * on this port, then this flag shall be ignored by the HWRM. If EEE is
8394 * disabled on this port, then this flag shall be ignored by the HWRM.
8396 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE UINT32_C(0x80)
8398 * When set to 1, then the HWRM shall enable FEC autonegotitation on
8399 * this port if supported. When set to 0, then this flag shall be
8400 * ignored. If FEC autonegotiation is not supported, then the HWRM shall
8403 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE UINT32_C(0x100)
8405 * When set to 1, then the HWRM shall disable FEC autonegotiation on
8406 * this port if supported. When set to 0, then this flag shall be
8407 * ignored. If FEC autonegotiation is not supported, then the HWRM shall
8410 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE UINT32_C(0x200)
8412 * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)
8413 * on this port if supported. When set to 0, then this flag shall be
8414 * ignored. If FEC CLAUSE 74 is not supported, then the HWRM shall
8417 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE UINT32_C(0x400)
8419 * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)
8420 * on this port if supported. When set to 0, then this flag shall be
8421 * ignored. If FEC CLAUSE 74 is not supported, then the HWRM shall
8424 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE UINT32_C(0x800)
8426 * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed
8427 * Solomon) on this port if supported. When set to 0, then this flag
8428 * shall be ignored. If FEC CLAUSE 91 is not supported, then the HWRM
8429 * shall ignore this flag.
8431 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE UINT32_C(0x1000)
8433 * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed
8434 * Solomon) on this port if supported. When set to 0, then this flag
8435 * shall be ignored. If FEC CLAUSE 91 is not supported, then the HWRM
8436 * shall ignore this flag.
8438 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE UINT32_C(0x2000)
8440 * When this bit is set to '1', the link shall be forced to be taken
8441 * down. # When this bit is set to '1", all other command input settings
8442 * related to the link speed shall be ignored. Once the link state is
8443 * forced down, it can be explicitly cleared from that state by setting
8444 * this flag to '0'. # If this flag is set to '0', then the link shall
8445 * be cleared from forced down state if the link is in forced down
8446 * state. There may be conditions (e.g. out-of-band or sideband
8447 * configuration changes for the link) outside the scope of the HWRM
8448 * implementation that may clear forced down link state.
8450 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN UINT32_C(0x4000)
8452 /* This bit must be '1' for the auto_mode field to be configured. */
8453 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE UINT32_C(0x1)
8454 /* This bit must be '1' for the auto_duplex field to be configured. */
8455 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX UINT32_C(0x2)
8456 /* This bit must be '1' for the auto_pause field to be configured. */
8457 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE UINT32_C(0x4)
8458 /* This bit must be '1' for the auto_link_speed field to be configured. */
8459 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED UINT32_C(0x8)
8461 * This bit must be '1' for the auto_link_speed_mask field to be
8464 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK UINT32_C(0x10)
8465 /* This bit must be '1' for the wirespeed field to be configured. */
8466 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED UINT32_C(0x20)
8467 /* This bit must be '1' for the lpbk field to be configured. */
8468 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK UINT32_C(0x40)
8469 /* This bit must be '1' for the preemphasis field to be configured. */
8470 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS UINT32_C(0x80)
8471 /* This bit must be '1' for the force_pause field to be configured. */
8472 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE UINT32_C(0x100)
8474 * This bit must be '1' for the eee_link_speed_mask field to be
8477 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK UINT32_C(0x200)
8478 /* This bit must be '1' for the tx_lpi_timer field to be configured. */
8479 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER UINT32_C(0x400)
8481 /* Port ID of port that is to be configured. */
8482 uint16_t force_link_speed;
8484 * This is the speed that will be used if the force bit is '1'. If
8485 * unsupported speed is selected, an error will be generated.
8487 /* 100Mb link speed */
8488 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
8489 /* 1Gb link speed */
8490 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
8491 /* 2Gb link speed */
8492 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
8493 /* 2.5Gb link speed */
8494 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
8495 /* 10Gb link speed */
8496 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
8497 /* 20Mb link speed */
8498 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
8499 /* 25Gb link speed */
8500 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
8501 /* 40Gb link speed */
8502 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
8503 /* 50Gb link speed */
8504 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
8505 /* 100Gb link speed */
8506 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
8507 /* 10Mb link speed */
8508 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
8511 * This value is used to identify what autoneg mode is used when the
8512 * link speed is not being forced.
8514 /* Disable autoneg or autoneg disabled. No speeds are selected. */
8515 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
8516 /* Select all possible speeds for autoneg mode. */
8517 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
8519 * Select only the auto_link_speed speed for autoneg mode. This
8520 * mode has been DEPRECATED. An HWRM client should not use this
8523 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
8525 * Select the auto_link_speed or any speed below that speed for
8526 * autoneg. This mode has been DEPRECATED. An HWRM client should
8527 * not use this mode.
8529 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
8531 * Select the speeds based on the corresponding link speed mask
8532 * value that is provided.
8534 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
8535 uint8_t auto_duplex;
8537 * This is the duplex setting that will be used if the autoneg_mode is
8538 * "one_speed" or "one_or_below".
8540 /* Half Duplex will be requested. */
8541 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
8542 /* Full duplex will be requested. */
8543 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
8544 /* Both Half and Full dupex will be requested. */
8545 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
8548 * This value is used to configure the pause that will be used for
8549 * autonegotiation. Add text on the usage of auto_pause and force_pause.
8552 * When this bit is '1', Generation of tx pause messages has been
8553 * requested. Disabled otherwise.
8555 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX UINT32_C(0x1)
8557 * When this bit is '1', Reception of rx pause messages has been
8558 * requested. Disabled otherwise.
8560 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX UINT32_C(0x2)
8562 * When set to 1, the advertisement of pause is enabled. # When the
8563 * auto_mode is not set to none and this flag is set to 1, then the
8564 * auto_pause bits on this port are being advertised and autoneg pause
8565 * results are being interpreted. # When the auto_mode is not set to
8566 * none and this flag is set to 0, the pause is forced as indicated in
8567 * force_pause, and also advertised as auto_pause bits, but the autoneg
8568 * results are not interpreted since the pause configuration is being
8569 * forced. # When the auto_mode is set to none and this flag is set to
8570 * 1, auto_pause bits should be ignored and should be set to 0.
8572 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE UINT32_C(0x4)
8574 uint16_t auto_link_speed;
8576 * This is the speed that will be used if the autoneg_mode is
8577 * "one_speed" or "one_or_below". If an unsupported speed is selected,
8578 * an error will be generated.
8580 /* 100Mb link speed */
8581 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
8582 /* 1Gb link speed */
8583 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
8584 /* 2Gb link speed */
8585 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
8586 /* 2.5Gb link speed */
8587 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
8588 /* 10Gb link speed */
8589 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
8590 /* 20Mb link speed */
8591 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
8592 /* 25Gb link speed */
8593 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
8594 /* 40Gb link speed */
8595 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
8596 /* 50Gb link speed */
8597 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
8598 /* 100Gb link speed */
8599 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
8600 /* 10Mb link speed */
8601 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
8602 uint16_t auto_link_speed_mask;
8604 * This is a mask of link speeds that will be used if autoneg_mode is
8605 * "mask". If unsupported speed is enabled an error will be generated.
8607 /* 100Mb link speed (Half-duplex) */
8608 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD UINT32_C(0x1)
8609 /* 100Mb link speed (Full-duplex) */
8610 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB UINT32_C(0x2)
8611 /* 1Gb link speed (Half-duplex) */
8612 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD UINT32_C(0x4)
8613 /* 1Gb link speed (Full-duplex) */
8614 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB UINT32_C(0x8)
8615 /* 2Gb link speed */
8616 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB UINT32_C(0x10)
8617 /* 2.5Gb link speed */
8618 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB UINT32_C(0x20)
8619 /* 10Gb link speed */
8620 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB UINT32_C(0x40)
8621 /* 20Gb link speed */
8622 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB UINT32_C(0x80)
8623 /* 25Gb link speed */
8624 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB UINT32_C(0x100)
8625 /* 40Gb link speed */
8626 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB UINT32_C(0x200)
8627 /* 50Gb link speed */
8628 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB UINT32_C(0x400)
8629 /* 100Gb link speed */
8630 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB UINT32_C(0x800)
8631 /* 10Mb link speed (Half-duplex) */
8632 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD UINT32_C(0x1000)
8633 /* 10Mb link speed (Full-duplex) */
8634 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB UINT32_C(0x2000)
8636 /* This value controls the wirespeed feature. */
8637 /* Wirespeed feature is disabled. */
8638 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
8639 /* Wirespeed feature is enabled. */
8640 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
8642 /* This value controls the loopback setting for the PHY. */
8643 /* No loopback is selected. Normal operation. */
8644 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
8646 * The HW will be configured with local loopback such that host
8647 * data is sent back to the host without modification.
8649 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
8651 * The HW will be configured with remote loopback such that port
8652 * logic will send packets back out the transmitter that are
8655 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
8656 uint8_t force_pause;
8658 * This value is used to configure the pause that will be used for force
8662 * When this bit is '1', Generation of tx pause messages is supported.
8663 * Disabled otherwise.
8665 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
8667 * When this bit is '1', Reception of rx pause messages is supported.
8668 * Disabled otherwise.
8670 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
8672 uint32_t preemphasis;
8674 * This value controls the pre-emphasis to be used for the link. Driver
8675 * should not set this value (use enable.preemphasis = 0) unless driver
8676 * is sure of setting. Normally HWRM FW will determine proper pre-
8679 uint16_t eee_link_speed_mask;
8681 * Setting for link speed mask that is used to advertise speeds during
8682 * autonegotiation when EEE is enabled. This field is valid only when
8683 * EEE is enabled. The speeds specified in this field shall be a subset
8684 * of speeds specified in auto_link_speed_mask. If EEE is enabled,then
8685 * at least one speed shall be provided in this mask.
8688 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 UINT32_C(0x1)
8689 /* 100Mb link speed (Full-duplex) */
8690 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB UINT32_C(0x2)
8692 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 UINT32_C(0x4)
8693 /* 1Gb link speed (Full-duplex) */
8694 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB UINT32_C(0x8)
8696 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 UINT32_C(0x10)
8698 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 UINT32_C(0x20)
8699 /* 10Gb link speed */
8700 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB UINT32_C(0x40)
8703 uint32_t tx_lpi_timer;
8706 * Reuested setting of TX LPI timer in microseconds. This field is valid
8707 * only when EEE is enabled and TX LPI is enabled.
8709 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
8710 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
8711 } __attribute__((packed));
8713 /* Output (16 bytes) */
8715 struct hwrm_port_phy_cfg_output {
8716 uint16_t error_code;
8718 * Pass/Fail or error type Note: receiver to verify the in parameters,
8719 * and fail the call with an error when appropriate
8722 /* This field returns the type of original request. */
8724 /* This field provides original sequence number of the command. */
8727 * This field is the length of the response in bytes. The last byte of
8728 * the response is a valid flag that will read as '1' when the command
8729 * has been completely written to memory.
8737 * This field is used in Output records to indicate that the output is
8738 * completely written to RAM. This field should be read as '1' to
8739 * indicate that the output has been completely written. When writing a
8740 * command completion or response to an internal processor, the order of
8741 * writes has to be such that this field is written last.
8743 } __attribute__((packed));
8745 /* hwrm_port_phy_qcfg */
8746 /* Description: This command queries the PHY configuration for the port. */
8747 /* Input (24 bytes) */
8749 struct hwrm_port_phy_qcfg_input {
8752 * This value indicates what type of request this is. The format for the
8753 * rest of the command is determined by this field.
8757 * This value indicates the what completion ring the request will be
8758 * optionally completed on. If the value is -1, then no CR completion
8759 * will be generated. Any other value must be a valid CR ring_id value
8760 * for this function.
8763 /* This value indicates the command sequence number. */
8766 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
8767 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
8771 * This is the host address where the response will be written when the
8772 * request is complete. This area must be 16B aligned and must be
8773 * cleared to zero before the request is made.
8776 /* Port ID of port that is to be queried. */
8777 uint16_t unused_0[3];
8778 } __attribute__((packed));
8780 /* Output (96 bytes) */
8782 struct hwrm_port_phy_qcfg_output {
8783 uint16_t error_code;
8785 * Pass/Fail or error type Note: receiver to verify the in parameters,
8786 * and fail the call with an error when appropriate
8789 /* This field returns the type of original request. */
8791 /* This field provides original sequence number of the command. */
8794 * This field is the length of the response in bytes. The last byte of
8795 * the response is a valid flag that will read as '1' when the command
8796 * has been completely written to memory.
8799 /* This value indicates the current link status. */
8800 /* There is no link or cable detected. */
8801 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
8802 /* There is no link, but a cable has been detected. */
8803 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
8804 /* There is a link. */
8805 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
8807 uint16_t link_speed;
8808 /* This value indicates the current link speed of the connection. */
8809 /* 100Mb link speed */
8810 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
8811 /* 1Gb link speed */
8812 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
8813 /* 2Gb link speed */
8814 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
8815 /* 2.5Gb link speed */
8816 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
8817 /* 10Gb link speed */
8818 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
8819 /* 20Mb link speed */
8820 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
8821 /* 25Gb link speed */
8822 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
8823 /* 40Gb link speed */
8824 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
8825 /* 50Gb link speed */
8826 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
8827 /* 100Gb link speed */
8828 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
8829 /* 10Mb link speed */
8830 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
8832 /* This value is indicates the duplex of the current configuration. */
8833 /* Half Duplex connection. */
8834 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
8835 /* Full duplex connection. */
8836 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
8839 * This value is used to indicate the current pause configuration. When
8840 * autoneg is enabled, this value represents the autoneg results of
8841 * pause configuration.
8844 * When this bit is '1', Generation of tx pause messages is supported.
8845 * Disabled otherwise.
8847 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
8849 * When this bit is '1', Reception of rx pause messages is supported.
8850 * Disabled otherwise.
8852 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
8853 uint16_t support_speeds;
8855 * The supported speeds for the port. This is a bit mask. For each speed
8856 * that is supported, the corrresponding bit will be set to '1'.
8858 /* 100Mb link speed (Half-duplex) */
8859 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD UINT32_C(0x1)
8860 /* 100Mb link speed (Full-duplex) */
8861 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB UINT32_C(0x2)
8862 /* 1Gb link speed (Half-duplex) */
8863 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD UINT32_C(0x4)
8864 /* 1Gb link speed (Full-duplex) */
8865 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB UINT32_C(0x8)
8866 /* 2Gb link speed */
8867 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB UINT32_C(0x10)
8868 /* 2.5Gb link speed */
8869 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB UINT32_C(0x20)
8870 /* 10Gb link speed */
8871 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB UINT32_C(0x40)
8872 /* 20Gb link speed */
8873 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB UINT32_C(0x80)
8874 /* 25Gb link speed */
8875 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB UINT32_C(0x100)
8876 /* 40Gb link speed */
8877 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB UINT32_C(0x200)
8878 /* 50Gb link speed */
8879 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB UINT32_C(0x400)
8880 /* 100Gb link speed */
8881 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB UINT32_C(0x800)
8882 /* 10Mb link speed (Half-duplex) */
8883 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD UINT32_C(0x1000)
8884 /* 10Mb link speed (Full-duplex) */
8885 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB UINT32_C(0x2000)
8886 uint16_t force_link_speed;
8888 * Current setting of forced link speed. When the link speed is not
8889 * being forced, this value shall be set to 0.
8891 /* 100Mb link speed */
8892 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
8893 /* 1Gb link speed */
8894 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
8895 /* 2Gb link speed */
8896 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
8897 /* 2.5Gb link speed */
8898 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
8899 /* 10Gb link speed */
8900 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
8901 /* 20Mb link speed */
8902 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
8903 /* 25Gb link speed */
8904 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
8905 /* 40Gb link speed */
8906 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
8907 /* 50Gb link speed */
8908 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
8909 /* 100Gb link speed */
8910 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
8911 /* 10Mb link speed */
8912 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
8914 /* Current setting of auto negotiation mode. */
8915 /* Disable autoneg or autoneg disabled. No speeds are selected. */
8916 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
8917 /* Select all possible speeds for autoneg mode. */
8918 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
8920 * Select only the auto_link_speed speed for autoneg mode. This
8921 * mode has been DEPRECATED. An HWRM client should not use this
8924 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
8926 * Select the auto_link_speed or any speed below that speed for
8927 * autoneg. This mode has been DEPRECATED. An HWRM client should
8928 * not use this mode.
8930 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
8932 * Select the speeds based on the corresponding link speed mask
8933 * value that is provided.
8935 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
8938 * Current setting of pause autonegotiation. Move autoneg_pause flag
8942 * When this bit is '1', Generation of tx pause messages has been
8943 * requested. Disabled otherwise.
8945 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX UINT32_C(0x1)
8947 * When this bit is '1', Reception of rx pause messages has been
8948 * requested. Disabled otherwise.
8950 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX UINT32_C(0x2)
8952 * When set to 1, the advertisement of pause is enabled. # When the
8953 * auto_mode is not set to none and this flag is set to 1, then the
8954 * auto_pause bits on this port are being advertised and autoneg pause
8955 * results are being interpreted. # When the auto_mode is not set to
8956 * none and this flag is set to 0, the pause is forced as indicated in
8957 * force_pause, and also advertised as auto_pause bits, but the autoneg
8958 * results are not interpreted since the pause configuration is being
8959 * forced. # When the auto_mode is set to none and this flag is set to
8960 * 1, auto_pause bits should be ignored and should be set to 0.
8962 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE UINT32_C(0x4)
8963 uint16_t auto_link_speed;
8965 * Current setting for auto_link_speed. This field is only valid when
8966 * auto_mode is set to "one_speed" or "one_or_below".
8968 /* 100Mb link speed */
8969 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
8970 /* 1Gb link speed */
8971 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
8972 /* 2Gb link speed */
8973 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
8974 /* 2.5Gb link speed */
8975 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
8976 /* 10Gb link speed */
8977 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
8978 /* 20Mb link speed */
8979 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
8980 /* 25Gb link speed */
8981 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
8982 /* 40Gb link speed */
8983 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
8984 /* 50Gb link speed */
8985 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
8986 /* 100Gb link speed */
8987 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
8988 /* 10Mb link speed */
8989 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
8990 uint16_t auto_link_speed_mask;
8992 * Current setting for auto_link_speed_mask that is used to advertise
8993 * speeds during autonegotiation. This field is only valid when
8994 * auto_mode is set to "mask". The speeds specified in this field shall
8995 * be a subset of supported speeds on this port.
8997 /* 100Mb link speed (Half-duplex) */
8998 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD UINT32_C(0x1)
8999 /* 100Mb link speed (Full-duplex) */
9000 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB UINT32_C(0x2)
9001 /* 1Gb link speed (Half-duplex) */
9002 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD UINT32_C(0x4)
9003 /* 1Gb link speed (Full-duplex) */
9004 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB UINT32_C(0x8)
9005 /* 2Gb link speed */
9006 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB UINT32_C(0x10)
9007 /* 2.5Gb link speed */
9008 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB UINT32_C(0x20)
9009 /* 10Gb link speed */
9010 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB UINT32_C(0x40)
9011 /* 20Gb link speed */
9012 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB UINT32_C(0x80)
9013 /* 25Gb link speed */
9014 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB UINT32_C(0x100)
9015 /* 40Gb link speed */
9016 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB UINT32_C(0x200)
9017 /* 50Gb link speed */
9018 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB UINT32_C(0x400)
9019 /* 100Gb link speed */
9020 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB UINT32_C(0x800)
9021 /* 10Mb link speed (Half-duplex) */
9022 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD UINT32_C(0x1000)
9023 /* 10Mb link speed (Full-duplex) */
9024 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB UINT32_C(0x2000)
9026 /* Current setting for wirespeed. */
9027 /* Wirespeed feature is disabled. */
9028 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
9029 /* Wirespeed feature is enabled. */
9030 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
9032 /* Current setting for loopback. */
9033 /* No loopback is selected. Normal operation. */
9034 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
9036 * The HW will be configured with local loopback such that host
9037 * data is sent back to the host without modification.
9039 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
9041 * The HW will be configured with remote loopback such that port
9042 * logic will send packets back out the transmitter that are
9045 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
9046 uint8_t force_pause;
9048 * Current setting of forced pause. When the pause configuration is not
9049 * being forced, then this value shall be set to 0.
9052 * When this bit is '1', Generation of tx pause messages is supported.
9053 * Disabled otherwise.
9055 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
9057 * When this bit is '1', Reception of rx pause messages is supported.
9058 * Disabled otherwise.
9060 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
9061 uint8_t module_status;
9063 * This value indicates the current status of the optics module on this
9066 /* Module is inserted and accepted */
9067 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE UINT32_C(0x0)
9068 /* Module is rejected and transmit side Laser is disabled. */
9069 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX UINT32_C(0x1)
9070 /* Module mismatch warning. */
9071 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG UINT32_C(0x2)
9072 /* Module is rejected and powered down. */
9073 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN UINT32_C(0x3)
9074 /* Module is not inserted. */
9075 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED UINT32_C(0x4)
9076 /* Module status is not applicable. */
9077 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE UINT32_C(0xff)
9078 uint32_t preemphasis;
9079 /* Current setting for preemphasis. */
9081 /* This field represents the major version of the PHY. */
9083 /* This field represents the minor version of the PHY. */
9085 /* This field represents the build version of the PHY. */
9087 /* This value represents a PHY type. */
9089 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN UINT32_C(0x0)
9091 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR UINT32_C(0x1)
9092 /* BASE-KR4 (Deprecated) */
9093 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 UINT32_C(0x2)
9095 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR UINT32_C(0x3)
9097 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR UINT32_C(0x4)
9098 /* BASE-KR2 (Deprecated) */
9099 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 UINT32_C(0x5)
9101 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX UINT32_C(0x6)
9103 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR UINT32_C(0x7)
9105 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET UINT32_C(0x8)
9106 /* EEE capable BASE-T */
9107 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE UINT32_C(0x9)
9108 /* SGMII connected external PHY */
9109 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY UINT32_C(0xa)
9110 /* 25G_BASECR_CA_L */
9111 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L UINT32_C(0xb)
9112 /* 25G_BASECR_CA_S */
9113 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S UINT32_C(0xc)
9114 /* 25G_BASECR_CA_N */
9115 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N UINT32_C(0xd)
9117 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR UINT32_C(0xe)
9119 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 UINT32_C(0xf)
9121 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 UINT32_C(0x10)
9123 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 UINT32_C(0x11)
9125 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 UINT32_C(0x12)
9127 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 UINT32_C(0x13)
9129 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 UINT32_C(0x14)
9131 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 UINT32_C(0x15)
9133 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 UINT32_C(0x16)
9135 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 UINT32_C(0x17)
9136 /* 40G_ACTIVE_CABLE */
9137 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE UINT32_C(0x18)
9139 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET UINT32_C(0x19)
9141 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX UINT32_C(0x1a)
9143 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX UINT32_C(0x1b)
9145 /* This value represents a media type. */
9147 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
9149 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
9150 /* Direct Attached Copper */
9151 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
9153 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
9154 uint8_t xcvr_pkg_type;
9155 /* This value represents a transceiver type. */
9156 /* PHY and MAC are in the same package */
9157 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL UINT32_C(0x1)
9158 /* PHY and MAC are in different packages */
9159 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL UINT32_C(0x2)
9160 uint8_t eee_config_phy_addr;
9162 * This field represents flags related to EEE configuration. These EEE
9163 * configuration flags are valid only when the auto_mode is not set to
9164 * none (in other words autonegotiation is enabled).
9166 /* This field represents PHY address. */
9167 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK UINT32_C(0x1f)
9168 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
9170 * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.
9171 * Speeds for autoneg with EEE mode enabled are based on
9172 * eee_link_speed_mask.
9174 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED UINT32_C(0x20)
9176 * This flag is valid only when eee_enabled is set to 1. # If
9177 * eee_enabled is set to 0, then EEE mode is disabled and this flag
9178 * shall be ignored. # If eee_enabled is set to 1 and this flag is set
9179 * to 1, then Energy Efficient Ethernet (EEE) mode is enabled and in
9180 * use. # If eee_enabled is set to 1 and this flag is set to 0, then
9181 * Energy Efficient Ethernet (EEE) mode is enabled but is currently not
9184 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE UINT32_C(0x40)
9186 * This flag is valid only when eee_enabled is set to 1. # If
9187 * eee_enabled is set to 0, then EEE mode is disabled and this flag
9188 * shall be ignored. # If eee_enabled is set to 1 and this flag is set
9189 * to 1, then Energy Efficient Ethernet (EEE) mode is enabled and TX LPI
9190 * is enabled. # If eee_enabled is set to 1 and this flag is set to 0,
9191 * then Energy Efficient Ethernet (EEE) mode is enabled but TX LPI is
9194 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI UINT32_C(0x80)
9196 * This field represents flags related to EEE configuration. These EEE
9197 * configuration flags are valid only when the auto_mode is not set to
9198 * none (in other words autonegotiation is enabled).
9200 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK UINT32_C(0xe0)
9201 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5
9202 uint8_t parallel_detect;
9203 /* Reserved field, set to 0 */
9205 * When set to 1, the parallel detection is used to determine the speed
9206 * of the link partner. Parallel detection is used when a
9207 * autonegotiation capable device is connected to a link parter that is
9208 * not capable of autonegotiation.
9210 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
9211 /* Reserved field, set to 0 */
9212 #define HWRM_PORT_PHY_QCFG_OUTPUT_RESERVED_MASK UINT32_C(0xfe)
9213 #define HWRM_PORT_PHY_QCFG_OUTPUT_RESERVED_SFT 1
9214 uint16_t link_partner_adv_speeds;
9216 * The advertised speeds for the port by the link partner. Each
9217 * advertised speed will be set to '1'.
9219 /* 100Mb link speed (Half-duplex) */
9220 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD UINT32_C(0x1)
9221 /* 100Mb link speed (Full-duplex) */
9222 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB UINT32_C(0x2)
9223 /* 1Gb link speed (Half-duplex) */
9224 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD UINT32_C(0x4)
9225 /* 1Gb link speed (Full-duplex) */
9226 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB UINT32_C(0x8)
9227 /* 2Gb link speed */
9228 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB UINT32_C(0x10)
9229 /* 2.5Gb link speed */
9230 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB UINT32_C(0x20)
9231 /* 10Gb link speed */
9232 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB UINT32_C(0x40)
9233 /* 20Gb link speed */
9234 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB UINT32_C(0x80)
9235 /* 25Gb link speed */
9236 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB UINT32_C(0x100)
9237 /* 40Gb link speed */
9238 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB UINT32_C(0x200)
9239 /* 50Gb link speed */
9240 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB UINT32_C(0x400)
9241 /* 100Gb link speed */
9242 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB UINT32_C(0x800)
9243 /* 10Mb link speed (Half-duplex) */
9244 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD UINT32_C(0x1000)
9245 /* 10Mb link speed (Full-duplex) */
9246 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB UINT32_C(0x2000)
9247 uint8_t link_partner_adv_auto_mode;
9249 * The advertised autoneg for the port by the link partner. This field
9250 * is deprecated and should be set to 0.
9252 /* Disable autoneg or autoneg disabled. No speeds are selected. */
9253 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE UINT32_C(0x0)
9254 /* Select all possible speeds for autoneg mode. */
9255 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
9257 * Select only the auto_link_speed speed for autoneg mode. This
9258 * mode has been DEPRECATED. An HWRM client should not use this
9261 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
9263 * Select the auto_link_speed or any speed below that speed for
9264 * autoneg. This mode has been DEPRECATED. An HWRM client should
9265 * not use this mode.
9267 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
9269 * Select the speeds based on the corresponding link speed mask
9270 * value that is provided.
9272 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
9273 uint8_t link_partner_adv_pause;
9274 /* The advertised pause settings on the port by the link partner. */
9276 * When this bit is '1', Generation of tx pause messages is supported.
9277 * Disabled otherwise.
9279 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX UINT32_C(0x1)
9281 * When this bit is '1', Reception of rx pause messages is supported.
9282 * Disabled otherwise.
9284 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX UINT32_C(0x2)
9285 uint16_t adv_eee_link_speed_mask;
9287 * Current setting for link speed mask that is used to advertise speeds
9288 * during autonegotiation when EEE is enabled. This field is valid only
9289 * when eee_enabled flags is set to 1. The speeds specified in this
9290 * field shall be a subset of speeds specified in auto_link_speed_mask.
9293 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 UINT32_C(0x1)
9294 /* 100Mb link speed (Full-duplex) */
9295 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB UINT32_C(0x2)
9297 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 UINT32_C(0x4)
9298 /* 1Gb link speed (Full-duplex) */
9299 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB UINT32_C(0x8)
9301 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 UINT32_C(0x10)
9303 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 UINT32_C(0x20)
9304 /* 10Gb link speed */
9305 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB UINT32_C(0x40)
9306 uint16_t link_partner_adv_eee_link_speed_mask;
9308 * Current setting for link speed mask that is advertised by the link
9309 * partner when EEE is enabled. This field is valid only when
9310 * eee_enabled flags is set to 1.
9313 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 UINT32_C(0x1)
9314 /* 100Mb link speed (Full-duplex) */
9315 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB UINT32_C(0x2)
9317 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 UINT32_C(0x4)
9318 /* 1Gb link speed (Full-duplex) */
9319 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB UINT32_C(0x8)
9321 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 UINT32_C(0x10)
9323 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 UINT32_C(0x20)
9324 /* 10Gb link speed */
9325 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB UINT32_C(0x40)
9326 uint32_t xcvr_identifier_type_tx_lpi_timer;
9327 /* This value represents transceiver identifier type. */
9329 * Current setting of TX LPI timer in microseconds. This field is valid
9330 * only when_eee_enabled flag is set to 1 and tx_lpi_enabled is set to
9333 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
9334 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
9335 /* This value represents transceiver identifier type. */
9336 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK UINT32_C(0xff000000)
9337 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24
9339 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN (UINT32_C(0x0) << 24)
9340 /* SFP/SFP+/SFP28 */
9341 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP (UINT32_C(0x3) << 24)
9343 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP (UINT32_C(0xc) << 24)
9345 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS (UINT32_C(0xd) << 24)
9347 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 (UINT32_C(0x11) << 24)
9350 * This value represents the current configuration of Forward Error
9351 * Correction (FEC) on the port.
9354 * When set to 1, then FEC is not supported on this port. If this flag
9355 * is set to 1, then all other FEC configuration flags shall be ignored.
9356 * When set to 0, then FEC is supported as indicated by other
9357 * configuration flags. If no cable is attached and the HWRM does not
9358 * yet know the FEC capability, then the HWRM shall set this flag to 1
9359 * when reporting FEC capability.
9361 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED UINT32_C(0x1)
9363 * When set to 1, then FEC autonegotiation is supported on this port.
9364 * When set to 0, then FEC autonegotiation is not supported on this
9367 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED UINT32_C(0x2)
9369 * When set to 1, then FEC autonegotiation is enabled on this port. When
9370 * set to 0, then FEC autonegotiation is disabled if supported. This
9371 * flag should be ignored if FEC autonegotiation is not supported on
9374 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED UINT32_C(0x4)
9376 * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this
9377 * port. When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported
9380 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED UINT32_C(0x8)
9382 * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this
9383 * port. When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if
9384 * supported. This flag should be ignored if FEC CLAUSE 74 is not
9385 * supported on this port.
9387 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED UINT32_C(0x10)
9389 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this
9390 * port. When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not
9391 * supported on this port.
9393 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED UINT32_C(0x20)
9395 * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this
9396 * port. When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if
9397 * supported. This flag should be ignored if FEC CLAUSE 91 is not
9398 * supported on this port.
9400 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED UINT32_C(0x40)
9401 uint8_t duplex_state;
9402 /* This value is indicates the duplex of the current connection state. */
9403 /* Half Duplex connection. */
9404 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
9405 /* Full duplex connection. */
9406 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
9408 char phy_vendor_name[16];
9410 * Up to 16 bytes of null padded ASCII string representing PHY vendor.
9411 * If the string is set to null, then the vendor name is not available.
9413 char phy_vendor_partnumber[16];
9415 * Up to 16 bytes of null padded ASCII string that identifies vendor
9416 * specific part number of the PHY. If the string is set to null, then
9417 * the vendor specific part number is not available.
9425 * This field is used in Output records to indicate that the output is
9426 * completely written to RAM. This field should be read as '1' to
9427 * indicate that the output has been completely written. When writing a
9428 * command completion or response to an internal processor, the order of
9429 * writes has to be such that this field is written last.
9431 } __attribute__((packed));
9433 /* hwrm_port_mac_cfg */
9435 * Description: This command configures the MAC block for the port. # Only PF
9436 * drivers shall be allowed to configure MAC. # A VF driver should not be
9437 * allowed to configure MAC using this command. # In a network partition mode, a
9438 * PF driver should not be allowed to configure MAC using this command. The QoS
9439 * settings in port_mac_cfg() are global for all ports/functions. If multiple PF
9440 * drivers on different ports are configuring QoS settings, then the HWRM is not
9441 * responsible for maintaining consistency between them. A PF driver changing
9442 * global QoS settings using this command may impact other PF drivers on
9445 /* Input (40 bytes) */
9447 struct hwrm_port_mac_cfg_input {
9450 * This value indicates what type of request this is. The format for the
9451 * rest of the command is determined by this field.
9455 * This value indicates the what completion ring the request will be
9456 * optionally completed on. If the value is -1, then no CR completion
9457 * will be generated. Any other value must be a valid CR ring_id value
9458 * for this function.
9461 /* This value indicates the command sequence number. */
9464 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
9465 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
9469 * This is the host address where the response will be written when the
9470 * request is complete. This area must be 16B aligned and must be
9471 * cleared to zero before the request is made.
9475 * In this field, there are a number of CoS mappings related flags that
9476 * are used to configure CoS mappings and their corresponding priorities
9477 * in the hardware. For the priorities of CoS mappings, the HWRM uses
9478 * the following priority order (high to low) by default: # vlan pri #
9479 * ip_dscp # tunnel_vlan_pri # default cos A subset of CoS mappings can
9480 * be enabled. If a priority is not specified for an enabled CoS
9481 * mapping, the priority will be assigned in the above order for the
9482 * enabled CoS mappings. For example, if vlan_pri and ip_dscp CoS
9483 * mappings are enabled and their priorities are not specified, the
9484 * following priority order (high to low) will be used by the HWRM: #
9485 * vlan_pri # ip_dscp # default cos vlan_pri CoS mapping together with
9486 * default CoS with lower priority are enabled by default by the HWRM.
9489 * When this bit is '1', this command will configure the MAC to match
9490 * the current link state of the PHY. If the link is not established on
9491 * the PHY, then this bit has no effect.
9493 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK UINT32_C(0x1)
9495 * When this bit is set to '1', the inner VLAN PRI to CoS mapping is
9496 * requested to be enabled.
9498 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE UINT32_C(0x2)
9500 * When this bit is set to '1', tunnel VLAN PRI field to CoS mapping is
9501 * requested to be enabled.
9503 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE UINT32_C(0x4)
9505 * When this bit is set to '1', the IP DSCP to CoS mapping is requested
9508 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE UINT32_C(0x8)
9510 * When this bit is '1', the HWRM is requested to enable timestamp
9511 * capture capability on the receive side of this port.
9513 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE UINT32_C(0x10)
9515 * When this bit is '1', the HWRM is requested to disable timestamp
9516 * capture capability on the receive side of this port.
9518 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE UINT32_C(0x20)
9520 * When this bit is '1', the HWRM is requested to enable timestamp
9521 * capture capability on the transmit side of this port.
9523 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE UINT32_C(0x40)
9525 * When this bit is '1', the HWRM is requested to disable timestamp
9526 * capture capability on the transmit side of this port.
9528 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE UINT32_C(0x80)
9530 * When this bit is '1', the Out-Of-Box WoL is requested to be enabled
9533 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE UINT32_C(0x100)
9535 * When this bit is '1', the the Out-Of-Box WoL is requested to be
9536 * disabled on this port.
9538 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE UINT32_C(0x200)
9540 * When this bit is set to '1', the inner VLAN PRI to CoS mapping is
9541 * requested to be disabled.
9543 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE UINT32_C(0x400)
9545 * When this bit is set to '1', tunnel VLAN PRI field to CoS mapping is
9546 * requested to be disabled.
9548 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE UINT32_C(0x800)
9550 * When this bit is set to '1', the IP DSCP to CoS mapping is requested
9553 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE UINT32_C(0x1000)
9555 /* This bit must be '1' for the ipg field to be configured. */
9556 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG UINT32_C(0x1)
9557 /* This bit must be '1' for the lpbk field to be configured. */
9558 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK UINT32_C(0x2)
9560 * This bit must be '1' for the vlan_pri2cos_map_pri field to be
9563 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI UINT32_C(0x4)
9564 /* This bit must be '1' for the Reserved1 field to be configured. */
9565 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RESERVED1 UINT32_C(0x8)
9567 * This bit must be '1' for the tunnel_pri2cos_map_pri field to be
9570 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI UINT32_C(0x10)
9571 /* This bit must be '1' for the dscp2cos_map_pri field to be configured. */
9572 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI UINT32_C(0x20)
9574 * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be
9577 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE UINT32_C(0x40)
9579 * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be
9582 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE UINT32_C(0x80)
9583 /* This bit must be '1' for the cos_field_cfg field to be configured. */
9584 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG UINT32_C(0x100)
9586 /* Port ID of port that is to be configured. */
9589 * This value is used to configure the minimum IPG that will be sent
9590 * between packets by this port.
9593 /* This value controls the loopback setting for the MAC. */
9594 /* No loopback is selected. Normal operation. */
9595 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
9597 * The HW will be configured with local loopback such that host
9598 * data is sent back to the host without modification.
9600 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
9602 * The HW will be configured with remote loopback such that port
9603 * logic will send packets back out the transmitter that are
9606 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
9607 uint8_t vlan_pri2cos_map_pri;
9609 * This value controls the priority setting of VLAN PRI to CoS mapping
9610 * based on VLAN Tags of inner packet headers of tunneled packets or
9611 * packet headers of non-tunneled packets. # Each XXX_pri variable shall
9612 * have a unique priority value when it is being specified. # When
9613 * comparing priorities of mappings, higher value indicates higher
9614 * priority. For example, a value of 0-3 is returned where 0 is being
9615 * the lowest priority and 3 is being the highest priority.
9618 /* Reserved field */
9619 uint8_t tunnel_pri2cos_map_pri;
9621 * This value controls the priority setting of VLAN PRI to CoS mapping
9622 * based on VLAN Tags of tunneled header. This mapping only applies when
9623 * tunneled headers are present. # Each XXX_pri variable shall have a
9624 * unique priority value when it is being specified. # When comparing
9625 * priorities of mappings, higher value indicates higher priority. For
9626 * example, a value of 0-3 is returned where 0 is being the lowest
9627 * priority and 3 is being the highest priority.
9629 uint8_t dscp2pri_map_pri;
9631 * This value controls the priority setting of IP DSCP to CoS mapping
9632 * based on inner IP header of tunneled packets or IP header of non-
9633 * tunneled packets. # Each XXX_pri variable shall have a unique
9634 * priority value when it is being specified. # When comparing
9635 * priorities of mappings, higher value indicates higher priority. For
9636 * example, a value of 0-3 is returned where 0 is being the lowest
9637 * priority and 3 is being the highest priority.
9639 uint16_t rx_ts_capture_ptp_msg_type;
9641 * This is a 16-bit bit mask that is used to request a specific
9642 * configuration of time stamp capture of PTP messages on the receive
9643 * side of this port. This field shall be ignored if the
9644 * ptp_rx_ts_capture_enable flag is not set in this command. Otherwise,
9645 * if bit 'i' is set, then the HWRM is being requested to configure the
9646 * receive side of the port to capture the time stamp of every received
9647 * PTP message with messageType field value set to i.
9649 uint16_t tx_ts_capture_ptp_msg_type;
9651 * This is a 16-bit bit mask that is used to request a specific
9652 * configuration of time stamp capture of PTP messages on the transmit
9653 * side of this port. This field shall be ignored if the
9654 * ptp_tx_ts_capture_enable flag is not set in this command. Otherwise,
9655 * if bit 'i' is set, then the HWRM is being requested to configure the
9656 * transmit sied of the port to capture the time stamp of every
9657 * transmitted PTP message with messageType field value set to i.
9659 uint8_t cos_field_cfg;
9660 /* Configuration of CoS fields. */
9662 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 UINT32_C(0x1)
9664 * This field is used to specify selection of VLAN PRI value based on
9665 * whether one or two VLAN Tags are present in the inner packet headers
9666 * of tunneled packets or non-tunneled packets. This field is valid only
9667 * if inner VLAN PRI to CoS mapping is enabled. If VLAN PRI to CoS
9668 * mapping is not enabled, then this field shall be ignored.
9670 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK UINT32_C(0x6)
9671 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1
9673 * Select inner VLAN PRI when 1 or 2 VLAN Tags are present in
9674 * the inner packet headers
9676 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (UINT32_C(0x0) << 1)
9678 * Select outer VLAN Tag PRI when 2 VLAN Tags are present in the
9679 * inner packet headers. No VLAN PRI shall be selected for this
9680 * configuration if only one VLAN Tag is present in the inner
9683 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (UINT32_C(0x1) << 1)
9685 * Select outermost VLAN PRI when 1 or 2 VLAN Tags are present
9686 * in the inner packet headers
9688 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (UINT32_C(0x2) << 1)
9690 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (UINT32_C(0x3) << 1)
9691 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
9693 * This field is used to specify selection of tunnel VLAN PRI value
9694 * based on whether one or two VLAN Tags are present in tunnel headers.
9695 * This field is valid only if tunnel VLAN PRI to CoS mapping is
9696 * enabled. If tunnel VLAN PRI to CoS mapping is not enabled, then this
9697 * field shall be ignored.
9699 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK UINT32_C(0x18)
9700 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3
9702 * Select inner VLAN PRI when 1 or 2 VLAN Tags are present in
9703 * the tunnel packet headers
9705 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (UINT32_C(0x0) << 3)
9707 * Select outer VLAN Tag PRI when 2 VLAN Tags are present in the
9708 * tunnel packet headers. No tunnel VLAN PRI shall be selected
9709 * for this configuration if only one VLAN Tag is present in the
9710 * tunnel packet headers.
9712 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (UINT32_C(0x1) << 3)
9714 * Select outermost VLAN PRI when 1 or 2 VLAN Tags are present
9715 * in the tunnel packet headers
9717 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (UINT32_C(0x2) << 3)
9719 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (UINT32_C(0x3) << 3)
9720 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
9722 * This field shall be used to provide default CoS value that has been
9723 * configured on this port. This field is valid only if default CoS
9724 * mapping is enabled. If default CoS mapping is not enabled, then this
9725 * field shall be ignored.
9727 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK UINT32_C(0xe0)
9728 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT 5
9729 uint8_t unused_0[3];
9730 } __attribute__((packed));
9732 /* Output (16 bytes) */
9734 struct hwrm_port_mac_cfg_output {
9735 uint16_t error_code;
9737 * Pass/Fail or error type Note: receiver to verify the in parameters,
9738 * and fail the call with an error when appropriate
9741 /* This field returns the type of original request. */
9743 /* This field provides original sequence number of the command. */
9746 * This field is the length of the response in bytes. The last byte of
9747 * the response is a valid flag that will read as '1' when the command
9748 * has been completely written to memory.
9752 * This is the configured maximum length of Ethernet packet payload that
9753 * is allowed to be received on the port. This value does not include
9754 * the number of bytes used by Ethernet header and trailer (CRC).
9758 * This is the configured maximum length of Ethernet packet payload that
9759 * is allowed to be transmitted on the port. This value does not include
9760 * the number of bytes used by Ethernet header and trailer (CRC).
9763 /* Current configuration of the IPG value. */
9765 /* Current value of the loopback value. */
9766 /* No loopback is selected. Normal operation. */
9767 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
9769 * The HW will be configured with local loopback such that host
9770 * data is sent back to the host without modification.
9772 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
9774 * The HW will be configured with remote loopback such that port
9775 * logic will send packets back out the transmitter that are
9778 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
9782 * This field is used in Output records to indicate that the output is
9783 * completely written to RAM. This field should be read as '1' to
9784 * indicate that the output has been completely written. When writing a
9785 * command completion or response to an internal processor, the order of
9786 * writes has to be such that this field is written last.
9788 } __attribute__((packed));
9790 /* hwrm_port_mac_qcfg */
9791 /* Description: This command queries the MAC block for the port. */
9792 /* Input (24 bytes) */
9794 struct hwrm_port_mac_qcfg_input {
9797 * This value indicates what type of request this is. The format for the
9798 * rest of the command is determined by this field.
9802 * This value indicates the what completion ring the request will be
9803 * optionally completed on. If the value is -1, then no CR completion
9804 * will be generated. Any other value must be a valid CR ring_id value
9805 * for this function.
9808 /* This value indicates the command sequence number. */
9811 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
9812 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
9816 * This is the host address where the response will be written when the
9817 * request is complete. This area must be 16B aligned and must be
9818 * cleared to zero before the request is made.
9821 /* Port ID of port that is to be configured. */
9822 uint16_t unused_0[3];
9823 } __attribute__((packed));
9825 /* Output (24 bytes) */
9827 struct hwrm_port_mac_qcfg_output {
9828 uint16_t error_code;
9830 * Pass/Fail or error type Note: receiver to verify the in parameters,
9831 * and fail the call with an error when appropriate
9834 /* This field returns the type of original request. */
9836 /* This field provides original sequence number of the command. */
9839 * This field is the length of the response in bytes. The last byte of
9840 * the response is a valid flag that will read as '1' when the command
9841 * has been completely written to memory.
9845 * This is the configured maximum length of Ethernet packet payload that
9846 * is allowed to be received on the port. This value does not include
9847 * the number of bytes used by the Ethernet header and trailer (CRC).
9851 * This is the configured maximum length of Ethernet packet payload that
9852 * is allowed to be transmitted on the port. This value does not include
9853 * the number of bytes used by the Ethernet header and trailer (CRC).
9856 /* The minimum IPG that will be sent between packets by this port. */
9858 /* The loopback setting for the MAC. */
9859 /* No loopback is selected. Normal operation. */
9860 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
9862 * The HW will be configured with local loopback such that host
9863 * data is sent back to the host without modification.
9865 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
9867 * The HW will be configured with remote loopback such that port
9868 * logic will send packets back out the transmitter that are
9871 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
9872 uint8_t vlan_pri2cos_map_pri;
9874 * Priority setting for VLAN PRI to CoS mapping. # Each XXX_pri variable
9875 * shall have a unique priority value when it is being used. # When
9876 * comparing priorities of mappings, higher value indicates higher
9877 * priority. For example, a value of 0-3 is returned where 0 is being
9878 * the lowest priority and 3 is being the highest priority. # If the
9879 * correspoding CoS mapping is not enabled, then this field should be
9880 * ignored. # This value indicates the normalized priority value
9881 * retained in the HWRM.
9885 * In this field, a number of CoS mappings related flags are used to
9886 * indicate configured CoS mappings.
9889 * When this bit is set to '1', the inner VLAN PRI to CoS mapping is
9892 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE UINT32_C(0x1)
9894 * When this bit is set to '1', tunnel VLAN PRI field to CoS mapping is
9897 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE UINT32_C(0x2)
9898 /* When this bit is set to '1', the IP DSCP to CoS mapping is enabled. */
9899 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE UINT32_C(0x4)
9900 /* When this bit is '1', the Out-Of-Box WoL is enabled on this port. */
9901 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE UINT32_C(0x8)
9902 /* When this bit is '1', PTP is enabled for RX on this port. */
9903 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE UINT32_C(0x10)
9904 /* When this bit is '1', PTP is enabled for TX on this port. */
9905 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE UINT32_C(0x20)
9906 uint8_t tunnel_pri2cos_map_pri;
9908 * Priority setting for tunnel VLAN PRI to CoS mapping. # Each XXX_pri
9909 * variable shall have a unique priority value when it is being used. #
9910 * When comparing priorities of mappings, higher value indicates higher
9911 * priority. For example, a value of 0-3 is returned where 0 is being
9912 * the lowest priority and 3 is being the highest priority. # If the
9913 * correspoding CoS mapping is not enabled, then this field should be
9914 * ignored. # This value indicates the normalized priority value
9915 * retained in the HWRM.
9917 uint8_t dscp2pri_map_pri;
9919 * Priority setting for DSCP to PRI mapping. # Each XXX_pri variable
9920 * shall have a unique priority value when it is being used. # When
9921 * comparing priorities of mappings, higher value indicates higher
9922 * priority. For example, a value of 0-3 is returned where 0 is being
9923 * the lowest priority and 3 is being the highest priority. # If the
9924 * correspoding CoS mapping is not enabled, then this field should be
9925 * ignored. # This value indicates the normalized priority value
9926 * retained in the HWRM.
9928 uint16_t rx_ts_capture_ptp_msg_type;
9930 * This is a 16-bit bit mask that represents the current configuration
9931 * of time stamp capture of PTP messages on the receive side of this
9932 * port. If bit 'i' is set, then the receive side of the port is
9933 * configured to capture the time stamp of every received PTP message
9934 * with messageType field value set to i. If all bits are set to 0 (i.e.
9935 * field value set 0), then the receive side of the port is not
9936 * configured to capture timestamp for PTP messages. If all bits are set
9937 * to 1, then the receive side of the port is configured to capture
9938 * timestamp for all PTP messages.
9940 uint16_t tx_ts_capture_ptp_msg_type;
9942 * This is a 16-bit bit mask that represents the current configuration
9943 * of time stamp capture of PTP messages on the transmit side of this
9944 * port. If bit 'i' is set, then the transmit side of the port is
9945 * configured to capture the time stamp of every received PTP message
9946 * with messageType field value set to i. If all bits are set to 0 (i.e.
9947 * field value set 0), then the transmit side of the port is not
9948 * configured to capture timestamp for PTP messages. If all bits are set
9949 * to 1, then the transmit side of the port is configured to capture
9950 * timestamp for all PTP messages.
9952 uint8_t cos_field_cfg;
9953 /* Configuration of CoS fields. */
9955 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD UINT32_C(0x1)
9957 * This field is used for selecting VLAN PRI value based on whether one
9958 * or two VLAN Tags are present in the inner packet headers of tunneled
9959 * packets or non-tunneled packets.
9961 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK UINT32_C(0x6)
9962 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1
9964 * Select inner VLAN PRI when 1 or 2 VLAN Tags are present in
9965 * the inner packet headers
9967 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (UINT32_C(0x0) << 1)
9969 * Select outer VLAN Tag PRI when 2 VLAN Tags are present in the
9970 * inner packet headers. No VLAN PRI is selected for this
9971 * configuration if only one VLAN Tag is present in the inner
9974 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (UINT32_C(0x1) << 1)
9976 * Select outermost VLAN PRI when 1 or 2 VLAN Tags are present
9977 * in the inner packet headers
9979 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (UINT32_C(0x2) << 1)
9981 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (UINT32_C(0x3) << 1)
9982 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED
9984 * This field is used for selecting tunnel VLAN PRI value based on
9985 * whether one or two VLAN Tags are present in the tunnel headers of
9986 * tunneled packets. This selection does not apply to non-tunneled
9989 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK UINT32_C(0x18)
9990 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3
9992 * Select inner VLAN PRI when 1 or 2 VLAN Tags are present in
9993 * the tunnel packet headers
9995 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (UINT32_C(0x0) << 3)
9997 * Select outer VLAN Tag PRI when 2 VLAN Tags are present in the
9998 * tunnel packet headers. No VLAN PRI is selected for this
9999 * configuration if only one VLAN Tag is present in the tunnel
10002 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (UINT32_C(0x1) << 3)
10004 * Select outermost VLAN PRI when 1 or 2 VLAN Tags are present
10005 * in the tunnel packet headers
10007 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (UINT32_C(0x2) << 3)
10009 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (UINT32_C(0x3) << 3)
10010 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED
10012 * This field is used to provide default CoS value that has been
10013 * configured on this port.
10015 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK UINT32_C(0xe0)
10016 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT 5
10019 * This field is used in Output records to indicate that the output is
10020 * completely written to RAM. This field should be read as '1' to
10021 * indicate that the output has been completely written. When writing a
10022 * command completion or response to an internal processor, the order of
10023 * writes has to be such that this field is written last.
10025 } __attribute__((packed));
10027 /* hwrm_port_mac_ptp_qcfg */
10028 /* Description: This command queries the PTP information for the port. */
10029 /* Input (24 bytes) */
10031 struct hwrm_port_mac_ptp_qcfg_input {
10034 * This value indicates what type of request this is. The format for the
10035 * rest of the command is determined by this field.
10037 uint16_t cmpl_ring;
10039 * This value indicates the what completion ring the request will be
10040 * optionally completed on. If the value is -1, then no CR completion
10041 * will be generated. Any other value must be a valid CR ring_id value
10042 * for this function.
10045 /* This value indicates the command sequence number. */
10046 uint16_t target_id;
10048 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
10049 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
10051 uint64_t resp_addr;
10053 * This is the host address where the response will be written when the
10054 * request is complete. This area must be 16B aligned and must be
10055 * cleared to zero before the request is made.
10058 /* Port ID of port that is being queried. */
10059 uint16_t unused_0[3];
10060 } __attribute__((packed));
10062 /* Output (80 bytes) */
10064 struct hwrm_port_mac_ptp_qcfg_output {
10065 uint16_t error_code;
10067 * Pass/Fail or error type Note: receiver to verify the in parameters,
10068 * and fail the call with an error when appropriate
10071 /* This field returns the type of original request. */
10073 /* This field provides original sequence number of the command. */
10076 * This field is the length of the response in bytes. The last byte of
10077 * the response is a valid flag that will read as '1' when the command
10078 * has been completely written to memory.
10082 * In this field, a number of PTP related flags are used to indicate
10083 * configured PTP capabilities.
10086 * When this bit is set to '1', the PTP related registers are directly
10087 * accessible by the host.
10089 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS UINT32_C(0x1)
10091 * When this bit is set to '1', the PTP information is accessible via
10094 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS UINT32_C(0x2)
10097 uint32_t rx_ts_reg_off_lower;
10098 /* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
10099 uint32_t rx_ts_reg_off_upper;
10100 /* Offset of the PTP register for the upper 32 bits of timestamp for RX. */
10101 uint32_t rx_ts_reg_off_seq_id;
10102 /* Offset of the PTP register for the sequence ID for RX. */
10103 uint32_t rx_ts_reg_off_src_id_0;
10104 /* Offset of the first PTP source ID for RX. */
10105 uint32_t rx_ts_reg_off_src_id_1;
10106 /* Offset of the second PTP source ID for RX. */
10107 uint32_t rx_ts_reg_off_src_id_2;
10108 /* Offset of the third PTP source ID for RX. */
10109 uint32_t rx_ts_reg_off_domain_id;
10110 /* Offset of the domain ID for RX. */
10111 uint32_t rx_ts_reg_off_fifo;
10112 /* Offset of the PTP FIFO register for RX. */
10113 uint32_t rx_ts_reg_off_fifo_adv;
10114 /* Offset of the PTP advance FIFO register for RX. */
10115 uint32_t rx_ts_reg_off_granularity;
10116 /* PTP timestamp granularity for RX. */
10117 uint32_t tx_ts_reg_off_lower;
10118 /* Offset of the PTP register for the lower 32 bits of timestamp for TX. */
10119 uint32_t tx_ts_reg_off_upper;
10120 /* Offset of the PTP register for the upper 32 bits of timestamp for TX. */
10121 uint32_t tx_ts_reg_off_seq_id;
10122 /* Offset of the PTP register for the sequence ID for TX. */
10123 uint32_t tx_ts_reg_off_fifo;
10124 /* Offset of the PTP FIFO register for TX. */
10125 uint32_t tx_ts_reg_off_granularity;
10126 /* PTP timestamp granularity for TX. */
10133 * This field is used in Output records to indicate that the output is
10134 * completely written to RAM. This field should be read as '1' to
10135 * indicate that the output has been completely written. When writing a
10136 * command completion or response to an internal processor, the order of
10137 * writes has to be such that this field is written last.
10139 } __attribute__((packed));
10141 /* hwrm_port_qstats */
10142 /* Description: This function returns per port Ethernet statistics. */
10143 /* Input (40 bytes) */
10145 struct hwrm_port_qstats_input {
10148 * This value indicates what type of request this is. The format for the
10149 * rest of the command is determined by this field.
10151 uint16_t cmpl_ring;
10153 * This value indicates the what completion ring the request will be
10154 * optionally completed on. If the value is -1, then no CR completion
10155 * will be generated. Any other value must be a valid CR ring_id value
10156 * for this function.
10159 /* This value indicates the command sequence number. */
10160 uint16_t target_id;
10162 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
10163 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
10165 uint64_t resp_addr;
10167 * This is the host address where the response will be written when the
10168 * request is complete. This area must be 16B aligned and must be
10169 * cleared to zero before the request is made.
10172 /* Port ID of port that is being queried. */
10175 uint8_t unused_2[3];
10177 uint64_t tx_stat_host_addr;
10178 /* This is the host address where Tx port statistics will be stored */
10179 uint64_t rx_stat_host_addr;
10180 /* This is the host address where Rx port statistics will be stored */
10181 } __attribute__((packed));
10183 /* Output (16 bytes) */
10185 struct hwrm_port_qstats_output {
10186 uint16_t error_code;
10188 * Pass/Fail or error type Note: receiver to verify the in parameters,
10189 * and fail the call with an error when appropriate
10192 /* This field returns the type of original request. */
10194 /* This field provides original sequence number of the command. */
10197 * This field is the length of the response in bytes. The last byte of
10198 * the response is a valid flag that will read as '1' when the command
10199 * has been completely written to memory.
10201 uint16_t tx_stat_size;
10202 /* The size of TX port statistics block in bytes. */
10203 uint16_t rx_stat_size;
10204 /* The size of RX port statistics block in bytes. */
10210 * This field is used in Output records to indicate that the output is
10211 * completely written to RAM. This field should be read as '1' to
10212 * indicate that the output has been completely written. When writing a
10213 * command completion or response to an internal processor, the order of
10214 * writes has to be such that this field is written last.
10216 } __attribute__((packed));
10218 /* hwrm_port_lpbk_qstats */
10219 /* Description: This function returns loopback statistics. */
10220 /* Input (16 bytes) */
10222 struct hwrm_port_lpbk_qstats_input {
10225 * This value indicates what type of request this is. The format for the
10226 * rest of the command is determined by this field.
10228 uint16_t cmpl_ring;
10230 * This value indicates the what completion ring the request will be
10231 * optionally completed on. If the value is -1, then no CR completion
10232 * will be generated. Any other value must be a valid CR ring_id value
10233 * for this function.
10236 /* This value indicates the command sequence number. */
10237 uint16_t target_id;
10239 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
10240 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
10242 uint64_t resp_addr;
10244 * This is the host address where the response will be written when the
10245 * request is complete. This area must be 16B aligned and must be
10246 * cleared to zero before the request is made.
10248 } __attribute__((packed));
10250 /* Output (96 bytes) */
10252 struct hwrm_port_lpbk_qstats_output {
10253 uint16_t error_code;
10255 * Pass/Fail or error type Note: receiver to verify the in parameters,
10256 * and fail the call with an error when appropriate
10259 /* This field returns the type of original request. */
10261 /* This field provides original sequence number of the command. */
10264 * This field is the length of the response in bytes. The last byte of
10265 * the response is a valid flag that will read as '1' when the command
10266 * has been completely written to memory.
10268 uint64_t lpbk_ucast_frames;
10269 /* Number of transmitted unicast frames */
10270 uint64_t lpbk_mcast_frames;
10271 /* Number of transmitted multicast frames */
10272 uint64_t lpbk_bcast_frames;
10273 /* Number of transmitted broadcast frames */
10274 uint64_t lpbk_ucast_bytes;
10275 /* Number of transmitted bytes for unicast traffic */
10276 uint64_t lpbk_mcast_bytes;
10277 /* Number of transmitted bytes for multicast traffic */
10278 uint64_t lpbk_bcast_bytes;
10279 /* Number of transmitted bytes for broadcast traffic */
10280 uint64_t tx_stat_discard;
10281 /* Total Tx Drops for loopback traffic reported by STATS block */
10282 uint64_t tx_stat_error;
10283 /* Total Tx Error Drops for loopback traffic reported by STATS block */
10284 uint64_t rx_stat_discard;
10285 /* Total Rx Drops for loopback traffic reported by STATS block */
10286 uint64_t rx_stat_error;
10287 /* Total Rx Error Drops for loopback traffic reported by STATS block */
10294 * This field is used in Output records to indicate that the output is
10295 * completely written to RAM. This field should be read as '1' to
10296 * indicate that the output has been completely written. When writing a
10297 * command completion or response to an internal processor, the order of
10298 * writes has to be such that this field is written last.
10300 } __attribute__((packed));
10302 /* hwrm_port_clr_stats */
10304 * Description: This function clears per port statistics. The HWRM shall not
10305 * allow a VF driver to clear port statistics. The HWRM shall not allow a PF
10306 * driver to clear port statistics in a partitioning mode. The HWRM may allow a
10307 * PF driver to clear port statistics in the non-partitioning mode.
10309 /* Input (24 bytes) */
10311 struct hwrm_port_clr_stats_input {
10314 * This value indicates what type of request this is. The format for the
10315 * rest of the command is determined by this field.
10317 uint16_t cmpl_ring;
10319 * This value indicates the what completion ring the request will be
10320 * optionally completed on. If the value is -1, then no CR completion
10321 * will be generated. Any other value must be a valid CR ring_id value
10322 * for this function.
10325 /* This value indicates the command sequence number. */
10326 uint16_t target_id;
10328 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
10329 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
10331 uint64_t resp_addr;
10333 * This is the host address where the response will be written when the
10334 * request is complete. This area must be 16B aligned and must be
10335 * cleared to zero before the request is made.
10338 /* Port ID of port that is being queried. */
10339 uint16_t unused_0[3];
10340 } __attribute__((packed));
10342 /* Output (16 bytes) */
10344 struct hwrm_port_clr_stats_output {
10345 uint16_t error_code;
10347 * Pass/Fail or error type Note: receiver to verify the in parameters,
10348 * and fail the call with an error when appropriate
10351 /* This field returns the type of original request. */
10353 /* This field provides original sequence number of the command. */
10356 * This field is the length of the response in bytes. The last byte of
10357 * the response is a valid flag that will read as '1' when the command
10358 * has been completely written to memory.
10366 * This field is used in Output records to indicate that the output is
10367 * completely written to RAM. This field should be read as '1' to
10368 * indicate that the output has been completely written. When writing a
10369 * command completion or response to an internal processor, the order of
10370 * writes has to be such that this field is written last.
10372 } __attribute__((packed));
10374 /* hwrm_port_lpbk_clr_stats */
10376 * Description: This function clears loopback statistics. The HWRM shall not
10377 * allow a VF driver to clear loopback statistics. The HWRM shall not allow a PF
10378 * driver to clear loopback statistics in a partitioning mode. The HWRM may
10379 * allow a PF driver to clear loopback statistics in the non-partitioning mode.
10381 /* Input (16 bytes) */
10383 struct hwrm_port_lpbk_clr_stats_input {
10386 * This value indicates what type of request this is. The format for the
10387 * rest of the command is determined by this field.
10389 uint16_t cmpl_ring;
10391 * This value indicates the what completion ring the request will be
10392 * optionally completed on. If the value is -1, then no CR completion
10393 * will be generated. Any other value must be a valid CR ring_id value
10394 * for this function.
10397 /* This value indicates the command sequence number. */
10398 uint16_t target_id;
10400 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
10401 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
10403 uint64_t resp_addr;
10405 * This is the host address where the response will be written when the
10406 * request is complete. This area must be 16B aligned and must be
10407 * cleared to zero before the request is made.
10409 } __attribute__((packed));
10411 /* Output (16 bytes) */
10413 struct hwrm_port_lpbk_clr_stats_output {
10414 uint16_t error_code;
10416 * Pass/Fail or error type Note: receiver to verify the in parameters,
10417 * and fail the call with an error when appropriate
10420 /* This field returns the type of original request. */
10422 /* This field provides original sequence number of the command. */
10425 * This field is the length of the response in bytes. The last byte of
10426 * the response is a valid flag that will read as '1' when the command
10427 * has been completely written to memory.
10435 * This field is used in Output records to indicate that the output is
10436 * completely written to RAM. This field should be read as '1' to
10437 * indicate that the output has been completely written. When writing a
10438 * command completion or response to an internal processor, the order of
10439 * writes has to be such that this field is written last.
10441 } __attribute__((packed));
10443 /* hwrm_port_ts_query */
10445 * Description: This function is used to read timestamp information captured for
10446 * PTP messages on this port.
10448 /* Input (24 bytes) */
10450 struct hwrm_port_ts_query_input {
10453 * This value indicates what type of request this is. The format for the
10454 * rest of the command is determined by this field.
10456 uint16_t cmpl_ring;
10458 * This value indicates the what completion ring the request will be
10459 * optionally completed on. If the value is -1, then no CR completion
10460 * will be generated. Any other value must be a valid CR ring_id value
10461 * for this function.
10464 /* This value indicates the command sequence number. */
10465 uint16_t target_id;
10467 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
10468 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
10470 uint64_t resp_addr;
10472 * This is the host address where the response will be written when the
10473 * request is complete. This area must be 16B aligned and must be
10474 * cleared to zero before the request is made.
10478 * Enumeration denoting the RX, TX type of the resource. This
10479 * enumeration is used for resources that are similar for both TX and RX
10480 * paths of the chip.
10482 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH UINT32_C(0x1)
10484 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
10486 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
10487 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX
10489 /* Port ID of port that is being queried. */
10491 } __attribute__((packed));
10493 /* Output (24 bytes) */
10495 struct hwrm_port_ts_query_output {
10496 uint16_t error_code;
10498 * Pass/Fail or error type Note: receiver to verify the in parameters,
10499 * and fail the call with an error when appropriate
10502 /* This field returns the type of original request. */
10504 /* This field provides original sequence number of the command. */
10507 * This field is the length of the response in bytes. The last byte of
10508 * the response is a valid flag that will read as '1' when the command
10509 * has been completely written to memory.
10511 uint64_t ptp_msg_ts;
10512 /* Timestamp value of PTP message captured. */
10513 uint16_t ptp_msg_seqid;
10514 /* Sequence ID of the PTP message captured. */
10522 * This field is used in Output records to indicate that the output is
10523 * completely written to RAM. This field should be read as '1' to
10524 * indicate that the output has been completely written. When writing a
10525 * command completion or response to an internal processor, the order of
10526 * writes has to be such that this field is written last.
10528 } __attribute__((packed));
10530 /* hwrm_port_phy_qcaps */
10532 * Description: This function is used to query the current capabilities of PHY
10535 /* Input (24 bytes) */
10537 struct hwrm_port_phy_qcaps_input {
10540 * This value indicates what type of request this is. The format for the
10541 * rest of the command is determined by this field.
10543 uint16_t cmpl_ring;
10545 * This value indicates the what completion ring the request will be
10546 * optionally completed on. If the value is -1, then no CR completion
10547 * will be generated. Any other value must be a valid CR ring_id value
10548 * for this function.
10551 /* This value indicates the command sequence number. */
10552 uint16_t target_id;
10554 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
10555 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
10557 uint64_t resp_addr;
10559 * This is the host address where the response will be written when the
10560 * request is complete. This area must be 16B aligned and must be
10561 * cleared to zero before the request is made.
10564 /* Port ID of port that is being queried. */
10565 uint16_t unused_0[3];
10566 } __attribute__((packed));
10568 /* Output (24 bytes) */
10570 struct hwrm_port_phy_qcaps_output {
10571 uint16_t error_code;
10573 * Pass/Fail or error type Note: receiver to verify the in parameters,
10574 * and fail the call with an error when appropriate
10577 /* This field returns the type of original request. */
10579 /* This field provides original sequence number of the command. */
10582 * This field is the length of the response in bytes. The last byte of
10583 * the response is a valid flag that will read as '1' when the command
10584 * has been completely written to memory.
10587 /* PHY capability flags */
10589 * If set to 1, then this field indicates that the link is capable of
10592 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED UINT32_C(0x1)
10594 * Reserved field. The HWRM shall set this field to 0. An HWRM client
10595 * shall ignore this field.
10597 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK UINT32_C(0xfe)
10598 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 1
10600 /* Number of front panel ports for this device. */
10601 /* Not supported or unknown */
10602 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
10603 /* single port device */
10604 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
10605 /* 2-port device */
10606 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
10607 /* 3-port device */
10608 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
10609 /* 4-port device */
10610 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
10611 uint16_t supported_speeds_force_mode;
10613 * This is a bit mask to indicate what speeds are supported as forced
10614 * speeds on this link. For each speed that can be forced on this link,
10615 * the corresponding mask bit shall be set to '1'.
10617 /* 100Mb link speed (Half-duplex) */
10618 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD UINT32_C(0x1)
10619 /* 100Mb link speed (Full-duplex) */
10620 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB UINT32_C(0x2)
10621 /* 1Gb link speed (Half-duplex) */
10622 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD UINT32_C(0x4)
10623 /* 1Gb link speed (Full-duplex) */
10624 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB UINT32_C(0x8)
10625 /* 2Gb link speed */
10626 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB UINT32_C(0x10)
10627 /* 2.5Gb link speed */
10628 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB UINT32_C(0x20)
10629 /* 10Gb link speed */
10630 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB UINT32_C(0x40)
10631 /* 20Gb link speed */
10632 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB UINT32_C(0x80)
10633 /* 25Gb link speed */
10634 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB UINT32_C(0x100)
10635 /* 40Gb link speed */
10636 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB UINT32_C(0x200)
10637 /* 50Gb link speed */
10638 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB UINT32_C(0x400)
10639 /* 100Gb link speed */
10640 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB UINT32_C(0x800)
10641 /* 10Mb link speed (Half-duplex) */
10642 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD UINT32_C(0x1000)
10643 /* 10Mb link speed (Full-duplex) */
10644 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB UINT32_C(0x2000)
10645 uint16_t supported_speeds_auto_mode;
10647 * This is a bit mask to indicate what speeds are supported for
10648 * autonegotiation on this link. For each speed that can be
10649 * autonegotiated on this link, the corresponding mask bit shall be set
10652 /* 100Mb link speed (Half-duplex) */
10653 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD UINT32_C(0x1)
10654 /* 100Mb link speed (Full-duplex) */
10655 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB UINT32_C(0x2)
10656 /* 1Gb link speed (Half-duplex) */
10657 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD UINT32_C(0x4)
10658 /* 1Gb link speed (Full-duplex) */
10659 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB UINT32_C(0x8)
10660 /* 2Gb link speed */
10661 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB UINT32_C(0x10)
10662 /* 2.5Gb link speed */
10663 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB UINT32_C(0x20)
10664 /* 10Gb link speed */
10665 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB UINT32_C(0x40)
10666 /* 20Gb link speed */
10667 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB UINT32_C(0x80)
10668 /* 25Gb link speed */
10669 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB UINT32_C(0x100)
10670 /* 40Gb link speed */
10671 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB UINT32_C(0x200)
10672 /* 50Gb link speed */
10673 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB UINT32_C(0x400)
10674 /* 100Gb link speed */
10675 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB UINT32_C(0x800)
10676 /* 10Mb link speed (Half-duplex) */
10677 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD UINT32_C(0x1000)
10678 /* 10Mb link speed (Full-duplex) */
10679 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB UINT32_C(0x2000)
10680 uint16_t supported_speeds_eee_mode;
10682 * This is a bit mask to indicate what speeds are supported for EEE on
10683 * this link. For each speed that can be autonegotiated when EEE is
10684 * enabled on this link, the corresponding mask bit shall be set to '1'.
10685 * This field is only valid when the eee_suppotred is set to '1'.
10688 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 UINT32_C(0x1)
10689 /* 100Mb link speed (Full-duplex) */
10690 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB UINT32_C(0x2)
10692 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 UINT32_C(0x4)
10693 /* 1Gb link speed (Full-duplex) */
10694 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB UINT32_C(0x8)
10696 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 UINT32_C(0x10)
10698 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 UINT32_C(0x20)
10699 /* 10Gb link speed */
10700 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB UINT32_C(0x40)
10701 uint32_t tx_lpi_timer_low;
10703 * Reserved field. The HWRM shall set this field to 0. An HWRM client
10704 * shall ignore this field.
10707 * The lowest value of TX LPI timer that can be set on this link when
10708 * EEE is enabled. This value is in microseconds. This field is valid
10709 * only when_eee_supported is set to '1'.
10711 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK UINT32_C(0xffffff)
10712 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
10714 * Reserved field. The HWRM shall set this field to 0. An HWRM client
10715 * shall ignore this field.
10717 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK UINT32_C(0xff000000)
10718 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24
10719 uint32_t valid_tx_lpi_timer_high;
10721 * This field is used in Output records to indicate that the output is
10722 * completely written to RAM. This field should be read as '1' to
10723 * indicate that the output has been completely written. When writing a
10724 * command completion or response to an internal processor, the order of
10725 * writes has to be such that this field is written last.
10728 * The highest value of TX LPI timer that can be set on this link when
10729 * EEE is enabled. This value is in microseconds. This field is valid
10730 * only when_eee_supported is set to '1'.
10732 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK UINT32_C(0xffffff)
10733 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
10735 * This field is used in Output records to indicate that the output is
10736 * completely written to RAM. This field should be read as '1' to
10737 * indicate that the output has been completely written. When writing a
10738 * command completion or response to an internal processor, the order of
10739 * writes has to be such that this field is written last.
10741 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK UINT32_C(0xff000000)
10742 #define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
10743 } __attribute__((packed));
10745 /* hwrm_port_led_cfg */
10747 * Description: This function is used to configure LEDs on a given port. Each
10748 * port has individual set of LEDs associated with it. These LEDs are used for
10749 * speed/link configuration as well as activity indicator configuration. Up to
10750 * three LEDs can be configured, one for activity and two for speeds.
10752 /* Input (64 bytes) */
10754 struct hwrm_port_led_cfg_input {
10757 * This value indicates what type of request this is. The format for the
10758 * rest of the command is determined by this field.
10760 uint16_t cmpl_ring;
10762 * This value indicates the what completion ring the request will be
10763 * optionally completed on. If the value is -1, then no CR completion
10764 * will be generated. Any other value must be a valid CR ring_id value
10765 * for this function.
10768 /* This value indicates the command sequence number. */
10769 uint16_t target_id;
10771 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
10772 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
10774 uint64_t resp_addr;
10776 * This is the host address where the response will be written when the
10777 * request is complete. This area must be 16B aligned and must be
10778 * cleared to zero before the request is made.
10781 /* This bit must be '1' for the led0_id field to be configured. */
10782 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID UINT32_C(0x1)
10783 /* This bit must be '1' for the led0_state field to be configured. */
10784 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE UINT32_C(0x2)
10785 /* This bit must be '1' for the led0_color field to be configured. */
10786 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR UINT32_C(0x4)
10787 /* This bit must be '1' for the led0_blink_on field to be configured. */
10788 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON UINT32_C(0x8)
10789 /* This bit must be '1' for the led0_blink_off field to be configured. */
10790 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF UINT32_C(0x10)
10791 /* This bit must be '1' for the led0_group_id field to be configured. */
10792 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID UINT32_C(0x20)
10793 /* This bit must be '1' for the led1_id field to be configured. */
10794 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID UINT32_C(0x40)
10795 /* This bit must be '1' for the led1_state field to be configured. */
10796 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE UINT32_C(0x80)
10797 /* This bit must be '1' for the led1_color field to be configured. */
10798 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR UINT32_C(0x100)
10799 /* This bit must be '1' for the led1_blink_on field to be configured. */
10800 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON UINT32_C(0x200)
10801 /* This bit must be '1' for the led1_blink_off field to be configured. */
10802 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF UINT32_C(0x400)
10803 /* This bit must be '1' for the led1_group_id field to be configured. */
10804 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID UINT32_C(0x800)
10805 /* This bit must be '1' for the led2_id field to be configured. */
10806 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID UINT32_C(0x1000)
10807 /* This bit must be '1' for the led2_state field to be configured. */
10808 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE UINT32_C(0x2000)
10809 /* This bit must be '1' for the led2_color field to be configured. */
10810 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR UINT32_C(0x4000)
10811 /* This bit must be '1' for the led2_blink_on field to be configured. */
10812 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON UINT32_C(0x8000)
10813 /* This bit must be '1' for the led2_blink_off field to be configured. */
10814 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF UINT32_C(0x10000)
10815 /* This bit must be '1' for the led2_group_id field to be configured. */
10816 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID UINT32_C(0x20000)
10817 /* This bit must be '1' for the led3_id field to be configured. */
10818 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID UINT32_C(0x40000)
10819 /* This bit must be '1' for the led3_state field to be configured. */
10820 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE UINT32_C(0x80000)
10821 /* This bit must be '1' for the led3_color field to be configured. */
10822 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR UINT32_C(0x100000)
10823 /* This bit must be '1' for the led3_blink_on field to be configured. */
10824 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON UINT32_C(0x200000)
10825 /* This bit must be '1' for the led3_blink_off field to be configured. */
10826 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF UINT32_C(0x400000)
10827 /* This bit must be '1' for the led3_group_id field to be configured. */
10828 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID UINT32_C(0x800000)
10830 /* Port ID of port whose LEDs are configured. */
10833 * The number of LEDs that are being configured. Up to 4 LEDs can be
10834 * configured with this command.
10837 /* Reserved field. */
10839 /* An identifier for the LED #0. */
10840 uint8_t led0_state;
10841 /* The requested state of the LED #0. */
10842 /* Default state of the LED */
10843 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
10845 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
10847 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
10849 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
10850 /* Blink Alternately */
10851 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
10852 uint8_t led0_color;
10853 /* The requested color of LED #0. */
10855 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
10857 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
10859 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
10860 /* Green or Amber */
10861 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
10863 uint16_t led0_blink_on;
10865 * If the LED #0 state is "blink" or "blinkalt", then this field
10866 * represents the requested time in milliseconds to keep LED on between
10869 uint16_t led0_blink_off;
10871 * If the LED #0 state is "blink" or "blinkalt", then this field
10872 * represents the requested time in milliseconds to keep LED off between
10875 uint8_t led0_group_id;
10877 * An identifier for the group of LEDs that LED #0 belongs to. If set to
10878 * 0, then the LED #0 shall not be grouped and shall be treated as an
10879 * individual resource. For all other non-zero values of this field, LED
10880 * #0 shall be grouped together with the LEDs with the same group ID
10884 /* Reserved field. */
10886 /* An identifier for the LED #1. */
10887 uint8_t led1_state;
10888 /* The requested state of the LED #1. */
10889 /* Default state of the LED */
10890 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
10892 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
10894 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
10896 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
10897 /* Blink Alternately */
10898 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
10899 uint8_t led1_color;
10900 /* The requested color of LED #1. */
10902 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
10904 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
10906 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
10907 /* Green or Amber */
10908 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
10910 uint16_t led1_blink_on;
10912 * If the LED #1 state is "blink" or "blinkalt", then this field
10913 * represents the requested time in milliseconds to keep LED on between
10916 uint16_t led1_blink_off;
10918 * If the LED #1 state is "blink" or "blinkalt", then this field
10919 * represents the requested time in milliseconds to keep LED off between
10922 uint8_t led1_group_id;
10924 * An identifier for the group of LEDs that LED #1 belongs to. If set to
10925 * 0, then the LED #1 shall not be grouped and shall be treated as an
10926 * individual resource. For all other non-zero values of this field, LED
10927 * #1 shall be grouped together with the LEDs with the same group ID
10931 /* Reserved field. */
10933 /* An identifier for the LED #2. */
10934 uint8_t led2_state;
10935 /* The requested state of the LED #2. */
10936 /* Default state of the LED */
10937 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
10939 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
10941 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
10943 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
10944 /* Blink Alternately */
10945 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
10946 uint8_t led2_color;
10947 /* The requested color of LED #2. */
10949 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
10951 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
10953 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
10954 /* Green or Amber */
10955 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
10957 uint16_t led2_blink_on;
10959 * If the LED #2 state is "blink" or "blinkalt", then this field
10960 * represents the requested time in milliseconds to keep LED on between
10963 uint16_t led2_blink_off;
10965 * If the LED #2 state is "blink" or "blinkalt", then this field
10966 * represents the requested time in milliseconds to keep LED off between
10969 uint8_t led2_group_id;
10971 * An identifier for the group of LEDs that LED #2 belongs to. If set to
10972 * 0, then the LED #2 shall not be grouped and shall be treated as an
10973 * individual resource. For all other non-zero values of this field, LED
10974 * #2 shall be grouped together with the LEDs with the same group ID
10978 /* Reserved field. */
10980 /* An identifier for the LED #3. */
10981 uint8_t led3_state;
10982 /* The requested state of the LED #3. */
10983 /* Default state of the LED */
10984 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
10986 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
10988 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
10990 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
10991 /* Blink Alternately */
10992 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
10993 uint8_t led3_color;
10994 /* The requested color of LED #3. */
10996 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
10998 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
11000 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
11001 /* Green or Amber */
11002 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
11004 uint16_t led3_blink_on;
11006 * If the LED #3 state is "blink" or "blinkalt", then this field
11007 * represents the requested time in milliseconds to keep LED on between
11010 uint16_t led3_blink_off;
11012 * If the LED #3 state is "blink" or "blinkalt", then this field
11013 * represents the requested time in milliseconds to keep LED off between
11016 uint8_t led3_group_id;
11018 * An identifier for the group of LEDs that LED #3 belongs to. If set to
11019 * 0, then the LED #3 shall not be grouped and shall be treated as an
11020 * individual resource. For all other non-zero values of this field, LED
11021 * #3 shall be grouped together with the LEDs with the same group ID
11025 /* Reserved field. */
11026 } __attribute__((packed));
11028 /* Output (16 bytes) */
11030 struct hwrm_port_led_cfg_output {
11031 uint16_t error_code;
11033 * Pass/Fail or error type Note: receiver to verify the in parameters,
11034 * and fail the call with an error when appropriate
11037 /* This field returns the type of original request. */
11039 /* This field provides original sequence number of the command. */
11042 * This field is the length of the response in bytes. The last byte of
11043 * the response is a valid flag that will read as '1' when the command
11044 * has been completely written to memory.
11052 * This field is used in Output records to indicate that the output is
11053 * completely written to RAM. This field should be read as '1' to
11054 * indicate that the output has been completely written. When writing a
11055 * command completion or response to an internal processor, the order of
11056 * writes has to be such that this field is written last.
11058 } __attribute__((packed));
11060 /* hwrm_port_led_qcfg */
11062 * Description: This function is used to query configuration of LEDs on a given
11063 * port. Each port has individual set of LEDs associated with it. These LEDs are
11064 * used for speed/link configuration as well as activity indicator
11065 * configuration. Up to three LEDs can be configured, one for activity and two
11068 /* Input (24 bytes) */
11070 struct hwrm_port_led_qcfg_input {
11073 * This value indicates what type of request this is. The format for the
11074 * rest of the command is determined by this field.
11076 uint16_t cmpl_ring;
11078 * This value indicates the what completion ring the request will be
11079 * optionally completed on. If the value is -1, then no CR completion
11080 * will be generated. Any other value must be a valid CR ring_id value
11081 * for this function.
11084 /* This value indicates the command sequence number. */
11085 uint16_t target_id;
11087 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
11088 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
11090 uint64_t resp_addr;
11092 * This is the host address where the response will be written when the
11093 * request is complete. This area must be 16B aligned and must be
11094 * cleared to zero before the request is made.
11097 /* Port ID of port whose LED configuration is being queried. */
11098 uint16_t unused_0[3];
11099 } __attribute__((packed));
11101 /* Output (56 bytes) */
11103 struct hwrm_port_led_qcfg_output {
11104 uint16_t error_code;
11106 * Pass/Fail or error type Note: receiver to verify the in parameters,
11107 * and fail the call with an error when appropriate
11110 /* This field returns the type of original request. */
11112 /* This field provides original sequence number of the command. */
11115 * This field is the length of the response in bytes. The last byte of
11116 * the response is a valid flag that will read as '1' when the command
11117 * has been completely written to memory.
11121 * The number of LEDs that are configured on this port. Up to 4 LEDs can
11122 * be returned in the response.
11125 /* An identifier for the LED #0. */
11127 /* The type of LED #0. */
11129 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
11131 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
11133 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
11134 uint8_t led0_state;
11135 /* The current state of the LED #0. */
11136 /* Default state of the LED */
11137 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
11139 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
11141 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
11143 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
11144 /* Blink Alternately */
11145 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
11146 uint8_t led0_color;
11147 /* The color of LED #0. */
11149 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
11151 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
11153 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
11154 /* Green or Amber */
11155 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
11157 uint16_t led0_blink_on;
11159 * If the LED #0 state is "blink" or "blinkalt", then this field
11160 * represents the requested time in milliseconds to keep LED on between
11163 uint16_t led0_blink_off;
11165 * If the LED #0 state is "blink" or "blinkalt", then this field
11166 * represents the requested time in milliseconds to keep LED off between
11169 uint8_t led0_group_id;
11171 * An identifier for the group of LEDs that LED #0 belongs to. If set to
11172 * 0, then the LED #0 is not grouped. For all other non-zero values of
11173 * this field, LED #0 is grouped together with the LEDs with the same
11177 /* An identifier for the LED #1. */
11179 /* The type of LED #1. */
11181 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
11183 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
11185 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
11186 uint8_t led1_state;
11187 /* The current state of the LED #1. */
11188 /* Default state of the LED */
11189 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
11191 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
11193 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
11195 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
11196 /* Blink Alternately */
11197 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
11198 uint8_t led1_color;
11199 /* The color of LED #1. */
11201 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
11203 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
11205 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
11206 /* Green or Amber */
11207 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
11209 uint16_t led1_blink_on;
11211 * If the LED #1 state is "blink" or "blinkalt", then this field
11212 * represents the requested time in milliseconds to keep LED on between
11215 uint16_t led1_blink_off;
11217 * If the LED #1 state is "blink" or "blinkalt", then this field
11218 * represents the requested time in milliseconds to keep LED off between
11221 uint8_t led1_group_id;
11223 * An identifier for the group of LEDs that LED #1 belongs to. If set to
11224 * 0, then the LED #1 is not grouped. For all other non-zero values of
11225 * this field, LED #1 is grouped together with the LEDs with the same
11229 /* An identifier for the LED #2. */
11231 /* The type of LED #2. */
11233 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
11235 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
11237 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
11238 uint8_t led2_state;
11239 /* The current state of the LED #2. */
11240 /* Default state of the LED */
11241 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
11243 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
11245 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
11247 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
11248 /* Blink Alternately */
11249 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
11250 uint8_t led2_color;
11251 /* The color of LED #2. */
11253 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
11255 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
11257 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
11258 /* Green or Amber */
11259 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
11261 uint16_t led2_blink_on;
11263 * If the LED #2 state is "blink" or "blinkalt", then this field
11264 * represents the requested time in milliseconds to keep LED on between
11267 uint16_t led2_blink_off;
11269 * If the LED #2 state is "blink" or "blinkalt", then this field
11270 * represents the requested time in milliseconds to keep LED off between
11273 uint8_t led2_group_id;
11275 * An identifier for the group of LEDs that LED #2 belongs to. If set to
11276 * 0, then the LED #2 is not grouped. For all other non-zero values of
11277 * this field, LED #2 is grouped together with the LEDs with the same
11281 /* An identifier for the LED #3. */
11283 /* The type of LED #3. */
11285 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
11287 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
11289 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
11290 uint8_t led3_state;
11291 /* The current state of the LED #3. */
11292 /* Default state of the LED */
11293 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
11295 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
11297 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
11299 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
11300 /* Blink Alternately */
11301 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
11302 uint8_t led3_color;
11303 /* The color of LED #3. */
11305 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
11307 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
11309 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
11310 /* Green or Amber */
11311 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
11313 uint16_t led3_blink_on;
11315 * If the LED #3 state is "blink" or "blinkalt", then this field
11316 * represents the requested time in milliseconds to keep LED on between
11319 uint16_t led3_blink_off;
11321 * If the LED #3 state is "blink" or "blinkalt", then this field
11322 * represents the requested time in milliseconds to keep LED off between
11325 uint8_t led3_group_id;
11327 * An identifier for the group of LEDs that LED #3 belongs to. If set to
11328 * 0, then the LED #3 is not grouped. For all other non-zero values of
11329 * this field, LED #3 is grouped together with the LEDs with the same
11339 * This field is used in Output records to indicate that the output is
11340 * completely written to RAM. This field should be read as '1' to
11341 * indicate that the output has been completely written. When writing a
11342 * command completion or response to an internal processor, the order of
11343 * writes has to be such that this field is written last.
11345 } __attribute__((packed));
11347 /* hwrm_port_led_qcaps */
11349 * Description: This function is used to query capabilities of LEDs on a given
11350 * port. Each port has individual set of LEDs associated with it. These LEDs are
11351 * used for speed/link configuration as well as activity indicator
11354 /* Input (24 bytes) */
11356 struct hwrm_port_led_qcaps_input {
11359 * This value indicates what type of request this is. The format for the
11360 * rest of the command is determined by this field.
11362 uint16_t cmpl_ring;
11364 * This value indicates the what completion ring the request will be
11365 * optionally completed on. If the value is -1, then no CR completion
11366 * will be generated. Any other value must be a valid CR ring_id value
11367 * for this function.
11370 /* This value indicates the command sequence number. */
11371 uint16_t target_id;
11373 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
11374 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
11376 uint64_t resp_addr;
11378 * This is the host address where the response will be written when the
11379 * request is complete. This area must be 16B aligned and must be
11380 * cleared to zero before the request is made.
11383 /* Port ID of port whose LED configuration is being queried. */
11384 uint16_t unused_0[3];
11385 } __attribute__((packed));
11387 /* Output (48 bytes) */
11389 struct hwrm_port_led_qcaps_output {
11390 uint16_t error_code;
11392 * Pass/Fail or error type Note: receiver to verify the in parameters,
11393 * and fail the call with an error when appropriate
11396 /* This field returns the type of original request. */
11398 /* This field provides original sequence number of the command. */
11401 * This field is the length of the response in bytes. The last byte of
11402 * the response is a valid flag that will read as '1' when the command
11403 * has been completely written to memory.
11407 * The number of LEDs that are configured on this port. Up to 4 LEDs can
11408 * be returned in the response.
11410 uint8_t unused_0[3];
11411 /* Reserved for future use. */
11413 /* An identifier for the LED #0. */
11415 /* The type of LED #0. */
11417 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
11419 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
11421 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
11422 uint8_t led0_group_id;
11424 * An identifier for the group of LEDs that LED #0 belongs to. If set to
11425 * 0, then the LED #0 cannot be grouped. For all other non-zero values
11426 * of this field, LED #0 is grouped together with the LEDs with the same
11430 uint16_t led0_state_caps;
11431 /* The states supported by LED #0. */
11432 /* If set to 1, this LED is enabled. If set to 0, this LED is disabled. */
11433 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED UINT32_C(0x1)
11435 * If set to 1, off state is supported on this LED. If set to 0, off
11436 * state is not supported on this LED.
11438 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED UINT32_C(0x2)
11440 * If set to 1, on state is supported on this LED. If set to 0, on state
11441 * is not supported on this LED.
11443 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED UINT32_C(0x4)
11445 * If set to 1, blink state is supported on this LED. If set to 0, blink
11446 * state is not supported on this LED.
11448 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED UINT32_C(0x8)
11450 * If set to 1, blink_alt state is supported on this LED. If set to 0,
11451 * blink_alt state is not supported on this LED.
11453 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED UINT32_C(0x10)
11454 uint16_t led0_color_caps;
11455 /* The colors supported by LED #0. */
11457 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD UINT32_C(0x1)
11459 * If set to 1, Amber color is supported on this LED. If set to 0, Amber
11460 * color is not supported on this LED.
11462 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED UINT32_C(0x2)
11464 * If set to 1, Green color is supported on this LED. If set to 0, Green
11465 * color is not supported on this LED.
11467 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED UINT32_C(0x4)
11469 /* An identifier for the LED #1. */
11471 /* The type of LED #1. */
11473 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
11475 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
11477 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
11478 uint8_t led1_group_id;
11480 * An identifier for the group of LEDs that LED #1 belongs to. If set to
11481 * 0, then the LED #0 cannot be grouped. For all other non-zero values
11482 * of this field, LED #0 is grouped together with the LEDs with the same
11486 uint16_t led1_state_caps;
11487 /* The states supported by LED #1. */
11488 /* If set to 1, this LED is enabled. If set to 0, this LED is disabled. */
11489 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED UINT32_C(0x1)
11491 * If set to 1, off state is supported on this LED. If set to 0, off
11492 * state is not supported on this LED.
11494 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED UINT32_C(0x2)
11496 * If set to 1, on state is supported on this LED. If set to 0, on state
11497 * is not supported on this LED.
11499 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED UINT32_C(0x4)
11501 * If set to 1, blink state is supported on this LED. If set to 0, blink
11502 * state is not supported on this LED.
11504 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED UINT32_C(0x8)
11506 * If set to 1, blink_alt state is supported on this LED. If set to 0,
11507 * blink_alt state is not supported on this LED.
11509 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED UINT32_C(0x10)
11510 uint16_t led1_color_caps;
11511 /* The colors supported by LED #1. */
11513 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD UINT32_C(0x1)
11515 * If set to 1, Amber color is supported on this LED. If set to 0, Amber
11516 * color is not supported on this LED.
11518 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED UINT32_C(0x2)
11520 * If set to 1, Green color is supported on this LED. If set to 0, Green
11521 * color is not supported on this LED.
11523 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED UINT32_C(0x4)
11525 /* An identifier for the LED #2. */
11527 /* The type of LED #2. */
11529 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
11531 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
11533 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
11534 uint8_t led2_group_id;
11536 * An identifier for the group of LEDs that LED #0 belongs to. If set to
11537 * 0, then the LED #0 cannot be grouped. For all other non-zero values
11538 * of this field, LED #0 is grouped together with the LEDs with the same
11542 uint16_t led2_state_caps;
11543 /* The states supported by LED #2. */
11544 /* If set to 1, this LED is enabled. If set to 0, this LED is disabled. */
11545 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED UINT32_C(0x1)
11547 * If set to 1, off state is supported on this LED. If set to 0, off
11548 * state is not supported on this LED.
11550 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED UINT32_C(0x2)
11552 * If set to 1, on state is supported on this LED. If set to 0, on state
11553 * is not supported on this LED.
11555 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED UINT32_C(0x4)
11557 * If set to 1, blink state is supported on this LED. If set to 0, blink
11558 * state is not supported on this LED.
11560 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED UINT32_C(0x8)
11562 * If set to 1, blink_alt state is supported on this LED. If set to 0,
11563 * blink_alt state is not supported on this LED.
11565 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED UINT32_C(0x10)
11566 uint16_t led2_color_caps;
11567 /* The colors supported by LED #2. */
11569 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD UINT32_C(0x1)
11571 * If set to 1, Amber color is supported on this LED. If set to 0, Amber
11572 * color is not supported on this LED.
11574 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED UINT32_C(0x2)
11576 * If set to 1, Green color is supported on this LED. If set to 0, Green
11577 * color is not supported on this LED.
11579 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED UINT32_C(0x4)
11581 /* An identifier for the LED #3. */
11583 /* The type of LED #3. */
11585 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
11587 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
11589 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
11590 uint8_t led3_group_id;
11592 * An identifier for the group of LEDs that LED #3 belongs to. If set to
11593 * 0, then the LED #0 cannot be grouped. For all other non-zero values
11594 * of this field, LED #0 is grouped together with the LEDs with the same
11598 uint16_t led3_state_caps;
11599 /* The states supported by LED #3. */
11600 /* If set to 1, this LED is enabled. If set to 0, this LED is disabled. */
11601 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED UINT32_C(0x1)
11603 * If set to 1, off state is supported on this LED. If set to 0, off
11604 * state is not supported on this LED.
11606 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED UINT32_C(0x2)
11608 * If set to 1, on state is supported on this LED. If set to 0, on state
11609 * is not supported on this LED.
11611 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED UINT32_C(0x4)
11613 * If set to 1, blink state is supported on this LED. If set to 0, blink
11614 * state is not supported on this LED.
11616 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED UINT32_C(0x8)
11618 * If set to 1, blink_alt state is supported on this LED. If set to 0,
11619 * blink_alt state is not supported on this LED.
11621 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED UINT32_C(0x10)
11622 uint16_t led3_color_caps;
11623 /* The colors supported by LED #3. */
11625 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD UINT32_C(0x1)
11627 * If set to 1, Amber color is supported on this LED. If set to 0, Amber
11628 * color is not supported on this LED.
11630 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED UINT32_C(0x2)
11632 * If set to 1, Green color is supported on this LED. If set to 0, Green
11633 * color is not supported on this LED.
11635 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED UINT32_C(0x4)
11641 * This field is used in Output records to indicate that the output is
11642 * completely written to RAM. This field should be read as '1' to
11643 * indicate that the output has been completely written. When writing a
11644 * command completion or response to an internal processor, the order of
11645 * writes has to be such that this field is written last.
11647 } __attribute__((packed));
11649 /* hwrm_queue_qportcfg */
11651 * Description: This function is called by a driver to query queue configuration
11652 * of a port. # The HWRM shall at least advertise one queue with lossy service
11653 * profile. # The driver shall use this command to query queue ids before
11654 * configuring or using any queues. # If a service profile is not set for a
11655 * queue, then the driver shall not use that queue without configuring a service
11656 * profile for it. # If the driver is not allowed to configure service profiles,
11657 * then the driver shall only use queues for which service profiles are pre-
11660 /* Input (24 bytes) */
11662 struct hwrm_queue_qportcfg_input {
11665 * This value indicates what type of request this is. The format for the
11666 * rest of the command is determined by this field.
11668 uint16_t cmpl_ring;
11670 * This value indicates the what completion ring the request will be
11671 * optionally completed on. If the value is -1, then no CR completion
11672 * will be generated. Any other value must be a valid CR ring_id value
11673 * for this function.
11676 /* This value indicates the command sequence number. */
11677 uint16_t target_id;
11679 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
11680 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
11682 uint64_t resp_addr;
11684 * This is the host address where the response will be written when the
11685 * request is complete. This area must be 16B aligned and must be
11686 * cleared to zero before the request is made.
11690 * Enumeration denoting the RX, TX type of the resource. This
11691 * enumeration is used for resources that are similar for both TX and RX
11692 * paths of the chip.
11694 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
11696 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
11698 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
11699 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX
11702 * Port ID of port for which the queue configuration is being queried.
11703 * This field is only required when sent by IPC.
11706 } __attribute__((packed));
11708 /* Output (32 bytes) */
11710 struct hwrm_queue_qportcfg_output {
11711 uint16_t error_code;
11713 * Pass/Fail or error type Note: receiver to verify the in parameters,
11714 * and fail the call with an error when appropriate
11717 /* This field returns the type of original request. */
11719 /* This field provides original sequence number of the command. */
11722 * This field is the length of the response in bytes. The last byte of
11723 * the response is a valid flag that will read as '1' when the command
11724 * has been completely written to memory.
11726 uint8_t max_configurable_queues;
11728 * The maximum number of queues that can be configured on this port.
11729 * Valid values range from 1 through 8.
11731 uint8_t max_configurable_lossless_queues;
11733 * The maximum number of lossless queues that can be configured on this
11734 * port. Valid values range from 0 through 8.
11736 uint8_t queue_cfg_allowed;
11738 * Bitmask indicating which queues can be configured by the
11739 * hwrm_queue_cfg command. Each bit represents a specific queue where
11740 * bit 0 represents queue 0 and bit 7 represents queue 7. # A value of 0
11741 * indicates that the queue is not configurable by the hwrm_queue_cfg
11742 * command. # A value of 1 indicates that the queue is configurable. # A
11743 * hwrm_queue_cfg command shall return error when trying to configure a
11744 * queue not configurable.
11746 uint8_t queue_cfg_info;
11747 /* Information about queue configuration. */
11749 * If this flag is set to '1', then the queues are configured
11750 * asymmetrically on TX and RX sides. If this flag is set to '0', then
11751 * the queues are configured symmetrically on TX and RX sides. For
11752 * symmetric configuration, the queue configuration including queue ids
11753 * and service profiles on the TX side is the same as the corresponding
11754 * queue configuration on the RX side.
11756 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG UINT32_C(0x1)
11757 uint8_t queue_pfcenable_cfg_allowed;
11759 * Bitmask indicating which queues can be configured by the
11760 * hwrm_queue_pfcenable_cfg command. Each bit represents a specific
11761 * priority where bit 0 represents priority 0 and bit 7 represents
11762 * priority 7. # A value of 0 indicates that the priority is not
11763 * configurable by the hwrm_queue_pfcenable_cfg command. # A value of 1
11764 * indicates that the priority is configurable. # A
11765 * hwrm_queue_pfcenable_cfg command shall return error when trying to
11766 * configure a priority that is not configurable.
11768 uint8_t queue_pri2cos_cfg_allowed;
11770 * Bitmask indicating which queues can be configured by the
11771 * hwrm_queue_pri2cos_cfg command. Each bit represents a specific queue
11772 * where bit 0 represents queue 0 and bit 7 represents queue 7. # A
11773 * value of 0 indicates that the queue is not configurable by the
11774 * hwrm_queue_pri2cos_cfg command. # A value of 1 indicates that the
11775 * queue is configurable. # A hwrm_queue_pri2cos_cfg command shall
11776 * return error when trying to configure a queue that is not
11779 uint8_t queue_cos2bw_cfg_allowed;
11781 * Bitmask indicating which queues can be configured by the
11782 * hwrm_queue_pri2cos_cfg command. Each bit represents a specific queue
11783 * where bit 0 represents queue 0 and bit 7 represents queue 7. # A
11784 * value of 0 indicates that the queue is not configurable by the
11785 * hwrm_queue_pri2cos_cfg command. # A value of 1 indicates that the
11786 * queue is configurable. # A hwrm_queue_pri2cos_cfg command shall
11787 * return error when trying to configure a queue not configurable.
11791 * ID of CoS Queue 0. FF - Invalid id # This ID can be used on any
11792 * subsequent call to an hwrm command that takes a queue id. # IDs must
11793 * always be queried by this command before any use by the driver or
11794 * software. # Any driver or software should not make any assumptions
11795 * about queue IDs. # A value of 0xff indicates that the queue is not
11796 * available. # Available queues may not be in sequential order.
11798 uint8_t queue_id0_service_profile;
11799 /* This value is applicable to CoS queues only. */
11800 /* Lossy (best-effort) */
11801 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
11803 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
11804 /* Set to 0xFF... (All Fs) if there is no service profile specified */
11805 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
11808 * ID of CoS Queue 1. FF - Invalid id # This ID can be used on any
11809 * subsequent call to an hwrm command that takes a queue id. # IDs must
11810 * always be queried by this command before any use by the driver or
11811 * software. # Any driver or software should not make any assumptions
11812 * about queue IDs. # A value of 0xff indicates that the queue is not
11813 * available. # Available queues may not be in sequential order.
11815 uint8_t queue_id1_service_profile;
11816 /* This value is applicable to CoS queues only. */
11817 /* Lossy (best-effort) */
11818 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
11820 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
11821 /* Set to 0xFF... (All Fs) if there is no service profile specified */
11822 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
11825 * ID of CoS Queue 2. FF - Invalid id # This ID can be used on any
11826 * subsequent call to an hwrm command that takes a queue id. # IDs must
11827 * always be queried by this command before any use by the driver or
11828 * software. # Any driver or software should not make any assumptions
11829 * about queue IDs. # A value of 0xff indicates that the queue is not
11830 * available. # Available queues may not be in sequential order.
11832 uint8_t queue_id2_service_profile;
11833 /* This value is applicable to CoS queues only. */
11834 /* Lossy (best-effort) */
11835 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
11837 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
11838 /* Set to 0xFF... (All Fs) if there is no service profile specified */
11839 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
11842 * ID of CoS Queue 3. FF - Invalid id # This ID can be used on any
11843 * subsequent call to an hwrm command that takes a queue id. # IDs must
11844 * always be queried by this command before any use by the driver or
11845 * software. # Any driver or software should not make any assumptions
11846 * about queue IDs. # A value of 0xff indicates that the queue is not
11847 * available. # Available queues may not be in sequential order.
11849 uint8_t queue_id3_service_profile;
11850 /* This value is applicable to CoS queues only. */
11851 /* Lossy (best-effort) */
11852 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
11854 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
11855 /* Set to 0xFF... (All Fs) if there is no service profile specified */
11856 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
11859 * ID of CoS Queue 4. FF - Invalid id # This ID can be used on any
11860 * subsequent call to an hwrm command that takes a queue id. # IDs must
11861 * always be queried by this command before any use by the driver or
11862 * software. # Any driver or software should not make any assumptions
11863 * about queue IDs. # A value of 0xff indicates that the queue is not
11864 * available. # Available queues may not be in sequential order.
11866 uint8_t queue_id4_service_profile;
11867 /* This value is applicable to CoS queues only. */
11868 /* Lossy (best-effort) */
11869 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
11871 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
11872 /* Set to 0xFF... (All Fs) if there is no service profile specified */
11873 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
11876 * ID of CoS Queue 5. FF - Invalid id # This ID can be used on any
11877 * subsequent call to an hwrm command that takes a queue id. # IDs must
11878 * always be queried by this command before any use by the driver or
11879 * software. # Any driver or software should not make any assumptions
11880 * about queue IDs. # A value of 0xff indicates that the queue is not
11881 * available. # Available queues may not be in sequential order.
11883 uint8_t queue_id5_service_profile;
11884 /* This value is applicable to CoS queues only. */
11885 /* Lossy (best-effort) */
11886 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
11888 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
11889 /* Set to 0xFF... (All Fs) if there is no service profile specified */
11890 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
11893 * ID of CoS Queue 6. FF - Invalid id # This ID can be used on any
11894 * subsequent call to an hwrm command that takes a queue id. # IDs must
11895 * always be queried by this command before any use by the driver or
11896 * software. # Any driver or software should not make any assumptions
11897 * about queue IDs. # A value of 0xff indicates that the queue is not
11898 * available. # Available queues may not be in sequential order.
11900 uint8_t queue_id6_service_profile;
11901 /* This value is applicable to CoS queues only. */
11902 /* Lossy (best-effort) */
11903 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
11905 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
11906 /* Set to 0xFF... (All Fs) if there is no service profile specified */
11907 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
11910 * ID of CoS Queue 7. FF - Invalid id # This ID can be used on any
11911 * subsequent call to an hwrm command that takes a queue id. # IDs must
11912 * always be queried by this command before any use by the driver or
11913 * software. # Any driver or software should not make any assumptions
11914 * about queue IDs. # A value of 0xff indicates that the queue is not
11915 * available. # Available queues may not be in sequential order.
11917 uint8_t queue_id7_service_profile;
11918 /* This value is applicable to CoS queues only. */
11919 /* Lossy (best-effort) */
11920 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
11922 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
11923 /* Set to 0xFF... (All Fs) if there is no service profile specified */
11924 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
11927 * This field is used in Output records to indicate that the output is
11928 * completely written to RAM. This field should be read as '1' to
11929 * indicate that the output has been completely written. When writing a
11930 * command completion or response to an internal processor, the order of
11931 * writes has to be such that this field is written last.
11933 } __attribute__((packed));
11935 /* hwrm_queue_qcfg */
11937 * Description: This function is called by a driver to query a queue
11940 /* Input (24 bytes) */
11942 struct hwrm_queue_qcfg_input {
11945 * This value indicates what type of request this is. The format for the
11946 * rest of the command is determined by this field.
11948 uint16_t cmpl_ring;
11950 * This value indicates the what completion ring the request will be
11951 * optionally completed on. If the value is -1, then no CR completion
11952 * will be generated. Any other value must be a valid CR ring_id value
11953 * for this function.
11956 /* This value indicates the command sequence number. */
11957 uint16_t target_id;
11959 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
11960 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
11962 uint64_t resp_addr;
11964 * This is the host address where the response will be written when the
11965 * request is complete. This area must be 16B aligned and must be
11966 * cleared to zero before the request is made.
11970 * Enumeration denoting the RX, TX type of the resource. This
11971 * enumeration is used for resources that are similar for both TX and RX
11972 * paths of the chip.
11974 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
11976 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
11978 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
11979 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX
11981 /* Queue ID of the queue. */
11982 } __attribute__((packed));
11984 /* Output (16 bytes) */
11986 struct hwrm_queue_qcfg_output {
11987 uint16_t error_code;
11989 * Pass/Fail or error type Note: receiver to verify the in parameters,
11990 * and fail the call with an error when appropriate
11993 /* This field returns the type of original request. */
11995 /* This field provides original sequence number of the command. */
11998 * This field is the length of the response in bytes. The last byte of
11999 * the response is a valid flag that will read as '1' when the command
12000 * has been completely written to memory.
12002 uint32_t queue_len;
12003 /* This value is a the estimate packet length used in the TX arbiter. */
12004 uint8_t service_profile;
12005 /* This value is applicable to CoS queues only. */
12006 /* Lossy (best-effort) */
12007 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
12009 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
12010 /* Set to 0xFF... (All Fs) if there is no service profile specified */
12011 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
12012 uint8_t queue_cfg_info;
12013 /* Information about queue configuration. */
12015 * If this flag is set to '1', then the queue is configured
12016 * asymmetrically on TX and RX sides. If this flag is set to '0', then
12017 * this queue is configured symmetrically on TX and RX sides.
12019 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG UINT32_C(0x1)
12023 * This field is used in Output records to indicate that the output is
12024 * completely written to RAM. This field should be read as '1' to
12025 * indicate that the output has been completely written. When writing a
12026 * command completion or response to an internal processor, the order of
12027 * writes has to be such that this field is written last.
12029 } __attribute__((packed));
12031 /* hwrm_queue_cfg */
12032 /* Description: This function is called by a driver to configure a queue. */
12033 /* Input (40 bytes) */
12035 struct hwrm_queue_cfg_input {
12038 * This value indicates what type of request this is. The format for the
12039 * rest of the command is determined by this field.
12041 uint16_t cmpl_ring;
12043 * This value indicates the what completion ring the request will be
12044 * optionally completed on. If the value is -1, then no CR completion
12045 * will be generated. Any other value must be a valid CR ring_id value
12046 * for this function.
12049 /* This value indicates the command sequence number. */
12050 uint16_t target_id;
12052 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
12053 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
12055 uint64_t resp_addr;
12057 * This is the host address where the response will be written when the
12058 * request is complete. This area must be 16B aligned and must be
12059 * cleared to zero before the request is made.
12063 * Enumeration denoting the RX, TX, or both directions applicable to the
12064 * resource. This enumeration is used for resources that are similar for
12065 * both TX and RX paths of the chip.
12067 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
12068 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
12070 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
12072 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
12073 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
12074 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
12075 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR
12077 /* This bit must be '1' for the dflt_len field to be configured. */
12078 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
12079 /* This bit must be '1' for the service_profile field to be configured. */
12080 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
12082 /* Queue ID of queue that is to be configured by this function. */
12085 * This value is a the estimate packet length used in the TX arbiter.
12086 * Set to 0xFF... (All Fs) to not adjust this value.
12088 uint8_t service_profile;
12089 /* This value is applicable to CoS queues only. */
12090 /* Lossy (best-effort) */
12091 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
12093 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
12094 /* Set to 0xFF... (All Fs) if there is no service profile specified */
12095 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
12096 uint8_t unused_0[7];
12097 } __attribute__((packed));
12099 /* Output (16 bytes) */
12101 struct hwrm_queue_cfg_output {
12102 uint16_t error_code;
12104 * Pass/Fail or error type Note: receiver to verify the in parameters,
12105 * and fail the call with an error when appropriate
12108 /* This field returns the type of original request. */
12110 /* This field provides original sequence number of the command. */
12113 * This field is the length of the response in bytes. The last byte of
12114 * the response is a valid flag that will read as '1' when the command
12115 * has been completely written to memory.
12123 * This field is used in Output records to indicate that the output is
12124 * completely written to RAM. This field should be read as '1' to
12125 * indicate that the output has been completely written. When writing a
12126 * command completion or response to an internal processor, the order of
12127 * writes has to be such that this field is written last.
12129 } __attribute__((packed));
12131 /* hwrm_queue_pfcenable_qcfg */
12133 * Description: This function is called by a driver to query PFC configuration
12134 * for different priorities on that port. This mapping can be different on
12137 /* Input (24 bytes) */
12139 struct hwrm_queue_pfcenable_qcfg_input {
12142 * This value indicates what type of request this is. The format for the
12143 * rest of the command is determined by this field.
12145 uint16_t cmpl_ring;
12147 * This value indicates the what completion ring the request will be
12148 * optionally completed on. If the value is -1, then no CR completion
12149 * will be generated. Any other value must be a valid CR ring_id value
12150 * for this function.
12153 /* This value indicates the command sequence number. */
12154 uint16_t target_id;
12156 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
12157 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
12159 uint64_t resp_addr;
12161 * This is the host address where the response will be written when the
12162 * request is complete. This area must be 16B aligned and must be
12163 * cleared to zero before the request is made.
12167 * Port ID of port for which the table is being configured. The HWRM
12168 * needs to check whether this function is allowed to configure pri2cos
12169 * mapping on this port.
12171 uint16_t unused_0[3];
12172 } __attribute__((packed));
12174 /* Output (16 bytes) */
12176 struct hwrm_queue_pfcenable_qcfg_output {
12177 uint16_t error_code;
12179 * Pass/Fail or error type Note: receiver to verify the in parameters,
12180 * and fail the call with an error when appropriate
12183 /* This field returns the type of original request. */
12185 /* This field provides original sequence number of the command. */
12188 * This field is the length of the response in bytes. The last byte of
12189 * the response is a valid flag that will read as '1' when the command
12190 * has been completely written to memory.
12193 /* If set to 1, then PFC is enabled on PRI 0. */
12194 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED UINT32_C(0x1)
12195 /* If set to 1, then PFC is enabled on PRI 1. */
12196 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED UINT32_C(0x2)
12197 /* If set to 1, then PFC is enabled on PRI 2. */
12198 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED UINT32_C(0x4)
12199 /* If set to 1, then PFC is enabled on PRI 3. */
12200 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED UINT32_C(0x8)
12201 /* If set to 1, then PFC is enabled on PRI 4. */
12202 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED UINT32_C(0x10)
12203 /* If set to 1, then PFC is enabled on PRI 5. */
12204 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED UINT32_C(0x20)
12205 /* If set to 1, then PFC is enabled on PRI 6. */
12206 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED UINT32_C(0x40)
12207 /* If set to 1, then PFC is enabled on PRI 7. */
12208 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED UINT32_C(0x80)
12214 * This field is used in Output records to indicate that the output is
12215 * completely written to RAM. This field should be read as '1' to
12216 * indicate that the output has been completely written. When writing a
12217 * command completion or response to an internal processor, the order of
12218 * writes has to be such that this field is written last.
12220 } __attribute__((packed));
12222 /* hwrm_queue_pfcenable_cfg */
12224 * Description: This function is called by a driver to configure the PFC enabled
12225 * for different priorities on that port. This mapping can be different on
12228 /* Input (24 bytes) */
12230 struct hwrm_queue_pfcenable_cfg_input {
12233 * This value indicates what type of request this is. The format for the
12234 * rest of the command is determined by this field.
12236 uint16_t cmpl_ring;
12238 * This value indicates the what completion ring the request will be
12239 * optionally completed on. If the value is -1, then no CR completion
12240 * will be generated. Any other value must be a valid CR ring_id value
12241 * for this function.
12244 /* This value indicates the command sequence number. */
12245 uint16_t target_id;
12247 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
12248 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
12250 uint64_t resp_addr;
12252 * This is the host address where the response will be written when the
12253 * request is complete. This area must be 16B aligned and must be
12254 * cleared to zero before the request is made.
12257 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
12258 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED UINT32_C(0x1)
12259 /* If set to 1, then PFC is requested to be enabled on PRI 1. */
12260 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED UINT32_C(0x2)
12261 /* If set to 1, then PFC is requested to be enabled on PRI 2. */
12262 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED UINT32_C(0x4)
12263 /* If set to 1, then PFC is requested to be enabled on PRI 3. */
12264 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED UINT32_C(0x8)
12265 /* If set to 1, then PFC is requested to be enabled on PRI 4. */
12266 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED UINT32_C(0x10)
12267 /* If set to 1, then PFC is requested to be enabled on PRI 5. */
12268 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED UINT32_C(0x20)
12269 /* If set to 1, then PFC is requested to be enabled on PRI 6. */
12270 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED UINT32_C(0x40)
12271 /* If set to 1, then PFC is requested to be enabled on PRI 7. */
12272 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED UINT32_C(0x80)
12275 * Port ID of port for which the table is being configured. The HWRM
12276 * needs to check whether this function is allowed to configure pri2cos
12277 * mapping on this port.
12280 } __attribute__((packed));
12282 /* Output (16 bytes) */
12284 struct hwrm_queue_pfcenable_cfg_output {
12285 uint16_t error_code;
12287 * Pass/Fail or error type Note: receiver to verify the in parameters,
12288 * and fail the call with an error when appropriate
12291 /* This field returns the type of original request. */
12293 /* This field provides original sequence number of the command. */
12296 * This field is the length of the response in bytes. The last byte of
12297 * the response is a valid flag that will read as '1' when the command
12298 * has been completely written to memory.
12306 * This field is used in Output records to indicate that the output is
12307 * completely written to RAM. This field should be read as '1' to
12308 * indicate that the output has been completely written. When writing a
12309 * command completion or response to an internal processor, the order of
12310 * writes has to be such that this field is written last.
12312 } __attribute__((packed));
12314 /* hwrm_queue_pri2cos_qcfg */
12316 * Description: This function is called by a driver to query configuration of
12317 * the priority to CoS queue mapping on the transmit side and receive side. This
12318 * mapping can be different in each direction (TX or RX). This mapping can be
12319 * different on different ports. Each CoS queue represents a Traffic Class (TC)
12322 /* Input (24 bytes) */
12324 struct hwrm_queue_pri2cos_qcfg_input {
12327 * This value indicates what type of request this is. The format for the
12328 * rest of the command is determined by this field.
12330 uint16_t cmpl_ring;
12332 * This value indicates the what completion ring the request will be
12333 * optionally completed on. If the value is -1, then no CR completion
12334 * will be generated. Any other value must be a valid CR ring_id value
12335 * for this function.
12338 /* This value indicates the command sequence number. */
12339 uint16_t target_id;
12341 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
12342 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
12344 uint64_t resp_addr;
12346 * This is the host address where the response will be written when the
12347 * request is complete. This area must be 16B aligned and must be
12348 * cleared to zero before the request is made.
12352 * Enumeration denoting the RX, TX type of the resource. This
12353 * enumeration is used for resources that are similar for both TX and RX
12354 * paths of the chip.
12356 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
12358 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX (UINT32_C(0x0) << 0)
12360 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX (UINT32_C(0x1) << 0)
12361 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX
12363 * When this bit is set to '0', the query is for VLAN PRI field in
12364 * tunnel headers. When this bit is set to '1', the query is for VLAN
12365 * PRI field in inner packet headers.
12367 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
12370 * Port ID of port for which the table is being configured. The HWRM
12371 * needs to check whether this function is allowed to configure pri2cos
12372 * mapping on this port.
12374 uint8_t unused_0[3];
12375 } __attribute__((packed));
12377 /* Output (24 bytes) */
12379 struct hwrm_queue_pri2cos_qcfg_output {
12380 uint16_t error_code;
12382 * Pass/Fail or error type Note: receiver to verify the in parameters,
12383 * and fail the call with an error when appropriate
12386 /* This field returns the type of original request. */
12388 /* This field provides original sequence number of the command. */
12391 * This field is the length of the response in bytes. The last byte of
12392 * the response is a valid flag that will read as '1' when the command
12393 * has been completely written to memory.
12395 uint8_t pri0_cos_queue_id;
12397 * CoS Queue assigned to priority 0. This value can only be changed
12398 * before traffic has started. A value of 0xff indicates that no CoS
12399 * queue is assigned to the specified priority.
12401 uint8_t pri1_cos_queue_id;
12403 * CoS Queue assigned to priority 1. This value can only be changed
12404 * before traffic has started. A value of 0xff indicates that no CoS
12405 * queue is assigned to the specified priority.
12407 uint8_t pri2_cos_queue_id;
12409 * CoS Queue assigned to priority 2 This value can only be changed
12410 * before traffic has started. A value of 0xff indicates that no CoS
12411 * queue is assigned to the specified priority.
12413 uint8_t pri3_cos_queue_id;
12415 * CoS Queue assigned to priority 3. This value can only be changed
12416 * before traffic has started. A value of 0xff indicates that no CoS
12417 * queue is assigned to the specified priority.
12419 uint8_t pri4_cos_queue_id;
12421 * CoS Queue assigned to priority 4. This value can only be changed
12422 * before traffic has started. A value of 0xff indicates that no CoS
12423 * queue is assigned to the specified priority.
12425 uint8_t pri5_cos_queue_id;
12427 * CoS Queue assigned to priority 5. This value can only be changed
12428 * before traffic has started. A value of 0xff indicates that no CoS
12429 * queue is assigned to the specified priority.
12431 uint8_t pri6_cos_queue_id;
12433 * CoS Queue assigned to priority 6. This value can only be changed
12434 * before traffic has started. A value of 0xff indicates that no CoS
12435 * queue is assigned to the specified priority.
12437 uint8_t pri7_cos_queue_id;
12439 * CoS Queue assigned to priority 7. This value can only be changed
12440 * before traffic has started. A value of 0xff indicates that no CoS
12441 * queue is assigned to the specified priority.
12443 uint8_t queue_cfg_info;
12444 /* Information about queue configuration. */
12446 * If this flag is set to '1', then the PRI to CoS configuration is
12447 * asymmetric on TX and RX sides. If this flag is set to '0', then PRI
12448 * to CoS configuration is symmetric on TX and RX sides.
12450 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG UINT32_C(0x1)
12458 * This field is used in Output records to indicate that the output is
12459 * completely written to RAM. This field should be read as '1' to
12460 * indicate that the output has been completely written. When writing a
12461 * command completion or response to an internal processor, the order of
12462 * writes has to be such that this field is written last.
12464 } __attribute__((packed));
12466 /* hwrm_queue_pri2cos_cfg */
12468 * Description: This function is called by a driver to configure the priority to
12469 * CoS queue mapping on the transmit side and receive side. This mapping can be
12470 * different in each direction (TX or RX). This mapping can be different on
12471 * different ports. Each CoS queue represents a Traffic Class (TC) on that port.
12472 * This command configures the VLAN PRI-to-TC mapping for a specific port in
12473 * specific direction.
12475 /* Input (40 bytes) */
12477 struct hwrm_queue_pri2cos_cfg_input {
12480 * This value indicates what type of request this is. The format for the
12481 * rest of the command is determined by this field.
12483 uint16_t cmpl_ring;
12485 * This value indicates the what completion ring the request will be
12486 * optionally completed on. If the value is -1, then no CR completion
12487 * will be generated. Any other value must be a valid CR ring_id value
12488 * for this function.
12491 /* This value indicates the command sequence number. */
12492 uint16_t target_id;
12494 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
12495 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
12497 uint64_t resp_addr;
12499 * This is the host address where the response will be written when the
12500 * request is complete. This area must be 16B aligned and must be
12501 * cleared to zero before the request is made.
12505 * Enumeration denoting the RX, TX, or both directions applicable to the
12506 * resource. This enumeration is used for resources that are similar for
12507 * both TX and RX paths of the chip.
12509 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
12510 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
12512 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX (UINT32_C(0x0) << 0)
12514 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX (UINT32_C(0x1) << 0)
12515 /* Bi-directional (Symmetrically applicable to TX and RX paths) */
12516 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR (UINT32_C(0x2) << 0)
12517 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR
12519 * When this bit is set to '0', the mapping is requested for VLAN PRI
12520 * field in tunnel headers. When this bit is set to '1', the mapping is
12521 * requested for VLAN PRI field in inner packet headers.
12523 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
12526 * This bit must be '1' for the pri0_cos_queue_id field to be
12529 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID UINT32_C(0x1)
12531 * This bit must be '1' for the pri1_cos_queue_id field to be
12534 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID UINT32_C(0x2)
12536 * This bit must be '1' for the pri2_cos_queue_id field to be
12539 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID UINT32_C(0x4)
12541 * This bit must be '1' for the pri3_cos_queue_id field to be
12544 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID UINT32_C(0x8)
12546 * This bit must be '1' for the pri4_cos_queue_id field to be
12549 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID UINT32_C(0x10)
12551 * This bit must be '1' for the pri5_cos_queue_id field to be
12554 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID UINT32_C(0x20)
12556 * This bit must be '1' for the pri6_cos_queue_id field to be
12559 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID UINT32_C(0x40)
12561 * This bit must be '1' for the pri7_cos_queue_id field to be
12564 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID UINT32_C(0x80)
12567 * Port ID of port for which the table is being configured. The HWRM
12568 * needs to check whether this function is allowed to configure pri2cos
12569 * mapping on this port.
12571 uint8_t pri0_cos_queue_id;
12573 * CoS Queue assigned to priority 0. This value can only be changed
12574 * before traffic has started.
12576 uint8_t pri1_cos_queue_id;
12578 * CoS Queue assigned to priority 1. This value can only be changed
12579 * before traffic has started.
12581 uint8_t pri2_cos_queue_id;
12583 * CoS Queue assigned to priority 2 This value can only be changed
12584 * before traffic has started.
12586 uint8_t pri3_cos_queue_id;
12588 * CoS Queue assigned to priority 3. This value can only be changed
12589 * before traffic has started.
12591 uint8_t pri4_cos_queue_id;
12593 * CoS Queue assigned to priority 4. This value can only be changed
12594 * before traffic has started.
12596 uint8_t pri5_cos_queue_id;
12598 * CoS Queue assigned to priority 5. This value can only be changed
12599 * before traffic has started.
12601 uint8_t pri6_cos_queue_id;
12603 * CoS Queue assigned to priority 6. This value can only be changed
12604 * before traffic has started.
12606 uint8_t pri7_cos_queue_id;
12608 * CoS Queue assigned to priority 7. This value can only be changed
12609 * before traffic has started.
12611 uint8_t unused_0[7];
12612 } __attribute__((packed));
12614 /* Output (16 bytes) */
12616 struct hwrm_queue_pri2cos_cfg_output {
12617 uint16_t error_code;
12619 * Pass/Fail or error type Note: receiver to verify the in parameters,
12620 * and fail the call with an error when appropriate
12623 /* This field returns the type of original request. */
12625 /* This field provides original sequence number of the command. */
12628 * This field is the length of the response in bytes. The last byte of
12629 * the response is a valid flag that will read as '1' when the command
12630 * has been completely written to memory.
12638 * This field is used in Output records to indicate that the output is
12639 * completely written to RAM. This field should be read as '1' to
12640 * indicate that the output has been completely written. When writing a
12641 * command completion or response to an internal processor, the order of
12642 * writes has to be such that this field is written last.
12644 } __attribute__((packed));
12646 /* hwrm_queue_cos2bw_qcfg */
12648 * Description: This function is called by a driver to query the BW to CoS queue
12649 * mapping on the transmit side of a specific port. This mapping can be
12650 * different on different ports. Each CoS queue represents a Traffic Class (TC)
12651 * on that port. Each traffic class can be assigned a valid combination of the
12652 * following: - Minimum bandwidth - Maximum bandwidth - Transmission selection
12653 * algorithm (TSA) - Priority Level (only applies to strict priority COS) -
12654 * Bandwidth weight # A CoS can be SP or non-SP: A SP CoS always gets the strict
12655 * priority. Is an COS min BW is set to 0x0 then it is considered to be non-SP;
12656 * this is a valid configuration. Note: SP provides lower latency in addition to
12657 * reserved bandwidth # For both SP CoS and non-SP CoS, min BW can be specified
12658 * to reserve specific amount of the port BW. # The min BW specified for a CoS
12659 * shall not exceed max port bandwidth. # The total of min BWs specified for all
12660 * CoS shall not exceed max port bandwidth. # For any non-SP CoS, the minimum
12661 * bandwidth guarantees are subject to round-robin scheduling. This allows BW
12662 * reservation with anti-starvation; one CoS will not block another CoS using
12663 * RR. Note: The bandwidth guarantees for any non-SP CoS are met after servicing
12664 * all SP CoS. # An SP CoS can potentially starve other lower priority SP CoS
12665 * and non-SP CoS queues. This can occur to the extent the SP min exceeds the
12666 * available port BW. # For any CoS, max BW can be specified to limit the BW
12667 * consumed by the CoS. # The max BW specified for a CoS shall not exceed the
12668 * max port bandwidth. # The WFQ provides a mechanism for sharing available
12669 * bandwidth beyond the reserved minimums configured for each CoS. The WFQ
12670 * scheduler is used to provide the percentages of remaining bandwidth after: *
12671 * first servicing the reserved bandwidth for all SP CoS, * followed by the
12672 * reserved bandwidth for all non-SP CoS * All CoS may participate in the WFQ #
12673 * If a CoS does not have a configured max BW it may use all available bandwidth
12674 * up to the max port bandwidth Minimum Bandwidth (min BW): # This is the
12675 * guaranteed bandwidth for the COS. # A value of 0x0 is valid and it means that
12676 * this COS is not guaranteed any bandwidth. A value of 0xFF.. (all Fs) means
12677 * min BW is not specified. When the min BW is not specified, the HWRM can set
12678 * it to any value it considers appropriate. Note: For a non-SP COS, the HWRM
12679 * should set min BW to 0 when the min BW is not specified. For an SP COS, the
12680 * HWRM should set min BW to some small value when the min BW is not specified.
12681 * Maximum Bandwidth: # This is the bandwidth limit of the COS. # Values 0x0 and
12682 * 0xFF.. (all Fs) are considered unspecified and the HWRM will set the maximum
12683 * bandwidth to maximum port bandwidth. Priority Level: # It applies only to SP.
12684 * # This parameter is ignored for non-SP. # 0-7 are valid values (higher value
12685 * means higher priority) # A priority level can be assigned to at most one SP.
12686 * # Invalid priority levels assignment for SPs shall result in failure.
12687 * Additional notes: # The HWRM may have to use min and (max - min) to set
12688 * appropriate counters of hardware rate limiters. # The bandwidth percentage as
12689 * specified in the DCB TC BW assignment should be used by the driver to specify
12690 * maximum bandwidth and bandwidth weight for a COS. For example, the driver
12691 * should set max BW to 20 Gbps and weight to 50 for two COSs when these two
12692 * COSs are assigned 50% share of 40 Gbps max port bandwidth.
12694 /* Input (24 bytes) */
12696 struct hwrm_queue_cos2bw_qcfg_input {
12699 * This value indicates what type of request this is. The format for the
12700 * rest of the command is determined by this field.
12702 uint16_t cmpl_ring;
12704 * This value indicates the what completion ring the request will be
12705 * optionally completed on. If the value is -1, then no CR completion
12706 * will be generated. Any other value must be a valid CR ring_id value
12707 * for this function.
12710 /* This value indicates the command sequence number. */
12711 uint16_t target_id;
12713 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
12714 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
12716 uint64_t resp_addr;
12718 * This is the host address where the response will be written when the
12719 * request is complete. This area must be 16B aligned and must be
12720 * cleared to zero before the request is made.
12724 * Port ID of port for which the table is being configured. The HWRM
12725 * needs to check whether this function is allowed to configure TC BW
12726 * assignment on this port.
12728 uint16_t unused_0[3];
12729 } __attribute__((packed));
12731 /* Output (112 bytes) */
12733 struct hwrm_queue_cos2bw_qcfg_output {
12734 uint16_t error_code;
12736 * Pass/Fail or error type Note: receiver to verify the in parameters,
12737 * and fail the call with an error when appropriate
12740 /* This field returns the type of original request. */
12742 /* This field provides original sequence number of the command. */
12745 * This field is the length of the response in bytes. The last byte of
12746 * the response is a valid flag that will read as '1' when the command
12747 * has been completely written to memory.
12750 /* ID of CoS Queue 0. */
12753 uint32_t queue_id0_min_bw;
12755 * Minimum BW allocated to CoS Queue. The HWRM will translate this value
12756 * into byte counter and time interval used for this COS inside the
12759 /* The bandwidth value. */
12760 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
12761 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
12762 /* The granularity of the value (bits or bytes). */
12763 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE UINT32_C(0x10000000)
12764 /* Value is in bits. */
12765 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
12766 /* Value is in bytes. */
12767 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
12768 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
12769 /* bw_value_unit is 3 b */
12770 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
12771 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
12772 /* Value is in Mb or MB (base 10). */
12773 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
12774 /* Value is in Kb or KB (base 10). */
12775 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
12776 /* Value is in bits or bytes. */
12777 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
12778 /* Value is in Gb or GB (base 10). */
12779 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
12780 /* Value is in 1/100th of a percentage of total bandwidth. */
12781 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
12783 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
12784 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
12785 uint32_t queue_id0_max_bw;
12787 * Maximum BW allocated to CoS Queue. The HWRM will translate this value
12788 * into byte counter and time interval used for this COS inside the
12791 /* The bandwidth value. */
12792 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
12793 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
12794 /* The granularity of the value (bits or bytes). */
12795 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE UINT32_C(0x10000000)
12796 /* Value is in bits. */
12797 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
12798 /* Value is in bytes. */
12799 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
12800 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
12801 /* bw_value_unit is 3 b */
12802 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
12803 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
12804 /* Value is in Mb or MB (base 10). */
12805 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
12806 /* Value is in Kb or KB (base 10). */
12807 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
12808 /* Value is in bits or bytes. */
12809 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
12810 /* Value is in Gb or GB (base 10). */
12811 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
12812 /* Value is in 1/100th of a percentage of total bandwidth. */
12813 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
12815 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
12816 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
12817 uint8_t queue_id0_tsa_assign;
12818 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
12819 /* Strict Priority */
12820 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP UINT32_C(0x0)
12821 /* Enhanced Transmission Selection */
12822 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS UINT32_C(0x1)
12824 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
12826 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
12827 uint8_t queue_id0_pri_lvl;
12829 * Priority level for strict priority. Valid only when the tsa_assign is
12830 * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved.
12832 uint8_t queue_id0_bw_weight;
12834 * Weight used to allocate remaining BW for this COS after servicing
12835 * guaranteed bandwidths for all COS.
12838 /* ID of CoS Queue 1. */
12839 uint32_t queue_id1_min_bw;
12841 * Minimum BW allocated to CoS Queue. The HWRM will translate this value
12842 * into byte counter and time interval used for this COS inside the
12845 /* The bandwidth value. */
12846 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
12847 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0
12848 /* The granularity of the value (bits or bytes). */
12849 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE UINT32_C(0x10000000)
12850 /* Value is in bits. */
12851 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
12852 /* Value is in bytes. */
12853 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
12854 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
12855 /* bw_value_unit is 3 b */
12856 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
12857 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29
12858 /* Value is in Mb or MB (base 10). */
12859 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
12860 /* Value is in Kb or KB (base 10). */
12861 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
12862 /* Value is in bits or bytes. */
12863 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
12864 /* Value is in Gb or GB (base 10). */
12865 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
12866 /* Value is in 1/100th of a percentage of total bandwidth. */
12867 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
12869 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
12870 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
12871 uint32_t queue_id1_max_bw;
12873 * Maximum BW allocated to CoS queue. The HWRM will translate this value
12874 * into byte counter and time interval used for this COS inside the
12877 /* The bandwidth value. */
12878 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
12879 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0
12880 /* The granularity of the value (bits or bytes). */
12881 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE UINT32_C(0x10000000)
12882 /* Value is in bits. */
12883 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
12884 /* Value is in bytes. */
12885 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
12886 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
12887 /* bw_value_unit is 3 b */
12888 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
12889 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29
12890 /* Value is in Mb or MB (base 10). */
12891 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
12892 /* Value is in Kb or KB (base 10). */
12893 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
12894 /* Value is in bits or bytes. */
12895 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
12896 /* Value is in Gb or GB (base 10). */
12897 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
12898 /* Value is in 1/100th of a percentage of total bandwidth. */
12899 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
12901 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
12902 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
12903 uint8_t queue_id1_tsa_assign;
12904 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
12905 /* Strict Priority */
12906 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP UINT32_C(0x0)
12907 /* Enhanced Transmission Selection */
12908 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS UINT32_C(0x1)
12910 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
12912 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
12913 uint8_t queue_id1_pri_lvl;
12915 * Priority level for strict priority. Valid only when the tsa_assign is
12916 * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved.
12918 uint8_t queue_id1_bw_weight;
12920 * Weight used to allocate remaining BW for this COS after servicing
12921 * guaranteed bandwidths for all COS.
12924 /* ID of CoS Queue 2. */
12925 uint32_t queue_id2_min_bw;
12927 * Minimum BW allocated to CoS Queue. The HWRM will translate this value
12928 * into byte counter and time interval used for this COS inside the
12931 /* The bandwidth value. */
12932 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
12933 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0
12934 /* The granularity of the value (bits or bytes). */
12935 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE UINT32_C(0x10000000)
12936 /* Value is in bits. */
12937 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
12938 /* Value is in bytes. */
12939 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
12940 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
12941 /* bw_value_unit is 3 b */
12942 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
12943 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29
12944 /* Value is in Mb or MB (base 10). */
12945 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
12946 /* Value is in Kb or KB (base 10). */
12947 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
12948 /* Value is in bits or bytes. */
12949 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
12950 /* Value is in Gb or GB (base 10). */
12951 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
12952 /* Value is in 1/100th of a percentage of total bandwidth. */
12953 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
12955 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
12956 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
12957 uint32_t queue_id2_max_bw;
12959 * Maximum BW allocated to CoS queue. The HWRM will translate this value
12960 * into byte counter and time interval used for this COS inside the
12963 /* The bandwidth value. */
12964 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
12965 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0
12966 /* The granularity of the value (bits or bytes). */
12967 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE UINT32_C(0x10000000)
12968 /* Value is in bits. */
12969 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
12970 /* Value is in bytes. */
12971 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
12972 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
12973 /* bw_value_unit is 3 b */
12974 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
12975 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29
12976 /* Value is in Mb or MB (base 10). */
12977 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
12978 /* Value is in Kb or KB (base 10). */
12979 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
12980 /* Value is in bits or bytes. */
12981 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
12982 /* Value is in Gb or GB (base 10). */
12983 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
12984 /* Value is in 1/100th of a percentage of total bandwidth. */
12985 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
12987 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
12988 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
12989 uint8_t queue_id2_tsa_assign;
12990 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
12991 /* Strict Priority */
12992 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP UINT32_C(0x0)
12993 /* Enhanced Transmission Selection */
12994 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS UINT32_C(0x1)
12996 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
12998 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
12999 uint8_t queue_id2_pri_lvl;
13001 * Priority level for strict priority. Valid only when the tsa_assign is
13002 * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved.
13004 uint8_t queue_id2_bw_weight;
13006 * Weight used to allocate remaining BW for this COS after servicing
13007 * guaranteed bandwidths for all COS.
13010 /* ID of CoS Queue 3. */
13011 uint32_t queue_id3_min_bw;
13013 * Minimum BW allocated to CoS Queue. The HWRM will translate this value
13014 * into byte counter and time interval used for this COS inside the
13017 /* The bandwidth value. */
13018 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
13019 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0
13020 /* The granularity of the value (bits or bytes). */
13021 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE UINT32_C(0x10000000)
13022 /* Value is in bits. */
13023 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
13024 /* Value is in bytes. */
13025 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
13026 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
13027 /* bw_value_unit is 3 b */
13028 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
13029 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29
13030 /* Value is in Mb or MB (base 10). */
13031 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
13032 /* Value is in Kb or KB (base 10). */
13033 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
13034 /* Value is in bits or bytes. */
13035 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
13036 /* Value is in Gb or GB (base 10). */
13037 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
13038 /* Value is in 1/100th of a percentage of total bandwidth. */
13039 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
13041 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
13042 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
13043 uint32_t queue_id3_max_bw;
13045 * Maximum BW allocated to CoS queue. The HWRM will translate this value
13046 * into byte counter and time interval used for this COS inside the
13049 /* The bandwidth value. */
13050 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
13051 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0
13052 /* The granularity of the value (bits or bytes). */
13053 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE UINT32_C(0x10000000)
13054 /* Value is in bits. */
13055 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
13056 /* Value is in bytes. */
13057 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
13058 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
13059 /* bw_value_unit is 3 b */
13060 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
13061 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29
13062 /* Value is in Mb or MB (base 10). */
13063 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
13064 /* Value is in Kb or KB (base 10). */
13065 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
13066 /* Value is in bits or bytes. */
13067 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
13068 /* Value is in Gb or GB (base 10). */
13069 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
13070 /* Value is in 1/100th of a percentage of total bandwidth. */
13071 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
13073 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
13074 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
13075 uint8_t queue_id3_tsa_assign;
13076 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
13077 /* Strict Priority */
13078 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP UINT32_C(0x0)
13079 /* Enhanced Transmission Selection */
13080 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS UINT32_C(0x1)
13082 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
13084 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
13085 uint8_t queue_id3_pri_lvl;
13087 * Priority level for strict priority. Valid only when the tsa_assign is
13088 * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved.
13090 uint8_t queue_id3_bw_weight;
13092 * Weight used to allocate remaining BW for this COS after servicing
13093 * guaranteed bandwidths for all COS.
13096 /* ID of CoS Queue 4. */
13097 uint32_t queue_id4_min_bw;
13099 * Minimum BW allocated to CoS Queue. The HWRM will translate this value
13100 * into byte counter and time interval used for this COS inside the
13103 /* The bandwidth value. */
13104 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
13105 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0
13106 /* The granularity of the value (bits or bytes). */
13107 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE UINT32_C(0x10000000)
13108 /* Value is in bits. */
13109 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
13110 /* Value is in bytes. */
13111 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
13112 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
13113 /* bw_value_unit is 3 b */
13114 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
13115 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29
13116 /* Value is in Mb or MB (base 10). */
13117 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
13118 /* Value is in Kb or KB (base 10). */
13119 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
13120 /* Value is in bits or bytes. */
13121 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
13122 /* Value is in Gb or GB (base 10). */
13123 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
13124 /* Value is in 1/100th of a percentage of total bandwidth. */
13125 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
13127 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
13128 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
13129 uint32_t queue_id4_max_bw;
13131 * Maximum BW allocated to CoS queue. The HWRM will translate this value
13132 * into byte counter and time interval used for this COS inside the
13135 /* The bandwidth value. */
13136 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
13137 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0
13138 /* The granularity of the value (bits or bytes). */
13139 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE UINT32_C(0x10000000)
13140 /* Value is in bits. */
13141 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
13142 /* Value is in bytes. */
13143 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
13144 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
13145 /* bw_value_unit is 3 b */
13146 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
13147 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29
13148 /* Value is in Mb or MB (base 10). */
13149 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
13150 /* Value is in Kb or KB (base 10). */
13151 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
13152 /* Value is in bits or bytes. */
13153 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
13154 /* Value is in Gb or GB (base 10). */
13155 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
13156 /* Value is in 1/100th of a percentage of total bandwidth. */
13157 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
13159 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
13160 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
13161 uint8_t queue_id4_tsa_assign;
13162 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
13163 /* Strict Priority */
13164 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP UINT32_C(0x0)
13165 /* Enhanced Transmission Selection */
13166 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS UINT32_C(0x1)
13168 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
13170 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
13171 uint8_t queue_id4_pri_lvl;
13173 * Priority level for strict priority. Valid only when the tsa_assign is
13174 * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved.
13176 uint8_t queue_id4_bw_weight;
13178 * Weight used to allocate remaining BW for this COS after servicing
13179 * guaranteed bandwidths for all COS.
13182 /* ID of CoS Queue 5. */
13183 uint32_t queue_id5_min_bw;
13185 * Minimum BW allocated to CoS Queue. The HWRM will translate this value
13186 * into byte counter and time interval used for this COS inside the
13189 /* The bandwidth value. */
13190 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
13191 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0
13192 /* The granularity of the value (bits or bytes). */
13193 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE UINT32_C(0x10000000)
13194 /* Value is in bits. */
13195 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
13196 /* Value is in bytes. */
13197 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
13198 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
13199 /* bw_value_unit is 3 b */
13200 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
13201 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29
13202 /* Value is in Mb or MB (base 10). */
13203 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
13204 /* Value is in Kb or KB (base 10). */
13205 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
13206 /* Value is in bits or bytes. */
13207 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
13208 /* Value is in Gb or GB (base 10). */
13209 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
13210 /* Value is in 1/100th of a percentage of total bandwidth. */
13211 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
13213 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
13214 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
13215 uint32_t queue_id5_max_bw;
13217 * Maximum BW allocated to CoS queue. The HWRM will translate this value
13218 * into byte counter and time interval used for this COS inside the
13221 /* The bandwidth value. */
13222 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
13223 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0
13224 /* The granularity of the value (bits or bytes). */
13225 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE UINT32_C(0x10000000)
13226 /* Value is in bits. */
13227 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
13228 /* Value is in bytes. */
13229 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
13230 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
13231 /* bw_value_unit is 3 b */
13232 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
13233 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29
13234 /* Value is in Mb or MB (base 10). */
13235 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
13236 /* Value is in Kb or KB (base 10). */
13237 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
13238 /* Value is in bits or bytes. */
13239 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
13240 /* Value is in Gb or GB (base 10). */
13241 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
13242 /* Value is in 1/100th of a percentage of total bandwidth. */
13243 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
13245 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
13246 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
13247 uint8_t queue_id5_tsa_assign;
13248 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
13249 /* Strict Priority */
13250 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP UINT32_C(0x0)
13251 /* Enhanced Transmission Selection */
13252 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS UINT32_C(0x1)
13254 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
13256 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
13257 uint8_t queue_id5_pri_lvl;
13259 * Priority level for strict priority. Valid only when the tsa_assign is
13260 * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved.
13262 uint8_t queue_id5_bw_weight;
13264 * Weight used to allocate remaining BW for this COS after servicing
13265 * guaranteed bandwidths for all COS.
13268 /* ID of CoS Queue 6. */
13269 uint32_t queue_id6_min_bw;
13271 * Minimum BW allocated to CoS Queue. The HWRM will translate this value
13272 * into byte counter and time interval used for this COS inside the
13275 /* The bandwidth value. */
13276 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
13277 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0
13278 /* The granularity of the value (bits or bytes). */
13279 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE UINT32_C(0x10000000)
13280 /* Value is in bits. */
13281 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
13282 /* Value is in bytes. */
13283 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
13284 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
13285 /* bw_value_unit is 3 b */
13286 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
13287 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29
13288 /* Value is in Mb or MB (base 10). */
13289 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
13290 /* Value is in Kb or KB (base 10). */
13291 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
13292 /* Value is in bits or bytes. */
13293 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
13294 /* Value is in Gb or GB (base 10). */
13295 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
13296 /* Value is in 1/100th of a percentage of total bandwidth. */
13297 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
13299 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
13300 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
13301 uint32_t queue_id6_max_bw;
13303 * Maximum BW allocated to CoS queue. The HWRM will translate this value
13304 * into byte counter and time interval used for this COS inside the
13307 /* The bandwidth value. */
13308 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
13309 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0
13310 /* The granularity of the value (bits or bytes). */
13311 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE UINT32_C(0x10000000)
13312 /* Value is in bits. */
13313 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
13314 /* Value is in bytes. */
13315 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
13316 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
13317 /* bw_value_unit is 3 b */
13318 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
13319 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29
13320 /* Value is in Mb or MB (base 10). */
13321 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
13322 /* Value is in Kb or KB (base 10). */
13323 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
13324 /* Value is in bits or bytes. */
13325 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
13326 /* Value is in Gb or GB (base 10). */
13327 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
13328 /* Value is in 1/100th of a percentage of total bandwidth. */
13329 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
13331 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
13332 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
13333 uint8_t queue_id6_tsa_assign;
13334 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
13335 /* Strict Priority */
13336 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP UINT32_C(0x0)
13337 /* Enhanced Transmission Selection */
13338 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS UINT32_C(0x1)
13340 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
13342 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
13343 uint8_t queue_id6_pri_lvl;
13345 * Priority level for strict priority. Valid only when the tsa_assign is
13346 * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved.
13348 uint8_t queue_id6_bw_weight;
13350 * Weight used to allocate remaining BW for this COS after servicing
13351 * guaranteed bandwidths for all COS.
13354 /* ID of CoS Queue 7. */
13355 uint32_t queue_id7_min_bw;
13357 * Minimum BW allocated to CoS Queue. The HWRM will translate this value
13358 * into byte counter and time interval used for this COS inside the
13361 /* The bandwidth value. */
13362 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
13363 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0
13364 /* The granularity of the value (bits or bytes). */
13365 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE UINT32_C(0x10000000)
13366 /* Value is in bits. */
13367 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
13368 /* Value is in bytes. */
13369 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
13370 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
13371 /* bw_value_unit is 3 b */
13372 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
13373 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29
13374 /* Value is in Mb or MB (base 10). */
13375 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
13376 /* Value is in Kb or KB (base 10). */
13377 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
13378 /* Value is in bits or bytes. */
13379 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
13380 /* Value is in Gb or GB (base 10). */
13381 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
13382 /* Value is in 1/100th of a percentage of total bandwidth. */
13383 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
13385 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
13386 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
13387 uint32_t queue_id7_max_bw;
13389 * Maximum BW allocated to CoS queue. The HWRM will translate this value
13390 * into byte counter and time interval used for this COS inside the
13393 /* The bandwidth value. */
13394 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
13395 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0
13396 /* The granularity of the value (bits or bytes). */
13397 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE UINT32_C(0x10000000)
13398 /* Value is in bits. */
13399 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
13400 /* Value is in bytes. */
13401 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
13402 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
13403 /* bw_value_unit is 3 b */
13404 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
13405 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29
13406 /* Value is in Mb or MB (base 10). */
13407 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
13408 /* Value is in Kb or KB (base 10). */
13409 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
13410 /* Value is in bits or bytes. */
13411 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
13412 /* Value is in Gb or GB (base 10). */
13413 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
13414 /* Value is in 1/100th of a percentage of total bandwidth. */
13415 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
13417 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
13418 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
13419 uint8_t queue_id7_tsa_assign;
13420 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
13421 /* Strict Priority */
13422 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP UINT32_C(0x0)
13423 /* Enhanced Transmission Selection */
13424 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS UINT32_C(0x1)
13426 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
13428 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
13429 uint8_t queue_id7_pri_lvl;
13431 * Priority level for strict priority. Valid only when the tsa_assign is
13432 * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved.
13434 uint8_t queue_id7_bw_weight;
13436 * Weight used to allocate remaining BW for this COS after servicing
13437 * guaranteed bandwidths for all COS.
13445 * This field is used in Output records to indicate that the output is
13446 * completely written to RAM. This field should be read as '1' to
13447 * indicate that the output has been completely written. When writing a
13448 * command completion or response to an internal processor, the order of
13449 * writes has to be such that this field is written last.
13451 } __attribute__((packed));
13453 /* hwrm_queue_cos2bw_cfg */
13455 * Description: This function is called by a driver to configure the BW to CoS
13456 * queue mapping on the transmit side of a specific port. This mapping can be
13457 * different on different ports. Each CoS queue represents a Traffic Class (TC)
13458 * on that port. Each traffic class can be assigned a valid combination of the
13459 * following: - Minimum bandwidth - Maximum bandwidth - Transmission selection
13460 * algorithm (TSA) - Priority Level (only applies to strict priority COS) -
13461 * Bandwidth weight # A CoS can be SP or non-SP: A SP CoS always gets the strict
13462 * priority. Note: SP provides lower latency in addition to reserved bandwidth #
13463 * For non-SP CoS, min BW can be specified to reserve specific amount of the
13464 * port BW. # The min BW specified for a CoS shall not exceed max port
13465 * bandwidth. # The total of min BWs specified for all CoS shall not exceed max
13466 * port bandwidth. # For any non-SP CoS, the minimum bandwidth guarantees are
13467 * subject to round-robin scheduling. This allows BW reservation with anti-
13468 * starvation; one CoS will not block another CoS using RR. Note: The bandwidth
13469 * guarantees for any non-SP CoS are met after servicing all SP CoS. # An SP CoS
13470 * can potentially starve other lower priority SP CoS and non-SP CoS queues.
13471 * This can occur to the extent the SP min exceeds the available port BW. # For
13472 * any CoS, max BW can be specified to limit the BW consumed by the CoS. # A max
13473 * BW can be used for a SP CoS to limit the starvation of other CoS, but using
13474 * this will cause some characteristics of any ETS CoS to be violated. # The max
13475 * BW specified for a CoS shall not exceed the max port bandwidth. # For SP CoS,
13476 * it is recommended to set min and max BW to 0. This instructs the adapter to
13477 * use default values. # The WFQ provides a mechanism for sharing available
13478 * bandwidth beyond the reserved minimums configured for each CoS. The WFQ
13479 * scheduler is used to provide the percentages of remaining bandwidth after: -
13480 * first servicing the reserved bandwidth for all SP CoS, - followed by the
13481 * reserved bandwidth for all non-SP CoS - All CoS may participate in the WFQ #
13482 * If a CoS does not have a configured max BW it may use all available bandwidth
13483 * up to the max port bandwidth Minimum Bandwidth (min BW): # This is the
13484 * guaranteed bandwidth for the COS. # A value of 0x0 is valid and it means that
13485 * this COS is not guaranteed any bandwidth. A value of 0xFF.. (all Fs) means
13486 * min BW is not specified. When the min BW is not specified, the HWRM can set
13487 * it to any value it considers appropriate. Note: For a non-SP COS, the HWRM
13488 * should set min BW to 0 when the min BW is not specified. For an SP COS, min
13489 * BW value is ignored. Maximum Bandwidth: # This is the bandwidth limit of the
13490 * COS. # Values 0x0 and 0xFF.. (all Fs) are considered unspecified and the HWRM
13491 * will set the maximum bandwidth to maximum port bandwidth. Priority Level: #
13492 * It applies only to SP. # This parameter is ignored for non-SP. # 0-7 are
13493 * valid values (higher value means higher priority) # A priority level can be
13494 * assigned to at most one SP. # Invalid priority levels assignment for SPs
13495 * shall result in failure. Additional notes: # The HWRM may have to use min and
13496 * (max - min) to set appropriate counters of hardware rate limiters. # The
13497 * bandwidth percentage as specified in the DCB TC BW assignment should be used
13498 * by the driver to specify minimum bandwidth and bandwidth weight for a COS.
13499 * For example, the driver should set max BW to 20 Gbps and weight to 50 for two
13500 * COSs when these two COSs are assigned 50% share of 40 Gbps max port
13501 * bandwidth. DCBX use cases should always use max BW of 100% for all ETS CoS
13504 /* Input (128 bytes) */
13506 struct hwrm_queue_cos2bw_cfg_input {
13509 * This value indicates what type of request this is. The format for the
13510 * rest of the command is determined by this field.
13512 uint16_t cmpl_ring;
13514 * This value indicates the what completion ring the request will be
13515 * optionally completed on. If the value is -1, then no CR completion
13516 * will be generated. Any other value must be a valid CR ring_id value
13517 * for this function.
13520 /* This value indicates the command sequence number. */
13521 uint16_t target_id;
13523 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
13524 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
13526 uint64_t resp_addr;
13528 * This is the host address where the response will be written when the
13529 * request is complete. This area must be 16B aligned and must be
13530 * cleared to zero before the request is made.
13535 * If this bit is set to 1, then all queue_id0 related parameters in
13536 * this command are valid.
13538 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID UINT32_C(0x1)
13540 * If this bit is set to 1, then all queue_id1 related parameters in
13541 * this command are valid.
13543 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID UINT32_C(0x2)
13545 * If this bit is set to 1, then all queue_id2 related parameters in
13546 * this command are valid.
13548 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID UINT32_C(0x4)
13550 * If this bit is set to 1, then all queue_id3 related parameters in
13551 * this command are valid.
13553 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID UINT32_C(0x8)
13555 * If this bit is set to 1, then all queue_id4 related parameters in
13556 * this command are valid.
13558 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID UINT32_C(0x10)
13560 * If this bit is set to 1, then all queue_id5 related parameters in
13561 * this command are valid.
13563 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID UINT32_C(0x20)
13565 * If this bit is set to 1, then all queue_id6 related parameters in
13566 * this command are valid.
13568 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID UINT32_C(0x40)
13570 * If this bit is set to 1, then all queue_id7 related parameters in
13571 * this command are valid.
13573 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID UINT32_C(0x80)
13576 * Port ID of port for which the table is being configured. The HWRM
13577 * needs to check whether this function is allowed to configure TC BW
13578 * assignment on this port.
13581 /* ID of CoS Queue 0. */
13583 uint32_t queue_id0_min_bw;
13585 * Minimum BW allocated to CoS Queue. The HWRM will translate this value
13586 * into byte counter and time interval used for this COS inside the
13589 /* The bandwidth value. */
13590 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
13591 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
13592 /* The granularity of the value (bits or bytes). */
13593 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE UINT32_C(0x10000000)
13594 /* Value is in bits. */
13595 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
13596 /* Value is in bytes. */
13597 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
13598 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES
13599 /* bw_value_unit is 3 b */
13600 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
13601 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29
13602 /* Value is in Mb or MB (base 10). */
13603 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
13604 /* Value is in Kb or KB (base 10). */
13605 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
13606 /* Value is in bits or bytes. */
13607 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
13608 /* Value is in Gb or GB (base 10). */
13609 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
13610 /* Value is in 1/100th of a percentage of total bandwidth. */
13611 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
13613 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
13614 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID
13615 uint32_t queue_id0_max_bw;
13617 * Maximum BW allocated to CoS Queue. The HWRM will translate this value
13618 * into byte counter and time interval used for this COS inside the
13621 /* The bandwidth value. */
13622 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
13623 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
13624 /* The granularity of the value (bits or bytes). */
13625 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE UINT32_C(0x10000000)
13626 /* Value is in bits. */
13627 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
13628 /* Value is in bytes. */
13629 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
13630 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES
13631 /* bw_value_unit is 3 b */
13632 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
13633 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29
13634 /* Value is in Mb or MB (base 10). */
13635 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
13636 /* Value is in Kb or KB (base 10). */
13637 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
13638 /* Value is in bits or bytes. */
13639 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
13640 /* Value is in Gb or GB (base 10). */
13641 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
13642 /* Value is in 1/100th of a percentage of total bandwidth. */
13643 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
13645 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
13646 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID
13647 uint8_t queue_id0_tsa_assign;
13648 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
13649 /* Strict Priority */
13650 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP UINT32_C(0x0)
13651 /* Enhanced Transmission Selection */
13652 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS UINT32_C(0x1)
13654 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
13656 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
13657 uint8_t queue_id0_pri_lvl;
13659 * Priority level for strict priority. Valid only when the tsa_assign is
13660 * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved.
13662 uint8_t queue_id0_bw_weight;
13664 * Weight used to allocate remaining BW for this COS after servicing
13665 * guaranteed bandwidths for all COS.
13668 /* ID of CoS Queue 1. */
13669 uint32_t queue_id1_min_bw;
13671 * Minimum BW allocated to CoS Queue. The HWRM will translate this value
13672 * into byte counter and time interval used for this COS inside the
13675 /* The bandwidth value. */
13676 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
13677 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0
13678 /* The granularity of the value (bits or bytes). */
13679 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE UINT32_C(0x10000000)
13680 /* Value is in bits. */
13681 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
13682 /* Value is in bytes. */
13683 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
13684 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES
13685 /* bw_value_unit is 3 b */
13686 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
13687 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29
13688 /* Value is in Mb or MB (base 10). */
13689 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
13690 /* Value is in Kb or KB (base 10). */
13691 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
13692 /* Value is in bits or bytes. */
13693 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
13694 /* Value is in Gb or GB (base 10). */
13695 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
13696 /* Value is in 1/100th of a percentage of total bandwidth. */
13697 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
13699 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
13700 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID
13701 uint32_t queue_id1_max_bw;
13703 * Maximum BW allocated to CoS queue. The HWRM will translate this value
13704 * into byte counter and time interval used for this COS inside the
13707 /* The bandwidth value. */
13708 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
13709 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0
13710 /* The granularity of the value (bits or bytes). */
13711 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE UINT32_C(0x10000000)
13712 /* Value is in bits. */
13713 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
13714 /* Value is in bytes. */
13715 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
13716 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES
13717 /* bw_value_unit is 3 b */
13718 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
13719 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29
13720 /* Value is in Mb or MB (base 10). */
13721 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
13722 /* Value is in Kb or KB (base 10). */
13723 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
13724 /* Value is in bits or bytes. */
13725 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
13726 /* Value is in Gb or GB (base 10). */
13727 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
13728 /* Value is in 1/100th of a percentage of total bandwidth. */
13729 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
13731 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
13732 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID
13733 uint8_t queue_id1_tsa_assign;
13734 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
13735 /* Strict Priority */
13736 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP UINT32_C(0x0)
13737 /* Enhanced Transmission Selection */
13738 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS UINT32_C(0x1)
13740 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
13742 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
13743 uint8_t queue_id1_pri_lvl;
13745 * Priority level for strict priority. Valid only when the tsa_assign is
13746 * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved.
13748 uint8_t queue_id1_bw_weight;
13750 * Weight used to allocate remaining BW for this COS after servicing
13751 * guaranteed bandwidths for all COS.
13754 /* ID of CoS Queue 2. */
13755 uint32_t queue_id2_min_bw;
13757 * Minimum BW allocated to CoS Queue. The HWRM will translate this value
13758 * into byte counter and time interval used for this COS inside the
13761 /* The bandwidth value. */
13762 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
13763 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0
13764 /* The granularity of the value (bits or bytes). */
13765 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE UINT32_C(0x10000000)
13766 /* Value is in bits. */
13767 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
13768 /* Value is in bytes. */
13769 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
13770 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES
13771 /* bw_value_unit is 3 b */
13772 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
13773 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29
13774 /* Value is in Mb or MB (base 10). */
13775 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
13776 /* Value is in Kb or KB (base 10). */
13777 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
13778 /* Value is in bits or bytes. */
13779 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
13780 /* Value is in Gb or GB (base 10). */
13781 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
13782 /* Value is in 1/100th of a percentage of total bandwidth. */
13783 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
13785 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
13786 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID
13787 uint32_t queue_id2_max_bw;
13789 * Maximum BW allocated to CoS queue. The HWRM will translate this value
13790 * into byte counter and time interval used for this COS inside the
13793 /* The bandwidth value. */
13794 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
13795 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0
13796 /* The granularity of the value (bits or bytes). */
13797 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE UINT32_C(0x10000000)
13798 /* Value is in bits. */
13799 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
13800 /* Value is in bytes. */
13801 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
13802 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES
13803 /* bw_value_unit is 3 b */
13804 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
13805 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29
13806 /* Value is in Mb or MB (base 10). */
13807 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
13808 /* Value is in Kb or KB (base 10). */
13809 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
13810 /* Value is in bits or bytes. */
13811 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
13812 /* Value is in Gb or GB (base 10). */
13813 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
13814 /* Value is in 1/100th of a percentage of total bandwidth. */
13815 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
13817 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
13818 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID
13819 uint8_t queue_id2_tsa_assign;
13820 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
13821 /* Strict Priority */
13822 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP UINT32_C(0x0)
13823 /* Enhanced Transmission Selection */
13824 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS UINT32_C(0x1)
13826 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
13828 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
13829 uint8_t queue_id2_pri_lvl;
13831 * Priority level for strict priority. Valid only when the tsa_assign is
13832 * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved.
13834 uint8_t queue_id2_bw_weight;
13836 * Weight used to allocate remaining BW for this COS after servicing
13837 * guaranteed bandwidths for all COS.
13840 /* ID of CoS Queue 3. */
13841 uint32_t queue_id3_min_bw;
13843 * Minimum BW allocated to CoS Queue. The HWRM will translate this value
13844 * into byte counter and time interval used for this COS inside the
13847 /* The bandwidth value. */
13848 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
13849 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0
13850 /* The granularity of the value (bits or bytes). */
13851 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE UINT32_C(0x10000000)
13852 /* Value is in bits. */
13853 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
13854 /* Value is in bytes. */
13855 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
13856 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES
13857 /* bw_value_unit is 3 b */
13858 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
13859 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29
13860 /* Value is in Mb or MB (base 10). */
13861 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
13862 /* Value is in Kb or KB (base 10). */
13863 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
13864 /* Value is in bits or bytes. */
13865 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
13866 /* Value is in Gb or GB (base 10). */
13867 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
13868 /* Value is in 1/100th of a percentage of total bandwidth. */
13869 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
13871 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
13872 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID
13873 uint32_t queue_id3_max_bw;
13875 * Maximum BW allocated to CoS queue. The HWRM will translate this value
13876 * into byte counter and time interval used for this COS inside the
13879 /* The bandwidth value. */
13880 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
13881 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0
13882 /* The granularity of the value (bits or bytes). */
13883 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE UINT32_C(0x10000000)
13884 /* Value is in bits. */
13885 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
13886 /* Value is in bytes. */
13887 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
13888 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES
13889 /* bw_value_unit is 3 b */
13890 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
13891 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29
13892 /* Value is in Mb or MB (base 10). */
13893 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
13894 /* Value is in Kb or KB (base 10). */
13895 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
13896 /* Value is in bits or bytes. */
13897 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
13898 /* Value is in Gb or GB (base 10). */
13899 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
13900 /* Value is in 1/100th of a percentage of total bandwidth. */
13901 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
13903 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
13904 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID
13905 uint8_t queue_id3_tsa_assign;
13906 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
13907 /* Strict Priority */
13908 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP UINT32_C(0x0)
13909 /* Enhanced Transmission Selection */
13910 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS UINT32_C(0x1)
13912 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
13914 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
13915 uint8_t queue_id3_pri_lvl;
13917 * Priority level for strict priority. Valid only when the tsa_assign is
13918 * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved.
13920 uint8_t queue_id3_bw_weight;
13922 * Weight used to allocate remaining BW for this COS after servicing
13923 * guaranteed bandwidths for all COS.
13926 /* ID of CoS Queue 4. */
13927 uint32_t queue_id4_min_bw;
13929 * Minimum BW allocated to CoS Queue. The HWRM will translate this value
13930 * into byte counter and time interval used for this COS inside the
13933 /* The bandwidth value. */
13934 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
13935 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0
13936 /* The granularity of the value (bits or bytes). */
13937 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE UINT32_C(0x10000000)
13938 /* Value is in bits. */
13939 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
13940 /* Value is in bytes. */
13941 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
13942 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES
13943 /* bw_value_unit is 3 b */
13944 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
13945 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29
13946 /* Value is in Mb or MB (base 10). */
13947 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
13948 /* Value is in Kb or KB (base 10). */
13949 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
13950 /* Value is in bits or bytes. */
13951 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
13952 /* Value is in Gb or GB (base 10). */
13953 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
13954 /* Value is in 1/100th of a percentage of total bandwidth. */
13955 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
13957 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
13958 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID
13959 uint32_t queue_id4_max_bw;
13961 * Maximum BW allocated to CoS queue. The HWRM will translate this value
13962 * into byte counter and time interval used for this COS inside the
13965 /* The bandwidth value. */
13966 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
13967 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0
13968 /* The granularity of the value (bits or bytes). */
13969 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE UINT32_C(0x10000000)
13970 /* Value is in bits. */
13971 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
13972 /* Value is in bytes. */
13973 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
13974 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES
13975 /* bw_value_unit is 3 b */
13976 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
13977 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29
13978 /* Value is in Mb or MB (base 10). */
13979 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
13980 /* Value is in Kb or KB (base 10). */
13981 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
13982 /* Value is in bits or bytes. */
13983 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
13984 /* Value is in Gb or GB (base 10). */
13985 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
13986 /* Value is in 1/100th of a percentage of total bandwidth. */
13987 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
13989 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
13990 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID
13991 uint8_t queue_id4_tsa_assign;
13992 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
13993 /* Strict Priority */
13994 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP UINT32_C(0x0)
13995 /* Enhanced Transmission Selection */
13996 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS UINT32_C(0x1)
13998 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
14000 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
14001 uint8_t queue_id4_pri_lvl;
14003 * Priority level for strict priority. Valid only when the tsa_assign is
14004 * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved.
14006 uint8_t queue_id4_bw_weight;
14008 * Weight used to allocate remaining BW for this COS after servicing
14009 * guaranteed bandwidths for all COS.
14012 /* ID of CoS Queue 5. */
14013 uint32_t queue_id5_min_bw;
14015 * Minimum BW allocated to CoS Queue. The HWRM will translate this value
14016 * into byte counter and time interval used for this COS inside the
14019 /* The bandwidth value. */
14020 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
14021 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0
14022 /* The granularity of the value (bits or bytes). */
14023 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE UINT32_C(0x10000000)
14024 /* Value is in bits. */
14025 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
14026 /* Value is in bytes. */
14027 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
14028 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES
14029 /* bw_value_unit is 3 b */
14030 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
14031 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29
14032 /* Value is in Mb or MB (base 10). */
14033 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
14034 /* Value is in Kb or KB (base 10). */
14035 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
14036 /* Value is in bits or bytes. */
14037 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
14038 /* Value is in Gb or GB (base 10). */
14039 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
14040 /* Value is in 1/100th of a percentage of total bandwidth. */
14041 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
14043 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
14044 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID
14045 uint32_t queue_id5_max_bw;
14047 * Maximum BW allocated to CoS queue. The HWRM will translate this value
14048 * into byte counter and time interval used for this COS inside the
14051 /* The bandwidth value. */
14052 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
14053 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0
14054 /* The granularity of the value (bits or bytes). */
14055 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE UINT32_C(0x10000000)
14056 /* Value is in bits. */
14057 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
14058 /* Value is in bytes. */
14059 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
14060 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES
14061 /* bw_value_unit is 3 b */
14062 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
14063 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29
14064 /* Value is in Mb or MB (base 10). */
14065 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
14066 /* Value is in Kb or KB (base 10). */
14067 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
14068 /* Value is in bits or bytes. */
14069 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
14070 /* Value is in Gb or GB (base 10). */
14071 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
14072 /* Value is in 1/100th of a percentage of total bandwidth. */
14073 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
14075 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
14076 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID
14077 uint8_t queue_id5_tsa_assign;
14078 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
14079 /* Strict Priority */
14080 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP UINT32_C(0x0)
14081 /* Enhanced Transmission Selection */
14082 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS UINT32_C(0x1)
14084 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
14086 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
14087 uint8_t queue_id5_pri_lvl;
14089 * Priority level for strict priority. Valid only when the tsa_assign is
14090 * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved.
14092 uint8_t queue_id5_bw_weight;
14094 * Weight used to allocate remaining BW for this COS after servicing
14095 * guaranteed bandwidths for all COS.
14098 /* ID of CoS Queue 6. */
14099 uint32_t queue_id6_min_bw;
14101 * Minimum BW allocated to CoS Queue. The HWRM will translate this value
14102 * into byte counter and time interval used for this COS inside the
14105 /* The bandwidth value. */
14106 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
14107 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0
14108 /* The granularity of the value (bits or bytes). */
14109 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE UINT32_C(0x10000000)
14110 /* Value is in bits. */
14111 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
14112 /* Value is in bytes. */
14113 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
14114 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES
14115 /* bw_value_unit is 3 b */
14116 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
14117 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29
14118 /* Value is in Mb or MB (base 10). */
14119 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
14120 /* Value is in Kb or KB (base 10). */
14121 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
14122 /* Value is in bits or bytes. */
14123 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
14124 /* Value is in Gb or GB (base 10). */
14125 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
14126 /* Value is in 1/100th of a percentage of total bandwidth. */
14127 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
14129 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
14130 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID
14131 uint32_t queue_id6_max_bw;
14133 * Maximum BW allocated to CoS queue. The HWRM will translate this value
14134 * into byte counter and time interval used for this COS inside the
14137 /* The bandwidth value. */
14138 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
14139 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0
14140 /* The granularity of the value (bits or bytes). */
14141 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE UINT32_C(0x10000000)
14142 /* Value is in bits. */
14143 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
14144 /* Value is in bytes. */
14145 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
14146 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES
14147 /* bw_value_unit is 3 b */
14148 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
14149 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29
14150 /* Value is in Mb or MB (base 10). */
14151 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
14152 /* Value is in Kb or KB (base 10). */
14153 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
14154 /* Value is in bits or bytes. */
14155 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
14156 /* Value is in Gb or GB (base 10). */
14157 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
14158 /* Value is in 1/100th of a percentage of total bandwidth. */
14159 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
14161 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
14162 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID
14163 uint8_t queue_id6_tsa_assign;
14164 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
14165 /* Strict Priority */
14166 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP UINT32_C(0x0)
14167 /* Enhanced Transmission Selection */
14168 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS UINT32_C(0x1)
14170 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
14172 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
14173 uint8_t queue_id6_pri_lvl;
14175 * Priority level for strict priority. Valid only when the tsa_assign is
14176 * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved.
14178 uint8_t queue_id6_bw_weight;
14180 * Weight used to allocate remaining BW for this COS after servicing
14181 * guaranteed bandwidths for all COS.
14184 /* ID of CoS Queue 7. */
14185 uint32_t queue_id7_min_bw;
14187 * Minimum BW allocated to CoS Queue. The HWRM will translate this value
14188 * into byte counter and time interval used for this COS inside the
14191 /* The bandwidth value. */
14192 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
14193 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0
14194 /* The granularity of the value (bits or bytes). */
14195 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE UINT32_C(0x10000000)
14196 /* Value is in bits. */
14197 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
14198 /* Value is in bytes. */
14199 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
14200 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES
14201 /* bw_value_unit is 3 b */
14202 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
14203 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29
14204 /* Value is in Mb or MB (base 10). */
14205 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
14206 /* Value is in Kb or KB (base 10). */
14207 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
14208 /* Value is in bits or bytes. */
14209 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
14210 /* Value is in Gb or GB (base 10). */
14211 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
14212 /* Value is in 1/100th of a percentage of total bandwidth. */
14213 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
14215 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
14216 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID
14217 uint32_t queue_id7_max_bw;
14219 * Maximum BW allocated to CoS queue. The HWRM will translate this value
14220 * into byte counter and time interval used for this COS inside the
14223 /* The bandwidth value. */
14224 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
14225 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0
14226 /* The granularity of the value (bits or bytes). */
14227 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE UINT32_C(0x10000000)
14228 /* Value is in bits. */
14229 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
14230 /* Value is in bytes. */
14231 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
14232 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES
14233 /* bw_value_unit is 3 b */
14234 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
14235 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29
14236 /* Value is in Mb or MB (base 10). */
14237 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
14238 /* Value is in Kb or KB (base 10). */
14239 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
14240 /* Value is in bits or bytes. */
14241 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
14242 /* Value is in Gb or GB (base 10). */
14243 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
14244 /* Value is in 1/100th of a percentage of total bandwidth. */
14245 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
14247 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
14248 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID
14249 uint8_t queue_id7_tsa_assign;
14250 /* Transmission Selection Algorithm (TSA) for CoS Queue. */
14251 /* Strict Priority */
14252 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP UINT32_C(0x0)
14253 /* Enhanced Transmission Selection */
14254 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS UINT32_C(0x1)
14256 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
14258 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
14259 uint8_t queue_id7_pri_lvl;
14261 * Priority level for strict priority. Valid only when the tsa_assign is
14262 * 0 - Strict Priority (SP) 0..7 - Valid values. 8..255 - Reserved.
14264 uint8_t queue_id7_bw_weight;
14266 * Weight used to allocate remaining BW for this COS after servicing
14267 * guaranteed bandwidths for all COS.
14269 uint8_t unused_1[5];
14270 } __attribute__((packed));
14272 /* Output (16 bytes) */
14274 struct hwrm_queue_cos2bw_cfg_output {
14275 uint16_t error_code;
14277 * Pass/Fail or error type Note: receiver to verify the in parameters,
14278 * and fail the call with an error when appropriate
14281 /* This field returns the type of original request. */
14283 /* This field provides original sequence number of the command. */
14286 * This field is the length of the response in bytes. The last byte of
14287 * the response is a valid flag that will read as '1' when the command
14288 * has been completely written to memory.
14296 * This field is used in Output records to indicate that the output is
14297 * completely written to RAM. This field should be read as '1' to
14298 * indicate that the output has been completely written. When writing a
14299 * command completion or response to an internal processor, the order of
14300 * writes has to be such that this field is written last.
14302 } __attribute__((packed));
14304 /* hwrm_queue_dscp_qcaps */
14306 * Description: This command is called by a driver to query the DSCP
14307 * capabilities for a port.
14309 /* Input (24 bytes) */
14311 struct hwrm_queue_dscp_qcaps_input {
14314 * This value indicates what type of request this is. The format for the
14315 * rest of the command is determined by this field.
14317 uint16_t cmpl_ring;
14319 * This value indicates the what completion ring the request will be
14320 * optionally completed on. If the value is -1, then no CR completion
14321 * will be generated. Any other value must be a valid CR ring_id value
14322 * for this function.
14325 /* This value indicates the command sequence number. */
14326 uint16_t target_id;
14328 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
14329 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
14331 uint64_t resp_addr;
14333 * This is the host address where the response will be written when the
14334 * request is complete. This area must be 16B aligned and must be
14335 * cleared to zero before the request is made.
14339 * Port ID of port for which the table is being configured. The HWRM
14340 * needs to check whether this function is allowed to configure pri2cos
14341 * mapping on this port.
14343 uint8_t unused_0[7];
14344 } __attribute__((packed));
14346 /* Output (16 bytes) */
14348 struct hwrm_queue_dscp_qcaps_output {
14349 uint16_t error_code;
14351 * Pass/Fail or error type Note: receiver to verify the in parameters,
14352 * and fail the call with an error when appropriate
14355 /* This field returns the type of original request. */
14357 /* This field provides original sequence number of the command. */
14360 * This field is the length of the response in bytes. The last byte of
14361 * the response is a valid flag that will read as '1' when the command
14362 * has been completely written to memory.
14364 uint8_t num_dscp_bits;
14365 /* The number of bits provided by the hardware for the DSCP value. */
14367 uint16_t max_entries;
14368 /* Max number of DSCP-MASK-PRI entries supported. */
14374 * This field is used in Output records to indicate that the output is
14375 * completely written to RAM. This field should be read as '1' to
14376 * indicate that the output has been completely written. When writing a
14377 * command completion or response to an internal processor, the order of
14378 * writes has to be such that this field is written last.
14380 } __attribute__((packed));
14382 /* hwrm_queue_dscp2pri_qcfg */
14384 * Description: This command is called by a driver to query configuration of the
14385 * DSCP to PRI mapping on the receive side. This mapping can be different on
14388 /* Input (32 bytes) */
14390 struct hwrm_queue_dscp2pri_qcfg_input {
14393 * This value indicates what type of request this is. The format for the
14394 * rest of the command is determined by this field.
14396 uint16_t cmpl_ring;
14398 * This value indicates the what completion ring the request will be
14399 * optionally completed on. If the value is -1, then no CR completion
14400 * will be generated. Any other value must be a valid CR ring_id value
14401 * for this function.
14404 /* This value indicates the command sequence number. */
14405 uint16_t target_id;
14407 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
14408 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
14410 uint64_t resp_addr;
14412 * This is the host address where the response will be written when the
14413 * request is complete. This area must be 16B aligned and must be
14414 * cleared to zero before the request is made.
14416 uint64_t dest_data_addr;
14418 * This is the host address where the 24-bits DSCP-MASK-PRI tuple(s)
14419 * will be copied to.
14423 * Port ID of port for which the table is being configured. The HWRM
14424 * needs to check whether this function is allowed to configure pri2cos
14425 * mapping on this port.
14428 uint16_t dest_data_buffer_size;
14429 /* Size of the buffer pointed to by dest_data_addr. */
14431 } __attribute__((packed));
14433 /* Output (16 bytes) */
14435 struct hwrm_queue_dscp2pri_qcfg_output {
14436 uint16_t error_code;
14438 * Pass/Fail or error type Note: receiver to verify the in parameters,
14439 * and fail the call with an error when appropriate
14442 /* This field returns the type of original request. */
14444 /* This field provides original sequence number of the command. */
14447 * This field is the length of the response in bytes. The last byte of
14448 * the response is a valid flag that will read as '1' when the command
14449 * has been completely written to memory.
14451 uint16_t entry_cnt;
14453 * A count of the number of DSCP-MASK-PRI tuple(s) pointed to by the
14456 uint8_t default_pri;
14458 * This is the default PRI which un-initialized DSCP values are mapped
14467 * This field is used in Output records to indicate that the output is
14468 * completely written to RAM. This field should be read as '1' to
14469 * indicate that the output has been completely written. When writing a
14470 * command completion or response to an internal processor, the order of
14471 * writes has to be such that this field is written last.
14473 } __attribute__((packed));
14475 /* hwrm_queue_dscp2pri_cfg */
14477 * Description: This command is called by a driver to configure the DSCP to PRI
14478 * mapping on the receive side. This mapping can be different on different
14481 /* Input (40 bytes) */
14483 struct hwrm_queue_dscp2pri_cfg_input {
14486 * This value indicates what type of request this is. The format for the
14487 * rest of the command is determined by this field.
14489 uint16_t cmpl_ring;
14491 * This value indicates the what completion ring the request will be
14492 * optionally completed on. If the value is -1, then no CR completion
14493 * will be generated. Any other value must be a valid CR ring_id value
14494 * for this function.
14497 /* This value indicates the command sequence number. */
14498 uint16_t target_id;
14500 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
14501 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
14503 uint64_t resp_addr;
14505 * This is the host address where the response will be written when the
14506 * request is complete. This area must be 16B aligned and must be
14507 * cleared to zero before the request is made.
14509 uint64_t src_data_addr;
14511 * This is the host address where the 24-bits DSCP-MASK-PRI tuple will
14515 /* use_hw_default_pri is 1 b */
14516 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI UINT32_C(0x1)
14518 /* This bit must be '1' for the default_pri field to be configured. */
14519 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI UINT32_C(0x1)
14522 * Port ID of port for which the table is being configured. The HWRM
14523 * needs to check whether this function is allowed to configure pri2cos
14524 * mapping on this port.
14526 uint8_t default_pri;
14528 * This is the default PRI which un-initialized DSCP values will be
14531 uint16_t entry_cnt;
14533 * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed
14534 * to by src_data_addr.
14537 } __attribute__((packed));
14539 /* Output (16 bytes) */
14541 struct hwrm_queue_dscp2pri_cfg_output {
14542 uint16_t error_code;
14544 * Pass/Fail or error type Note: receiver to verify the in parameters,
14545 * and fail the call with an error when appropriate
14548 /* This field returns the type of original request. */
14550 /* This field provides original sequence number of the command. */
14553 * This field is the length of the response in bytes. The last byte of
14554 * the response is a valid flag that will read as '1' when the command
14555 * has been completely written to memory.
14563 * This field is used in Output records to indicate that the output is
14564 * completely written to RAM. This field should be read as '1' to
14565 * indicate that the output has been completely written. When writing a
14566 * command completion or response to an internal processor, the order of
14567 * writes has to be such that this field is written last.
14569 } __attribute__((packed));
14571 /* hwrm_vnic_alloc */
14573 * Description: This VNIC is a resource in the RX side of the chip that is used
14574 * to represent a virtual host "interface". # At the time of VNIC allocation or
14575 * configuration, the function can specify whether it wants the requested VNIC
14576 * to be the default VNIC for the function or not. # If a function requests
14577 * allocation of a VNIC for the first time and a VNIC is successfully allocated
14578 * by the HWRM, then the HWRM shall make the allocated VNIC as the default VNIC
14579 * for that function. # The default VNIC shall be used for the default action
14580 * for a partition or function. # For each VNIC allocated on a function, a
14581 * mapping on the RX side to map the allocated VNIC to source virtual interface
14582 * shall be performed by the HWRM. This should be hidden to the function driver
14583 * requesting the VNIC allocation. This enables broadcast/multicast replication
14584 * with source knockout. # If multicast replication with source knockout is
14585 * enabled, then the internal VNIC to SVIF mapping data structures shall be
14586 * programmed at the time of VNIC allocation.
14588 /* Input (24 bytes) */
14590 struct hwrm_vnic_alloc_input {
14593 * This value indicates what type of request this is. The format for the
14594 * rest of the command is determined by this field.
14596 uint16_t cmpl_ring;
14598 * This value indicates the what completion ring the request will be
14599 * optionally completed on. If the value is -1, then no CR completion
14600 * will be generated. Any other value must be a valid CR ring_id value
14601 * for this function.
14604 /* This value indicates the command sequence number. */
14605 uint16_t target_id;
14607 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
14608 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
14610 uint64_t resp_addr;
14612 * This is the host address where the response will be written when the
14613 * request is complete. This area must be 16B aligned and must be
14614 * cleared to zero before the request is made.
14618 * When this bit is '1', this VNIC is requested to be the default VNIC
14619 * for this function.
14621 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
14623 } __attribute__((packed));
14625 /* Output (16 bytes) */
14627 struct hwrm_vnic_alloc_output {
14628 uint16_t error_code;
14630 * Pass/Fail or error type Note: receiver to verify the in parameters,
14631 * and fail the call with an error when appropriate
14634 /* This field returns the type of original request. */
14636 /* This field provides original sequence number of the command. */
14639 * This field is the length of the response in bytes. The last byte of
14640 * the response is a valid flag that will read as '1' when the command
14641 * has been completely written to memory.
14644 /* Logical vnic ID */
14650 * This field is used in Output records to indicate that the output is
14651 * completely written to RAM. This field should be read as '1' to
14652 * indicate that the output has been completely written. When writing a
14653 * command completion or response to an internal processor, the order of
14654 * writes has to be such that this field is written last.
14656 } __attribute__((packed));
14658 /* hwrm_vnic_free */
14660 * Description: Free a VNIC resource. Idle any resources associated with the
14661 * VNIC as well as the VNIC. Reset and release all resources associated with the
14664 /* Input (24 bytes) */
14666 struct hwrm_vnic_free_input {
14669 * This value indicates what type of request this is. The format for the
14670 * rest of the command is determined by this field.
14672 uint16_t cmpl_ring;
14674 * This value indicates the what completion ring the request will be
14675 * optionally completed on. If the value is -1, then no CR completion
14676 * will be generated. Any other value must be a valid CR ring_id value
14677 * for this function.
14680 /* This value indicates the command sequence number. */
14681 uint16_t target_id;
14683 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
14684 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
14686 uint64_t resp_addr;
14688 * This is the host address where the response will be written when the
14689 * request is complete. This area must be 16B aligned and must be
14690 * cleared to zero before the request is made.
14693 /* Logical vnic ID */
14695 } __attribute__((packed));
14697 /* Output (16 bytes) */
14699 struct hwrm_vnic_free_output {
14700 uint16_t error_code;
14702 * Pass/Fail or error type Note: receiver to verify the in parameters,
14703 * and fail the call with an error when appropriate
14706 /* This field returns the type of original request. */
14708 /* This field provides original sequence number of the command. */
14711 * This field is the length of the response in bytes. The last byte of
14712 * the response is a valid flag that will read as '1' when the command
14713 * has been completely written to memory.
14721 * This field is used in Output records to indicate that the output is
14722 * completely written to RAM. This field should be read as '1' to
14723 * indicate that the output has been completely written. When writing a
14724 * command completion or response to an internal processor, the order of
14725 * writes has to be such that this field is written last.
14727 } __attribute__((packed));
14729 /* hwrm_vnic_cfg */
14730 /* Description: Configure the RX VNIC structure. */
14731 /* Input (40 bytes) */
14733 struct hwrm_vnic_cfg_input {
14736 * This value indicates what type of request this is. The format for the
14737 * rest of the command is determined by this field.
14739 uint16_t cmpl_ring;
14741 * This value indicates the what completion ring the request will be
14742 * optionally completed on. If the value is -1, then no CR completion
14743 * will be generated. Any other value must be a valid CR ring_id value
14744 * for this function.
14747 /* This value indicates the command sequence number. */
14748 uint16_t target_id;
14750 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
14751 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
14753 uint64_t resp_addr;
14755 * This is the host address where the response will be written when the
14756 * request is complete. This area must be 16B aligned and must be
14757 * cleared to zero before the request is made.
14761 * When this bit is '1', the VNIC is requested to be the default VNIC
14762 * for the function.
14764 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
14766 * When this bit is '1', the VNIC is being configured to strip VLAN in
14767 * the RX path. If set to '0', then VLAN stripping is disabled on this
14770 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE UINT32_C(0x2)
14772 * When this bit is '1', the VNIC is being configured to buffer receive
14773 * packets in the hardware until the host posts new receive buffers. If
14774 * set to '0', then bd_stall is being configured to be disabled on this
14777 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE UINT32_C(0x4)
14779 * When this bit is '1', the VNIC is being configured to receive both
14780 * RoCE and non-RoCE traffic. If set to '0', then this VNIC is not
14781 * configured to be operating in dual VNIC mode.
14783 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE UINT32_C(0x8)
14785 * When this flag is set to '1', the VNIC is requested to be configured
14786 * to receive only RoCE traffic. If this flag is set to '0', then this
14787 * flag shall be ignored by the HWRM. If roce_dual_vnic_mode flag is set
14788 * to '1', then the HWRM client shall not set this flag to '1'.
14790 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE UINT32_C(0x10)
14792 * When a VNIC uses one destination ring group for certain application
14793 * (e.g. Receive Flow Steering) where exact match is used to direct
14794 * packets to a VNIC with one destination ring group only, there is no
14795 * need to configure RSS indirection table for that VNIC as only one
14796 * destination ring group is used. This flag is used to enable a mode
14797 * where RSS is enabled in the VNIC using a RSS context for computing
14798 * RSS hash but the RSS indirection table is not configured using
14799 * hwrm_vnic_rss_cfg. If this mode is enabled, then the driver should
14800 * not program RSS indirection table for the RSS context that is used
14801 * for computing RSS hash only.
14803 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE UINT32_C(0x20)
14805 /* This bit must be '1' for the dflt_ring_grp field to be configured. */
14806 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP UINT32_C(0x1)
14807 /* This bit must be '1' for the rss_rule field to be configured. */
14808 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE UINT32_C(0x2)
14809 /* This bit must be '1' for the cos_rule field to be configured. */
14810 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE UINT32_C(0x4)
14811 /* This bit must be '1' for the lb_rule field to be configured. */
14812 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE UINT32_C(0x8)
14813 /* This bit must be '1' for the mru field to be configured. */
14814 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU UINT32_C(0x10)
14816 /* Logical vnic ID */
14817 uint16_t dflt_ring_grp;
14819 * Default Completion ring for the VNIC. This ring will be chosen if
14820 * packet does not match any RSS rules and if there is no COS rule.
14824 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if there is no
14829 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if there is no
14834 * RSS ID for load balancing rule/table structure. 0xFF... (All Fs) if
14835 * there is no LB rule.
14839 * The maximum receive unit of the vnic. Each vnic is associated with a
14840 * function. The vnic mru value overwrites the mru setting of the
14841 * associated function. The HWRM shall make sure that vnic mru does not
14842 * exceed the mru of the port the function is associated with.
14845 } __attribute__((packed));
14847 /* Output (16 bytes) */
14849 struct hwrm_vnic_cfg_output {
14850 uint16_t error_code;
14852 * Pass/Fail or error type Note: receiver to verify the in parameters,
14853 * and fail the call with an error when appropriate
14856 /* This field returns the type of original request. */
14858 /* This field provides original sequence number of the command. */
14861 * This field is the length of the response in bytes. The last byte of
14862 * the response is a valid flag that will read as '1' when the command
14863 * has been completely written to memory.
14871 * This field is used in Output records to indicate that the output is
14872 * completely written to RAM. This field should be read as '1' to
14873 * indicate that the output has been completely written. When writing a
14874 * command completion or response to an internal processor, the order of
14875 * writes has to be such that this field is written last.
14877 } __attribute__((packed));
14879 /* hwrm_vnic_qcfg */
14881 * Description: Query the RX VNIC structure. This function can be used by a PF
14882 * driver to query its own VNIC resource or VNIC resource of its child VF. This
14883 * function can also be used by a VF driver to query its own VNIC resource.
14885 /* Input (32 bytes) */
14887 struct hwrm_vnic_qcfg_input {
14890 * This value indicates what type of request this is. The format for the
14891 * rest of the command is determined by this field.
14893 uint16_t cmpl_ring;
14895 * This value indicates the what completion ring the request will be
14896 * optionally completed on. If the value is -1, then no CR completion
14897 * will be generated. Any other value must be a valid CR ring_id value
14898 * for this function.
14901 /* This value indicates the command sequence number. */
14902 uint16_t target_id;
14904 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
14905 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
14907 uint64_t resp_addr;
14909 * This is the host address where the response will be written when the
14910 * request is complete. This area must be 16B aligned and must be
14911 * cleared to zero before the request is made.
14914 /* This bit must be '1' for the vf_id_valid field to be configured. */
14915 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
14917 /* Logical vnic ID */
14919 /* ID of Virtual Function whose VNIC resource is being queried. */
14920 uint16_t unused_0[3];
14921 } __attribute__((packed));
14923 /* Output (32 bytes) */
14925 struct hwrm_vnic_qcfg_output {
14926 uint16_t error_code;
14928 * Pass/Fail or error type Note: receiver to verify the in parameters,
14929 * and fail the call with an error when appropriate
14932 /* This field returns the type of original request. */
14934 /* This field provides original sequence number of the command. */
14937 * This field is the length of the response in bytes. The last byte of
14938 * the response is a valid flag that will read as '1' when the command
14939 * has been completely written to memory.
14941 uint16_t dflt_ring_grp;
14942 /* Default Completion ring for the VNIC. */
14945 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if there is no
14950 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if there is no
14955 * RSS ID for load balancing rule/table structure. 0xFF... (All Fs) if
14956 * there is no LB rule.
14959 /* The maximum receive unit of the vnic. */
14963 /* When this bit is '1', the VNIC is the default VNIC for the function. */
14964 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT UINT32_C(0x1)
14966 * When this bit is '1', the VNIC is configured to strip VLAN in the RX
14967 * path. If set to '0', then VLAN stripping is disabled on this VNIC.
14969 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE UINT32_C(0x2)
14971 * When this bit is '1', the VNIC is configured to buffer receive
14972 * packets in the hardware until the host posts new receive buffers. If
14973 * set to '0', then bd_stall is disabled on this VNIC.
14975 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE UINT32_C(0x4)
14977 * When this bit is '1', the VNIC is configured to receive both RoCE and
14978 * non-RoCE traffic. If set to '0', then this VNIC is not configured to
14979 * operate in dual VNIC mode.
14981 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE UINT32_C(0x8)
14983 * When this flag is set to '1', the VNIC is configured to receive only
14984 * RoCE traffic. When this flag is set to '0', the VNIC is not
14985 * configured to receive only RoCE traffic. If roce_dual_vnic_mode flag
14986 * and this flag both are set to '1', then it is an invalid
14987 * configuration of the VNIC. The HWRM should not allow that type of
14988 * mis-configuration by HWRM clients.
14990 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE UINT32_C(0x10)
14992 * When a VNIC uses one destination ring group for certain application
14993 * (e.g. Receive Flow Steering) where exact match is used to direct
14994 * packets to a VNIC with one destination ring group only, there is no
14995 * need to configure RSS indirection table for that VNIC as only one
14996 * destination ring group is used. When this bit is set to '1', then the
14997 * VNIC is enabled in a mode where RSS is enabled in the VNIC using a
14998 * RSS context for computing RSS hash but the RSS indirection table is
15001 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE UINT32_C(0x20)
15008 * This field is used in Output records to indicate that the output is
15009 * completely written to RAM. This field should be read as '1' to
15010 * indicate that the output has been completely written. When writing a
15011 * command completion or response to an internal processor, the order of
15012 * writes has to be such that this field is written last.
15014 } __attribute__((packed));
15016 /* hwrm_vnic_qcaps */
15018 * Description: This function is used to query the capabilities of VNIC
15021 /* Input (24 bytes) */
15023 struct hwrm_vnic_qcaps_input {
15026 * This value indicates what type of request this is. The format for the
15027 * rest of the command is determined by this field.
15029 uint16_t cmpl_ring;
15031 * This value indicates the what completion ring the request will be
15032 * optionally completed on. If the value is -1, then no CR completion
15033 * will be generated. Any other value must be a valid CR ring_id value
15034 * for this function.
15037 /* This value indicates the command sequence number. */
15038 uint16_t target_id;
15040 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
15041 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
15043 uint64_t resp_addr;
15045 * This is the host address where the response will be written when the
15046 * request is complete. This area must be 16B aligned and must be
15047 * cleared to zero before the request is made.
15051 } __attribute__((packed));
15053 /* Output (24 bytes) */
15055 struct hwrm_vnic_qcaps_output {
15056 uint16_t error_code;
15058 * Pass/Fail or error type Note: receiver to verify the in parameters,
15059 * and fail the call with an error when appropriate
15062 /* This field returns the type of original request. */
15064 /* This field provides original sequence number of the command. */
15067 * This field is the length of the response in bytes. The last byte of
15068 * the response is a valid flag that will read as '1' when the command
15069 * has been completely written to memory.
15072 /* The maximum receive unit that is settable on a vnic. */
15077 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED UINT32_C(0x1)
15079 * When this bit is '1', the capability of stripping VLAN in the RX path
15080 * is supported on VNIC(s). If set to '0', then VLAN stripping
15081 * capability is not supported on VNIC(s).
15083 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP UINT32_C(0x2)
15085 * When this bit is '1', the capability to buffer receive packets in the
15086 * hardware until the host posts new receive buffers is supported on
15087 * VNIC(s). If set to '0', then bd_stall capability is not supported on
15090 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP UINT32_C(0x4)
15092 * When this bit is '1', the capability to receive both RoCE and non-
15093 * RoCE traffic on VNIC(s) is supported. If set to '0', then the
15094 * capability to receive both RoCE and non-RoCE traffic on VNIC(s) is
15097 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP UINT32_C(0x8)
15099 * When this bit is set to '1', the capability to configure a VNIC to
15100 * receive only RoCE traffic is supported. When this flag is set to '0',
15101 * the VNIC capability to configure to receive only RoCE traffic is not
15104 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP UINT32_C(0x10)
15106 * When this bit is set to '1', then the capability to enable a VNIC in
15107 * a mode where RSS context without configuring RSS indirection table is
15108 * supported (for RSS hash computation). When this bit is set to '0',
15109 * then a VNIC can not be configured with a mode to enable RSS context
15110 * without configuring RSS indirection table.
15112 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP UINT32_C(0x20)
15119 * This field is used in Output records to indicate that the output is
15120 * completely written to RAM. This field should be read as '1' to
15121 * indicate that the output has been completely written. When writing a
15122 * command completion or response to an internal processor, the order of
15123 * writes has to be such that this field is written last.
15125 } __attribute__((packed));
15127 /* hwrm_vnic_tpa_cfg */
15128 /* Description: This function is used to enable/configure TPA on the VNIC. */
15129 /* Input (40 bytes) */
15131 struct hwrm_vnic_tpa_cfg_input {
15134 * This value indicates what type of request this is. The format for the
15135 * rest of the command is determined by this field.
15137 uint16_t cmpl_ring;
15139 * This value indicates the what completion ring the request will be
15140 * optionally completed on. If the value is -1, then no CR completion
15141 * will be generated. Any other value must be a valid CR ring_id value
15142 * for this function.
15145 /* This value indicates the command sequence number. */
15146 uint16_t target_id;
15148 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
15149 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
15151 uint64_t resp_addr;
15153 * This is the host address where the response will be written when the
15154 * request is complete. This area must be 16B aligned and must be
15155 * cleared to zero before the request is made.
15159 * When this bit is '1', the VNIC shall be configured to perform
15160 * transparent packet aggregation (TPA) of non-tunneled TCP packets.
15162 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA UINT32_C(0x1)
15164 * When this bit is '1', the VNIC shall be configured to perform
15165 * transparent packet aggregation (TPA) of tunneled TCP packets.
15167 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA UINT32_C(0x2)
15169 * When this bit is '1', the VNIC shall be configured to perform
15170 * transparent packet aggregation (TPA) according to Windows Receive
15171 * Segment Coalescing (RSC) rules.
15173 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE UINT32_C(0x4)
15175 * When this bit is '1', the VNIC shall be configured to perform
15176 * transparent packet aggregation (TPA) according to Linux Generic
15177 * Receive Offload (GRO) rules.
15179 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO UINT32_C(0x8)
15181 * When this bit is '1', the VNIC shall be configured to perform
15182 * transparent packet aggregation (TPA) for TCP packets with IP ECN set
15185 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN UINT32_C(0x10)
15187 * When this bit is '1', the VNIC shall be configured to perform
15188 * transparent packet aggregation (TPA) for GRE tunneled TCP packets
15189 * only if all packets have the same GRE sequence.
15191 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ UINT32_C(0x20)
15193 * When this bit is '1' and the GRO mode is enabled, the VNIC shall be
15194 * configured to perform transparent packet aggregation (TPA) for
15195 * TCP/IPv4 packets with consecutively increasing IPIDs. In other words,
15196 * the last packet that is being aggregated to an already existing
15197 * aggregation context shall have IPID 1 more than the IPID of the last
15198 * packet that was aggregated in that aggregation context.
15200 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK UINT32_C(0x40)
15202 * When this bit is '1' and the GRO mode is enabled, the VNIC shall be
15203 * configured to perform transparent packet aggregation (TPA) for TCP
15204 * packets with the same TTL (IPv4) or Hop limit (IPv6) value.
15206 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK UINT32_C(0x80)
15208 /* This bit must be '1' for the max_agg_segs field to be configured. */
15209 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
15210 /* This bit must be '1' for the max_aggs field to be configured. */
15211 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
15212 /* This bit must be '1' for the max_agg_timer field to be configured. */
15213 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
15214 /* This bit must be '1' for the min_agg_len field to be configured. */
15215 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
15217 /* Logical vnic ID */
15218 uint16_t max_agg_segs;
15220 * This is the maximum number of TCP segments that can be aggregated
15221 * (unit is Log2). Max value is 31.
15224 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
15226 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
15228 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
15230 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
15231 /* Any segment size larger than this is not valid */
15232 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
15235 * This is the maximum number of aggregations this VNIC is allowed (unit
15236 * is Log2). Max value is 7
15238 /* 1 aggregation */
15239 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
15240 /* 2 aggregations */
15241 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
15242 /* 4 aggregations */
15243 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
15244 /* 8 aggregations */
15245 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
15246 /* 16 aggregations */
15247 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
15248 /* Any aggregation size larger than this is not valid */
15249 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
15252 uint32_t max_agg_timer;
15254 * This is the maximum amount of time allowed for an aggregation context
15255 * to complete after it was initiated.
15257 uint32_t min_agg_len;
15259 * This is the minimum amount of payload length required to start an
15260 * aggregation context.
15262 } __attribute__((packed));
15264 /* Output (16 bytes) */
15266 struct hwrm_vnic_tpa_cfg_output {
15267 uint16_t error_code;
15269 * Pass/Fail or error type Note: receiver to verify the in parameters,
15270 * and fail the call with an error when appropriate
15273 /* This field returns the type of original request. */
15275 /* This field provides original sequence number of the command. */
15278 * This field is the length of the response in bytes. The last byte of
15279 * the response is a valid flag that will read as '1' when the command
15280 * has been completely written to memory.
15288 * This field is used in Output records to indicate that the output is
15289 * completely written to RAM. This field should be read as '1' to
15290 * indicate that the output has been completely written. When writing a
15291 * command completion or response to an internal processor, the order of
15292 * writes has to be such that this field is written last.
15294 } __attribute__((packed));
15296 /* hwrm_vnic_tpa_qcfg */
15298 * Description: This function can be used to query TPA configuration on the
15301 /* Input (24 bytes) */
15303 struct hwrm_vnic_tpa_qcfg_input {
15306 * This value indicates what type of request this is. The format for the
15307 * rest of the command is determined by this field.
15309 uint16_t cmpl_ring;
15311 * This value indicates the what completion ring the request will be
15312 * optionally completed on. If the value is -1, then no CR completion
15313 * will be generated. Any other value must be a valid CR ring_id value
15314 * for this function.
15317 /* This value indicates the command sequence number. */
15318 uint16_t target_id;
15320 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
15321 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
15323 uint64_t resp_addr;
15325 * This is the host address where the response will be written when the
15326 * request is complete. This area must be 16B aligned and must be
15327 * cleared to zero before the request is made.
15330 /* Logical vnic ID */
15331 uint16_t unused_0[3];
15332 } __attribute__((packed));
15334 /* Output (32 bytes) */
15336 struct hwrm_vnic_tpa_qcfg_output {
15337 uint16_t error_code;
15339 * Pass/Fail or error type Note: receiver to verify the in parameters,
15340 * and fail the call with an error when appropriate
15343 /* This field returns the type of original request. */
15345 /* This field provides original sequence number of the command. */
15348 * This field is the length of the response in bytes. The last byte of
15349 * the response is a valid flag that will read as '1' when the command
15350 * has been completely written to memory.
15354 * When this bit is '1', the VNIC is configured to perform transparent
15355 * packet aggregation (TPA) of non-tunneled TCP packets.
15357 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_TPA UINT32_C(0x1)
15359 * When this bit is '1', the VNIC is configured to perform transparent
15360 * packet aggregation (TPA) of tunneled TCP packets.
15362 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_ENCAP_TPA UINT32_C(0x2)
15364 * When this bit is '1', the VNIC is configured to perform transparent
15365 * packet aggregation (TPA) according to Windows Receive Segment
15366 * Coalescing (RSC) rules.
15368 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_RSC_WND_UPDATE UINT32_C(0x4)
15370 * When this bit is '1', the VNIC is configured to perform transparent
15371 * packet aggregation (TPA) according to Linux Generic Receive Offload
15374 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO UINT32_C(0x8)
15376 * When this bit is '1', the VNIC is configured to perform transparent
15377 * packet aggregation (TPA) for TCP packets with IP ECN set to non-zero.
15379 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_ECN UINT32_C(0x10)
15381 * When this bit is '1', the VNIC is configured to perform transparent
15382 * packet aggregation (TPA) for GRE tunneled TCP packets only if all
15383 * packets have the same GRE sequence.
15385 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ UINT32_C(0x20)
15387 * When this bit is '1' and the GRO mode is enabled, the VNIC is
15388 * configured to perform transparent packet aggregation (TPA) for
15389 * TCP/IPv4 packets with consecutively increasing IPIDs. In other words,
15390 * the last packet that is being aggregated to an already existing
15391 * aggregation context shall have IPID 1 more than the IPID of the last
15392 * packet that was aggregated in that aggregation context.
15394 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_IPID_CHECK UINT32_C(0x40)
15396 * When this bit is '1' and the GRO mode is enabled, the VNIC is
15397 * configured to perform transparent packet aggregation (TPA) for TCP
15398 * packets with the same TTL (IPv4) or Hop limit (IPv6) value.
15400 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_TTL_CHECK UINT32_C(0x80)
15401 uint16_t max_agg_segs;
15403 * This is the maximum number of TCP segments that can be aggregated
15404 * (unit is Log2). Max value is 31.
15407 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
15409 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
15411 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
15413 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
15414 /* Any segment size larger than this is not valid */
15415 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
15418 * This is the maximum number of aggregations this VNIC is allowed (unit
15419 * is Log2). Max value is 7
15421 /* 1 aggregation */
15422 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_1 UINT32_C(0x0)
15423 /* 2 aggregations */
15424 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_2 UINT32_C(0x1)
15425 /* 4 aggregations */
15426 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_4 UINT32_C(0x2)
15427 /* 8 aggregations */
15428 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_8 UINT32_C(0x3)
15429 /* 16 aggregations */
15430 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_16 UINT32_C(0x4)
15431 /* Any aggregation size larger than this is not valid */
15432 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX UINT32_C(0x7)
15433 uint32_t max_agg_timer;
15435 * This is the maximum amount of time allowed for an aggregation context
15436 * to complete after it was initiated.
15438 uint32_t min_agg_len;
15440 * This is the minimum amount of payload length required to start an
15441 * aggregation context.
15449 * This field is used in Output records to indicate that the output is
15450 * completely written to RAM. This field should be read as '1' to
15451 * indicate that the output has been completely written. When writing a
15452 * command completion or response to an internal processor, the order of
15453 * writes has to be such that this field is written last.
15455 } __attribute__((packed));
15457 /* hwrm_vnic_rss_cfg */
15458 /* Description: This function is used to enable RSS configuration. */
15459 /* Input (48 bytes) */
15461 struct hwrm_vnic_rss_cfg_input {
15464 * This value indicates what type of request this is. The format for the
15465 * rest of the command is determined by this field.
15467 uint16_t cmpl_ring;
15469 * This value indicates the what completion ring the request will be
15470 * optionally completed on. If the value is -1, then no CR completion
15471 * will be generated. Any other value must be a valid CR ring_id value
15472 * for this function.
15475 /* This value indicates the command sequence number. */
15476 uint16_t target_id;
15478 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
15479 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
15481 uint64_t resp_addr;
15483 * This is the host address where the response will be written when the
15484 * request is complete. This area must be 16B aligned and must be
15485 * cleared to zero before the request is made.
15487 uint32_t hash_type;
15489 * When this bit is '1', the RSS hash shall be computed over source and
15490 * destination IPv4 addresses of IPv4 packets.
15492 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
15494 * When this bit is '1', the RSS hash shall be computed over
15495 * source/destination IPv4 addresses and source/destination ports of
15496 * TCP/IPv4 packets.
15498 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
15500 * When this bit is '1', the RSS hash shall be computed over
15501 * source/destination IPv4 addresses and source/destination ports of
15502 * UDP/IPv4 packets.
15504 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
15506 * When this bit is '1', the RSS hash shall be computed over source and
15507 * destination IPv4 addresses of IPv6 packets.
15509 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
15511 * When this bit is '1', the RSS hash shall be computed over
15512 * source/destination IPv6 addresses and source/destination ports of
15513 * TCP/IPv6 packets.
15515 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
15517 * When this bit is '1', the RSS hash shall be computed over
15518 * source/destination IPv6 addresses and source/destination ports of
15519 * UDP/IPv6 packets.
15521 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
15523 uint64_t ring_grp_tbl_addr;
15524 /* This is the address for rss ring group table */
15525 uint64_t hash_key_tbl_addr;
15526 /* This is the address for rss hash key table */
15527 uint16_t rss_ctx_idx;
15528 /* Index to the rss indirection table. */
15529 uint16_t unused_1[3];
15530 } __attribute__((packed));
15532 /* Output (16 bytes) */
15534 struct hwrm_vnic_rss_cfg_output {
15535 uint16_t error_code;
15537 * Pass/Fail or error type Note: receiver to verify the in parameters,
15538 * and fail the call with an error when appropriate
15541 /* This field returns the type of original request. */
15543 /* This field provides original sequence number of the command. */
15546 * This field is the length of the response in bytes. The last byte of
15547 * the response is a valid flag that will read as '1' when the command
15548 * has been completely written to memory.
15556 * This field is used in Output records to indicate that the output is
15557 * completely written to RAM. This field should be read as '1' to
15558 * indicate that the output has been completely written. When writing a
15559 * command completion or response to an internal processor, the order of
15560 * writes has to be such that this field is written last.
15562 } __attribute__((packed));
15564 /* hwrm_vnic_rss_qcfg */
15565 /* Description: This function is used to query RSS context configuration. */
15566 /* Input (24 bytes) */
15568 struct hwrm_vnic_rss_qcfg_input {
15571 * This value indicates what type of request this is. The format for the
15572 * rest of the command is determined by this field.
15574 uint16_t cmpl_ring;
15576 * This value indicates the what completion ring the request will be
15577 * optionally completed on. If the value is -1, then no CR completion
15578 * will be generated. Any other value must be a valid CR ring_id value
15579 * for this function.
15582 /* This value indicates the command sequence number. */
15583 uint16_t target_id;
15585 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
15586 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
15588 uint64_t resp_addr;
15590 * This is the host address where the response will be written when the
15591 * request is complete. This area must be 16B aligned and must be
15592 * cleared to zero before the request is made.
15594 uint16_t rss_ctx_idx;
15595 /* Index to the rss indirection table. */
15596 uint16_t unused_0[3];
15597 } __attribute__((packed));
15599 /* Output (64 bytes) */
15601 struct hwrm_vnic_rss_qcfg_output {
15602 uint16_t error_code;
15604 * Pass/Fail or error type Note: receiver to verify the in parameters,
15605 * and fail the call with an error when appropriate
15608 /* This field returns the type of original request. */
15610 /* This field provides original sequence number of the command. */
15613 * This field is the length of the response in bytes. The last byte of
15614 * the response is a valid flag that will read as '1' when the command
15615 * has been completely written to memory.
15617 uint32_t hash_type;
15619 * When this bit is '1', the RSS hash shall be computed over source and
15620 * destination IPv4 addresses of IPv4 packets.
15622 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
15624 * When this bit is '1', the RSS hash shall be computed over
15625 * source/destination IPv4 addresses and source/destination ports of
15626 * TCP/IPv4 packets.
15628 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
15630 * When this bit is '1', the RSS hash shall be computed over
15631 * source/destination IPv4 addresses and source/destination ports of
15632 * UDP/IPv4 packets.
15634 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
15636 * When this bit is '1', the RSS hash shall be computed over source and
15637 * destination IPv4 addresses of IPv6 packets.
15639 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
15641 * When this bit is '1', the RSS hash shall be computed over
15642 * source/destination IPv6 addresses and source/destination ports of
15643 * TCP/IPv6 packets.
15645 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
15647 * When this bit is '1', the RSS hash shall be computed over
15648 * source/destination IPv6 addresses and source/destination ports of
15649 * UDP/IPv6 packets.
15651 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
15653 uint32_t hash_key[10];
15654 /* This is the value of rss hash key */
15661 * This field is used in Output records to indicate that the output is
15662 * completely written to RAM. This field should be read as '1' to
15663 * indicate that the output has been completely written. When writing a
15664 * command completion or response to an internal processor, the order of
15665 * writes has to be such that this field is written last.
15667 } __attribute__((packed));
15669 /* hwrm_vnic_plcmodes_cfg */
15671 * Description: This function can be used to set placement mode configuration of
15674 /* Input (40 bytes) */
15676 struct hwrm_vnic_plcmodes_cfg_input {
15679 * This value indicates what type of request this is. The format for the
15680 * rest of the command is determined by this field.
15682 uint16_t cmpl_ring;
15684 * This value indicates the what completion ring the request will be
15685 * optionally completed on. If the value is -1, then no CR completion
15686 * will be generated. Any other value must be a valid CR ring_id value
15687 * for this function.
15690 /* This value indicates the command sequence number. */
15691 uint16_t target_id;
15693 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
15694 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
15696 uint64_t resp_addr;
15698 * This is the host address where the response will be written when the
15699 * request is complete. This area must be 16B aligned and must be
15700 * cleared to zero before the request is made.
15704 * When this bit is '1', the VNIC shall be configured to use regular
15705 * placement algorithm. By default, the regular placement algorithm
15706 * shall be enabled on the VNIC.
15708 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT UINT32_C(0x1)
15710 * When this bit is '1', the VNIC shall be configured use the jumbo
15711 * placement algorithm.
15713 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT UINT32_C(0x2)
15715 * When this bit is '1', the VNIC shall be configured to enable Header-
15716 * Data split for IPv4 packets according to the following rules: # If
15717 * the packet is identified as TCP/IPv4, then the packet is split at the
15718 * beginning of the TCP payload. # If the packet is identified as
15719 * UDP/IPv4, then the packet is split at the beginning of UDP payload. #
15720 * If the packet is identified as non-TCP and non-UDP IPv4 packet, then
15721 * the packet is split at the beginning of the upper layer protocol
15722 * header carried in the IPv4 packet.
15724 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 UINT32_C(0x4)
15726 * When this bit is '1', the VNIC shall be configured to enable Header-
15727 * Data split for IPv6 packets according to the following rules: # If
15728 * the packet is identified as TCP/IPv6, then the packet is split at the
15729 * beginning of the TCP payload. # If the packet is identified as
15730 * UDP/IPv6, then the packet is split at the beginning of UDP payload. #
15731 * If the packet is identified as non-TCP and non-UDP IPv6 packet, then
15732 * the packet is split at the beginning of the upper layer protocol
15733 * header carried in the IPv6 packet.
15735 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 UINT32_C(0x8)
15737 * When this bit is '1', the VNIC shall be configured to enable Header-
15738 * Data split for FCoE packets at the beginning of FC payload.
15740 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE UINT32_C(0x10)
15742 * When this bit is '1', the VNIC shall be configured to enable Header-
15743 * Data split for RoCE packets at the beginning of RoCE payload (after
15744 * BTH/GRH headers).
15746 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE UINT32_C(0x20)
15749 * This bit must be '1' for the jumbo_thresh_valid field to be
15752 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID UINT32_C(0x1)
15753 /* This bit must be '1' for the hds_offset_valid field to be configured. */
15754 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID UINT32_C(0x2)
15756 * This bit must be '1' for the hds_threshold_valid field to be
15759 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID UINT32_C(0x4)
15761 /* Logical vnic ID */
15762 uint16_t jumbo_thresh;
15764 * When jumbo placement algorithm is enabled, this value is used to
15765 * determine the threshold for jumbo placement. Packets with length
15766 * larger than this value will be placed according to the jumbo
15767 * placement algorithm.
15769 uint16_t hds_offset;
15771 * This value is used to determine the offset into packet buffer where
15772 * the split data (payload) will be placed according to one of of HDS
15773 * placement algorithm. The lengths of packet buffers provided for split
15774 * data shall be larger than this value.
15776 uint16_t hds_threshold;
15778 * When one of the HDS placement algorithm is enabled, this value is
15779 * used to determine the threshold for HDS placement. Packets with
15780 * length larger than this value will be placed according to the HDS
15781 * placement algorithm. This value shall be in multiple of 4 bytes.
15783 uint16_t unused_0[3];
15784 } __attribute__((packed));
15786 /* Output (16 bytes) */
15788 struct hwrm_vnic_plcmodes_cfg_output {
15789 uint16_t error_code;
15791 * Pass/Fail or error type Note: receiver to verify the in parameters,
15792 * and fail the call with an error when appropriate
15795 /* This field returns the type of original request. */
15797 /* This field provides original sequence number of the command. */
15800 * This field is the length of the response in bytes. The last byte of
15801 * the response is a valid flag that will read as '1' when the command
15802 * has been completely written to memory.
15810 * This field is used in Output records to indicate that the output is
15811 * completely written to RAM. This field should be read as '1' to
15812 * indicate that the output has been completely written. When writing a
15813 * command completion or response to an internal processor, the order of
15814 * writes has to be such that this field is written last.
15816 } __attribute__((packed));
15818 /* hwrm_vnic_plcmodes_qcfg */
15820 * Description: This function can be used to query placement mode configuration
15823 /* Input (24 bytes) */
15825 struct hwrm_vnic_plcmodes_qcfg_input {
15828 * This value indicates what type of request this is. The format for the
15829 * rest of the command is determined by this field.
15831 uint16_t cmpl_ring;
15833 * This value indicates the what completion ring the request will be
15834 * optionally completed on. If the value is -1, then no CR completion
15835 * will be generated. Any other value must be a valid CR ring_id value
15836 * for this function.
15839 /* This value indicates the command sequence number. */
15840 uint16_t target_id;
15842 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
15843 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
15845 uint64_t resp_addr;
15847 * This is the host address where the response will be written when the
15848 * request is complete. This area must be 16B aligned and must be
15849 * cleared to zero before the request is made.
15852 /* Logical vnic ID */
15854 } __attribute__((packed));
15856 /* Output (24 bytes) */
15858 struct hwrm_vnic_plcmodes_qcfg_output {
15859 uint16_t error_code;
15861 * Pass/Fail or error type Note: receiver to verify the in parameters,
15862 * and fail the call with an error when appropriate
15865 /* This field returns the type of original request. */
15867 /* This field provides original sequence number of the command. */
15870 * This field is the length of the response in bytes. The last byte of
15871 * the response is a valid flag that will read as '1' when the command
15872 * has been completely written to memory.
15876 * When this bit is '1', the VNIC is configured to use regular placement
15879 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT UINT32_C(0x1)
15881 * When this bit is '1', the VNIC is configured to use the jumbo
15882 * placement algorithm.
15884 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT UINT32_C(0x2)
15886 * When this bit is '1', the VNIC is configured to enable Header-Data
15887 * split for IPv4 packets.
15889 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 UINT32_C(0x4)
15891 * When this bit is '1', the VNIC is configured to enable Header-Data
15892 * split for IPv6 packets.
15894 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 UINT32_C(0x8)
15896 * When this bit is '1', the VNIC is configured to enable Header-Data
15897 * split for FCoE packets.
15899 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE UINT32_C(0x10)
15901 * When this bit is '1', the VNIC is configured to enable Header-Data
15902 * split for RoCE packets.
15904 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE UINT32_C(0x20)
15906 * When this bit is '1', the VNIC is configured to be the default VNIC
15907 * of the requesting function.
15909 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC UINT32_C(0x40)
15910 uint16_t jumbo_thresh;
15912 * When jumbo placement algorithm is enabled, this value is used to
15913 * determine the threshold for jumbo placement. Packets with length
15914 * larger than this value will be placed according to the jumbo
15915 * placement algorithm.
15917 uint16_t hds_offset;
15919 * This value is used to determine the offset into packet buffer where
15920 * the split data (payload) will be placed according to one of of HDS
15921 * placement algorithm. The lengths of packet buffers provided for split
15922 * data shall be larger than this value.
15924 uint16_t hds_threshold;
15926 * When one of the HDS placement algorithm is enabled, this value is
15927 * used to determine the threshold for HDS placement. Packets with
15928 * length larger than this value will be placed according to the HDS
15929 * placement algorithm. This value shall be in multiple of 4 bytes.
15938 * This field is used in Output records to indicate that the output is
15939 * completely written to RAM. This field should be read as '1' to
15940 * indicate that the output has been completely written. When writing a
15941 * command completion or response to an internal processor, the order of
15942 * writes has to be such that this field is written last.
15944 } __attribute__((packed));
15946 /* hwrm_vnic_rss_cos_lb_ctx_alloc */
15947 /* Description: This function is used to allocate COS/Load Balance context. */
15948 /* Input (16 bytes) */
15950 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
15953 * This value indicates what type of request this is. The format for the
15954 * rest of the command is determined by this field.
15956 uint16_t cmpl_ring;
15958 * This value indicates the what completion ring the request will be
15959 * optionally completed on. If the value is -1, then no CR completion
15960 * will be generated. Any other value must be a valid CR ring_id value
15961 * for this function.
15964 /* This value indicates the command sequence number. */
15965 uint16_t target_id;
15967 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
15968 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
15970 uint64_t resp_addr;
15972 * This is the host address where the response will be written when the
15973 * request is complete. This area must be 16B aligned and must be
15974 * cleared to zero before the request is made.
15976 } __attribute__((packed));
15978 /* Output (16 bytes) */
15980 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
15981 uint16_t error_code;
15983 * Pass/Fail or error type Note: receiver to verify the in parameters,
15984 * and fail the call with an error when appropriate
15987 /* This field returns the type of original request. */
15989 /* This field provides original sequence number of the command. */
15992 * This field is the length of the response in bytes. The last byte of
15993 * the response is a valid flag that will read as '1' when the command
15994 * has been completely written to memory.
15996 uint16_t rss_cos_lb_ctx_id;
15997 /* rss_cos_lb_ctx_id is 16 b */
16005 * This field is used in Output records to indicate that the output is
16006 * completely written to RAM. This field should be read as '1' to
16007 * indicate that the output has been completely written. When writing a
16008 * command completion or response to an internal processor, the order of
16009 * writes has to be such that this field is written last.
16011 } __attribute__((packed));
16013 /* hwrm_vnic_rss_cos_lb_ctx_free */
16014 /* Description: This function can be used to free COS/Load Balance context. */
16015 /* Input (24 bytes) */
16017 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
16020 * This value indicates what type of request this is. The format for the
16021 * rest of the command is determined by this field.
16023 uint16_t cmpl_ring;
16025 * This value indicates the what completion ring the request will be
16026 * optionally completed on. If the value is -1, then no CR completion
16027 * will be generated. Any other value must be a valid CR ring_id value
16028 * for this function.
16031 /* This value indicates the command sequence number. */
16032 uint16_t target_id;
16034 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
16035 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
16037 uint64_t resp_addr;
16039 * This is the host address where the response will be written when the
16040 * request is complete. This area must be 16B aligned and must be
16041 * cleared to zero before the request is made.
16043 uint16_t rss_cos_lb_ctx_id;
16044 /* rss_cos_lb_ctx_id is 16 b */
16045 uint16_t unused_0[3];
16046 } __attribute__((packed));
16048 /* Output (16 bytes) */
16050 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
16051 uint16_t error_code;
16053 * Pass/Fail or error type Note: receiver to verify the in parameters,
16054 * and fail the call with an error when appropriate
16057 /* This field returns the type of original request. */
16059 /* This field provides original sequence number of the command. */
16062 * This field is the length of the response in bytes. The last byte of
16063 * the response is a valid flag that will read as '1' when the command
16064 * has been completely written to memory.
16072 * This field is used in Output records to indicate that the output is
16073 * completely written to RAM. This field should be read as '1' to
16074 * indicate that the output has been completely written. When writing a
16075 * command completion or response to an internal processor, the order of
16076 * writes has to be such that this field is written last.
16078 } __attribute__((packed));
16080 /* hwrm_ring_alloc */
16082 * Description: This command allocates and does basic preparation for a ring.
16084 /* Input (80 bytes) */
16086 struct hwrm_ring_alloc_input {
16089 * This value indicates what type of request this is. The format for the
16090 * rest of the command is determined by this field.
16092 uint16_t cmpl_ring;
16094 * This value indicates the what completion ring the request will be
16095 * optionally completed on. If the value is -1, then no CR completion
16096 * will be generated. Any other value must be a valid CR ring_id value
16097 * for this function.
16100 /* This value indicates the command sequence number. */
16101 uint16_t target_id;
16103 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
16104 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
16106 uint64_t resp_addr;
16108 * This is the host address where the response will be written when the
16109 * request is complete. This area must be 16B aligned and must be
16110 * cleared to zero before the request is made.
16113 /* This bit must be '1' for the Reserved1 field to be configured. */
16114 #define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED1 UINT32_C(0x1)
16115 /* This bit must be '1' for the ring_arb_cfg field to be configured. */
16116 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG UINT32_C(0x2)
16117 /* This bit must be '1' for the Reserved3 field to be configured. */
16118 #define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED3 UINT32_C(0x4)
16120 * This bit must be '1' for the stat_ctx_id_valid field to be
16123 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID UINT32_C(0x8)
16124 /* This bit must be '1' for the Reserved4 field to be configured. */
16125 #define HWRM_RING_ALLOC_INPUT_ENABLES_RESERVED4 UINT32_C(0x10)
16126 /* This bit must be '1' for the max_bw_valid field to be configured. */
16127 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID UINT32_C(0x20)
16130 /* L2 Completion Ring (CR) */
16131 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
16133 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
16135 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
16136 /* RoCE Notification Completion Ring (ROCE_CR) */
16137 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
16140 uint64_t page_tbl_addr;
16141 /* This value is a pointer to the page table for the Ring. */
16143 /* First Byte Offset of the first entry in the first page. */
16146 * Actual page size in 2^page_size. The supported range is increments in
16147 * powers of 2 from 16 bytes to 1GB. - 4 = 16 B Page size is 16 B. - 12
16148 * = 4 KB Page size is 4 KB. - 13 = 8 KB Page size is 8 KB. - 16 = 64 KB
16149 * Page size is 64 KB. - 21 = 2 MB Page size is 2 MB. - 22 = 4 MB Page
16150 * size is 4 MB. - 30 = 1 GB Page size is 1 GB.
16152 uint8_t page_tbl_depth;
16154 * This value indicates the depth of page table. For this version of the
16155 * specification, value other than 0 or 1 shall be considered as an
16156 * invalid value. When the page_tbl_depth = 0, then it is treated as a
16157 * special case with the following. 1. FBO and page size fields are not
16158 * valid. 2. page_tbl_addr is the physical address of the first element
16165 * Number of 16B units in the ring. Minimum size for a ring is 16 16B
16168 uint16_t logical_id;
16170 * Logical ring number for the ring to be allocated. This value
16171 * determines the position in the doorbell area where the update to the
16172 * ring will be made. For completion rings, this value is also the MSI-X
16173 * vector number for the function the completion ring is associated
16176 uint16_t cmpl_ring_id;
16178 * This field is used only when ring_type is a TX ring. This value
16179 * indicates what completion ring the TX ring is associated with.
16183 * This field is used only when ring_type is a TX ring. This value
16184 * indicates what CoS queue the TX ring is associated with.
16188 uint32_t reserved1;
16189 /* This field is reserved for the future use. It shall be set to 0. */
16190 uint16_t ring_arb_cfg;
16192 * This field is used only when ring_type is a TX ring. This field is
16193 * used to configure arbitration related parameters for a TX ring.
16195 /* Arbitration policy used for the ring. */
16196 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK UINT32_C(0xf)
16197 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
16199 * Use strict priority for the TX ring. Priority value is
16200 * specified in arb_policy_param
16202 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP (UINT32_C(0x1) << 0)
16204 * Use weighted fair queue arbitration for the TX ring. Weight
16205 * is specified in arb_policy_param
16207 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ (UINT32_C(0x2) << 0)
16208 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ
16209 /* Reserved field. */
16210 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK UINT32_C(0xf0)
16211 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4
16213 * Arbitration policy specific parameter. # For strict priority
16214 * arbitration policy, this field represents a priority value. If set to
16215 * 0, then the priority is not specified and the HWRM is allowed to
16216 * select any priority for this TX ring. # For weighted fair queue
16217 * arbitration policy, this field represents a weight value. If set to
16218 * 0, then the weight is not specified and the HWRM is allowed to select
16219 * any weight for this TX ring.
16221 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK UINT32_C(0xff00)
16222 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8
16225 uint32_t reserved3;
16226 /* This field is reserved for the future use. It shall be set to 0. */
16227 uint32_t stat_ctx_id;
16229 * This field is used only when ring_type is a TX ring. This input
16230 * indicates what statistics context this ring should be associated
16233 uint32_t reserved4;
16234 /* This field is reserved for the future use. It shall be set to 0. */
16237 * This field is used only when ring_type is a TX ring to specify
16238 * maximum BW allocated to the TX ring. The HWRM will translate this
16239 * value into byte counter and time interval used for this ring inside
16242 /* The bandwidth value. */
16243 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
16244 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
16245 /* The granularity of the value (bits or bytes). */
16246 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE UINT32_C(0x10000000)
16247 /* Value is in bits. */
16248 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
16249 /* Value is in bytes. */
16250 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
16251 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES
16252 /* bw_value_unit is 3 b */
16253 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
16254 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29
16255 /* Value is in Mb or MB (base 10). */
16256 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
16257 /* Value is in Kb or KB (base 10). */
16258 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
16259 /* Value is in bits or bytes. */
16260 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
16261 /* Value is in Gb or GB (base 10). */
16262 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
16263 /* Value is in 1/100th of a percentage of total bandwidth. */
16264 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
16266 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
16267 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID
16270 * This field is used only when ring_type is a Completion ring. This
16271 * value indicates what interrupt mode should be used on this completion
16272 * ring. Note: In the legacy interrupt mode, no more than 16 completion
16273 * rings are allowed.
16276 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
16278 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
16280 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
16281 /* No Interrupt - Polled mode */
16282 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
16283 uint8_t unused_8[3];
16284 } __attribute__((packed));
16286 /* Output (16 bytes) */
16288 struct hwrm_ring_alloc_output {
16289 uint16_t error_code;
16291 * Pass/Fail or error type Note: receiver to verify the in parameters,
16292 * and fail the call with an error when appropriate
16295 /* This field returns the type of original request. */
16297 /* This field provides original sequence number of the command. */
16300 * This field is the length of the response in bytes. The last byte of
16301 * the response is a valid flag that will read as '1' when the command
16302 * has been completely written to memory.
16306 * Physical number of ring allocated. This value shall be unique for a
16309 uint16_t logical_ring_id;
16310 /* Logical number of ring allocated. */
16316 * This field is used in Output records to indicate that the output is
16317 * completely written to RAM. This field should be read as '1' to
16318 * indicate that the output has been completely written. When writing a
16319 * command completion or response to an internal processor, the order of
16320 * writes has to be such that this field is written last.
16322 } __attribute__((packed));
16324 /* hwrm_ring_free */
16326 * Description: This command is used to free a ring and associated resources.
16327 * With QoS and DCBx agents, it is possible the traffic classes will be moved
16328 * from one CoS queue to another. When this occurs, the driver shall call
16329 * 'hwrm_ring_free' to free the allocated rings and then call 'hwrm_ring_alloc'
16330 * to re-allocate each ring and assign it to a new CoS queue. hwrm_ring_free
16331 * shall be called on a ring only after it has been idle for 500ms or more and
16332 * no frames have been posted to the ring during this time. All frames queued
16333 * for transmission shall be completed and at least 500ms time elapsed from the
16334 * last completion before calling this command.
16336 /* Input (24 bytes) */
16338 struct hwrm_ring_free_input {
16341 * This value indicates what type of request this is. The format for the
16342 * rest of the command is determined by this field.
16344 uint16_t cmpl_ring;
16346 * This value indicates the what completion ring the request will be
16347 * optionally completed on. If the value is -1, then no CR completion
16348 * will be generated. Any other value must be a valid CR ring_id value
16349 * for this function.
16352 /* This value indicates the command sequence number. */
16353 uint16_t target_id;
16355 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
16356 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
16358 uint64_t resp_addr;
16360 * This is the host address where the response will be written when the
16361 * request is complete. This area must be 16B aligned and must be
16362 * cleared to zero before the request is made.
16366 /* L2 Completion Ring (CR) */
16367 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
16369 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
16371 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
16372 /* RoCE Notification Completion Ring (ROCE_CR) */
16373 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
16376 /* Physical number of ring allocated. */
16378 } __attribute__((packed));
16380 /* Output (16 bytes) */
16382 struct hwrm_ring_free_output {
16383 uint16_t error_code;
16385 * Pass/Fail or error type Note: receiver to verify the in parameters,
16386 * and fail the call with an error when appropriate
16389 /* This field returns the type of original request. */
16391 /* This field provides original sequence number of the command. */
16394 * This field is the length of the response in bytes. The last byte of
16395 * the response is a valid flag that will read as '1' when the command
16396 * has been completely written to memory.
16404 * This field is used in Output records to indicate that the output is
16405 * completely written to RAM. This field should be read as '1' to
16406 * indicate that the output has been completely written. When writing a
16407 * command completion or response to an internal processor, the order of
16408 * writes has to be such that this field is written last.
16410 } __attribute__((packed));
16412 /* hwrm_ring_cmpl_ring_qaggint_params */
16414 * Description: This command is used to query aggregation and interrupt related
16415 * parameters specified on a given completion ring.
16417 /* Input (24 bytes) */
16419 struct hwrm_ring_cmpl_ring_qaggint_params_input {
16422 * This value indicates what type of request this is. The format for the
16423 * rest of the command is determined by this field.
16425 uint16_t cmpl_ring;
16427 * This value indicates the what completion ring the request will be
16428 * optionally completed on. If the value is -1, then no CR completion
16429 * will be generated. Any other value must be a valid CR ring_id value
16430 * for this function.
16433 /* This value indicates the command sequence number. */
16434 uint16_t target_id;
16436 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
16437 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
16439 uint64_t resp_addr;
16441 * This is the host address where the response will be written when the
16442 * request is complete. This area must be 16B aligned and must be
16443 * cleared to zero before the request is made.
16446 /* Physical number of completion ring. */
16447 uint16_t unused_0[3];
16448 } __attribute__((packed));
16450 /* Output (32 bytes) */
16452 struct hwrm_ring_cmpl_ring_qaggint_params_output {
16453 uint16_t error_code;
16455 * Pass/Fail or error type Note: receiver to verify the in parameters,
16456 * and fail the call with an error when appropriate
16459 /* This field returns the type of original request. */
16461 /* This field provides original sequence number of the command. */
16464 * This field is the length of the response in bytes. The last byte of
16465 * the response is a valid flag that will read as '1' when the command
16466 * has been completely written to memory.
16470 * When this bit is set to '1', interrupt max timer is reset whenever a
16471 * completion is received.
16473 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET UINT32_C(0x1)
16475 * When this bit is set to '1', ring idle mode aggregation will be
16478 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE UINT32_C(0x2)
16479 uint16_t num_cmpl_dma_aggr;
16480 /* Number of completions to aggregate before DMA during the normal mode. */
16481 uint16_t num_cmpl_dma_aggr_during_int;
16483 * Number of completions to aggregate before DMA during the interrupt
16486 uint16_t cmpl_aggr_dma_tmr;
16488 * Timer in unit of 80-nsec used to aggregate completions before DMA
16489 * during the normal mode (not in interrupt mode).
16491 uint16_t cmpl_aggr_dma_tmr_during_int;
16493 * Timer in unit of 80-nsec used to aggregate completions before DMA
16494 * during the interrupt mode.
16496 uint16_t int_lat_tmr_min;
16497 /* Minimum time (in unit of 80-nsec) between two interrupts. */
16498 uint16_t int_lat_tmr_max;
16500 * Maximum wait time (in unit of 80-nsec) spent aggregating completions
16501 * before signaling the interrupt after the interrupt is enabled.
16503 uint16_t num_cmpl_aggr_int;
16505 * Minimum number of completions aggregated before signaling an
16514 * This field is used in Output records to indicate that the output is
16515 * completely written to RAM. This field should be read as '1' to
16516 * indicate that the output has been completely written. When writing a
16517 * command completion or response to an internal processor, the order of
16518 * writes has to be such that this field is written last.
16520 } __attribute__((packed));
16522 /* hwrm_ring_cmpl_ring_cfg_aggint_params */
16524 * Description: This command is used to configure aggregation and interrupt
16525 * related parameters specified on a given completion ring.
16527 /* Input (40 bytes) */
16529 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
16532 * This value indicates what type of request this is. The format for the
16533 * rest of the command is determined by this field.
16535 uint16_t cmpl_ring;
16537 * This value indicates the what completion ring the request will be
16538 * optionally completed on. If the value is -1, then no CR completion
16539 * will be generated. Any other value must be a valid CR ring_id value
16540 * for this function.
16543 /* This value indicates the command sequence number. */
16544 uint16_t target_id;
16546 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
16547 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
16549 uint64_t resp_addr;
16551 * This is the host address where the response will be written when the
16552 * request is complete. This area must be 16B aligned and must be
16553 * cleared to zero before the request is made.
16556 /* Physical number of completion ring. */
16559 * When this bit is set to '1', interrupt latency max timer is reset
16560 * whenever a completion is received.
16562 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET UINT32_C(0x1)
16564 * When this bit is set to '1', ring idle mode aggregation will be
16567 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE UINT32_C(0x2)
16568 uint16_t num_cmpl_dma_aggr;
16569 /* Number of completions to aggregate before DMA during the normal mode. */
16570 uint16_t num_cmpl_dma_aggr_during_int;
16572 * Number of completions to aggregate before DMA during the interrupt
16575 uint16_t cmpl_aggr_dma_tmr;
16577 * Timer in unit of 80-nsec used to aggregate completions before DMA
16578 * during the normal mode (not in interrupt mode).
16580 uint16_t cmpl_aggr_dma_tmr_during_int;
16582 * Timer in unit of 80-nsec used to aggregate completions before DMA
16583 * during the interrupt mode.
16585 uint16_t int_lat_tmr_min;
16586 /* Minimum time (in unit of 80-nsec) between two interrupts. */
16587 uint16_t int_lat_tmr_max;
16589 * Maximum wait time (in unit of 80-nsec) spent aggregating cmpls before
16590 * signaling the interrupt after the interrupt is enabled.
16592 uint16_t num_cmpl_aggr_int;
16594 * Minimum number of completions aggregated before signaling an
16597 uint16_t unused_0[3];
16598 } __attribute__((packed));
16600 /* Output (16 bytes) */
16602 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
16603 uint16_t error_code;
16605 * Pass/Fail or error type Note: receiver to verify the in parameters,
16606 * and fail the call with an error when appropriate
16609 /* This field returns the type of original request. */
16611 /* This field provides original sequence number of the command. */
16614 * This field is the length of the response in bytes. The last byte of
16615 * the response is a valid flag that will read as '1' when the command
16616 * has been completely written to memory.
16624 * This field is used in Output records to indicate that the output is
16625 * completely written to RAM. This field should be read as '1' to
16626 * indicate that the output has been completely written. When writing a
16627 * command completion or response to an internal processor, the order of
16628 * writes has to be such that this field is written last.
16630 } __attribute__((packed));
16632 /* hwrm_ring_reset */
16634 * Description: This command is used to reset a given ring. When an RX ring is
16635 * being reset, the HWRM shall perform TPA flush on all VNICs associated with
16636 * the RX ring that is being reset.
16638 /* Input (24 bytes) */
16640 struct hwrm_ring_reset_input {
16643 * This value indicates what type of request this is. The format for the
16644 * rest of the command is determined by this field.
16646 uint16_t cmpl_ring;
16648 * This value indicates the what completion ring the request will be
16649 * optionally completed on. If the value is -1, then no CR completion
16650 * will be generated. Any other value must be a valid CR ring_id value
16651 * for this function.
16654 /* This value indicates the command sequence number. */
16655 uint16_t target_id;
16657 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
16658 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
16660 uint64_t resp_addr;
16662 * This is the host address where the response will be written when the
16663 * request is complete. This area must be 16B aligned and must be
16664 * cleared to zero before the request is made.
16668 /* L2 Completion Ring (CR) */
16669 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
16671 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
16673 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
16674 /* RoCE Notification Completion Ring (ROCE_CR) */
16675 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
16678 /* Physical number of the ring. */
16680 } __attribute__((packed));
16682 /* Output (16 bytes) */
16684 struct hwrm_ring_reset_output {
16685 uint16_t error_code;
16687 * Pass/Fail or error type Note: receiver to verify the in parameters,
16688 * and fail the call with an error when appropriate
16691 /* This field returns the type of original request. */
16693 /* This field provides original sequence number of the command. */
16696 * This field is the length of the response in bytes. The last byte of
16697 * the response is a valid flag that will read as '1' when the command
16698 * has been completely written to memory.
16706 * This field is used in Output records to indicate that the output is
16707 * completely written to RAM. This field should be read as '1' to
16708 * indicate that the output has been completely written. When writing a
16709 * command completion or response to an internal processor, the order of
16710 * writes has to be such that this field is written last.
16712 } __attribute__((packed));
16714 /* hwrm_ring_grp_alloc */
16716 * Description: This API allocates and does basic preparation for a ring group.
16718 /* Input (24 bytes) */
16720 struct hwrm_ring_grp_alloc_input {
16723 * This value indicates what type of request this is. The format for the
16724 * rest of the command is determined by this field.
16726 uint16_t cmpl_ring;
16728 * This value indicates the what completion ring the request will be
16729 * optionally completed on. If the value is -1, then no CR completion
16730 * will be generated. Any other value must be a valid CR ring_id value
16731 * for this function.
16734 /* This value indicates the command sequence number. */
16735 uint16_t target_id;
16737 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
16738 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
16740 uint64_t resp_addr;
16742 * This is the host address where the response will be written when the
16743 * request is complete. This area must be 16B aligned and must be
16744 * cleared to zero before the request is made.
16747 /* This value identifies the CR associated with the ring group. */
16749 /* This value identifies the main RR associated with the ring group. */
16752 * This value identifies the aggregation RR associated with the ring
16753 * group. If this value is 0xFF... (All Fs), then no Aggregation ring
16758 * This value identifies the statistics context associated with the ring
16761 } __attribute__((packed));
16763 /* Output (16 bytes) */
16765 struct hwrm_ring_grp_alloc_output {
16766 uint16_t error_code;
16768 * Pass/Fail or error type Note: receiver to verify the in parameters,
16769 * and fail the call with an error when appropriate
16772 /* This field returns the type of original request. */
16774 /* This field provides original sequence number of the command. */
16777 * This field is the length of the response in bytes. The last byte of
16778 * the response is a valid flag that will read as '1' when the command
16779 * has been completely written to memory.
16781 uint32_t ring_group_id;
16783 * This is the ring group ID value. Use this value to program the
16784 * default ring group for the VNIC or as table entries in an RSS/COS
16792 * This field is used in Output records to indicate that the output is
16793 * completely written to RAM. This field should be read as '1' to
16794 * indicate that the output has been completely written. When writing a
16795 * command completion or response to an internal processor, the order of
16796 * writes has to be such that this field is written last.
16798 } __attribute__((packed));
16800 /* hwrm_ring_grp_free */
16802 * Description: This API frees a ring group and associated resources. # If a
16803 * ring in the ring group is reset or free, then the associated rings in the
16804 * ring group shall also be reset/free using hwrm_ring_free. # A function driver
16805 * shall always use hwrm_ring_grp_free after freeing all rings in a group. # As
16806 * a part of executing this command, the HWRM shall reset all associated ring
16809 /* Input (24 bytes) */
16811 struct hwrm_ring_grp_free_input {
16814 * This value indicates what type of request this is. The format for the
16815 * rest of the command is determined by this field.
16817 uint16_t cmpl_ring;
16819 * This value indicates the what completion ring the request will be
16820 * optionally completed on. If the value is -1, then no CR completion
16821 * will be generated. Any other value must be a valid CR ring_id value
16822 * for this function.
16825 /* This value indicates the command sequence number. */
16826 uint16_t target_id;
16828 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
16829 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
16831 uint64_t resp_addr;
16833 * This is the host address where the response will be written when the
16834 * request is complete. This area must be 16B aligned and must be
16835 * cleared to zero before the request is made.
16837 uint32_t ring_group_id;
16838 /* This is the ring group ID value. */
16840 } __attribute__((packed));
16842 /* Output (16 bytes) */
16844 struct hwrm_ring_grp_free_output {
16845 uint16_t error_code;
16847 * Pass/Fail or error type Note: receiver to verify the in parameters,
16848 * and fail the call with an error when appropriate
16851 /* This field returns the type of original request. */
16853 /* This field provides original sequence number of the command. */
16856 * This field is the length of the response in bytes. The last byte of
16857 * the response is a valid flag that will read as '1' when the command
16858 * has been completely written to memory.
16866 * This field is used in Output records to indicate that the output is
16867 * completely written to RAM. This field should be read as '1' to
16868 * indicate that the output has been completely written. When writing a
16869 * command completion or response to an internal processor, the order of
16870 * writes has to be such that this field is written last.
16872 } __attribute__((packed));
16874 /* hwrm_cfa_l2_filter_alloc */
16876 * Description: An L2 filter is a filter resource that is used to identify a
16877 * vnic or ring for a packet based on layer 2 fields. Layer 2 fields for
16878 * encapsulated packets include both outer L2 header and/or inner l2 header of
16879 * encapsulated packet. The L2 filter resource covers the following OS specific
16880 * L2 filters. Linux/FreeBSD (per function): # Broadcast enable/disable # List
16881 * of individual multicast filters # All multicast enable/disable filter #
16882 * Unicast filters # Promiscuous mode VMware: # Broadcast enable/disable (per
16883 * physical function) # All multicast enable/disable (per function) # Unicast
16884 * filters per ring or vnic # Promiscuous mode per PF Windows: # Broadcast
16885 * enable/disable (per physical function) # List of individual multicast filters
16886 * (Driver needs to advertise the maximum number of filters supported) # All
16887 * multicast enable/disable per physical function # Unicast filters per vnic #
16888 * Promiscuous mode per PF Implementation notes on the use of VNIC in this
16889 * command: # By default, these filters belong to default vnic for the function.
16890 * # Once these filters are set up, only destination VNIC can be modified. # If
16891 * the destination VNIC is not specified in this command, then the HWRM shall
16892 * only create an l2 context id. HWRM Implementation notes for multicast
16893 * filters: # The hwrm_filter_alloc command can be used to set up multicast
16894 * filters (perfect match or partial match). Each individual function driver can
16895 * set up multicast filters independently. # The HWRM needs to keep track of
16896 * multicast filters set up by function drivers and maintain multicast group
16897 * replication records to enable a subset of functions to receive traffic for a
16898 * specific multicast address. # When a specific multicast filter cannot be set,
16899 * the HWRM shall return an error. In this error case, the driver should fall
16900 * back to using one general filter (rather than specific) for all multicast
16901 * traffic. # When the SR-IOV is enabled, the HWRM needs to additionally track
16902 * source knockout per multicast group record. Examples of setting unicast
16903 * filters: For a unicast MAC based filter, one can use a combination of the
16904 * fields and masks provided in this command to set up the filter. Below are
16905 * some examples: # MAC + no VLAN filter: This filter is used to identify
16906 * traffic that does not contain any VLAN tags and matches destination (or
16907 * source) MAC address. This filter can be set up by setting only l2_addr field
16908 * to be a valid field. All other fields are not valid. The following value is
16909 * set for l2_addr. l2_addr = MAC # MAC + Any VLAN filter: This filter is used
16910 * to identify traffic that carries single VLAN tag and matches (destination or
16911 * source) MAC address. This filter can be set up by setting only l2_addr and
16912 * l2_ovlan_mask fields to be valid fields. All other fields are not valid. The
16913 * following values are set for those two valid fields. l2_addr = MAC,
16914 * l2_ovlan_mask = 0xFFFF # MAC + no VLAN or VLAN ID=0: This filter is used to
16915 * identify untagged traffic that does not contain any VLAN tags or a VLAN tag
16916 * with VLAN ID = 0 and matches destination (or source) MAC address. This filter
16917 * can be set up by setting only l2_addr and l2_ovlan fields to be valid fields.
16918 * All other fields are not valid. The following value are set for l2_addr and
16919 * l2_ovlan. l2_addr = MAC, l2_ovlan = 0x0 # MAC + no VLAN or any VLAN: This
16920 * filter is used to identify traffic that contains zero or 1 VLAN tag and
16921 * matches destination (or source) MAC address. This filter can be set up by
16922 * setting only l2_addr, l2_ovlan, and l2_mask fields to be valid fields. All
16923 * other fields are not valid. The following value are set for l2_addr,
16924 * l2_ovlan, and l2_mask fields. l2_addr = MAC, l2_ovlan = 0x0, l2_ovlan_mask =
16925 * 0xFFFF # MAC + VLAN ID filter: This filter can be set up by setting only
16926 * l2_addr, l2_ovlan, and l2_ovlan_mask fields to be valid fields. All other
16927 * fields are not valid. The following values are set for those three valid
16928 * fields. l2_addr = MAC, l2_ovlan = VLAN ID, l2_ovlan_mask = 0xF000
16930 /* Input (96 bytes) */
16932 struct hwrm_cfa_l2_filter_alloc_input {
16935 * This value indicates what type of request this is. The format for the
16936 * rest of the command is determined by this field.
16938 uint16_t cmpl_ring;
16940 * This value indicates the what completion ring the request will be
16941 * optionally completed on. If the value is -1, then no CR completion
16942 * will be generated. Any other value must be a valid CR ring_id value
16943 * for this function.
16946 /* This value indicates the command sequence number. */
16947 uint16_t target_id;
16949 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
16950 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
16952 uint64_t resp_addr;
16954 * This is the host address where the response will be written when the
16955 * request is complete. This area must be 16B aligned and must be
16956 * cleared to zero before the request is made.
16960 * Enumeration denoting the RX, TX type of the resource. This
16961 * enumeration is used for resources that are similar for both TX and RX
16962 * paths of the chip.
16964 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
16966 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX (UINT32_C(0x0) << 0)
16968 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX (UINT32_C(0x1) << 0)
16969 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX
16971 * Setting of this flag indicates the applicability to the loopback
16974 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x2)
16976 * Setting of this flag indicates drop action. If this flag is not set,
16977 * then it should be considered accept action.
16979 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x4)
16981 * If this flag is set, all t_l2_* fields are invalid and they should
16982 * not be specified. If this flag is set, then l2_* fields refer to
16983 * fields of outermost L2 header.
16985 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST UINT32_C(0x8)
16987 /* This bit must be '1' for the l2_addr field to be configured. */
16988 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR UINT32_C(0x1)
16989 /* This bit must be '1' for the l2_addr_mask field to be configured. */
16990 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK UINT32_C(0x2)
16991 /* This bit must be '1' for the l2_ovlan field to be configured. */
16992 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN UINT32_C(0x4)
16993 /* This bit must be '1' for the l2_ovlan_mask field to be configured. */
16994 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK UINT32_C(0x8)
16995 /* This bit must be '1' for the l2_ivlan field to be configured. */
16996 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN UINT32_C(0x10)
16997 /* This bit must be '1' for the l2_ivlan_mask field to be configured. */
16998 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK UINT32_C(0x20)
16999 /* This bit must be '1' for the t_l2_addr field to be configured. */
17000 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR UINT32_C(0x40)
17001 /* This bit must be '1' for the t_l2_addr_mask field to be configured. */
17002 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK UINT32_C(0x80)
17003 /* This bit must be '1' for the t_l2_ovlan field to be configured. */
17004 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN UINT32_C(0x100)
17005 /* This bit must be '1' for the t_l2_ovlan_mask field to be configured. */
17006 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK UINT32_C(0x200)
17007 /* This bit must be '1' for the t_l2_ivlan field to be configured. */
17008 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN UINT32_C(0x400)
17009 /* This bit must be '1' for the t_l2_ivlan_mask field to be configured. */
17010 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK UINT32_C(0x800)
17011 /* This bit must be '1' for the src_type field to be configured. */
17012 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE UINT32_C(0x1000)
17013 /* This bit must be '1' for the src_id field to be configured. */
17014 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID UINT32_C(0x2000)
17015 /* This bit must be '1' for the tunnel_type field to be configured. */
17016 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x4000)
17017 /* This bit must be '1' for the dst_id field to be configured. */
17018 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x8000)
17019 /* This bit must be '1' for the mirror_vnic_id field to be configured. */
17020 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x10000)
17021 uint8_t l2_addr[6];
17023 * This value sets the match value for the L2 MAC address. Destination
17024 * MAC address for RX path. Source MAC address for TX path.
17028 uint8_t l2_addr_mask[6];
17030 * This value sets the mask value for the L2 address. A value of 0 will
17031 * mask the corresponding bit from compare.
17034 /* This value sets VLAN ID value for outer VLAN. */
17035 uint16_t l2_ovlan_mask;
17037 * This value sets the mask value for the ovlan id. A value of 0 will
17038 * mask the corresponding bit from compare.
17041 /* This value sets VLAN ID value for inner VLAN. */
17042 uint16_t l2_ivlan_mask;
17044 * This value sets the mask value for the ivlan id. A value of 0 will
17045 * mask the corresponding bit from compare.
17049 uint8_t t_l2_addr[6];
17051 * This value sets the match value for the tunnel L2 MAC address.
17052 * Destination MAC address for RX path. Source MAC address for TX path.
17056 uint8_t t_l2_addr_mask[6];
17058 * This value sets the mask value for the tunnel L2 address. A value of
17059 * 0 will mask the corresponding bit from compare.
17061 uint16_t t_l2_ovlan;
17062 /* This value sets VLAN ID value for tunnel outer VLAN. */
17063 uint16_t t_l2_ovlan_mask;
17065 * This value sets the mask value for the tunnel ovlan id. A value of 0
17066 * will mask the corresponding bit from compare.
17068 uint16_t t_l2_ivlan;
17069 /* This value sets VLAN ID value for tunnel inner VLAN. */
17070 uint16_t t_l2_ivlan_mask;
17072 * This value sets the mask value for the tunnel ivlan id. A value of 0
17073 * will mask the corresponding bit from compare.
17076 /* This value identifies the type of source of the packet. */
17078 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
17079 /* Physical function */
17080 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
17081 /* Virtual function */
17082 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
17083 /* Virtual NIC of a function */
17084 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
17085 /* Embedded processor for CFA management */
17086 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
17087 /* Embedded processor for OOB management */
17088 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
17089 /* Embedded processor for RoCE */
17090 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
17091 /* Embedded processor for network proxy functions */
17092 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
17096 * This value is the id of the source. For a network port, it represents
17097 * port_id. For a physical function, it represents fid. For a virtual
17098 * function, it represents vf_id. For a vnic, it represents vnic_id. For
17099 * embedded processors, this id is not valid. Notes: 1. The function ID
17100 * is implied if it src_id is not provided for a src_type that is either
17102 uint8_t tunnel_type;
17105 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
17106 /* Virtual eXtensible Local Area Network (VXLAN) */
17107 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
17108 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
17109 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
17110 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
17111 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
17113 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
17114 /* Generic Network Virtualization Encapsulation (Geneve) */
17115 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
17116 /* Multi-Protocol Lable Switching (MPLS) */
17117 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
17118 /* Stateless Transport Tunnel (STT) */
17119 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
17120 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
17121 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
17122 /* Any tunneled traffic */
17123 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
17127 * If set, this value shall represent the Logical VNIC ID of the
17128 * destination VNIC for the RX path and network port id of the
17129 * destination port for the TX path.
17131 uint16_t mirror_vnic_id;
17132 /* Logical VNIC ID of the VNIC where traffic is mirrored. */
17135 * This hint is provided to help in placing the filter in the filter
17138 /* No preference */
17139 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER UINT32_C(0x0)
17140 /* Above the given filter */
17141 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER UINT32_C(0x1)
17142 /* Below the given filter */
17143 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER UINT32_C(0x2)
17144 /* As high as possible */
17145 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX UINT32_C(0x3)
17146 /* As low as possible */
17147 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN UINT32_C(0x4)
17150 uint64_t l2_filter_id_hint;
17152 * This is the ID of the filter that goes along with the pri_hint. This
17153 * field is valid only for the following values. 1 - Above the given
17154 * filter 2 - Below the given filter
17156 } __attribute__((packed));
17158 /* Output (24 bytes) */
17160 struct hwrm_cfa_l2_filter_alloc_output {
17161 uint16_t error_code;
17163 * Pass/Fail or error type Note: receiver to verify the in parameters,
17164 * and fail the call with an error when appropriate
17167 /* This field returns the type of original request. */
17169 /* This field provides original sequence number of the command. */
17172 * This field is the length of the response in bytes. The last byte of
17173 * the response is a valid flag that will read as '1' when the command
17174 * has been completely written to memory.
17176 uint64_t l2_filter_id;
17178 * This value identifies a set of CFA data structures used for an L2
17183 * This is the ID of the flow associated with this filter. This value
17184 * shall be used to match and associate the flow identifier returned in
17185 * completion records. A value of 0xFFFFFFFF shall indicate no flow id.
17192 * This field is used in Output records to indicate that the output is
17193 * completely written to RAM. This field should be read as '1' to
17194 * indicate that the output has been completely written. When writing a
17195 * command completion or response to an internal processor, the order of
17196 * writes has to be such that this field is written last.
17198 } __attribute__((packed));
17200 /* hwrm_cfa_l2_filter_free */
17202 * Description: Free a L2 filter. The HWRM shall free all associated filter
17203 * resources with the L2 filter.
17205 /* Input (24 bytes) */
17207 struct hwrm_cfa_l2_filter_free_input {
17210 * This value indicates what type of request this is. The format for the
17211 * rest of the command is determined by this field.
17213 uint16_t cmpl_ring;
17215 * This value indicates the what completion ring the request will be
17216 * optionally completed on. If the value is -1, then no CR completion
17217 * will be generated. Any other value must be a valid CR ring_id value
17218 * for this function.
17221 /* This value indicates the command sequence number. */
17222 uint16_t target_id;
17224 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
17225 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
17227 uint64_t resp_addr;
17229 * This is the host address where the response will be written when the
17230 * request is complete. This area must be 16B aligned and must be
17231 * cleared to zero before the request is made.
17233 uint64_t l2_filter_id;
17235 * This value identifies a set of CFA data structures used for an L2
17238 } __attribute__((packed));
17240 /* Output (16 bytes) */
17242 struct hwrm_cfa_l2_filter_free_output {
17243 uint16_t error_code;
17245 * Pass/Fail or error type Note: receiver to verify the in parameters,
17246 * and fail the call with an error when appropriate
17249 /* This field returns the type of original request. */
17251 /* This field provides original sequence number of the command. */
17254 * This field is the length of the response in bytes. The last byte of
17255 * the response is a valid flag that will read as '1' when the command
17256 * has been completely written to memory.
17264 * This field is used in Output records to indicate that the output is
17265 * completely written to RAM. This field should be read as '1' to
17266 * indicate that the output has been completely written. When writing a
17267 * command completion or response to an internal processor, the order of
17268 * writes has to be such that this field is written last.
17270 } __attribute__((packed));
17272 /* hwrm_cfa_l2_filter_cfg */
17273 /* Description: Change the configuration of an existing L2 filter */
17274 /* Input (40 bytes) */
17276 struct hwrm_cfa_l2_filter_cfg_input {
17279 * This value indicates what type of request this is. The format for the
17280 * rest of the command is determined by this field.
17282 uint16_t cmpl_ring;
17284 * This value indicates the what completion ring the request will be
17285 * optionally completed on. If the value is -1, then no CR completion
17286 * will be generated. Any other value must be a valid CR ring_id value
17287 * for this function.
17290 /* This value indicates the command sequence number. */
17291 uint16_t target_id;
17293 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
17294 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
17296 uint64_t resp_addr;
17298 * This is the host address where the response will be written when the
17299 * request is complete. This area must be 16B aligned and must be
17300 * cleared to zero before the request is made.
17304 * Enumeration denoting the RX, TX type of the resource. This
17305 * enumeration is used for resources that are similar for both TX and RX
17306 * paths of the chip.
17308 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
17310 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX (UINT32_C(0x0) << 0)
17312 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX (UINT32_C(0x1) << 0)
17313 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX
17315 * Setting of this flag indicates drop action. If this flag is not set,
17316 * then it should be considered accept action.
17318 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP UINT32_C(0x2)
17320 /* This bit must be '1' for the dst_id field to be configured. */
17321 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID UINT32_C(0x1)
17323 * This bit must be '1' for the new_mirror_vnic_id field to be
17326 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2)
17327 uint64_t l2_filter_id;
17329 * This value identifies a set of CFA data structures used for an L2
17334 * If set, this value shall represent the Logical VNIC ID of the
17335 * destination VNIC for the RX path and network port id of the
17336 * destination port for the TX path.
17338 uint32_t new_mirror_vnic_id;
17339 /* New Logical VNIC ID of the VNIC where traffic is mirrored. */
17340 } __attribute__((packed));
17342 /* Output (16 bytes) */
17344 struct hwrm_cfa_l2_filter_cfg_output {
17345 uint16_t error_code;
17347 * Pass/Fail or error type Note: receiver to verify the in parameters,
17348 * and fail the call with an error when appropriate
17351 /* This field returns the type of original request. */
17353 /* This field provides original sequence number of the command. */
17356 * This field is the length of the response in bytes. The last byte of
17357 * the response is a valid flag that will read as '1' when the command
17358 * has been completely written to memory.
17366 * This field is used in Output records to indicate that the output is
17367 * completely written to RAM. This field should be read as '1' to
17368 * indicate that the output has been completely written. When writing a
17369 * command completion or response to an internal processor, the order of
17370 * writes has to be such that this field is written last.
17372 } __attribute__((packed));
17374 /* hwrm_cfa_l2_set_rx_mask */
17375 /* Description: This command will set rx mask of the function. */
17376 /* Input (56 bytes) */
17378 struct hwrm_cfa_l2_set_rx_mask_input {
17381 * This value indicates what type of request this is. The format for the
17382 * rest of the command is determined by this field.
17384 uint16_t cmpl_ring;
17386 * This value indicates the what completion ring the request will be
17387 * optionally completed on. If the value is -1, then no CR completion
17388 * will be generated. Any other value must be a valid CR ring_id value
17389 * for this function.
17392 /* This value indicates the command sequence number. */
17393 uint16_t target_id;
17395 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
17396 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
17398 uint64_t resp_addr;
17400 * This is the host address where the response will be written when the
17401 * request is complete. This area must be 16B aligned and must be
17402 * cleared to zero before the request is made.
17407 /* Reserved for future use. */
17408 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_RESERVED UINT32_C(0x1)
17410 * When this bit is '1', the function is requested to accept multi-cast
17411 * packets specified by the multicast addr table.
17413 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST UINT32_C(0x2)
17415 * When this bit is '1', the function is requested to accept all multi-
17418 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST UINT32_C(0x4)
17420 * When this bit is '1', the function is requested to accept broadcast
17423 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST UINT32_C(0x8)
17425 * When this bit is '1', the function is requested to be put in the
17426 * promiscuous mode. The HWRM should accept any function to set up
17427 * promiscuous mode. The HWRM shall follow the semantics below for the
17428 * promiscuous mode support. # When partitioning is not enabled on a
17429 * port (i.e. single PF on the port), then the PF shall be allowed to be
17430 * in the promiscuous mode. When the PF is in the promiscuous mode, then
17431 * it shall receive all host bound traffic on that port. # When
17432 * partitioning is enabled on a port (i.e. multiple PFs per port) and a
17433 * PF on that port is in the promiscuous mode, then the PF receives all
17434 * traffic within that partition as identified by a unique identifier
17435 * for the PF (e.g. S-Tag). If a unique outer VLAN for the PF is
17436 * specified, then the setting of promiscuous mode on that PF shall
17437 * result in the PF receiving all host bound traffic with matching outer
17438 * VLAN. # A VF shall can be set in the promiscuous mode. In the
17439 * promiscuous mode, the VF does not receive any traffic unless a unique
17440 * outer VLAN for the VF is specified. If a unique outer VLAN for the VF
17441 * is specified, then the setting of promiscuous mode on that VF shall
17442 * result in the VF receiving all host bound traffic with the matching
17443 * outer VLAN. # The HWRM shall allow the setting of promiscuous mode on
17444 * a function independently from the promiscuous mode settings on other
17447 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS UINT32_C(0x10)
17449 * If this flag is set, the corresponding RX filters shall be set up to
17450 * cover multicast/broadcast filters for the outermost Layer 2
17451 * destination MAC address field.
17453 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST UINT32_C(0x20)
17455 * If this flag is set, the corresponding RX filters shall be set up to
17456 * cover multicast/broadcast filters for the VLAN-tagged packets that
17457 * match the TPID and VID fields of VLAN tags in the VLAN tag table
17458 * specified in this command.
17460 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY UINT32_C(0x40)
17462 * If this flag is set, the corresponding RX filters shall be set up to
17463 * cover multicast/broadcast filters for non-VLAN tagged packets and
17464 * VLAN-tagged packets that match the TPID and VID fields of VLAN tags
17465 * in the VLAN tag table specified in this command.
17467 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN UINT32_C(0x80)
17469 * If this flag is set, the corresponding RX filters shall be set up to
17470 * cover multicast/broadcast filters for non-VLAN tagged packets and
17471 * VLAN-tagged packets matching any VLAN tag. If this flag is set, then
17472 * the HWRM shall ignore VLAN tags specified in vlan_tag_tbl. If none of
17473 * vlanonly, vlan_nonvlan, and anyvlan_nonvlan flags is set, then the
17474 * HWRM shall ignore VLAN tags specified in vlan_tag_tbl. The HWRM
17475 * client shall set at most one flag out of vlanonly, vlan_nonvlan, and
17478 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN UINT32_C(0x100)
17479 uint64_t mc_tbl_addr;
17480 /* This is the address for mcast address tbl. */
17481 uint32_t num_mc_entries;
17483 * This value indicates how many entries in mc_tbl are valid. Each entry
17487 uint64_t vlan_tag_tbl_addr;
17489 * This is the address for VLAN tag table. Each VLAN entry in the table
17490 * is 4 bytes of a VLAN tag including TPID, PCP, DEI, and VID fields in
17491 * network byte order.
17493 uint32_t num_vlan_tags;
17495 * This value indicates how many entries in vlan_tag_tbl are valid. Each
17496 * entry is 4 bytes.
17499 } __attribute__((packed));
17501 /* Output (16 bytes) */
17503 struct hwrm_cfa_l2_set_rx_mask_output {
17504 uint16_t error_code;
17506 * Pass/Fail or error type Note: receiver to verify the in parameters,
17507 * and fail the call with an error when appropriate
17510 /* This field returns the type of original request. */
17512 /* This field provides original sequence number of the command. */
17515 * This field is the length of the response in bytes. The last byte of
17516 * the response is a valid flag that will read as '1' when the command
17517 * has been completely written to memory.
17525 * This field is used in Output records to indicate that the output is
17526 * completely written to RAM. This field should be read as '1' to
17527 * indicate that the output has been completely written. When writing a
17528 * command completion or response to an internal processor, the order of
17529 * writes has to be such that this field is written last.
17531 } __attribute__((packed));
17533 /* Command specific Error Codes (8 bytes) */
17535 struct hwrm_cfa_l2_set_rx_mask_cmd_err {
17538 * command specific error codes that goes to the cmd_err field in Common
17539 * HWRM Error Response.
17541 /* Unknown error */
17542 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
17543 /* Unable to complete operation due to conflict with Ntuple Filter */
17544 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR UINT32_C(0x1)
17545 uint8_t unused_0[7];
17546 } __attribute__((packed));
17548 /* hwrm_cfa_vlan_antispoof_cfg */
17549 /* Description: Configures vlan anti-spoof filters for VF. */
17550 /* Input (32 bytes) */
17552 struct hwrm_cfa_vlan_antispoof_cfg_input {
17555 * This value indicates what type of request this is. The format for the
17556 * rest of the command is determined by this field.
17558 uint16_t cmpl_ring;
17560 * This value indicates the what completion ring the request will be
17561 * optionally completed on. If the value is -1, then no CR completion
17562 * will be generated. Any other value must be a valid CR ring_id value
17563 * for this function.
17566 /* This value indicates the command sequence number. */
17567 uint16_t target_id;
17569 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
17570 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
17572 uint64_t resp_addr;
17574 * This is the host address where the response will be written when the
17575 * request is complete. This area must be 16B aligned and must be
17576 * cleared to zero before the request is made.
17580 * Function ID of the function that is being configured. Only valid for
17581 * a VF FID configured by the PF.
17585 uint32_t num_vlan_entries;
17586 /* Number of VLAN entries in the vlan_tag_mask_tbl. */
17587 uint64_t vlan_tag_mask_tbl_addr;
17589 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN antispoof
17590 * table. Each table entry contains the 16-bit TPID (0x8100 or 0x88a8
17591 * only), 16-bit VLAN ID, and a 16-bit mask, all in network order to
17592 * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry, the mask
17593 * value should be 0xfff for the 12-bit VLAN ID.
17595 } __attribute__((packed));
17597 /* Output (16 bytes) */
17599 struct hwrm_cfa_vlan_antispoof_cfg_output {
17600 uint16_t error_code;
17602 * Pass/Fail or error type Note: receiver to verify the in parameters,
17603 * and fail the call with an error when appropriate
17606 /* This field returns the type of original request. */
17608 /* This field provides original sequence number of the command. */
17611 * This field is the length of the response in bytes. The last byte of
17612 * the response is a valid flag that will read as '1' when the command
17613 * has been completely written to memory.
17621 * This field is used in Output records to indicate that the output is
17622 * completely written to RAM. This field should be read as '1' to
17623 * indicate that the output has been completely written. When writing a
17624 * command completion or response to an internal processor, the order of
17625 * writes has to be such that this field is written last.
17627 } __attribute__((packed));
17629 /* hwrm_cfa_vlan_antispoof_qcfg */
17631 * Description: Returns the current configuration of the vlan anti-spoof filters
17634 /* Input (32 bytes) */
17636 struct hwrm_cfa_vlan_antispoof_qcfg_input {
17639 * This value indicates what type of request this is. The format for the
17640 * rest of the command is determined by this field.
17642 uint16_t cmpl_ring;
17644 * This value indicates the what completion ring the request will be
17645 * optionally completed on. If the value is -1, then no CR completion
17646 * will be generated. Any other value must be a valid CR ring_id value
17647 * for this function.
17650 /* This value indicates the command sequence number. */
17651 uint16_t target_id;
17653 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
17654 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
17656 uint64_t resp_addr;
17658 * This is the host address where the response will be written when the
17659 * request is complete. This area must be 16B aligned and must be
17660 * cleared to zero before the request is made.
17664 * Function ID of the function that is being queried. Only valid for a
17665 * VF FID queried by the PF.
17669 uint32_t max_vlan_entries;
17671 * Maximum number of VLAN entries the firmware is allowed to DMA to
17672 * vlan_tag_mask_tbl.
17674 uint64_t vlan_tag_mask_tbl_addr;
17676 * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN antispoof
17677 * table to which firmware will DMA to. Each table entry will contain
17678 * the 16-bit TPID (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit
17679 * mask, all in network order to match hwrm_cfa_l2_set_rx_mask. For an
17680 * individual VLAN entry, the mask value should be 0xfff for the 12-bit
17683 } __attribute__((packed));
17685 /* Output (16 bytes) */
17687 struct hwrm_cfa_vlan_antispoof_qcfg_output {
17688 uint16_t error_code;
17690 * Pass/Fail or error type Note: receiver to verify the in parameters,
17691 * and fail the call with an error when appropriate
17694 /* This field returns the type of original request. */
17696 /* This field provides original sequence number of the command. */
17699 * This field is the length of the response in bytes. The last byte of
17700 * the response is a valid flag that will read as '1' when the command
17701 * has been completely written to memory.
17703 uint32_t num_vlan_entries;
17704 /* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */
17710 * This field is used in Output records to indicate that the output is
17711 * completely written to RAM. This field should be read as '1' to
17712 * indicate that the output has been completely written. When writing a
17713 * command completion or response to an internal processor, the order of
17714 * writes has to be such that this field is written last.
17716 } __attribute__((packed));
17718 /* hwrm_cfa_tunnel_filter_alloc */
17720 * Description: This is a tunnel filter that uses fields from tunnel header in
17721 * addition to l2 context. The tunnel filter applies to receive side only. The
17722 * l2_* fields in this command represent fields of inner L2 header. They are
17723 * optional to be specified. It allows l2_filter_id to be created with outer L2
17724 * header fields that can be shared with multiple tunnel filters specified as
17725 * combinations of inner L2 header fields, tunnel type, and VNI.
17727 /* Input (88 bytes) */
17729 struct hwrm_cfa_tunnel_filter_alloc_input {
17732 * This value indicates what type of request this is. The format for the
17733 * rest of the command is determined by this field.
17735 uint16_t cmpl_ring;
17737 * This value indicates the what completion ring the request will be
17738 * optionally completed on. If the value is -1, then no CR completion
17739 * will be generated. Any other value must be a valid CR ring_id value
17740 * for this function.
17743 /* This value indicates the command sequence number. */
17744 uint16_t target_id;
17746 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
17747 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
17749 uint64_t resp_addr;
17751 * This is the host address where the response will be written when the
17752 * request is complete. This area must be 16B aligned and must be
17753 * cleared to zero before the request is made.
17757 * Setting of this flag indicates the applicability to the loopback
17760 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x1)
17762 /* This bit must be '1' for the l2_filter_id field to be configured. */
17763 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1)
17764 /* This bit must be '1' for the l2_addr field to be configured. */
17765 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR UINT32_C(0x2)
17766 /* This bit must be '1' for the l2_ivlan field to be configured. */
17767 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN UINT32_C(0x4)
17768 /* This bit must be '1' for the l3_addr field to be configured. */
17769 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR UINT32_C(0x8)
17770 /* This bit must be '1' for the l3_addr_type field to be configured. */
17771 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE UINT32_C(0x10)
17772 /* This bit must be '1' for the t_l3_addr_type field to be configured. */
17773 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE UINT32_C(0x20)
17774 /* This bit must be '1' for the t_l3_addr field to be configured. */
17775 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR UINT32_C(0x40)
17776 /* This bit must be '1' for the tunnel_type field to be configured. */
17777 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x80)
17778 /* This bit must be '1' for the vni field to be configured. */
17779 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI UINT32_C(0x100)
17780 /* This bit must be '1' for the dst_vnic_id field to be configured. */
17781 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID UINT32_C(0x200)
17782 /* This bit must be '1' for the mirror_vnic_id field to be configured. */
17783 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x400)
17784 uint64_t l2_filter_id;
17786 * This value identifies a set of CFA data structures used for an L2
17789 uint8_t l2_addr[6];
17791 * This value sets the match value for the inner L2 MAC address.
17792 * Destination MAC address for RX path. Source MAC address for TX path.
17796 * This value sets VLAN ID value for inner VLAN. Only 12-bits of VLAN ID
17797 * are used in setting the filter.
17799 uint32_t l3_addr[4];
17801 * The value of inner destination IP address to be used in filtering.
17802 * For IPv4, first four bytes represent the IP address.
17804 uint32_t t_l3_addr[4];
17806 * The value of tunnel destination IP address to be used in filtering.
17807 * For IPv4, first four bytes represent the IP address.
17809 uint8_t l3_addr_type;
17811 * This value indicates the type of inner IP address. 4 - IPv4 6 - IPv6
17812 * All others are invalid.
17814 uint8_t t_l3_addr_type;
17816 * This value indicates the type of tunnel IP address. 4 - IPv4 6 - IPv6
17817 * All others are invalid.
17819 uint8_t tunnel_type;
17822 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
17823 /* Virtual eXtensible Local Area Network (VXLAN) */
17824 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
17825 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
17826 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
17827 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
17828 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
17830 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
17831 /* Generic Network Virtualization Encapsulation (Geneve) */
17832 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
17833 /* Multi-Protocol Lable Switching (MPLS) */
17834 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
17835 /* Stateless Transport Tunnel (STT) */
17836 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
17837 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
17838 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
17839 /* Any tunneled traffic */
17840 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
17844 * Virtual Network Identifier (VNI). Only valid with tunnel_types VXLAN,
17845 * NVGRE, and Geneve. Only lower 24-bits of VNI field are used in
17846 * setting up the filter.
17848 uint32_t dst_vnic_id;
17849 /* Logical VNIC ID of the destination VNIC. */
17850 uint32_t mirror_vnic_id;
17851 /* Logical VNIC ID of the VNIC where traffic is mirrored. */
17852 } __attribute__((packed));
17854 /* Output (24 bytes) */
17856 struct hwrm_cfa_tunnel_filter_alloc_output {
17857 uint16_t error_code;
17859 * Pass/Fail or error type Note: receiver to verify the in parameters,
17860 * and fail the call with an error when appropriate
17863 /* This field returns the type of original request. */
17865 /* This field provides original sequence number of the command. */
17868 * This field is the length of the response in bytes. The last byte of
17869 * the response is a valid flag that will read as '1' when the command
17870 * has been completely written to memory.
17872 uint64_t tunnel_filter_id;
17873 /* This value is an opaque id into CFA data structures. */
17876 * This is the ID of the flow associated with this filter. This value
17877 * shall be used to match and associate the flow identifier returned in
17878 * completion records. A value of 0xFFFFFFFF shall indicate no flow id.
17885 * This field is used in Output records to indicate that the output is
17886 * completely written to RAM. This field should be read as '1' to
17887 * indicate that the output has been completely written. When writing a
17888 * command completion or response to an internal processor, the order of
17889 * writes has to be such that this field is written last.
17891 } __attribute__((packed));
17893 /* hwrm_cfa_tunnel_filter_free */
17894 /* Description: Free a tunnel filter */
17895 /* Input (24 bytes) */
17897 struct hwrm_cfa_tunnel_filter_free_input {
17900 * This value indicates what type of request this is. The format for the
17901 * rest of the command is determined by this field.
17903 uint16_t cmpl_ring;
17905 * This value indicates the what completion ring the request will be
17906 * optionally completed on. If the value is -1, then no CR completion
17907 * will be generated. Any other value must be a valid CR ring_id value
17908 * for this function.
17911 /* This value indicates the command sequence number. */
17912 uint16_t target_id;
17914 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
17915 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
17917 uint64_t resp_addr;
17919 * This is the host address where the response will be written when the
17920 * request is complete. This area must be 16B aligned and must be
17921 * cleared to zero before the request is made.
17923 uint64_t tunnel_filter_id;
17924 /* This value is an opaque id into CFA data structures. */
17925 } __attribute__((packed));
17927 /* Output (16 bytes) */
17929 struct hwrm_cfa_tunnel_filter_free_output {
17930 uint16_t error_code;
17932 * Pass/Fail or error type Note: receiver to verify the in parameters,
17933 * and fail the call with an error when appropriate
17936 /* This field returns the type of original request. */
17938 /* This field provides original sequence number of the command. */
17941 * This field is the length of the response in bytes. The last byte of
17942 * the response is a valid flag that will read as '1' when the command
17943 * has been completely written to memory.
17951 * This field is used in Output records to indicate that the output is
17952 * completely written to RAM. This field should be read as '1' to
17953 * indicate that the output has been completely written. When writing a
17954 * command completion or response to an internal processor, the order of
17955 * writes has to be such that this field is written last.
17957 } __attribute__((packed));
17959 /* hwrm_cfa_encap_record_alloc */
17961 * Description: This command is used to create an encapsulation record. The
17962 * source MAC address and source IP address specified for the source property
17963 * checks shall be used in the encapsulation where applicable.
17965 /* Input (32 bytes) */
17967 struct hwrm_cfa_encap_record_alloc_input {
17970 * This value indicates what type of request this is. The format for the
17971 * rest of the command is determined by this field.
17973 uint16_t cmpl_ring;
17975 * This value indicates the what completion ring the request will be
17976 * optionally completed on. If the value is -1, then no CR completion
17977 * will be generated. Any other value must be a valid CR ring_id value
17978 * for this function.
17981 /* This value indicates the command sequence number. */
17982 uint16_t target_id;
17984 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
17985 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
17987 uint64_t resp_addr;
17989 * This is the host address where the response will be written when the
17990 * request is complete. This area must be 16B aligned and must be
17991 * cleared to zero before the request is made.
17995 * Setting of this flag indicates the applicability to the loopback
17998 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x1)
17999 uint8_t encap_type;
18000 /* Encapsulation Type. */
18001 /* Virtual eXtensible Local Area Network (VXLAN) */
18002 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN UINT32_C(0x1)
18003 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
18004 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE UINT32_C(0x2)
18005 /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
18006 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE UINT32_C(0x3)
18008 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP UINT32_C(0x4)
18009 /* Generic Network Virtualization Encapsulation (Geneve) */
18010 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE UINT32_C(0x5)
18011 /* Multi-Protocol Lable Switching (MPLS) */
18012 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS UINT32_C(0x6)
18014 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN UINT32_C(0x7)
18015 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
18016 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE UINT32_C(0x8)
18019 uint32_t encap_data[20];
18020 /* This value is encap data used for the given encap type. */
18021 } __attribute__((packed));
18023 /* Output (16 bytes) */
18025 struct hwrm_cfa_encap_record_alloc_output {
18026 uint16_t error_code;
18028 * Pass/Fail or error type Note: receiver to verify the in parameters,
18029 * and fail the call with an error when appropriate
18032 /* This field returns the type of original request. */
18034 /* This field provides original sequence number of the command. */
18037 * This field is the length of the response in bytes. The last byte of
18038 * the response is a valid flag that will read as '1' when the command
18039 * has been completely written to memory.
18041 uint32_t encap_record_id;
18042 /* This value is an opaque id into CFA data structures. */
18048 * This field is used in Output records to indicate that the output is
18049 * completely written to RAM. This field should be read as '1' to
18050 * indicate that the output has been completely written. When writing a
18051 * command completion or response to an internal processor, the order of
18052 * writes has to be such that this field is written last.
18054 } __attribute__((packed));
18056 /* hwrm_cfa_encap_record_free */
18057 /* Description: Free an encap record */
18058 /* Input (24 bytes) */
18060 struct hwrm_cfa_encap_record_free_input {
18063 * This value indicates what type of request this is. The format for the
18064 * rest of the command is determined by this field.
18066 uint16_t cmpl_ring;
18068 * This value indicates the what completion ring the request will be
18069 * optionally completed on. If the value is -1, then no CR completion
18070 * will be generated. Any other value must be a valid CR ring_id value
18071 * for this function.
18074 /* This value indicates the command sequence number. */
18075 uint16_t target_id;
18077 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
18078 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
18080 uint64_t resp_addr;
18082 * This is the host address where the response will be written when the
18083 * request is complete. This area must be 16B aligned and must be
18084 * cleared to zero before the request is made.
18086 uint32_t encap_record_id;
18087 /* This value is an opaque id into CFA data structures. */
18089 } __attribute__((packed));
18091 /* Output (16 bytes) */
18093 struct hwrm_cfa_encap_record_free_output {
18094 uint16_t error_code;
18096 * Pass/Fail or error type Note: receiver to verify the in parameters,
18097 * and fail the call with an error when appropriate
18100 /* This field returns the type of original request. */
18102 /* This field provides original sequence number of the command. */
18105 * This field is the length of the response in bytes. The last byte of
18106 * the response is a valid flag that will read as '1' when the command
18107 * has been completely written to memory.
18115 * This field is used in Output records to indicate that the output is
18116 * completely written to RAM. This field should be read as '1' to
18117 * indicate that the output has been completely written. When writing a
18118 * command completion or response to an internal processor, the order of
18119 * writes has to be such that this field is written last.
18121 } __attribute__((packed));
18123 /* hwrm_cfa_ntuple_filter_alloc */
18125 * Description: This is a ntuple filter that uses fields from L4/L3 header and
18126 * optionally fields from L2. The ntuple filters apply to receive traffic only.
18127 * All L2/L3/L4 header fields are specified in network byte order. These filters
18128 * can be used for Receive Flow Steering (RFS). # For ethertype value, only
18129 * 0x0800 (IPv4) and 0x86dd (IPv6) shall be supported for ntuple filters. # If a
18130 * field specified in this command is not enabled as a valid field, then that
18131 * field shall not be used in matching packet header fields against this filter.
18133 /* Input (128 bytes) */
18135 struct hwrm_cfa_ntuple_filter_alloc_input {
18138 * This value indicates what type of request this is. The format for the
18139 * rest of the command is determined by this field.
18141 uint16_t cmpl_ring;
18143 * This value indicates the what completion ring the request will be
18144 * optionally completed on. If the value is -1, then no CR completion
18145 * will be generated. Any other value must be a valid CR ring_id value
18146 * for this function.
18149 /* This value indicates the command sequence number. */
18150 uint16_t target_id;
18152 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
18153 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
18155 uint64_t resp_addr;
18157 * This is the host address where the response will be written when the
18158 * request is complete. This area must be 16B aligned and must be
18159 * cleared to zero before the request is made.
18163 * Setting of this flag indicates the applicability to the loopback
18166 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x1)
18168 * Setting of this flag indicates drop action. If this flag is not set,
18169 * then it should be considered accept action.
18171 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x2)
18173 * Setting of this flag indicates that a meter is expected to be
18174 * attached to this flow. This hint can be used when choosing the action
18175 * record format required for the flow.
18177 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER UINT32_C(0x4)
18179 /* This bit must be '1' for the l2_filter_id field to be configured. */
18180 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1)
18181 /* This bit must be '1' for the ethertype field to be configured. */
18182 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x2)
18183 /* This bit must be '1' for the tunnel_type field to be configured. */
18184 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x4)
18185 /* This bit must be '1' for the src_macaddr field to be configured. */
18186 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR UINT32_C(0x8)
18187 /* This bit must be '1' for the ipaddr_type field to be configured. */
18188 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x10)
18189 /* This bit must be '1' for the src_ipaddr field to be configured. */
18190 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x20)
18191 /* This bit must be '1' for the src_ipaddr_mask field to be configured. */
18192 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK UINT32_C(0x40)
18193 /* This bit must be '1' for the dst_ipaddr field to be configured. */
18194 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x80)
18195 /* This bit must be '1' for the dst_ipaddr_mask field to be configured. */
18196 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK UINT32_C(0x100)
18197 /* This bit must be '1' for the ip_protocol field to be configured. */
18198 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x200)
18199 /* This bit must be '1' for the src_port field to be configured. */
18200 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x400)
18201 /* This bit must be '1' for the src_port_mask field to be configured. */
18202 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK UINT32_C(0x800)
18203 /* This bit must be '1' for the dst_port field to be configured. */
18204 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x1000)
18205 /* This bit must be '1' for the dst_port_mask field to be configured. */
18206 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK UINT32_C(0x2000)
18207 /* This bit must be '1' for the pri_hint field to be configured. */
18208 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT UINT32_C(0x4000)
18209 /* This bit must be '1' for the ntuple_filter_id field to be configured. */
18210 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID UINT32_C(0x8000)
18211 /* This bit must be '1' for the dst_id field to be configured. */
18212 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x10000)
18213 /* This bit must be '1' for the mirror_vnic_id field to be configured. */
18214 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x20000)
18215 /* This bit must be '1' for the dst_macaddr field to be configured. */
18216 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR UINT32_C(0x40000)
18217 uint64_t l2_filter_id;
18219 * This value identifies a set of CFA data structures used for an L2
18222 uint8_t src_macaddr[6];
18223 /* This value indicates the source MAC address in the Ethernet header. */
18224 uint16_t ethertype; /* big endian */
18225 /* This value indicates the ethertype in the Ethernet header. */
18226 uint8_t ip_addr_type;
18228 * This value indicates the type of IP address. 4 - IPv4 6 - IPv6 All
18229 * others are invalid.
18232 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
18234 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
18236 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
18237 uint8_t ip_protocol;
18239 * The value of protocol filed in IP header. Applies to UDP and TCP
18240 * traffic. 6 - TCP 17 - UDP
18243 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
18245 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
18247 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
18250 * If set, this value shall represent the Logical VNIC ID of the
18251 * destination VNIC for the RX path and network port id of the
18252 * destination port for the TX path.
18254 uint16_t mirror_vnic_id;
18255 /* Logical VNIC ID of the VNIC where traffic is mirrored. */
18256 uint8_t tunnel_type;
18258 * This value indicates the tunnel type for this filter. If this field
18259 * is not specified, then the filter shall apply to both non-tunneled
18260 * and tunneled packets. If this field conflicts with the tunnel_type
18261 * specified in the l2_filter_id, then the HWRM shall return an error
18262 * for this command.
18265 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
18266 /* Virtual eXtensible Local Area Network (VXLAN) */
18267 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
18268 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
18269 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
18270 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
18271 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
18273 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
18274 /* Generic Network Virtualization Encapsulation (Geneve) */
18275 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
18276 /* Multi-Protocol Lable Switching (MPLS) */
18277 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
18278 /* Stateless Transport Tunnel (STT) */
18279 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
18280 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
18281 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
18282 /* Any tunneled traffic */
18283 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
18286 * This hint is provided to help in placing the filter in the filter
18289 /* No preference */
18290 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER UINT32_C(0x0)
18291 /* Above the given filter */
18292 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE UINT32_C(0x1)
18293 /* Below the given filter */
18294 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW UINT32_C(0x2)
18295 /* As high as possible */
18296 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST UINT32_C(0x3)
18297 /* As low as possible */
18298 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST UINT32_C(0x4)
18299 uint32_t src_ipaddr[4]; /* big endian */
18301 * The value of source IP address to be used in filtering. For IPv4,
18302 * first four bytes represent the IP address.
18304 uint32_t src_ipaddr_mask[4]; /* big endian */
18306 * The value of source IP address mask to be used in filtering. For
18307 * IPv4, first four bytes represent the IP address mask.
18309 uint32_t dst_ipaddr[4]; /* big endian */
18311 * The value of destination IP address to be used in filtering. For
18312 * IPv4, first four bytes represent the IP address.
18314 uint32_t dst_ipaddr_mask[4]; /* big endian */
18316 * The value of destination IP address mask to be used in filtering. For
18317 * IPv4, first four bytes represent the IP address mask.
18319 uint16_t src_port; /* big endian */
18321 * The value of source port to be used in filtering. Applies to UDP and
18324 uint16_t src_port_mask; /* big endian */
18326 * The value of source port mask to be used in filtering. Applies to UDP
18329 uint16_t dst_port; /* big endian */
18331 * The value of destination port to be used in filtering. Applies to UDP
18334 uint16_t dst_port_mask; /* big endian */
18336 * The value of destination port mask to be used in filtering. Applies
18337 * to UDP and TCP traffic.
18339 uint64_t ntuple_filter_id_hint;
18340 /* This is the ID of the filter that goes along with the pri_hint. */
18341 } __attribute__((packed));
18343 /* Output (24 bytes) */
18345 struct hwrm_cfa_ntuple_filter_alloc_output {
18346 uint16_t error_code;
18348 * Pass/Fail or error type Note: receiver to verify the in parameters,
18349 * and fail the call with an error when appropriate
18352 /* This field returns the type of original request. */
18354 /* This field provides original sequence number of the command. */
18357 * This field is the length of the response in bytes. The last byte of
18358 * the response is a valid flag that will read as '1' when the command
18359 * has been completely written to memory.
18361 uint64_t ntuple_filter_id;
18362 /* This value is an opaque id into CFA data structures. */
18365 * This is the ID of the flow associated with this filter. This value
18366 * shall be used to match and associate the flow identifier returned in
18367 * completion records. A value of 0xFFFFFFFF shall indicate no flow id.
18374 * This field is used in Output records to indicate that the output is
18375 * completely written to RAM. This field should be read as '1' to
18376 * indicate that the output has been completely written. When writing a
18377 * command completion or response to an internal processor, the order of
18378 * writes has to be such that this field is written last.
18380 } __attribute__((packed));
18382 /* Command specific Error Codes (8 bytes) */
18384 struct hwrm_cfa_ntuple_filter_alloc_cmd_err {
18387 * command specific error codes that goes to the cmd_err field in Common
18388 * HWRM Error Response.
18390 /* Unknown error */
18391 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
18392 /* Unable to complete operation due to conflict with Rx Mask VLAN */
18393 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR UINT32_C(0x1)
18394 uint8_t unused_0[7];
18395 } __attribute__((packed));
18397 /* hwrm_cfa_ntuple_filter_free */
18398 /* Description: Free an ntuple filter */
18399 /* Input (24 bytes) */
18401 struct hwrm_cfa_ntuple_filter_free_input {
18404 * This value indicates what type of request this is. The format for the
18405 * rest of the command is determined by this field.
18407 uint16_t cmpl_ring;
18409 * This value indicates the what completion ring the request will be
18410 * optionally completed on. If the value is -1, then no CR completion
18411 * will be generated. Any other value must be a valid CR ring_id value
18412 * for this function.
18415 /* This value indicates the command sequence number. */
18416 uint16_t target_id;
18418 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
18419 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
18421 uint64_t resp_addr;
18423 * This is the host address where the response will be written when the
18424 * request is complete. This area must be 16B aligned and must be
18425 * cleared to zero before the request is made.
18427 uint64_t ntuple_filter_id;
18428 /* This value is an opaque id into CFA data structures. */
18429 } __attribute__((packed));
18431 /* Output (16 bytes) */
18433 struct hwrm_cfa_ntuple_filter_free_output {
18434 uint16_t error_code;
18436 * Pass/Fail or error type Note: receiver to verify the in parameters,
18437 * and fail the call with an error when appropriate
18440 /* This field returns the type of original request. */
18442 /* This field provides original sequence number of the command. */
18445 * This field is the length of the response in bytes. The last byte of
18446 * the response is a valid flag that will read as '1' when the command
18447 * has been completely written to memory.
18455 * This field is used in Output records to indicate that the output is
18456 * completely written to RAM. This field should be read as '1' to
18457 * indicate that the output has been completely written. When writing a
18458 * command completion or response to an internal processor, the order of
18459 * writes has to be such that this field is written last.
18461 } __attribute__((packed));
18463 /* hwrm_cfa_ntuple_filter_cfg */
18465 * Description: Configure an ntuple filter with a new destination VNIC and/or
18468 /* Input (48 bytes) */
18470 struct hwrm_cfa_ntuple_filter_cfg_input {
18473 * This value indicates what type of request this is. The format for the
18474 * rest of the command is determined by this field.
18476 uint16_t cmpl_ring;
18478 * This value indicates the what completion ring the request will be
18479 * optionally completed on. If the value is -1, then no CR completion
18480 * will be generated. Any other value must be a valid CR ring_id value
18481 * for this function.
18484 /* This value indicates the command sequence number. */
18485 uint16_t target_id;
18487 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
18488 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
18490 uint64_t resp_addr;
18492 * This is the host address where the response will be written when the
18493 * request is complete. This area must be 16B aligned and must be
18494 * cleared to zero before the request is made.
18497 /* This bit must be '1' for the new_dst_id field to be configured. */
18498 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID UINT32_C(0x1)
18500 * This bit must be '1' for the new_mirror_vnic_id field to be
18503 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2)
18505 * This bit must be '1' for the new_meter_instance_id field to be
18508 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID UINT32_C(0x4)
18510 uint64_t ntuple_filter_id;
18511 /* This value is an opaque id into CFA data structures. */
18512 uint32_t new_dst_id;
18514 * If set, this value shall represent the new Logical VNIC ID of the
18515 * destination VNIC for the RX path and new network port id of the
18516 * destination port for the TX path.
18518 uint32_t new_mirror_vnic_id;
18519 /* New Logical VNIC ID of the VNIC where traffic is mirrored. */
18520 uint16_t new_meter_instance_id;
18522 * New meter to attach to the flow. Specifying the invalid instance ID
18523 * is used to remove any existing meter from the flow.
18526 * A value of 0xfff is considered invalid and implies the
18527 * instance is not configured.
18529 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
18530 uint16_t unused_1[3];
18531 } __attribute__((packed));
18533 /* Output (16 bytes) */
18535 struct hwrm_cfa_ntuple_filter_cfg_output {
18536 uint16_t error_code;
18538 * Pass/Fail or error type Note: receiver to verify the in parameters,
18539 * and fail the call with an error when appropriate
18542 /* This field returns the type of original request. */
18544 /* This field provides original sequence number of the command. */
18547 * This field is the length of the response in bytes. The last byte of
18548 * the response is a valid flag that will read as '1' when the command
18549 * has been completely written to memory.
18557 * This field is used in Output records to indicate that the output is
18558 * completely written to RAM. This field should be read as '1' to
18559 * indicate that the output has been completely written. When writing a
18560 * command completion or response to an internal processor, the order of
18561 * writes has to be such that this field is written last.
18563 } __attribute__((packed));
18565 /* hwrm_cfa_em_flow_alloc */
18567 * Description: This is a generic Exact Match (EM) flow that uses fields from
18568 * L4/L3/L2 headers. The EM flows apply to transmit and receive traffic. All
18569 * L2/L3/L4 header fields are specified in network byte order. For each EM flow,
18570 * there is an associated set of actions specified. For tunneled packets, all
18571 * L2/L3/L4 fields specified are fields of inner headers unless otherwise
18572 * specified. # If a field specified in this command is not enabled as a valid
18573 * field, then that field shall not be used in matching packet header fields
18574 * against this EM flow entry.
18576 /* Input (112 bytes) */
18578 struct hwrm_cfa_em_flow_alloc_input {
18581 * This value indicates what type of request this is. The format for the
18582 * rest of the command is determined by this field.
18584 uint16_t cmpl_ring;
18586 * This value indicates the what completion ring the request will be
18587 * optionally completed on. If the value is -1, then no CR completion
18588 * will be generated. Any other value must be a valid CR ring_id value
18589 * for this function.
18592 /* This value indicates the command sequence number. */
18593 uint16_t target_id;
18595 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
18596 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
18598 uint64_t resp_addr;
18600 * This is the host address where the response will be written when the
18601 * request is complete. This area must be 16B aligned and must be
18602 * cleared to zero before the request is made.
18606 * Enumeration denoting the RX, TX type of the resource. This
18607 * enumeration is used for resources that are similar for both TX and RX
18608 * paths of the chip.
18610 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
18612 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX (UINT32_C(0x0) << 0)
18614 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX (UINT32_C(0x1) << 0)
18615 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX
18617 * Setting of this flag indicates enabling of a byte counter for a given
18620 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
18622 * Setting of this flag indicates enabling of a packet counter for a
18625 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
18627 * Setting of this flag indicates de-capsulation action for the given
18630 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
18632 * Setting of this flag indicates encapsulation action for the given
18635 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
18637 * Setting of this flag indicates drop action. If this flag is not set,
18638 * then it should be considered accept action.
18640 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
18642 * Setting of this flag indicates that a meter is expected to be
18643 * attached to this flow. This hint can be used when choosing the action
18644 * record format required for the flow.
18646 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
18648 /* This bit must be '1' for the l2_filter_id field to be configured. */
18649 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1)
18650 /* This bit must be '1' for the tunnel_type field to be configured. */
18651 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x2)
18652 /* This bit must be '1' for the tunnel_id field to be configured. */
18653 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID UINT32_C(0x4)
18654 /* This bit must be '1' for the src_macaddr field to be configured. */
18655 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR UINT32_C(0x8)
18656 /* This bit must be '1' for the dst_macaddr field to be configured. */
18657 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR UINT32_C(0x10)
18658 /* This bit must be '1' for the ovlan_vid field to be configured. */
18659 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID UINT32_C(0x20)
18660 /* This bit must be '1' for the ivlan_vid field to be configured. */
18661 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID UINT32_C(0x40)
18662 /* This bit must be '1' for the ethertype field to be configured. */
18663 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x80)
18664 /* This bit must be '1' for the src_ipaddr field to be configured. */
18665 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x100)
18666 /* This bit must be '1' for the dst_ipaddr field to be configured. */
18667 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x200)
18668 /* This bit must be '1' for the ipaddr_type field to be configured. */
18669 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x400)
18670 /* This bit must be '1' for the ip_protocol field to be configured. */
18671 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x800)
18672 /* This bit must be '1' for the src_port field to be configured. */
18673 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x1000)
18674 /* This bit must be '1' for the dst_port field to be configured. */
18675 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x2000)
18676 /* This bit must be '1' for the dst_id field to be configured. */
18677 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x4000)
18678 /* This bit must be '1' for the mirror_vnic_id field to be configured. */
18679 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x8000)
18680 /* This bit must be '1' for the encap_record_id field to be configured. */
18681 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID UINT32_C(0x10000)
18683 * This bit must be '1' for the meter_instance_id field to be
18686 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID UINT32_C(0x20000)
18687 uint64_t l2_filter_id;
18689 * This value identifies a set of CFA data structures used for an L2
18692 uint8_t tunnel_type;
18695 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
18696 /* Virtual eXtensible Local Area Network (VXLAN) */
18697 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
18698 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
18699 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
18700 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
18701 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
18703 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
18704 /* Generic Network Virtualization Encapsulation (Geneve) */
18705 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
18706 /* Multi-Protocol Lable Switching (MPLS) */
18707 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
18708 /* Stateless Transport Tunnel (STT) */
18709 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
18710 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
18711 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
18712 /* Any tunneled traffic */
18713 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
18716 uint32_t tunnel_id;
18718 * Tunnel identifier. Virtual Network Identifier (VNI). Only valid with
18719 * tunnel_types VXLAN, NVGRE, and Geneve. Only lower 24-bits of VNI
18720 * field are used in setting up the filter.
18722 uint8_t src_macaddr[6];
18723 /* This value indicates the source MAC address in the Ethernet header. */
18724 uint16_t meter_instance_id;
18725 /* The meter instance to attach to the flow. */
18727 * A value of 0xfff is considered invalid and implies the
18728 * instance is not configured.
18730 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
18731 uint8_t dst_macaddr[6];
18733 * This value indicates the destination MAC address in the Ethernet
18736 uint16_t ovlan_vid;
18738 * This value indicates the VLAN ID of the outer VLAN tag in the
18741 uint16_t ivlan_vid;
18743 * This value indicates the VLAN ID of the inner VLAN tag in the
18746 uint16_t ethertype; /* big endian */
18747 /* This value indicates the ethertype in the Ethernet header. */
18748 uint8_t ip_addr_type;
18750 * This value indicates the type of IP address. 4 - IPv4 6 - IPv6 All
18751 * others are invalid.
18754 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
18756 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
18758 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
18759 uint8_t ip_protocol;
18761 * The value of protocol filed in IP header. Applies to UDP and TCP
18762 * traffic. 6 - TCP 17 - UDP
18765 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
18767 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
18769 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
18772 uint32_t src_ipaddr[4]; /* big endian */
18774 * The value of source IP address to be used in filtering. For IPv4,
18775 * first four bytes represent the IP address.
18777 uint32_t dst_ipaddr[4]; /* big endian */
18779 * big_endian = True The value of destination IP address to be used in
18780 * filtering. For IPv4, first four bytes represent the IP address.
18782 uint16_t src_port; /* big endian */
18784 * The value of source port to be used in filtering. Applies to UDP and
18787 uint16_t dst_port; /* big endian */
18789 * The value of destination port to be used in filtering. Applies to UDP
18794 * If set, this value shall represent the Logical VNIC ID of the
18795 * destination VNIC for the RX path and network port id of the
18796 * destination port for the TX path.
18798 uint16_t mirror_vnic_id;
18799 /* Logical VNIC ID of the VNIC where traffic is mirrored. */
18800 uint32_t encap_record_id;
18801 /* Logical ID of the encapsulation record. */
18803 } __attribute__((packed));
18805 /* Output (24 bytes) */
18807 struct hwrm_cfa_em_flow_alloc_output {
18808 uint16_t error_code;
18810 * Pass/Fail or error type Note: receiver to verify the in parameters,
18811 * and fail the call with an error when appropriate
18814 /* This field returns the type of original request. */
18816 /* This field provides original sequence number of the command. */
18819 * This field is the length of the response in bytes. The last byte of
18820 * the response is a valid flag that will read as '1' when the command
18821 * has been completely written to memory.
18823 uint64_t em_filter_id;
18824 /* This value is an opaque id into CFA data structures. */
18827 * This is the ID of the flow associated with this filter. This value
18828 * shall be used to match and associate the flow identifier returned in
18829 * completion records. A value of 0xFFFFFFFF shall indicate no flow id.
18836 * This field is used in Output records to indicate that the output is
18837 * completely written to RAM. This field should be read as '1' to
18838 * indicate that the output has been completely written. When writing a
18839 * command completion or response to an internal processor, the order of
18840 * writes has to be such that this field is written last.
18842 } __attribute__((packed));
18844 /* hwrm_cfa_em_flow_free */
18845 /* Description: Free an EM flow table entry */
18846 /* Input (24 bytes) */
18848 struct hwrm_cfa_em_flow_free_input {
18851 * This value indicates what type of request this is. The format for the
18852 * rest of the command is determined by this field.
18854 uint16_t cmpl_ring;
18856 * This value indicates the what completion ring the request will be
18857 * optionally completed on. If the value is -1, then no CR completion
18858 * will be generated. Any other value must be a valid CR ring_id value
18859 * for this function.
18862 /* This value indicates the command sequence number. */
18863 uint16_t target_id;
18865 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
18866 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
18868 uint64_t resp_addr;
18870 * This is the host address where the response will be written when the
18871 * request is complete. This area must be 16B aligned and must be
18872 * cleared to zero before the request is made.
18874 uint64_t em_filter_id;
18875 /* This value is an opaque id into CFA data structures. */
18876 } __attribute__((packed));
18878 /* Output (16 bytes) */
18880 struct hwrm_cfa_em_flow_free_output {
18881 uint16_t error_code;
18883 * Pass/Fail or error type Note: receiver to verify the in parameters,
18884 * and fail the call with an error when appropriate
18887 /* This field returns the type of original request. */
18889 /* This field provides original sequence number of the command. */
18892 * This field is the length of the response in bytes. The last byte of
18893 * the response is a valid flag that will read as '1' when the command
18894 * has been completely written to memory.
18902 * This field is used in Output records to indicate that the output is
18903 * completely written to RAM. This field should be read as '1' to
18904 * indicate that the output has been completely written. When writing a
18905 * command completion or response to an internal processor, the order of
18906 * writes has to be such that this field is written last.
18908 } __attribute__((packed));
18910 /* hwrm_cfa_em_flow_cfg */
18912 * Description: Configure an EM flow with a new destination VNIC and/or meter.
18914 /* Input (48 bytes) */
18916 struct hwrm_cfa_em_flow_cfg_input {
18919 * This value indicates what type of request this is. The format for the
18920 * rest of the command is determined by this field.
18922 uint16_t cmpl_ring;
18924 * This value indicates the what completion ring the request will be
18925 * optionally completed on. If the value is -1, then no CR completion
18926 * will be generated. Any other value must be a valid CR ring_id value
18927 * for this function.
18930 /* This value indicates the command sequence number. */
18931 uint16_t target_id;
18933 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
18934 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
18936 uint64_t resp_addr;
18938 * This is the host address where the response will be written when the
18939 * request is complete. This area must be 16B aligned and must be
18940 * cleared to zero before the request is made.
18943 /* This bit must be '1' for the new_dst_id field to be configured. */
18944 #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_DST_ID UINT32_C(0x1)
18946 * This bit must be '1' for the new_mirror_vnic_id field to be
18949 #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2)
18951 * This bit must be '1' for the new_meter_instance_id field to be
18954 #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID UINT32_C(0x4)
18956 uint64_t em_filter_id;
18957 /* This value is an opaque id into CFA data structures. */
18958 uint32_t new_dst_id;
18960 * If set, this value shall represent the new Logical VNIC ID of the
18961 * destination VNIC for the RX path and network port id of the
18962 * destination port for the TX path.
18964 uint32_t new_mirror_vnic_id;
18965 /* New Logical VNIC ID of the VNIC where traffic is mirrored. */
18966 uint16_t new_meter_instance_id;
18968 * New meter to attach to the flow. Specifying the invalid instance ID
18969 * is used to remove any existing meter from the flow.
18972 * A value of 0xfff is considered invalid and implies the
18973 * instance is not configured.
18975 #define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
18976 uint16_t unused_1[3];
18977 } __attribute__((packed));
18979 /* Output (16 bytes) */
18981 struct hwrm_cfa_em_flow_cfg_output {
18982 uint16_t error_code;
18984 * Pass/Fail or error type Note: receiver to verify the in parameters,
18985 * and fail the call with an error when appropriate
18988 /* This field returns the type of original request. */
18990 /* This field provides original sequence number of the command. */
18993 * This field is the length of the response in bytes. The last byte of
18994 * the response is a valid flag that will read as '1' when the command
18995 * has been completely written to memory.
19003 * This field is used in Output records to indicate that the output is
19004 * completely written to RAM. This field should be read as '1' to
19005 * indicate that the output has been completely written. When writing a
19006 * command completion or response to an internal processor, the order of
19007 * writes has to be such that this field is written last.
19009 } __attribute__((packed));
19011 /* hwrm_cfa_meter_profile_alloc */
19013 * Description: This is a meter profile that defines the characteristics of the
19014 * meter. This includes the algorithm, information rates, and burst sizes. No
19015 * running state is kept in a profile and instead meter instances are allocated
19016 * that reference a profile.
19018 /* Input (40 bytes) */
19020 struct hwrm_cfa_meter_profile_alloc_input {
19023 * This value indicates what type of request this is. The format for the
19024 * rest of the command is determined by this field.
19026 uint16_t cmpl_ring;
19028 * This value indicates the what completion ring the request will be
19029 * optionally completed on. If the value is -1, then no CR completion
19030 * will be generated. Any other value must be a valid CR ring_id value
19031 * for this function.
19034 /* This value indicates the command sequence number. */
19035 uint16_t target_id;
19037 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
19038 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
19040 uint64_t resp_addr;
19042 * This is the host address where the response will be written when the
19043 * request is complete. This area must be 16B aligned and must be
19044 * cleared to zero before the request is made.
19048 * Enumeration denoting the RX, TX type of the resource. This
19049 * enumeration is used for resources that are similar for both TX and RX
19050 * paths of the chip.
19052 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
19054 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
19056 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
19057 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
19058 uint8_t meter_type;
19059 /* The meter algorithm type. */
19060 /* RFC 2697 (srTCM) */
19061 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 UINT32_C(0x0)
19062 /* RFC 2698 (trTCM) */
19063 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 UINT32_C(0x1)
19064 /* RFC 4115 (trTCM) */
19065 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 UINT32_C(0x2)
19066 uint16_t reserved1;
19067 /* This field is reserved for the future use. It shall be set to 0. */
19068 uint32_t reserved2;
19069 /* This field is reserved for the future use. It shall be set to 0. */
19070 uint32_t commit_rate;
19071 /* A meter rate specified in bytes-per-second. */
19072 /* The bandwidth value. */
19073 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK UINT32_C(0xfffffff)
19074 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT 0
19075 /* The granularity of the value (bits or bytes). */
19076 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE UINT32_C(0x10000000)
19077 /* Value is in bits. */
19078 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS (UINT32_C(0x0) << 28)
19079 /* Value is in bytes. */
19080 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES (UINT32_C(0x1) << 28)
19081 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
19082 /* bw_value_unit is 3 b */
19083 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
19084 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT 29
19085 /* Value is in Mb or MB (base 10). */
19086 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
19087 /* Value is in Kb or KB (base 10). */
19088 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
19089 /* Value is in bits or bytes. */
19090 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
19091 /* Value is in Gb or GB (base 10). */
19092 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
19093 /* Value is in 1/100th of a percentage of total bandwidth. */
19094 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
19096 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
19097 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
19098 uint32_t commit_burst;
19099 /* A meter burst size specified in bytes. */
19100 /* The bandwidth value. */
19101 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK UINT32_C(0xfffffff)
19102 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT 0
19103 /* The granularity of the value (bits or bytes). */
19104 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE UINT32_C(0x10000000)
19105 /* Value is in bits. */
19106 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS (UINT32_C(0x0) << 28)
19107 /* Value is in bytes. */
19108 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES (UINT32_C(0x1) << 28)
19109 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
19110 /* bw_value_unit is 3 b */
19111 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
19112 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT 29
19113 /* Value is in Mb or MB (base 10). */
19114 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
19115 /* Value is in Kb or KB (base 10). */
19116 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
19117 /* Value is in bits or bytes. */
19118 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
19119 /* Value is in Gb or GB (base 10). */
19120 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
19121 /* Value is in 1/100th of a percentage of total bandwidth. */
19122 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
19124 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
19125 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
19126 uint32_t excess_peak_rate;
19127 /* A meter rate specified in bytes-per-second. */
19128 /* The bandwidth value. */
19129 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK UINT32_C(0xfffffff)
19130 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT 0
19131 /* The granularity of the value (bits or bytes). */
19132 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE UINT32_C(0x10000000)
19133 /* Value is in bits. */
19134 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS (UINT32_C(0x0) << 28)
19135 /* Value is in bytes. */
19136 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES (UINT32_C(0x1) << 28)
19137 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
19138 /* bw_value_unit is 3 b */
19139 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
19140 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT 29
19141 /* Value is in Mb or MB (base 10). */
19142 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
19143 /* Value is in Kb or KB (base 10). */
19144 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
19145 /* Value is in bits or bytes. */
19146 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
19147 /* Value is in Gb or GB (base 10). */
19148 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
19149 /* Value is in 1/100th of a percentage of total bandwidth. */
19150 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
19152 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
19153 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
19154 uint32_t excess_peak_burst;
19155 /* A meter burst size specified in bytes. */
19156 /* The bandwidth value. */
19157 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK UINT32_C(0xfffffff)
19158 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT 0
19159 /* The granularity of the value (bits or bytes). */
19160 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE UINT32_C(0x10000000)
19161 /* Value is in bits. */
19162 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS (UINT32_C(0x0) << 28)
19163 /* Value is in bytes. */
19164 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES (UINT32_C(0x1) << 28)
19165 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
19166 /* bw_value_unit is 3 b */
19167 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
19168 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT 29
19169 /* Value is in Mb or MB (base 10). */
19170 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
19171 /* Value is in Kb or KB (base 10). */
19172 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
19173 /* Value is in bits or bytes. */
19174 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
19175 /* Value is in Gb or GB (base 10). */
19176 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
19177 /* Value is in 1/100th of a percentage of total bandwidth. */
19178 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
19180 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
19181 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
19182 } __attribute__((packed));
19184 /* Output (16 bytes) */
19186 struct hwrm_cfa_meter_profile_alloc_output {
19187 uint16_t error_code;
19189 * Pass/Fail or error type Note: receiver to verify the in parameters,
19190 * and fail the call with an error when appropriate
19193 /* This field returns the type of original request. */
19195 /* This field provides original sequence number of the command. */
19198 * This field is the length of the response in bytes. The last byte of
19199 * the response is a valid flag that will read as '1' when the command
19200 * has been completely written to memory.
19202 uint16_t meter_profile_id;
19203 /* This value identifies a meter profile in CFA. */
19205 * A value of 0xfff is considered invalid and implies the
19206 * profile is not configured.
19208 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
19216 * This field is used in Output records to indicate that the output is
19217 * completely written to RAM. This field should be read as '1' to
19218 * indicate that the output has been completely written. When writing a
19219 * command completion or response to an internal processor, the order of
19220 * writes has to be such that this field is written last.
19222 } __attribute__((packed));
19224 /* hwrm_cfa_meter_profile_free */
19225 /* Description: Free a meter profile. */
19226 /* Input (24 bytes) */
19228 struct hwrm_cfa_meter_profile_free_input {
19231 * This value indicates what type of request this is. The format for the
19232 * rest of the command is determined by this field.
19234 uint16_t cmpl_ring;
19236 * This value indicates the what completion ring the request will be
19237 * optionally completed on. If the value is -1, then no CR completion
19238 * will be generated. Any other value must be a valid CR ring_id value
19239 * for this function.
19242 /* This value indicates the command sequence number. */
19243 uint16_t target_id;
19245 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
19246 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
19248 uint64_t resp_addr;
19250 * This is the host address where the response will be written when the
19251 * request is complete. This area must be 16B aligned and must be
19252 * cleared to zero before the request is made.
19256 * Enumeration denoting the RX, TX type of the resource. This
19257 * enumeration is used for resources that are similar for both TX and RX
19258 * paths of the chip.
19260 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
19262 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
19264 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
19265 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
19267 uint16_t meter_profile_id;
19268 /* This value identifies a meter profile in CFA. */
19270 * A value of 0xfff is considered invalid and implies the
19271 * profile is not configured.
19273 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
19275 } __attribute__((packed));
19277 /* Output (16 bytes) */
19279 struct hwrm_cfa_meter_profile_free_output {
19280 uint16_t error_code;
19282 * Pass/Fail or error type Note: receiver to verify the in parameters,
19283 * and fail the call with an error when appropriate
19286 /* This field returns the type of original request. */
19288 /* This field provides original sequence number of the command. */
19291 * This field is the length of the response in bytes. The last byte of
19292 * the response is a valid flag that will read as '1' when the command
19293 * has been completely written to memory.
19301 * This field is used in Output records to indicate that the output is
19302 * completely written to RAM. This field should be read as '1' to
19303 * indicate that the output has been completely written. When writing a
19304 * command completion or response to an internal processor, the order of
19305 * writes has to be such that this field is written last.
19307 } __attribute__((packed));
19309 /* hwrm_cfa_meter_profile_cfg */
19310 /* Description: Reconfigure a meter profile. */
19311 /* Input (40 bytes) */
19313 struct hwrm_cfa_meter_profile_cfg_input {
19316 * This value indicates what type of request this is. The format for the
19317 * rest of the command is determined by this field.
19319 uint16_t cmpl_ring;
19321 * This value indicates the what completion ring the request will be
19322 * optionally completed on. If the value is -1, then no CR completion
19323 * will be generated. Any other value must be a valid CR ring_id value
19324 * for this function.
19327 /* This value indicates the command sequence number. */
19328 uint16_t target_id;
19330 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
19331 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
19333 uint64_t resp_addr;
19335 * This is the host address where the response will be written when the
19336 * request is complete. This area must be 16B aligned and must be
19337 * cleared to zero before the request is made.
19341 * Enumeration denoting the RX, TX type of the resource. This
19342 * enumeration is used for resources that are similar for both TX and RX
19343 * paths of the chip.
19345 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
19347 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
19349 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
19350 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
19351 uint8_t meter_type;
19352 /* The meter algorithm type. */
19353 /* RFC 2697 (srTCM) */
19354 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 UINT32_C(0x0)
19355 /* RFC 2698 (trTCM) */
19356 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 UINT32_C(0x1)
19357 /* RFC 4115 (trTCM) */
19358 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 UINT32_C(0x2)
19359 uint16_t meter_profile_id;
19360 /* This value identifies a meter profile in CFA. */
19362 * A value of 0xfff is considered invalid and implies the
19363 * profile is not configured.
19365 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
19367 /* This field is reserved for the future use. It shall be set to 0. */
19368 uint32_t commit_rate;
19369 /* A meter rate specified in bytes-per-second. */
19370 /* The bandwidth value. */
19371 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK UINT32_C(0xfffffff)
19372 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT 0
19373 /* The granularity of the value (bits or bytes). */
19374 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE UINT32_C(0x10000000)
19375 /* Value is in bits. */
19376 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS (UINT32_C(0x0) << 28)
19377 /* Value is in bytes. */
19378 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES (UINT32_C(0x1) << 28)
19379 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
19380 /* bw_value_unit is 3 b */
19381 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
19382 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT 29
19383 /* Value is in Mb or MB (base 10). */
19384 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
19385 /* Value is in Kb or KB (base 10). */
19386 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
19387 /* Value is in bits or bytes. */
19388 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
19389 /* Value is in Gb or GB (base 10). */
19390 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
19391 /* Value is in 1/100th of a percentage of total bandwidth. */
19392 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
19394 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
19395 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
19396 uint32_t commit_burst;
19397 /* A meter burst size specified in bytes. */
19398 /* The bandwidth value. */
19399 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK UINT32_C(0xfffffff)
19400 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT 0
19401 /* The granularity of the value (bits or bytes). */
19402 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE UINT32_C(0x10000000)
19403 /* Value is in bits. */
19404 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS (UINT32_C(0x0) << 28)
19405 /* Value is in bytes. */
19406 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES (UINT32_C(0x1) << 28)
19407 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
19408 /* bw_value_unit is 3 b */
19409 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
19410 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT 29
19411 /* Value is in Mb or MB (base 10). */
19412 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
19413 /* Value is in Kb or KB (base 10). */
19414 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
19415 /* Value is in bits or bytes. */
19416 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
19417 /* Value is in Gb or GB (base 10). */
19418 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
19419 /* Value is in 1/100th of a percentage of total bandwidth. */
19420 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
19422 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
19423 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
19424 uint32_t excess_peak_rate;
19425 /* A meter rate specified in bytes-per-second. */
19426 /* The bandwidth value. */
19427 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK UINT32_C(0xfffffff)
19428 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT 0
19429 /* The granularity of the value (bits or bytes). */
19430 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE UINT32_C(0x10000000)
19431 /* Value is in bits. */
19432 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS (UINT32_C(0x0) << 28)
19433 /* Value is in bytes. */
19434 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES (UINT32_C(0x1) << 28)
19435 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
19436 /* bw_value_unit is 3 b */
19437 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
19438 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT 29
19439 /* Value is in Mb or MB (base 10). */
19440 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
19441 /* Value is in Kb or KB (base 10). */
19442 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
19443 /* Value is in bits or bytes. */
19444 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
19445 /* Value is in Gb or GB (base 10). */
19446 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
19447 /* Value is in 1/100th of a percentage of total bandwidth. */
19448 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
19450 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
19451 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
19452 uint32_t excess_peak_burst;
19453 /* A meter burst size specified in bytes. */
19454 /* The bandwidth value. */
19455 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK UINT32_C(0xfffffff)
19456 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT 0
19457 /* The granularity of the value (bits or bytes). */
19458 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE UINT32_C(0x10000000)
19459 /* Value is in bits. */
19460 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS (UINT32_C(0x0) << 28)
19461 /* Value is in bytes. */
19462 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES (UINT32_C(0x1) << 28)
19463 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
19464 /* bw_value_unit is 3 b */
19465 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
19466 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT 29
19467 /* Value is in Mb or MB (base 10). */
19468 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
19469 /* Value is in Kb or KB (base 10). */
19470 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
19471 /* Value is in bits or bytes. */
19472 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
19473 /* Value is in Gb or GB (base 10). */
19474 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
19475 /* Value is in 1/100th of a percentage of total bandwidth. */
19476 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
19478 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
19479 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
19480 } __attribute__((packed));
19482 /* Output (16 bytes) */
19484 struct hwrm_cfa_meter_profile_cfg_output {
19485 uint16_t error_code;
19487 * Pass/Fail or error type Note: receiver to verify the in parameters,
19488 * and fail the call with an error when appropriate
19491 /* This field returns the type of original request. */
19493 /* This field provides original sequence number of the command. */
19496 * This field is the length of the response in bytes. The last byte of
19497 * the response is a valid flag that will read as '1' when the command
19498 * has been completely written to memory.
19506 * This field is used in Output records to indicate that the output is
19507 * completely written to RAM. This field should be read as '1' to
19508 * indicate that the output has been completely written. When writing a
19509 * command completion or response to an internal processor, the order of
19510 * writes has to be such that this field is written last.
19512 } __attribute__((packed));
19514 /* hwrm_cfa_meter_instance_alloc */
19516 * Description: This is a meter instance which is used to track a meter's bucket
19517 * fill values for a flow. Each meter instance references a meter profile that
19518 * defines the meter algorithm in use.
19520 /* Input (24 bytes) */
19522 struct hwrm_cfa_meter_instance_alloc_input {
19525 * This value indicates what type of request this is. The format for the
19526 * rest of the command is determined by this field.
19528 uint16_t cmpl_ring;
19530 * This value indicates the what completion ring the request will be
19531 * optionally completed on. If the value is -1, then no CR completion
19532 * will be generated. Any other value must be a valid CR ring_id value
19533 * for this function.
19536 /* This value indicates the command sequence number. */
19537 uint16_t target_id;
19539 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
19540 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
19542 uint64_t resp_addr;
19544 * This is the host address where the response will be written when the
19545 * request is complete. This area must be 16B aligned and must be
19546 * cleared to zero before the request is made.
19550 * Enumeration denoting the RX, TX type of the resource. This
19551 * enumeration is used for resources that are similar for both TX and RX
19552 * paths of the chip.
19554 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
19556 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
19558 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
19559 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
19561 uint16_t meter_profile_id;
19562 /* This value identifies a meter profile in CFA. */
19564 * A value of 0xfff is considered invalid and implies the
19565 * profile is not configured.
19567 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
19569 } __attribute__((packed));
19571 /* Output (16 bytes) */
19573 struct hwrm_cfa_meter_instance_alloc_output {
19574 uint16_t error_code;
19576 * Pass/Fail or error type Note: receiver to verify the in parameters,
19577 * and fail the call with an error when appropriate
19580 /* This field returns the type of original request. */
19582 /* This field provides original sequence number of the command. */
19585 * This field is the length of the response in bytes. The last byte of
19586 * the response is a valid flag that will read as '1' when the command
19587 * has been completely written to memory.
19589 uint16_t meter_instance_id;
19590 /* This value identifies a meter instance in CFA. */
19592 * A value of 0xfff is considered invalid and implies the
19593 * instance is not configured.
19595 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
19603 * This field is used in Output records to indicate that the output is
19604 * completely written to RAM. This field should be read as '1' to
19605 * indicate that the output has been completely written. When writing a
19606 * command completion or response to an internal processor, the order of
19607 * writes has to be such that this field is written last.
19609 } __attribute__((packed));
19611 /* hwrm_cfa_meter_instance_free */
19612 /* Description: Free a meter instance. */
19613 /* Input (24 bytes) */
19615 struct hwrm_cfa_meter_instance_free_input {
19618 * This value indicates what type of request this is. The format for the
19619 * rest of the command is determined by this field.
19621 uint16_t cmpl_ring;
19623 * This value indicates the what completion ring the request will be
19624 * optionally completed on. If the value is -1, then no CR completion
19625 * will be generated. Any other value must be a valid CR ring_id value
19626 * for this function.
19629 /* This value indicates the command sequence number. */
19630 uint16_t target_id;
19632 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
19633 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
19635 uint64_t resp_addr;
19637 * This is the host address where the response will be written when the
19638 * request is complete. This area must be 16B aligned and must be
19639 * cleared to zero before the request is made.
19643 * Enumeration denoting the RX, TX type of the resource. This
19644 * enumeration is used for resources that are similar for both TX and RX
19645 * paths of the chip.
19647 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
19649 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
19651 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
19652 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
19654 uint16_t meter_instance_id;
19655 /* This value identifies a meter instance in CFA. */
19657 * A value of 0xfff is considered invalid and implies the
19658 * instance is not configured.
19660 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
19662 } __attribute__((packed));
19664 /* Output (16 bytes) */
19666 struct hwrm_cfa_meter_instance_free_output {
19667 uint16_t error_code;
19669 * Pass/Fail or error type Note: receiver to verify the in parameters,
19670 * and fail the call with an error when appropriate
19673 /* This field returns the type of original request. */
19675 /* This field provides original sequence number of the command. */
19678 * This field is the length of the response in bytes. The last byte of
19679 * the response is a valid flag that will read as '1' when the command
19680 * has been completely written to memory.
19688 * This field is used in Output records to indicate that the output is
19689 * completely written to RAM. This field should be read as '1' to
19690 * indicate that the output has been completely written. When writing a
19691 * command completion or response to an internal processor, the order of
19692 * writes has to be such that this field is written last.
19694 } __attribute__((packed));
19696 /* hwrm_cfa_decap_filter_alloc */
19698 * Description: This command uses fields from L4/L3/L2 headers. All L2/L3/L4
19699 * header fields are specified in network byte order.
19701 /* Input (104 bytes) */
19703 struct hwrm_cfa_decap_filter_alloc_input {
19706 * This value indicates what type of request this is. The format for the
19707 * rest of the command is determined by this field.
19709 uint16_t cmpl_ring;
19711 * This value indicates the what completion ring the request will be
19712 * optionally completed on. If the value is -1, then no CR completion
19713 * will be generated. Any other value must be a valid CR ring_id value
19714 * for this function.
19717 /* This value indicates the command sequence number. */
19718 uint16_t target_id;
19720 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
19721 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
19723 uint64_t resp_addr;
19725 * This is the host address where the response will be written when the
19726 * request is complete. This area must be 16B aligned and must be
19727 * cleared to zero before the request is made.
19730 /* ovs_tunnel is 1 b */
19731 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL UINT32_C(0x1)
19733 /* This bit must be '1' for the tunnel_type field to be configured. */
19734 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x1)
19735 /* This bit must be '1' for the tunnel_id field to be configured. */
19736 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID UINT32_C(0x2)
19737 /* This bit must be '1' for the src_macaddr field to be configured. */
19738 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR UINT32_C(0x4)
19739 /* This bit must be '1' for the dst_macaddr field to be configured. */
19740 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR UINT32_C(0x8)
19741 /* This bit must be '1' for the ovlan_vid field to be configured. */
19742 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID UINT32_C(0x10)
19743 /* This bit must be '1' for the ivlan_vid field to be configured. */
19744 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID UINT32_C(0x20)
19745 /* This bit must be '1' for the t_ovlan_vid field to be configured. */
19746 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID UINT32_C(0x40)
19747 /* This bit must be '1' for the t_ivlan_vid field to be configured. */
19748 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID UINT32_C(0x80)
19749 /* This bit must be '1' for the ethertype field to be configured. */
19750 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x100)
19751 /* This bit must be '1' for the src_ipaddr field to be configured. */
19752 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x200)
19753 /* This bit must be '1' for the dst_ipaddr field to be configured. */
19754 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x400)
19755 /* This bit must be '1' for the ipaddr_type field to be configured. */
19756 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x800)
19757 /* This bit must be '1' for the ip_protocol field to be configured. */
19758 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x1000)
19759 /* This bit must be '1' for the src_port field to be configured. */
19760 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x2000)
19761 /* This bit must be '1' for the dst_port field to be configured. */
19762 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x4000)
19763 /* This bit must be '1' for the dst_id field to be configured. */
19764 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x8000)
19765 /* This bit must be '1' for the mirror_vnic_id field to be configured. */
19766 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x10000)
19767 uint32_t tunnel_id;
19769 * Tunnel identifier. Virtual Network Identifier (VNI). Only valid with
19770 * tunnel_types VXLAN, NVGRE, and Geneve. Only lower 24-bits of VNI
19771 * field are used in setting up the filter.
19773 uint8_t tunnel_type;
19776 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
19777 /* Virtual eXtensible Local Area Network (VXLAN) */
19778 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
19779 /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
19780 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
19781 /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
19782 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
19784 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
19785 /* Generic Network Virtualization Encapsulation (Geneve) */
19786 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
19787 /* Multi-Protocol Lable Switching (MPLS) */
19788 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
19789 /* Stateless Transport Tunnel (STT) */
19790 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
19791 /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
19792 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
19793 /* Any tunneled traffic */
19794 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
19797 uint8_t src_macaddr[6];
19798 /* This value indicates the source MAC address in the Ethernet header. */
19801 uint8_t dst_macaddr[6];
19803 * This value indicates the destination MAC address in the Ethernet
19806 uint16_t ovlan_vid;
19808 * This value indicates the VLAN ID of the outer VLAN tag in the
19811 uint16_t ivlan_vid;
19813 * This value indicates the VLAN ID of the inner VLAN tag in the
19816 uint16_t t_ovlan_vid;
19818 * This value indicates the VLAN ID of the outer VLAN tag in the tunnel
19821 uint16_t t_ivlan_vid;
19823 * This value indicates the VLAN ID of the inner VLAN tag in the tunnel
19826 uint16_t ethertype; /* big endian */
19827 /* This value indicates the ethertype in the Ethernet header. */
19828 uint8_t ip_addr_type;
19830 * This value indicates the type of IP address. 4 - IPv4 6 - IPv6 All
19831 * others are invalid.
19834 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
19836 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
19838 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
19839 uint8_t ip_protocol;
19841 * The value of protocol filed in IP header. Applies to UDP and TCP
19842 * traffic. 6 - TCP 17 - UDP
19845 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
19847 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
19849 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
19852 uint8_t unused_6[3];
19854 uint32_t src_ipaddr[4]; /* big endian */
19856 * The value of source IP address to be used in filtering. For IPv4,
19857 * first four bytes represent the IP address.
19859 uint32_t dst_ipaddr[4]; /* big endian */
19861 * The value of destination IP address to be used in filtering. For
19862 * IPv4, first four bytes represent the IP address.
19864 uint16_t src_port; /* big endian */
19866 * The value of source port to be used in filtering. Applies to UDP and
19869 uint16_t dst_port; /* big endian */
19871 * The value of destination port to be used in filtering. Applies to UDP
19876 * If set, this value shall represent the Logical VNIC ID of the
19877 * destination VNIC for the RX path.
19879 uint16_t l2_ctxt_ref_id;
19881 * If set, this value shall represent the L2 context that matches the L2
19882 * information of the decap filter.
19884 } __attribute__((packed));
19886 /* Output (16 bytes) */
19888 struct hwrm_cfa_decap_filter_alloc_output {
19889 uint16_t error_code;
19891 * Pass/Fail or error type Note: receiver to verify the in parameters,
19892 * and fail the call with an error when appropriate
19895 /* This field returns the type of original request. */
19897 /* This field provides original sequence number of the command. */
19900 * This field is the length of the response in bytes. The last byte of
19901 * the response is a valid flag that will read as '1' when the command
19902 * has been completely written to memory.
19904 uint32_t decap_filter_id;
19905 /* This value is an opaque id into CFA data structures. */
19911 * This field is used in Output records to indicate that the output is
19912 * completely written to RAM. This field should be read as '1' to
19913 * indicate that the output has been completely written. When writing a
19914 * command completion or response to an internal processor, the order of
19915 * writes has to be such that this field is written last.
19917 } __attribute__((packed));
19919 /* hwrm_cfa_decap_filter_free */
19920 /* Description: Free an decap filter table entry */
19921 /* Input (24 bytes) */
19923 struct hwrm_cfa_decap_filter_free_input {
19926 * This value indicates what type of request this is. The format for the
19927 * rest of the command is determined by this field.
19929 uint16_t cmpl_ring;
19931 * This value indicates the what completion ring the request will be
19932 * optionally completed on. If the value is -1, then no CR completion
19933 * will be generated. Any other value must be a valid CR ring_id value
19934 * for this function.
19937 /* This value indicates the command sequence number. */
19938 uint16_t target_id;
19940 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
19941 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
19943 uint64_t resp_addr;
19945 * This is the host address where the response will be written when the
19946 * request is complete. This area must be 16B aligned and must be
19947 * cleared to zero before the request is made.
19949 uint32_t decap_filter_id;
19950 /* This value is an opaque id into CFA data structures. */
19952 } __attribute__((packed));
19954 /* Output (16 bytes) */
19956 struct hwrm_cfa_decap_filter_free_output {
19957 uint16_t error_code;
19959 * Pass/Fail or error type Note: receiver to verify the in parameters,
19960 * and fail the call with an error when appropriate
19963 /* This field returns the type of original request. */
19965 /* This field provides original sequence number of the command. */
19968 * This field is the length of the response in bytes. The last byte of
19969 * the response is a valid flag that will read as '1' when the command
19970 * has been completely written to memory.
19978 * This field is used in Output records to indicate that the output is
19979 * completely written to RAM. This field should be read as '1' to
19980 * indicate that the output has been completely written. When writing a
19981 * command completion or response to an internal processor, the order of
19982 * writes has to be such that this field is written last.
19984 } __attribute__((packed));
19986 /* hwrm_cfa_flow_alloc */
19987 /* Description: Flow is added to table and resources are allocated. */
19988 /* Input (128 bytes) */
19990 struct hwrm_cfa_flow_alloc_input {
19993 * This value indicates what type of request this is. The format for the
19994 * rest of the command is determined by this field.
19996 uint16_t cmpl_ring;
19998 * This value indicates the what completion ring the request will be
19999 * optionally completed on. If the value is -1, then no CR completion
20000 * will be generated. Any other value must be a valid CR ring_id value
20001 * for this function.
20004 /* This value indicates the command sequence number. */
20005 uint16_t target_id;
20007 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
20008 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
20010 uint64_t resp_addr;
20012 * This is the host address where the response will be written when the
20013 * request is complete. This area must be 16B aligned and must be
20014 * cleared to zero before the request is made.
20017 /* tunnel is 1 b */
20018 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL UINT32_C(0x1)
20019 /* num_vlan is 2 b */
20020 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK UINT32_C(0x6)
20021 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
20023 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE (UINT32_C(0x0) << 1)
20025 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE (UINT32_C(0x1) << 1)
20027 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO (UINT32_C(0x2) << 1)
20028 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
20029 /* Enumeration denoting the Flow Type. */
20030 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK UINT32_C(0x38)
20031 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
20033 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 (UINT32_C(0x0) << 3)
20035 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 (UINT32_C(0x1) << 3)
20037 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 (UINT32_C(0x2) << 3)
20038 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
20040 /* Tx Flow: vf fid. Rx Flow: pf fid. */
20041 uint32_t tunnel_handle;
20042 /* Tunnel handle valid when tunnel flag is set. */
20043 uint16_t action_flags;
20045 * Setting of this flag indicates drop action. If this flag is not set,
20046 * then it should be considered accept action.
20048 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD UINT32_C(0x1)
20049 /* recycle is 1 b */
20050 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE UINT32_C(0x2)
20052 * Setting of this flag indicates drop action. If this flag is not set,
20053 * then it should be considered accept action.
20055 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP UINT32_C(0x4)
20057 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER UINT32_C(0x8)
20058 /* tunnel is 1 b */
20059 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL UINT32_C(0x10)
20060 /* nat_src is 1 b */
20061 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC UINT32_C(0x20)
20062 /* nat_dest is 1 b */
20063 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST UINT32_C(0x40)
20064 /* nat_ipv4_address is 1 b */
20065 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS UINT32_C(0x80)
20066 /* l2_header_rewrite is 1 b */
20067 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE UINT32_C(0x100)
20068 /* ttl_decrement is 1 b */
20069 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT UINT32_C(0x200)
20071 /* Tx Flow: pf or vf fid. Rx Flow: vf fid. */
20072 uint16_t l2_rewrite_vlan_tpid; /* big endian */
20073 /* VLAN tpid, valid when push_vlan flag is set. */
20074 uint16_t l2_rewrite_vlan_tci; /* big endian */
20075 /* VLAN tci, valid when push_vlan flag is set. */
20076 uint16_t act_meter_id;
20077 /* Meter id, valid when meter flag is set. */
20078 uint16_t ref_flow_handle;
20079 /* Flow with the same l2 context tcam key. */
20080 uint16_t ethertype; /* big endian */
20081 /* This value sets the match value for the ethertype. */
20082 uint16_t outer_vlan_tci; /* big endian */
20083 /* valid when num tags is 1 or 2. */
20084 uint16_t dmac[3]; /* big endian */
20085 /* This value sets the match value for the Destination MAC address. */
20086 uint16_t inner_vlan_tci; /* big endian */
20087 /* valid when num tags is 2. */
20088 uint16_t smac[3]; /* big endian */
20089 /* This value sets the match value for the Source MAC address. */
20090 uint8_t ip_dst_mask_len;
20091 /* The bit length of destination IP address mask. */
20092 uint8_t ip_src_mask_len;
20093 /* The bit length of source IP address mask. */
20094 uint32_t ip_dst[4]; /* big endian */
20095 /* The value of destination IPv4/IPv6 address. */
20096 uint32_t ip_src[4]; /* big endian */
20097 /* The source IPv4/IPv6 address. */
20098 uint16_t l4_src_port; /* big endian */
20099 /* The value of source port. Applies to UDP and TCP traffic. */
20100 uint16_t l4_src_port_mask; /* big endian */
20101 /* The value of source port mask. Applies to UDP and TCP traffic. */
20102 uint16_t l4_dst_port; /* big endian */
20103 /* The value of destination port. Applies to UDP and TCP traffic. */
20104 uint16_t l4_dst_port_mask; /* big endian */
20105 /* The value of destination port mask. Applies to UDP and TCP traffic. */
20106 uint32_t nat_ip_address[4]; /* big endian */
20107 /* NAT IPv4/6 address based on address type flag. 0 values are ignored. */
20108 uint16_t l2_rewrite_dmac[3]; /* big endian */
20109 /* L2 header re-write Destination MAC address. */
20110 uint16_t nat_port; /* big endian */
20112 * The NAT source/destination port based on direction flag. Applies to
20113 * UDP and TCP traffic. 0 values are ignored.
20115 uint16_t l2_rewrite_smac[3]; /* big endian */
20116 /* L2 header re-write Source MAC address. */
20118 /* The value of ip protocol. */
20120 } __attribute__((packed));
20122 /* Output (16 bytes) */
20124 struct hwrm_cfa_flow_alloc_output {
20125 uint16_t error_code;
20127 * Pass/Fail or error type Note: receiver to verify the in parameters,
20128 * and fail the call with an error when appropriate
20131 /* This field returns the type of original request. */
20133 /* This field provides original sequence number of the command. */
20136 * This field is the length of the response in bytes. The last byte of
20137 * the response is a valid flag that will read as '1' when the command
20138 * has been completely written to memory.
20140 uint16_t flow_handle;
20141 /* Flow record index. */
20149 * This field is used in Output records to indicate that the output is
20150 * completely written to RAM. This field should be read as '1' to
20151 * indicate that the output has been completely written. When writing a
20152 * command completion or response to an internal processor, the order of
20153 * writes has to be such that this field is written last.
20155 } __attribute__((packed));
20157 /* hwrm_cfa_flow_free */
20158 /* Description: Flow is removed from table and resources are released. */
20159 /* Input (24 bytes) */
20161 struct hwrm_cfa_flow_free_input {
20164 * This value indicates what type of request this is. The format for the
20165 * rest of the command is determined by this field.
20167 uint16_t cmpl_ring;
20169 * This value indicates the what completion ring the request will be
20170 * optionally completed on. If the value is -1, then no CR completion
20171 * will be generated. Any other value must be a valid CR ring_id value
20172 * for this function.
20175 /* This value indicates the command sequence number. */
20176 uint16_t target_id;
20178 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
20179 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
20181 uint64_t resp_addr;
20183 * This is the host address where the response will be written when the
20184 * request is complete. This area must be 16B aligned and must be
20185 * cleared to zero before the request is made.
20187 uint16_t flow_handle;
20188 /* Flow record index. */
20189 uint16_t unused_0[3];
20190 } __attribute__((packed));
20192 /* Output (32 bytes) */
20194 struct hwrm_cfa_flow_free_output {
20195 uint16_t error_code;
20197 * Pass/Fail or error type Note: receiver to verify the in parameters,
20198 * and fail the call with an error when appropriate
20201 /* This field returns the type of original request. */
20203 /* This field provides original sequence number of the command. */
20206 * This field is the length of the response in bytes. The last byte of
20207 * the response is a valid flag that will read as '1' when the command
20208 * has been completely written to memory.
20211 /* packet is 64 b */
20220 * This field is used in Output records to indicate that the output is
20221 * completely written to RAM. This field should be read as '1' to
20222 * indicate that the output has been completely written. When writing a
20223 * command completion or response to an internal processor, the order of
20224 * writes has to be such that this field is written last.
20226 } __attribute__((packed));
20228 /* hwrm_cfa_flow_info */
20229 /* Description: Flow record content for specified flow is returned. */
20230 /* Input (24 bytes) */
20232 struct hwrm_cfa_flow_info_input {
20235 * This value indicates what type of request this is. The format for the
20236 * rest of the command is determined by this field.
20238 uint16_t cmpl_ring;
20240 * This value indicates the what completion ring the request will be
20241 * optionally completed on. If the value is -1, then no CR completion
20242 * will be generated. Any other value must be a valid CR ring_id value
20243 * for this function.
20246 /* This value indicates the command sequence number. */
20247 uint16_t target_id;
20249 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
20250 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
20252 uint64_t resp_addr;
20254 * This is the host address where the response will be written when the
20255 * request is complete. This area must be 16B aligned and must be
20256 * cleared to zero before the request is made.
20258 uint16_t flow_handle;
20259 /* Flow record index. */
20260 /* Max flow handle */
20261 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK UINT32_C(0xfff)
20262 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
20263 /* CNP flow handle */
20264 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT UINT32_C(0x1000)
20266 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_RESERVED_MASK UINT32_C(0x6000)
20267 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_RESERVED_SFT 13
20268 /* Direction rx = 1 */
20269 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX UINT32_C(0x8000)
20270 uint16_t unused_0[3];
20271 } __attribute__((packed));
20273 /* Output (56 bytes) */
20275 struct hwrm_cfa_flow_info_output {
20276 uint16_t error_code;
20278 * Pass/Fail or error type Note: receiver to verify the in parameters,
20279 * and fail the call with an error when appropriate
20282 /* This field returns the type of original request. */
20284 /* This field provides original sequence number of the command. */
20287 * This field is the length of the response in bytes. The last byte of
20288 * the response is a valid flag that will read as '1' when the command
20289 * has been completely written to memory.
20294 /* profile is 8 b */
20296 /* src_fid is 16 b */
20298 /* dst_fid is 16 b */
20299 uint16_t l2_ctxt_id;
20300 /* l2_ctxt_id is 16 b */
20302 /* em_info is 64 b */
20303 uint64_t tcam_info;
20304 /* tcam_info is 64 b */
20305 uint64_t vfp_tcam_info;
20306 /* vfp_tcam_info is 64 b */
20308 /* ar_id is 16 b */
20309 uint16_t flow_handle;
20310 /* flow_handle is 16 b */
20311 uint32_t tunnel_handle;
20312 /* tunnel_handle is 32 b */
20319 * This field is used in Output records to indicate that the output is
20320 * completely written to RAM. This field should be read as '1' to
20321 * indicate that the output has been completely written. When writing a
20322 * command completion or response to an internal processor, the order of
20323 * writes has to be such that this field is written last.
20325 } __attribute__((packed));
20327 /* hwrm_cfa_flow_flush */
20328 /* Description: All flows are removed from table and resources are released. */
20329 /* Input (24 bytes) */
20331 struct hwrm_cfa_flow_flush_input {
20334 * This value indicates what type of request this is. The format for the
20335 * rest of the command is determined by this field.
20337 uint16_t cmpl_ring;
20339 * This value indicates the what completion ring the request will be
20340 * optionally completed on. If the value is -1, then no CR completion
20341 * will be generated. Any other value must be a valid CR ring_id value
20342 * for this function.
20345 /* This value indicates the command sequence number. */
20346 uint16_t target_id;
20348 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
20349 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
20351 uint64_t resp_addr;
20353 * This is the host address where the response will be written when the
20354 * request is complete. This area must be 16B aligned and must be
20355 * cleared to zero before the request is made.
20359 } __attribute__((packed));
20361 /* Output (16 bytes) */
20363 struct hwrm_cfa_flow_flush_output {
20364 uint16_t error_code;
20366 * Pass/Fail or error type Note: receiver to verify the in parameters,
20367 * and fail the call with an error when appropriate
20370 /* This field returns the type of original request. */
20372 /* This field provides original sequence number of the command. */
20375 * This field is the length of the response in bytes. The last byte of
20376 * the response is a valid flag that will read as '1' when the command
20377 * has been completely written to memory.
20385 * This field is used in Output records to indicate that the output is
20386 * completely written to RAM. This field should be read as '1' to
20387 * indicate that the output has been completely written. When writing a
20388 * command completion or response to an internal processor, the order of
20389 * writes has to be such that this field is written last.
20391 } __attribute__((packed));
20393 /* hwrm_cfa_flow_stats */
20394 /* Description: Flow is removed from table and resources are released. */
20395 /* Input (40 bytes) */
20397 struct hwrm_cfa_flow_stats_input {
20400 * This value indicates what type of request this is. The format for the
20401 * rest of the command is determined by this field.
20403 uint16_t cmpl_ring;
20405 * This value indicates the what completion ring the request will be
20406 * optionally completed on. If the value is -1, then no CR completion
20407 * will be generated. Any other value must be a valid CR ring_id value
20408 * for this function.
20411 /* This value indicates the command sequence number. */
20412 uint16_t target_id;
20414 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
20415 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
20417 uint64_t resp_addr;
20419 * This is the host address where the response will be written when the
20420 * request is complete. This area must be 16B aligned and must be
20421 * cleared to zero before the request is made.
20423 uint16_t num_flows;
20425 uint16_t flow_handle_0;
20427 uint16_t flow_handle_1;
20429 uint16_t flow_handle_2;
20431 uint16_t flow_handle_3;
20433 uint16_t flow_handle_4;
20435 uint16_t flow_handle_5;
20437 uint16_t flow_handle_6;
20439 uint16_t flow_handle_7;
20441 uint16_t flow_handle_8;
20443 uint16_t flow_handle_9;
20446 } __attribute__((packed));
20448 /* Output (176 bytes) */
20450 struct hwrm_cfa_flow_stats_output {
20451 uint16_t error_code;
20453 * Pass/Fail or error type Note: receiver to verify the in parameters,
20454 * and fail the call with an error when appropriate
20457 /* This field returns the type of original request. */
20459 /* This field provides original sequence number of the command. */
20462 * This field is the length of the response in bytes. The last byte of
20463 * the response is a valid flag that will read as '1' when the command
20464 * has been completely written to memory.
20467 /* packet_0 is 64 b */
20469 /* packet_1 is 64 b */
20471 /* packet_2 is 64 b */
20473 /* packet_3 is 64 b */
20475 /* packet_4 is 64 b */
20477 /* packet_5 is 64 b */
20479 /* packet_6 is 64 b */
20481 /* packet_7 is 64 b */
20483 /* packet_8 is 64 b */
20485 /* packet_9 is 64 b */
20487 /* byte_0 is 64 b */
20489 /* byte_1 is 64 b */
20491 /* byte_2 is 64 b */
20493 /* byte_3 is 64 b */
20495 /* byte_4 is 64 b */
20497 /* byte_5 is 64 b */
20499 /* byte_6 is 64 b */
20501 /* byte_7 is 64 b */
20503 /* byte_8 is 64 b */
20505 /* byte_9 is 64 b */
20512 * This field is used in Output records to indicate that the output is
20513 * completely written to RAM. This field should be read as '1' to
20514 * indicate that the output has been completely written. When writing a
20515 * command completion or response to an internal processor, the order of
20516 * writes has to be such that this field is written last.
20518 } __attribute__((packed));
20520 /* hwrm_cfa_vf_pair_alloc */
20521 /* Description: VF pair is added to table and resources are allocated. */
20522 /* Input (32 bytes) */
20524 struct hwrm_cfa_vf_pair_alloc_input {
20527 * This value indicates what type of request this is. The format for the
20528 * rest of the command is determined by this field.
20530 uint16_t cmpl_ring;
20532 * This value indicates the what completion ring the request will be
20533 * optionally completed on. If the value is -1, then no CR completion
20534 * will be generated. Any other value must be a valid CR ring_id value
20535 * for this function.
20538 /* This value indicates the command sequence number. */
20539 uint16_t target_id;
20541 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
20542 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
20544 uint64_t resp_addr;
20546 * This is the host address where the response will be written when the
20547 * request is complete. This area must be 16B aligned and must be
20548 * cleared to zero before the request is made.
20551 /* Logical VF number (range: 0 -> MAX_VFS -1). */
20553 /* Logical VF number (range: 0 -> MAX_VFS -1). */
20555 char pair_name[32];
20556 /* VF Pair name (32 byte string). */
20557 } __attribute__((packed));
20559 /* Output (16 bytes) */
20561 struct hwrm_cfa_vf_pair_alloc_output {
20562 uint16_t error_code;
20564 * Pass/Fail or error type Note: receiver to verify the in parameters,
20565 * and fail the call with an error when appropriate
20568 /* This field returns the type of original request. */
20570 /* This field provides original sequence number of the command. */
20573 * This field is the length of the response in bytes. The last byte of
20574 * the response is a valid flag that will read as '1' when the command
20575 * has been completely written to memory.
20583 * This field is used in Output records to indicate that the output is
20584 * completely written to RAM. This field should be read as '1' to
20585 * indicate that the output has been completely written. When writing a
20586 * command completion or response to an internal processor, the order of
20587 * writes has to be such that this field is written last.
20589 } __attribute__((packed));
20591 /* hwrm_cfa_vf_pair_free */
20592 /* Description: VF Pair is removed from table and resources are released. */
20593 /* Input (24 bytes) */
20595 struct hwrm_cfa_vf_pair_free_input {
20598 * This value indicates what type of request this is. The format for the
20599 * rest of the command is determined by this field.
20601 uint16_t cmpl_ring;
20603 * This value indicates the what completion ring the request will be
20604 * optionally completed on. If the value is -1, then no CR completion
20605 * will be generated. Any other value must be a valid CR ring_id value
20606 * for this function.
20609 /* This value indicates the command sequence number. */
20610 uint16_t target_id;
20612 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
20613 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
20615 uint64_t resp_addr;
20617 * This is the host address where the response will be written when the
20618 * request is complete. This area must be 16B aligned and must be
20619 * cleared to zero before the request is made.
20621 char pair_name[32];
20622 /* VF Pair name (32 byte string). */
20623 } __attribute__((packed));
20625 /* Output (16 bytes) */
20627 struct hwrm_cfa_vf_pair_free_output {
20628 uint16_t error_code;
20630 * Pass/Fail or error type Note: receiver to verify the in parameters,
20631 * and fail the call with an error when appropriate
20634 /* This field returns the type of original request. */
20636 /* This field provides original sequence number of the command. */
20639 * This field is the length of the response in bytes. The last byte of
20640 * the response is a valid flag that will read as '1' when the command
20641 * has been completely written to memory.
20649 * This field is used in Output records to indicate that the output is
20650 * completely written to RAM. This field should be read as '1' to
20651 * indicate that the output has been completely written. When writing a
20652 * command completion or response to an internal processor, the order of
20653 * writes has to be such that this field is written last.
20655 } __attribute__((packed));
20657 /* hwrm_cfa_vf_pair_info */
20658 /* Description: VF pair information is returned. */
20659 /* Input (32 bytes) */
20661 struct hwrm_cfa_vf_pair_info_input {
20664 * This value indicates what type of request this is. The format for the
20665 * rest of the command is determined by this field.
20667 uint16_t cmpl_ring;
20669 * This value indicates the what completion ring the request will be
20670 * optionally completed on. If the value is -1, then no CR completion
20671 * will be generated. Any other value must be a valid CR ring_id value
20672 * for this function.
20675 /* This value indicates the command sequence number. */
20676 uint16_t target_id;
20678 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
20679 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
20681 uint64_t resp_addr;
20683 * This is the host address where the response will be written when the
20684 * request is complete. This area must be 16B aligned and must be
20685 * cleared to zero before the request is made.
20688 /* If this flag is set, lookup by name else lookup by index. */
20689 #define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
20690 uint16_t vf_pair_index;
20691 /* vf pair table index. */
20694 char vf_pair_name[32];
20695 /* VF Pair name (32 byte string). */
20696 } __attribute__((packed));
20698 /* Output (64 bytes) */
20700 struct hwrm_cfa_vf_pair_info_output {
20701 uint16_t error_code;
20703 * Pass/Fail or error type Note: receiver to verify the in parameters,
20704 * and fail the call with an error when appropriate
20707 /* This field returns the type of original request. */
20709 /* This field provides original sequence number of the command. */
20712 * This field is the length of the response in bytes. The last byte of
20713 * the response is a valid flag that will read as '1' when the command
20714 * has been completely written to memory.
20716 uint16_t next_vf_pair_index;
20717 /* vf pair table index. */
20719 /* vf pair member a's vf_fid. */
20720 uint16_t vf_a_index;
20721 /* vf pair member a's Linux logical VF number. */
20723 /* vf pair member b's vf_fid. */
20724 uint16_t vf_b_index;
20725 /* vf pair member a's Linux logical VF number. */
20726 uint8_t pair_state;
20727 /* vf pair state. */
20728 /* Pair has been allocated */
20729 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
20730 /* Both pair members are active */
20731 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
20734 char pair_name[32];
20735 /* VF Pair name (32 byte string). */
20742 * This field is used in Output records to indicate that the output is
20743 * completely written to RAM. This field should be read as '1' to
20744 * indicate that the output has been completely written. When writing a
20745 * command completion or response to an internal processor, the order of
20746 * writes has to be such that this field is written last.
20748 } __attribute__((packed));
20750 /* hwrm_cfa_vfr_alloc */
20751 /* Description: VF-R is added to table and resources are allocated. */
20752 /* Input (32 bytes) */
20754 struct hwrm_cfa_vfr_alloc_input {
20757 * This value indicates what type of request this is. The format for the
20758 * rest of the command is determined by this field.
20760 uint16_t cmpl_ring;
20762 * This value indicates the what completion ring the request will be
20763 * optionally completed on. If the value is -1, then no CR completion
20764 * will be generated. Any other value must be a valid CR ring_id value
20765 * for this function.
20768 /* This value indicates the command sequence number. */
20769 uint16_t target_id;
20771 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
20772 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
20774 uint64_t resp_addr;
20776 * This is the host address where the response will be written when the
20777 * request is complete. This area must be 16B aligned and must be
20778 * cleared to zero before the request is made.
20781 /* Logical VF number (range: 0 -> MAX_VFS -1). */
20783 /* This field is reserved for the future use. It shall be set to 0. */
20786 /* VF Representor name (32 byte string). */
20787 } __attribute__((packed));
20789 /* Output (16 bytes) */
20791 struct hwrm_cfa_vfr_alloc_output {
20792 uint16_t error_code;
20794 * Pass/Fail or error type Note: receiver to verify the in parameters,
20795 * and fail the call with an error when appropriate
20798 /* This field returns the type of original request. */
20800 /* This field provides original sequence number of the command. */
20803 * This field is the length of the response in bytes. The last byte of
20804 * the response is a valid flag that will read as '1' when the command
20805 * has been completely written to memory.
20807 uint16_t rx_cfa_code;
20809 uint16_t tx_cfa_action;
20810 /* Tx CFA action. */
20816 * This field is used in Output records to indicate that the output is
20817 * completely written to RAM. This field should be read as '1' to
20818 * indicate that the output has been completely written. When writing a
20819 * command completion or response to an internal processor, the order of
20820 * writes has to be such that this field is written last.
20822 } __attribute__((packed));
20824 /* hwrm_cfa_vfr_free */
20825 /* Description: VF-R is removed from table and resources are released. */
20826 /* Input (24 bytes) */
20828 struct hwrm_cfa_vfr_free_input {
20831 * This value indicates what type of request this is. The format for the
20832 * rest of the command is determined by this field.
20834 uint16_t cmpl_ring;
20836 * This value indicates the what completion ring the request will be
20837 * optionally completed on. If the value is -1, then no CR completion
20838 * will be generated. Any other value must be a valid CR ring_id value
20839 * for this function.
20842 /* This value indicates the command sequence number. */
20843 uint16_t target_id;
20845 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
20846 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
20848 uint64_t resp_addr;
20850 * This is the host address where the response will be written when the
20851 * request is complete. This area must be 16B aligned and must be
20852 * cleared to zero before the request is made.
20855 /* VF Representor name (32 byte string). */
20856 } __attribute__((packed));
20858 /* Output (16 bytes) */
20860 struct hwrm_cfa_vfr_free_output {
20861 uint16_t error_code;
20863 * Pass/Fail or error type Note: receiver to verify the in parameters,
20864 * and fail the call with an error when appropriate
20867 /* This field returns the type of original request. */
20869 /* This field provides original sequence number of the command. */
20872 * This field is the length of the response in bytes. The last byte of
20873 * the response is a valid flag that will read as '1' when the command
20874 * has been completely written to memory.
20882 * This field is used in Output records to indicate that the output is
20883 * completely written to RAM. This field should be read as '1' to
20884 * indicate that the output has been completely written. When writing a
20885 * command completion or response to an internal processor, the order of
20886 * writes has to be such that this field is written last.
20888 } __attribute__((packed));
20890 /* hwrm_tunnel_dst_port_query */
20892 * Description: This function is called by a driver to query tunnel type
20893 * specific destination port configuration.
20895 /* Input (24 bytes) */
20897 struct hwrm_tunnel_dst_port_query_input {
20900 * This value indicates what type of request this is. The format for the
20901 * rest of the command is determined by this field.
20903 uint16_t cmpl_ring;
20905 * This value indicates the what completion ring the request will be
20906 * optionally completed on. If the value is -1, then no CR completion
20907 * will be generated. Any other value must be a valid CR ring_id value
20908 * for this function.
20911 /* This value indicates the command sequence number. */
20912 uint16_t target_id;
20914 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
20915 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
20917 uint64_t resp_addr;
20919 * This is the host address where the response will be written when the
20920 * request is complete. This area must be 16B aligned and must be
20921 * cleared to zero before the request is made.
20923 uint8_t tunnel_type;
20925 /* Virtual eXtensible Local Area Network (VXLAN) */
20926 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
20927 /* Generic Network Virtualization Encapsulation (Geneve) */
20928 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
20929 uint8_t unused_0[7];
20930 } __attribute__((packed));
20932 /* Output (16 bytes) */
20934 struct hwrm_tunnel_dst_port_query_output {
20935 uint16_t error_code;
20937 * Pass/Fail or error type Note: receiver to verify the in parameters,
20938 * and fail the call with an error when appropriate
20941 /* This field returns the type of original request. */
20943 /* This field provides original sequence number of the command. */
20946 * This field is the length of the response in bytes. The last byte of
20947 * the response is a valid flag that will read as '1' when the command
20948 * has been completely written to memory.
20950 uint16_t tunnel_dst_port_id;
20952 * This field represents the identifier of L4 destination port used for
20953 * the given tunnel type. This field is valid for specific tunnel types
20954 * that use layer 4 (e.g. UDP) transports for tunneling.
20956 uint16_t tunnel_dst_port_val; /* big endian */
20958 * This field represents the value of L4 destination port identified by
20959 * tunnel_dst_port_id. This field is valid for specific tunnel types
20960 * that use layer 4 (e.g. UDP) transports for tunneling. This field is
20961 * in network byte order. A value of 0 means that the destination port
20962 * is not configured.
20969 * This field is used in Output records to indicate that the output is
20970 * completely written to RAM. This field should be read as '1' to
20971 * indicate that the output has been completely written. When writing a
20972 * command completion or response to an internal processor, the order of
20973 * writes has to be such that this field is written last.
20975 } __attribute__((packed));
20977 /* hwrm_tunnel_dst_port_alloc */
20979 * Description: This function is called by a driver to allocate l4 destination
20980 * port for a specific tunnel type. The destination port value is provided in
20981 * the input. If the HWRM supports only one global destination port for a tunnel
20982 * type, then the HWRM shall keep track of its usage as described below. # The
20983 * first caller that allocates a destination port shall always succeed and the
20984 * HWRM shall save the destination port configuration for that tunnel type and
20985 * increment the usage count to 1. # Subsequent callers allocating the same
20986 * destination port for that tunnel type shall succeed and the HWRM shall
20987 * increment the usage count for that port for each subsequent caller that
20988 * succeeds. # Any subsequent caller trying to allocate a different destination
20989 * port for that tunnel type shall fail until the usage count for the original
20990 * destination port goes to zero. # A caller that frees a port will cause the
20991 * usage count for that port to decrement.
20993 /* Input (24 bytes) */
20995 struct hwrm_tunnel_dst_port_alloc_input {
20998 * This value indicates what type of request this is. The format for the
20999 * rest of the command is determined by this field.
21001 uint16_t cmpl_ring;
21003 * This value indicates the what completion ring the request will be
21004 * optionally completed on. If the value is -1, then no CR completion
21005 * will be generated. Any other value must be a valid CR ring_id value
21006 * for this function.
21009 /* This value indicates the command sequence number. */
21010 uint16_t target_id;
21012 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
21013 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
21015 uint64_t resp_addr;
21017 * This is the host address where the response will be written when the
21018 * request is complete. This area must be 16B aligned and must be
21019 * cleared to zero before the request is made.
21021 uint8_t tunnel_type;
21023 /* Virtual eXtensible Local Area Network (VXLAN) */
21024 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
21025 /* Generic Network Virtualization Encapsulation (Geneve) */
21026 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
21028 uint16_t tunnel_dst_port_val; /* big endian */
21030 * This field represents the value of L4 destination port used for the
21031 * given tunnel type. This field is valid for specific tunnel types that
21032 * use layer 4 (e.g. UDP) transports for tunneling. This field is in
21033 * network byte order. A value of 0 shall fail the command.
21036 } __attribute__((packed));
21038 /* Output (16 bytes) */
21040 struct hwrm_tunnel_dst_port_alloc_output {
21041 uint16_t error_code;
21043 * Pass/Fail or error type Note: receiver to verify the in parameters,
21044 * and fail the call with an error when appropriate
21047 /* This field returns the type of original request. */
21049 /* This field provides original sequence number of the command. */
21052 * This field is the length of the response in bytes. The last byte of
21053 * the response is a valid flag that will read as '1' when the command
21054 * has been completely written to memory.
21056 uint16_t tunnel_dst_port_id;
21058 * Identifier of a tunnel L4 destination port value. Only applies to
21059 * tunnel types that has l4 destination port parameters.
21068 * This field is used in Output records to indicate that the output is
21069 * completely written to RAM. This field should be read as '1' to
21070 * indicate that the output has been completely written. When writing a
21071 * command completion or response to an internal processor, the order of
21072 * writes has to be such that this field is written last.
21074 } __attribute__((packed));
21076 /* hwrm_tunnel_dst_port_free */
21078 * Description: This function is called by a driver to free l4 destination port
21079 * for a specific tunnel type.
21081 /* Input (24 bytes) */
21083 struct hwrm_tunnel_dst_port_free_input {
21086 * This value indicates what type of request this is. The format for the
21087 * rest of the command is determined by this field.
21089 uint16_t cmpl_ring;
21091 * This value indicates the what completion ring the request will be
21092 * optionally completed on. If the value is -1, then no CR completion
21093 * will be generated. Any other value must be a valid CR ring_id value
21094 * for this function.
21097 /* This value indicates the command sequence number. */
21098 uint16_t target_id;
21100 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
21101 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
21103 uint64_t resp_addr;
21105 * This is the host address where the response will be written when the
21106 * request is complete. This area must be 16B aligned and must be
21107 * cleared to zero before the request is made.
21109 uint8_t tunnel_type;
21111 /* Virtual eXtensible Local Area Network (VXLAN) */
21112 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
21113 /* Generic Network Virtualization Encapsulation (Geneve) */
21114 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
21116 uint16_t tunnel_dst_port_id;
21118 * Identifier of a tunnel L4 destination port value. Only applies to
21119 * tunnel types that has l4 destination port parameters.
21122 } __attribute__((packed));
21124 /* Output (16 bytes) */
21126 struct hwrm_tunnel_dst_port_free_output {
21127 uint16_t error_code;
21129 * Pass/Fail or error type Note: receiver to verify the in parameters,
21130 * and fail the call with an error when appropriate
21133 /* This field returns the type of original request. */
21135 /* This field provides original sequence number of the command. */
21138 * This field is the length of the response in bytes. The last byte of
21139 * the response is a valid flag that will read as '1' when the command
21140 * has been completely written to memory.
21148 * This field is used in Output records to indicate that the output is
21149 * completely written to RAM. This field should be read as '1' to
21150 * indicate that the output has been completely written. When writing a
21151 * command completion or response to an internal processor, the order of
21152 * writes has to be such that this field is written last.
21154 } __attribute__((packed));
21156 /* hwrm_stat_ctx_alloc */
21158 * Description: This command allocates and does basic preparation for a stat
21161 /* Input (32 bytes) */
21163 struct hwrm_stat_ctx_alloc_input {
21166 * This value indicates what type of request this is. The format for the
21167 * rest of the command is determined by this field.
21169 uint16_t cmpl_ring;
21171 * This value indicates the what completion ring the request will be
21172 * optionally completed on. If the value is -1, then no CR completion
21173 * will be generated. Any other value must be a valid CR ring_id value
21174 * for this function.
21177 /* This value indicates the command sequence number. */
21178 uint16_t target_id;
21180 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
21181 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
21183 uint64_t resp_addr;
21185 * This is the host address where the response will be written when the
21186 * request is complete. This area must be 16B aligned and must be
21187 * cleared to zero before the request is made.
21189 uint64_t stats_dma_addr;
21190 /* This is the address for statistic block. */
21191 uint32_t update_period_ms;
21193 * The statistic block update period in ms. e.g. 250ms, 500ms, 750ms,
21194 * 1000ms. If update_period_ms is 0, then the stats update shall be
21195 * never done and the DMA address shall not be used. In this case, the
21196 * stat block can only be read by hwrm_stat_ctx_query command.
21198 uint8_t stat_ctx_flags;
21200 * This field is used to specify statistics context specific
21201 * configuration flags.
21204 * When this bit is set to '1', the statistics context shall be
21205 * allocated for RoCE traffic only. In this case, traffic other than
21206 * offloaded RoCE traffic shall not be included in this statistic
21207 * context. When this bit is set to '0', the statistics context shall be
21208 * used for the network traffic other than offloaded RoCE traffic.
21210 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
21211 uint8_t unused_0[3];
21212 } __attribute__((packed));
21214 /* Output (16 bytes) */
21216 struct hwrm_stat_ctx_alloc_output {
21217 uint16_t error_code;
21219 * Pass/Fail or error type Note: receiver to verify the in parameters,
21220 * and fail the call with an error when appropriate
21223 /* This field returns the type of original request. */
21225 /* This field provides original sequence number of the command. */
21228 * This field is the length of the response in bytes. The last byte of
21229 * the response is a valid flag that will read as '1' when the command
21230 * has been completely written to memory.
21232 uint32_t stat_ctx_id;
21233 /* This is the statistics context ID value. */
21239 * This field is used in Output records to indicate that the output is
21240 * completely written to RAM. This field should be read as '1' to
21241 * indicate that the output has been completely written. When writing a
21242 * command completion or response to an internal processor, the order of
21243 * writes has to be such that this field is written last.
21245 } __attribute__((packed));
21247 /* hwrm_stat_ctx_free */
21248 /* Description: This command is used to free a stat context. */
21249 /* Input (24 bytes) */
21251 struct hwrm_stat_ctx_free_input {
21254 * This value indicates what type of request this is. The format for the
21255 * rest of the command is determined by this field.
21257 uint16_t cmpl_ring;
21259 * This value indicates the what completion ring the request will be
21260 * optionally completed on. If the value is -1, then no CR completion
21261 * will be generated. Any other value must be a valid CR ring_id value
21262 * for this function.
21265 /* This value indicates the command sequence number. */
21266 uint16_t target_id;
21268 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
21269 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
21271 uint64_t resp_addr;
21273 * This is the host address where the response will be written when the
21274 * request is complete. This area must be 16B aligned and must be
21275 * cleared to zero before the request is made.
21277 uint32_t stat_ctx_id;
21278 /* ID of the statistics context that is being queried. */
21280 } __attribute__((packed));
21282 /* Output (16 bytes) */
21284 struct hwrm_stat_ctx_free_output {
21285 uint16_t error_code;
21287 * Pass/Fail or error type Note: receiver to verify the in parameters,
21288 * and fail the call with an error when appropriate
21291 /* This field returns the type of original request. */
21293 /* This field provides original sequence number of the command. */
21296 * This field is the length of the response in bytes. The last byte of
21297 * the response is a valid flag that will read as '1' when the command
21298 * has been completely written to memory.
21300 uint32_t stat_ctx_id;
21301 /* This is the statistics context ID value. */
21307 * This field is used in Output records to indicate that the output is
21308 * completely written to RAM. This field should be read as '1' to
21309 * indicate that the output has been completely written. When writing a
21310 * command completion or response to an internal processor, the order of
21311 * writes has to be such that this field is written last.
21313 } __attribute__((packed));
21315 /* hwrm_stat_ctx_query */
21316 /* Description: This command returns statistics of a context. */
21317 /* Input (24 bytes) */
21319 struct hwrm_stat_ctx_query_input {
21322 * This value indicates what type of request this is. The format for the
21323 * rest of the command is determined by this field.
21325 uint16_t cmpl_ring;
21327 * This value indicates the what completion ring the request will be
21328 * optionally completed on. If the value is -1, then no CR completion
21329 * will be generated. Any other value must be a valid CR ring_id value
21330 * for this function.
21333 /* This value indicates the command sequence number. */
21334 uint16_t target_id;
21336 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
21337 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
21339 uint64_t resp_addr;
21341 * This is the host address where the response will be written when the
21342 * request is complete. This area must be 16B aligned and must be
21343 * cleared to zero before the request is made.
21345 uint32_t stat_ctx_id;
21346 /* ID of the statistics context that is being queried. */
21348 } __attribute__((packed));
21350 /* Output (176 bytes) */
21352 struct hwrm_stat_ctx_query_output {
21353 uint16_t error_code;
21355 * Pass/Fail or error type Note: receiver to verify the in parameters,
21356 * and fail the call with an error when appropriate
21359 /* This field returns the type of original request. */
21361 /* This field provides original sequence number of the command. */
21364 * This field is the length of the response in bytes. The last byte of
21365 * the response is a valid flag that will read as '1' when the command
21366 * has been completely written to memory.
21368 uint64_t tx_ucast_pkts;
21369 /* Number of transmitted unicast packets */
21370 uint64_t tx_mcast_pkts;
21371 /* Number of transmitted multicast packets */
21372 uint64_t tx_bcast_pkts;
21373 /* Number of transmitted broadcast packets */
21374 uint64_t tx_err_pkts;
21375 /* Number of transmitted packets with error */
21376 uint64_t tx_drop_pkts;
21377 /* Number of dropped packets on transmit path */
21378 uint64_t tx_ucast_bytes;
21379 /* Number of transmitted bytes for unicast traffic */
21380 uint64_t tx_mcast_bytes;
21381 /* Number of transmitted bytes for multicast traffic */
21382 uint64_t tx_bcast_bytes;
21383 /* Number of transmitted bytes for broadcast traffic */
21384 uint64_t rx_ucast_pkts;
21385 /* Number of received unicast packets */
21386 uint64_t rx_mcast_pkts;
21387 /* Number of received multicast packets */
21388 uint64_t rx_bcast_pkts;
21389 /* Number of received broadcast packets */
21390 uint64_t rx_err_pkts;
21391 /* Number of received packets with error */
21392 uint64_t rx_drop_pkts;
21393 /* Number of dropped packets on received path */
21394 uint64_t rx_ucast_bytes;
21395 /* Number of received bytes for unicast traffic */
21396 uint64_t rx_mcast_bytes;
21397 /* Number of received bytes for multicast traffic */
21398 uint64_t rx_bcast_bytes;
21399 /* Number of received bytes for broadcast traffic */
21400 uint64_t rx_agg_pkts;
21401 /* Number of aggregated unicast packets */
21402 uint64_t rx_agg_bytes;
21403 /* Number of aggregated unicast bytes */
21404 uint64_t rx_agg_events;
21405 /* Number of aggregation events */
21406 uint64_t rx_agg_aborts;
21407 /* Number of aborted aggregations */
21414 * This field is used in Output records to indicate that the output is
21415 * completely written to RAM. This field should be read as '1' to
21416 * indicate that the output has been completely written. When writing a
21417 * command completion or response to an internal processor, the order of
21418 * writes has to be such that this field is written last.
21420 } __attribute__((packed));
21422 /* hwrm_stat_ctx_clr_stats */
21423 /* Description: This command clears statistics of a context. */
21424 /* Input (24 bytes) */
21426 struct hwrm_stat_ctx_clr_stats_input {
21429 * This value indicates what type of request this is. The format for the
21430 * rest of the command is determined by this field.
21432 uint16_t cmpl_ring;
21434 * This value indicates the what completion ring the request will be
21435 * optionally completed on. If the value is -1, then no CR completion
21436 * will be generated. Any other value must be a valid CR ring_id value
21437 * for this function.
21440 /* This value indicates the command sequence number. */
21441 uint16_t target_id;
21443 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
21444 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
21446 uint64_t resp_addr;
21448 * This is the host address where the response will be written when the
21449 * request is complete. This area must be 16B aligned and must be
21450 * cleared to zero before the request is made.
21452 uint32_t stat_ctx_id;
21453 /* ID of the statistics context that is being queried. */
21455 } __attribute__((packed));
21457 /* Output (16 bytes) */
21459 struct hwrm_stat_ctx_clr_stats_output {
21460 uint16_t error_code;
21462 * Pass/Fail or error type Note: receiver to verify the in parameters,
21463 * and fail the call with an error when appropriate
21466 /* This field returns the type of original request. */
21468 /* This field provides original sequence number of the command. */
21471 * This field is the length of the response in bytes. The last byte of
21472 * the response is a valid flag that will read as '1' when the command
21473 * has been completely written to memory.
21481 * This field is used in Output records to indicate that the output is
21482 * completely written to RAM. This field should be read as '1' to
21483 * indicate that the output has been completely written. When writing a
21484 * command completion or response to an internal processor, the order of
21485 * writes has to be such that this field is written last.
21487 } __attribute__((packed));
21489 /* hwrm_fw_reset */
21491 * Description: This function is called by a driver to self reset the firmware
21492 * running on the processor indicated by the embedded_proc_type.
21494 /* Input (24 bytes) */
21496 struct hwrm_fw_reset_input {
21499 * This value indicates what type of request this is. The format for the
21500 * rest of the command is determined by this field.
21502 uint16_t cmpl_ring;
21504 * This value indicates the what completion ring the request will be
21505 * optionally completed on. If the value is -1, then no CR completion
21506 * will be generated. Any other value must be a valid CR ring_id value
21507 * for this function.
21510 /* This value indicates the command sequence number. */
21511 uint16_t target_id;
21513 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
21514 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
21516 uint64_t resp_addr;
21518 * This is the host address where the response will be written when the
21519 * request is complete. This area must be 16B aligned and must be
21520 * cleared to zero before the request is made.
21522 uint8_t embedded_proc_type;
21523 /* Type of embedded processor. */
21524 /* Boot Processor */
21525 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT UINT32_C(0x0)
21526 /* Management Processor */
21527 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT UINT32_C(0x1)
21528 /* Network control processor */
21529 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL UINT32_C(0x2)
21530 /* RoCE control processor */
21531 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE UINT32_C(0x3)
21533 * Host (in multi-host environment): This is only valid if
21536 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST UINT32_C(0x4)
21537 uint8_t selfrst_status;
21538 /* Type of self reset. */
21539 /* No Self Reset */
21540 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE UINT32_C(0x0)
21541 /* Self Reset as soon as possible to do so safely */
21542 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP UINT32_C(0x1)
21543 /* Self Reset on PCIe Reset */
21544 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST UINT32_C(0x2)
21547 * Indicate which host is being reset. 0 means first host. Only valid
21548 * when embedded_proc_type is host in multihost environment
21550 uint8_t unused_0[5];
21551 } __attribute__((packed));
21553 /* Output (16 bytes) */
21555 struct hwrm_fw_reset_output {
21556 uint16_t error_code;
21558 * Pass/Fail or error type Note: receiver to verify the in parameters,
21559 * and fail the call with an error when appropriate
21562 /* This field returns the type of original request. */
21564 /* This field provides original sequence number of the command. */
21567 * This field is the length of the response in bytes. The last byte of
21568 * the response is a valid flag that will read as '1' when the command
21569 * has been completely written to memory.
21571 uint8_t selfrst_status;
21572 /* Type of self reset. */
21573 /* No Self Reset */
21574 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE UINT32_C(0x0)
21575 /* Self Reset as soon as possible to do so safely */
21576 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP UINT32_C(0x1)
21577 /* Self Reset on PCIe Reset */
21578 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST UINT32_C(0x2)
21586 * This field is used in Output records to indicate that the output is
21587 * completely written to RAM. This field should be read as '1' to
21588 * indicate that the output has been completely written. When writing a
21589 * command completion or response to an internal processor, the order of
21590 * writes has to be such that this field is written last.
21592 } __attribute__((packed));
21594 /* hwrm_fw_qstatus */
21596 * Description: This function is called by a driver to query the status of the
21597 * firmware running on the processor indicated by the embedded_proc_type.
21599 /* Input (24 bytes) */
21601 struct hwrm_fw_qstatus_input {
21604 * This value indicates what type of request this is. The format for the
21605 * rest of the command is determined by this field.
21607 uint16_t cmpl_ring;
21609 * This value indicates the what completion ring the request will be
21610 * optionally completed on. If the value is -1, then no CR completion
21611 * will be generated. Any other value must be a valid CR ring_id value
21612 * for this function.
21615 /* This value indicates the command sequence number. */
21616 uint16_t target_id;
21618 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
21619 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
21621 uint64_t resp_addr;
21623 * This is the host address where the response will be written when the
21624 * request is complete. This area must be 16B aligned and must be
21625 * cleared to zero before the request is made.
21627 uint8_t embedded_proc_type;
21628 /* Type of embedded processor. */
21629 /* Boot Processor */
21630 #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_BOOT UINT32_C(0x0)
21631 /* Management Processor */
21632 #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_MGMT UINT32_C(0x1)
21633 /* Network control processor */
21634 #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_NETCTRL UINT32_C(0x2)
21635 /* RoCE control processor */
21636 #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_ROCE UINT32_C(0x3)
21638 * Host (in multi-host environment): This is only valid if
21641 #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_HOST UINT32_C(0x4)
21642 uint8_t unused_0[7];
21643 } __attribute__((packed));
21645 /* Output (16 bytes) */
21647 struct hwrm_fw_qstatus_output {
21648 uint16_t error_code;
21650 * Pass/Fail or error type Note: receiver to verify the in parameters,
21651 * and fail the call with an error when appropriate
21654 /* This field returns the type of original request. */
21656 /* This field provides original sequence number of the command. */
21659 * This field is the length of the response in bytes. The last byte of
21660 * the response is a valid flag that will read as '1' when the command
21661 * has been completely written to memory.
21663 uint8_t selfrst_status;
21664 /* Type of self reset. */
21665 /* No Self Reset */
21666 #define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTNONE UINT32_C(0x0)
21667 /* Self Reset as soon as possible to do so safely */
21668 #define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTASAP UINT32_C(0x1)
21669 /* Self Reset on PCIe Reset */
21670 #define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST UINT32_C(0x2)
21678 * This field is used in Output records to indicate that the output is
21679 * completely written to RAM. This field should be read as '1' to
21680 * indicate that the output has been completely written. When writing a
21681 * command completion or response to an internal processor, the order of
21682 * writes has to be such that this field is written last.
21684 } __attribute__((packed));
21686 /* hwrm_fw_set_time */
21688 * Description: Inform the HWRM firmware of the current date/time. Ideally, the
21689 * date/time will be current time in GMT/UTC and the zone value will be 0
21690 * (indicating UTC). If the time zone is not known, the zone value shall be
21691 * 0xffff. Other values for zone are discouraged, but if specified, they
21692 * indicate the number of minutes east of UTC, while zones west of UTC are
21693 * represented with a 2's complement negative value (e.g. PST would be -480
21694 * while PDT would be -420).
21696 /* Input (32 bytes) */
21698 struct hwrm_fw_set_time_input {
21701 * This value indicates what type of request this is. The format for the
21702 * rest of the command is determined by this field.
21704 uint16_t cmpl_ring;
21706 * This value indicates the what completion ring the request will be
21707 * optionally completed on. If the value is -1, then no CR completion
21708 * will be generated. Any other value must be a valid CR ring_id value
21709 * for this function.
21712 /* This value indicates the command sequence number. */
21713 uint16_t target_id;
21715 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
21716 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
21718 uint64_t resp_addr;
21720 * This is the host address where the response will be written when the
21721 * request is complete. This area must be 16B aligned and must be
21722 * cleared to zero before the request is made.
21726 /* Date/time is not known */
21727 #define HWRM_FW_SET_TIME_INPUT_YEAR_UNKNOWN UINT32_C(0x0)
21729 /* Current month of year (1-12) */
21731 /* Current day of month (1-31) */
21733 /* Current hour (0-23) */
21735 /* Current minute (0-59) */
21737 /* Current second (0-59) */
21739 uint16_t millisecond;
21740 /* Current millisecond (0-999) */
21742 /* Minutes east of UTC, 0xffff if TZ is not known */
21743 /* Time zone is Coordinated Universal Time (UTC) */
21744 #define HWRM_FW_SET_TIME_INPUT_ZONE_UTC UINT32_C(0x0)
21745 /* Time zone is not known */
21746 #define HWRM_FW_SET_TIME_INPUT_ZONE_UNKNOWN UINT32_C(0xffff)
21748 } __attribute__((packed));
21750 /* Output (16 bytes) */
21752 struct hwrm_fw_set_time_output {
21753 uint16_t error_code;
21755 * Pass/Fail or error type Note: receiver to verify the in parameters,
21756 * and fail the call with an error when appropriate
21759 /* This field returns the type of original request. */
21761 /* This field provides original sequence number of the command. */
21764 * This field is the length of the response in bytes. The last byte of
21765 * the response is a valid flag that will read as '1' when the command
21766 * has been completely written to memory.
21774 * This field is used in Output records to indicate that the output is
21775 * completely written to RAM. This field should be read as '1' to
21776 * indicate that the output has been completely written. When writing a
21777 * command completion or response to an internal processor, the order of
21778 * writes has to be such that this field is written last.
21780 } __attribute__((packed));
21782 /* hwrm_fw_get_time */
21783 /* Description: Query the HWRM firmware's notion of the current date/time. */
21784 /* Input (16 bytes) */
21786 struct hwrm_fw_get_time_input {
21789 * This value indicates what type of request this is. The format for the
21790 * rest of the command is determined by this field.
21792 uint16_t cmpl_ring;
21794 * This value indicates the what completion ring the request will be
21795 * optionally completed on. If the value is -1, then no CR completion
21796 * will be generated. Any other value must be a valid CR ring_id value
21797 * for this function.
21800 /* This value indicates the command sequence number. */
21801 uint16_t target_id;
21803 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
21804 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
21806 uint64_t resp_addr;
21808 * This is the host address where the response will be written when the
21809 * request is complete. This area must be 16B aligned and must be
21810 * cleared to zero before the request is made.
21812 } __attribute__((packed));
21814 /* Output (24 bytes) */
21816 struct hwrm_fw_get_time_output {
21817 uint16_t error_code;
21819 * Pass/Fail or error type Note: receiver to verify the in parameters,
21820 * and fail the call with an error when appropriate
21823 /* This field returns the type of original request. */
21825 /* This field provides original sequence number of the command. */
21828 * This field is the length of the response in bytes. The last byte of
21829 * the response is a valid flag that will read as '1' when the command
21830 * has been completely written to memory.
21834 /* Date/time is not known */
21835 #define HWRM_FW_GET_TIME_OUTPUT_YEAR_UNKNOWN UINT32_C(0x0)
21837 /* Current month of year (1-12) */
21839 /* Current day of month (1-31) */
21841 /* Current hour (0-23) */
21843 /* Current minute (0-59) */
21845 /* Current second (0-59) */
21847 uint16_t millisecond;
21848 /* Current millisecond (0-999) */
21850 /* Minutes east of UTC, 0xffff if TZ is not known */
21851 /* Time zone is Coordinated Universal Time (UTC) */
21852 #define HWRM_FW_GET_TIME_OUTPUT_ZONE_UTC UINT32_C(0x0)
21853 /* Time zone is not known */
21854 #define HWRM_FW_GET_TIME_OUTPUT_ZONE_UNKNOWN UINT32_C(0xffff)
21860 * This field is used in Output records to indicate that the output is
21861 * completely written to RAM. This field should be read as '1' to
21862 * indicate that the output has been completely written. When writing a
21863 * command completion or response to an internal processor, the order of
21864 * writes has to be such that this field is written last.
21866 } __attribute__((packed));
21868 /* hwrm_fw_set_structured_data */
21870 * Description: There can be a variable number of Structure Data Headers (SDH)
21871 * between offset 0x0 and the 'valid' field to handle customizable return
21872 * values. Each Structure Data Header will include one defined structure. The
21873 * number of returned structures can be 0, in which case the 'valid' field
21874 * starts at offset 0x8. The 'valid' field offset is adjusted based on the
21875 * Structure Data Header length and the length of the structured data it
21878 /* Input (32 bytes) */
21880 struct hwrm_fw_set_structured_data_input {
21883 * This value indicates what type of request this is. The format for the
21884 * rest of the command is determined by this field.
21886 uint16_t cmpl_ring;
21888 * This value indicates the what completion ring the request will be
21889 * optionally completed on. If the value is -1, then no CR completion
21890 * will be generated. Any other value must be a valid CR ring_id value
21891 * for this function.
21894 /* This value indicates the command sequence number. */
21895 uint16_t target_id;
21897 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
21898 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
21900 uint64_t resp_addr;
21902 * This is the host address where the response will be written when the
21903 * request is complete. This area must be 16B aligned and must be
21904 * cleared to zero before the request is made.
21906 uint64_t src_data_addr;
21907 /* This is the host address where structured data will be copied from */
21909 /* size of data in bytes */
21912 * a count of the number of Structured Data Headers in the data pointed
21913 * by src_data_addr.
21915 uint8_t unused_0[5];
21916 } __attribute__((packed));
21918 /* Output (16 bytes) */
21920 struct hwrm_fw_set_structured_data_output {
21921 uint16_t error_code;
21923 * Pass/Fail or error type Note: receiver to verify the in parameters,
21924 * and fail the call with an error when appropriate
21927 /* This field returns the type of original request. */
21929 /* This field provides original sequence number of the command. */
21932 * This field is the length of the response in bytes. The last byte of
21933 * the response is a valid flag that will read as '1' when the command
21934 * has been completely written to memory.
21942 * This field is used in Output records to indicate that the output is
21943 * completely written to RAM. This field should be read as '1' to
21944 * indicate that the output has been completely written. When writing a
21945 * command completion or response to an internal processor, the order of
21946 * writes has to be such that this field is written last.
21948 } __attribute__((packed));
21950 /* Command specific Error Codes (8 bytes) */
21952 struct hwrm_fw_set_structured_data_cmd_err {
21955 * command specific error codes that goes to the cmd_err field in Common
21956 * HWRM Error Response.
21958 /* Unknown error */
21959 #define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
21960 /* count_of_headers is incorrect */
21961 #define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT UINT32_C(0x1)
21962 /* data improperly formatted */
21963 #define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT UINT32_C(0x2)
21964 /* unknown structure ID(s) */
21965 #define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID UINT32_C(0x3)
21966 uint8_t unused_0[7];
21967 } __attribute__((packed));
21969 /* hwrm_fw_get_structured_data */
21970 /* Input (32 bytes) */
21972 struct hwrm_fw_get_structured_data_input {
21975 * This value indicates what type of request this is. The format for the
21976 * rest of the command is determined by this field.
21978 uint16_t cmpl_ring;
21980 * This value indicates the what completion ring the request will be
21981 * optionally completed on. If the value is -1, then no CR completion
21982 * will be generated. Any other value must be a valid CR ring_id value
21983 * for this function.
21986 /* This value indicates the command sequence number. */
21987 uint16_t target_id;
21989 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
21990 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
21992 uint64_t resp_addr;
21994 * This is the host address where the response will be written when the
21995 * request is complete. This area must be 16B aligned and must be
21996 * cleared to zero before the request is made.
21998 uint64_t dest_data_addr;
21999 /* This is the host address where structured data will be copied to */
22001 /* size of data in bytes */
22002 uint16_t structure_id;
22004 * Structure_id is the id of the structure data requesting and count is
22005 * a requested number of instances of this data requested. The actual
22006 * number will be returned in count_of_headers
22010 * Subtype is an optional field used to specify additional information
22011 * of the data being retrieved. For example, if data can be categorized
22012 * as "live" vs "saved" then this field can be used to provide an
22013 * indication of "saved" vs "live" data. Not all structured data
22014 * supports subtypes and if they are supported then the structured data
22015 * will specify the valid values. If structured data is requested that
22016 * supports subtypes but no subtype is given then it is implementation
22017 * specific what will be returned. Some structure data can support a
22018 * subtype of "All" which would cause a list of structures to be
22019 * returned for all supported subtypes. "All" is only used on the
22020 * hwrm_get_structured_data command.
22022 #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_ALL UINT32_C(0xffff)
22023 #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NEAR_BRIDGE_ADMIN UINT32_C(0x100)
22024 #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NEAR_BRIDGE_PEER UINT32_C(0x101)
22025 #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NEAR_BRIDGE_OPERATIONAL UINT32_C(0x102)
22026 #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NON_TPMR_ADMIN UINT32_C(0x200)
22027 #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NON_TPMR_PEER UINT32_C(0x201)
22028 #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NON_TPMR_OPERATIONAL UINT32_C(0x202)
22029 #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_HOST_OPERATIONAL UINT32_C(0x300)
22031 /* Number of elements. This allows support of arrayed data */
22033 } __attribute__((packed));
22035 /* Output (16 bytes) */
22037 struct hwrm_fw_get_structured_data_output {
22038 uint16_t error_code;
22040 * Pass/Fail or error type Note: receiver to verify the in parameters,
22041 * and fail the call with an error when appropriate
22044 /* This field returns the type of original request. */
22046 /* This field provides original sequence number of the command. */
22049 * This field is the length of the response in bytes. The last byte of
22050 * the response is a valid flag that will read as '1' when the command
22051 * has been completely written to memory.
22055 * a count of the number of Structured Data Headers in the data pointed
22056 * by dest_data_addr.
22065 * This field is used in Output records to indicate that the output is
22066 * completely written to RAM. This field should be read as '1' to
22067 * indicate that the output has been completely written. When writing a
22068 * command completion or response to an internal processor, the order of
22069 * writes has to be such that this field is written last.
22071 } __attribute__((packed));
22073 /* Command specific Error Codes (8 bytes) */
22075 struct hwrm_fw_get_structured_data_cmd_err {
22078 * command specific error codes that goes to the cmd_err field in Common
22079 * HWRM Error Response.
22081 /* Unknown error */
22082 #define HWRM_FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
22083 /* unknown structure ID(s) */
22084 #define HWRM_FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID UINT32_C(0x3)
22085 uint8_t unused_0[7];
22086 } __attribute__((packed));
22088 /* hwrm_fw_ipc_mailbox */
22089 /* Input (32 bytes) */
22091 struct hwrm_fw_ipc_mailbox_input {
22094 * This value indicates what type of request this is. The format for the
22095 * rest of the command is determined by this field.
22097 uint16_t cmpl_ring;
22099 * This value indicates the what completion ring the request will be
22100 * optionally completed on. If the value is -1, then no CR completion
22101 * will be generated. Any other value must be a valid CR ring_id value
22102 * for this function.
22105 /* This value indicates the command sequence number. */
22106 uint16_t target_id;
22108 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
22109 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
22111 uint64_t resp_addr;
22113 * This is the host address where the response will be written when the
22114 * request is complete. This area must be 16B aligned and must be
22115 * cleared to zero before the request is made.
22119 /* unused is 8 b */
22121 /* asynchronous event to hosts. */
22124 uint32_t event_data1;
22125 /* event data1 of asynchronous event */
22126 uint32_t event_data2;
22127 /* event data2 of asynchronous event */
22129 } __attribute__((packed));
22131 /* Output (16 bytes) */
22133 struct hwrm_fw_ipc_mailbox_output {
22134 uint16_t error_code;
22136 * Pass/Fail or error type Note: receiver to verify the in parameters,
22137 * and fail the call with an error when appropriate
22140 /* This field returns the type of original request. */
22142 /* This field provides original sequence number of the command. */
22145 * This field is the length of the response in bytes. The last byte of
22146 * the response is a valid flag that will read as '1' when the command
22147 * has been completely written to memory.
22155 * This field is used in Output records to indicate that the output is
22156 * completely written to RAM. This field should be read as '1' to
22157 * indicate that the output has been completely written. When writing a
22158 * command completion or response to an internal processor, the order of
22159 * writes has to be such that this field is written last.
22161 } __attribute__((packed));
22163 /* Command specific Error Codes (8 bytes) */
22165 struct hwrm_fw_ipc_mailbox_cmd_err {
22168 * command specific error codes that goes to the cmd_err field in Common
22169 * HWRM Error Response.
22171 /* Unknown error */
22172 #define HWRM_FW_IPC_MAILBOX_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
22173 /* invalid event */
22174 #define HWRM_FW_IPC_MAILBOX_CMD_ERR_CODE_BAD_ID UINT32_C(0x3)
22175 uint8_t unused_0[7];
22176 } __attribute__((packed));
22178 /* hwrm_exec_fwd_resp */
22180 * Description: This command is used to send an encapsulated request to the
22181 * HWRM. This command instructs the HWRM to execute the request and forward the
22182 * response of the encapsulated request to the location specified in the
22183 * original request that is encapsulated. The target id of this command shall be
22184 * set to 0xFFFF (HWRM). The response location in this command shall be used to
22185 * acknowledge the receipt of the encapsulated request and forwarding of the
22188 /* Input (128 bytes) */
22190 struct hwrm_exec_fwd_resp_input {
22193 * This value indicates what type of request this is. The format for the
22194 * rest of the command is determined by this field.
22196 uint16_t cmpl_ring;
22198 * This value indicates the what completion ring the request will be
22199 * optionally completed on. If the value is -1, then no CR completion
22200 * will be generated. Any other value must be a valid CR ring_id value
22201 * for this function.
22204 /* This value indicates the command sequence number. */
22205 uint16_t target_id;
22207 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
22208 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
22210 uint64_t resp_addr;
22212 * This is the host address where the response will be written when the
22213 * request is complete. This area must be 16B aligned and must be
22214 * cleared to zero before the request is made.
22216 uint32_t encap_request[26];
22218 * This is an encapsulated request. This request should be executed by
22219 * the HWRM and the response should be provided in the response buffer
22220 * inside the encapsulated request.
22222 uint16_t encap_resp_target_id;
22224 * This value indicates the target id of the response to the
22225 * encapsulated request. 0x0 - 0xFFF8 - Used for function ids 0xFFF8 -
22226 * 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
22228 uint16_t unused_0[3];
22229 } __attribute__((packed));
22231 /* Output (16 bytes) */
22233 struct hwrm_exec_fwd_resp_output {
22234 uint16_t error_code;
22236 * Pass/Fail or error type Note: receiver to verify the in parameters,
22237 * and fail the call with an error when appropriate
22240 /* This field returns the type of original request. */
22242 /* This field provides original sequence number of the command. */
22245 * This field is the length of the response in bytes. The last byte of
22246 * the response is a valid flag that will read as '1' when the command
22247 * has been completely written to memory.
22255 * This field is used in Output records to indicate that the output is
22256 * completely written to RAM. This field should be read as '1' to
22257 * indicate that the output has been completely written. When writing a
22258 * command completion or response to an internal processor, the order of
22259 * writes has to be such that this field is written last.
22261 } __attribute__((packed));
22263 /* hwrm_reject_fwd_resp */
22265 * Description: This command is used to send an encapsulated request to the
22266 * HWRM. This command instructs the HWRM to reject the request and forward the
22267 * error response of the encapsulated request to the location specified in the
22268 * original request that is encapsulated. The target id of this command shall be
22269 * set to 0xFFFF (HWRM). The response location in this command shall be used to
22270 * acknowledge the receipt of the encapsulated request and forwarding of the
22273 /* Input (128 bytes) */
22275 struct hwrm_reject_fwd_resp_input {
22278 * This value indicates what type of request this is. The format for the
22279 * rest of the command is determined by this field.
22281 uint16_t cmpl_ring;
22283 * This value indicates the what completion ring the request will be
22284 * optionally completed on. If the value is -1, then no CR completion
22285 * will be generated. Any other value must be a valid CR ring_id value
22286 * for this function.
22289 /* This value indicates the command sequence number. */
22290 uint16_t target_id;
22292 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
22293 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
22295 uint64_t resp_addr;
22297 * This is the host address where the response will be written when the
22298 * request is complete. This area must be 16B aligned and must be
22299 * cleared to zero before the request is made.
22301 uint32_t encap_request[26];
22303 * This is an encapsulated request. This request should be rejected by
22304 * the HWRM and the error response should be provided in the response
22305 * buffer inside the encapsulated request.
22307 uint16_t encap_resp_target_id;
22309 * This value indicates the target id of the response to the
22310 * encapsulated request. 0x0 - 0xFFF8 - Used for function ids 0xFFF8 -
22311 * 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
22313 uint16_t unused_0[3];
22314 } __attribute__((packed));
22316 /* Output (16 bytes) */
22318 struct hwrm_reject_fwd_resp_output {
22319 uint16_t error_code;
22321 * Pass/Fail or error type Note: receiver to verify the in parameters,
22322 * and fail the call with an error when appropriate
22325 /* This field returns the type of original request. */
22327 /* This field provides original sequence number of the command. */
22330 * This field is the length of the response in bytes. The last byte of
22331 * the response is a valid flag that will read as '1' when the command
22332 * has been completely written to memory.
22340 * This field is used in Output records to indicate that the output is
22341 * completely written to RAM. This field should be read as '1' to
22342 * indicate that the output has been completely written. When writing a
22343 * command completion or response to an internal processor, the order of
22344 * writes has to be such that this field is written last.
22346 } __attribute__((packed));
22348 /* hwrm_fwd_resp */
22350 * Description: This command is used to send an encapsulated response to the
22351 * HWRM. The HWRM shall forward this response based on the target id. The
22352 * response address provided in this command shall be used to acknowledge the
22353 * receipt of the encapsulated response. The encapsulated response address
22354 * provided in this command shall be used to provide the encapsulated response.
22356 /* Input (40 bytes) */
22358 struct hwrm_fwd_resp_input {
22361 * This value indicates what type of request this is. The format for the
22362 * rest of the command is determined by this field.
22364 uint16_t cmpl_ring;
22366 * This value indicates the what completion ring the request will be
22367 * optionally completed on. If the value is -1, then no CR completion
22368 * will be generated. Any other value must be a valid CR ring_id value
22369 * for this function.
22372 /* This value indicates the command sequence number. */
22373 uint16_t target_id;
22375 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
22376 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
22378 uint64_t resp_addr;
22380 * This is the host address where the response will be written when the
22381 * request is complete. This area must be 16B aligned and must be
22382 * cleared to zero before the request is made.
22384 uint16_t encap_resp_target_id;
22386 * This value indicates the target id of the encapsulated response. 0x0
22387 * - 0xFFF8 - Used for function ids 0xFFF8 - 0xFFFE - Reserved for
22388 * internal processors 0xFFFF - HWRM
22390 uint16_t encap_resp_cmpl_ring;
22392 * This value indicates the completion ring the encapsulated response
22393 * will be optionally completed on. If the value is -1, then no CR
22394 * completion shall be generated for the encapsulated response. Any
22395 * other value must be a valid CR ring_id value. If a valid
22396 * encap_resp_cmpl_ring is provided, then a CR completion shall be
22397 * generated for the encapsulated response.
22399 uint16_t encap_resp_len;
22400 /* This field indicates the length of encapsulated response. */
22403 uint64_t encap_resp_addr;
22405 * This is the host address where the encapsulated response will be
22406 * written. This area must be 16B aligned and must be cleared to zero
22407 * before the original request is made.
22409 uint32_t encap_resp[24];
22410 /* This is an encapsulated response. */
22411 } __attribute__((packed));
22413 /* Output (16 bytes) */
22415 struct hwrm_fwd_resp_output {
22416 uint16_t error_code;
22418 * Pass/Fail or error type Note: receiver to verify the in parameters,
22419 * and fail the call with an error when appropriate
22422 /* This field returns the type of original request. */
22424 /* This field provides original sequence number of the command. */
22427 * This field is the length of the response in bytes. The last byte of
22428 * the response is a valid flag that will read as '1' when the command
22429 * has been completely written to memory.
22437 * This field is used in Output records to indicate that the output is
22438 * completely written to RAM. This field should be read as '1' to
22439 * indicate that the output has been completely written. When writing a
22440 * command completion or response to an internal processor, the order of
22441 * writes has to be such that this field is written last.
22443 } __attribute__((packed));
22445 /* hwrm_fwd_async_event_cmpl */
22447 * Description: This command is used to send an encapsulated asynchronous event
22448 * completion to the HWRM. The HWRM shall forward this asynchronous event
22449 * completion to target(s) specified in the command. The HWRM shall complete
22450 * this command only after forwarding asynchronous event completion to specified
22453 /* Input (32 bytes) */
22455 struct hwrm_fwd_async_event_cmpl_input {
22458 * This value indicates what type of request this is. The format for the
22459 * rest of the command is determined by this field.
22461 uint16_t cmpl_ring;
22463 * This value indicates the what completion ring the request will be
22464 * optionally completed on. If the value is -1, then no CR completion
22465 * will be generated. Any other value must be a valid CR ring_id value
22466 * for this function.
22469 /* This value indicates the command sequence number. */
22470 uint16_t target_id;
22472 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
22473 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
22475 uint64_t resp_addr;
22477 * This is the host address where the response will be written when the
22478 * request is complete. This area must be 16B aligned and must be
22479 * cleared to zero before the request is made.
22481 uint16_t encap_async_event_target_id;
22483 * This value indicates the target id of the encapsulated asynchronous
22484 * event. 0x0 - 0xFFF8 - Used for function ids 0xFFF8 - 0xFFFE -
22485 * Reserved for internal processors 0xFFFF - Broadcast to all children
22486 * VFs (only applicable when a PF is the requester)
22490 uint8_t unused_2[3];
22492 uint32_t encap_async_event_cmpl[4];
22493 /* This is an encapsulated asynchronous event completion. */
22494 } __attribute__((packed));
22496 /* Output (16 bytes) */
22498 struct hwrm_fwd_async_event_cmpl_output {
22499 uint16_t error_code;
22501 * Pass/Fail or error type Note: receiver to verify the in parameters,
22502 * and fail the call with an error when appropriate
22505 /* This field returns the type of original request. */
22507 /* This field provides original sequence number of the command. */
22510 * This field is the length of the response in bytes. The last byte of
22511 * the response is a valid flag that will read as '1' when the command
22512 * has been completely written to memory.
22520 * This field is used in Output records to indicate that the output is
22521 * completely written to RAM. This field should be read as '1' to
22522 * indicate that the output has been completely written. When writing a
22523 * command completion or response to an internal processor, the order of
22524 * writes has to be such that this field is written last.
22526 } __attribute__((packed));
22528 /* hwrm_temp_monitor_query */
22530 * Description: A temperature monitor is used to query the device temperature.
22532 /* Input (16 bytes) */
22534 struct hwrm_temp_monitor_query_input {
22537 * This value indicates what type of request this is. The format for the
22538 * rest of the command is determined by this field.
22540 uint16_t cmpl_ring;
22542 * This value indicates the what completion ring the request will be
22543 * optionally completed on. If the value is -1, then no CR completion
22544 * will be generated. Any other value must be a valid CR ring_id value
22545 * for this function.
22548 /* This value indicates the command sequence number. */
22549 uint16_t target_id;
22551 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
22552 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
22554 uint64_t resp_addr;
22556 * This is the host address where the response will be written when the
22557 * request is complete. This area must be 16B aligned and must be
22558 * cleared to zero before the request is made.
22560 } __attribute__((packed));
22562 /* Output (16 bytes) */
22564 struct hwrm_temp_monitor_query_output {
22565 uint16_t error_code;
22567 * Pass/Fail or error type Note: receiver to verify the in parameters,
22568 * and fail the call with an error when appropriate
22571 /* This field returns the type of original request. */
22573 /* This field provides original sequence number of the command. */
22576 * This field is the length of the response in bytes. The last byte of
22577 * the response is a valid flag that will read as '1' when the command
22578 * has been completely written to memory.
22581 /* The HWRM shall provide the current temperature of device in Celsius. */
22589 * This field is used in Output records to indicate that the output is
22590 * completely written to RAM. This field should be read as '1' to
22591 * indicate that the output has been completely written. When writing a
22592 * command completion or response to an internal processor, the order of
22593 * writes has to be such that this field is written last.
22595 } __attribute__((packed));
22597 /* hwrm_wol_filter_alloc */
22599 * Description: A Wake-On-LAN (WoL) filter is a filter resource that is used to
22600 * identify a WoL packet. # Among all function drivers, the HWRM shall only
22601 * allow PF drivers to allocate WoL filters. # The HWRM shall not allow VF
22602 * drivers to allocate any WoL filters. # When partitioning is enabled and WoL
22603 * is supported, the HWRM shall support at least one WoL filter per partition. #
22604 * The HWRM shall retain a WoL filter setting until the filter is freed. # If
22605 * the HWRM client is a function driver, then the HWRM shall not allow the HWRM
22606 * client to set up WoL filters on the port that the function is not associated
22607 * with. # If the HWRM client is one of the trusted embedded services (e.g.
22608 * management service), the the HWRM shall allow the HWRM client to set up WoL
22609 * filters on any port of the device.
22611 /* Input (64 bytes) */
22613 struct hwrm_wol_filter_alloc_input {
22616 * This value indicates what type of request this is. The format for the
22617 * rest of the command is determined by this field.
22619 uint16_t cmpl_ring;
22621 * This value indicates the what completion ring the request will be
22622 * optionally completed on. If the value is -1, then no CR completion
22623 * will be generated. Any other value must be a valid CR ring_id value
22624 * for this function.
22627 /* This value indicates the command sequence number. */
22628 uint16_t target_id;
22630 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
22631 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
22633 uint64_t resp_addr;
22635 * This is the host address where the response will be written when the
22636 * request is complete. This area must be 16B aligned and must be
22637 * cleared to zero before the request is made.
22641 /* This bit must be '1' for the mac_address field to be configured. */
22642 #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_MAC_ADDRESS UINT32_C(0x1)
22643 /* This bit must be '1' for the pattern_offset field to be configured. */
22644 #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_OFFSET UINT32_C(0x2)
22645 /* This bit must be '1' for the pattern_buf_size field to be configured. */
22646 #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_BUF_SIZE UINT32_C(0x4)
22647 /* This bit must be '1' for the pattern_buf_addr field to be configured. */
22648 #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_BUF_ADDR UINT32_C(0x8)
22650 * This bit must be '1' for the pattern_mask_addr field to be
22653 #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_MASK_ADDR UINT32_C(0x10)
22655 * This bit must be '1' for the pattern_mask_size field to be
22658 #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_MASK_SIZE UINT32_C(0x20)
22660 /* Port ID of port on which WoL filter is configured. */
22662 /* This value represents a Wake-on-LAN type. */
22664 #define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_MAGICPKT UINT32_C(0x0)
22666 #define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_BMP UINT32_C(0x1)
22668 #define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_INVALID UINT32_C(0xff)
22671 uint8_t mac_address[6];
22673 * # If this field is enabled and magic packet WoL filter type is
22674 * specified in this command, the value set in this field shall be used
22675 * in setting the magic packet based WoL filter. # If this field is not
22676 * enabled and magic packet WoL filter type is specified and port id is
22677 * specified to 0xFF in this command, then the HWRM shall use default
22678 * MAC address configured on the function associated with the HWRM
22679 * client. # If this field is not enabled and magic packet WoL filter
22680 * type is specified and port id is not specified to 0xFF in this
22681 * command, then the HWRM shall use default MAC address configured on
22684 uint16_t pattern_offset;
22686 * The offset from the beginning of MAC header where pattern should be
22687 * matched. Applies to bitmap WoL.
22689 uint16_t pattern_buf_size;
22690 /* The size of the pattern that is being matched. Applies to bitmap WoL. */
22691 uint16_t pattern_mask_size;
22692 /* The size of the pattern mask. Applies to bitmap WoL. */
22694 uint64_t pattern_buf_addr;
22695 /* Physical address of the pattern buffer. Applies to bitmap WoL. */
22696 uint64_t pattern_mask_addr;
22697 /* Physical address of the pattern mask. Applies to bitmap WoL. */
22698 } __attribute__((packed));
22700 /* Output (16 bytes) */
22702 struct hwrm_wol_filter_alloc_output {
22703 uint16_t error_code;
22705 * Pass/Fail or error type Note: receiver to verify the in parameters,
22706 * and fail the call with an error when appropriate
22709 /* This field returns the type of original request. */
22711 /* This field provides original sequence number of the command. */
22714 * This field is the length of the response in bytes. The last byte of
22715 * the response is a valid flag that will read as '1' when the command
22716 * has been completely written to memory.
22718 uint8_t wol_filter_id;
22719 /* This value identifies a Wake-on-LAN (WoL) filter. */
22727 * This field is used in Output records to indicate that the output is
22728 * completely written to RAM. This field should be read as '1' to
22729 * indicate that the output has been completely written. When writing a
22730 * command completion or response to an internal processor, the order of
22731 * writes has to be such that this field is written last.
22733 } __attribute__((packed));
22735 /* hwrm_wol_filter_free */
22737 * Description: Free a WoL filter. # Among all function drivers, the HWRM shall
22738 * only allow PF drivers to free WoL filters. # The HWRM shall not allow VF
22739 * drivers to free any WoL filters. # The HWRM shall not allow a function driver
22740 * to free an Out-Of-Box WoL filter. # The HWRM shall not allow a function
22741 * driver to free a WoL filter on a port that the corresponding function is not
22742 * associated with. # The HWRM shall not allow a function driver to free a WoL
22743 * filter on a function that the function driver is not associated with.
22745 /* Input (32 bytes) */
22747 struct hwrm_wol_filter_free_input {
22750 * This value indicates what type of request this is. The format for the
22751 * rest of the command is determined by this field.
22753 uint16_t cmpl_ring;
22755 * This value indicates the what completion ring the request will be
22756 * optionally completed on. If the value is -1, then no CR completion
22757 * will be generated. Any other value must be a valid CR ring_id value
22758 * for this function.
22761 /* This value indicates the command sequence number. */
22762 uint16_t target_id;
22764 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
22765 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
22767 uint64_t resp_addr;
22769 * This is the host address where the response will be written when the
22770 * request is complete. This area must be 16B aligned and must be
22771 * cleared to zero before the request is made.
22775 * # When this bit is set to '1', then all active WoL filters on the
22776 * port are requested to be freed. # If the a function driver sets this
22777 * flag to '1', then the HWRM shall free all active WoL filters that are
22778 * not set by other function drivers on that port.
22780 #define HWRM_WOL_FILTER_FREE_INPUT_FLAGS_FREE_ALL_WOL_FILTERS UINT32_C(0x1)
22782 /* This bit must be '1' for the wol_filter_id field to be configured. */
22783 #define HWRM_WOL_FILTER_FREE_INPUT_ENABLES_WOL_FILTER_ID UINT32_C(0x1)
22785 /* Port ID of the port on which WoL filter(s) is (are) being freed. */
22786 uint8_t wol_filter_id;
22787 /* The HWRM shall ignore this field if free_all_wol_filters flag is set. */
22788 uint8_t unused_0[5];
22789 } __attribute__((packed));
22791 /* Output (16 bytes) */
22793 struct hwrm_wol_filter_free_output {
22794 uint16_t error_code;
22796 * Pass/Fail or error type Note: receiver to verify the in parameters,
22797 * and fail the call with an error when appropriate
22800 /* This field returns the type of original request. */
22802 /* This field provides original sequence number of the command. */
22805 * This field is the length of the response in bytes. The last byte of
22806 * the response is a valid flag that will read as '1' when the command
22807 * has been completely written to memory.
22815 * This field is used in Output records to indicate that the output is
22816 * completely written to RAM. This field should be read as '1' to
22817 * indicate that the output has been completely written. When writing a
22818 * command completion or response to an internal processor, the order of
22819 * writes has to be such that this field is written last.
22821 } __attribute__((packed));
22823 /* hwrm_wol_filter_qcfg */
22825 * Description: Query WoL filter configuration. # Among all function drivers,
22826 * the HWRM shall only allow PF drivers to query WoL filters. # The HWRM shall
22827 * not allow VF drivers to query any WoL filters. # The HWRM shall return WoL
22828 * filters that are active on the associated port for which this query is being
22829 * performed. # If the HWRM client is a function driver, then the HWRM shall not
22830 * allow the HWRM client to query WoL filters that are set up by other function
22831 * drivers. # If the HWRM client is a function driver, then the HWRM shall not
22832 * allow the HWRM client to query WoL filters on the port that the function is
22833 * not associated with. # If the HWRM client is one of the trusted embedded
22834 * service (e.g. management service), the the HWRM shall allow the HWRM client
22835 * to query WoL filters on any port of the device.
22837 /* Input (56 bytes) */
22839 struct hwrm_wol_filter_qcfg_input {
22842 * This value indicates what type of request this is. The format for the
22843 * rest of the command is determined by this field.
22845 uint16_t cmpl_ring;
22847 * This value indicates the what completion ring the request will be
22848 * optionally completed on. If the value is -1, then no CR completion
22849 * will be generated. Any other value must be a valid CR ring_id value
22850 * for this function.
22853 /* This value indicates the command sequence number. */
22854 uint16_t target_id;
22856 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
22857 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
22859 uint64_t resp_addr;
22861 * This is the host address where the response will be written when the
22862 * request is complete. This area must be 16B aligned and must be
22863 * cleared to zero before the request is made.
22866 /* Port ID of port on which WoL filter that is being queried. */
22869 * This is an opaque handle used to access filters. # The HWRM client
22870 * shall set this field to 0x0000 to begin the query. # After the first
22871 * query, the HWRM client shall retrieve next filters (if they exist)
22872 * using the HWRM provided handle in the response.
22875 uint64_t pattern_buf_addr;
22877 * Physical address of the pattern buffer. Applies to bitmap WoL filter
22878 * only. # Value of 0 indicates an invalid buffer address. If this field
22879 * is set to 0, then HWRM shall ignore pattern_buf_size. # If the HWRM
22880 * client provides an invalid buffer address for the pattern, then the
22881 * HWRM is not required to provide pattern when the response contains a
22882 * bitmap WoL filter.
22884 uint16_t pattern_buf_size;
22885 /* The size of the pattern buffer. Applies to bitmap WoL filter only. */
22888 uint8_t unused_3[3];
22890 uint64_t pattern_mask_addr;
22892 * Physical address of the pattern mask. Applies to bitmap WoL filter
22893 * only. # Value of 0 indicates an invalid pattern mask address. If this
22894 * field is set to 0, then HWRM shall ignore pattern_mask_size. # If the
22895 * HWRM client provides an invalid mask address for the pattern, then
22896 * the HWRM is not required to provide mask when the response contains a
22897 * bitmap WoL filter.
22899 uint16_t pattern_mask_size;
22901 * The size of the buffer for pattern mask. Applies to bitmap WoL filter
22904 uint16_t unused_5[3];
22905 } __attribute__((packed));
22907 /* Output (32 bytes) */
22909 struct hwrm_wol_filter_qcfg_output {
22910 uint16_t error_code;
22912 * Pass/Fail or error type Note: receiver to verify the in parameters,
22913 * and fail the call with an error when appropriate
22916 /* This field returns the type of original request. */
22918 /* This field provides original sequence number of the command. */
22921 * This field is the length of the response in bytes. The last byte of
22922 * the response is a valid flag that will read as '1' when the command
22923 * has been completely written to memory.
22925 uint16_t next_handle;
22927 * This is the next handle that is used to access filters. # If this
22928 * field is set to 0x0000, then no WoL filters are currently configured
22929 * on this port and all other fields in the output shall be ignored by
22930 * the HWRM client. # If this field is set to neither 0x0000 nor 0xFFFF,
22931 * then the wol_filter_id is valid and the parameters provided in the
22932 * response are based on the wol_type. # If this field is set to 0xFFFF,
22933 * then there are no remaining configured WoL filters to be queried for
22934 * the queried function after this response, wol_filter_id is valid and
22935 * the parameters provided in the response are based on the wol_type.
22937 uint8_t wol_filter_id;
22938 /* This value identifies the filter returned in this response. */
22941 * This value identifies the type of WoL filter returned in this
22945 #define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_MAGICPKT UINT32_C(0x0)
22947 #define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_BMP UINT32_C(0x1)
22949 #define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_INVALID UINT32_C(0xff)
22951 uint8_t mac_address[6];
22953 * The MAC address value used by the WoL filter. Applies to magic packet
22956 uint16_t pattern_offset;
22958 * The offset from the beginning of MAC header where pattern should be
22959 * matched. Applies to bitmap WoL.
22961 uint16_t pattern_size;
22963 * The actual size of the pattern that is being returned. Applies to
22966 uint16_t pattern_mask_size;
22968 * The actual size of the pattern mask that is being returned. Applies
22976 * This field is used in Output records to indicate that the output is
22977 * completely written to RAM. This field should be read as '1' to
22978 * indicate that the output has been completely written. When writing a
22979 * command completion or response to an internal processor, the order of
22980 * writes has to be such that this field is written last.
22982 } __attribute__((packed));
22984 /* hwrm_wol_reason_qcfg */
22985 /* Description: Query WoL reason for the last system wake up. */
22986 /* Input (40 bytes) */
22988 struct hwrm_wol_reason_qcfg_input {
22991 * This value indicates what type of request this is. The format for the
22992 * rest of the command is determined by this field.
22994 uint16_t cmpl_ring;
22996 * This value indicates the what completion ring the request will be
22997 * optionally completed on. If the value is -1, then no CR completion
22998 * will be generated. Any other value must be a valid CR ring_id value
22999 * for this function.
23002 /* This value indicates the command sequence number. */
23003 uint16_t target_id;
23005 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
23006 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
23008 uint64_t resp_addr;
23010 * This is the host address where the response will be written when the
23011 * request is complete. This area must be 16B aligned and must be
23012 * cleared to zero before the request is made.
23015 /* Port ID of port for which this query is for. */
23018 uint8_t unused_2[3];
23020 uint64_t wol_pkt_buf_addr;
23021 /* Physical address of the packet buffer for querying WoL packet. */
23022 uint16_t wol_pkt_buf_size;
23023 /* The size of the buffer for the WoL packet. */
23024 uint16_t unused_4[3];
23025 } __attribute__((packed));
23027 /* Output (16 bytes) */
23029 struct hwrm_wol_reason_qcfg_output {
23030 uint16_t error_code;
23032 * Pass/Fail or error type Note: receiver to verify the in parameters,
23033 * and fail the call with an error when appropriate
23036 /* This field returns the type of original request. */
23038 /* This field provides original sequence number of the command. */
23041 * This field is the length of the response in bytes. The last byte of
23042 * the response is a valid flag that will read as '1' when the command
23043 * has been completely written to memory.
23045 uint8_t wol_filter_id;
23047 * This value identifies the filter that matched the last WoL packet.
23048 * This id is only valid with valid WoL reason.
23050 uint8_t wol_reason;
23052 * This value identifies the type of WoL reason returned in this
23053 * response. When the wol_type is set to invalid, then there is no WoL
23054 * event that happened during last system wake-up.
23057 #define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_MAGICPKT UINT32_C(0x0)
23059 #define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_BMP UINT32_C(0x1)
23061 #define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_INVALID UINT32_C(0xff)
23062 uint8_t wol_pkt_len;
23063 /* The value identifies the length of the WoL packet in bytes. */
23070 * This field is used in Output records to indicate that the output is
23071 * completely written to RAM. This field should be read as '1' to
23072 * indicate that the output has been completely written. When writing a
23073 * command completion or response to an internal processor, the order of
23074 * writes has to be such that this field is written last.
23076 } __attribute__((packed));
23078 /* hwrm_dbg_dump */
23080 * Description: This command is used by to initiate the dump of debug
23081 * information to a driver specified address.
23083 /* Input (40 bytes) */
23085 struct hwrm_dbg_dump_input {
23088 * This value indicates what type of request this is. The format for the
23089 * rest of the command is determined by this field.
23091 uint16_t cmpl_ring;
23093 * This value indicates the what completion ring the request will be
23094 * optionally completed on. If the value is -1, then no CR completion
23095 * will be generated. Any other value must be a valid CR ring_id value
23096 * for this function.
23099 /* This value indicates the command sequence number. */
23100 uint16_t target_id;
23102 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
23103 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
23105 uint64_t resp_addr;
23107 * This is the host address where the response will be written when the
23108 * request is complete. This area must be 16B aligned and must be
23109 * cleared to zero before the request is made.
23113 * Handle used to dump debug data. handle = 0 indicates the beginning of
23114 * the dump. handle != 0 indicates the request to dump the next part.
23117 uint64_t host_dbg_dump_addr;
23119 * Address of the host buffer where the debug data is requested to be
23122 uint64_t host_dbg_dump_addr_len;
23123 /* Length of host buffer used for transferring debug data. */
23124 } __attribute__((packed));
23126 /* Output (24 bytes) */
23128 struct hwrm_dbg_dump_output {
23129 uint16_t error_code;
23131 * Pass/Fail or error type Note: receiver to verify the in parameters,
23132 * and fail the call with an error when appropriate
23135 /* This field returns the type of original request. */
23137 /* This field provides original sequence number of the command. */
23140 * This field is the length of the response in bytes. The last byte of
23141 * the response is a valid flag that will read as '1' when the command
23142 * has been completely written to memory.
23144 uint32_t nexthandle;
23146 * Handle used to indicate availability of additional debug data.
23147 * nexthandle = 0 indicates that there is no more debug data available.
23148 * nexthandle != 0 indicates the handle value that should be used to
23149 * request the next part of debug data.
23151 uint32_t dbg_data_len;
23152 /* The number of bytes of debug data written to debug dump buffer. */
23159 * This field is used in Output records to indicate that the output is
23160 * completely written to RAM. This field should be read as '1' to
23161 * indicate that the output has been completely written. When writing a
23162 * command completion or response to an internal processor, the order of
23163 * writes has to be such that this field is written last.
23165 } __attribute__((packed));
23167 /* hwrm_nvm_raw_write_blk */
23169 * Note: Write an unmanaged block of data at any physical offset within the
23170 * NVRAM. Used for initial provisioning/manufacturing purposes only. Implemented
23171 * in the ChiMP boot-strap firmware (fwutil.bin) only.
23173 /* Input (32 bytes) */
23175 struct hwrm_nvm_raw_write_blk_input {
23178 * This value indicates what type of request this is. The format for the
23179 * rest of the command is determined by this field.
23181 uint16_t cmpl_ring;
23183 * This value indicates the what completion ring the request will be
23184 * optionally completed on. If the value is -1, then no CR completion
23185 * will be generated. Any other value must be a valid CR ring_id value
23186 * for this function.
23189 /* This value indicates the command sequence number. */
23190 uint16_t target_id;
23192 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
23193 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
23195 uint64_t resp_addr;
23197 * This is the host address where the response will be written when the
23198 * request is complete. This area must be 16B aligned and must be
23199 * cleared to zero before the request is made.
23201 uint64_t host_src_addr;
23203 * 64-bit Host Source Address. This is the loation of the source data to
23206 uint32_t dest_addr;
23208 * 32-bit Destination Address. This is the NVRAM byte-offset where the
23209 * source data will be written to.
23212 /* Length of data to be written, in bytes. */
23213 } __attribute__((packed));
23215 /* Output (16 bytes) */
23217 struct hwrm_nvm_raw_write_blk_output {
23218 uint16_t error_code;
23220 * Pass/Fail or error type Note: receiver to verify the in parameters,
23221 * and fail the call with an error when appropriate
23224 /* This field returns the type of original request. */
23226 /* This field provides original sequence number of the command. */
23229 * This field is the length of the response in bytes. The last byte of
23230 * the response is a valid flag that will read as '1' when the command
23231 * has been completely written to memory.
23239 * This field is used in Output records to indicate that the output is
23240 * completely written to RAM. This field should be read as '1' to
23241 * indicate that the output has been completely written. When writing a
23242 * command completion or response to an internal processor, the order of
23243 * writes has to be such that this field is written last.
23245 } __attribute__((packed));
23247 /* hwrm_nvm_read */
23249 * Note: Read the contents of an NVRAM item as referenced (indexed) by an
23250 * existing directory entry.
23252 /* Input (40 bytes) */
23254 struct hwrm_nvm_read_input {
23257 * This value indicates what type of request this is. The format for the
23258 * rest of the command is determined by this field.
23260 uint16_t cmpl_ring;
23262 * This value indicates the what completion ring the request will be
23263 * optionally completed on. If the value is -1, then no CR completion
23264 * will be generated. Any other value must be a valid CR ring_id value
23265 * for this function.
23268 /* This value indicates the command sequence number. */
23269 uint16_t target_id;
23271 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
23272 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
23274 uint64_t resp_addr;
23276 * This is the host address where the response will be written when the
23277 * request is complete. This area must be 16B aligned and must be
23278 * cleared to zero before the request is made.
23280 uint64_t host_dest_addr;
23282 * 64-bit Host Destination Address. This is the host address where the
23283 * data will be written to.
23286 /* The 0-based index of the directory entry. */
23290 /* The NVRAM byte-offset to read from. */
23292 /* The length of the data to be read, in bytes. */
23294 } __attribute__((packed));
23296 /* Output (16 bytes) */
23298 struct hwrm_nvm_read_output {
23299 uint16_t error_code;
23301 * Pass/Fail or error type Note: receiver to verify the in parameters,
23302 * and fail the call with an error when appropriate
23305 /* This field returns the type of original request. */
23307 /* This field provides original sequence number of the command. */
23310 * This field is the length of the response in bytes. The last byte of
23311 * the response is a valid flag that will read as '1' when the command
23312 * has been completely written to memory.
23320 * This field is used in Output records to indicate that the output is
23321 * completely written to RAM. This field should be read as '1' to
23322 * indicate that the output has been completely written. When writing a
23323 * command completion or response to an internal processor, the order of
23324 * writes has to be such that this field is written last.
23326 } __attribute__((packed));
23328 /* hwrm_nvm_raw_dump */
23329 /* Note: Dump a raw block of data from NVRAM. */
23330 /* Input (32 bytes) */
23332 struct hwrm_nvm_raw_dump_input {
23335 * This value indicates what type of request this is. The format for the
23336 * rest of the command is determined by this field.
23338 uint16_t cmpl_ring;
23340 * This value indicates the what completion ring the request will be
23341 * optionally completed on. If the value is -1, then no CR completion
23342 * will be generated. Any other value must be a valid CR ring_id value
23343 * for this function.
23346 /* This value indicates the command sequence number. */
23347 uint16_t target_id;
23349 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
23350 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
23352 uint64_t resp_addr;
23354 * This is the host address where the response will be written when the
23355 * request is complete. This area must be 16B aligned and must be
23356 * cleared to zero before the request is made.
23358 uint64_t host_dest_addr;
23360 * 64-bit Host Destination Address. This is the host address where the
23361 * data will be written to.
23364 /* 32-bit NVRAM byte-offset to read from. */
23366 /* Total length of NVRAM contents to be read, in bytes. */
23367 } __attribute__((packed));
23369 /* Output (16 bytes) */
23371 struct hwrm_nvm_raw_dump_output {
23372 uint16_t error_code;
23374 * Pass/Fail or error type Note: receiver to verify the in parameters,
23375 * and fail the call with an error when appropriate
23378 /* This field returns the type of original request. */
23380 /* This field provides original sequence number of the command. */
23383 * This field is the length of the response in bytes. The last byte of
23384 * the response is a valid flag that will read as '1' when the command
23385 * has been completely written to memory.
23393 * This field is used in Output records to indicate that the output is
23394 * completely written to RAM. This field should be read as '1' to
23395 * indicate that the output has been completely written. When writing a
23396 * command completion or response to an internal processor, the order of
23397 * writes has to be such that this field is written last.
23399 } __attribute__((packed));
23401 /* hwrm_nvm_get_dir_entries */
23403 * Description: Read the NVRAM directory. Each directory entry is at least 24
23404 * bytes in length and contains the: - 16-bit directory entry type
23405 * (BNX_DIR_TYPE_* value) - 16-bit ordinal (instance of this directory entry
23406 * type) - 16-bit extension flags (identifies inactive entries and entries for
23407 * firmware update) - 16-bit attribute flags (identifies entries with a
23408 * purposely invalid chksum value) - 32-bit byte-offset into NVRAM where this
23409 * item data is located - 32-bit length of allocated NVRAM for item, in bytes
23410 * (multiple of block size) - 32-bit length of data (excluding padding), in
23411 * bytes (may be 0) - 32-bit data checksum (CRC-32) See the
23412 * bnxnvm_directory_entry_t definition in the file bnxnvm_defs.h.
23414 /* Input (24 bytes) */
23416 struct hwrm_nvm_get_dir_entries_input {
23419 * This value indicates what type of request this is. The format for the
23420 * rest of the command is determined by this field.
23422 uint16_t cmpl_ring;
23424 * This value indicates the what completion ring the request will be
23425 * optionally completed on. If the value is -1, then no CR completion
23426 * will be generated. Any other value must be a valid CR ring_id value
23427 * for this function.
23430 /* This value indicates the command sequence number. */
23431 uint16_t target_id;
23433 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
23434 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
23436 uint64_t resp_addr;
23438 * This is the host address where the response will be written when the
23439 * request is complete. This area must be 16B aligned and must be
23440 * cleared to zero before the request is made.
23442 uint64_t host_dest_addr;
23444 * 64-bit Host Destination Address. This is the host address where the
23445 * directory will be written.
23447 } __attribute__((packed));
23449 /* Output (16 bytes) */
23451 struct hwrm_nvm_get_dir_entries_output {
23452 uint16_t error_code;
23454 * Pass/Fail or error type Note: receiver to verify the in parameters,
23455 * and fail the call with an error when appropriate
23458 /* This field returns the type of original request. */
23460 /* This field provides original sequence number of the command. */
23463 * This field is the length of the response in bytes. The last byte of
23464 * the response is a valid flag that will read as '1' when the command
23465 * has been completely written to memory.
23473 * This field is used in Output records to indicate that the output is
23474 * completely written to RAM. This field should be read as '1' to
23475 * indicate that the output has been completely written. When writing a
23476 * command completion or response to an internal processor, the order of
23477 * writes has to be such that this field is written last.
23479 } __attribute__((packed));
23481 /* hwrm_nvm_get_dir_info */
23482 /* Note: Get Directory Header info. */
23483 /* Input (16 bytes) */
23485 struct hwrm_nvm_get_dir_info_input {
23488 * This value indicates what type of request this is. The format for the
23489 * rest of the command is determined by this field.
23491 uint16_t cmpl_ring;
23493 * This value indicates the what completion ring the request will be
23494 * optionally completed on. If the value is -1, then no CR completion
23495 * will be generated. Any other value must be a valid CR ring_id value
23496 * for this function.
23499 /* This value indicates the command sequence number. */
23500 uint16_t target_id;
23502 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
23503 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
23505 uint64_t resp_addr;
23507 * This is the host address where the response will be written when the
23508 * request is complete. This area must be 16B aligned and must be
23509 * cleared to zero before the request is made.
23511 } __attribute__((packed));
23513 /* Output (24 bytes) */
23515 struct hwrm_nvm_get_dir_info_output {
23516 uint16_t error_code;
23518 * Pass/Fail or error type Note: receiver to verify the in parameters,
23519 * and fail the call with an error when appropriate
23522 /* This field returns the type of original request. */
23524 /* This field provides original sequence number of the command. */
23527 * This field is the length of the response in bytes. The last byte of
23528 * the response is a valid flag that will read as '1' when the command
23529 * has been completely written to memory.
23532 /* Number of directory entries in the directory. */
23533 uint32_t entry_length;
23534 /* Size of each directory entry, in bytes. */
23541 * This field is used in Output records to indicate that the output is
23542 * completely written to RAM. This field should be read as '1' to
23543 * indicate that the output has been completely written. When writing a
23544 * command completion or response to an internal processor, the order of
23545 * writes has to be such that this field is written last.
23547 } __attribute__((packed));
23549 /* hwrm_nvm_write */
23551 * Note: Write to the allocated NVRAM of an item referenced by an existing
23554 /* Input (48 bytes) */
23556 struct hwrm_nvm_write_input {
23559 * This value indicates what type of request this is. The format for the
23560 * rest of the command is determined by this field.
23562 uint16_t cmpl_ring;
23564 * This value indicates the what completion ring the request will be
23565 * optionally completed on. If the value is -1, then no CR completion
23566 * will be generated. Any other value must be a valid CR ring_id value
23567 * for this function.
23570 /* This value indicates the command sequence number. */
23571 uint16_t target_id;
23573 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
23574 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
23576 uint64_t resp_addr;
23578 * This is the host address where the response will be written when the
23579 * request is complete. This area must be 16B aligned and must be
23580 * cleared to zero before the request is made.
23582 uint64_t host_src_addr;
23583 /* 64-bit Host Source Address. This is where the source data is. */
23586 * The Directory Entry Type (valid values are defined in the
23587 * bnxnvm_directory_type enum defined in the file bnxnvm_defs.h).
23589 uint16_t dir_ordinal;
23591 * Directory ordinal. The 0-based instance of the combined Directory
23592 * Entry Type and Extension.
23596 * The Directory Entry Extension flags (see BNX_DIR_EXT_* in the file
23601 * Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file
23604 uint32_t dir_data_length;
23606 * Length of data to write, in bytes. May be less than or equal to the
23607 * allocated size for the directory entry. The data length stored in the
23608 * directory entry will be updated to reflect this value once the write
23615 * When this bit is '1', the original active image will not be removed.
23616 * TBD: what purpose is this?
23618 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG UINT32_C(0x1)
23619 uint32_t dir_item_length;
23621 * The requested length of the allocated NVM for the item, in bytes.
23622 * This value may be greater than or equal to the specified data length
23623 * (dir_data_length). If this value is less than the specified data
23624 * length, it will be ignored. The response will contain the actual
23625 * allocated item length, which may be greater than the requested item
23626 * length. The purpose for allocating more than the required number of
23627 * bytes for an item's data is to pre-allocate extra storage (padding)
23628 * to accomodate the potential future growth of an item (e.g. upgraded
23629 * firmware with a size increase, log growth, expanded configuration
23633 } __attribute__((packed));
23635 /* Output (16 bytes) */
23637 struct hwrm_nvm_write_output {
23638 uint16_t error_code;
23640 * Pass/Fail or error type Note: receiver to verify the in parameters,
23641 * and fail the call with an error when appropriate
23644 /* This field returns the type of original request. */
23646 /* This field provides original sequence number of the command. */
23649 * This field is the length of the response in bytes. The last byte of
23650 * the response is a valid flag that will read as '1' when the command
23651 * has been completely written to memory.
23653 uint32_t dir_item_length;
23655 * Length of the allocated NVM for the item, in bytes. The value may be
23656 * greater than or equal to the specified data length or the requested
23657 * item length. The actual item length used when creating a new
23658 * directory entry will be a multiple of an NVM block size.
23661 /* The directory index of the created or modified item. */
23665 * This field is used in Output records to indicate that the output is
23666 * completely written to RAM. This field should be read as '1' to
23667 * indicate that the output has been completely written. When writing a
23668 * command completion or response to an internal processor, the order of
23669 * writes has to be such that this field is written last.
23671 } __attribute__((packed));
23673 /* Command specific Error Codes (8 bytes) */
23675 struct hwrm_nvm_write_cmd_err {
23678 * command specific error codes that goes to the cmd_err field in Common
23679 * HWRM Error Response.
23681 /* Unknown error */
23682 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
23683 /* Unable to complete operation due to fragmentation */
23684 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
23685 /* nvm is completely full. */
23686 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
23687 uint8_t unused_0[7];
23688 } __attribute__((packed));
23690 /* hwrm_nvm_modify */
23692 * Note: Modify the contents of an NVRAM item as referenced (indexed) by an
23693 * existing directory entry.
23695 /* Input (40 bytes) */
23697 struct hwrm_nvm_modify_input {
23700 * This value indicates what type of request this is. The format for the
23701 * rest of the command is determined by this field.
23703 uint16_t cmpl_ring;
23705 * This value indicates the what completion ring the request will be
23706 * optionally completed on. If the value is -1, then no CR completion
23707 * will be generated. Any other value must be a valid CR ring_id value
23708 * for this function.
23711 /* This value indicates the command sequence number. */
23712 uint16_t target_id;
23714 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
23715 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
23717 uint64_t resp_addr;
23719 * This is the host address where the response will be written when the
23720 * request is complete. This area must be 16B aligned and must be
23721 * cleared to zero before the request is made.
23723 uint64_t host_src_addr;
23724 /* 64-bit Host Source Address. This is where the modified data is. */
23726 /* 16-bit directory entry index. */
23730 /* 32-bit NVRAM byte-offset to modify content from. */
23733 * Length of data to be modified, in bytes. The length shall be non-
23737 } __attribute__((packed));
23739 /* Output (16 bytes) */
23741 struct hwrm_nvm_modify_output {
23742 uint16_t error_code;
23744 * Pass/Fail or error type Note: receiver to verify the in parameters,
23745 * and fail the call with an error when appropriate
23748 /* This field returns the type of original request. */
23750 /* This field provides original sequence number of the command. */
23753 * This field is the length of the response in bytes. The last byte of
23754 * the response is a valid flag that will read as '1' when the command
23755 * has been completely written to memory.
23763 * This field is used in Output records to indicate that the output is
23764 * completely written to RAM. This field should be read as '1' to
23765 * indicate that the output has been completely written. When writing a
23766 * command completion or response to an internal processor, the order of
23767 * writes has to be such that this field is written last.
23769 } __attribute__((packed));
23771 /* hwrm_nvm_find_dir_entry */
23773 * Note: Search a directory entry in the directory by either directory entry
23774 * index or directory entry parameters.
23776 /* Input (32 bytes) */
23778 struct hwrm_nvm_find_dir_entry_input {
23781 * This value indicates what type of request this is. The format for the
23782 * rest of the command is determined by this field.
23784 uint16_t cmpl_ring;
23786 * This value indicates the what completion ring the request will be
23787 * optionally completed on. If the value is -1, then no CR completion
23788 * will be generated. Any other value must be a valid CR ring_id value
23789 * for this function.
23792 /* This value indicates the command sequence number. */
23793 uint16_t target_id;
23795 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
23796 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
23798 uint64_t resp_addr;
23800 * This is the host address where the response will be written when the
23801 * request is complete. This area must be 16B aligned and must be
23802 * cleared to zero before the request is made.
23805 /* This bit must be '1' for the dir_idx_valid field to be configured. */
23806 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID UINT32_C(0x1)
23808 /* Directory Entry Index */
23810 /* Directory Entry (Image) Type */
23811 uint16_t dir_ordinal;
23812 /* Directory ordinal. The instance of this Directory Type */
23814 /* The Directory Entry Extension flags. */
23815 uint8_t opt_ordinal;
23816 /* This value indicates the search option using dir_ordinal. */
23817 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
23818 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
23819 /* Equal to specified ordinal value. */
23820 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
23821 /* Greater than or equal to specified ordinal value */
23822 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
23823 /* Greater than specified ordinal value */
23824 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
23825 uint8_t unused_1[3];
23826 } __attribute__((packed));
23828 /* Output (32 bytes) */
23830 struct hwrm_nvm_find_dir_entry_output {
23831 uint16_t error_code;
23833 * Pass/Fail or error type Note: receiver to verify the in parameters,
23834 * and fail the call with an error when appropriate
23837 /* This field returns the type of original request. */
23839 /* This field provides original sequence number of the command. */
23842 * This field is the length of the response in bytes. The last byte of
23843 * the response is a valid flag that will read as '1' when the command
23844 * has been completely written to memory.
23846 uint32_t dir_item_length;
23847 /* Allocated NVRAM for this directory entry, in bytes. */
23848 uint32_t dir_data_length;
23849 /* Size of the stored data for this directory entry, in bytes. */
23852 * Firmware version. Only valid if the directory entry is for embedded
23853 * firmware stored in APE_BIN Format.
23855 uint16_t dir_ordinal;
23856 /* Directory ordinal. */
23858 /* Directory Entry Index */
23865 * This field is used in Output records to indicate that the output is
23866 * completely written to RAM. This field should be read as '1' to
23867 * indicate that the output has been completely written. When writing a
23868 * command completion or response to an internal processor, the order of
23869 * writes has to be such that this field is written last.
23871 } __attribute__((packed));
23873 /* hwrm_nvm_erase_dir_entry */
23875 * Note: Remove a directory entry specified by the directory entry index from
23878 /* Input (24 bytes) */
23880 struct hwrm_nvm_erase_dir_entry_input {
23883 * This value indicates what type of request this is. The format for the
23884 * rest of the command is determined by this field.
23886 uint16_t cmpl_ring;
23888 * This value indicates the what completion ring the request will be
23889 * optionally completed on. If the value is -1, then no CR completion
23890 * will be generated. Any other value must be a valid CR ring_id value
23891 * for this function.
23894 /* This value indicates the command sequence number. */
23895 uint16_t target_id;
23897 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
23898 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
23900 uint64_t resp_addr;
23902 * This is the host address where the response will be written when the
23903 * request is complete. This area must be 16B aligned and must be
23904 * cleared to zero before the request is made.
23907 /* Directory Entry Index */
23908 uint16_t unused_0[3];
23909 } __attribute__((packed));
23911 /* Output (16 bytes) */
23913 struct hwrm_nvm_erase_dir_entry_output {
23914 uint16_t error_code;
23916 * Pass/Fail or error type Note: receiver to verify the in parameters,
23917 * and fail the call with an error when appropriate
23920 /* This field returns the type of original request. */
23922 /* This field provides original sequence number of the command. */
23925 * This field is the length of the response in bytes. The last byte of
23926 * the response is a valid flag that will read as '1' when the command
23927 * has been completely written to memory.
23935 * This field is used in Output records to indicate that the output is
23936 * completely written to RAM. This field should be read as '1' to
23937 * indicate that the output has been completely written. When writing a
23938 * command completion or response to an internal processor, the order of
23939 * writes has to be such that this field is written last.
23941 } __attribute__((packed));
23943 /* hwrm_nvm_get_dev_info */
23945 * Note: Get device info. Return Manufacturer_ID, Device_ID, block_size,
23946 * nvram_size, reserved_size and available_size.
23948 /* Input (16 bytes) */
23950 struct hwrm_nvm_get_dev_info_input {
23953 * This value indicates what type of request this is. The format for the
23954 * rest of the command is determined by this field.
23956 uint16_t cmpl_ring;
23958 * This value indicates the what completion ring the request will be
23959 * optionally completed on. If the value is -1, then no CR completion
23960 * will be generated. Any other value must be a valid CR ring_id value
23961 * for this function.
23964 /* This value indicates the command sequence number. */
23965 uint16_t target_id;
23967 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
23968 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
23970 uint64_t resp_addr;
23972 * This is the host address where the response will be written when the
23973 * request is complete. This area must be 16B aligned and must be
23974 * cleared to zero before the request is made.
23976 } __attribute__((packed));
23978 /* Output (32 bytes) */
23980 struct hwrm_nvm_get_dev_info_output {
23981 uint16_t error_code;
23983 * Pass/Fail or error type Note: receiver to verify the in parameters,
23984 * and fail the call with an error when appropriate
23987 /* This field returns the type of original request. */
23989 /* This field provides original sequence number of the command. */
23992 * This field is the length of the response in bytes. The last byte of
23993 * the response is a valid flag that will read as '1' when the command
23994 * has been completely written to memory.
23996 uint16_t manufacturer_id;
23997 /* Manufacturer ID. */
23998 uint16_t device_id;
24000 uint32_t sector_size;
24001 /* Sector size of the NVRAM device. */
24002 uint32_t nvram_size;
24003 /* Total size, in bytes of the NVRAM device. */
24004 uint32_t reserved_size;
24005 uint32_t available_size;
24007 * Available size that can be used, in bytes. Available size is the
24008 * NVRAM size take away the used size and reserved size.
24015 * This field is used in Output records to indicate that the output is
24016 * completely written to RAM. This field should be read as '1' to
24017 * indicate that the output has been completely written. When writing a
24018 * command completion or response to an internal processor, the order of
24019 * writes has to be such that this field is written last.
24021 } __attribute__((packed));
24023 /* hwrm_nvm_mod_dir_entry */
24024 /* Note: Modify a directory entry parameters in the directory. */
24025 /* Input (32 bytes) */
24027 struct hwrm_nvm_mod_dir_entry_input {
24030 * This value indicates what type of request this is. The format for the
24031 * rest of the command is determined by this field.
24033 uint16_t cmpl_ring;
24035 * This value indicates the what completion ring the request will be
24036 * optionally completed on. If the value is -1, then no CR completion
24037 * will be generated. Any other value must be a valid CR ring_id value
24038 * for this function.
24041 /* This value indicates the command sequence number. */
24042 uint16_t target_id;
24044 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
24045 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
24047 uint64_t resp_addr;
24049 * This is the host address where the response will be written when the
24050 * request is complete. This area must be 16B aligned and must be
24051 * cleared to zero before the request is made.
24054 /* This bit must be '1' for the checksum field to be configured. */
24055 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
24057 /* Directory Entry Index */
24058 uint16_t dir_ordinal;
24059 /* Directory ordinal. The (0-based) instance of this Directory Type. */
24062 * The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension
24063 * flag definitions).
24067 * Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute
24068 * flag definitions).
24072 * If valid, then this field updates the checksum value of the content
24073 * in the directory entry.
24075 } __attribute__((packed));
24077 /* Output (16 bytes) */
24079 struct hwrm_nvm_mod_dir_entry_output {
24080 uint16_t error_code;
24082 * Pass/Fail or error type Note: receiver to verify the in parameters,
24083 * and fail the call with an error when appropriate
24086 /* This field returns the type of original request. */
24088 /* This field provides original sequence number of the command. */
24091 * This field is the length of the response in bytes. The last byte of
24092 * the response is a valid flag that will read as '1' when the command
24093 * has been completely written to memory.
24101 * This field is used in Output records to indicate that the output is
24102 * completely written to RAM. This field should be read as '1' to
24103 * indicate that the output has been completely written. When writing a
24104 * command completion or response to an internal processor, the order of
24105 * writes has to be such that this field is written last.
24107 } __attribute__((packed));
24109 /* hwrm_nvm_verify_update */
24111 * Description: Verify updated content of a directory entry. Before this
24112 * verification, there should be two valid directory entries of the given
24113 * directory type (one with "UPDATE" directory extension flag and the current
24114 * one "ACTIVE"). Below are steps the HWRM performs for executing this command:
24115 * # The HWRM finds the directory entry with "UDPATE" extension flag based on
24116 * input parameters. The new directory entry should already have updated
24117 * contents. # The HWRM performs signature verification of the updated content.
24118 * # If the signature verification is successful, the two directory entries are
24119 * switched (the verified updated entry is made active and the current "ACTIVE"
24120 * entry is marked with "UPDATE" extension flag). Implementation notes: # The
24121 * HWRM shall allow this command to be requested against any dir_type value (and
24122 * not limit it to a subset). # In the case of an updated HWRM firmware, the new
24123 * firmware version shall not automatically take effect (i.e. be executed).
24125 /* Input (24 bytes) */
24127 struct hwrm_nvm_verify_update_input {
24130 * This value indicates what type of request this is. The format for the
24131 * rest of the command is determined by this field.
24133 uint16_t cmpl_ring;
24135 * This value indicates the what completion ring the request will be
24136 * optionally completed on. If the value is -1, then no CR completion
24137 * will be generated. Any other value must be a valid CR ring_id value
24138 * for this function.
24141 /* This value indicates the command sequence number. */
24142 uint16_t target_id;
24144 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
24145 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
24147 uint64_t resp_addr;
24149 * This is the host address where the response will be written when the
24150 * request is complete. This area must be 16B aligned and must be
24151 * cleared to zero before the request is made.
24154 /* Directory Entry Type, to be verified. */
24155 uint16_t dir_ordinal;
24156 /* Directory ordinal. The instance of the Directory Type to be verified. */
24159 * The Directory Entry Extension flags. The "UPDATE" extension flag must
24160 * be set in this value. A corresponding directory entry with the same
24161 * type and ordinal values but *without* the "UPDATE" extension flag
24162 * must also exist. The other flags of the extension must be identical
24163 * between the active and update entries.
24166 } __attribute__((packed));
24168 /* Output (16 bytes) */
24170 struct hwrm_nvm_verify_update_output {
24171 uint16_t error_code;
24173 * Pass/Fail or error type Note: receiver to verify the in parameters,
24174 * and fail the call with an error when appropriate
24177 /* This field returns the type of original request. */
24179 /* This field provides original sequence number of the command. */
24182 * This field is the length of the response in bytes. The last byte of
24183 * the response is a valid flag that will read as '1' when the command
24184 * has been completely written to memory.
24192 * This field is used in Output records to indicate that the output is
24193 * completely written to RAM. This field should be read as '1' to
24194 * indicate that the output has been completely written. When writing a
24195 * command completion or response to an internal processor, the order of
24196 * writes has to be such that this field is written last.
24198 } __attribute__((packed));
24200 /* hwrm_nvm_install_update */
24202 * Description: Install a staged NVM package. A package file must first be
24203 * staged into the "UPDATE" NVM item. This staging is accomplished using the
24204 * nvm_write and/or nvm_modify HWRM commands.
24206 /* Input (24 bytes) */
24208 struct hwrm_nvm_install_update_input {
24211 * This value indicates what type of request this is. The format for the
24212 * rest of the command is determined by this field.
24214 uint16_t cmpl_ring;
24216 * This value indicates the what completion ring the request will be
24217 * optionally completed on. If the value is -1, then no CR completion
24218 * will be generated. Any other value must be a valid CR ring_id value
24219 * for this function.
24222 /* This value indicates the command sequence number. */
24223 uint16_t target_id;
24225 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
24226 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
24228 uint64_t resp_addr;
24230 * This is the host address where the response will be written when the
24231 * request is complete. This area must be 16B aligned and must be
24232 * cleared to zero before the request is made.
24234 uint32_t install_type;
24236 * Installation type. If the value 3 through 0xffff is used, only
24237 * packaged items with that type value will be installed and conditional
24238 * installation directives for those packaged items will be over-ridden
24239 * (i.e. 'create' or 'replace' will be treated as 'install').
24242 * Perform a normal package installation. Conditional
24243 * installation directives (e.g. 'create' and 'replace') of
24244 * packaged items will be followed.
24246 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
24248 * Install all packaged items regardless of installation
24249 * directive (i.e. treat all packaged items as though they have
24250 * an installation directive of 'install').
24252 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL UINT32_C(0xffffffff)
24255 * If set to 1, then securely erase all unused locations in persistent
24258 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE UINT32_C(0x1)
24260 * If set to 1, then unspecifed images, images not in the package file,
24261 * will be safely deleted. When combined with erase_unused_space then
24262 * unspecified images will be securely erased.
24264 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG UINT32_C(0x2)
24266 * If set to 1, FW will defragment the NVM if defragmentation is
24267 * required for the update. Allow additional time for this command to
24268 * complete if this bit is set to 1.
24270 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG UINT32_C(0x4)
24272 } __attribute__((packed));
24274 /* Output (24 bytes) */
24276 struct hwrm_nvm_install_update_output {
24277 uint16_t error_code;
24279 * Pass/Fail or error type Note: receiver to verify the in parameters,
24280 * and fail the call with an error when appropriate
24283 /* This field returns the type of original request. */
24285 /* This field provides original sequence number of the command. */
24288 * This field is the length of the response in bytes. The last byte of
24289 * the response is a valid flag that will read as '1' when the command
24290 * has been completely written to memory.
24292 uint64_t installed_items;
24294 * Bit-mask of successfully installed items. Bit-0 corresponding to the
24295 * first packaged item, Bit-1 for the second item, etc. A value of 0
24296 * indicates that no items were successfully installed.
24299 /* result is 8 b */
24300 /* There was no problem with the package installation. */
24301 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
24302 uint8_t problem_item;
24303 /* problem_item is 8 b */
24304 /* There was no problem with any packaged items. */
24305 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE UINT32_C(0x0)
24306 /* There was a problem with the NVM package itself. */
24307 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE UINT32_C(0xff)
24308 uint8_t reset_required;
24309 /* reset_required is 8 b */
24311 * No reset is required for installed/updated firmware or
24312 * microcode to take effect.
24314 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE UINT32_C(0x0)
24316 * A PCIe reset (e.g. system reboot) is required for newly
24317 * installed/updated firmware or microcode to take effect.
24319 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI UINT32_C(0x1)
24321 * A controller power reset (e.g. system power-cycle) is
24322 * required for newly installed/updated firmware or microcode to
24323 * take effect. Some newly installed/updated firmware or
24324 * microcode may still take effect upon the next PCIe reset.
24326 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER UINT32_C(0x2)
24333 * This field is used in Output records to indicate that the output is
24334 * completely written to RAM. This field should be read as '1' to
24335 * indicate that the output has been completely written. When writing a
24336 * command completion or response to an internal processor, the order of
24337 * writes has to be such that this field is written last.
24339 } __attribute__((packed));
24341 /* Command specific Error Codes (8 bytes) */
24343 struct hwrm_nvm_install_update_cmd_err {
24346 * command specific error codes that goes to the cmd_err field in Common
24347 * HWRM Error Response.
24349 /* Unknown error */
24350 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
24351 /* Unable to complete operation due to fragmentation */
24352 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
24353 /* nvm is completely full. */
24354 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
24355 uint8_t unused_0[7];
24356 } __attribute__((packed));
24358 /* hwrm_nvm_flush */
24359 /* Input (16 bytes) */
24361 struct hwrm_nvm_flush_input {
24364 * This value indicates what type of request this is. The format for the
24365 * rest of the command is determined by this field.
24367 uint16_t cmpl_ring;
24369 * This value indicates the what completion ring the request will be
24370 * optionally completed on. If the value is -1, then no CR completion
24371 * will be generated. Any other value must be a valid CR ring_id value
24372 * for this function.
24375 /* This value indicates the command sequence number. */
24376 uint16_t target_id;
24378 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
24379 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
24381 uint64_t resp_addr;
24383 * This is the host address where the response will be written when the
24384 * request is complete. This area must be 16B aligned and must be
24385 * cleared to zero before the request is made.
24387 } __attribute__((packed));
24389 /* Output (16 bytes) */
24391 struct hwrm_nvm_flush_output {
24392 uint16_t error_code;
24394 * Pass/Fail or error type Note: receiver to verify the in parameters,
24395 * and fail the call with an error when appropriate
24398 /* This field returns the type of original request. */
24400 /* This field provides original sequence number of the command. */
24403 * This field is the length of the response in bytes. The last byte of
24404 * the response is a valid flag that will read as '1' when the command
24405 * has been completely written to memory.
24413 * This field is used in Output records to indicate that the output is
24414 * completely written to RAM. This field should be read as '1' to
24415 * indicate that the output has been completely written. When writing a
24416 * command completion or response to an internal processor, the order of
24417 * writes has to be such that this field is written last.
24419 } __attribute__((packed));
24421 /* Command specific Error Codes (8 bytes) */
24423 struct hwrm_nvm_flush_cmd_err {
24426 * command specific error codes that goes to the cmd_err field in Common
24427 * HWRM Error Response.
24429 /* Unknown error */
24430 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
24431 /* flush could not be performed */
24432 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
24433 uint8_t unused_0[7];
24434 } __attribute__((packed));
24436 /* hwrm_nvm_get_variable */
24437 /* Input (40 bytes) */
24439 struct hwrm_nvm_get_variable_input {
24442 * This value indicates what type of request this is. The format for the
24443 * rest of the command is determined by this field.
24445 uint16_t cmpl_ring;
24447 * This value indicates the what completion ring the request will be
24448 * optionally completed on. If the value is -1, then no CR completion
24449 * will be generated. Any other value must be a valid CR ring_id value
24450 * for this function.
24453 /* This value indicates the command sequence number. */
24454 uint16_t target_id;
24456 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
24457 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
24459 uint64_t resp_addr;
24461 * This is the host address where the response will be written when the
24462 * request is complete. This area must be 16B aligned and must be
24463 * cleared to zero before the request is made.
24465 uint64_t dest_data_addr;
24466 /* This is the host address where nvm variable will be stored */
24468 /* size of data in bits */
24469 uint16_t option_num;
24470 /* nvm cfg option number */
24472 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
24474 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff)
24475 uint16_t dimensions;
24477 * Number of dimensions for this nvm configuration variable. This value
24478 * indicates how many of the indexN values to use. A value of 0 means
24479 * that none of the indexN values are valid. A value of 1 requires at
24480 * index0 is valued, a value of 2 requires that index0 and index1 are
24481 * valid, and so forth
24484 /* index for the 1st dimensions */
24486 /* index for the 2nd dimensions */
24488 /* index for the 3rd dimensions */
24490 /* index for the 4th dimensions */
24493 * When this bit is set to 1, the factory default value will be
24494 * returned, 0 returns the operational value.
24496 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT UINT32_C(0x1)
24498 } __attribute__((packed));
24500 /* Output (16 bytes) */
24502 struct hwrm_nvm_get_variable_output {
24503 uint16_t error_code;
24505 * Pass/Fail or error type Note: receiver to verify the in parameters,
24506 * and fail the call with an error when appropriate
24509 /* This field returns the type of original request. */
24511 /* This field provides original sequence number of the command. */
24514 * This field is the length of the response in bytes. The last byte of
24515 * the response is a valid flag that will read as '1' when the command
24516 * has been completely written to memory.
24519 /* size of data of the actual variable retrieved in bits */
24520 uint16_t option_num;
24522 * option_num is the option number for the data retrieved. It is
24523 * possible in the future that the option number returned would be
24524 * different than requested. This condition could occur if an option is
24525 * deprecated and a new option id is defined with similar
24526 * characteristics, but has a slightly different definition. This also
24527 * makes it convenient for the caller to identify the variable result
24528 * with the option id from the response.
24531 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
24533 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff)
24539 * This field is used in Output records to indicate that the output is
24540 * completely written to RAM. This field should be read as '1' to
24541 * indicate that the output has been completely written. When writing a
24542 * command completion or response to an internal processor, the order of
24543 * writes has to be such that this field is written last.
24545 } __attribute__((packed));
24547 /* Command specific Error Codes (8 bytes) */
24549 struct hwrm_nvm_get_variable_cmd_err {
24552 * command specific error codes that goes to the cmd_err field in Common
24553 * HWRM Error Response.
24555 /* Unknown error */
24556 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
24557 /* variable does not exist */
24558 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
24559 /* configuration is corrupted and the variable cannot be saved */
24560 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
24561 /* length specified is too small */
24562 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
24563 uint8_t unused_0[7];
24564 } __attribute__((packed));
24566 /* hwrm_nvm_set_variable */
24567 /* Input (40 bytes) */
24569 struct hwrm_nvm_set_variable_input {
24572 * This value indicates what type of request this is. The format for the
24573 * rest of the command is determined by this field.
24575 uint16_t cmpl_ring;
24577 * This value indicates the what completion ring the request will be
24578 * optionally completed on. If the value is -1, then no CR completion
24579 * will be generated. Any other value must be a valid CR ring_id value
24580 * for this function.
24583 /* This value indicates the command sequence number. */
24584 uint16_t target_id;
24586 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
24587 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
24589 uint64_t resp_addr;
24591 * This is the host address where the response will be written when the
24592 * request is complete. This area must be 16B aligned and must be
24593 * cleared to zero before the request is made.
24595 uint64_t src_data_addr;
24596 /* This is the host address where nvm variable will be copied from */
24598 /* size of data in bits */
24599 uint16_t option_num;
24600 /* nvm cfg option number */
24602 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
24604 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff)
24605 uint16_t dimensions;
24607 * Number of dimensions for this nvm configuration variable. This value
24608 * indicates how many of the indexN values to use. A value of 0 means
24609 * that none of the indexN values are valid. A value of 1 requires at
24610 * index0 is valued, a value of 2 requires that index0 and index1 are
24611 * valid, and so forth
24614 /* index for the 1st dimensions */
24616 /* index for the 2nd dimensions */
24618 /* index for the 3rd dimensions */
24620 /* index for the 4th dimensions */
24623 * When this bit is 1, flush internal cache after this write operation
24624 * (see hwrm_nvm_flush command.)
24626 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH UINT32_C(0x1)
24627 /* encryption method */
24628 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK UINT32_C(0xe)
24629 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_SFT 1
24630 /* No encryption. */
24631 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE (UINT32_C(0x0) << 1)
24632 /* one-way encryption. */
24633 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (UINT32_C(0x1) << 1)
24634 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_LAST HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1
24636 } __attribute__((packed));
24638 /* Output (16 bytes) */
24640 struct hwrm_nvm_set_variable_output {
24641 uint16_t error_code;
24643 * Pass/Fail or error type Note: receiver to verify the in parameters,
24644 * and fail the call with an error when appropriate
24647 /* This field returns the type of original request. */
24649 /* This field provides original sequence number of the command. */
24652 * This field is the length of the response in bytes. The last byte of
24653 * the response is a valid flag that will read as '1' when the command
24654 * has been completely written to memory.
24662 * This field is used in Output records to indicate that the output is
24663 * completely written to RAM. This field should be read as '1' to
24664 * indicate that the output has been completely written. When writing a
24665 * command completion or response to an internal processor, the order of
24666 * writes has to be such that this field is written last.
24668 } __attribute__((packed));
24670 /* Command specific Error Codes (8 bytes) */
24672 struct hwrm_nvm_set_variable_cmd_err {
24675 * command specific error codes that goes to the cmd_err field in Common
24676 * HWRM Error Response.
24678 /* Unknown error */
24679 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
24680 /* variable does not exist */
24681 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
24682 /* configuration is corrupted and the variable cannot be saved */
24683 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
24684 uint8_t unused_0[7];
24685 } __attribute__((packed));
24687 /* hwrm_nvm_validate_option */
24688 /* Input (40 bytes) */
24690 struct hwrm_nvm_validate_option_input {
24693 * This value indicates what type of request this is. The format for the
24694 * rest of the command is determined by this field.
24696 uint16_t cmpl_ring;
24698 * This value indicates the what completion ring the request will be
24699 * optionally completed on. If the value is -1, then no CR completion
24700 * will be generated. Any other value must be a valid CR ring_id value
24701 * for this function.
24704 /* This value indicates the command sequence number. */
24705 uint16_t target_id;
24707 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
24708 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
24710 uint64_t resp_addr;
24712 * This is the host address where the response will be written when the
24713 * request is complete. This area must be 16B aligned and must be
24714 * cleared to zero before the request is made.
24716 uint64_t src_data_addr;
24717 /* This is the host address where nvm variable will be copied from */
24719 /* size of data in bits */
24720 uint16_t option_num;
24721 /* nvm cfg option number */
24723 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
24725 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff)
24726 uint16_t dimensions;
24728 * Number of dimensions for this nvm configuration variable. This value
24729 * indicates how many of the indexN values to use. A value of 0 means
24730 * that none of the indexN values are valid. A value of 1 requires at
24731 * index0 is valued, a value of 2 requires that index0 and index1 are
24732 * valid, and so forth
24735 /* index for the 1st dimensions */
24737 /* index for the 2nd dimensions */
24739 /* index for the 3rd dimensions */
24741 /* index for the 4th dimensions */
24743 } __attribute__((packed));
24745 /* Output (16 bytes) */
24747 struct hwrm_nvm_validate_option_output {
24748 uint16_t error_code;
24750 * Pass/Fail or error type Note: receiver to verify the in parameters,
24751 * and fail the call with an error when appropriate
24754 /* This field returns the type of original request. */
24756 /* This field provides original sequence number of the command. */
24759 * This field is the length of the response in bytes. The last byte of
24760 * the response is a valid flag that will read as '1' when the command
24761 * has been completely written to memory.
24765 * indicates that the value provided for the option is not
24766 * matching with the saved data.
24768 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
24770 * indicates that the value provided for the option is matching
24773 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
24781 * This field is used in Output records to indicate that the output is
24782 * completely written to RAM. This field should be read as '1' to
24783 * indicate that the output has been completely written. When writing a
24784 * command completion or response to an internal processor, the order of
24785 * writes has to be such that this field is written last.
24787 } __attribute__((packed));
24789 /* Command specific Error Codes (8 bytes) */
24791 struct hwrm_nvm_validate_option_cmd_err {
24794 * command specific error codes that goes to the cmd_err field in Common
24795 * HWRM Error Response.
24797 /* Unknown error */
24798 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
24799 uint8_t unused_0[7];
24800 } __attribute__((packed));
24802 /* Command Queue (CMDQ) Interface */
24803 /* Description: This command queries congestion control settings. */
24804 /* Init CMDQ (16 bytes) */
24808 /* CMDQ PBL physical address. */
24809 uint16_t cmdq_size_cmdq_lvl;
24811 /* CMDQ PBL indirection levels. */
24812 #define CMDQ_INIT_CMDQ_LVL_MASK UINT32_C(0x3)
24813 #define CMDQ_INIT_CMDQ_LVL_SFT 0
24815 #define CMDQ_INIT_CMDQ_SIZE_MASK UINT32_C(0xfffc)
24816 #define CMDQ_INIT_CMDQ_SIZE_SFT 2
24817 uint16_t creq_ring_id;
24818 /* CREQ completion ring id. */
24820 /* Mailbox producer index. MSB must also be set. */
24821 } __attribute__((packed));
24823 /* Update CMDQ producer index (16 bytes) */
24825 struct cmdq_update {
24826 uint64_t reserved64;
24827 /* reserved64 is 64 b */
24828 uint32_t reserved32;
24829 /* reserved32 is 32 b */
24831 /* Mailbox producer index. */
24832 } __attribute__((packed));
24834 /* CMDQ common header structure (16 bytes) */
24838 /* Command opcode. */
24840 * Create QP command allocates QP context with the specified SQ,
24841 * RQ/SRQ, CQ and other parameters.
24843 #define CMDQ_BASE_OPCODE_CREATE_QP UINT32_C(0x1)
24845 * Destroy QP command deletes the QP context and ceases any
24846 * further reference.
24848 #define CMDQ_BASE_OPCODE_DESTROY_QP UINT32_C(0x2)
24850 * Modify QP command changes QP states and other QP specific
24853 #define CMDQ_BASE_OPCODE_MODIFY_QP UINT32_C(0x3)
24854 /* Query QP command retrieves info about the specified QP. */
24855 #define CMDQ_BASE_OPCODE_QUERY_QP UINT32_C(0x4)
24856 /* Create SRQ command allocates a SRQ with the specified parameters. */
24857 #define CMDQ_BASE_OPCODE_CREATE_SRQ UINT32_C(0x5)
24858 /* Destroy SRQ command deletes and flushes the specified SRQ. */
24859 #define CMDQ_BASE_OPCODE_DESTROY_SRQ UINT32_C(0x6)
24860 /* Query SRP command retrieves info about the specified SRQ. */
24861 #define CMDQ_BASE_OPCODE_QUERY_SRQ UINT32_C(0x8)
24862 /* Create CQ command allocates a CQ with the specified parameters. */
24863 #define CMDQ_BASE_OPCODE_CREATE_CQ UINT32_C(0x9)
24864 /* Destroy CQ command deletes and flushes the specified CQ. */
24865 #define CMDQ_BASE_OPCODE_DESTROY_CQ UINT32_C(0xa)
24866 /* Resize CQ command resizes the specified CQ. */
24867 #define CMDQ_BASE_OPCODE_RESIZE_CQ UINT32_C(0xc)
24869 * Allocate MRW command allocates a MR/MW with the specified
24870 * parameters and returns the region's L_KEY/R_KEY
24872 #define CMDQ_BASE_OPCODE_ALLOCATE_MRW UINT32_C(0xd)
24874 * De-allocate key command frees a MR/MW entry associated with
24875 * the specified key.
24877 #define CMDQ_BASE_OPCODE_DEALLOCATE_KEY UINT32_C(0xe)
24878 /* Register MR command registers memory to the specified MR. */
24879 #define CMDQ_BASE_OPCODE_REGISTER_MR UINT32_C(0xf)
24880 /* Deregister MR command de-registers memory from the specified MR. */
24881 #define CMDQ_BASE_OPCODE_DEREGISTER_MR UINT32_C(0x10)
24882 /* Add GID command adds a GID to the local address table. */
24883 #define CMDQ_BASE_OPCODE_ADD_GID UINT32_C(0x11)
24884 /* Delete GID command deletes a GID from the local address table. */
24885 #define CMDQ_BASE_OPCODE_DELETE_GID UINT32_C(0x12)
24886 /* Modify GID command modifies a GID in the local address table. */
24887 #define CMDQ_BASE_OPCODE_MODIFY_GID UINT32_C(0x17)
24888 /* Query GID command queries a GID in the local address table. */
24889 #define CMDQ_BASE_OPCODE_QUERY_GID UINT32_C(0x18)
24890 /* Create QP1 command allocates a QP1 only. */
24891 #define CMDQ_BASE_OPCODE_CREATE_QP1 UINT32_C(0x13)
24892 /* Destroy QP1 command deletes and flushes the specified QP1. */
24893 #define CMDQ_BASE_OPCODE_DESTROY_QP1 UINT32_C(0x14)
24894 /* Create AH command allocates an AH with the specified parameters. */
24895 #define CMDQ_BASE_OPCODE_CREATE_AH UINT32_C(0x15)
24896 /* Destroy AH command deletes the specified AH. */
24897 #define CMDQ_BASE_OPCODE_DESTROY_AH UINT32_C(0x16)
24899 * Initialize firmware command initializes the firmware with the
24900 * specified parameters.
24902 #define CMDQ_BASE_OPCODE_INITIALIZE_FW UINT32_C(0x80)
24903 /* De-initialize firmware command deinitializes the firmware. */
24904 #define CMDQ_BASE_OPCODE_DEINITIALIZE_FW UINT32_C(0x81)
24905 /* Stop the function */
24906 #define CMDQ_BASE_OPCODE_STOP_FUNC UINT32_C(0x82)
24907 /* Query the HW capabilities for the function. */
24908 #define CMDQ_BASE_OPCODE_QUERY_FUNC UINT32_C(0x83)
24910 * Set the following resources for the function: - Max QP, CQ,
24911 * MR+MW, SRQ per PF - Max QP, CQ, MR+MW, SRQ per VF
24913 #define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES UINT32_C(0x84)
24915 * Read the current state of any internal resource context. Can
24916 * only be issued from a PF.
24918 #define CMDQ_BASE_OPCODE_READ_CONTEXT UINT32_C(0x85)
24920 * Send a request from VF to pass a command to the PF. VF HSI is
24921 * suspended until the PF returns the response
24923 #define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST UINT32_C(0x86)
24925 * Read VF memory (primarily to get the backchannel request
24926 * blob). Can only be issued from a PF.
24928 #define CMDQ_BASE_OPCODE_READ_VF_MEMORY UINT32_C(0x87)
24930 * Write VF memory (primarily to put the backchannel response
24931 * blob), and reenable VF HSI (post a CAG completion to it). Can
24932 * only be issued from a PF.
24934 #define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST UINT32_C(0x88)
24936 * Extend resource (QPC, MRW, CQ, SRQ) array, after the host
24937 * allocates more. Can only be issued from a PF.
24939 #define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRRAY UINT32_C(0x89)
24940 /* Map TC to COS. Can only be issued from a PF. */
24941 #define CMDQ_BASE_OPCODE_MAP_TC_TO_COS UINT32_C(0x8a)
24942 /* Query version. */
24943 #define CMDQ_BASE_OPCODE_QUERY_VERSION UINT32_C(0x8b)
24944 /* Modify congestion control. Can only be issued from a PF. */
24945 #define CMDQ_BASE_OPCODE_MODIFY_ROCE_CC UINT32_C(0x8c)
24946 /* Query congestion control. */
24947 #define CMDQ_BASE_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d)
24949 /* Size of the command in 16-byte units. */
24951 /* Flags and attribs of the command. */
24953 /* Driver supplied handle to associate the command and the response. */
24955 /* Size of the response buffer in 16-byte units. */
24957 uint64_t resp_addr;
24958 /* Host address of the response. */
24959 } __attribute__((packed));
24961 /* Create QP command (96 bytes) */
24963 struct cmdq_create_qp {
24965 /* Command opcode. */
24967 * Create QP command allocates QP context with the specified SQ,
24968 * RQ/SRQ, CQ and other parameters.
24970 #define CMDQ_CREATE_QP_OPCODE_CREATE_QP UINT32_C(0x1)
24972 /* Size of the command in 16-byte units. */
24974 /* Flags and attribs of the command. */
24976 /* Driver supplied handle to associate the command and the response. */
24978 /* Size of the response buffer in 16-byte units. */
24980 uint64_t resp_addr;
24981 /* Host address of the response. */
24982 uint64_t qp_handle;
24985 /* Create QP flags. */
24987 #define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED UINT32_C(0x1)
24988 /* post CQE for all SQ WQEs. */
24989 #define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION UINT32_C(0x2)
24990 /* This QP can use reserved L_Key */
24991 #define CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE UINT32_C(0x4)
24992 /* This QP can fast register physical memory */
24993 #define CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED UINT32_C(0x8)
24995 /* Supported QP types. */
24996 /* Reliable Connection. */
24997 #define CMDQ_CREATE_QP_TYPE_RC UINT32_C(0x2)
24998 /* Unreliable Datagram. */
24999 #define CMDQ_CREATE_QP_TYPE_UD UINT32_C(0x4)
25000 /* Raw Ethertype. */
25001 #define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE UINT32_C(0x6)
25002 uint8_t sq_pg_size_sq_lvl;
25003 /* SQ page size. */
25004 /* SQ PBL indirect levels. */
25005 #define CMDQ_CREATE_QP_SQ_LVL_MASK UINT32_C(0xf)
25006 #define CMDQ_CREATE_QP_SQ_LVL_SFT 0
25007 /* PBL pointer is physical start address. */
25008 #define CMDQ_CREATE_QP_SQ_LVL_LVL_0 UINT32_C(0x0)
25009 /* PBL pointer points to PTE table. */
25010 #define CMDQ_CREATE_QP_SQ_LVL_LVL_1 UINT32_C(0x1)
25012 * PBL pointer points to PDE table with each entry pointing to
25015 #define CMDQ_CREATE_QP_SQ_LVL_LVL_2 UINT32_C(0x2)
25016 /* SQ page size. */
25017 #define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK UINT32_C(0xf0)
25018 #define CMDQ_CREATE_QP_SQ_PG_SIZE_SFT 4
25020 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
25022 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
25024 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
25026 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
25028 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
25030 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
25031 uint8_t rq_pg_size_rq_lvl;
25032 /* RQ page size. */
25033 /* RQ PBL indirect levels. */
25034 #define CMDQ_CREATE_QP_RQ_LVL_MASK UINT32_C(0xf)
25035 #define CMDQ_CREATE_QP_RQ_LVL_SFT 0
25036 /* PBL pointer is physical start address. */
25037 #define CMDQ_CREATE_QP_RQ_LVL_LVL_0 UINT32_C(0x0)
25038 /* PBL pointer points to PTE table. */
25039 #define CMDQ_CREATE_QP_RQ_LVL_LVL_1 UINT32_C(0x1)
25041 * PBL pointer points to PDE table with each entry pointing to
25044 #define CMDQ_CREATE_QP_RQ_LVL_LVL_2 UINT32_C(0x2)
25045 /* RQ page size. */
25046 #define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK UINT32_C(0xf0)
25047 #define CMDQ_CREATE_QP_RQ_PG_SIZE_SFT 4
25049 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
25051 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
25053 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
25055 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
25057 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
25059 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
25062 /* Doorbell page index. */
25064 /* Max number of SQ wqes. */
25066 /* Max number of RQ wqes. */
25067 uint16_t sq_fwo_sq_sge;
25068 /* Offset of First WQE in the first SQ page, in 128 byte units */
25069 /* Max send SGEs per SWQE. */
25070 #define CMDQ_CREATE_QP_SQ_SGE_MASK UINT32_C(0xf)
25071 #define CMDQ_CREATE_QP_SQ_SGE_SFT 0
25072 /* Offset of First WQE in the first SQ page, in 128 byte units */
25073 #define CMDQ_CREATE_QP_SQ_FWO_MASK UINT32_C(0xfff0)
25074 #define CMDQ_CREATE_QP_SQ_FWO_SFT 4
25075 uint16_t rq_fwo_rq_sge;
25076 /* Offset of First WQE in the first RQ page, in 128 byte units */
25077 /* Max recv SGEs per RWQE (NOT SUPPORTED BY HARDWARE). */
25078 #define CMDQ_CREATE_QP_RQ_SGE_MASK UINT32_C(0xf)
25079 #define CMDQ_CREATE_QP_RQ_SGE_SFT 0
25080 /* Offset of First WQE in the first RQ page, in 128 byte units */
25081 #define CMDQ_CREATE_QP_RQ_FWO_MASK UINT32_C(0xfff0)
25082 #define CMDQ_CREATE_QP_RQ_FWO_SFT 4
25084 /* Send CQ context id. */
25086 /* Receive CQ context id. */
25088 /* SRQ CQ context id. */
25090 /* Protection domain id. */
25092 /* SQ PBL physical address. */
25094 /* RQ PBL physical address. */
25095 uint64_t irrq_addr;
25096 /* IRRQ address. */
25097 uint64_t orrq_addr;
25098 /* ORRQ address. */
25099 } __attribute__((packed));
25101 /* Destroy QP command (24 bytes) */
25103 struct cmdq_destroy_qp {
25105 /* Command opcode. */
25107 * Destroy QP command deletes the QP context and ceases any
25108 * further reference.
25110 #define CMDQ_DESTROY_QP_OPCODE_DESTROY_QP UINT32_C(0x2)
25112 /* Size of the command in 16-byte units. */
25114 /* Flags and attribs of the command. */
25116 /* Driver supplied handle to associate the command and the response. */
25118 /* Size of the response buffer in 16-byte units. */
25120 uint64_t resp_addr;
25121 /* Host address of the response. */
25123 /* QP context id */
25125 } __attribute__((packed));
25127 /* Modify QP command (112 bytes) */
25129 struct cmdq_modify_qp {
25131 /* Command opcode. */
25133 * Modify QP command changes QP states and other QP specific
25136 #define CMDQ_MODIFY_QP_OPCODE_MODIFY_QP UINT32_C(0x3)
25138 /* Size of the command in 16-byte units. */
25140 /* Flags and attribs of the command. */
25142 /* Driver supplied handle to associate the command and the response. */
25144 /* Size of the response buffer in 16-byte units. */
25146 uint64_t resp_addr;
25147 /* Host address of the response. */
25148 uint32_t modify_mask;
25149 /* Modify mask signifies the field that is requesting the change. */
25150 /* QP state change. */
25151 #define CMDQ_MODIFY_QP_MODIFY_MASK_STATE UINT32_C(0x1)
25152 /* Enable SQ drain asynchronous notification change. */
25153 #define CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY UINT32_C(0x2)
25154 /* Access change. */
25155 #define CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS UINT32_C(0x4)
25156 /* P_KEY change. */
25157 #define CMDQ_MODIFY_QP_MODIFY_MASK_PKEY UINT32_C(0x8)
25158 /* Q_KEY index change. */
25159 #define CMDQ_MODIFY_QP_MODIFY_MASK_QKEY UINT32_C(0x10)
25160 /* Destination GID change. */
25161 #define CMDQ_MODIFY_QP_MODIFY_MASK_DGID UINT32_C(0x20)
25162 /* Flow label change. */
25163 #define CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL UINT32_C(0x40)
25165 #define CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX UINT32_C(0x80)
25166 /* Hop limit change. */
25167 #define CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT UINT32_C(0x100)
25168 /* Traffic class change. */
25169 #define CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS UINT32_C(0x200)
25170 /* destination MAC change. */
25171 #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC UINT32_C(0x400)
25172 /* unused is 1 b */
25173 #define CMDQ_MODIFY_QP_MODIFY_MASK_UNUSED UINT32_C(0x800)
25174 /* Path MTU change. */
25175 #define CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU UINT32_C(0x1000)
25176 /* Timeout change. */
25177 #define CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT UINT32_C(0x2000)
25178 /* Retry count change. */
25179 #define CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT UINT32_C(0x4000)
25180 /* RNR Retry change. */
25181 #define CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY UINT32_C(0x8000)
25182 /* RQ start packet sequence number change. */
25183 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN UINT32_C(0x10000)
25184 /* Max outstanding RDMA read atomic change. */
25185 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC UINT32_C(0x20000)
25186 /* RNR minimum timer change. */
25187 #define CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER UINT32_C(0x40000)
25188 /* SQ start packet sequence number change. */
25189 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN UINT32_C(0x80000)
25190 /* Max destination outstanding RDMA read atomic change. */
25191 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC UINT32_C(0x100000)
25192 /* Max send WQE change. */
25193 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE UINT32_C(0x200000)
25194 /* Max recv WQE change. */
25195 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE UINT32_C(0x400000)
25196 /* Max recv SGEs per SWQE change. */
25197 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE UINT32_C(0x800000)
25198 /* Max send SGEs per RWQE change. */
25199 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE UINT32_C(0x1000000)
25200 /* Max inline data length change. */
25201 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA UINT32_C(0x2000000)
25202 /* Destination QP id change. */
25203 #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID UINT32_C(0x4000000)
25204 /* Source MAC change. */
25205 #define CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC UINT32_C(0x8000000)
25206 /* Source VLAN id change. */
25207 #define CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID UINT32_C(0x10000000)
25208 /* Congestion control RoCE v2 change. */
25209 #define CMDQ_MODIFY_QP_MODIFY_MASK_ENABLE_CC UINT32_C(0x20000000)
25210 /* IP TOS ECN change */
25211 #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_ECN UINT32_C(0x40000000)
25212 /* IP TOS DSCP change */
25213 #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP UINT32_C(0x80000000)
25215 /* QP context id. */
25216 uint8_t network_type_en_sqd_async_notify_new_state;
25217 /* network type. */
25218 /* New QP state. */
25219 #define CMDQ_MODIFY_QP_NEW_STATE_MASK UINT32_C(0xf)
25220 #define CMDQ_MODIFY_QP_NEW_STATE_SFT 0
25222 #define CMDQ_MODIFY_QP_NEW_STATE_RESET UINT32_C(0x0)
25224 #define CMDQ_MODIFY_QP_NEW_STATE_INIT UINT32_C(0x1)
25225 /* Ready To Receive. */
25226 #define CMDQ_MODIFY_QP_NEW_STATE_RTR UINT32_C(0x2)
25227 /* Ready To Send. */
25228 #define CMDQ_MODIFY_QP_NEW_STATE_RTS UINT32_C(0x3)
25230 #define CMDQ_MODIFY_QP_NEW_STATE_SQD UINT32_C(0x4)
25232 #define CMDQ_MODIFY_QP_NEW_STATE_SQE UINT32_C(0x5)
25234 #define CMDQ_MODIFY_QP_NEW_STATE_ERR UINT32_C(0x6)
25235 /* Enable SQ drain asynchronous notification. */
25236 #define CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY UINT32_C(0x10)
25237 /* unused1 is 1 b */
25238 /* network type. */
25239 #define CMDQ_MODIFY_QP_NETWORK_TYPE_MASK UINT32_C(0xc0)
25240 #define CMDQ_MODIFY_QP_NETWORK_TYPE_SFT 6
25242 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1 (UINT32_C(0x0) << 6)
25244 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4 (UINT32_C(0x2) << 6)
25246 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 (UINT32_C(0x3) << 6)
25248 /* Access flags. */
25249 /* Local write access. */
25250 #define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE UINT32_C(0x1)
25251 /* Remote write access. */
25252 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE UINT32_C(0x2)
25253 /* Remote read access. */
25254 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ UINT32_C(0x4)
25255 /* Remote atomic access. */
25256 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC UINT32_C(0x8)
25262 /* Destination GID. */
25263 uint32_t flow_label;
25265 uint16_t sgid_index;
25266 /* Source GID index. */
25269 uint8_t traffic_class;
25270 /* Traffic class. */
25271 uint16_t dest_mac[3];
25272 /* Destination MAC address. */
25273 uint8_t tos_dscp_tos_ecn;
25275 /* IP TOS ECN. Valid values are 1 or 2 when ECN is enabled. */
25276 #define CMDQ_MODIFY_QP_TOS_ECN_MASK UINT32_C(0x3)
25277 #define CMDQ_MODIFY_QP_TOS_ECN_SFT 0
25279 #define CMDQ_MODIFY_QP_TOS_DSCP_MASK UINT32_C(0xfc)
25280 #define CMDQ_MODIFY_QP_TOS_DSCP_SFT 2
25283 /* unused4 is 4 b */
25285 #define CMDQ_MODIFY_QP_PATH_MTU_MASK UINT32_C(0xf0)
25286 #define CMDQ_MODIFY_QP_PATH_MTU_SFT 4
25288 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_256 (UINT32_C(0x0) << 4)
25290 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_512 (UINT32_C(0x1) << 4)
25292 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_1024 (UINT32_C(0x2) << 4)
25294 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_2048 (UINT32_C(0x3) << 4)
25296 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_4096 (UINT32_C(0x4) << 4)
25298 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 (UINT32_C(0x5) << 4)
25300 /* Timeout value for SWQEs. */
25302 /* Max retry count for WQEs. */
25304 /* Max RNR retry count for WQEs. */
25305 uint8_t min_rnr_timer;
25306 /* Min RNR timer that the QP will report to the remote. */
25308 /* RQ start packet sequence number. */
25310 /* SQ start packet sequence number. */
25311 uint8_t max_rd_atomic;
25312 /* Max outstanding RDMA read atomic. */
25313 uint8_t max_dest_rd_atomic;
25314 /* Max destination outstanding RDMA read atomic. */
25315 uint16_t enable_cc;
25316 /* unused15 is 15 b */
25317 /* Enable congestion control. */
25318 #define CMDQ_MODIFY_QP_ENABLE_CC UINT32_C(0x1)
25319 /* unused15 is 15 b */
25321 /* Max send WQE. */
25323 /* Max recv WQE. */
25325 /* Max send SGEs per SWQE. */
25327 /* Max recv SGEs per RWQE. */
25328 uint32_t max_inline_data;
25329 /* Max inline data length (upto 120 bytes). */
25330 uint32_t dest_qp_id;
25331 /* Destination QP id. */
25333 uint16_t src_mac[3];
25334 /* Source MAC. (Unused. Comes from Source GID index) */
25335 uint16_t vlan_pcp_vlan_dei_vlan_id;
25336 /* VLAN PCP field - Priority Code Point. */
25337 /* VLAN id. (Unused. Comes from Source GID index) */
25338 #define CMDQ_MODIFY_QP_VLAN_ID_MASK UINT32_C(0xfff)
25339 #define CMDQ_MODIFY_QP_VLAN_ID_SFT 0
25340 /* VLAN DEI field - Drop Eligibility Indicator. */
25341 #define CMDQ_MODIFY_QP_VLAN_DEI UINT32_C(0x1000)
25342 /* VLAN PCP field - Priority Code Point. */
25343 #define CMDQ_MODIFY_QP_VLAN_PCP_MASK UINT32_C(0xe000)
25344 #define CMDQ_MODIFY_QP_VLAN_PCP_SFT 13
25345 } __attribute__((packed));
25347 /* Query QP command (24 bytes) */
25349 struct cmdq_query_qp {
25351 /* Command opcode. */
25352 /* Query QP command retrieves info about the specified QP. */
25353 #define CMDQ_QUERY_QP_OPCODE_QUERY_QP UINT32_C(0x4)
25355 /* Size of the command in 16-byte units. */
25357 /* Flags and attribs of the command. */
25359 /* Driver supplied handle to associate the command and the response. */
25361 /* Size of the response buffer in 16-byte units. */
25363 uint64_t resp_addr;
25364 /* Host address of the response. */
25366 /* QP context id */
25368 } __attribute__((packed));
25370 /* Create SRQ command (48 bytes) */
25372 struct cmdq_create_srq {
25374 /* Command opcode. */
25375 /* Create SRQ command allocates a SRQ with the specified parameters. */
25376 #define CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ UINT32_C(0x5)
25378 /* Size of the command in 16-byte units. */
25380 /* Flags and attribs of the command. */
25382 /* Driver supplied handle to associate the command and the response. */
25384 /* Size of the response buffer in 16-byte units. */
25386 uint64_t resp_addr;
25387 /* Host address of the response. */
25388 uint64_t srq_handle;
25390 uint16_t pg_size_lvl;
25391 /* unused11 is 11 b */
25392 /* SRQ PBL indirect levels. */
25393 #define CMDQ_CREATE_SRQ_LVL_MASK UINT32_C(0x3)
25394 #define CMDQ_CREATE_SRQ_LVL_SFT 0
25395 /* PBL pointer is physical start address. */
25396 #define CMDQ_CREATE_SRQ_LVL_LVL_0 UINT32_C(0x0)
25397 /* PBL pointer points to PTE table. */
25398 #define CMDQ_CREATE_SRQ_LVL_LVL_1 UINT32_C(0x1)
25400 * PBL pointer points to PDE table with each entry pointing to
25403 #define CMDQ_CREATE_SRQ_LVL_LVL_2 UINT32_C(0x2)
25405 #define CMDQ_CREATE_SRQ_PG_SIZE_MASK UINT32_C(0x1c)
25406 #define CMDQ_CREATE_SRQ_PG_SIZE_SFT 2
25408 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 2)
25410 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 2)
25412 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 2)
25414 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 2)
25416 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 2)
25418 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 2)
25419 /* unused11 is 11 b */
25420 uint16_t eventq_id;
25421 /* unused4 is 4 b */
25422 /* eventq_id is 12 b */
25423 #define CMDQ_CREATE_SRQ_EVENTQ_ID_MASK UINT32_C(0xfff)
25424 #define CMDQ_CREATE_SRQ_EVENTQ_ID_SFT 0
25425 /* unused4 is 4 b */
25427 /* Max number of SRQ wqes. */
25429 /* Offsetof first WQE in the first page of SRQ, in 128 byte units */
25431 /* Doorbell page index. */
25433 /* Protection domain id. */
25435 /* RQ PBL physical address. */
25436 } __attribute__((packed));
25438 /* Destroy SRQ command (24 bytes) */
25440 struct cmdq_destroy_srq {
25442 /* Command opcode. */
25443 /* Destroy SRQ command deletes and flushes the specified SRQ. */
25444 #define CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ UINT32_C(0x6)
25446 /* Size of the command in 16-byte units. */
25448 /* Flags and attribs of the command. */
25450 /* Driver supplied handle to associate the command and the response. */
25452 /* Size of the response buffer in 16-byte units. */
25454 uint64_t resp_addr;
25455 /* Host address of the response. */
25457 /* SRQ context id */
25459 } __attribute__((packed));
25461 /* Query SRQ command (24 bytes) */
25463 struct cmdq_query_srq {
25465 /* Command opcode. */
25466 /* Query SRP command retrieves info about the specified SRQ. */
25467 #define CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ UINT32_C(0x8)
25469 /* Size of the command in 16-byte units. */
25471 /* Flags and attribs of the command. */
25473 /* Driver supplied handle to associate the command and the response. */
25475 /* Size of the response buffer in 16-byte units. */
25477 uint64_t resp_addr;
25478 /* Host address of the response. */
25480 /* SRQ context id */
25482 } __attribute__((packed));
25484 /* Create CQ command (48 bytes) */
25486 struct cmdq_create_cq {
25488 /* Command opcode. */
25489 /* Create CQ command allocates a CQ with the specified parameters. */
25490 #define CMDQ_CREATE_CQ_OPCODE_CREATE_CQ UINT32_C(0x9)
25492 /* Size of the command in 16-byte units. */
25494 /* Flags and attribs of the command. */
25496 /* Driver supplied handle to associate the command and the response. */
25498 /* Size of the response buffer in 16-byte units. */
25500 uint64_t resp_addr;
25501 /* Host address of the response. */
25502 uint64_t cq_handle;
25504 uint32_t pg_size_lvl;
25505 /* unused27 is 27 b */
25506 /* PBL indirect levels. */
25507 #define CMDQ_CREATE_CQ_LVL_MASK UINT32_C(0x3)
25508 #define CMDQ_CREATE_CQ_LVL_SFT 0
25509 /* PBL pointer is physical start address. */
25510 #define CMDQ_CREATE_CQ_LVL_LVL_0 UINT32_C(0x0)
25511 /* PBL pointer points to PTE table. */
25512 #define CMDQ_CREATE_CQ_LVL_LVL_1 UINT32_C(0x1)
25514 * PBL pointer points to PDE table with each entry pointing to
25517 #define CMDQ_CREATE_CQ_LVL_LVL_2 UINT32_C(0x2)
25519 #define CMDQ_CREATE_CQ_PG_SIZE_MASK UINT32_C(0x1c)
25520 #define CMDQ_CREATE_CQ_PG_SIZE_SFT 2
25522 #define CMDQ_CREATE_CQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 2)
25524 #define CMDQ_CREATE_CQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 2)
25526 #define CMDQ_CREATE_CQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 2)
25528 #define CMDQ_CREATE_CQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 2)
25530 #define CMDQ_CREATE_CQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 2)
25532 #define CMDQ_CREATE_CQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 2)
25533 /* unused27 is 27 b */
25534 uint32_t cq_fco_cnq_id;
25535 /* Offset of first CQE in the first Page, in 32 byte units */
25536 /* cnq_id is 12 b */
25537 #define CMDQ_CREATE_CQ_CNQ_ID_MASK UINT32_C(0xfff)
25538 #define CMDQ_CREATE_CQ_CNQ_ID_SFT 0
25539 /* Offset of first CQE in the first Page, in 32 byte units */
25540 #define CMDQ_CREATE_CQ_CQ_FCO_MASK UINT32_C(0xfffff000)
25541 #define CMDQ_CREATE_CQ_CQ_FCO_SFT 12
25543 /* Doorbell page index. */
25545 /* Max number of CQ wqes. */
25547 /* CQ PBL physical address. */
25548 } __attribute__((packed));
25550 /* Destroy CQ command (24 bytes) */
25552 struct cmdq_destroy_cq {
25554 /* Command opcode. */
25555 /* Destroy CQ command deletes and flushes the specified CQ. */
25556 #define CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ UINT32_C(0xa)
25558 /* Size of the command in 16-byte units. */
25560 /* Flags and attribs of the command. */
25562 /* Driver supplied handle to associate the command and the response. */
25564 /* Size of the response buffer in 16-byte units. */
25566 uint64_t resp_addr;
25567 /* Host address of the response. */
25569 /* CQ context id */
25571 } __attribute__((packed));
25573 /* Resize CQ command (40 bytes) */
25575 struct cmdq_resize_cq {
25577 /* Command opcode. */
25578 /* Resize CQ command resizes the specified CQ. */
25579 #define CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ UINT32_C(0xc)
25581 /* Size of the command in 16-byte units. */
25583 /* Flags and attribs of the command. */
25585 /* Driver supplied handle to associate the command and the response. */
25587 /* Size of the response buffer in 16-byte units. */
25589 uint64_t resp_addr;
25590 /* Host address of the response. */
25592 /* CQ context id */
25593 uint32_t new_cq_size_pg_size_lvl;
25594 /* PBL indirect levels. */
25595 #define CMDQ_RESIZE_CQ_LVL_MASK UINT32_C(0x3)
25596 #define CMDQ_RESIZE_CQ_LVL_SFT 0
25597 /* PBL pointer is physical start address. */
25598 #define CMDQ_RESIZE_CQ_LVL_LVL_0 UINT32_C(0x0)
25599 /* PBL pointer points to PTE table. */
25600 #define CMDQ_RESIZE_CQ_LVL_LVL_1 UINT32_C(0x1)
25602 * PBL pointer points to PDE table with each entry pointing to
25605 #define CMDQ_RESIZE_CQ_LVL_LVL_2 UINT32_C(0x2)
25607 #define CMDQ_RESIZE_CQ_PG_SIZE_MASK UINT32_C(0x1c)
25608 #define CMDQ_RESIZE_CQ_PG_SIZE_SFT 2
25610 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 2)
25612 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 2)
25614 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 2)
25616 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 2)
25618 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 2)
25620 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 2)
25621 /* New max number of CQ wqes. */
25622 #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK UINT32_C(0x1fffe0)
25623 #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_SFT 5
25625 /* CQ PBL physical address. */
25626 uint32_t new_cq_fco;
25627 /* Offset of first CQE in the first Page, in 32 byte units */
25629 } __attribute__((packed));
25631 /* Allocate MRW command (32 bytes) */
25633 struct cmdq_allocate_mrw {
25635 /* Command opcode. */
25637 * Allocate MRW command allocates a MR/MW with the specified
25638 * parameters and returns the region's L_KEY/R_KEY
25640 #define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW UINT32_C(0xd)
25642 /* Size of the command in 16-byte units. */
25644 /* Flags and attribs of the command. */
25646 /* Driver supplied handle to associate the command and the response. */
25648 /* Size of the response buffer in 16-byte units. */
25650 uint64_t resp_addr;
25651 /* Host address of the response. */
25652 uint64_t mrw_handle;
25655 /* unused4 is 4 b */
25656 /* Allocate MRW flags. */
25657 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK UINT32_C(0xf)
25658 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_SFT 0
25659 /* Allocate Memory Region */
25660 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR UINT32_C(0x0)
25661 /* Allocate Physical Memory Region */
25662 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR UINT32_C(0x1)
25663 /* Allocate Memory Window (type 1) */
25664 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 UINT32_C(0x2)
25665 /* Allocate Memory Window (type 2A) */
25666 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A UINT32_C(0x3)
25667 /* Allocate Memory Window (type 2B) */
25668 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B UINT32_C(0x4)
25669 /* unused4 is 4 b */
25671 /* Access flags. */
25672 #define CMDQ_ALLOCATE_MRW_ACCESS_RESERVED_MASK UINT32_C(0x1f)
25673 #define CMDQ_ALLOCATE_MRW_ACCESS_RESERVED_SFT 0
25674 /* Consumer owns the key */
25675 #define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY UINT32_C(0x20)
25677 /* unused16 is 16 b */
25679 /* Protection domain id. */
25680 } __attribute__((packed));
25682 /* De-allocate key command (24 bytes) */
25684 struct cmdq_deallocate_key {
25686 /* Command opcode. */
25688 * De-allocate key command frees a MR/MW entry associated with
25689 * the specified key.
25691 #define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY UINT32_C(0xe)
25693 /* Size of the command in 16-byte units. */
25695 /* Flags and attribs of the command. */
25697 /* Driver supplied handle to associate the command and the response. */
25699 /* Size of the response buffer in 16-byte units. */
25701 uint64_t resp_addr;
25702 /* Host address of the response. */
25704 /* unused4 is 4 b */
25705 /* Deallocate MRW flags. */
25706 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MASK UINT32_C(0xf)
25707 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_SFT 0
25708 /* Deallocate Memory Region */
25709 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MR UINT32_C(0x0)
25710 /* Deallocate Physical Memory Region */
25711 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_PMR UINT32_C(0x1)
25712 /* Deallocate Memory Window (type 1) */
25713 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE1 UINT32_C(0x2)
25714 /* Deallocate Memory Window (type 2A) */
25715 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2A UINT32_C(0x3)
25716 /* Deallocate Memory Window (type 2B) */
25717 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B UINT32_C(0x4)
25718 /* unused4 is 4 b */
25719 uint8_t unused_1[3];
25720 /* unused24 is 24 b */
25723 } __attribute__((packed));
25725 /* Register MR command (48 bytes) */
25727 struct cmdq_register_mr {
25729 /* Command opcode. */
25730 /* Register MR command registers memory to the specified MR. */
25731 #define CMDQ_REGISTER_MR_OPCODE_REGISTER_MR UINT32_C(0xf)
25733 /* Size of the command in 16-byte units. */
25735 /* Flags and attribs of the command. */
25737 /* Driver supplied handle to associate the command and the response. */
25739 /* Size of the response buffer in 16-byte units. */
25741 uint64_t resp_addr;
25742 /* Host address of the response. */
25743 uint8_t log2_pg_size_lvl;
25744 /* unused1 is 1 b */
25745 /* PBL indirect levels. */
25746 #define CMDQ_REGISTER_MR_LVL_MASK UINT32_C(0x3)
25747 #define CMDQ_REGISTER_MR_LVL_SFT 0
25748 /* PBL pointer is physical start address. */
25749 #define CMDQ_REGISTER_MR_LVL_LVL_0 UINT32_C(0x0)
25750 /* PBL pointer points to PTE table. */
25751 #define CMDQ_REGISTER_MR_LVL_LVL_1 UINT32_C(0x1)
25753 * PBL pointer points to PDE table with each entry pointing to
25756 #define CMDQ_REGISTER_MR_LVL_LVL_2 UINT32_C(0x2)
25758 * Log base 2 of page size; 12 is the minimum for 4KB. HW supported
25759 * values are enumerated below.
25761 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK UINT32_C(0x7c)
25762 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT 2
25764 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4K (UINT32_C(0xc) << 2)
25766 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_8K (UINT32_C(0xd) << 2)
25768 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_64K (UINT32_C(0x10) << 2)
25770 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_256K (UINT32_C(0x12) << 2)
25772 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1M (UINT32_C(0x14) << 2)
25774 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_2M (UINT32_C(0x15) << 2)
25776 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4M (UINT32_C(0x16) << 2)
25778 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G (UINT32_C(0x1e) << 2)
25779 /* unused1 is 1 b */
25781 /* Access flags. */
25782 /* Local write access. */
25783 #define CMDQ_REGISTER_MR_ACCESS_LOCAL_WRITE UINT32_C(0x1)
25784 /* Remote read access. */
25785 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_READ UINT32_C(0x2)
25786 /* Remote write access. */
25787 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_WRITE UINT32_C(0x4)
25788 /* Remote atomic access. */
25789 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_ATOMIC UINT32_C(0x8)
25790 /* Bind access allowed. */
25791 #define CMDQ_REGISTER_MR_ACCESS_MW_BIND UINT32_C(0x10)
25792 /* Indicate Zero Based Virtual Address (ZBVA). */
25793 #define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED UINT32_C(0x20)
25794 uint16_t log2_pbl_pg_size;
25795 /* unused11 is 11 b */
25797 * Log base 2 of PBL page size; 12 is the minimum for 4KB. HW supported
25798 * values are enumerated below
25800 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK UINT32_C(0x1f)
25801 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT 0
25803 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K UINT32_C(0xc)
25805 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K UINT32_C(0xd)
25807 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K UINT32_C(0x10)
25809 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K UINT32_C(0x12)
25811 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M UINT32_C(0x14)
25813 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M UINT32_C(0x15)
25815 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M UINT32_C(0x16)
25817 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G UINT32_C(0x1e)
25818 /* unused11 is 11 b */
25820 /* KEY of the MR. */
25822 /* Page table of the MR memory. */
25824 /* Virtual address of the MR. */
25826 /* Size of the MR. */
25827 } __attribute__((packed));
25829 /* Deregister MR command (24 bytes) */
25831 struct cmdq_deregister_mr {
25833 /* Command opcode. */
25834 /* Deregister MR command de-registers memory from the specified MR. */
25835 #define CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR UINT32_C(0x10)
25837 /* Size of the command in 16-byte units. */
25839 /* Flags and attribs of the command. */
25841 /* Driver supplied handle to associate the command and the response. */
25843 /* Size of the response buffer in 16-byte units. */
25845 uint64_t resp_addr;
25846 /* Host address of the response. */
25848 /* L_KEY of the MR. */
25850 } __attribute__((packed));
25852 /* Add GID command (48 bytes) */
25854 struct cmdq_add_gid {
25856 /* Command opcode. */
25857 /* Add GID command adds a GID to the local address table. */
25858 #define CMDQ_ADD_GID_OPCODE_ADD_GID UINT32_C(0x11)
25860 /* Size of the command in 16-byte units. */
25862 /* Flags and attribs of the command. */
25864 /* Driver supplied handle to associate the command and the response. */
25866 /* Size of the response buffer in 16-byte units. */
25868 uint64_t resp_addr;
25869 /* Host address of the response. */
25872 uint16_t src_mac[3];
25876 /* Source VLAN id. */
25877 #define CMDQ_ADD_GID_VLAN_VLAN_ID_MASK UINT32_C(0xfff)
25878 #define CMDQ_ADD_GID_VLAN_VLAN_ID_SFT 0
25879 /* This set of bits select the TPID of the VLAN Tag. */
25880 #define CMDQ_ADD_GID_VLAN_TPID_MASK UINT32_C(0x7000)
25881 #define CMDQ_ADD_GID_VLAN_TPID_SFT 12
25882 /* TPID = 0x88A8. */
25883 #define CMDQ_ADD_GID_VLAN_TPID_TPID_88A8 (UINT32_C(0x0) << 12)
25884 /* TPID = 0x8100. */
25885 #define CMDQ_ADD_GID_VLAN_TPID_TPID_8100 (UINT32_C(0x1) << 12)
25886 /* TPID = 0x9100. */
25887 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9100 (UINT32_C(0x2) << 12)
25888 /* TPID = 0x9200. */
25889 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9200 (UINT32_C(0x3) << 12)
25890 /* TPID = 0x9300. */
25891 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9300 (UINT32_C(0x4) << 12)
25892 /* TPID = Configurable 1. */
25893 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG1 (UINT32_C(0x5) << 12)
25894 /* TPID = Configurable 2. */
25895 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG2 (UINT32_C(0x6) << 12)
25896 /* TPID = Configurable 3. */
25897 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 (UINT32_C(0x7) << 12)
25898 #define CMDQ_ADD_GID_VLAN_TPID_LAST CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3
25900 * Setting this bit to 1 enables insertion of a VLAN Tag to a RoCE
25903 #define CMDQ_ADD_GID_VLAN_VLAN_EN UINT32_C(0x8000)
25905 /* Identifier field in the IP header. */
25906 uint16_t stats_ctx;
25907 /* Stats context ID to use with this SGID */
25908 /* stats_ctx_id is 15 b */
25909 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK UINT32_C(0x7fff)
25910 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_SFT 0
25912 * Setting this bit to 1 enables use of own stats context ID instead of
25915 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID UINT32_C(0x8000)
25917 } __attribute__((packed));
25919 /* Delete GID command (24 bytes) */
25921 struct cmdq_delete_gid {
25923 /* Command opcode. */
25924 /* Delete GID command deletes a GID from the local address table. */
25925 #define CMDQ_DELETE_GID_OPCODE_DELETE_GID UINT32_C(0x12)
25927 /* Size of the command in 16-byte units. */
25929 /* Flags and attribs of the command. */
25931 /* Driver supplied handle to associate the command and the response. */
25933 /* Size of the response buffer in 16-byte units. */
25935 uint64_t resp_addr;
25936 /* Host address of the response. */
25937 uint16_t gid_index;
25940 /* unused16 is 16 b */
25942 } __attribute__((packed));
25944 /* Modify GID command (48 bytes) */
25946 struct cmdq_modify_gid {
25948 /* Command opcode. */
25949 /* Modify GID command modifies a GID in the local address table. */
25950 #define CMDQ_MODIFY_GID_OPCODE_MODIFY_GID UINT32_C(0x17)
25952 /* Size of the command in 16-byte units. */
25954 /* Flags and attribs of the command. */
25956 /* Driver supplied handle to associate the command and the response. */
25958 /* Size of the response buffer in 16-byte units. */
25960 uint64_t resp_addr;
25961 /* Host address of the response. */
25964 uint16_t src_mac[3];
25968 /* Source VLAN id. */
25969 #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_MASK UINT32_C(0xfff)
25970 #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_SFT 0
25971 /* This set of bits select the TPID of the VLAN Tag. */
25972 #define CMDQ_MODIFY_GID_VLAN_TPID_MASK UINT32_C(0x7000)
25973 #define CMDQ_MODIFY_GID_VLAN_TPID_SFT 12
25974 /* TPID = 0x88A8. */
25975 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_88A8 (UINT32_C(0x0) << 12)
25976 /* TPID = 0x8100. */
25977 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_8100 (UINT32_C(0x1) << 12)
25978 /* TPID = 0x9100. */
25979 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9100 (UINT32_C(0x2) << 12)
25980 /* TPID = 0x9200. */
25981 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9200 (UINT32_C(0x3) << 12)
25982 /* TPID = 0x9300. */
25983 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9300 (UINT32_C(0x4) << 12)
25984 /* TPID = Configurable 1. */
25985 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG1 (UINT32_C(0x5) << 12)
25986 /* TPID = Configurable 2. */
25987 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG2 (UINT32_C(0x6) << 12)
25988 /* TPID = Configurable 3. */
25989 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 (UINT32_C(0x7) << 12)
25990 #define CMDQ_MODIFY_GID_VLAN_TPID_LAST CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3
25992 * Setting this bit to 1 enables insertion of a VLAN Tag to a RoCE
25995 #define CMDQ_MODIFY_GID_VLAN_VLAN_EN UINT32_C(0x8000)
25997 /* Identifier field in the IP header. */
25998 uint16_t gid_index;
26000 uint16_t stats_ctx;
26001 /* Stats context ID to use with this SGID */
26002 /* stats_ctx_id is 15 b */
26003 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK UINT32_C(0x7fff)
26004 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_SFT 0
26006 * Setting this bit to 1 enables use of own stats context ID instead of
26009 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID UINT32_C(0x8000)
26011 } __attribute__((packed));
26013 /* Query GID command (24 bytes) */
26015 struct cmdq_query_gid {
26017 /* Command opcode. */
26018 /* Query GID command queries a GID in the local address table. */
26019 #define CMDQ_QUERY_GID_OPCODE_QUERY_GID UINT32_C(0x18)
26021 /* Size of the command in 16-byte units. */
26023 /* Flags and attribs of the command. */
26025 /* Driver supplied handle to associate the command and the response. */
26027 /* Size of the response buffer in 16-byte units. */
26029 uint64_t resp_addr;
26030 /* Host address of the response. */
26031 uint16_t gid_index;
26034 /* unused16 is 16 b */
26036 } __attribute__((packed));
26038 /* Create QP1 command (80 bytes) */
26040 struct cmdq_create_qp1 {
26042 /* Command opcode. */
26043 /* Create QP1 command allocates a QP1 only. */
26044 #define CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 UINT32_C(0x13)
26046 /* Size of the command in 16-byte units. */
26048 /* Flags and attribs of the command. */
26050 /* Driver supplied handle to associate the command and the response. */
26052 /* Size of the response buffer in 16-byte units. */
26054 uint64_t resp_addr;
26055 /* Host address of the response. */
26056 uint64_t qp_handle;
26059 /* Create QP1 flags. */
26061 #define CMDQ_CREATE_QP1_QP_FLAGS_SRQ_USED UINT32_C(0x1)
26062 /* post CQE for all SQ WQEs. */
26063 #define CMDQ_CREATE_QP1_QP_FLAGS_FORCE_COMPLETION UINT32_C(0x2)
26064 /* This QP can use reserved L_Key */
26065 #define CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE UINT32_C(0x4)
26067 /* Supported QP1 types. */
26068 /* General Services Interface on QP 1. */
26069 #define CMDQ_CREATE_QP1_TYPE_GSI UINT32_C(0x1)
26070 uint8_t sq_pg_size_sq_lvl;
26071 /* SQ page size. */
26072 /* SQ PBL indirect levels. */
26073 #define CMDQ_CREATE_QP1_SQ_LVL_MASK UINT32_C(0xf)
26074 #define CMDQ_CREATE_QP1_SQ_LVL_SFT 0
26075 /* PBL pointer is physical start address. */
26076 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_0 UINT32_C(0x0)
26077 /* PBL pointer points to PTE table. */
26078 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_1 UINT32_C(0x1)
26080 * PBL pointer points to PDE table with each entry pointing to
26083 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_2 UINT32_C(0x2)
26084 /* SQ page size. */
26085 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_MASK UINT32_C(0xf0)
26086 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_SFT 4
26088 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
26090 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
26092 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
26094 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
26096 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
26098 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
26099 uint8_t rq_pg_size_rq_lvl;
26100 /* RQ page size. */
26101 /* RQ PBL indirect levels. */
26102 #define CMDQ_CREATE_QP1_RQ_LVL_MASK UINT32_C(0xf)
26103 #define CMDQ_CREATE_QP1_RQ_LVL_SFT 0
26104 /* PBL pointer is physical start address. */
26105 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_0 UINT32_C(0x0)
26106 /* PBL pointer points to PTE table. */
26107 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_1 UINT32_C(0x1)
26109 * PBL pointer points to PDE table with each entry pointing to
26112 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_2 UINT32_C(0x2)
26113 /* RQ page size. */
26114 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_MASK UINT32_C(0xf0)
26115 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_SFT 4
26117 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
26119 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
26121 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
26123 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
26125 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
26127 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
26130 /* Doorbell page index. */
26132 /* Max number of SQ wqes. */
26134 /* Max number of RQ wqes. */
26135 uint16_t sq_fwo_sq_sge;
26136 /* Offset of First WQE in the first SQ page, in 128 byte units */
26137 /* Max send SGEs per SWQE. */
26138 #define CMDQ_CREATE_QP1_SQ_SGE_MASK UINT32_C(0xf)
26139 #define CMDQ_CREATE_QP1_SQ_SGE_SFT 0
26140 /* Offset of First WQE in the first SQ page, in 128 byte units */
26141 #define CMDQ_CREATE_QP1_SQ_FWO_MASK UINT32_C(0xfff0)
26142 #define CMDQ_CREATE_QP1_SQ_FWO_SFT 4
26143 uint16_t rq_fwo_rq_sge;
26144 /* Offset of First WQE in the first RQ page, in 128 byte units */
26145 /* Max recv SGEs per RWQE (NOT SUPPORTED BY HARDWARE). */
26146 #define CMDQ_CREATE_QP1_RQ_SGE_MASK UINT32_C(0xf)
26147 #define CMDQ_CREATE_QP1_RQ_SGE_SFT 0
26148 /* Offset of First WQE in the first RQ page, in 128 byte units */
26149 #define CMDQ_CREATE_QP1_RQ_FWO_MASK UINT32_C(0xfff0)
26150 #define CMDQ_CREATE_QP1_RQ_FWO_SFT 4
26152 /* Send CQ context id. */
26154 /* Receive CQ context id. */
26156 /* SRQ CQ context id. */
26158 /* Protection domain id. */
26160 /* SQ PBL physical address. */
26162 /* RQ PBL physical address. */
26163 } __attribute__((packed));
26165 /* Destroy QP1 command (24 bytes) */
26167 struct cmdq_destroy_qp1 {
26169 /* Command opcode. */
26170 /* Destroy QP1 command deletes and flushes the specified QP1. */
26171 #define CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 UINT32_C(0x14)
26173 /* Size of the command in 16-byte units. */
26175 /* Flags and attribs of the command. */
26177 /* Driver supplied handle to associate the command and the response. */
26179 /* Size of the response buffer in 16-byte units. */
26181 uint64_t resp_addr;
26182 /* Host address of the response. */
26184 /* QP1 context id */
26186 } __attribute__((packed));
26188 /* Create AH command (64 bytes) */
26190 struct cmdq_create_ah {
26192 /* Command opcode. */
26193 /* Create AH command allocates an AH with the specified parameters. */
26194 #define CMDQ_CREATE_AH_OPCODE_CREATE_AH UINT32_C(0x15)
26196 /* Size of the command in 16-byte units. */
26198 /* Flags and attribs of the command. */
26200 /* Driver supplied handle to associate the command and the response. */
26202 /* Size of the response buffer in 16-byte units. */
26204 uint64_t resp_addr;
26205 /* Host address of the response. */
26206 uint64_t ah_handle;
26209 /* Destination GID. */
26211 /* V1, V2IPv4 or V2IPv6. */
26213 #define CMDQ_CREATE_AH_TYPE_V1 UINT32_C(0x0)
26215 #define CMDQ_CREATE_AH_TYPE_V2IPV4 UINT32_C(0x2)
26217 #define CMDQ_CREATE_AH_TYPE_V2IPV6 UINT32_C(0x3)
26219 /* IPv6 Hop limit. */
26220 uint16_t sgid_index;
26222 uint32_t dest_vlan_id_flow_label;
26223 /* Destination VLAN ID. */
26225 #define CMDQ_CREATE_AH_FLOW_LABEL_MASK UINT32_C(0xfffff)
26226 #define CMDQ_CREATE_AH_FLOW_LABEL_SFT 0
26227 /* Destination VLAN ID. */
26228 #define CMDQ_CREATE_AH_DEST_VLAN_ID_MASK UINT32_C(0xfff00000)
26229 #define CMDQ_CREATE_AH_DEST_VLAN_ID_SFT 20
26231 /* Protection domain id. */
26233 uint16_t dest_mac[3];
26234 /* Destination MAC address. */
26235 uint8_t traffic_class;
26236 /* Traffic class. */
26238 /* Enable congestion control. */
26239 #define CMDQ_CREATE_AH_ENABLE_CC UINT32_C(0x1)
26240 } __attribute__((packed));
26242 /* Destroy AH command (24 bytes) */
26244 struct cmdq_destroy_ah {
26246 /* Command opcode. */
26247 /* Destroy AH command deletes the specified AH. */
26248 #define CMDQ_DESTROY_AH_OPCODE_DESTROY_AH UINT32_C(0x16)
26250 /* Size of the command in 16-byte units. */
26252 /* Flags and attribs of the command. */
26254 /* Driver supplied handle to associate the command and the response. */
26256 /* Size of the response buffer in 16-byte units. */
26258 uint64_t resp_addr;
26259 /* Host address of the response. */
26261 /* AH context id */
26263 } __attribute__((packed));
26265 /* Initialize Firmware command (112 bytes) */
26267 struct cmdq_initialize_fw {
26269 /* Command opcode. */
26271 * Initialize firmware command initializes the firmware with the
26272 * specified parameters.
26274 #define CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW UINT32_C(0x80)
26276 /* Size of the command in 16-byte units. */
26278 /* Flags and attribs of the command. */
26280 /* Driver supplied handle to associate the command and the response. */
26282 /* Size of the response buffer in 16-byte units. */
26284 uint64_t resp_addr;
26285 /* Host address of the response. */
26286 uint8_t qpc_pg_size_qpc_lvl;
26287 /* QPC page size. */
26288 /* QPC PBL indirect levels. */
26289 #define CMDQ_INITIALIZE_FW_QPC_LVL_MASK UINT32_C(0xf)
26290 #define CMDQ_INITIALIZE_FW_QPC_LVL_SFT 0
26291 /* PBL pointer is physical start address. */
26292 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0 UINT32_C(0x0)
26293 /* PBL pointer points to PTE table. */
26294 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1 UINT32_C(0x1)
26296 * PBL pointer points to PDE table with each entry pointing to
26299 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 UINT32_C(0x2)
26300 /* QPC page size. */
26301 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_MASK UINT32_C(0xf0)
26302 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT 4
26304 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
26306 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
26308 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
26310 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
26312 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
26314 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
26315 uint8_t mrw_pg_size_mrw_lvl;
26316 /* MRW page size. */
26317 /* MRW PBL indirect levels. */
26318 #define CMDQ_INITIALIZE_FW_MRW_LVL_MASK UINT32_C(0xf)
26319 #define CMDQ_INITIALIZE_FW_MRW_LVL_SFT 0
26320 /* PBL pointer is physical start address. */
26321 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0 UINT32_C(0x0)
26322 /* PBL pointer points to PTE table. */
26323 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1 UINT32_C(0x1)
26325 * PBL pointer points to PDE table with each entry pointing to
26328 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 UINT32_C(0x2)
26329 /* MRW page size. */
26330 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_MASK UINT32_C(0xf0)
26331 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_SFT 4
26333 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
26335 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
26337 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
26339 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
26341 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
26343 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
26344 uint8_t srq_pg_size_srq_lvl;
26345 /* SRQ page size. */
26346 /* SRQ PBL indirect levels. */
26347 #define CMDQ_INITIALIZE_FW_SRQ_LVL_MASK UINT32_C(0xf)
26348 #define CMDQ_INITIALIZE_FW_SRQ_LVL_SFT 0
26349 /* PBL pointer is physical start address. */
26350 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0 UINT32_C(0x0)
26351 /* PBL pointer points to PTE table. */
26352 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1 UINT32_C(0x1)
26354 * PBL pointer points to PDE table with each entry pointing to
26357 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 UINT32_C(0x2)
26358 /* SRQ page size. */
26359 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_MASK UINT32_C(0xf0)
26360 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_SFT 4
26362 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
26364 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
26366 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
26368 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
26370 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
26372 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
26373 uint8_t cq_pg_size_cq_lvl;
26374 /* CQ page size. */
26375 /* CQ PBL indirect levels. */
26376 #define CMDQ_INITIALIZE_FW_CQ_LVL_MASK UINT32_C(0xf)
26377 #define CMDQ_INITIALIZE_FW_CQ_LVL_SFT 0
26378 /* PBL pointer is physical start address. */
26379 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0 UINT32_C(0x0)
26380 /* PBL pointer points to PTE table. */
26381 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1 UINT32_C(0x1)
26383 * PBL pointer points to PDE table with each entry pointing to
26386 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 UINT32_C(0x2)
26387 /* CQ page size. */
26388 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_MASK UINT32_C(0xf0)
26389 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_SFT 4
26391 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
26393 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
26395 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
26397 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
26399 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
26401 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
26402 uint8_t tqm_pg_size_tqm_lvl;
26403 /* TQM page size. */
26404 /* TQM PBL indirect levels. */
26405 #define CMDQ_INITIALIZE_FW_TQM_LVL_MASK UINT32_C(0xf)
26406 #define CMDQ_INITIALIZE_FW_TQM_LVL_SFT 0
26407 /* PBL pointer is physical start address. */
26408 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0 UINT32_C(0x0)
26409 /* PBL pointer points to PTE table. */
26410 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1 UINT32_C(0x1)
26412 * PBL pointer points to PDE table with each entry pointing to
26415 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 UINT32_C(0x2)
26416 /* TQM page size. */
26417 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_MASK UINT32_C(0xf0)
26418 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_SFT 4
26420 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
26422 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
26424 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
26426 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
26428 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
26430 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
26431 uint8_t tim_pg_size_tim_lvl;
26432 /* TIM page size. */
26433 /* TIM PBL indirect levels. */
26434 #define CMDQ_INITIALIZE_FW_TIM_LVL_MASK UINT32_C(0xf)
26435 #define CMDQ_INITIALIZE_FW_TIM_LVL_SFT 0
26436 /* PBL pointer is physical start address. */
26437 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0 UINT32_C(0x0)
26438 /* PBL pointer points to PTE table. */
26439 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1 UINT32_C(0x1)
26441 * PBL pointer points to PDE table with each entry pointing to
26444 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 UINT32_C(0x2)
26445 /* TIM page size. */
26446 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_MASK UINT32_C(0xf0)
26447 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_SFT 4
26449 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
26451 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
26453 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
26455 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
26457 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
26459 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
26460 uint16_t reserved16;
26461 uint64_t qpc_page_dir;
26462 /* Kernel notification queue page directory. */
26463 uint64_t mrw_page_dir;
26464 /* MRW page directory. */
26465 uint64_t srq_page_dir;
26466 /* SRQ page directory. */
26467 uint64_t cq_page_dir;
26468 /* CQ page directory. */
26469 uint64_t tqm_page_dir;
26470 /* TQM page directory. */
26471 uint64_t tim_page_dir;
26472 /* TIM page directory. */
26473 uint32_t number_of_qp;
26474 /* Number of QPs. */
26475 uint32_t number_of_mrw;
26476 /* Number of MRWs. */
26477 uint32_t number_of_srq;
26478 /* Number of SRQs. */
26479 uint32_t number_of_cq;
26480 /* Number of CQs. */
26481 uint32_t max_qp_per_vf;
26482 /* Number of QPs per VF. */
26483 uint32_t max_mrw_per_vf;
26484 /* Number of MRWs per VF. */
26485 uint32_t max_srq_per_vf;
26486 /* Number of SRQs per VF. */
26487 uint32_t max_cq_per_vf;
26488 /* Number of CQs per VF. */
26489 uint32_t max_gid_per_vf;
26490 /* Number of GIDs per VF. */
26491 uint32_t stat_ctx_id;
26492 /* Statistics context index for this function. */
26493 } __attribute__((packed));
26495 /* De-initialize Firmware command (16 bytes) */
26497 struct cmdq_deinitialize_fw {
26499 /* Command opcode. */
26500 /* De-initialize firmware command deinitializes the firmware. */
26501 #define CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW UINT32_C(0x81)
26503 /* Size of the command in 16-byte units. */
26505 /* Flags and attribs of the command. */
26507 /* Driver supplied handle to associate the command and the response. */
26509 /* Size of the response buffer in 16-byte units. */
26511 uint64_t resp_addr;
26512 /* Host address of the response. */
26513 } __attribute__((packed));
26515 /* Stop function command (16 bytes) */
26517 struct cmdq_stop_func {
26519 /* Command opcode. */
26520 /* Stop the function */
26521 #define CMDQ_STOP_FUNC_OPCODE_STOP_FUNC UINT32_C(0x82)
26523 /* Size of the command in 16-byte units. */
26525 /* Flags and attribs of the command. */
26527 /* Driver supplied handle to associate the command and the response. */
26529 /* Size of the response buffer in 16-byte units. */
26531 uint64_t resp_addr;
26532 /* Host address of the response. */
26533 } __attribute__((packed));
26535 /* Query function command (16 bytes) */
26537 struct cmdq_query_func {
26539 /* Command opcode. */
26540 /* Query the HW capabilities for the function. */
26541 #define CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC UINT32_C(0x83)
26543 /* Size of the command in 16-byte units. */
26545 /* Flags and attribs of the command. */
26547 /* Driver supplied handle to associate the command and the response. */
26549 /* Size of the response buffer in 16-byte units. */
26551 uint64_t resp_addr;
26552 /* Host address of the response. */
26553 } __attribute__((packed));
26555 /* Set function resources command (56 bytes) */
26557 struct cmdq_set_func_resources {
26559 /* Command opcode. */
26561 * Set the following resources for the function: - Max QP, CQ,
26562 * MR+MW, SRQ per PF - Max QP, CQ, MR+MW, SRQ per VF
26564 #define CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES UINT32_C(0x84)
26566 /* Size of the command in 16-byte units. */
26568 /* Flags and attribs of the command. */
26570 /* Driver supplied handle to associate the command and the response. */
26572 /* Size of the response buffer in 16-byte units. */
26574 uint64_t resp_addr;
26575 /* Host address of the response. */
26576 uint32_t number_of_qp;
26578 * Number of QPs. It is the responsibility of the host to first extend
26579 * the existing PBL with new addresses to pages to handle the
26580 * adjustment. Must be greater or equal to current.
26582 uint32_t number_of_mrw;
26584 * Number of MRWs. It is the responsibility of the host to first extend
26585 * the existing PBL with new addresses to pages to handle the
26586 * adjustment. Must be greater or equal to current.
26588 uint32_t number_of_srq;
26590 * Number of SRQs. It is the responsibility of the host to first extend
26591 * the existing PBL with new addresses to pages to handle the
26592 * adjustment. Must be greater or equal to current.
26594 uint32_t number_of_cq;
26596 * Number of CQs. It is the responsibility of the host to first extend
26597 * the existing PBL with new addresses to pages to handle the
26598 * adjustment. Must be greater or equal to current.
26600 uint32_t max_qp_per_vf;
26601 /* Number of QPs per VF. */
26602 uint32_t max_mrw_per_vf;
26603 /* Number of MRWs per VF. */
26604 uint32_t max_srq_per_vf;
26605 /* Number of SRQs per VF. */
26606 uint32_t max_cq_per_vf;
26607 /* Number of CQs per VF. */
26608 uint32_t max_gid_per_vf;
26609 /* Number of GIDs per VF. */
26610 uint32_t stat_ctx_id;
26611 /* Statistics context index for this function. */
26612 } __attribute__((packed));
26614 /* Read hardware resource context command (24 bytes) */
26616 struct cmdq_read_context {
26618 /* Command opcode. */
26620 * Read the current state of any internal resource context. Can
26621 * only be issued from a PF.
26623 #define CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT UINT32_C(0x85)
26625 /* Size of the command in 16-byte units. */
26627 /* Flags and attribs of the command. */
26629 /* Driver supplied handle to associate the command and the response. */
26631 /* Size of the response buffer in 16-byte units. */
26633 uint64_t resp_addr;
26634 /* Host address of the response. */
26638 #define CMDQ_READ_CONTEXT_XID_MASK UINT32_C(0xffffff)
26639 #define CMDQ_READ_CONTEXT_XID_SFT 0
26641 #define CMDQ_READ_CONTEXT_TYPE_MASK UINT32_C(0xff000000)
26642 #define CMDQ_READ_CONTEXT_TYPE_SFT 24
26644 * Read QPC. The context (448 bytes) goes to resp_addr (as is,
26645 * without a header), and resp_size should be set to 28 (448/16)
26647 #define CMDQ_READ_CONTEXT_TYPE_QPC (UINT32_C(0x0) << 24)
26649 * Read CQ. The context (64 bytes) goes to resp_addr (as is,
26650 * without a header), and resp_size should be set to 4 (64/16)
26652 #define CMDQ_READ_CONTEXT_TYPE_CQ (UINT32_C(0x1) << 24)
26654 * Read MRW. The context (128 bytes) goes to resp_addr (as is,
26655 * without a header), and resp_size should be set to 8 (128/16)
26657 #define CMDQ_READ_CONTEXT_TYPE_MRW (UINT32_C(0x2) << 24)
26659 * Read SRQ. The context (64 bytes) goes to resp_addr (as is,
26660 * without a header), and resp_size should be set to 4 (64/16)
26662 #define CMDQ_READ_CONTEXT_TYPE_SRQ (UINT32_C(0x3) << 24)
26664 } __attribute__((packed));
26666 /* Send a request from VF to pass a command to the PF. VF HSI is suspended until the PF returns the response (32 bytes) */
26668 struct cmdq_vf_backchannel_request {
26670 /* Command opcode. */
26672 * Send a request from VF to pass a command to the PF. VF HSI is
26673 * suspended until the PF returns the response
26675 #define CMDQ_VF_BACKCHANNEL_REQUEST_OPCODE_VF_BACKCHANNEL_REQUEST UINT32_C(0x86)
26677 /* Size of the command in 16-byte units. */
26679 /* Flags and attribs of the command. */
26681 /* Driver supplied handle to associate the command and the response. */
26683 /* Size of the response buffer in 16-byte units. */
26685 uint64_t resp_addr;
26686 /* Host address of the response. */
26687 uint64_t command_addr;
26688 /* Address of command request structure in VF space */
26689 uint16_t command_length;
26691 * Command request length (up to 4K). An optional address of the
26692 * extended response buffer should be provided in the request
26694 uint16_t unused_0[3];
26695 } __attribute__((packed));
26697 /* Read VF memory (primarily to get the backchannel request blob). Can only be issued from a PF. (32 bytes) */
26699 struct cmdq_read_vf_memory {
26701 /* Command opcode. */
26703 * Read VF memory (primarily to get the backchannel request
26704 * blob). Can only be issued from a PF.
26706 #define CMDQ_READ_VF_MEMORY_OPCODE_READ_VF_MEMORY UINT32_C(0x87)
26708 /* Size of the command in 16-byte units. */
26710 /* Flags and attribs of the command. */
26712 /* Driver supplied handle to associate the command and the response. */
26714 /* Size of the response buffer in 16-byte units. */
26716 uint64_t resp_addr;
26717 /* Host address of the response. */
26719 /* Address of memory in VF space to read */
26721 /* VF id, as provided in 0xC0 VF request notification */
26723 /* Length to read, up to 4K */
26725 } __attribute__((packed));
26727 /* Write VF memory (primarily to put the backchannel response blob), and reenable VF HSI (post a CAG completion to it). Can only be issued from a PF. (40 bytes) */
26729 struct cmdq_complete_vf_request {
26731 /* Command opcode. */
26733 * Write VF memory (primarily to put the backchannel response
26734 * blob), and reenable VF HSI (post a CAG completion to it). Can
26735 * only be issued from a PF.
26737 #define CMDQ_COMPLETE_VF_REQUEST_OPCODE_COMPLETE_VF_REQUEST UINT32_C(0x88)
26739 /* Size of the command in 16-byte units. */
26741 /* Flags and attribs of the command. */
26743 /* Driver supplied handle to associate the command and the response. */
26745 /* Size of the response buffer in 16-byte units. */
26747 uint64_t resp_addr;
26748 /* Host address of the response. */
26751 * Optional address of extended response in VF space to write. Length is
26752 * in resp_size in 16 byte units.
26755 /* Completion misc field to VF CREQ */
26757 /* VF id, as provided in 0xC0 VF request notification */
26758 uint16_t vf_cookie;
26759 /* Completion cookie for the VF command, goes to VF CREQ */
26761 /* Completion status for the VF command, goes to VF CREQ */
26762 uint8_t unused_0[7];
26763 } __attribute__((packed));
26765 /* Map TC to COS. Can only be issued from a PF (24 bytes) */
26767 struct cmdq_map_tc_to_cos {
26769 /* Command opcode. */
26770 /* Map TC to COS. Can only be issued from a PF. */
26771 #define CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS UINT32_C(0x8a)
26773 /* Size of the command in 16-byte units. */
26775 /* Flags and attribs of the command. */
26777 /* Driver supplied handle to associate the command and the response. */
26779 /* Size of the response buffer in 16-byte units. */
26781 uint64_t resp_addr;
26782 /* Host address of the response. */
26784 /* 1st COS index mapped to RoCE */
26785 /* Don't change this COS. */
26786 #define CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE UINT32_C(0xffff)
26788 /* 2nd COS index mapped to RoCE */
26789 /* Disable this COS. */
26790 #define CMDQ_MAP_TC_TO_COS_COS1_DISABLE UINT32_C(0x8000)
26791 /* Don't change this COS. */
26792 #define CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE UINT32_C(0xffff)
26794 } __attribute__((packed));
26796 /* Query version command (16 bytes) */
26798 struct cmdq_query_version {
26800 /* Command opcode. */
26801 /* Query version. */
26802 #define CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION UINT32_C(0x8b)
26804 /* Size of the command in 16-byte units. */
26806 /* Flags and attribs of the command. */
26808 /* Driver supplied handle to associate the command and the response. */
26810 /* Size of the response buffer in 16-byte units. */
26812 uint64_t resp_addr;
26813 /* Host address of the response. */
26814 } __attribute__((packed));
26816 /* Modify congestion control command (56 bytes) */
26818 struct cmdq_modify_roce_cc {
26820 /* Command opcode. */
26821 /* Modify congestion control. Can only be issued from a PF. */
26822 #define CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC UINT32_C(0x8c)
26824 /* Size of the command in 16-byte units. */
26826 /* Flags and attribs of the command. */
26828 /* Driver supplied handle to associate the command and the response. */
26830 /* Size of the response buffer in 16-byte units. */
26832 uint64_t resp_addr;
26833 /* Host address of the response. */
26834 uint32_t modify_mask;
26835 /* Modify mask signifies the field that is requesting the change. */
26836 /* Enable change. */
26837 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC UINT32_C(0x1)
26838 /* Running average weight change. */
26839 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_G UINT32_C(0x2)
26840 /* Number of phases in Fast Recovery. */
26841 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_NUMPHASEPERSTATE UINT32_C(0x4)
26842 /* The starting value of rate change. */
26843 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_CR UINT32_C(0x8)
26844 /* The starting value of target rate change. */
26845 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_TR UINT32_C(0x10)
26846 /* IP TOS ECN change */
26847 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN UINT32_C(0x20)
26848 /* IP TOS DSCP change */
26849 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_DSCP UINT32_C(0x40)
26850 /* Alternate IP TOS ECN change */
26851 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_VLAN_PCP UINT32_C(0x80)
26852 /* Alternate IP TOS DSCP change */
26853 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_TOS_DSCP UINT32_C(0x100)
26854 /* Round trip time in units of usecs */
26855 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_RTT UINT32_C(0x200)
26856 /* 0 for DCTCP , 1 for TCP */
26857 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE UINT32_C(0x400)
26858 /* The value used as CP when cc_mode is 1(TCP) */
26859 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TCP_CP UINT32_C(0x800)
26860 /* Specifies the RoCE Tx Queue ( o to 3) to use for sending CNP packets */
26861 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TX_QUEUE UINT32_C(0x1000)
26862 /* Inactivity time after which QP CC parameters are initialized */
26863 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INACTIVITY_CP UINT32_C(0x2000)
26867 #define CMDQ_MODIFY_ROCE_CC_ENABLE_CC UINT32_C(0x1)
26869 #define CMDQ_MODIFY_ROCE_CC_RSVD1_MASK UINT32_C(0xfe)
26870 #define CMDQ_MODIFY_ROCE_CC_RSVD1_SFT 1
26873 /* Congestion Probability averaging factor. */
26874 #define CMDQ_MODIFY_ROCE_CC_G_MASK UINT32_C(0x7)
26875 #define CMDQ_MODIFY_ROCE_CC_G_SFT 0
26877 #define CMDQ_MODIFY_ROCE_CC_RSVD2_MASK UINT32_C(0xf8)
26878 #define CMDQ_MODIFY_ROCE_CC_RSVD2_SFT 3
26879 uint8_t num_phases_per_state;
26880 /* Number of phases in Fast Recovery. */
26884 /* The starting value of rate. */
26886 /* The starting value of target rate. */
26887 uint8_t tos_dscp_tos_ecn;
26889 /* IP TOS ECN. Valid values are 1 or 2 when ECN is enabled. */
26890 #define CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK UINT32_C(0x3)
26891 #define CMDQ_MODIFY_ROCE_CC_TOS_ECN_SFT 0
26893 #define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_MASK UINT32_C(0xfc)
26894 #define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT 2
26895 uint8_t alt_vlan_pcp;
26897 /* Alternate vlan pcp value for CNP packets. */
26898 #define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_MASK UINT32_C(0x7)
26899 #define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_SFT 0
26901 #define CMDQ_MODIFY_ROCE_CC_RSVD3_MASK UINT32_C(0xf8)
26902 #define CMDQ_MODIFY_ROCE_CC_RSVD3_SFT 3
26903 uint16_t alt_tos_dscp;
26904 /* rsvd4 is 10 b */
26905 /* Alternate IP TOS DSCP. */
26906 #define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_MASK UINT32_C(0x3f)
26907 #define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_SFT 0
26908 /* rsvd4 is 10 b */
26909 #define CMDQ_MODIFY_ROCE_CC_RSVD4_MASK UINT32_C(0xffc0)
26910 #define CMDQ_MODIFY_ROCE_CC_RSVD4_SFT 6
26913 /* Round trip time in units of usecs */
26914 #define CMDQ_MODIFY_ROCE_CC_RTT_MASK UINT32_C(0x3fff)
26915 #define CMDQ_MODIFY_ROCE_CC_RTT_SFT 0
26917 #define CMDQ_MODIFY_ROCE_CC_RSVD5_MASK UINT32_C(0xc000)
26918 #define CMDQ_MODIFY_ROCE_CC_RSVD5_SFT 14
26921 /* The value used as CP when cc_mode is 1(TCP) */
26922 #define CMDQ_MODIFY_ROCE_CC_TCP_CP_MASK UINT32_C(0x3ff)
26923 #define CMDQ_MODIFY_ROCE_CC_TCP_CP_SFT 0
26925 #define CMDQ_MODIFY_ROCE_CC_RSVD6_MASK UINT32_C(0xfc00)
26926 #define CMDQ_MODIFY_ROCE_CC_RSVD6_SFT 10
26929 /* 0 for DCTCP , 1 for TCP */
26930 #define CMDQ_MODIFY_ROCE_CC_CC_MODE UINT32_C(0x1)
26932 #define CMDQ_MODIFY_ROCE_CC_RSVD7_MASK UINT32_C(0xfe)
26933 #define CMDQ_MODIFY_ROCE_CC_RSVD7_SFT 1
26936 /* Specifies the RoCE Tx Queue ( o to 3) to use for sending CNP packets */
26937 #define CMDQ_MODIFY_ROCE_CC_TX_QUEUE_MASK UINT32_C(0x3)
26938 #define CMDQ_MODIFY_ROCE_CC_TX_QUEUE_SFT 0
26940 #define CMDQ_MODIFY_ROCE_CC_RSVD8_MASK UINT32_C(0xfc)
26941 #define CMDQ_MODIFY_ROCE_CC_RSVD8_SFT 2
26942 uint16_t inactivity_th;
26943 /* Inactivity time after which QP CC parameters are initialized */
26944 uint64_t reserved64;
26945 uint64_t reserved64_1;
26946 } __attribute__((packed));
26948 /* Query congestion control command (16 bytes) */
26950 struct cmdq_query_roce_cc {
26952 /* Command opcode. */
26953 /* Query congestion control. */
26954 #define CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d)
26956 /* Size of the command in 16-byte units. */
26958 /* Flags and attribs of the command. */
26960 /* Driver supplied handle to associate the command and the response. */
26962 /* Size of the response buffer in 16-byte units. */
26964 uint64_t resp_addr;
26965 /* Host address of the response. */
26966 } __attribute__((packed));
26968 /* Command-Response Event Queue (CREQ) Structures */
26969 /* Description: This is an async event indicating error happened on a QP. */
26970 /* Base CREQ Record (16 bytes) */
26975 * This field indicates the exact type of the completion. By convention,
26976 * the LSB identifies the length of the record in 16B units. Even values
26977 * indicate 16B records. Odd values indicate 32B records.
26979 #define CREQ_BASE_TYPE_MASK UINT32_C(0x3f)
26980 #define CREQ_BASE_TYPE_SFT 0
26981 /* QP Async Notification */
26982 #define CREQ_BASE_TYPE_QP_EVENT UINT32_C(0x38)
26983 /* Function Async Notification */
26984 #define CREQ_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
26985 #define CREQ_BASE_RESERVED2_MASK UINT32_C(0xc0)
26986 #define CREQ_BASE_RESERVED2_SFT 6
26987 uint8_t reserved56[7];
26990 * This value is written by the NIC such that it will be different for
26991 * each pass through the completion queue. The even passes will write 1.
26992 * The odd passes will write 0.
26994 #define CREQ_BASE_V UINT32_C(0x1)
26995 #define CREQ_BASE_RESERVED7_MASK UINT32_C(0xfe)
26996 #define CREQ_BASE_RESERVED7_SFT 1
26998 /* This is the modifier on to the type field. */
26999 uint16_t reserved48[3];
27000 } __attribute__((packed));
27002 /* RoCE Function Async Event Notification (16 bytes) */
27004 struct creq_func_event {
27007 * This field indicates the exact type of the completion. By convention,
27008 * the LSB identifies the length of the record in 16B units. Even values
27009 * indicate 16B records. Odd values indicate 32B records.
27011 #define CREQ_FUNC_EVENT_TYPE_MASK UINT32_C(0x3f)
27012 #define CREQ_FUNC_EVENT_TYPE_SFT 0
27013 /* Function Async Notification */
27014 #define CREQ_FUNC_EVENT_TYPE_FUNC_EVENT UINT32_C(0x3a)
27015 #define CREQ_FUNC_EVENT_RESERVED2_MASK UINT32_C(0xc0)
27016 #define CREQ_FUNC_EVENT_RESERVED2_SFT 6
27017 uint8_t reserved56[7];
27020 * This value is written by the NIC such that it will be different for
27021 * each pass through the completion queue. The even passes will write 1.
27022 * The odd passes will write 0.
27024 #define CREQ_FUNC_EVENT_V UINT32_C(0x1)
27025 #define CREQ_FUNC_EVENT_RESERVED7_MASK UINT32_C(0xfe)
27026 #define CREQ_FUNC_EVENT_RESERVED7_SFT 1
27029 * This value defines what type of async event has occurred on the
27033 * Invalid PBL or PCIE UR response occurred in SQ WQE or IRRQ
27036 #define CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR UINT32_C(0x1)
27037 /* Invalid PBL or PCIE UR response occurred during data read access. */
27038 #define CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR UINT32_C(0x2)
27040 * Invalid PBL or PCIE UR response occurred in RQ/SRQ WQE or
27041 * ORRQ read access.
27043 #define CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR UINT32_C(0x3)
27044 /* Invalid PBL occurred during data write access. */
27045 #define CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR UINT32_C(0x4)
27046 /* Invalid PBL occurred during CQ write access. */
27047 #define CREQ_FUNC_EVENT_EVENT_CQ_ERROR UINT32_C(0x5)
27048 /* Invalid PBL or PCIE UR response occurred in TQM read access. */
27049 #define CREQ_FUNC_EVENT_EVENT_TQM_ERROR UINT32_C(0x6)
27050 /* PCIE UR response occurred in CFC read access. */
27051 #define CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR UINT32_C(0x7)
27052 /* PCIE UR response occurred in CFC read access. */
27053 #define CREQ_FUNC_EVENT_EVENT_CFCS_ERROR UINT32_C(0x8)
27054 /* PCIE UR response occurred in CFC read access. */
27055 #define CREQ_FUNC_EVENT_EVENT_CFCC_ERROR UINT32_C(0x9)
27056 /* PCIE UR response occurred in CFC read access. */
27057 #define CREQ_FUNC_EVENT_EVENT_CFCM_ERROR UINT32_C(0xa)
27058 /* Invalid PBL or PCIE UR response occurred on timer read access. */
27059 #define CREQ_FUNC_EVENT_EVENT_TIM_ERROR UINT32_C(0xb)
27060 /* A VF sent a backchannel command request */
27061 #define CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST UINT32_C(0x80)
27063 * Communication resource (QPC, CQ, SRQ, MRW) exhausted, and
27064 * resource array extension is enabled
27066 #define CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED UINT32_C(0x81)
27067 uint16_t reserved48[3];
27068 } __attribute__((packed));
27070 /* RoCE Slowpath Command Completion (16 bytes) */
27072 struct creq_qp_event {
27075 * This field indicates the exact type of the completion. By convention,
27076 * the LSB identifies the length of the record in 16B units. Even values
27077 * indicate 16B records. Odd values indicate 32B records.
27079 #define CREQ_QP_EVENT_TYPE_MASK UINT32_C(0x3f)
27080 #define CREQ_QP_EVENT_TYPE_SFT 0
27081 /* QP Async Notification */
27082 #define CREQ_QP_EVENT_TYPE_QP_EVENT UINT32_C(0x38)
27083 #define CREQ_QP_EVENT_RESERVED2_MASK UINT32_C(0xc0)
27084 #define CREQ_QP_EVENT_RESERVED2_SFT 6
27086 /* Status of the response. */
27088 #define CREQ_QP_EVENT_STATUS_SUCCESS UINT32_C(0x0)
27090 #define CREQ_QP_EVENT_STATUS_FAIL UINT32_C(0x1)
27092 #define CREQ_QP_EVENT_STATUS_RESOURCES UINT32_C(0x2)
27093 /* Invalid command. */
27094 #define CREQ_QP_EVENT_STATUS_INVALID_CMD UINT32_C(0x3)
27095 /* Not implemented. */
27096 #define CREQ_QP_EVENT_STATUS_NOT_IMPLEMENTED UINT32_C(0x4)
27097 /* Invalid parameter. */
27098 #define CREQ_QP_EVENT_STATUS_INVALID_PARAMETER UINT32_C(0x5)
27099 /* Hardware operation failed. */
27100 #define CREQ_QP_EVENT_STATUS_HARDWARE_ERROR UINT32_C(0x6)
27101 /* Firmware operation failed due to internal error. */
27102 #define CREQ_QP_EVENT_STATUS_INTERNAL_ERROR UINT32_C(0x7)
27104 /* Driver supplied handle to associate the command and the response. */
27105 uint32_t reserved32;
27108 * This value is written by the NIC such that it will be different for
27109 * each pass through the completion queue. The even passes will write 1.
27110 * The odd passes will write 0.
27112 #define CREQ_QP_EVENT_V UINT32_C(0x1)
27113 #define CREQ_QP_EVENT_RESERVED7_MASK UINT32_C(0xfe)
27114 #define CREQ_QP_EVENT_RESERVED7_SFT 1
27116 /* Event or command opcode. */
27117 /* Create QP command response. */
27118 #define CREQ_QP_EVENT_EVENT_CREATE_QP UINT32_C(0x1)
27119 /* Destroy QP command response. */
27120 #define CREQ_QP_EVENT_EVENT_DESTROY_QP UINT32_C(0x2)
27121 /* Modify QP command response. */
27122 #define CREQ_QP_EVENT_EVENT_MODIFY_QP UINT32_C(0x3)
27123 /* Query QP command response. */
27124 #define CREQ_QP_EVENT_EVENT_QUERY_QP UINT32_C(0x4)
27125 /* Create SRQ command response. */
27126 #define CREQ_QP_EVENT_EVENT_CREATE_SRQ UINT32_C(0x5)
27127 /* Destroy SRQ command response. */
27128 #define CREQ_QP_EVENT_EVENT_DESTROY_SRQ UINT32_C(0x6)
27129 /* Query SRQ command response. */
27130 #define CREQ_QP_EVENT_EVENT_QUERY_SRQ UINT32_C(0x8)
27131 /* Create CQ command response. */
27132 #define CREQ_QP_EVENT_EVENT_CREATE_CQ UINT32_C(0x9)
27133 /* Destroy CQ command response. */
27134 #define CREQ_QP_EVENT_EVENT_DESTROY_CQ UINT32_C(0xa)
27135 /* Resize CQ command response. */
27136 #define CREQ_QP_EVENT_EVENT_RESIZE_CQ UINT32_C(0xc)
27137 /* Allocate MRW command response. */
27138 #define CREQ_QP_EVENT_EVENT_ALLOCATE_MRW UINT32_C(0xd)
27139 /* De-allocate key command response. */
27140 #define CREQ_QP_EVENT_EVENT_DEALLOCATE_KEY UINT32_C(0xe)
27141 /* Register MR command response. */
27142 #define CREQ_QP_EVENT_EVENT_REGISTER_MR UINT32_C(0xf)
27143 /* Deregister MR command response. */
27144 #define CREQ_QP_EVENT_EVENT_DEREGISTER_MR UINT32_C(0x10)
27145 /* Add GID command response. */
27146 #define CREQ_QP_EVENT_EVENT_ADD_GID UINT32_C(0x11)
27147 /* Delete GID command response. */
27148 #define CREQ_QP_EVENT_EVENT_DELETE_GID UINT32_C(0x12)
27149 /* Modify GID command response. */
27150 #define CREQ_QP_EVENT_EVENT_MODIFY_GID UINT32_C(0x17)
27151 /* Query GID command response. */
27152 #define CREQ_QP_EVENT_EVENT_QUERY_GID UINT32_C(0x18)
27153 /* Create QP1 command response. */
27154 #define CREQ_QP_EVENT_EVENT_CREATE_QP1 UINT32_C(0x13)
27155 /* Destroy QP1 command response. */
27156 #define CREQ_QP_EVENT_EVENT_DESTROY_QP1 UINT32_C(0x14)
27157 /* Create AH command response. */
27158 #define CREQ_QP_EVENT_EVENT_CREATE_AH UINT32_C(0x15)
27159 /* Destroy AH command response. */
27160 #define CREQ_QP_EVENT_EVENT_DESTROY_AH UINT32_C(0x16)
27161 /* Initialize firmware command response. */
27162 #define CREQ_QP_EVENT_EVENT_INITIALIZE_FW UINT32_C(0x80)
27163 /* De-initialize firmware command response. */
27164 #define CREQ_QP_EVENT_EVENT_DEINITIALIZE_FW UINT32_C(0x81)
27165 /* Stop PF command response. */
27166 #define CREQ_QP_EVENT_EVENT_STOP_FUNC UINT32_C(0x82)
27167 /* Query info PF command response. */
27168 #define CREQ_QP_EVENT_EVENT_QUERY_FUNC UINT32_C(0x83)
27169 /* Set function resources command response. */
27170 #define CREQ_QP_EVENT_EVENT_SET_FUNC_RESOURCES UINT32_C(0x84)
27171 /* Map TC to COS response. */
27172 #define CREQ_QP_EVENT_EVENT_MAP_TC_TO_COS UINT32_C(0x8a)
27173 /* Query firmware and interface version response. */
27174 #define CREQ_QP_EVENT_EVENT_QUERY_VERSION UINT32_C(0x8b)
27175 /* Modify congestion control response. */
27176 #define CREQ_QP_EVENT_EVENT_MODIFY_ROCE_CC UINT32_C(0x8c)
27177 /* Query congestion control response. */
27178 #define CREQ_QP_EVENT_EVENT_QUERY_ROCE_CC UINT32_C(0x8d)
27179 /* QP error notification event. */
27180 #define CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION UINT32_C(0xc0)
27181 uint16_t reserved48[3];
27182 } __attribute__((packed));
27184 /* Create QP command response (16 bytes) */
27186 struct creq_create_qp_resp {
27189 * This field indicates the exact type of the completion. By convention,
27190 * the LSB identifies the length of the record in 16B units. Even values
27191 * indicate 16B records. Odd values indicate 32B records.
27193 #define CREQ_CREATE_QP_RESP_TYPE_MASK UINT32_C(0x3f)
27194 #define CREQ_CREATE_QP_RESP_TYPE_SFT 0
27195 /* QP Async Notification */
27196 #define CREQ_CREATE_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38)
27197 #define CREQ_CREATE_QP_RESP_RESERVED2_MASK UINT32_C(0xc0)
27198 #define CREQ_CREATE_QP_RESP_RESERVED2_SFT 6
27200 /* Status of the response. */
27202 /* Driver supplied handle to associate the command and the response. */
27204 /* QP context id */
27207 * This value is written by the NIC such that it will be different for
27208 * each pass through the completion queue. The even passes will write 1.
27209 * The odd passes will write 0.
27211 #define CREQ_CREATE_QP_RESP_V UINT32_C(0x1)
27212 #define CREQ_CREATE_QP_RESP_RESERVED7_MASK UINT32_C(0xfe)
27213 #define CREQ_CREATE_QP_RESP_RESERVED7_SFT 1
27215 /* Event or command opcode. */
27216 /* Create QP command response. */
27217 #define CREQ_CREATE_QP_RESP_EVENT_CREATE_QP UINT32_C(0x1)
27218 uint16_t reserved48[3];
27219 } __attribute__((packed));
27221 /* Destroy QP command response (16 bytes) */
27223 struct creq_destroy_qp_resp {
27226 * This field indicates the exact type of the completion. By convention,
27227 * the LSB identifies the length of the record in 16B units. Even values
27228 * indicate 16B records. Odd values indicate 32B records.
27230 #define CREQ_DESTROY_QP_RESP_TYPE_MASK UINT32_C(0x3f)
27231 #define CREQ_DESTROY_QP_RESP_TYPE_SFT 0
27232 /* QP Async Notification */
27233 #define CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38)
27234 #define CREQ_DESTROY_QP_RESP_RESERVED2_MASK UINT32_C(0xc0)
27235 #define CREQ_DESTROY_QP_RESP_RESERVED2_SFT 6
27237 /* Status of the response. */
27239 /* Driver supplied handle to associate the command and the response. */
27241 /* QP context id */
27244 * This value is written by the NIC such that it will be different for
27245 * each pass through the completion queue. The even passes will write 1.
27246 * The odd passes will write 0.
27248 #define CREQ_DESTROY_QP_RESP_V UINT32_C(0x1)
27249 #define CREQ_DESTROY_QP_RESP_RESERVED7_MASK UINT32_C(0xfe)
27250 #define CREQ_DESTROY_QP_RESP_RESERVED7_SFT 1
27252 /* Event or command opcode. */
27253 /* Destroy QP command response. */
27254 #define CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP UINT32_C(0x2)
27255 uint16_t reserved48[3];
27256 } __attribute__((packed));
27258 /* Modify QP command response (16 bytes) */
27260 struct creq_modify_qp_resp {
27263 * This field indicates the exact type of the completion. By convention,
27264 * the LSB identifies the length of the record in 16B units. Even values
27265 * indicate 16B records. Odd values indicate 32B records.
27267 #define CREQ_MODIFY_QP_RESP_TYPE_MASK UINT32_C(0x3f)
27268 #define CREQ_MODIFY_QP_RESP_TYPE_SFT 0
27269 /* QP Async Notification */
27270 #define CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38)
27271 #define CREQ_MODIFY_QP_RESP_RESERVED2_MASK UINT32_C(0xc0)
27272 #define CREQ_MODIFY_QP_RESP_RESERVED2_SFT 6
27274 /* Status of the response. */
27276 /* Driver supplied handle to associate the command and the response. */
27278 /* QP context id */
27281 * This value is written by the NIC such that it will be different for
27282 * each pass through the completion queue. The even passes will write 1.
27283 * The odd passes will write 0.
27285 #define CREQ_MODIFY_QP_RESP_V UINT32_C(0x1)
27286 #define CREQ_MODIFY_QP_RESP_RESERVED7_MASK UINT32_C(0xfe)
27287 #define CREQ_MODIFY_QP_RESP_RESERVED7_SFT 1
27289 /* Event or command opcode. */
27290 /* Modify QP command response. */
27291 #define CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP UINT32_C(0x3)
27292 uint16_t reserved48[3];
27293 } __attribute__((packed));
27295 /* Query QP command response (16 bytes) */
27297 struct creq_query_qp_resp {
27300 * This field indicates the exact type of the completion. By convention,
27301 * the LSB identifies the length of the record in 16B units. Even values
27302 * indicate 16B records. Odd values indicate 32B records.
27304 #define CREQ_QUERY_QP_RESP_TYPE_MASK UINT32_C(0x3f)
27305 #define CREQ_QUERY_QP_RESP_TYPE_SFT 0
27306 /* QP Async Notification */
27307 #define CREQ_QUERY_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38)
27308 #define CREQ_QUERY_QP_RESP_RESERVED2_MASK UINT32_C(0xc0)
27309 #define CREQ_QUERY_QP_RESP_RESERVED2_SFT 6
27311 /* Status of the response. */
27313 /* Driver supplied handle to associate the command and the response. */
27315 /* Side buffer size in 16-byte units */
27318 * This value is written by the NIC such that it will be different for
27319 * each pass through the completion queue. The even passes will write 1.
27320 * The odd passes will write 0.
27322 #define CREQ_QUERY_QP_RESP_V UINT32_C(0x1)
27323 #define CREQ_QUERY_QP_RESP_RESERVED7_MASK UINT32_C(0xfe)
27324 #define CREQ_QUERY_QP_RESP_RESERVED7_SFT 1
27326 /* Event or command opcode. */
27327 /* Query QP command response. */
27328 #define CREQ_QUERY_QP_RESP_EVENT_QUERY_QP UINT32_C(0x4)
27329 uint16_t reserved48[3];
27330 } __attribute__((packed));
27332 /* Query QP command response side buffer structure (104 bytes) */
27334 struct creq_query_qp_resp_sb {
27336 /* Command opcode. */
27337 /* Query QP command response. */
27338 #define CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP UINT32_C(0x4)
27340 /* Status of the response. */
27342 /* Driver supplied handle to associate the command and the response. */
27344 /* Flags and attribs of the command. */
27346 /* Size of the response buffer in 16-byte units. */
27349 /* QP context id */
27350 uint8_t en_sqd_async_notify_state;
27351 /* Enable congestion control. */
27353 #define CREQ_QUERY_QP_RESP_SB_STATE_MASK UINT32_C(0xf)
27354 #define CREQ_QUERY_QP_RESP_SB_STATE_SFT 0
27356 #define CREQ_QUERY_QP_RESP_SB_STATE_RESET UINT32_C(0x0)
27358 #define CREQ_QUERY_QP_RESP_SB_STATE_INIT UINT32_C(0x1)
27359 /* Ready To Receive. */
27360 #define CREQ_QUERY_QP_RESP_SB_STATE_RTR UINT32_C(0x2)
27361 /* Ready To Send. */
27362 #define CREQ_QUERY_QP_RESP_SB_STATE_RTS UINT32_C(0x3)
27364 #define CREQ_QUERY_QP_RESP_SB_STATE_SQD UINT32_C(0x4)
27366 #define CREQ_QUERY_QP_RESP_SB_STATE_SQE UINT32_C(0x5)
27368 #define CREQ_QUERY_QP_RESP_SB_STATE_ERR UINT32_C(0x6)
27369 /* SQ drain asynchronous notification. */
27370 #define CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY UINT32_C(0x10)
27371 /* Enable congestion control. */
27373 /* Access flags. */
27374 /* Local write access. */
27375 #define CREQ_QUERY_QP_RESP_SB_ACCESS_LOCAL_WRITE UINT32_C(0x1)
27376 /* Remote write access. */
27377 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_WRITE UINT32_C(0x2)
27378 /* Remote read access. */
27379 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_READ UINT32_C(0x4)
27380 /* Remote atomic access. */
27381 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC UINT32_C(0x8)
27386 uint32_t reserved32;
27388 /* Destination GID. */
27389 uint32_t flow_label;
27391 uint16_t sgid_index;
27392 /* Source GID index. */
27395 uint8_t traffic_class;
27396 /* Traffic class. */
27397 uint16_t dest_mac[3];
27398 /* Destination MAC address. */
27399 uint16_t path_mtu_dest_vlan_id;
27401 /* Destination VLAN ID. */
27402 #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_MASK UINT32_C(0xfff)
27403 #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_SFT 0
27405 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK UINT32_C(0xf000)
27406 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_SFT 12
27408 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_256 (UINT32_C(0x0) << 12)
27410 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_512 (UINT32_C(0x1) << 12)
27412 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_1024 (UINT32_C(0x2) << 12)
27414 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_2048 (UINT32_C(0x3) << 12)
27416 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_4096 (UINT32_C(0x4) << 12)
27418 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 (UINT32_C(0x5) << 12)
27420 /* Timeout value for SWQEs. */
27422 /* Max retry count for WQEs. */
27424 /* Max RNR retry count for WQEs. */
27425 uint8_t min_rnr_timer;
27426 /* Min RNR timer that the QP will report to the remote. */
27428 /* RQ start packet sequence number. */
27430 /* SQ start packet sequence number. */
27431 uint8_t max_rd_atomic;
27432 /* Max outstanding RDMA read atomic. */
27433 uint8_t max_dest_rd_atomic;
27434 /* Max destination outstanding RDMA read atomic. */
27435 uint8_t tos_dscp_tos_ecn;
27438 #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_MASK UINT32_C(0x3)
27439 #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_SFT 0
27441 #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_MASK UINT32_C(0xfc)
27442 #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_SFT 2
27444 /* enable_cc is 1 b */
27445 #define CREQ_QUERY_QP_RESP_SB_ENABLE_CC UINT32_C(0x1)
27446 #define CREQ_QUERY_QP_RESP_SB_RESERVED7_MASK UINT32_C(0xfe)
27447 #define CREQ_QUERY_QP_RESP_SB_RESERVED7_SFT 1
27449 /* Max send WQE. */
27451 /* Max recv WQE. */
27453 /* Max send SGEs per SWQE. */
27455 /* Max recv SGEs per RWQE (NOT SUPPORTED BY HARDWARE). */
27456 uint32_t max_inline_data;
27457 /* Max inline data length (upto 120 bytes). */
27458 uint32_t dest_qp_id;
27459 /* Destination QP id. */
27461 uint16_t src_mac[3];
27463 uint16_t vlan_pcp_vlan_dei_vlan_id;
27464 /* VLAN PCP field - Priority Code Point. */
27465 /* Source VLAN id. */
27466 #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK UINT32_C(0xfff)
27467 #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT 0
27468 /* VLAN DEI field - Drop Eligibility Indicator. */
27469 #define CREQ_QUERY_QP_RESP_SB_VLAN_DEI UINT32_C(0x1000)
27470 /* VLAN PCP field - Priority Code Point. */
27471 #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_MASK UINT32_C(0xe000)
27472 #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_SFT 13
27473 } __attribute__((packed));
27475 /* Create SRQ command response (16 bytes) */
27477 struct creq_create_srq_resp {
27480 * This field indicates the exact type of the completion. By convention,
27481 * the LSB identifies the length of the record in 16B units. Even values
27482 * indicate 16B records. Odd values indicate 32B records.
27484 #define CREQ_CREATE_SRQ_RESP_TYPE_MASK UINT32_C(0x3f)
27485 #define CREQ_CREATE_SRQ_RESP_TYPE_SFT 0
27486 /* QP Async Notification */
27487 #define CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
27488 #define CREQ_CREATE_SRQ_RESP_RESERVED2_MASK UINT32_C(0xc0)
27489 #define CREQ_CREATE_SRQ_RESP_RESERVED2_SFT 6
27491 /* Status of the response. */
27493 /* Driver supplied handle to associate the command and the response. */
27495 /* SRQ context id */
27498 * This value is written by the NIC such that it will be different for
27499 * each pass through the completion queue. The even passes will write 1.
27500 * The odd passes will write 0.
27502 #define CREQ_CREATE_SRQ_RESP_V UINT32_C(0x1)
27503 #define CREQ_CREATE_SRQ_RESP_RESERVED7_MASK UINT32_C(0xfe)
27504 #define CREQ_CREATE_SRQ_RESP_RESERVED7_SFT 1
27506 /* Event or command opcode. */
27507 /* Create SRQ command response. */
27508 #define CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ UINT32_C(0x5)
27509 uint16_t reserved48[3];
27510 } __attribute__((packed));
27512 /* Destroy SRQ command response (16 bytes) */
27514 struct creq_destroy_srq_resp {
27517 * This field indicates the exact type of the completion. By convention,
27518 * the LSB identifies the length of the record in 16B units. Even values
27519 * indicate 16B records. Odd values indicate 32B records.
27521 #define CREQ_DESTROY_SRQ_RESP_TYPE_MASK UINT32_C(0x3f)
27522 #define CREQ_DESTROY_SRQ_RESP_TYPE_SFT 0
27523 /* QP Async Notification */
27524 #define CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
27525 #define CREQ_DESTROY_SRQ_RESP_RESERVED2_MASK UINT32_C(0xc0)
27526 #define CREQ_DESTROY_SRQ_RESP_RESERVED2_SFT 6
27528 /* Status of the response. */
27530 /* Driver supplied handle to associate the command and the response. */
27532 /* SRQ context id */
27535 * This value is written by the NIC such that it will be different for
27536 * each pass through the completion queue. The even passes will write 1.
27537 * The odd passes will write 0.
27539 #define CREQ_DESTROY_SRQ_RESP_V UINT32_C(0x1)
27540 #define CREQ_DESTROY_SRQ_RESP_RESERVED7_MASK UINT32_C(0xfe)
27541 #define CREQ_DESTROY_SRQ_RESP_RESERVED7_SFT 1
27543 /* Event or command opcode. */
27544 /* Destroy SRQ command response. */
27545 #define CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ UINT32_C(0x6)
27546 uint16_t enable_for_arm[3];
27547 /* Set to 1 if this SRQ is allowed to be armed for threshold async event */
27548 #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK UINT32_C(0x30000)
27549 #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_SFT 16
27550 #define CREQ_DESTROY_SRQ_RESP_RESERVED46_MASK UINT32_C(0xfffc0000)
27551 #define CREQ_DESTROY_SRQ_RESP_RESERVED46_SFT 18
27552 } __attribute__((packed));
27554 /* Query SRQ command response (16 bytes) */
27556 struct creq_query_srq_resp {
27559 * This field indicates the exact type of the completion. By convention,
27560 * the LSB identifies the length of the record in 16B units. Even values
27561 * indicate 16B records. Odd values indicate 32B records.
27563 #define CREQ_QUERY_SRQ_RESP_TYPE_MASK UINT32_C(0x3f)
27564 #define CREQ_QUERY_SRQ_RESP_TYPE_SFT 0
27565 /* QP Async Notification */
27566 #define CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
27567 #define CREQ_QUERY_SRQ_RESP_RESERVED2_MASK UINT32_C(0xc0)
27568 #define CREQ_QUERY_SRQ_RESP_RESERVED2_SFT 6
27570 /* Status of the response. */
27572 /* Driver supplied handle to associate the command and the response. */
27574 /* Side buffer size in 16-byte units */
27577 * This value is written by the NIC such that it will be different for
27578 * each pass through the completion queue. The even passes will write 1.
27579 * The odd passes will write 0.
27581 #define CREQ_QUERY_SRQ_RESP_V UINT32_C(0x1)
27582 #define CREQ_QUERY_SRQ_RESP_RESERVED7_MASK UINT32_C(0xfe)
27583 #define CREQ_QUERY_SRQ_RESP_RESERVED7_SFT 1
27585 /* Event or command opcode. */
27586 /* Query SRQ command response. */
27587 #define CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ UINT32_C(0x8)
27588 uint16_t reserved48[3];
27589 } __attribute__((packed));
27591 /* Query SRQ command response side buffer structure (24 bytes) */
27593 struct creq_query_srq_resp_sb {
27595 /* Command opcode. */
27596 /* Query SRQ command response. */
27597 #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ UINT32_C(0x8)
27599 /* Status of the response. */
27601 /* Driver supplied handle to associate the command and the response. */
27603 /* Flags and attribs of the command. */
27605 /* Size of the response buffer in 16-byte units. */
27608 /* SRQ context id */
27609 uint16_t srq_limit;
27610 /* Watermark value to generate a SRQ limit event. */
27611 uint16_t reserved16;
27613 /* data is 128 b */
27614 } __attribute__((packed));
27616 /* Create CQ command Response (16 bytes) */
27618 struct creq_create_cq_resp {
27621 * This field indicates the exact type of the completion. By convention,
27622 * the LSB identifies the length of the record in 16B units. Even values
27623 * indicate 16B records. Odd values indicate 32B records.
27625 #define CREQ_CREATE_CQ_RESP_TYPE_MASK UINT32_C(0x3f)
27626 #define CREQ_CREATE_CQ_RESP_TYPE_SFT 0
27627 /* QP Async Notification */
27628 #define CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
27629 #define CREQ_CREATE_CQ_RESP_RESERVED2_MASK UINT32_C(0xc0)
27630 #define CREQ_CREATE_CQ_RESP_RESERVED2_SFT 6
27632 /* Status of the response. */
27634 /* Driver supplied handle to associate the command and the response. */
27636 /* CQ context id */
27639 * This value is written by the NIC such that it will be different for
27640 * each pass through the completion queue. The even passes will write 1.
27641 * The odd passes will write 0.
27643 #define CREQ_CREATE_CQ_RESP_V UINT32_C(0x1)
27644 #define CREQ_CREATE_CQ_RESP_RESERVED7_MASK UINT32_C(0xfe)
27645 #define CREQ_CREATE_CQ_RESP_RESERVED7_SFT 1
27647 /* Event or command opcode. */
27648 /* Create CQ command response. */
27649 #define CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ UINT32_C(0x9)
27650 uint16_t reserved48[3];
27651 } __attribute__((packed));
27653 /* Destroy CQ command response (16 bytes) */
27655 struct creq_destroy_cq_resp {
27658 * This field indicates the exact type of the completion. By convention,
27659 * the LSB identifies the length of the record in 16B units. Even values
27660 * indicate 16B records. Odd values indicate 32B records.
27662 #define CREQ_DESTROY_CQ_RESP_TYPE_MASK UINT32_C(0x3f)
27663 #define CREQ_DESTROY_CQ_RESP_TYPE_SFT 0
27664 /* QP Async Notification */
27665 #define CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
27666 #define CREQ_DESTROY_CQ_RESP_RESERVED2_MASK UINT32_C(0xc0)
27667 #define CREQ_DESTROY_CQ_RESP_RESERVED2_SFT 6
27669 /* Status of the response. */
27671 /* Driver supplied handle to associate the command and the response. */
27673 /* CQ context id */
27676 * This value is written by the NIC such that it will be different for
27677 * each pass through the completion queue. The even passes will write 1.
27678 * The odd passes will write 0.
27680 #define CREQ_DESTROY_CQ_RESP_V UINT32_C(0x1)
27681 #define CREQ_DESTROY_CQ_RESP_RESERVED7_MASK UINT32_C(0xfe)
27682 #define CREQ_DESTROY_CQ_RESP_RESERVED7_SFT 1
27684 /* Event or command opcode. */
27685 /* Destroy CQ command response. */
27686 #define CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ UINT32_C(0xa)
27687 uint16_t cq_arm_lvl;
27689 * CQ ARM Level: 0 ? Not Armed 1 ? Arm SE Only, Generate CNQE only for
27690 * incoming Solicted Events 2 ? Arm all, Generate CNQE for Rx and Tx
27692 #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK UINT32_C(0x3)
27693 #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_SFT 0
27694 #define CREQ_DESTROY_CQ_RESP_RESERVED14_MASK UINT32_C(0xfffc)
27695 #define CREQ_DESTROY_CQ_RESP_RESERVED14_SFT 2
27696 uint16_t total_cnq_events;
27698 * The total number of CNQ events for the CQ, incremented on each CNQ
27699 * event for the CQ (including firmware-generated CQ error
27702 uint16_t reserved16;
27703 } __attribute__((packed));
27705 /* Resize CQ command response (16 bytes) */
27707 struct creq_resize_cq_resp {
27710 * This field indicates the exact type of the completion. By convention,
27711 * the LSB identifies the length of the record in 16B units. Even values
27712 * indicate 16B records. Odd values indicate 32B records.
27714 #define CREQ_RESIZE_CQ_RESP_TYPE_MASK UINT32_C(0x3f)
27715 #define CREQ_RESIZE_CQ_RESP_TYPE_SFT 0
27716 /* QP Async Notification */
27717 #define CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
27718 #define CREQ_RESIZE_CQ_RESP_RESERVED2_MASK UINT32_C(0xc0)
27719 #define CREQ_RESIZE_CQ_RESP_RESERVED2_SFT 6
27721 /* Status of the response. */
27723 /* Driver supplied handle to associate the command and the response. */
27725 /* CQ context id */
27728 * This value is written by the NIC such that it will be different for
27729 * each pass through the completion queue. The even passes will write 1.
27730 * The odd passes will write 0.
27732 #define CREQ_RESIZE_CQ_RESP_V UINT32_C(0x1)
27733 #define CREQ_RESIZE_CQ_RESP_RESERVED7_MASK UINT32_C(0xfe)
27734 #define CREQ_RESIZE_CQ_RESP_RESERVED7_SFT 1
27736 /* Event or command opcode. */
27737 /* Resize CQ command response. */
27738 #define CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ UINT32_C(0xc)
27739 uint16_t reserved48[3];
27740 } __attribute__((packed));
27742 /* Allocate MRW command response (16 bytes) */
27744 struct creq_allocate_mrw_resp {
27747 * This field indicates the exact type of the completion. By convention,
27748 * the LSB identifies the length of the record in 16B units. Even values
27749 * indicate 16B records. Odd values indicate 32B records.
27751 #define CREQ_ALLOCATE_MRW_RESP_TYPE_MASK UINT32_C(0x3f)
27752 #define CREQ_ALLOCATE_MRW_RESP_TYPE_SFT 0
27753 /* QP Async Notification */
27754 #define CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT UINT32_C(0x38)
27755 #define CREQ_ALLOCATE_MRW_RESP_RESERVED2_MASK UINT32_C(0xc0)
27756 #define CREQ_ALLOCATE_MRW_RESP_RESERVED2_SFT 6
27758 /* Status of the response. */
27760 /* Driver supplied handle to associate the command and the response. */
27762 /* L_KEY for MR, R_KEY for MW */
27765 * This value is written by the NIC such that it will be different for
27766 * each pass through the completion queue. The even passes will write 1.
27767 * The odd passes will write 0.
27769 #define CREQ_ALLOCATE_MRW_RESP_V UINT32_C(0x1)
27770 #define CREQ_ALLOCATE_MRW_RESP_RESERVED7_MASK UINT32_C(0xfe)
27771 #define CREQ_ALLOCATE_MRW_RESP_RESERVED7_SFT 1
27773 /* Event or command opcode. */
27774 /* Allocate MRW command response. */
27775 #define CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW UINT32_C(0xd)
27776 uint16_t reserved48[3];
27777 } __attribute__((packed));
27779 /* De-allocate key command response (16 bytes) */
27781 struct creq_deallocate_key_resp {
27784 * This field indicates the exact type of the completion. By convention,
27785 * the LSB identifies the length of the record in 16B units. Even values
27786 * indicate 16B records. Odd values indicate 32B records.
27788 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_MASK UINT32_C(0x3f)
27789 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_SFT 0
27790 /* QP Async Notification */
27791 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT UINT32_C(0x38)
27792 #define CREQ_DEALLOCATE_KEY_RESP_RESERVED2_MASK UINT32_C(0xc0)
27793 #define CREQ_DEALLOCATE_KEY_RESP_RESERVED2_SFT 6
27795 /* Status of the response. */
27797 /* Driver supplied handle to associate the command and the response. */
27799 /* L_KEY for MR, R_KEY for MW */
27802 * This value is written by the NIC such that it will be different for
27803 * each pass through the completion queue. The even passes will write 1.
27804 * The odd passes will write 0.
27806 #define CREQ_DEALLOCATE_KEY_RESP_V UINT32_C(0x1)
27807 #define CREQ_DEALLOCATE_KEY_RESP_RESERVED7_MASK UINT32_C(0xfe)
27808 #define CREQ_DEALLOCATE_KEY_RESP_RESERVED7_SFT 1
27810 /* Event or command opcode. */
27811 /* De-allocate key command response. */
27812 #define CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY UINT32_C(0xe)
27813 uint16_t reserved16;
27814 uint32_t bound_window_info;
27816 * This is advisory data to facilitate eventual descruction of lingering
27817 * memory regions in Windows. For memory window, it contains non-zero
27818 * HWID of a region this window was bound to (without the 8-bit key
27819 * portion). The host may check if the region is lingering in destroyed
27820 * state and try to destroy it now. For memory region, if deallocation
27821 * fails because there are windows bound to this region, this field will
27822 * contain approximate number of those windows. This number is read from
27823 * the context right before the deregistration is attempted and can
27824 * potentially be slightly different from the current number.
27826 } __attribute__((packed));
27828 /* Register MR command response (16 bytes) */
27830 struct creq_register_mr_resp {
27833 * This field indicates the exact type of the completion. By convention,
27834 * the LSB identifies the length of the record in 16B units. Even values
27835 * indicate 16B records. Odd values indicate 32B records.
27837 #define CREQ_REGISTER_MR_RESP_TYPE_MASK UINT32_C(0x3f)
27838 #define CREQ_REGISTER_MR_RESP_TYPE_SFT 0
27839 /* QP Async Notification */
27840 #define CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT UINT32_C(0x38)
27841 #define CREQ_REGISTER_MR_RESP_RESERVED2_MASK UINT32_C(0xc0)
27842 #define CREQ_REGISTER_MR_RESP_RESERVED2_SFT 6
27844 /* Status of the response. */
27846 /* Driver supplied handle to associate the command and the response. */
27851 * This value is written by the NIC such that it will be different for
27852 * each pass through the completion queue. The even passes will write 1.
27853 * The odd passes will write 0.
27855 #define CREQ_REGISTER_MR_RESP_V UINT32_C(0x1)
27856 #define CREQ_REGISTER_MR_RESP_RESERVED7_MASK UINT32_C(0xfe)
27857 #define CREQ_REGISTER_MR_RESP_RESERVED7_SFT 1
27859 /* Event or command opcode. */
27860 /* Register MR command response. */
27861 #define CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR UINT32_C(0xf)
27862 uint16_t reserved48[3];
27863 } __attribute__((packed));
27865 /* Deregister MR command response (16 bytes) */
27867 struct creq_deregister_mr_resp {
27870 * This field indicates the exact type of the completion. By convention,
27871 * the LSB identifies the length of the record in 16B units. Even values
27872 * indicate 16B records. Odd values indicate 32B records.
27874 #define CREQ_DEREGISTER_MR_RESP_TYPE_MASK UINT32_C(0x3f)
27875 #define CREQ_DEREGISTER_MR_RESP_TYPE_SFT 0
27876 /* QP Async Notification */
27877 #define CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT UINT32_C(0x38)
27878 #define CREQ_DEREGISTER_MR_RESP_RESERVED2_MASK UINT32_C(0xc0)
27879 #define CREQ_DEREGISTER_MR_RESP_RESERVED2_SFT 6
27881 /* Status of the response. */
27883 /* Driver supplied handle to associate the command and the response. */
27888 * This value is written by the NIC such that it will be different for
27889 * each pass through the completion queue. The even passes will write 1.
27890 * The odd passes will write 0.
27892 #define CREQ_DEREGISTER_MR_RESP_V UINT32_C(0x1)
27893 #define CREQ_DEREGISTER_MR_RESP_RESERVED7_MASK UINT32_C(0xfe)
27894 #define CREQ_DEREGISTER_MR_RESP_RESERVED7_SFT 1
27896 /* Event or command opcode. */
27897 /* Deregister MR command response. */
27898 #define CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR UINT32_C(0x10)
27899 uint16_t reserved16;
27900 uint32_t bound_windows;
27902 * If deregister fails because there are windows bound to this region,
27903 * this field will contain approximate number of those windows. This
27904 * number is read from the context right before the deregistration is
27905 * attempted and can potentially be slightly different from the current
27908 } __attribute__((packed));
27910 /* Add GID command response (16 bytes) */
27912 struct creq_add_gid_resp {
27915 * This field indicates the exact type of the completion. By convention,
27916 * the LSB identifies the length of the record in 16B units. Even values
27917 * indicate 16B records. Odd values indicate 32B records.
27919 #define CREQ_ADD_GID_RESP_TYPE_MASK UINT32_C(0x3f)
27920 #define CREQ_ADD_GID_RESP_TYPE_SFT 0
27921 /* QP Async Notification */
27922 #define CREQ_ADD_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38)
27923 #define CREQ_ADD_GID_RESP_RESERVED2_MASK UINT32_C(0xc0)
27924 #define CREQ_ADD_GID_RESP_RESERVED2_SFT 6
27926 /* Status of the response. */
27928 /* Driver supplied handle to associate the command and the response. */
27933 * This value is written by the NIC such that it will be different for
27934 * each pass through the completion queue. The even passes will write 1.
27935 * The odd passes will write 0.
27937 #define CREQ_ADD_GID_RESP_V UINT32_C(0x1)
27938 #define CREQ_ADD_GID_RESP_RESERVED7_MASK UINT32_C(0xfe)
27939 #define CREQ_ADD_GID_RESP_RESERVED7_SFT 1
27941 /* Event or command opcode. */
27942 /* Add GID command response. */
27943 #define CREQ_ADD_GID_RESP_EVENT_ADD_GID UINT32_C(0x11)
27944 uint16_t reserved48[3];
27945 } __attribute__((packed));
27947 /* Delete GID command response (16 bytes) */
27949 struct creq_delete_gid_resp {
27952 * This field indicates the exact type of the completion. By convention,
27953 * the LSB identifies the length of the record in 16B units. Even values
27954 * indicate 16B records. Odd values indicate 32B records.
27956 #define CREQ_DELETE_GID_RESP_TYPE_MASK UINT32_C(0x3f)
27957 #define CREQ_DELETE_GID_RESP_TYPE_SFT 0
27958 /* QP Async Notification */
27959 #define CREQ_DELETE_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38)
27960 #define CREQ_DELETE_GID_RESP_RESERVED2_MASK UINT32_C(0xc0)
27961 #define CREQ_DELETE_GID_RESP_RESERVED2_SFT 6
27963 /* Status of the response. */
27965 /* Driver supplied handle to associate the command and the response. */
27970 * This value is written by the NIC such that it will be different for
27971 * each pass through the completion queue. The even passes will write 1.
27972 * The odd passes will write 0.
27974 #define CREQ_DELETE_GID_RESP_V UINT32_C(0x1)
27975 #define CREQ_DELETE_GID_RESP_RESERVED7_MASK UINT32_C(0xfe)
27976 #define CREQ_DELETE_GID_RESP_RESERVED7_SFT 1
27978 /* Event or command opcode. */
27979 /* Delete GID command response. */
27980 #define CREQ_DELETE_GID_RESP_EVENT_DELETE_GID UINT32_C(0x12)
27981 uint16_t reserved48[3];
27982 } __attribute__((packed));
27984 /* Modify GID command response (16 bytes) */
27986 struct creq_modify_gid_resp {
27989 * This field indicates the exact type of the completion. By convention,
27990 * the LSB identifies the length of the record in 16B units. Even values
27991 * indicate 16B records. Odd values indicate 32B records.
27993 #define CREQ_MODIFY_GID_RESP_TYPE_MASK UINT32_C(0x3f)
27994 #define CREQ_MODIFY_GID_RESP_TYPE_SFT 0
27995 /* QP Async Notification */
27996 #define CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38)
27997 #define CREQ_MODIFY_GID_RESP_RESERVED2_MASK UINT32_C(0xc0)
27998 #define CREQ_MODIFY_GID_RESP_RESERVED2_SFT 6
28000 /* Status of the response. */
28002 /* Driver supplied handle to associate the command and the response. */
28007 * This value is written by the NIC such that it will be different for
28008 * each pass through the completion queue. The even passes will write 1.
28009 * The odd passes will write 0.
28011 #define CREQ_MODIFY_GID_RESP_V UINT32_C(0x1)
28012 #define CREQ_MODIFY_GID_RESP_RESERVED7_MASK UINT32_C(0xfe)
28013 #define CREQ_MODIFY_GID_RESP_RESERVED7_SFT 1
28015 /* Event or command opcode. */
28016 /* Add GID command response. */
28017 #define CREQ_MODIFY_GID_RESP_EVENT_ADD_GID UINT32_C(0x11)
28018 uint16_t reserved48[3];
28019 } __attribute__((packed));
28021 /* Query GID command response (16 bytes) */
28023 struct creq_query_gid_resp {
28026 * This field indicates the exact type of the completion. By convention,
28027 * the LSB identifies the length of the record in 16B units. Even values
28028 * indicate 16B records. Odd values indicate 32B records.
28030 #define CREQ_QUERY_GID_RESP_TYPE_MASK UINT32_C(0x3f)
28031 #define CREQ_QUERY_GID_RESP_TYPE_SFT 0
28032 /* QP Async Notification */
28033 #define CREQ_QUERY_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38)
28034 #define CREQ_QUERY_GID_RESP_RESERVED2_MASK UINT32_C(0xc0)
28035 #define CREQ_QUERY_GID_RESP_RESERVED2_SFT 6
28037 /* Status of the response. */
28039 /* Driver supplied handle to associate the command and the response. */
28041 /* Side buffer size in 16-byte units */
28044 * This value is written by the NIC such that it will be different for
28045 * each pass through the completion queue. The even passes will write 1.
28046 * The odd passes will write 0.
28048 #define CREQ_QUERY_GID_RESP_V UINT32_C(0x1)
28049 #define CREQ_QUERY_GID_RESP_RESERVED7_MASK UINT32_C(0xfe)
28050 #define CREQ_QUERY_GID_RESP_RESERVED7_SFT 1
28052 /* Event or command opcode. */
28053 /* Query GID command response. */
28054 #define CREQ_QUERY_GID_RESP_EVENT_QUERY_GID UINT32_C(0x18)
28055 uint16_t reserved48[3];
28056 } __attribute__((packed));
28058 /* Query GID command response side buffer structure (40 bytes) */
28060 struct creq_query_gid_resp_sb {
28062 /* Command opcode. */
28063 /* Query GID command response. */
28064 #define CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID UINT32_C(0x18)
28066 /* Status of the response. */
28068 /* Driver supplied handle to associate the command and the response. */
28070 /* Flags and attribs of the command. */
28072 /* Size of the response buffer in 16-byte units. */
28076 uint16_t src_mac[3];
28080 /* Source VLAN id. */
28081 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_MASK UINT32_C(0xfff)
28082 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_SFT 0
28083 /* This set of bits select the TPID of the VLAN Tag. */
28084 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_MASK UINT32_C(0x7000)
28085 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_SFT 12
28086 /* TPID = 0x88A8. */
28087 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_88A8 (UINT32_C(0x0) << 12)
28088 /* TPID = 0x8100. */
28089 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_8100 (UINT32_C(0x1) << 12)
28090 /* TPID = 0x9100. */
28091 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9100 (UINT32_C(0x2) << 12)
28092 /* TPID = 0x9200. */
28093 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9200 (UINT32_C(0x3) << 12)
28094 /* TPID = 0x9300. */
28095 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9300 (UINT32_C(0x4) << 12)
28096 /* TPID = Configurable 1. */
28097 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG1 (UINT32_C(0x5) << 12)
28098 /* TPID = Configurable 2. */
28099 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG2 (UINT32_C(0x6) << 12)
28100 /* TPID = Configurable 3. */
28101 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 (UINT32_C(0x7) << 12)
28102 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_LAST CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3
28104 * Setting this bit to 1 enables insertion of a VLAN Tag to a RoCE
28107 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN UINT32_C(0x8000)
28109 /* Identifier field in the IP header. */
28110 uint16_t gid_index;
28113 } __attribute__((packed));
28115 /* Create QP1 command response (16 bytes) */
28117 struct creq_create_qp1_resp {
28120 * This field indicates the exact type of the completion. By convention,
28121 * the LSB identifies the length of the record in 16B units. Even values
28122 * indicate 16B records. Odd values indicate 32B records.
28124 #define CREQ_CREATE_QP1_RESP_TYPE_MASK UINT32_C(0x3f)
28125 #define CREQ_CREATE_QP1_RESP_TYPE_SFT 0
28126 /* QP Async Notification */
28127 #define CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT UINT32_C(0x38)
28128 #define CREQ_CREATE_QP1_RESP_RESERVED2_MASK UINT32_C(0xc0)
28129 #define CREQ_CREATE_QP1_RESP_RESERVED2_SFT 6
28131 /* Status of the response. */
28133 /* Driver supplied handle to associate the command and the response. */
28135 /* QP1 context id */
28138 * This value is written by the NIC such that it will be different for
28139 * each pass through the completion queue. The even passes will write 1.
28140 * The odd passes will write 0.
28142 #define CREQ_CREATE_QP1_RESP_V UINT32_C(0x1)
28143 #define CREQ_CREATE_QP1_RESP_RESERVED7_MASK UINT32_C(0xfe)
28144 #define CREQ_CREATE_QP1_RESP_RESERVED7_SFT 1
28146 /* Event or command opcode. */
28147 /* Create QP1 command response. */
28148 #define CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 UINT32_C(0x13)
28149 uint16_t reserved48[3];
28150 } __attribute__((packed));
28152 /* Destroy QP1 command response (16 bytes) */
28154 struct creq_destroy_qp1_resp {
28157 * This field indicates the exact type of the completion. By convention,
28158 * the LSB identifies the length of the record in 16B units. Even values
28159 * indicate 16B records. Odd values indicate 32B records.
28161 #define CREQ_DESTROY_QP1_RESP_TYPE_MASK UINT32_C(0x3f)
28162 #define CREQ_DESTROY_QP1_RESP_TYPE_SFT 0
28163 /* QP Async Notification */
28164 #define CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT UINT32_C(0x38)
28165 #define CREQ_DESTROY_QP1_RESP_RESERVED2_MASK UINT32_C(0xc0)
28166 #define CREQ_DESTROY_QP1_RESP_RESERVED2_SFT 6
28168 /* Status of the response. */
28170 /* Driver supplied handle to associate the command and the response. */
28172 /* QP1 context id */
28175 * This value is written by the NIC such that it will be different for
28176 * each pass through the completion queue. The even passes will write 1.
28177 * The odd passes will write 0.
28179 #define CREQ_DESTROY_QP1_RESP_V UINT32_C(0x1)
28180 #define CREQ_DESTROY_QP1_RESP_RESERVED7_MASK UINT32_C(0xfe)
28181 #define CREQ_DESTROY_QP1_RESP_RESERVED7_SFT 1
28183 /* Event or command opcode. */
28184 /* Destroy QP1 command response. */
28185 #define CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 UINT32_C(0x14)
28186 uint16_t reserved48[3];
28187 } __attribute__((packed));
28189 /* Create AH command response (16 bytes) */
28191 struct creq_create_ah_resp {
28194 * This field indicates the exact type of the completion. By convention,
28195 * the LSB identifies the length of the record in 16B units. Even values
28196 * indicate 16B records. Odd values indicate 32B records.
28198 #define CREQ_CREATE_AH_RESP_TYPE_MASK UINT32_C(0x3f)
28199 #define CREQ_CREATE_AH_RESP_TYPE_SFT 0
28200 /* QP Async Notification */
28201 #define CREQ_CREATE_AH_RESP_TYPE_QP_EVENT UINT32_C(0x38)
28202 #define CREQ_CREATE_AH_RESP_RESERVED2_MASK UINT32_C(0xc0)
28203 #define CREQ_CREATE_AH_RESP_RESERVED2_SFT 6
28205 /* Status of the response. */
28207 /* Driver supplied handle to associate the command and the response. */
28209 /* AH context id */
28212 * This value is written by the NIC such that it will be different for
28213 * each pass through the completion queue. The even passes will write 1.
28214 * The odd passes will write 0.
28216 #define CREQ_CREATE_AH_RESP_V UINT32_C(0x1)
28217 #define CREQ_CREATE_AH_RESP_RESERVED7_MASK UINT32_C(0xfe)
28218 #define CREQ_CREATE_AH_RESP_RESERVED7_SFT 1
28220 /* Event or command opcode. */
28221 /* Create AH command response. */
28222 #define CREQ_CREATE_AH_RESP_EVENT_CREATE_AH UINT32_C(0x15)
28223 uint16_t reserved48[3];
28224 } __attribute__((packed));
28226 /* Destroy AH command response (16 bytes) */
28228 struct creq_destroy_ah_resp {
28231 * This field indicates the exact type of the completion. By convention,
28232 * the LSB identifies the length of the record in 16B units. Even values
28233 * indicate 16B records. Odd values indicate 32B records.
28235 #define CREQ_DESTROY_AH_RESP_TYPE_MASK UINT32_C(0x3f)
28236 #define CREQ_DESTROY_AH_RESP_TYPE_SFT 0
28237 /* QP Async Notification */
28238 #define CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT UINT32_C(0x38)
28239 #define CREQ_DESTROY_AH_RESP_RESERVED2_MASK UINT32_C(0xc0)
28240 #define CREQ_DESTROY_AH_RESP_RESERVED2_SFT 6
28242 /* Status of the response. */
28244 /* Driver supplied handle to associate the command and the response. */
28246 /* AH context id */
28249 * This value is written by the NIC such that it will be different for
28250 * each pass through the completion queue. The even passes will write 1.
28251 * The odd passes will write 0.
28253 #define CREQ_DESTROY_AH_RESP_V UINT32_C(0x1)
28254 #define CREQ_DESTROY_AH_RESP_RESERVED7_MASK UINT32_C(0xfe)
28255 #define CREQ_DESTROY_AH_RESP_RESERVED7_SFT 1
28257 /* Event or command opcode. */
28258 /* Destroy AH command response. */
28259 #define CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH UINT32_C(0x16)
28260 uint16_t reserved48[3];
28261 } __attribute__((packed));
28263 /* Initialize Firmware command response (16 bytes) */
28265 struct creq_initialize_fw_resp {
28268 * This field indicates the exact type of the completion. By convention,
28269 * the LSB identifies the length of the record in 16B units. Even values
28270 * indicate 16B records. Odd values indicate 32B records.
28272 #define CREQ_INITIALIZE_FW_RESP_TYPE_MASK UINT32_C(0x3f)
28273 #define CREQ_INITIALIZE_FW_RESP_TYPE_SFT 0
28274 /* QP Async Notification */
28275 #define CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT UINT32_C(0x38)
28276 #define CREQ_INITIALIZE_FW_RESP_RESERVED2_MASK UINT32_C(0xc0)
28277 #define CREQ_INITIALIZE_FW_RESP_RESERVED2_SFT 6
28279 /* Status of the response. */
28281 /* Driver supplied handle to associate the command and the response. */
28282 uint32_t reserved32;
28285 * This value is written by the NIC such that it will be different for
28286 * each pass through the completion queue. The even passes will write 1.
28287 * The odd passes will write 0.
28289 #define CREQ_INITIALIZE_FW_RESP_V UINT32_C(0x1)
28290 #define CREQ_INITIALIZE_FW_RESP_RESERVED7_MASK UINT32_C(0xfe)
28291 #define CREQ_INITIALIZE_FW_RESP_RESERVED7_SFT 1
28293 /* Event or command opcode. */
28294 /* Initialize firmware command response. */
28295 #define CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW UINT32_C(0x80)
28296 uint16_t reserved48[3];
28297 } __attribute__((packed));
28299 /* De-initialize Firmware command response (16 bytes) */
28301 struct creq_deinitialize_fw_resp {
28304 * This field indicates the exact type of the completion. By convention,
28305 * the LSB identifies the length of the record in 16B units. Even values
28306 * indicate 16B records. Odd values indicate 32B records.
28308 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_MASK UINT32_C(0x3f)
28309 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_SFT 0
28310 /* QP Async Notification */
28311 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT UINT32_C(0x38)
28312 #define CREQ_DEINITIALIZE_FW_RESP_RESERVED2_MASK UINT32_C(0xc0)
28313 #define CREQ_DEINITIALIZE_FW_RESP_RESERVED2_SFT 6
28315 /* Status of the response. */
28317 /* Driver supplied handle to associate the command and the response. */
28318 uint32_t reserved32;
28321 * This value is written by the NIC such that it will be different for
28322 * each pass through the completion queue. The even passes will write 1.
28323 * The odd passes will write 0.
28325 #define CREQ_DEINITIALIZE_FW_RESP_V UINT32_C(0x1)
28326 #define CREQ_DEINITIALIZE_FW_RESP_RESERVED7_MASK UINT32_C(0xfe)
28327 #define CREQ_DEINITIALIZE_FW_RESP_RESERVED7_SFT 1
28329 /* Event or command opcode. */
28330 /* De-initialize firmware command response. */
28331 #define CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW UINT32_C(0x81)
28332 uint16_t reserved48[3];
28333 } __attribute__((packed));
28335 /* Stop function command response (16 bytes) */
28337 struct creq_stop_func_resp {
28340 * This field indicates the exact type of the completion. By convention,
28341 * the LSB identifies the length of the record in 16B units. Even values
28342 * indicate 16B records. Odd values indicate 32B records.
28344 #define CREQ_STOP_FUNC_RESP_TYPE_MASK UINT32_C(0x3f)
28345 #define CREQ_STOP_FUNC_RESP_TYPE_SFT 0
28346 /* QP Async Notification */
28347 #define CREQ_STOP_FUNC_RESP_TYPE_QP_EVENT UINT32_C(0x38)
28348 #define CREQ_STOP_FUNC_RESP_RESERVED2_MASK UINT32_C(0xc0)
28349 #define CREQ_STOP_FUNC_RESP_RESERVED2_SFT 6
28351 /* Status of the response. */
28353 /* Driver supplied handle to associate the command and the response. */
28354 uint32_t reserved32;
28357 * This value is written by the NIC such that it will be different for
28358 * each pass through the completion queue. The even passes will write 1.
28359 * The odd passes will write 0.
28361 #define CREQ_STOP_FUNC_RESP_V UINT32_C(0x1)
28362 #define CREQ_STOP_FUNC_RESP_RESERVED7_MASK UINT32_C(0xfe)
28363 #define CREQ_STOP_FUNC_RESP_RESERVED7_SFT 1
28365 /* Event or command opcode. */
28366 /* Stop PF command response. */
28367 #define CREQ_STOP_FUNC_RESP_EVENT_STOP_FUNC UINT32_C(0x82)
28368 uint16_t reserved48[3];
28369 } __attribute__((packed));
28371 /* Query function command response (16 bytes) */
28373 struct creq_query_func_resp {
28376 * This field indicates the exact type of the completion. By convention,
28377 * the LSB identifies the length of the record in 16B units. Even values
28378 * indicate 16B records. Odd values indicate 32B records.
28380 #define CREQ_QUERY_FUNC_RESP_TYPE_MASK UINT32_C(0x3f)
28381 #define CREQ_QUERY_FUNC_RESP_TYPE_SFT 0
28382 /* QP Async Notification */
28383 #define CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT UINT32_C(0x38)
28384 #define CREQ_QUERY_FUNC_RESP_RESERVED2_MASK UINT32_C(0xc0)
28385 #define CREQ_QUERY_FUNC_RESP_RESERVED2_SFT 6
28387 /* Status of the response. */
28389 /* Driver supplied handle to associate the command and the response. */
28391 /* Side buffer size in 16-byte units */
28394 * This value is written by the NIC such that it will be different for
28395 * each pass through the completion queue. The even passes will write 1.
28396 * The odd passes will write 0.
28398 #define CREQ_QUERY_FUNC_RESP_V UINT32_C(0x1)
28399 #define CREQ_QUERY_FUNC_RESP_RESERVED7_MASK UINT32_C(0xfe)
28400 #define CREQ_QUERY_FUNC_RESP_RESERVED7_SFT 1
28402 /* Event or command opcode. */
28403 /* Query info PF command response. */
28404 #define CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC UINT32_C(0x83)
28405 uint16_t reserved48[3];
28406 } __attribute__((packed));
28408 /* Query function command response side buffer structure (88 bytes) */
28410 struct creq_query_func_resp_sb {
28412 /* Command opcode. */
28413 /* Query info PF command response. */
28414 #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC UINT32_C(0x83)
28416 /* Status of the response. */
28418 /* Driver supplied handle to associate the command and the response. */
28420 /* Flags and attribs of the command. */
28422 /* Size of the response buffer in 16-byte units. */
28424 uint64_t max_mr_size;
28425 /* Max MR size supported. */
28427 /* Max QP supported. */
28428 uint16_t max_qp_wr;
28429 /* Max WQEs per QP. */
28430 uint16_t dev_cap_flags;
28431 /* Device capability flags. */
28432 /* Allow QP resizing. */
28433 #define CREQ_QUERY_FUNC_RESP_SB_DEV_CAP_FLAGS_RESIZE_QP UINT32_C(0x1)
28435 /* Max CQs supported. */
28437 /* Max CQEs per CQ supported. */
28439 /* Max PDs supported. */
28441 /* Max SGEs per QP WQE supported. */
28442 uint8_t max_srq_sge;
28443 /* Max SGEs per SRQ WQE supported. */
28444 uint8_t max_qp_rd_atom;
28445 /* Max outstanding RDMA read & atomic supported. */
28446 uint8_t max_qp_init_rd_atom;
28448 * Max outstanding RDMA read & atomic that can be sent from an
28452 /* Max MRs supported. */
28454 /* Max MWs supported. */
28455 uint32_t max_raw_eth_qp;
28456 /* Max Raw Ethertype QPs supported. */
28458 /* Max AHs supported. */
28460 /* Max FMRs supported. */
28461 uint32_t max_srq_wr;
28462 /* Max WQEs per SRQ supported. */
28463 uint32_t max_pkeys;
28464 /* Max PKEYs supported. */
28465 uint32_t max_inline_data;
28466 /* Max inline data supported. */
28467 uint8_t max_map_per_fmr;
28468 /* Max mappings per FMR supported. */
28469 uint8_t l2_db_space_size;
28470 /* L2 DB space size in pages. */
28472 /* Max SRQs supported. */
28474 /* Max GIDs supported. */
28475 uint32_t tqm_alloc_reqs[12];
28477 * An array of 48 8-bit values to specify allocation multiplier for TQM
28478 * host buffer regions. Each region occupies 16 MB of TQM PBL address
28479 * space: 0x00000000, 0x01000000, 0x02000000, etc. The host needs to
28480 * allocate (<Number of QPs>*multiplier, rounded up to page size) of
28481 * physical memory for non-zero slots and map the pages to the
28482 * corresponding 16MB regions. Typically there are total 3 non-zero
28483 * values in this array, their values are 16, 16, 12. Cu+ will only
28484 * populate up to index 11. SR may populate up to index 47.
28486 } __attribute__((packed));
28488 /* Set resources command response (16 bytes) */
28490 struct creq_set_func_resources_resp {
28493 * This field indicates the exact type of the completion. By convention,
28494 * the LSB identifies the length of the record in 16B units. Even values
28495 * indicate 16B records. Odd values indicate 32B records.
28497 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_MASK UINT32_C(0x3f)
28498 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_SFT 0
28499 /* QP Async Notification */
28500 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT UINT32_C(0x38)
28501 #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED2_MASK UINT32_C(0xc0)
28502 #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED2_SFT 6
28504 /* Status of the response. */
28506 /* Driver supplied handle to associate the command and the response. */
28507 uint32_t reserved32;
28510 * This value is written by the NIC such that it will be different for
28511 * each pass through the completion queue. The even passes will write 1.
28512 * The odd passes will write 0.
28514 #define CREQ_SET_FUNC_RESOURCES_RESP_V UINT32_C(0x1)
28515 #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED7_MASK UINT32_C(0xfe)
28516 #define CREQ_SET_FUNC_RESOURCES_RESP_RESERVED7_SFT 1
28518 /* Event or command opcode. */
28519 /* Set function resources command response. */
28520 #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES UINT32_C(0x84)
28521 uint16_t reserved48[3];
28522 } __attribute__((packed));
28524 /* Map TC to COS response (16 bytes) */
28526 struct creq_map_tc_to_cos_resp {
28529 * This field indicates the exact type of the completion. By convention,
28530 * the LSB identifies the length of the record in 16B units. Even values
28531 * indicate 16B records. Odd values indicate 32B records.
28533 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_MASK UINT32_C(0x3f)
28534 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_SFT 0
28535 /* QP Async Notification */
28536 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT UINT32_C(0x38)
28537 #define CREQ_MAP_TC_TO_COS_RESP_RESERVED2_MASK UINT32_C(0xc0)
28538 #define CREQ_MAP_TC_TO_COS_RESP_RESERVED2_SFT 6
28540 /* Status of the response. */
28542 /* Driver supplied handle to associate the command and the response. */
28543 uint32_t reserved32;
28546 * This value is written by the NIC such that it will be different for
28547 * each pass through the completion queue. The even passes will write 1.
28548 * The odd passes will write 0.
28550 #define CREQ_MAP_TC_TO_COS_RESP_V UINT32_C(0x1)
28551 #define CREQ_MAP_TC_TO_COS_RESP_RESERVED7_MASK UINT32_C(0xfe)
28552 #define CREQ_MAP_TC_TO_COS_RESP_RESERVED7_SFT 1
28554 /* Event or command opcode. */
28555 /* Map TC to COS response. */
28556 #define CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS UINT32_C(0x8a)
28557 uint16_t reserved48[3];
28558 } __attribute__((packed));
28560 /* Query version response (16 bytes) */
28562 struct creq_query_version_resp {
28565 * This field indicates the exact type of the completion. By convention,
28566 * the LSB identifies the length of the record in 16B units. Even values
28567 * indicate 16B records. Odd values indicate 32B records.
28569 #define CREQ_QUERY_VERSION_RESP_TYPE_MASK UINT32_C(0x3f)
28570 #define CREQ_QUERY_VERSION_RESP_TYPE_SFT 0
28571 /* QP Async Notification */
28572 #define CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT UINT32_C(0x38)
28573 #define CREQ_QUERY_VERSION_RESP_RESERVED2_MASK UINT32_C(0xc0)
28574 #define CREQ_QUERY_VERSION_RESP_RESERVED2_SFT 6
28576 /* Status of the response. */
28578 /* Driver supplied handle to associate the command and the response. */
28580 /* firmware major version */
28582 /* firmware minor version */
28584 /* firmware build version */
28586 /* firmware reserved version */
28589 * This value is written by the NIC such that it will be different for
28590 * each pass through the completion queue. The even passes will write 1.
28591 * The odd passes will write 0.
28593 #define CREQ_QUERY_VERSION_RESP_V UINT32_C(0x1)
28594 #define CREQ_QUERY_VERSION_RESP_RESERVED7_MASK UINT32_C(0xfe)
28595 #define CREQ_QUERY_VERSION_RESP_RESERVED7_SFT 1
28597 /* Event or command opcode. */
28598 /* Query firmware and interface version response. */
28599 #define CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION UINT32_C(0x8b)
28600 uint16_t reserved16;
28602 /* interface major version */
28603 uint8_t intf_minor;
28604 /* interface minor version */
28606 /* interface build version */
28608 /* interface reserved version */
28609 } __attribute__((packed));
28611 /* Modify congestion control command response (16 bytes) */
28613 struct creq_modify_roce_cc_resp {
28616 * This field indicates the exact type of the completion. By convention,
28617 * the LSB identifies the length of the record in 16B units. Even values
28618 * indicate 16B records. Odd values indicate 32B records.
28620 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_MASK UINT32_C(0x3f)
28621 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_SFT 0
28622 /* QP Async Notification */
28623 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT UINT32_C(0x38)
28624 #define CREQ_MODIFY_ROCE_CC_RESP_RESERVED2_MASK UINT32_C(0xc0)
28625 #define CREQ_MODIFY_ROCE_CC_RESP_RESERVED2_SFT 6
28627 /* Status of the response. */
28629 /* Driver supplied handle to associate the command and the response. */
28630 uint32_t reserved32;
28633 * This value is written by the NIC such that it will be different for
28634 * each pass through the completion queue. The even passes will write 1.
28635 * The odd passes will write 0.
28637 #define CREQ_MODIFY_ROCE_CC_RESP_V UINT32_C(0x1)
28638 #define CREQ_MODIFY_ROCE_CC_RESP_RESERVED7_MASK UINT32_C(0xfe)
28639 #define CREQ_MODIFY_ROCE_CC_RESP_RESERVED7_SFT 1
28641 /* Event or command opcode. */
28642 /* Modify congestion control response. */
28643 #define CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC UINT32_C(0x8c)
28644 uint16_t reserved48[3];
28645 } __attribute__((packed));
28647 /* Query congestion control command response (16 bytes) */
28649 struct creq_query_roce_cc_resp {
28652 * This field indicates the exact type of the completion. By convention,
28653 * the LSB identifies the length of the record in 16B units. Even values
28654 * indicate 16B records. Odd values indicate 32B records.
28656 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_MASK UINT32_C(0x3f)
28657 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_SFT 0
28658 /* QP Async Notification */
28659 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT UINT32_C(0x38)
28660 #define CREQ_QUERY_ROCE_CC_RESP_RESERVED2_MASK UINT32_C(0xc0)
28661 #define CREQ_QUERY_ROCE_CC_RESP_RESERVED2_SFT 6
28663 /* Status of the response. */
28665 /* Driver supplied handle to associate the command and the response. */
28667 /* Side buffer size in 16-byte units */
28670 * This value is written by the NIC such that it will be different for
28671 * each pass through the completion queue. The even passes will write 1.
28672 * The odd passes will write 0.
28674 #define CREQ_QUERY_ROCE_CC_RESP_V UINT32_C(0x1)
28675 #define CREQ_QUERY_ROCE_CC_RESP_RESERVED7_MASK UINT32_C(0xfe)
28676 #define CREQ_QUERY_ROCE_CC_RESP_RESERVED7_SFT 1
28678 /* Event or command opcode. */
28679 /* Query congestion control response. */
28680 #define CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC UINT32_C(0x8d)
28681 uint16_t reserved48[3];
28682 } __attribute__((packed));
28684 /* Query congestion control command response side buffer structure (32 bytes) */
28686 struct creq_query_roce_cc_resp_sb {
28688 /* Command opcode. */
28689 /* Query congestion control response. */
28690 #define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d)
28692 /* Status of the response. */
28694 /* Driver supplied handle to associate the command and the response. */
28696 /* Flags and attribs of the command. */
28698 /* Size of the response buffer in 16-byte units. */
28701 /* unused7 is 7 b */
28703 #define CREQ_QUERY_ROCE_CC_RESP_SB_ENABLE_CC UINT32_C(0x1)
28704 /* unused7 is 7 b */
28705 uint8_t tos_dscp_tos_ecn;
28708 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_MASK UINT32_C(0x3)
28709 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_SFT 0
28711 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_MASK UINT32_C(0xfc)
28712 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_SFT 2
28714 /* unused5 is 5 b */
28715 /* Congestion Probability averaging factor. */
28716 #define CREQ_QUERY_ROCE_CC_RESP_SB_G_MASK UINT32_C(0x7)
28717 #define CREQ_QUERY_ROCE_CC_RESP_SB_G_SFT 0
28718 /* unused5 is 5 b */
28719 uint8_t num_phases_per_state;
28720 /* Number of phases in Fast Recovery and Active Increase. */
28722 /* The starting value of rate. */
28724 /* The starting value of target rate. */
28725 uint8_t alt_vlan_pcp;
28727 /* Alternate vlan pcp value for CNP packets. */
28728 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_MASK UINT32_C(0x7)
28729 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_SFT 0
28731 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_MASK UINT32_C(0xf8)
28732 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_SFT 3
28733 uint8_t alt_tos_dscp;
28735 /* Alternate IP TOS DSCP. */
28736 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_MASK UINT32_C(0x3f)
28737 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_SFT 0
28739 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_MASK UINT32_C(0xc0)
28740 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_SFT 6
28743 /* 0 for DCTCP , 1 for TCP */
28744 #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE UINT32_C(0x1)
28746 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD2_MASK UINT32_C(0xfe)
28747 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD2_SFT 1
28750 /* Specifies the RoCE Tx Queue ( o to 3) to use for sending CNP packets */
28751 #define CREQ_QUERY_ROCE_CC_RESP_SB_TX_QUEUE_MASK UINT32_C(0x3)
28752 #define CREQ_QUERY_ROCE_CC_RESP_SB_TX_QUEUE_SFT 0
28754 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD3_MASK UINT32_C(0xfc)
28755 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD3_SFT 2
28758 /* Round trip time in units of usecs */
28759 #define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_MASK UINT32_C(0x3fff)
28760 #define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_SFT 0
28762 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_MASK UINT32_C(0xc000)
28763 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_SFT 14
28766 /* The value used as CP when cc_mode is 1(TCP) */
28767 #define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_MASK UINT32_C(0x3ff)
28768 #define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_SFT 0
28770 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_MASK UINT32_C(0xfc00)
28771 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_SFT 10
28772 uint16_t inactivity_th;
28773 /* Inactivity time after which QP CC parameters are initialized */
28774 uint16_t reserved16;
28775 uint32_t reserved32;
28776 } __attribute__((packed));
28778 /* QP error notification event (16 bytes) */
28780 struct creq_qp_error_notification {
28783 * This field indicates the exact type of the completion. By convention,
28784 * the LSB identifies the length of the record in 16B units. Even values
28785 * indicate 16B records. Odd values indicate 32B records.
28787 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_MASK UINT32_C(0x3f)
28788 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_SFT 0
28789 /* QP Async Notification */
28790 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT UINT32_C(0x38)
28791 #define CREQ_QP_ERROR_NOTIFICATION_RESERVED2_MASK UINT32_C(0xc0)
28792 #define CREQ_QP_ERROR_NOTIFICATION_RESERVED2_SFT 6
28794 /* Status of the response. */
28795 uint8_t req_slow_path_state;
28796 /* requestor slow path state */
28797 uint8_t req_err_state_reason;
28798 /* requestor error reason */
28800 /* QP context id */
28803 * This value is written by the NIC such that it will be different for
28804 * each pass through the completion queue. The even passes will write 1.
28805 * The odd passes will write 0.
28807 #define CREQ_QP_ERROR_NOTIFICATION_V UINT32_C(0x1)
28808 #define CREQ_QP_ERROR_NOTIFICATION_RESERVED7_MASK UINT32_C(0xfe)
28809 #define CREQ_QP_ERROR_NOTIFICATION_RESERVED7_SFT 1
28811 /* Event or command opcode. */
28812 /* QP error notification event. */
28813 #define CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION UINT32_C(0xc0)
28814 uint8_t res_slow_path_state;
28815 /* responder slow path state */
28816 uint8_t res_err_state_reason;
28817 uint16_t sq_cons_idx;
28819 * Final SQ Consumer Index value. Any additional SQ WQEs will have to be
28820 * completed by the user provider.
28822 uint16_t rq_cons_idx;
28824 * Final RQ Consumer Index value. Any additional RQ WQEs will have to be
28825 * completed by the user provider.
28827 } __attribute__((packed));
28829 /* RoCE Slowpath Data Structures */
28831 * Note: This section documents the Host Structures used between software and
28832 * RoCE control firmware.
28834 /* hwrm_selftest_qlist */
28836 * Description: This function is called by a driver to determine which selftests
28837 * are available to be run against the requested function.
28839 /* Input (16 bytes) */
28841 struct hwrm_selftest_qlist_input {
28844 * This value indicates what type of request this is. The format for the
28845 * rest of the command is determined by this field.
28847 uint16_t cmpl_ring;
28849 * This value indicates the what completion ring the request will be
28850 * optionally completed on. If the value is -1, then no CR completion
28851 * will be generated. Any other value must be a valid CR ring_id value
28852 * for this function.
28855 /* This value indicates the command sequence number. */
28856 uint16_t target_id;
28858 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
28859 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
28861 uint64_t resp_addr;
28863 * This is the host address where the response will be written when the
28864 * request is complete. This area must be 16B aligned and must be
28865 * cleared to zero before the request is made.
28867 } __attribute__((packed));
28869 /* Output (272 bytes) */
28871 struct hwrm_selftest_qlist_output {
28872 uint16_t error_code;
28874 * Pass/Fail or error type Note: receiver to verify the in parameters,
28875 * and fail the call with an error when appropriate
28878 /* This field returns the type of original request. */
28880 /* This field provides original sequence number of the command. */
28883 * This field is the length of the response in bytes. The last byte of
28884 * the response is a valid flag that will read as '1' when the command
28885 * has been completely written to memory.
28889 * This field represents the number of tests available to be requested
28892 uint8_t available_tests;
28893 /* This field indicates which self-test is available to be run. */
28894 /* Can run the NVM test. */
28895 #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_NVM_TEST UINT32_C(0x1)
28896 /* Can run the link test. */
28897 #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_LINK_TEST UINT32_C(0x2)
28898 /* Can run the register test. */
28899 #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_REGISTER_TEST UINT32_C(0x4)
28900 /* Can run the memory test. */
28901 #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_MEMORY_TEST UINT32_C(0x8)
28902 /* Can run the PCIe serdes test. */
28903 #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_PCIE_SERDES_TEST UINT32_C(0x10)
28904 /* Can run the Ethernet serdes test. */
28905 #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_ETHERNET_SERDES_TEST UINT32_C(0x20)
28906 uint8_t offline_tests;
28907 /* The NVM test is an offline test. */
28908 #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_NVM_TEST UINT32_C(0x1)
28909 /* The link test is an offline test. */
28910 #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_LINK_TEST UINT32_C(0x2)
28911 /* The register test is an offline test. */
28912 #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_REGISTER_TEST UINT32_C(0x4)
28913 /* The memory test is an offline test. */
28914 #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_MEMORY_TEST UINT32_C(0x8)
28915 /* The PCIe serdes test is an offline test. */
28916 #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_PCIE_SERDES_TEST UINT32_C(0x10)
28917 /* The Ethernet serdes test is an offline test. */
28918 #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_ETHERNET_SERDES_TEST UINT32_C(0x20)
28920 uint16_t test_timeout;
28922 * This field represents the the maximum timeout for all the tests to
28923 * complete in milliseconds.
28927 char test0_name[32];
28929 * This field represents the name of the NVM test (ASCII chars with NULL
28932 char test1_name[32];
28934 * This field represents the name of the link test (ASCII chars with
28935 * NULL at the end).
28937 char test2_name[32];
28939 * This field represents the name of the register test (ASCII chars with
28940 * NULL at the end).
28942 char test3_name[32];
28944 * This field represents the name of the memory test (ASCII chars with
28945 * NULL at the end).
28947 char test4_name[32];
28949 * This field represents the name of the PCIe serdes test (ASCII chars
28950 * with NULL at the end).
28952 char test5_name[32];
28954 * This field represents the name of the Ethernet serdes test (ASCII
28955 * chars with NULL at the end).
28957 char test6_name[32];
28959 * This field represents the name of some future test (ASCII chars with
28960 * NULL at the end).
28962 char test7_name[32];
28964 * This field represents the name of some future test (ASCII chars with
28965 * NULL at the end).
28967 } __attribute__((packed));
28969 /* hwrm_selftest_exec */
28971 * Description: This function is called by a driver to request which self tests
28974 /* Input (24 bytes) */
28976 struct hwrm_selftest_exec_input {
28979 * This value indicates what type of request this is. The format for the
28980 * rest of the command is determined by this field.
28982 uint16_t cmpl_ring;
28984 * This value indicates the what completion ring the request will be
28985 * optionally completed on. If the value is -1, then no CR completion
28986 * will be generated. Any other value must be a valid CR ring_id value
28987 * for this function.
28990 /* This value indicates the command sequence number. */
28991 uint16_t target_id;
28993 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
28994 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
28996 uint64_t resp_addr;
28998 * This is the host address where the response will be written when the
28999 * request is complete. This area must be 16B aligned and must be
29000 * cleared to zero before the request is made.
29003 /* This field indicates which self-test is being requested to run. */
29004 /* Run the NVM test. */
29005 #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_NVM_TEST UINT32_C(0x1)
29006 /* Run the link test. */
29007 #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_LINK_TEST UINT32_C(0x2)
29008 /* Run the register test. */
29009 #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_REGISTER_TEST UINT32_C(0x4)
29010 /* Run the memory test. */
29011 #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_MEMORY_TEST UINT32_C(0x8)
29012 /* Run the PCIe serdes test. */
29013 #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_PCIE_SERDES_TEST UINT32_C(0x10)
29014 /* Run the Ethernet serdes test. */
29015 #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_ETHERNET_SERDES_TEST UINT32_C(0x20)
29016 uint8_t unused_0[7];
29017 } __attribute__((packed));
29019 /* Output (16 bytes) */
29021 struct hwrm_selftest_exec_output {
29022 uint16_t error_code;
29024 * Pass/Fail or error type Note: receiver to verify the in parameters,
29025 * and fail the call with an error when appropriate
29028 /* This field returns the type of original request. */
29030 /* This field provides original sequence number of the command. */
29033 * This field is the length of the response in bytes. The last byte of
29034 * the response is a valid flag that will read as '1' when the command
29035 * has been completely written to memory.
29037 uint8_t requested_tests;
29038 /* The following tests were requested to be run. */
29039 /* A reqeust was made to run the NVM test. */
29040 #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_NVM_TEST UINT32_C(0x1)
29041 /* A request was made to run the link test. */
29042 #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_LINK_TEST UINT32_C(0x2)
29043 /* A request was made to run the register test. */
29044 #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_REGISTER_TEST UINT32_C(0x4)
29045 /* A request was made to run the memory test. */
29046 #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_MEMORY_TEST UINT32_C(0x8)
29047 /* A request was made to run the PCIe serdes test. */
29048 #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_PCIE_SERDES_TEST UINT32_C(0x10)
29049 /* A request was made to run the Ethernet serdes test. */
29050 #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_ETHERNET_SERDES_TEST UINT32_C(0x20)
29051 uint8_t test_success;
29053 * If a test was requested to be run as seen in the requested_tests
29054 * field, this bit indicates whether the test was successful(1) or
29058 * If requested, a value of 1 indicates the NVM test completed
29061 #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_NVM_TEST UINT32_C(0x1)
29063 * If requested, a value of 1 indicates the link test completed
29066 #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_LINK_TEST UINT32_C(0x2)
29068 * If requested, a value of 1 indicates the register test completed
29071 #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_REGISTER_TEST UINT32_C(0x4)
29073 * If requested, a value of 1 indicates the memory test completed
29076 #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_MEMORY_TEST UINT32_C(0x8)
29078 * If requested, a value of 1 indicates the PCIe serdes test completed
29081 #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_PCIE_SERDES_TEST UINT32_C(0x10)
29083 * If requested, a value of 1 indicates the Ethernet serdes test
29084 * completed successfully.
29086 #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_ETHERNET_SERDES_TEST UINT32_C(0x20)
29087 uint16_t unused_0[3];
29088 } __attribute__((packed));
29090 /* hwrm_selftest_irq */
29092 * Description: This function is called by a driver to request the interrupt
29093 * test be run. In response to this request the interrupt associated with the
29094 * completion ring specified in the cmpl_ring field will be asserted to the
29097 /* Input (16 bytes) */
29099 struct hwrm_selftest_irq_input {
29102 * This value indicates what type of request this is. The format for the
29103 * rest of the command is determined by this field.
29105 uint16_t cmpl_ring;
29107 * This value indicates the what completion ring the request will be
29108 * optionally completed on. If the value is -1, then no CR completion
29109 * will be generated. Any other value must be a valid CR ring_id value
29110 * for this function.
29113 /* This value indicates the command sequence number. */
29114 uint16_t target_id;
29116 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
29117 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
29119 uint64_t resp_addr;
29121 * This is the host address where the response will be written when the
29122 * request is complete. This area must be 16B aligned and must be
29123 * cleared to zero before the request is made.
29125 } __attribute__((packed));
29127 /* Output (8 bytes) */
29129 struct hwrm_selftest_irq_output {
29130 uint16_t error_code;
29132 * Pass/Fail or error type Note: receiver to verify the in parameters,
29133 * and fail the call with an error when appropriate
29136 /* This field returns the type of original request. */
29138 /* This field provides original sequence number of the command. */
29141 * This field is the length of the response in bytes. The last byte of
29142 * the response is a valid flag that will read as '1' when the command
29143 * has been completely written to memory.
29145 } __attribute__((packed));
29147 /* hwrm_selftest_retreive_serdes_data */
29149 * Description: This function is called by a driver to retreieve the data
29150 * collected when running the previous PCIe or Ethernet serdes test. The driver
29151 * can use multiple calls to this command to retreive the entire stored buffer
29152 * in the event it cannot do so with a single call.
29154 /* Input (32 bytes) */
29156 struct hwrm_selftest_retreive_serdes_data_input {
29159 * This value indicates what type of request this is. The format for the
29160 * rest of the command is determined by this field.
29162 uint16_t cmpl_ring;
29164 * This value indicates the what completion ring the request will be
29165 * optionally completed on. If the value is -1, then no CR completion
29166 * will be generated. Any other value must be a valid CR ring_id value
29167 * for this function.
29170 /* This value indicates the command sequence number. */
29171 uint16_t target_id;
29173 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
29174 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
29176 uint64_t resp_addr;
29178 * This is the host address where the response will be written when the
29179 * request is complete. This area must be 16B aligned and must be
29180 * cleared to zero before the request is made.
29182 uint64_t resp_data_addr;
29183 /* Host address data is to DMA'd to. */
29184 uint32_t resp_data_offset;
29186 * This field contains the offset into the captured data to begin
29187 * copying the data to the host from. This should be set to 0 on the
29188 * initial call to this command.
29192 * Size of the buffer pointed to by resp_data_addr. The firmware may use
29193 * this entire buffer or less than the entire buffer, but never more.
29197 * This field allows this command to request the individual serdes tests
29198 * to be run using this command.
29201 #define HWRM_SELFTEST_RETREIVE_SERDES_DATA_INPUT_FLAGS_UNUSED_TEST_MASK UINT32_C(0xf)
29202 #define HWRM_SELFTEST_RETREIVE_SERDES_DATA_INPUT_FLAGS_UNUSED_TEST_SFT 0
29203 /* Run the PCIe serdes test. */
29204 #define HWRM_SELFTEST_RETREIVE_SERDES_DATA_INPUT_FLAGS_PCIE_SERDES_TEST UINT32_C(0x10)
29205 /* Run the Ethernet serdes test. */
29206 #define HWRM_SELFTEST_RETREIVE_SERDES_DATA_INPUT_FLAGS_ETHERNET_SERDES_TEST UINT32_C(0x20)
29208 } __attribute__((packed));
29210 /* Output (16 bytes) */
29212 struct hwrm_selftest_retreive_serdes_data_output {
29213 uint16_t error_code;
29215 * Pass/Fail or error type Note: receiver to verify the in parameters,
29216 * and fail the call with an error when appropriate
29219 /* This field returns the type of original request. */
29221 /* This field provides original sequence number of the command. */
29224 * This field is the length of the response in bytes. The last byte of
29225 * the response is a valid flag that will read as '1' when the command
29226 * has been completely written to memory.
29228 uint16_t total_data_len;
29229 /* Total length of stored data. */
29230 uint16_t copied_data_len;
29232 * Amount of data DMA'd to host by this call. The driver can use this
29233 * field along with the total_data_len field above to determine the
29234 * value to write to the resp_data_offset field in the next call if more
29235 * than one call to these commands is required to retreive all the
29239 } __attribute__((packed));
29241 /* Hardware Resource Manager Specification */
29242 /* Description: This structure is used to configure a RSS Context. */
29244 * Note: The Hardware Resource Manager (HWRM) manages various hardware resources
29245 * inside the chip. The HWRM is implemented in firmware, and runs on embedded
29246 * processors inside the chip. This firmware service is vital part of the chip.
29247 * The chip can not be used by a driver or HWRM client without the HWRM.
29249 /* Input (16 bytes) */
29254 * This value indicates what type of request this is. The format for the
29255 * rest of the command is determined by this field.
29257 uint16_t cmpl_ring;
29259 * This value indicates the what completion ring the request will be
29260 * optionally completed on. If the value is -1, then no CR completion
29261 * will be generated. Any other value must be a valid CR ring_id value
29262 * for this function.
29265 /* This value indicates the command sequence number. */
29266 uint16_t target_id;
29268 * Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
29269 * 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
29271 uint64_t resp_addr;
29273 * This is the host address where the response will be written when the
29274 * request is complete. This area must be 16B aligned and must be
29275 * cleared to zero before the request is made.
29277 } __attribute__((packed));
29279 /* Output (8 bytes) */
29282 uint16_t error_code;
29284 * Pass/Fail or error type Note: receiver to verify the in parameters,
29285 * and fail the call with an error when appropriate
29288 /* This field returns the type of original request. */
29290 /* This field provides original sequence number of the command. */
29293 * This field is the length of the response in bytes. The last byte of
29294 * the response is a valid flag that will read as '1' when the command
29295 * has been completely written to memory.
29297 } __attribute__((packed));
29299 /* Short Command Structure (16 bytes) */
29301 struct hwrm_short_input {
29304 * This field indicates the type of request in the request buffer. The
29305 * format for the rest of the command (request) is determined by this
29308 uint16_t signature;
29310 * This field indicates a signature that is used to identify short form
29311 * of the command listed here. This field shall be set to 17185
29314 /* Signature indicating this is a short form of HWRM command */
29315 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
29317 /* Reserved for future use. */
29319 /* This value indicates the length of the request. */
29322 * This is the host address where the request was written. This area
29323 * must be 16B aligned.
29325 } __attribute__((packed));
29327 #define GET_HWRM_REQ_TYPE(x) \
29328 ((x) == 0x99 ? "HWRM_CFA_NTUPLE_FILTER_ALLOC": \
29329 ((x) == 0x90 ? "HWRM_CFA_L2_FILTER_ALLOC": \
29330 ((x) == 0x91 ? "HWRM_CFA_L2_FILTER_FREE": \
29331 ((x) == 0x92 ? "HWRM_CFA_L2_FILTER_CFG": \
29332 ((x) == 0x93 ? "HWRM_CFA_L2_SET_RX_MASK": \
29333 ((x) == 0x94 ? "HWRM_CFA_VLAN_ANTISPOOF_CFG": \
29334 ((x) == 0x95 ? "HWRM_CFA_TUNNEL_FILTER_ALLOC": \
29335 ((x) == 0x96 ? "HWRM_CFA_TUNNEL_FILTER_FREE": \
29336 ((x) == 0x10 ? "RESERVED1": \
29337 ((x) == 0x11 ? "HWRM_FUNC_RESET": \
29338 ((x) == 0x12 ? "HWRM_FUNC_GETFID": \
29339 ((x) == 0x13 ? "HWRM_FUNC_VF_ALLOC": \
29340 ((x) == 0x14 ? "HWRM_FUNC_VF_FREE": \
29341 ((x) == 0x15 ? "HWRM_FUNC_QCAPS": \
29342 ((x) == 0x16 ? "HWRM_FUNC_QCFG": \
29343 ((x) == 0x17 ? "HWRM_FUNC_CFG": \
29344 ((x) == 0x18 ? "HWRM_FUNC_QSTATS": \
29345 ((x) == 0x19 ? "HWRM_FUNC_CLR_STATS": \
29346 ((x) == 0xe0 ? "HWRM_TEMP_MONITOR_QUERY": \
29347 ((x) == 0x1a ? "HWRM_FUNC_DRV_UNRGTR": \
29348 ((x) == 0x1b ? "HWRM_FUNC_VF_RESC_FREE": \
29349 ((x) == 0x1c ? "HWRM_FUNC_VF_VNIC_IDS_QUERY": \
29350 ((x) == 0x1d ? "HWRM_FUNC_DRV_RGTR": \
29351 ((x) == 0x1e ? "HWRM_FUNC_DRV_QVER": \
29352 ((x) == 0x1f ? "HWRM_FUNC_BUF_RGTR": \
29353 ((x) == 0x9a ? "HWRM_CFA_NTUPLE_FILTER_FREE": \
29354 ((x) == 0x9b ? "HWRM_CFA_NTUPLE_FILTER_CFG": \
29355 ((x) == 0xd3 ? "HWRM_FWD_ASYNC_EVENT_CMPL": \
29356 ((x) == 0xd2 ? "HWRM_FWD_RESP": \
29357 ((x) == 0xd1 ? "HWRM_REJECT_FWD_RESP": \
29358 ((x) == 0xd0 ? "HWRM_EXEC_FWD_RESP": \
29359 ((x) == 0xc0 ? "HWRM_FW_RESET": \
29360 ((x) == 0xc1 ? "HWRM_FW_QSTATUS": \
29361 ((x) == 0x70 ? "HWRM_VNIC_RSS_COS_LB_CTX_ALLOC": \
29362 ((x) == 0x71 ? "HWRM_VNIC_RSS_COS_LB_CTX_FREE": \
29363 ((x) == 0xb1 ? "HWRM_STAT_CTX_FREE": \
29364 ((x) == 0xb0 ? "HWRM_STAT_CTX_ALLOC": \
29365 ((x) == 0xb3 ? "HWRM_STAT_CTX_CLR_STATS": \
29366 ((x) == 0xb2 ? "HWRM_STAT_CTX_QUERY": \
29367 ((x) == 0xfff6 ? "HWRM_NVM_GET_DEV_INFO": \
29368 ((x) == 0x61 ? "HWRM_RING_GRP_FREE": \
29369 ((x) == 0x60 ? "HWRM_RING_GRP_ALLOC": \
29370 ((x) == 0x24 ? "HWRM_PORT_LPBK_QSTATS": \
29371 ((x) == 0xf3 ? "HWRM_WOL_REASON_QCFG": \
29372 ((x) == 0xa0 ? "HWRM_TUNNEL_DST_PORT_QUERY": \
29373 ((x) == 0xa1 ? "HWRM_TUNNEL_DST_PORT_ALLOC": \
29374 ((x) == 0xa2 ? "HWRM_TUNNEL_DST_PORT_FREE": \
29375 ((x) == 0xfffc ? "HWRM_NVM_RAW_DUMP": \
29376 ((x) == 0xfffb ? "HWRM_NVM_GET_DIR_INFO": \
29377 ((x) == 0xfffa ? "HWRM_NVM_GET_DIR_ENTRIES": \
29378 ((x) == 0x10a ? "HWRM_CFA_VLAN_ANTISPOOF_QCFG": \
29379 ((x) == 0xe ? "HWRM_FUNC_BUF_UNRGTR": \
29380 ((x) == 0xf ? "HWRM_FUNC_VF_CFG": \
29381 ((x) == 0xffff ? "HWRM_NVM_RAW_WRITE_BLK": \
29382 ((x) == 0xfffe ? "HWRM_NVM_WRITE": \
29383 ((x) == 0xfffd ? "HWRM_NVM_READ": \
29384 ((x) == 0x50 ? "HWRM_RING_ALLOC": \
29385 ((x) == 0x51 ? "HWRM_RING_FREE": \
29386 ((x) == 0x52 ? "HWRM_RING_CMPL_RING_QAGGINT_PARAMS": \
29387 ((x) == 0x53 ? "HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS": \
29388 ((x) == 0x4a ? "HWRM_VNIC_QCAPS": \
29389 ((x) == 0x49 ? "HWRM_VNIC_PLCMODES_QCFG": \
29390 ((x) == 0x48 ? "HWRM_VNIC_PLCMODES_CFG": \
29391 ((x) == 0x47 ? "HWRM_VNIC_RSS_QCFG": \
29392 ((x) == 0x46 ? "HWRM_VNIC_RSS_CFG": \
29393 ((x) == 0x44 ? "HWRM_VNIC_TPA_CFG": \
29394 ((x) == 0x43 ? "HWRM_VNIC_QCFG": \
29395 ((x) == 0x42 ? "HWRM_VNIC_CFG": \
29396 ((x) == 0x41 ? "HWRM_VNIC_FREE": \
29397 ((x) == 0x40 ? "HWRM_VNIC_ALLOC": \
29398 ((x) == 0x0 ? "HWRM_VER_GET": \
29399 ((x) == 0xfff9 ? "HWRM_NVM_FIND_DIR_ENTRY": \
29400 ((x) == 0xfff8 ? "HWRM_NVM_MOD_DIR_ENTRY": \
29401 ((x) == 0xfff7 ? "HWRM_NVM_ERASE_DIR_ENTRY": \
29402 ((x) == 0x5e ? "HWRM_RING_RESET": \
29403 ((x) == 0xfff5 ? "HWRM_NVM_VERIFY_UPDATE": \
29404 ((x) == 0xfff4 ? "HWRM_NVM_MODIFY": \
29405 ((x) == 0xfff3 ? "HWRM_NVM_INSTALL_UPDATE": \
29406 ((x) == 0xfff2 ? "HWRM_NVM_SET_VARIABLE": \
29407 ((x) == 0xfff1 ? "HWRM_NVM_GET_VARIABLE": \
29408 ((x) == 0xfff0 ? "HWRM_NVM_FLUSH": \
29409 ((x) == 0x2e ? "HWRM_PORT_LED_QCFG": \
29410 ((x) == 0x2d ? "HWRM_PORT_LED_CFG": \
29411 ((x) == 0x2f ? "HWRM_PORT_LED_QCAPS": \
29412 ((x) == 0x2a ? "HWRM_PORT_PHY_QCAPS": \
29413 ((x) == 0x38 ? "HWRM_QUEUE_PRI2COS_CFG": \
29414 ((x) == 0x39 ? "HWRM_QUEUE_COS2BW_QCFG": \
29415 ((x) == 0x32 ? "HWRM_QUEUE_CFG": \
29416 ((x) == 0x33 ? "HWRM_FUNC_VLAN_CFG": \
29417 ((x) == 0x30 ? "HWRM_QUEUE_QPORTCFG": \
29418 ((x) == 0x31 ? "HWRM_QUEUE_QCFG": \
29419 ((x) == 0x36 ? "HWRM_QUEUE_PFCENABLE_CFG": \
29420 ((x) == 0x37 ? "HWRM_QUEUE_PRI2COS_QCFG": \
29421 ((x) == 0x34 ? "HWRM_FUNC_VLAN_QCFG": \
29422 ((x) == 0x35 ? "HWRM_QUEUE_PFCENABLE_QCFG": \
29423 ((x) == 0xff14 ? "HWRM_DBG_DUMP": \
29424 ((x) == 0xc8 ? "HWRM_FW_SET_TIME": \
29425 ((x) == 0xc9 ? "HWRM_FW_GET_TIME": \
29426 ((x) == 0xf1 ? "HWRM_WOL_FILTER_FREE": \
29427 ((x) == 0xf0 ? "HWRM_WOL_FILTER_ALLOC": \
29428 ((x) == 0x27 ? "HWRM_PORT_PHY_QCFG": \
29429 ((x) == 0xf2 ? "HWRM_WOL_FILTER_QCFG": \
29430 ((x) == 0x21 ? "HWRM_PORT_MAC_CFG": \
29431 ((x) == 0x20 ? "HWRM_PORT_PHY_CFG": \
29432 ((x) == 0x23 ? "HWRM_PORT_QSTATS": \
29433 ((x) == 0x28 ? "HWRM_PORT_MAC_QCFG": \
29434 ((x) == 0xffef ? "HWRM_NVM_VALIDATE_OPTION": \
29435 ((x) == 0x3a ? "HWRM_QUEUE_COS2BW_CFG": \
29436 "Unknown req_type"))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))
29438 /* Command numbering (8 bytes) */
29443 * This version of the specification defines the commands listed in the
29444 * table below. The following are general implementation requirements
29445 * for these commands: # All commands listed below that are marked
29446 * neither reserved nor experimental shall be implemented by the HWRM. #
29447 * A HWRM client compliant to this specification should not use commands
29448 * outside of the list below. # A HWRM client compliant to this
29449 * specification should not use command numbers marked reserved below. #
29450 * A command marked experimental below may not be implemented by the
29451 * HWRM. # A command marked experimental may change in the future
29452 * version of the HWRM specification. # A command not listed below may
29453 * be implemented by the HWRM. The behavior of commands that are not
29454 * listed below is outside the scope of this specification.
29456 #define HWRM_VER_GET (UINT32_C(0x0))
29457 #define HWRM_FUNC_BUF_UNRGTR (UINT32_C(0xe))
29458 #define HWRM_FUNC_VF_CFG (UINT32_C(0xf))
29459 /* Reserved for future use */
29460 #define RESERVED1 (UINT32_C(0x10))
29461 #define HWRM_FUNC_RESET (UINT32_C(0x11))
29462 #define HWRM_FUNC_GETFID (UINT32_C(0x12))
29463 #define HWRM_FUNC_VF_ALLOC (UINT32_C(0x13))
29464 #define HWRM_FUNC_VF_FREE (UINT32_C(0x14))
29465 #define HWRM_FUNC_QCAPS (UINT32_C(0x15))
29466 #define HWRM_FUNC_QCFG (UINT32_C(0x16))
29467 #define HWRM_FUNC_CFG (UINT32_C(0x17))
29468 #define HWRM_FUNC_QSTATS (UINT32_C(0x18))
29469 #define HWRM_FUNC_CLR_STATS (UINT32_C(0x19))
29470 #define HWRM_FUNC_DRV_UNRGTR (UINT32_C(0x1a))
29471 #define HWRM_FUNC_VF_RESC_FREE (UINT32_C(0x1b))
29472 #define HWRM_FUNC_VF_VNIC_IDS_QUERY (UINT32_C(0x1c))
29473 #define HWRM_FUNC_DRV_RGTR (UINT32_C(0x1d))
29474 #define HWRM_FUNC_DRV_QVER (UINT32_C(0x1e))
29475 #define HWRM_FUNC_BUF_RGTR (UINT32_C(0x1f))
29476 #define HWRM_PORT_PHY_CFG (UINT32_C(0x20))
29477 #define HWRM_PORT_MAC_CFG (UINT32_C(0x21))
29478 #define HWRM_PORT_QSTATS (UINT32_C(0x23))
29479 #define HWRM_PORT_LPBK_QSTATS (UINT32_C(0x24))
29480 #define HWRM_PORT_PHY_QCFG (UINT32_C(0x27))
29481 #define HWRM_PORT_MAC_QCFG (UINT32_C(0x28))
29482 #define HWRM_PORT_PHY_QCAPS (UINT32_C(0x2a))
29483 #define HWRM_PORT_LED_CFG (UINT32_C(0x2d))
29484 #define HWRM_PORT_LED_QCFG (UINT32_C(0x2e))
29485 #define HWRM_PORT_LED_QCAPS (UINT32_C(0x2f))
29486 #define HWRM_QUEUE_QPORTCFG (UINT32_C(0x30))
29487 #define HWRM_QUEUE_QCFG (UINT32_C(0x31))
29488 #define HWRM_QUEUE_CFG (UINT32_C(0x32))
29489 #define HWRM_FUNC_VLAN_CFG (UINT32_C(0x33))
29490 #define HWRM_FUNC_VLAN_QCFG (UINT32_C(0x34))
29491 #define HWRM_QUEUE_PFCENABLE_QCFG (UINT32_C(0x35))
29492 #define HWRM_QUEUE_PFCENABLE_CFG (UINT32_C(0x36))
29493 #define HWRM_QUEUE_PRI2COS_QCFG (UINT32_C(0x37))
29494 #define HWRM_QUEUE_PRI2COS_CFG (UINT32_C(0x38))
29495 #define HWRM_QUEUE_COS2BW_QCFG (UINT32_C(0x39))
29496 #define HWRM_QUEUE_COS2BW_CFG (UINT32_C(0x3a))
29497 #define HWRM_VNIC_ALLOC (UINT32_C(0x40))
29498 #define HWRM_VNIC_FREE (UINT32_C(0x41))
29499 #define HWRM_VNIC_CFG (UINT32_C(0x42))
29500 #define HWRM_VNIC_QCFG (UINT32_C(0x43))
29501 #define HWRM_VNIC_TPA_CFG (UINT32_C(0x44))
29502 #define HWRM_VNIC_RSS_CFG (UINT32_C(0x46))
29503 #define HWRM_VNIC_RSS_QCFG (UINT32_C(0x47))
29504 #define HWRM_VNIC_PLCMODES_CFG (UINT32_C(0x48))
29505 #define HWRM_VNIC_PLCMODES_QCFG (UINT32_C(0x49))
29506 #define HWRM_VNIC_QCAPS (UINT32_C(0x4a))
29507 #define HWRM_RING_ALLOC (UINT32_C(0x50))
29508 #define HWRM_RING_FREE (UINT32_C(0x51))
29509 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS (UINT32_C(0x52))
29510 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS (UINT32_C(0x53))
29511 #define HWRM_RING_RESET (UINT32_C(0x5e))
29512 #define HWRM_RING_GRP_ALLOC (UINT32_C(0x60))
29513 #define HWRM_RING_GRP_FREE (UINT32_C(0x61))
29514 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (UINT32_C(0x70))
29515 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE (UINT32_C(0x71))
29516 #define HWRM_CFA_L2_FILTER_ALLOC (UINT32_C(0x90))
29517 #define HWRM_CFA_L2_FILTER_FREE (UINT32_C(0x91))
29518 #define HWRM_CFA_L2_FILTER_CFG (UINT32_C(0x92))
29519 #define HWRM_CFA_L2_SET_RX_MASK (UINT32_C(0x93))
29520 #define HWRM_CFA_VLAN_ANTISPOOF_CFG (UINT32_C(0x94))
29521 #define HWRM_CFA_TUNNEL_FILTER_ALLOC (UINT32_C(0x95))
29522 #define HWRM_CFA_TUNNEL_FILTER_FREE (UINT32_C(0x96))
29523 #define HWRM_CFA_NTUPLE_FILTER_ALLOC (UINT32_C(0x99))
29524 #define HWRM_CFA_NTUPLE_FILTER_FREE (UINT32_C(0x9a))
29525 #define HWRM_CFA_NTUPLE_FILTER_CFG (UINT32_C(0x9b))
29526 #define HWRM_TUNNEL_DST_PORT_QUERY (UINT32_C(0xa0))
29527 #define HWRM_TUNNEL_DST_PORT_ALLOC (UINT32_C(0xa1))
29528 #define HWRM_TUNNEL_DST_PORT_FREE (UINT32_C(0xa2))
29529 #define HWRM_STAT_CTX_ALLOC (UINT32_C(0xb0))
29530 #define HWRM_STAT_CTX_FREE (UINT32_C(0xb1))
29531 #define HWRM_STAT_CTX_QUERY (UINT32_C(0xb2))
29532 #define HWRM_STAT_CTX_CLR_STATS (UINT32_C(0xb3))
29533 #define HWRM_FW_RESET (UINT32_C(0xc0))
29534 #define HWRM_FW_QSTATUS (UINT32_C(0xc1))
29535 #define HWRM_FW_SET_TIME (UINT32_C(0xc8))
29536 #define HWRM_FW_GET_TIME (UINT32_C(0xc9))
29537 #define HWRM_EXEC_FWD_RESP (UINT32_C(0xd0))
29538 #define HWRM_REJECT_FWD_RESP (UINT32_C(0xd1))
29539 #define HWRM_FWD_RESP (UINT32_C(0xd2))
29540 #define HWRM_FWD_ASYNC_EVENT_CMPL (UINT32_C(0xd3))
29541 #define HWRM_TEMP_MONITOR_QUERY (UINT32_C(0xe0))
29542 #define HWRM_WOL_FILTER_ALLOC (UINT32_C(0xf0))
29543 #define HWRM_WOL_FILTER_FREE (UINT32_C(0xf1))
29544 #define HWRM_WOL_FILTER_QCFG (UINT32_C(0xf2))
29545 #define HWRM_WOL_REASON_QCFG (UINT32_C(0xf3))
29546 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG (UINT32_C(0x10a))
29547 #define HWRM_DBG_DUMP (UINT32_C(0xff14))
29548 #define HWRM_NVM_VALIDATE_OPTION (UINT32_C(0xffef))
29549 #define HWRM_NVM_FLUSH (UINT32_C(0xfff0))
29550 #define HWRM_NVM_GET_VARIABLE (UINT32_C(0xfff1))
29551 #define HWRM_NVM_SET_VARIABLE (UINT32_C(0xfff2))
29552 #define HWRM_NVM_INSTALL_UPDATE (UINT32_C(0xfff3))
29553 #define HWRM_NVM_MODIFY (UINT32_C(0xfff4))
29554 #define HWRM_NVM_VERIFY_UPDATE (UINT32_C(0xfff5))
29555 #define HWRM_NVM_GET_DEV_INFO (UINT32_C(0xfff6))
29556 #define HWRM_NVM_ERASE_DIR_ENTRY (UINT32_C(0xfff7))
29557 #define HWRM_NVM_MOD_DIR_ENTRY (UINT32_C(0xfff8))
29558 #define HWRM_NVM_FIND_DIR_ENTRY (UINT32_C(0xfff9))
29559 #define HWRM_NVM_GET_DIR_ENTRIES (UINT32_C(0xfffa))
29560 #define HWRM_NVM_GET_DIR_INFO (UINT32_C(0xfffb))
29561 #define HWRM_NVM_RAW_DUMP (UINT32_C(0xfffc))
29562 #define HWRM_NVM_READ (UINT32_C(0xfffd))
29563 #define HWRM_NVM_WRITE (UINT32_C(0xfffe))
29564 #define HWRM_NVM_RAW_WRITE_BLK (UINT32_C(0xffff))
29565 uint16_t unused_0[3];
29566 } __attribute__((packed));
29568 #define GET_HWRM_ERROR_CODE(x) \
29569 ((x) == 0xf ? "HWRM_ERROR": \
29570 ((x) == 0xffff ? "CMD_NOT_SUPPORTED": \
29571 ((x) == 0xfffe ? "UNKNOWN_ERR": \
29572 ((x) == 0x4 ? "RESOURCE_ALLOC_ERROR": \
29573 ((x) == 0x5 ? "INVALID_FLAGS": \
29574 ((x) == 0x6 ? "INVALID_ENABLES": \
29575 ((x) == 0x0 ? "SUCCESS": \
29576 ((x) == 0x1 ? "FAIL": \
29577 ((x) == 0x2 ? "INVALID_PARAMS": \
29578 ((x) == 0x3 ? "RESOURCE_ACCESS_DENIED": \
29579 "Unknown error_code"))))))))))
29581 /* Return Codes (8 bytes) */
29584 uint16_t error_code;
29585 /* These are numbers assigned to return/error codes. */
29586 /* Request was successfully executed by the HWRM. */
29587 #define HWRM_ERR_CODE_SUCCESS (UINT32_C(0x0))
29588 /* THe HWRM failed to execute the request. */
29589 #define HWRM_ERR_CODE_FAIL (UINT32_C(0x1))
29590 /* The request contains invalid argument(s) or input parameters. */
29591 #define HWRM_ERR_CODE_INVALID_PARAMS (UINT32_C(0x2))
29593 * The requester is not allowed to access the requested
29594 * resource. This error code shall be provided in a response to
29595 * a request to query or modify an existing resource that is not
29596 * accessible by the requester.
29598 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (UINT32_C(0x3))
29600 * The HWRM is unable to allocate the requested resource. This
29601 * code only applies to requests for HWRM resource allocations.
29603 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR (UINT32_C(0x4))
29604 /* Invalid combination of flags is specified in the request. */
29605 #define HWRM_ERR_CODE_INVALID_FLAGS (UINT32_C(0x5))
29607 * Invalid combination of enables fields is specified in the
29610 #define HWRM_ERR_CODE_INVALID_ENABLES (UINT32_C(0x6))
29611 /* Generic HWRM execution error that represents an internal error. */
29612 #define HWRM_ERR_CODE_HWRM_ERROR (UINT32_C(0xf))
29613 /* Unknown error */
29614 #define HWRM_ERR_CODE_UNKNOWN_ERR (UINT32_C(0xfffe))
29615 /* Unsupported or invalid command */
29616 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED (UINT32_C(0xffff))
29617 uint16_t unused_0[3];
29618 } __attribute__((packed));
29620 /* Output (16 bytes) */
29622 struct hwrm_err_output {
29623 uint16_t error_code;
29625 * Pass/Fail or error type Note: receiver to verify the in parameters,
29626 * and fail the call with an error when appropriate
29629 /* This field returns the type of original request. */
29631 /* This field provides original sequence number of the command. */
29634 * This field is the length of the response in bytes. The last byte of
29635 * the response is a valid flag that will read as '1' when the command
29636 * has been completely written to memory.
29639 /* debug info for this error response. */
29641 /* debug info for this error response. */
29644 * In the case of an error response, command specific error code is
29645 * returned in this field.
29649 * This field is used in Output records to indicate that the output is
29650 * completely written to RAM. This field should be read as '1' to
29651 * indicate that the output has been completely written. When writing a
29652 * command completion or response to an internal processor, the order of
29653 * writes has to be such that this field is written last.
29655 } __attribute__((packed));
29657 /* Port Tx Statistics Formats (408 bytes) */
29659 struct tx_port_stats {
29660 uint64_t tx_64b_frames;
29661 /* Total Number of 64 Bytes frames transmitted */
29662 uint64_t tx_65b_127b_frames;
29663 /* Total Number of 65-127 Bytes frames transmitted */
29664 uint64_t tx_128b_255b_frames;
29665 /* Total Number of 128-255 Bytes frames transmitted */
29666 uint64_t tx_256b_511b_frames;
29667 /* Total Number of 256-511 Bytes frames transmitted */
29668 uint64_t tx_512b_1023b_frames;
29669 /* Total Number of 512-1023 Bytes frames transmitted */
29670 uint64_t tx_1024b_1518_frames;
29671 /* Total Number of 1024-1518 Bytes frames transmitted */
29672 uint64_t tx_good_vlan_frames;
29674 * Total Number of each good VLAN (exludes FCS errors) frame transmitted
29675 * which is 1519 to 1522 bytes in length inclusive (excluding framing
29676 * bits but including FCS bytes).
29678 uint64_t tx_1519b_2047_frames;
29679 /* Total Number of 1519-2047 Bytes frames transmitted */
29680 uint64_t tx_2048b_4095b_frames;
29681 /* Total Number of 2048-4095 Bytes frames transmitted */
29682 uint64_t tx_4096b_9216b_frames;
29683 /* Total Number of 4096-9216 Bytes frames transmitted */
29684 uint64_t tx_9217b_16383b_frames;
29685 /* Total Number of 9217-16383 Bytes frames transmitted */
29686 uint64_t tx_good_frames;
29687 /* Total Number of good frames transmitted */
29688 uint64_t tx_total_frames;
29689 /* Total Number of frames transmitted */
29690 uint64_t tx_ucast_frames;
29691 /* Total number of unicast frames transmitted */
29692 uint64_t tx_mcast_frames;
29693 /* Total number of multicast frames transmitted */
29694 uint64_t tx_bcast_frames;
29695 /* Total number of broadcast frames transmitted */
29696 uint64_t tx_pause_frames;
29697 /* Total number of PAUSE control frames transmitted */
29698 uint64_t tx_pfc_frames;
29699 /* Total number of PFC/per-priority PAUSE control frames transmitted */
29700 uint64_t tx_jabber_frames;
29701 /* Total number of jabber frames transmitted */
29702 uint64_t tx_fcs_err_frames;
29703 /* Total number of frames transmitted with FCS error */
29704 uint64_t tx_control_frames;
29705 /* Total number of control frames transmitted */
29706 uint64_t tx_oversz_frames;
29707 /* Total number of over-sized frames transmitted */
29708 uint64_t tx_single_dfrl_frames;
29709 /* Total number of frames with single deferral */
29710 uint64_t tx_multi_dfrl_frames;
29711 /* Total number of frames with multiple deferrals */
29712 uint64_t tx_single_coll_frames;
29713 /* Total number of frames with single collision */
29714 uint64_t tx_multi_coll_frames;
29715 /* Total number of frames with multiple collisions */
29716 uint64_t tx_late_coll_frames;
29717 /* Total number of frames with late collisions */
29718 uint64_t tx_excessive_coll_frames;
29719 /* Total number of frames with excessive collisions */
29720 uint64_t tx_frag_frames;
29721 /* Total number of fragmented frames transmitted */
29723 /* Total number of transmit errors */
29724 uint64_t tx_tagged_frames;
29725 /* Total number of single VLAN tagged frames transmitted */
29726 uint64_t tx_dbl_tagged_frames;
29727 /* Total number of double VLAN tagged frames transmitted */
29728 uint64_t tx_runt_frames;
29729 /* Total number of runt frames transmitted */
29730 uint64_t tx_fifo_underruns;
29731 /* Total number of TX FIFO under runs */
29732 uint64_t tx_pfc_ena_frames_pri0;
29733 /* Total number of PFC frames with PFC enabled bit for Pri 0 transmitted */
29734 uint64_t tx_pfc_ena_frames_pri1;
29735 /* Total number of PFC frames with PFC enabled bit for Pri 1 transmitted */
29736 uint64_t tx_pfc_ena_frames_pri2;
29737 /* Total number of PFC frames with PFC enabled bit for Pri 2 transmitted */
29738 uint64_t tx_pfc_ena_frames_pri3;
29739 /* Total number of PFC frames with PFC enabled bit for Pri 3 transmitted */
29740 uint64_t tx_pfc_ena_frames_pri4;
29741 /* Total number of PFC frames with PFC enabled bit for Pri 4 transmitted */
29742 uint64_t tx_pfc_ena_frames_pri5;
29743 /* Total number of PFC frames with PFC enabled bit for Pri 5 transmitted */
29744 uint64_t tx_pfc_ena_frames_pri6;
29745 /* Total number of PFC frames with PFC enabled bit for Pri 6 transmitted */
29746 uint64_t tx_pfc_ena_frames_pri7;
29747 /* Total number of PFC frames with PFC enabled bit for Pri 7 transmitted */
29748 uint64_t tx_eee_lpi_events;
29749 /* Total number of EEE LPI Events on TX */
29750 uint64_t tx_eee_lpi_duration;
29751 /* EEE LPI Duration Counter on TX */
29752 uint64_t tx_llfc_logical_msgs;
29753 /* Total number of Link Level Flow Control (LLFC) messages transmitted */
29754 uint64_t tx_hcfc_msgs;
29755 /* Total number of HCFC messages transmitted */
29756 uint64_t tx_total_collisions;
29757 /* Total number of TX collisions */
29759 /* Total number of transmitted bytes */
29760 uint64_t tx_xthol_frames;
29761 /* Total number of end-to-end HOL frames */
29762 uint64_t tx_stat_discard;
29763 /* Total Tx Drops per Port reported by STATS block */
29764 uint64_t tx_stat_error;
29765 /* Total Tx Error Drops per Port reported by STATS block */
29766 } __attribute__((packed));
29768 /* Port Rx Statistics Formats (528 bytes) */
29770 struct rx_port_stats {
29771 uint64_t rx_64b_frames;
29772 /* Total Number of 64 Bytes frames received */
29773 uint64_t rx_65b_127b_frames;
29774 /* Total Number of 65-127 Bytes frames received */
29775 uint64_t rx_128b_255b_frames;
29776 /* Total Number of 128-255 Bytes frames received */
29777 uint64_t rx_256b_511b_frames;
29778 /* Total Number of 256-511 Bytes frames received */
29779 uint64_t rx_512b_1023b_frames;
29780 /* Total Number of 512-1023 Bytes frames received */
29781 uint64_t rx_1024b_1518_frames;
29782 /* Total Number of 1024-1518 Bytes frames received */
29783 uint64_t rx_good_vlan_frames;
29785 * Total Number of each good VLAN (exludes FCS errors) frame received
29786 * which is 1519 to 1522 bytes in length inclusive (excluding framing
29787 * bits but including FCS bytes).
29789 uint64_t rx_1519b_2047b_frames;
29790 /* Total Number of 1519-2047 Bytes frames received */
29791 uint64_t rx_2048b_4095b_frames;
29792 /* Total Number of 2048-4095 Bytes frames received */
29793 uint64_t rx_4096b_9216b_frames;
29794 /* Total Number of 4096-9216 Bytes frames received */
29795 uint64_t rx_9217b_16383b_frames;
29796 /* Total Number of 9217-16383 Bytes frames received */
29797 uint64_t rx_total_frames;
29798 /* Total number of frames received */
29799 uint64_t rx_ucast_frames;
29800 /* Total number of unicast frames received */
29801 uint64_t rx_mcast_frames;
29802 /* Total number of multicast frames received */
29803 uint64_t rx_bcast_frames;
29804 /* Total number of broadcast frames received */
29805 uint64_t rx_fcs_err_frames;
29806 /* Total number of received frames with FCS error */
29807 uint64_t rx_ctrl_frames;
29808 /* Total number of control frames received */
29809 uint64_t rx_pause_frames;
29810 /* Total number of PAUSE frames received */
29811 uint64_t rx_pfc_frames;
29812 /* Total number of PFC frames received */
29813 uint64_t rx_unsupported_opcode_frames;
29814 /* Total number of frames received with an unsupported opcode */
29815 uint64_t rx_unsupported_da_pausepfc_frames;
29817 * Total number of frames received with an unsupported DA for pause and
29820 uint64_t rx_wrong_sa_frames;
29821 /* Total number of frames received with an unsupported SA */
29822 uint64_t rx_align_err_frames;
29823 /* Total number of received packets with alignment error */
29824 uint64_t rx_oor_len_frames;
29825 /* Total number of received frames with out-of-range length */
29826 uint64_t rx_code_err_frames;
29827 /* Total number of received frames with error termination */
29828 uint64_t rx_false_carrier_frames;
29830 * Total number of received frames with a false carrier is detected
29831 * during idle, as defined by RX_ER samples active and RXD is 0xE. The
29832 * event is reported along with the statistics generated on the next
29833 * received frame. Only one false carrier condition can be detected and
29834 * logged between frames. Carrier event, valid for 10M/100M speed modes
29837 uint64_t rx_ovrsz_frames;
29838 /* Total number of over-sized frames received */
29839 uint64_t rx_jbr_frames;
29840 /* Total number of jabber packets received */
29841 uint64_t rx_mtu_err_frames;
29842 /* Total number of received frames with MTU error */
29843 uint64_t rx_match_crc_frames;
29844 /* Total number of received frames with CRC match */
29845 uint64_t rx_promiscuous_frames;
29846 /* Total number of frames received promiscuously */
29847 uint64_t rx_tagged_frames;
29848 /* Total number of received frames with one or two VLAN tags */
29849 uint64_t rx_double_tagged_frames;
29850 /* Total number of received frames with two VLAN tags */
29851 uint64_t rx_trunc_frames;
29852 /* Total number of truncated frames received */
29853 uint64_t rx_good_frames;
29854 /* Total number of good frames (without errors) received */
29855 uint64_t rx_pfc_xon2xoff_frames_pri0;
29857 * Total number of received PFC frames with transition from XON to XOFF
29860 uint64_t rx_pfc_xon2xoff_frames_pri1;
29862 * Total number of received PFC frames with transition from XON to XOFF
29865 uint64_t rx_pfc_xon2xoff_frames_pri2;
29867 * Total number of received PFC frames with transition from XON to XOFF
29870 uint64_t rx_pfc_xon2xoff_frames_pri3;
29872 * Total number of received PFC frames with transition from XON to XOFF
29875 uint64_t rx_pfc_xon2xoff_frames_pri4;
29877 * Total number of received PFC frames with transition from XON to XOFF
29880 uint64_t rx_pfc_xon2xoff_frames_pri5;
29882 * Total number of received PFC frames with transition from XON to XOFF
29885 uint64_t rx_pfc_xon2xoff_frames_pri6;
29887 * Total number of received PFC frames with transition from XON to XOFF
29890 uint64_t rx_pfc_xon2xoff_frames_pri7;
29892 * Total number of received PFC frames with transition from XON to XOFF
29895 uint64_t rx_pfc_ena_frames_pri0;
29896 /* Total number of received PFC frames with PFC enabled bit for Pri 0 */
29897 uint64_t rx_pfc_ena_frames_pri1;
29898 /* Total number of received PFC frames with PFC enabled bit for Pri 1 */
29899 uint64_t rx_pfc_ena_frames_pri2;
29900 /* Total number of received PFC frames with PFC enabled bit for Pri 2 */
29901 uint64_t rx_pfc_ena_frames_pri3;
29902 /* Total number of received PFC frames with PFC enabled bit for Pri 3 */
29903 uint64_t rx_pfc_ena_frames_pri4;
29904 /* Total number of received PFC frames with PFC enabled bit for Pri 4 */
29905 uint64_t rx_pfc_ena_frames_pri5;
29906 /* Total number of received PFC frames with PFC enabled bit for Pri 5 */
29907 uint64_t rx_pfc_ena_frames_pri6;
29908 /* Total number of received PFC frames with PFC enabled bit for Pri 6 */
29909 uint64_t rx_pfc_ena_frames_pri7;
29910 /* Total number of received PFC frames with PFC enabled bit for Pri 7 */
29911 uint64_t rx_sch_crc_err_frames;
29912 /* Total Number of frames received with SCH CRC error */
29913 uint64_t rx_undrsz_frames;
29914 /* Total Number of under-sized frames received */
29915 uint64_t rx_frag_frames;
29916 /* Total Number of fragmented frames received */
29917 uint64_t rx_eee_lpi_events;
29918 /* Total number of RX EEE LPI Events */
29919 uint64_t rx_eee_lpi_duration;
29920 /* EEE LPI Duration Counter on RX */
29921 uint64_t rx_llfc_physical_msgs;
29923 * Total number of physical type Link Level Flow Control (LLFC) messages
29926 uint64_t rx_llfc_logical_msgs;
29928 * Total number of logical type Link Level Flow Control (LLFC) messages
29931 uint64_t rx_llfc_msgs_with_crc_err;
29933 * Total number of logical type Link Level Flow Control (LLFC) messages
29934 * received with CRC error
29936 uint64_t rx_hcfc_msgs;
29937 /* Total number of HCFC messages received */
29938 uint64_t rx_hcfc_msgs_with_crc_err;
29939 /* Total number of HCFC messages received with CRC error */
29941 /* Total number of received bytes */
29942 uint64_t rx_runt_bytes;
29943 /* Total number of bytes received in runt frames */
29944 uint64_t rx_runt_frames;
29945 /* Total number of runt frames received */
29946 uint64_t rx_stat_discard;
29947 /* Total Rx Discards per Port reported by STATS block */
29948 uint64_t rx_stat_err;
29949 /* Total Rx Error Drops per Port reported by STATS block */
29950 } __attribute__((packed));
29952 /* Periodic Statistics Context DMA to host (160 bytes) */
29954 struct ctx_hw_stats {
29955 uint64_t rx_ucast_pkts;
29956 /* Number of received unicast packets */
29957 uint64_t rx_mcast_pkts;
29958 /* Number of received multicast packets */
29959 uint64_t rx_bcast_pkts;
29960 /* Number of received broadcast packets */
29961 uint64_t rx_discard_pkts;
29962 /* Number of discarded packets on received path */
29963 uint64_t rx_drop_pkts;
29964 /* Number of dropped packets on received path */
29965 uint64_t rx_ucast_bytes;
29966 /* Number of received bytes for unicast traffic */
29967 uint64_t rx_mcast_bytes;
29968 /* Number of received bytes for multicast traffic */
29969 uint64_t rx_bcast_bytes;
29970 /* Number of received bytes for broadcast traffic */
29971 uint64_t tx_ucast_pkts;
29972 /* Number of transmitted unicast packets */
29973 uint64_t tx_mcast_pkts;
29974 /* Number of transmitted multicast packets */
29975 uint64_t tx_bcast_pkts;
29976 /* Number of transmitted broadcast packets */
29977 uint64_t tx_discard_pkts;
29978 /* Number of discarded packets on transmit path */
29979 uint64_t tx_drop_pkts;
29980 /* Number of dropped packets on transmit path */
29981 uint64_t tx_ucast_bytes;
29982 /* Number of transmitted bytes for unicast traffic */
29983 uint64_t tx_mcast_bytes;
29984 /* Number of transmitted bytes for multicast traffic */
29985 uint64_t tx_bcast_bytes;
29986 /* Number of transmitted bytes for broadcast traffic */
29988 /* Number of TPA packets */
29989 uint64_t tpa_bytes;
29990 /* Number of TPA bytes */
29991 uint64_t tpa_events;
29992 /* Number of TPA events */
29993 uint64_t tpa_aborts;
29994 /* Number of TPA aborts */
29995 } __attribute__((packed));
29997 /* Structure data header (16 bytes) */
29999 struct hwrm_struct_hdr {
30000 uint16_t struct_id;
30001 /* This value indicates the structured data ID. */
30002 /* LLDP configuration structured data ID. */
30003 #define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_CFG UINT32_C(0x41b)
30004 /* DCBX ETS configuration structured data ID. */
30005 #define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_ETS UINT32_C(0x41d)
30006 /* DCBX PFC configuration structured data ID. */
30007 #define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_PFC UINT32_C(0x41f)
30008 /* DCBX APP configuration structured data ID. */
30009 #define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_APP UINT32_C(0x421)
30011 * DCBX state configuration structured data ID for all DCBX
30014 #define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE UINT32_C(0x422)
30016 * LLDP generic structured data ID. This is used with
30017 * GET_STRUCTURED_DATA only.
30019 #define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_GENERIC UINT32_C(0x424)
30021 * LLDP device structured data ID. This is used with
30022 * GET_STRUCTURED_DATA only.
30024 #define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_DEVICE UINT32_C(0x426)
30025 /* reserved for AFM usage. */
30026 #define HWRM_STRUCT_HDR_STRUCT_ID_AFM_OPAQUE UINT32_C(0x1)
30027 /* Port description. */
30028 #define HWRM_STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION UINT32_C(0xa)
30029 /* RSSv2 Configuration. */
30030 #define HWRM_STRUCT_HDR_STRUCT_ID_RSS_V2 UINT32_C(0x64)
30032 /* This value indicates the length of structured data. */
30034 /* This value indicates the version of structured data. */
30036 /* This value indicates the number of structured data elements. */
30038 /* This value indicates the subtype. */
30039 uint16_t next_offset;
30041 * This value indicates the count of 64-bit values that point to the
30042 * next header. A value of 0 means that this is the last element. The
30043 * value is a count of 64-bit words from the beginning of the current
30046 /* This value indicates this is the last element */
30047 #define HWRM_STRUCT_HDR_NEXT_OFFSET_LAST UINT32_C(0x0)
30048 uint16_t unused_0[3];
30049 } __attribute__((packed));
30051 /* DCBX ETS configuration structure (1053) (32 bytes) */
30053 struct hwrm_struct_data_dcbx_ets {
30054 uint8_t destination;
30056 * This field indicates if this configuration is ETS recommendation or
30057 * ETS configuration. A value 1 means it is ETS configuration, A value
30058 * of 2 means it is a ETS recommendation.
30060 /* ETS configuration */
30061 #define HWRM_STRUCT_DATA_DCBX_ETS_DESTINATION_CONFIGURATION UINT32_C(0x1)
30062 /* ETS recommendation */
30063 #define HWRM_STRUCT_DATA_DCBX_ETS_DESTINATION_RECOMMMENDATION UINT32_C(0x2)
30065 /* This value indicates maximum ETS TCs supported. */
30068 uint8_t pri0_to_tc_map;
30069 /* ETS priority 0 to TC map. */
30070 uint8_t pri1_to_tc_map;
30071 /* ETS priority 1 to TC map. */
30072 uint8_t pri2_to_tc_map;
30073 /* ETS priority 2 to TC map. */
30074 uint8_t pri3_to_tc_map;
30075 /* ETS priority 3 to TC map. */
30076 uint8_t pri4_to_tc_map;
30077 /* ETS priority 4 to TC map. */
30078 uint8_t pri5_to_tc_map;
30079 /* ETS priority 5 to TC map. */
30080 uint8_t pri6_to_tc_map;
30081 /* ETS priority 6 to TC map. */
30082 uint8_t pri7_to_tc_map;
30083 /* ETS priority 7 to TC map. */
30084 uint8_t tc0_to_bw_map;
30085 /* ETS TC 0 to bandwidth map. */
30086 uint8_t tc1_to_bw_map;
30087 /* ETS TC 1 to bandwidth map. */
30088 uint8_t tc2_to_bw_map;
30089 /* ETS TC 2 to bandwidth map. */
30090 uint8_t tc3_to_bw_map;
30091 /* ETS TC 3 to bandwidth map. */
30092 uint8_t tc4_to_bw_map;
30093 /* ETS TC 4 to bandwidth map. */
30094 uint8_t tc5_to_bw_map;
30095 /* ETS TC 5 to bandwidth map. */
30096 uint8_t tc6_to_bw_map;
30097 /* ETS TC 6 to bandwidth map. */
30098 uint8_t tc7_to_bw_map;
30099 /* ETS TC 7 to bandwidth map. */
30100 uint8_t tc0_to_tsa_map;
30101 /* ETS TC 0 to TSA map. */
30102 /* strict priority */
30103 #define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_SP UINT32_C(0x0)
30104 /* credit based shaper */
30105 #define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_CBS UINT32_C(0x1)
30107 #define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_ETS UINT32_C(0x2)
30108 /* vendor specific */
30109 #define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_VENDOR_SPECIFIC UINT32_C(0xff)
30110 uint8_t tc1_to_tsa_map;
30111 /* ETS TC 1 to TSA map. */
30112 uint8_t tc2_to_tsa_map;
30113 /* ETS TC 2 to TSA map. */
30114 uint8_t tc3_to_tsa_map;
30115 /* ETS TC 3 to TSA map. */
30116 uint8_t tc4_to_tsa_map;
30117 /* ETS TC 4 to TSA map. */
30118 uint8_t tc5_to_tsa_map;
30119 /* ETS TC 5 to TSA map. */
30120 uint8_t tc6_to_tsa_map;
30121 /* ETS TC 6 to TSA map. */
30122 uint8_t tc7_to_tsa_map;
30123 /* ETS TC 7 to TSA map. */
30125 } __attribute__((packed));
30127 /* DCBX PFC configuration structure (1055) (8 bytes) */
30129 struct hwrm_struct_data_dcbx_pfc {
30130 uint8_t pfc_priority_bitmap;
30132 * This field indicates PFC priority bit map. A value of '0' indicates
30133 * PFC is disabled. A value of '1' indicates PFC is enabled on that
30136 uint8_t max_pfc_tcs;
30138 * This field indicates max PFC TCs supported. Each PFC TC will map to a
30139 * lossless CoS queue.
30143 * This field indicates if MACSec bypass capability is enabled. A value
30144 * of '1' indicates MBC is enabled. A value of '0' indicates MBC is
30147 uint8_t unused_0[5];
30148 } __attribute__((packed));
30150 /* DCBX Application configuration structure (1057) (8 bytes) */
30152 struct hwrm_struct_data_dcbx_app {
30153 uint16_t protocol_id; /* big endian */
30155 * This field indicates the protocol identifier. This should be
30156 * specified in big endian format.
30158 uint8_t protocol_selector;
30160 * This field indicates the protocol selector. The valid values are
30164 #define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE UINT32_C(0x1)
30166 #define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT UINT32_C(0x2)
30168 #define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT UINT32_C(0x3)
30169 /* TCP & UDP port */
30170 #define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT UINT32_C(0x4)
30172 /* This field indicates application priority. */
30174 /* This field indicates this entry is valid. */
30175 uint8_t unused_0[3];
30176 } __attribute__((packed));
30178 /* DCBX feature states configuration structure (1058) (8 bytes) */
30180 struct hwrm_struct_data_dcbx_feature_state {
30182 /* DCBX mode - IEEE or CEE. This is read only field. */
30183 /* DCBX disabled mode. */
30184 #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_DISABLED UINT32_C(0x0)
30185 /* DCBX IEEE mode. */
30186 #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_IEEE UINT32_C(0x1)
30187 /* DCBX CEE mode. */
30188 #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_CEE UINT32_C(0x2)
30190 /* ETS TLV state. */
30192 /* PFC TLV state. */
30194 /* App TLV state. */
30195 /* Feature enable bit position. */
30196 #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ENABLE_BIT_POS UINT32_C(0x7)
30197 /* Feature willing bit position. */
30198 #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_WILLING_BIT_POS UINT32_C(0x6)
30199 /* Feature advertise bit position. */
30200 #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ADVERTISE_BIT_POS UINT32_C(0x5)
30201 uint8_t unused_0[3];
30205 * This field is used to reset the DCBX configuration to factory
30208 /* reset ETS configuration. */
30209 #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_ETS UINT32_C(0x1)
30210 /* reset PFC configuration. */
30211 #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_PFC UINT32_C(0x2)
30212 /* reset application configuration. */
30213 #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_APP UINT32_C(0x4)
30214 /* reset DCBX state configuration. */
30215 #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_STATE UINT32_C(0x8)
30216 } __attribute__((packed));
30218 /* LLDP TLVs transmit configuration structure (1051) (8 bytes) */
30220 struct hwrm_struct_data_lldp {
30221 uint8_t admin_state;
30222 /* Port admin state */
30223 /* Disable both Tx and Rx */
30224 #define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_DISABLE UINT32_C(0x0)
30225 /* Enable Tx only */
30226 #define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_TX UINT32_C(0x1)
30227 /* Enable Rx only */
30228 #define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_RX UINT32_C(0x2)
30229 /* Enable both Tx and Rx */
30230 #define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_ENABLE UINT32_C(0x3)
30231 uint8_t port_description_state;
30232 /* Port desciption TLV transmit state (enable(1)/disable(0)). */
30234 #define HWRM_STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_DISABLE UINT32_C(0x0)
30236 #define HWRM_STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_ENABLE UINT32_C(0x1)
30237 uint8_t system_name_state;
30238 /* System name TLV transmit state (enable(1)/disable(0)). */
30240 #define HWRM_STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_DISABLE UINT32_C(0x0)
30242 #define HWRM_STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_ENABLE UINT32_C(0x1)
30243 uint8_t system_desc_state;
30244 /* System desciption TLV transmit state (enable(1)/disable(0)). */
30246 #define HWRM_STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_DISABLE UINT32_C(0x0)
30248 #define HWRM_STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_ENABLE UINT32_C(0x1)
30249 uint8_t system_cap_state;
30250 /* System capabilities TLV transmit state (enable(1)/disable(0)). */
30252 #define HWRM_STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_DISABLE UINT32_C(0x0)
30254 #define HWRM_STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_ENABLE UINT32_C(0x1)
30255 uint8_t mgmt_addr_state;
30256 /* Management address TLV transmit state (enable(1)/disable(0)). */
30258 #define HWRM_STRUCT_DATA_LLDP_MGMT_ADDR_STATE_DISABLE UINT32_C(0x0)
30260 #define HWRM_STRUCT_DATA_LLDP_MGMT_ADDR_STATE_ENABLE UINT32_C(0x1)
30261 uint8_t async_event_notification_state;
30262 /* Async event notification state (enable(1)/disable(0)). */
30264 #define HWRM_STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_DISABLE UINT32_C(0x0)
30266 #define HWRM_STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_ENABLE UINT32_C(0x1)
30268 } __attribute__((packed));
30270 /* LLDP generic TLV configuration (1060) (16 bytes) */
30272 struct hwrm_struct_data_lldp_generic {
30275 /* Chassis ID TLV */
30276 #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_CHASSIS UINT32_C(0x1)
30278 #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT UINT32_C(0x2)
30279 /* System name TLV */
30280 #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_SYSTEM_NAME UINT32_C(0x3)
30281 /* System description TLV */
30282 #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_SYSTEM_DESCRIPTION UINT32_C(0x4)
30283 /* Port name TLV */
30284 #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_NAME UINT32_C(0x5)
30285 /* Port description TLV */
30286 #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_DESCRIPTION UINT32_C(0x6)
30288 /* TLV sub-type. */
30294 uint32_t tlv_value[64];
30296 } __attribute__((packed));
30298 /* LLDP device TLV configuration (1062) (64 bytes) */
30300 struct hwrm_struct_data_lldp_device {
30302 /* Time to Live. */
30303 uint8_t mgmt_addr_len;
30304 /* Management address length. */
30305 uint8_t mgmt_addr_type;
30306 /* Management address type. */
30308 uint32_t mgmt_addr[8];
30309 /* Management address. */
30310 uint32_t system_caps;
30311 /* System capabilities. */
30312 uint8_t intf_num_type;
30313 /* Interface number type. */
30314 uint8_t mgmt_addr_oid_length;
30315 /* Management address OID length. */
30319 /* Interface number. */
30321 uint32_t mgmt_addr_oid[32];
30322 /* Management address OID. */
30323 } __attribute__((packed));
30325 /* port description (10) (8 bytes) */
30327 struct hwrm_struct_data_port_description {
30330 * Port #. Port number starts at 0 and anything greater than number of
30331 * ports minus 1 is an error.
30333 uint8_t unused_0[7];
30334 } __attribute__((packed));
30336 /* RSSv2 Configuration (100) (16 bytes) */
30338 struct hwrm_struct_data_rss_v2 {
30340 /* When this bit is '1', the hash type and hash key are included. */
30341 #define HWRM_STRUCT_DATA_RSS_V2_FLAGS_HASH_VALID UINT32_C(0x1)
30342 uint16_t rss_ctx_id;
30343 /* RSS Context index. */
30344 uint16_t num_ring_groups;
30345 /* Number ring group IDs. */
30346 uint16_t hash_type;
30348 * When this bit is '1', the RSS hash shall be computed over source and
30349 * destination IPv4 addresses of IPv4 packets.
30351 #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_IPV4 UINT32_C(0x1)
30353 * When this bit is '1', the RSS hash shall be computed over
30354 * source/destination IPv4 addresses and source/destination ports of
30355 * TCP/IPv4 packets.
30357 #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
30359 * When this bit is '1', the RSS hash shall be computed over
30360 * source/destination IPv4 addresses and source/destination ports of
30361 * UDP/IPv4 packets.
30363 #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
30365 * When this bit is '1', the RSS hash shall be computed over source and
30366 * destination IPv4 addresses of IPv6 packets.
30368 #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_IPV6 UINT32_C(0x8)
30370 * When this bit is '1', the RSS hash shall be computed over
30371 * source/destination IPv6 addresses and source/destination ports of
30372 * TCP/IPv6 packets.
30374 #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
30376 * When this bit is '1', the RSS hash shall be computed over
30377 * source/destination IPv6 addresses and source/destination ports of
30378 * UDP/IPv6 packets.
30380 #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
30381 uint64_t hash_key_ring_group_ids;
30382 /* Variable size data. Hash key (optional) followed by ring_group_ids. */
30383 } __attribute__((packed));
30385 #endif /* _HSI_STRUCT_DEF_EXTERNAL_H_ */